task_id string | shuttle_name string | project_name string | task_name string | system_message string | prompt string | golden_module string |
|---|---|---|---|---|---|---|
ttsky26b_0001 | ttsky26b | 5iri-tt-riscv-cpu | task_vga_sync | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_systolic_vga.v" 1
// Tiny Tapeout top: 8x8 ternary systolic-array demo rendered directly to VGA.
//
// The logical matrix is 8x8, but it is computed in two passes using a 4x8
// systolic slice so the hardware only contains 32 live PEs.
// ui_in[1:0] select one of four tiny matrix demos.
// VGA shows the ... | module vga_sync (
input wire clk,
input wire rst,
output reg hsync,
output reg vsync,
output wire active,
output wire [ 9:0] px, // pixel x (0..639 in active region)
output wire [ 8:0] py, // pixel y (0..479 in active region)
outpu... |
ttsky26b_0002 | ttsky26b | 5iri-tt-riscv-gpu | task_spi_slave | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_riscv_gpu.v" 1
`timescale 1ns/1ps
`default_nettype none
// TinyTapeout top wrapper for BitNet b1.58-style 4x4 matrix multiply accelerator (W1.58A8).
// Weights (B) are ternary {-1, 0, +1}; activations (A) are uint8. No multipliers needed.
//
// Pin map:
// ui_in[0] = SPI SCLK
// ui_in[1] = SPI CS_... | module spi_slave (
input wire clk, // system clock (must be >> spi_sclk)
input wire rst,
// SPI pins
input wire spi_sclk,
input wire spi_cs_n,
input wire spi_mosi,
output reg spi_miso,
// Register interface
output reg c... |
ttihp26a_0003 | ttihp26a | ADDTDR-tt-pwm-controller | task_PWM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_pwm_controller_atudoroi (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module PWM (
input clk,
input [7:0] PWM_in,
output PWM_out
);
reg [8:0] PWM_accumulator;
initial
PWM_accumulator = 0;
always @(posedge clk) begin
PWM_accumulator <= PWM_accumulator[7:0] + PWM_in;
end
assign PWM_out = PWM_accumulator[8];
endmodule |
ttihp26a_0004 | ttihp26a | ADDTDR-tt-pwm-controller | task_main | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_pwm_controller_atudoroi (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module main(
input CLK_i,
output D1,
output D2,
output D3,
output D4,
output D5,
output D6,
output D7,
output D8,
output TX_TO_FTDI,
input RX_FROM_FTDI
);
wire tx_busy;
wire RxD_data_ready;
wire [7:0] RxD_data;
reg [7:0] GPout;
reg [3:0] mem_address = 4'h0;
reg [7:0] mem [0:8];
... |
ttihp26a_0005 | ttihp26a | ADDTDR-tt-pwm-controller | task_uart_transmitter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_pwm_controller_atudoroi (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module uart_transmitter (
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
parameter ClkFrequency = 12000000; // 12MHz
parameter Baud = 115200;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incom... |
ttsky25b_0006 | ttsky25b | AG2048-tiny-calculator-asic | task_button_reader | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2025 Andy Gong
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_ag2048_tiny_calculator (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module button_reader (
input logic clk,
input logic rst_n,
output logic [3:0] o_word_lines,
input logic [3:0] i_bit_lines,
input logic i_ac_pin,
input logic i_add_pin,
input logic i_sub_pin,
input logic i_mul_pin,
input logic i_div_... |
ttsky26a_0007 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_alu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module alu (
//input data
input wire [15:0] x,
input wire [15:0] y,
//control bits (can potentially code 128 different calculations)
input wire zx,
input wire nx,
input wire zy,
input wire ny,
input wire f,
input wire no,
//
output wire zr,
output wire ng,
//ou... |
ttsky26a_0008 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_computer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module computer (
input reset,
input clk,
//GPIO
input [7:0] gp_inputs, // Dedicated inputs
output [7:0] gp_outputs, // Dedicated outputs
//UI GPIO
output [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input [7:0] uio_in, // IOs: Input path
output [7:0] uio_... |
ttsky26a_0009 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_cpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module cpu (
//from data memory
input [15:0] inM, //RAM[A]
//from instruction memory
input [15:0] instruction, //cccccccccccccccc
//instuction[15] -> 0 -> A-instruction -> load into A register
//instruction[15] -> 1 -> C-instuction -> it's a control capsule -> 1xxaccccccdddjjj
//1xxaccccccd... |
ttsky26a_0010 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_gpio | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module gpio (
input clk,
input reset,
//being driven outside the chip
input [7:0] input_signals, //Read-only
output [7:0] output_signals,
input load,
input [7:0] data_in,
output [15:0] out
);
reg [7:0] outputs_reg;
always @(posedge clk or posedge reset) begin
... |
ttsky26a_0011 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_memory_router | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module memory_router(
input clk,
input reset,
// CPU addresses
input [13:0] ram_address,
input [13:0] rom_address,
// RAM write interface
input [15:0] ram_data_in,
input ram_write,
// Data returned to CPU
output [15:0] ram_data_out,
output [15:0] rom_data_out,
// Sign... |
ttsky26a_0012 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_pc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module pc (
input load,
input inc,
input reset,
input clk,
input [13:0] in,
output reg [13:0] out
);
always @(posedge clk or posedge reset) begin
if(reset) begin
out <= 14'b0;
end else if(load) begin
out <= in;
end else if(inc) begin
... |
ttsky26a_0013 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_register_16 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module register_16(
input [15:0] in,
input load,
input clk,
input reset,
output reg [15:0]out
);
always @(posedge clk or posedge reset) begin
if (reset) begin
out <= 16'b0;
end else if(load) begin
out <= in;
end
end
endmodule |
ttsky26a_0014 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_spi_memory | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module spi_memory (
input clk,
input reset,
input ram_enabled, //0 -> only read ROM, 1 -> read both ROM and RAM
// CPU addresses (WORD addresses)
input [13:0] ram_address,
input [13:0] rom_address,
// RAM write interface
input [15:0] ram_data_in,
input ram_write,
// Data retu... |
ttsky26a_0015 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_uio | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Acrazt05_titan_proccesing_unit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input... | module uio (
input clk,
input reset,
input [15:0] in,
input [7:0] uio_input,
input load,
output [15:0] out
);
reg [15:0] internal_reg;
always @(posedge clk or posedge reset) begin
if (reset) begin
internal_reg <= 16'b0;
end
else begin... |
ttsky26b_0016 | ttsky26b | AdvaittejPS-vspace-snn-afib-detector | task_readout | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snn_afib_detector.v" 1
`default_nettype none
module tt_um_snn_afib_detector (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire ... | module readout (
input wire clk,
input wire rst_n,
input wire ena,
input wire w_load,
input wire w_data,
input wire w_clk,
input wire [7:0] neuron_spikes,
input wire spike_valid,
output reg afib_flag,
output reg... |
ttsky26b_0017 | ttsky26b | AdvaittejPS-vspace-snn-afib-detector | task_reservoir | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snn_afib_detector.v" 1
`default_nettype none
module tt_um_snn_afib_detector (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire ... | module reservoir (
input wire clk,
input wire rst_n,
input wire ena,
input wire [3:0] spike_interval,
input wire [3:0] spike_delta,
input wire spike_valid,
output wire [7:0] neuron_spikes,
output wire any_spike
);
wire [3:0] gi = spike_v... |
ttsky26b_0018 | ttsky26b | AdvaittejPS-vspace-snn-afib-detector | task_rr_features | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snn_afib_detector.v" 1
`default_nettype none
module tt_um_snn_afib_detector (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire ... | module rr_features (
input wire clk,
input wire rst_n,
input wire ena,
input wire r_peak,
output reg [5:0] rr_interval,
output reg [5:0] rr_delta,
output reg rr_valid,
output reg asystole_flag
);
reg [15:0] tick_count;
reg [5:0] rr_... |
ttsky26b_0019 | ttsky26b | AdvaittejPS-vspace-snn-afib-detector | task_spike_encoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snn_afib_detector.v" 1
`default_nettype none
module tt_um_snn_afib_detector (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire ... | module spike_encoder (
input wire clk,
input wire rst_n,
input wire ena,
input wire [5:0] rr_interval,
input wire [5:0] rr_delta,
input wire rr_valid,
output reg [3:0] spike_interval,
output reg [3:0] spike_delta,
output reg spike_valid
);
w... |
ttsky26b_0020 | ttsky26b | AhmedMustakim-777-tt-riscv-alu | task_riscv_alu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_riscv_alu.v" 1
`default_nettype none
// TinyTapeout wrapper for rv32i RISC-V ALU
// UCF EEE-5390C Full Custom VLSI Design
//
// Protocol:
// Load A: ui_in[7]=1, ui_in[6:5]=byte_sel(0-3),
// ui_in[4:1]=ALU_op (on byte 0 only)
// uio_in[7:0]=data byte
//
// Load B: ui_in[7]=0, ui... | module riscv_alu
(
// Inputs
input [ 3:0] alu_op_i
,input [ 31:0] alu_a_i
,input [ 31:0] alu_b_i
// Outputs
,output [ 31:0] alu_p_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
... |
ttsky26b_0021 | ttsky26b | Akul18-ttsky-verilog-template | task_button_sync_onepulse | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_flappy_vga_Akul18 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire ... | module button_sync_onepulse (
input logic clk,
input logic reset,
input logic btn_in,
output logic btn_pulse
);
logic sync0, sync1, sync1_d;
always_ff @(posedge clk or posedge reset) begin
if (reset) begin
sync0 <= 1'b0;
sync1 <= 1'b0;
sync1_... |
ttsky26b_0022 | ttsky26b | Akul18-ttsky-verilog-template | task_flappy_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_flappy_vga_Akul18 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire ... | module flappy_top (
input logic CLOCK_50,
input logic reset,
input logic btn_start,
input logic btn_jump,
output logic HS,
output logic VS,
output logic blank,
output logic [2:0] r,
output logic [2:0] g,
output logic [2:0] b
);
... |
ttsky26b_0023 | ttsky26b | Akul18-ttsky-verilog-template | task_game_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_flappy_vga_Akul18 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire ... | module game_fsm (
input logic clk,
input logic reset,
input logic tick,
input logic start_pulse,
input logic collision,
output logic game_active,
output logic clear_game,
output logic [1:0] state
);
typedef enum logic [1:0] {
IDL... |
ttsky26b_0024 | ttsky26b | Akul18-ttsky-verilog-template | task_vga | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_flappy_vga_Akul18 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire ... | module vga (
output logic [9:0] row, col,
output logic HS, VS, blank,
input logic CLOCK_50, reset
);
logic [9:0] col_count;
logic [9:0] row_count;
simple_counter #(10) col_counter (
.Q (col_count),
.en (1'b1),
.clr (col_count >= 10'd799),
.... |
ttgf26b_0025 | ttgf26b | Alanduan21-ttgf-triad01 | task_triad01_arbitration_engine | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Duan Yihe
* SPDX-License-Identifier: Apache-2.0
* project.v — TRIAD01 Top Level
* TinyTapeout GF180nm submission
*
* Clocked failsafe decision block for autonomous drones.
* Evaluates RC and FC health signals using temporal filtering
* and ternary inference to selec... | module triad01_arbitration_engine (
input wire [1:0] fc_score,
input wire [1:0] rc_score,
output reg [1:0] raw_decision
);
// Combinational policy table
always @(*) begin
casez ({rc_score, fc_score})
// RC HIGH — always PRIMARY regardless of FC
4'b10_10: raw_decision = 2'b10; // RC=H... |
ttgf26b_0026 | ttgf26b | Alanduan21-ttgf-triad01 | task_triad01_decision_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Duan Yihe
* SPDX-License-Identifier: Apache-2.0
* project.v — TRIAD01 Top Level
* TinyTapeout GF180nm submission
*
* Clocked failsafe decision block for autonomous drones.
* Evaluates RC and FC health signals using temporal filtering
* and ternary inference to selec... | module triad01_decision_fsm (
input wire clk,
input wire rst_n,
input wire [1:0] raw_decision,
output reg [1:0] decision,
output reg decision_valid,
output wire safehold_active // HIGH when decision == SAFE_HOLD
);
// Number of consecutive stable cycles before commi... |
ttgf26b_0027 | ttgf26b | Alanduan21-ttgf-triad01 | task_triad01_input_filter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Duan Yihe
* SPDX-License-Identifier: Apache-2.0
* project.v — TRIAD01 Top Level
* TinyTapeout GF180nm submission
*
* Clocked failsafe decision block for autonomous drones.
* Evaluates RC and FC health signals using temporal filtering
* and ternary inference to selec... | module triad01_input_filter (
input wire clk,
input wire rst_n,
// raw health inputs
input wire fc_live,
input wire rc_live, // RC signal present
input wire fc_conf, // FC confidence qualifier
input wire rc_conf, // RC confidence qualifier
// 2-bit confidence scores out
ou... |
ttgf26b_0028 | ttgf26b | Alanduan21-ttgf-triad01 | task_triad01_lbist | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Duan Yihe
* SPDX-License-Identifier: Apache-2.0
* project.v — TRIAD01 Top Level
* TinyTapeout GF180nm submission
*
* Clocked failsafe decision block for autonomous drones.
* Evaluates RC and FC health signals using temporal filtering
* and ternary inference to selec... | module triad01_lbist (
input wire clk,
input wire rst_n,
input wire bist_en, // start/enable BIST
// Captured outputs from DUT to compress
input wire [7:0] dut_out, // connect to uo_out in top level
// LFSR stimulus outputs — drive into DUT inputs during BIS... |
ttgf26b_0029 | ttgf26b | Alanduan21-ttgf-triad01 | task_triad01_pwm_gen | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Duan Yihe
* SPDX-License-Identifier: Apache-2.0
* project.v — TRIAD01 Top Level
* TinyTapeout GF180nm submission
*
* Clocked failsafe decision block for autonomous drones.
* Evaluates RC and FC health signals using temporal filtering
* and ternary inference to selec... | module triad01_pwm_gen (
input wire clk,
input wire rst_n,
// Pulse width in clock cycles (from pwm_memory)
// 10 MHz: 10000..20000 = 1..2 ms
input wire [16:0] pulse_width,
// PWM output — connect to servo/ESC signal line
output reg pwm_out
);
// Period counter:... |
ttgf26b_0030 | ttgf26b | Alanduan21-ttgf-triad01 | task_triad01_scan_chain | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Duan Yihe
* SPDX-License-Identifier: Apache-2.0
* project.v — TRIAD01 Top Level
* TinyTapeout GF180nm submission
*
* Clocked failsafe decision block for autonomous drones.
* Evaluates RC and FC health signals using temporal filtering
* and ternary inference to selec... | module triad01_scan_chain (
input wire clk,
input wire rst_n,
input wire scan_en,
input wire scan_in,
output wire scan_out,
// Functional data inputs (wired to actual registers in top)
input wire [3:0] fc_cnt,
input wire [3:0] rc_cnt,
// Scan-obs... |
ttgf26b_0031 | ttgf26b | Alanduan21-ttgf-triad01 | task_triad01_scan_ff | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Duan Yihe
* SPDX-License-Identifier: Apache-2.0
* project.v — TRIAD01 Top Level
* TinyTapeout GF180nm submission
*
* Clocked failsafe decision block for autonomous drones.
* Evaluates RC and FC health signals using temporal filtering
* and ternary inference to selec... | module triad01_scan_ff (
input wire clk,
input wire rst_n,
input wire scan_en,
input wire d_func,
input wire d_scan,
output reg q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 1'b0;
else
q <= scan_en ? d_scan : d_func;
end
endmodule |
ttsky26b_0032 | ttsky26b | Alden-G878-ttsky-verilog-sandsim | task_vga_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sandsim.sv" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// updates sand line
module update
#(parameter COL = 48)
(input logic clk, rst_b,
input logic [COL-1:0] c_in_src, c_in_dest,
output logic [COL-1:0] c_out_sr... | module vga_controller
(input logic clk, rst_b,
input logic pix, pix_valid,
output logic [$clog2(800)-1:0] x_pos,
output logic [$clog2(524)-1:0] y_pos,
output logic [1:0] vga_r, vga_g, vga_b,
output logic vga_hsync, vga_vsync);
always_ff @(posedge clk) beg... |
ttsky26a_0033 | ttsky26a | AmitChen1415-tiny-blackjack | task_blackjack_core | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_AmitChen1415.v" 1
/*
* TinyTapeout Blackjack Wrapper
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_AmitChen1415 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input ... | module blackjack_core (
input wire clk,
input wire rst_n,
input wire btn_hit,
input wire btn_stand,
input wire btn_double,
input wire btn_start,
input wire rng_load,
input wire [15:0] rng_seed,
output reg [5:0] user_total,... |
ttsky26a_0034 | ttsky26a | AmitChen1415-tiny-blackjack | task_blackjack_table | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_AmitChen1415.v" 1
/*
* TinyTapeout Blackjack Wrapper
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_AmitChen1415 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input ... | module blackjack_table (
input wire clk_25MHz,
input wire rst_n,
// VALUES: 0 empty, 2..11 (11=A), 10 means 10/J/Q/K
input wire [3:0] dealer_card1,
input wire [3:0] dealer_card2,
input wire [3:0] dealer_card3,
input wire [3:0] dealer_card4,
input wire [3:0] dea... |
ttsky26a_0035 | ttsky26a | AmitChen1415-tiny-blackjack | task_glyph5x7 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_AmitChen1415.v" 1
/*
* TinyTapeout Blackjack Wrapper
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_AmitChen1415 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input ... | module glyph5x7 (
input wire [4:0] code,
input wire [2:0] col,
input wire [2:0] row,
output reg on
);
reg [4:0] r0,r1,r2,r3,r4,r5,r6;
always @(*) begin
r0=5'b00000; r1=5'b00000; r2=5'b00000; r3=5'b00000; r4=5'b00000; r5=5'b00000; r6=5'b00000;
case (code)
5... |
ttsky25b_0036 | ttsky25b | ArsenoL-ICdesign | task_bitGen | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_flappy_vga_cutout1.v" 1
// Top level module for a VGA based flappy bird game to be included in Tiny Tapeout 05
//
// Author: Daniel Robinson (cutout on Discord)
module tt_um_flappy_vga_cutout1 (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] u... | module bitGen (
input wire clock, reset, bright,
input wire [9:0] h_count, v_count,
input wire [8:0] bird_pos, hole_pos,
input wire [9:0] pipe_pos,
output reg red, green, blue
);
reg next_red, next_blue, next_green;
always@(posedge clock)
begin
if(!reset)
begin
red <= 1'b0;
green <= 1'b0;
blue ... |
ttsky25b_0037 | ttsky25b | ArsenoL-ICdesign | task_gameControl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_flappy_vga_cutout1.v" 1
// Top level module for a VGA based flappy bird game to be included in Tiny Tapeout 05
//
// Author: Daniel Robinson (cutout on Discord)
module tt_um_flappy_vga_cutout1 (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] u... | module gameControl (
input wire clock, reset, v_sync, button,
output reg [8:0] bird_pos, hole_pos,
output reg [9:0] pipe_pos,
output reg [7:0] score
);
reg [8:0] bird_vert_velocity;
reg [7:0] next_hole_pos;
reg has_flapped;
reg game_over;
reg restart_game;
reg has_updated_during_current_v_sync;
reg update_... |
ttsky25b_0038 | ttsky25b | ArsenoL-ICdesign | task_vgaControl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_flappy_vga_cutout1.v" 1
// Top level module for a VGA based flappy bird game to be included in Tiny Tapeout 05
//
// Author: Daniel Robinson (cutout on Discord)
module tt_um_flappy_vga_cutout1 (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] u... | module vgaControl (
input wire clock, reset, // action on posedge clock, reset is active low, enable active high
output reg h_sync, v_sync, // syncs are active low
output reg bright, // bright is active high
output reg [9:0] h_count, v_count
);
always @(posedge clock)
begin
... |
ttgf26a_0039 | ttgf26a | Arty3-ttgf-mac-engine | task_spi_slave | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "pipeline_reg.sv" 1
// ============================================================================
// pipeline_reg.sv - Single pipeline register stage with valid/ready
// ============================================================================
module pipeline_reg #(
parameter int DATA_W = 32
) (
i... | module spi_slave (
input logic clk,
input logic rst_n,
// Raw pad signals (asynchronous to clk)
input logic spi_cs_n_pad,
input logic spi_sclk_pad,
input logic spi_mosi_pad,
output logic spi_miso,
// Regfile port (system clock domain)
output... |
ttsky26b_0040 | ttsky26b | Aymene-ml-IEEE-tiny-8bit-cpu | task_alu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// Expanded ALU for the teaching CPU.
// Supports: ADD, SUB, AND, OR, XOR, SHL, SHR.
module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
... | module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
input wire [7:0] mem_i, // operand B
output reg [7:0] result_o,
output reg carry_o
);
// Operation codes
localparam OP_ADD = 4'h0;
localparam OP_SUB = 4'h1;
localparam OP_AND ... |
ttsky26b_0041 | ttsky26b | Aymene-ml-IEEE-tiny-8bit-cpu | task_control_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// Expanded ALU for the teaching CPU.
// Supports: ADD, SUB, AND, OR, XOR, SHL, SHR.
module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
... | module control_fsm (
input wire clk,
input wire rst_n,
input wire ena,
output reg fetch_phase,
output reg exec_phase
);
reg state_q;
always @(posedge clk) begin
if (!rst_n) begin
state_q <= 1'b0;
end else if (ena) begin
state_q <= ~state_q;
end
end
always @* b... |
ttsky26b_0042 | ttsky26b | Aymene-ml-IEEE-tiny-8bit-cpu | task_control_unit | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// Expanded ALU for the teaching CPU.
// Supports: ADD, SUB, AND, OR, XOR, SHL, SHR.
module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
... | module control_unit (
input wire clk,
input wire rst_n,
input wire ena,
input wire [3:0] opcode_i,
input wire acc_zero_i,
output wire fetch_phase_o,
output wire exec_phase_o,
output reg acc_we_o,
output reg pc_we_o,
output re... |
ttsky26b_0043 | ttsky26b | Aymene-ml-IEEE-tiny-8bit-cpu | task_cpu_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// Expanded ALU for the teaching CPU.
// Supports: ADD, SUB, AND, OR, XOR, SHL, SHR.
module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
... | module cpu_top (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
wire fetch_phase;
wire exec_phase;
wire [7:0] rd_q;
wire... |
ttsky26b_0044 | ttsky26b | Aymene-ml-IEEE-tiny-8bit-cpu | task_datapath | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// Expanded ALU for the teaching CPU.
// Supports: ADD, SUB, AND, OR, XOR, SHL, SHR.
module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
... | module datapath (
input wire clk,
input wire rst_n,
input wire ena,
input wire [7:0] instr_i,
input wire reg_we_i,
input wire pc_we_i,
input wire ir_we_i,
input wire data_we_i,
input wire [3:0] alu_op_i,
input wire [1:0] acc_src... |
ttsky26b_0045 | ttsky26b | Aymene-ml-IEEE-tiny-8bit-cpu | task_memory | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// Expanded ALU for the teaching CPU.
// Supports: ADD, SUB, AND, OR, XOR, SHL, SHR.
module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
... | module memory (
input wire clk,
input wire rst_n,
input wire ena,
input wire [4:0] data_addr,
input wire [7:0] data_wdata,
input wire data_we,
output reg [7:0] data_rdata
);
reg [7:0] data_mem [0:23];
integer idx;
always @* begin
data_rdata = data_m... |
ttsky26b_0046 | ttsky26b | Aymene-ml-IEEE-tiny-8bit-cpu | task_registers | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// Expanded ALU for the teaching CPU.
// Supports: ADD, SUB, AND, OR, XOR, SHL, SHR.
module alu (
input wire [3:0] op_i, // operation select
input wire [7:0] acc_i, // operand A
... | module registers (
input wire clk,
input wire rst_n,
input wire ena,
input wire reg_we, // register write enable
input wire [1:0] reg_wd_idx, // write destination register index (0-3)
input wire [1:0] reg_rs_idx, // read source register index (0-3)
inp... |
ttsky26a_0047 | ttsky26a | BigTurtle8-chip-w26 | task_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar, Derek Maeshiro, Chloe Zhong
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_madech_8bit_processor_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [... | module controller (
input wire clk,
input wire rst,
output wire begin_fetch,
input wire fetch_done,
output wire begin_decode,
input wire decode_done,
output wire begin_executor,
input wire executor_done
);
reg prev_rst;
always @(posedge clk) begin
prev_rst <= rst;
... |
ttsky26a_0048 | ttsky26a | BigTurtle8-chip-w26 | task_decoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar, Derek Maeshiro, Chloe Zhong
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_madech_8bit_processor_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [... | module decoder (
input wire clk,
input wire rst,
input wire [15:0] ins,
input wire begin_decode,
output wire [2:0] op,
output wire [2:0] tt, // og: tf
output wire [2:0] ns, // og: se
output wire [2:0] sf, // og: rt
output wire [5:0] imm,
output wire l,
output wire decod... |
ttsky26a_0049 | ttsky26a | BigTurtle8-chip-w26 | task_processor_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar, Derek Maeshiro, Chloe Zhong
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_madech_8bit_processor_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [... | module processor_top (
input wire clk,
input wire rst,
output wire sck,
output wire [2:0] cs,
output wire mosi,
input wire miso,
input wire [7:0] xpos,
input wire [7:0] ypos,
output wire [5:0] rgb
);
localparam IALEN = 11;
localparam ALEN = 8;
wire fetch_req;
w... |
ttsky26a_0050 | ttsky26a | BigTurtle8-chip-w26 | task_register | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar, Derek Maeshiro, Chloe Zhong
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_madech_8bit_processor_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [... | module register (
input wire clk,
input wire rst,
input wire we,
input wire [7:0] in,
output wire [7:0] out
);
reg [7:0] data;
always @(posedge clk) begin
if (rst) begin
data <= 8'd0;
end else if (we) begin
data <= in;
end else begin
data <= data;
end
end
assign out = data... |
ttsky26a_0051 | ttsky26a | BigTurtle8-ttsky26a-bad-ode-plotter | task_centerer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_bad_ode_plotter_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
outpu... | module centerer(
input wire [7:0] x,
input wire [7:0] y,
output wire signed [7:0] xc,
output wire signed [7:0] yc
);
wire signed [8:0] ext_x = $signed(x);
wire signed [8:0] ext_y = $signed(y);
assign xc = ext_x - 8'sd80;
assign yc = -ext_y + 8'sd59;
endmodule |
ttsky26a_0052 | ttsky26a | BigTurtle8-ttsky26a-bad-ode-plotter | task_gridder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_bad_ode_plotter_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
outpu... | module gridder(
input wire [9:0] hpos,
input wire [9:0] vpos,
output wire [7:0] x,
output wire [7:0] y
);
// declarations for TV-simulator sync parameters
// horizontal constants
parameter H_DISPLAY = 640; // horizontal display width
parameter H_BACK = 48; // horizontal left border (back... |
ttsky26a_0053 | ttsky26a | BigTurtle8-ttsky26a-bad-ode-plotter | task_predictor | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_bad_ode_plotter_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
outpu... | module predictor(
input wire clk,
input wire rst,
input wire signed [7:0] xc,
input wire signed [7:0] yc,
output wire [5:0] curr_rgb,
output wire signed [7:0] xcn, // next centered x
output wire signed [7:0] ycn, // next centered y
input wire [5:0] next_rgb
);
reg signed [7:0] old_xc;
always @(pose... |
ttsky26a_0054 | ttsky26a | BigTurtle8-ttsky26a-bad-ode-plotter | task_solver | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_bad_ode_plotter_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
outpu... | module solver(
input wire clk,
input wire rst,
input wire signed [7:0] xin,
input wire signed [7:0] yin,
output wire is_point,
input wire step
);
localparam a = 2'sd0;
localparam b = -2'sd1;
localparam c = 2'sd1;
localparam d = 2'sd0;
reg signed [7:0] old_x;
always @(posedge clk) begin
... |
ttsky26a_0055 | ttsky26a | BigTurtle8-ttsky26a-bad-ode-plotter | task_solver_step | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Marcus Alagar
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_bad_ode_plotter_vga (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
outpu... | module solver_step(
input wire signed [7:0] xin,
input wire signed [7:0] yin,
output wire signed [7:0] xout,
output wire signed [7:0] yout,
input wire signed [1:0] a,
input wire signed [1:0] b,
input wire signed [1:0] c,
input wire signed [1:0] d
);
// VGA playground doesn't seem to support arithmetic... |
ttihp0p4_0056 | ttihp0p4 | Bynaryman-ttihp04 | task_fpmult_loop_muladd_s3fdp | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 L. Ledoux
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lledoux_bf16_diminished_kulisch (
input wire [7:0] ui_in,
output logic [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe... | module fpmult_loop_muladd_s3fdp(
input clk,
reset,
input [1:0][15:0] a,
b,
c,
input clk_0,
output [15:0] r
);
wire [31:0] _GEN;
wire [31:0] _GEN_0;
wire _GEN_1;
wire [15:0] _s3fdp_accum_r;
wire [31:0... |
ttihp0p4_0057 | ttihp0p4 | Bynaryman-ttihp04 | task_s3fdp_accum_core_wE8_wF7_cs16 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 L. Ledoux
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lledoux_bf16_diminished_kulisch (
input wire [7:0] ui_in,
output logic [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe... | module s3fdp_accum_core_wE8_wF7_cs16(
input clk,
reset,
input [15:0] x,
y,
output [15:0] r
);
reg [10:0] _GEN;
reg [16:0] _GEN_0;
reg [16:0] _GEN_1;
reg [16:0] _GEN_2;
reg [16:0] _GEN_3;
reg [16:0] _GEN_4;
reg [16:0] _GEN_5;
reg [16:0] _GEN... |
ttihp0p4_0058 | ttihp0p4 | Bynaryman-ttihp04_ieee754 | task_fpmult_loop_muladd_s3fdp | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 L. Ledoux
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_lledoux_s3fdp_seqcomb (
input wire [7:0] ui_in,
output logic [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module fpmult_loop_muladd_s3fdp(
input clk,
reset,
input [1:0][31:0] a,
b,
c,
input clk_0,
output [31:0] r
);
wire [31:0] _GEN;
wire [31:0] _GEN_0;
wire [31:0] _GEN_1;
wire _GEN_2;
wire [63:0] _GEN_3... |
ttsky25b_0059 | ttsky25b | Bynaryman-ttihp0p3-z2a-logo-screensaver | task_bitmap_rom | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_zerotoasic_logo_screensaver.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Author: Uri Shaked
*/
`default_nettype none
parameter LOGO_SIZE = 128; // Size of the logo in pixels
parameter DISPLAY_WIDTH = 640; // VGA display width
parameter DISPLAY_HEIGHT = 480... | module bitmap_rom (
input wire [6:0] x,
input wire [6:0] y,
output wire pixel
);
reg [7:0] mem[2047:0];
initial begin
mem[0] = 8'h00;
mem[1] = 8'h00;
mem[2] = 8'h00;
mem[3] = 8'h00;
mem[4] = 8'h00;
mem[5] = 8'h00;
mem[6] = 8'h00;
mem[7] = 8'hff;
mem[8] = 8'hff;
m... |
ttgf26b_0060 | ttgf26b | Cambridge-CIT-ASIC-Tapeouts-ttgf-4b-accumulator-cpu | task_alu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
`timescale 1ns / 1ps
module alu (
input [3:0] acc,
input [3:0] imm,
input [3:0] opcode,
output reg [3:0] result
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`line 20 "alu.v" 2
`line 1 "rom.v" 1
`timescale 1ns / 1ps
module rom (
input [3:... | module alu (
input [3:0] acc,
input [3:0] imm,
input [3:0] opcode,
output reg [3:0] result
);
always @(*) begin
case (opcode)
4'h2: result = acc + imm; // ADD
4'h3: result = acc - imm; // SUB
4'h4: result = acc & imm; // AND
4'h5: result = acc | imm; // OR
... |
ttgf26b_0061 | ttgf26b | Cambridge-CIT-ASIC-Tapeouts-ttgf-4b-accumulator-cpu | task_rom | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu.v" 1
`timescale 1ns / 1ps
module alu (
input [3:0] acc,
input [3:0] imm,
input [3:0] opcode,
output reg [3:0] result
);
always @(*) begin
case (opcode)
4'h2: result = acc + imm; // ADD
4'h3: result = acc - imm; // SUB
4'h4: result = acc & imm; // AND
... | module rom (
input [3:0] addr,
output reg [7:0] instr
);
always @(*) begin
case (addr)
4'd0: instr = 8'h12; // 2
4'd1: instr = 8'h22; // 2
4'd2: instr = 8'h23; // 3
4'd3: instr = 8'h70; // 0
4'd4: instr = 8'h64; // 4
default: instr = 8'h00; // NOP
... |
ttgf0p2_0062 | ttgf0p2 | Capulus123-ttihp03-multi-bit-puf | task_Dlatch | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "multi_bit_puf_wrapper.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_multi_bit_puf_wrapper (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input pat... | module Dlatch(
input enable,
input reset,
input D,
// (* KEEP = "TRUE" *)
output reg Q
);
always @(enable or reset or D) begin
if (reset)
Q <= 1'b0;
else if (enable)
Q <= D; // The input to latch 1 is the inverted signal P1
end
endmodule |
ttgf0p2_0063 | ttgf0p2 | Capulus123-ttihp03-multi-bit-puf | task_one_bit_puf | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "multi_bit_puf_wrapper.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_multi_bit_puf_wrapper (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input pat... | module one_bit_puf(
input wire START, // PUF Start signal
input wire reset, // Reset signal
output wire OUT
);
(* KEEP = "TRUE" *) wire Q0;
(* KEEP = "TRUE" *) wire Q1; // Outputs from the D-Latches
wire P0; // Delays through inverters
wire P1; // Delays through invert... |
ttsky26b_0064 | ttsky26b | Chimmy-U-ttsky-verilog-fp24b-digit-serial-divider | task_controlpath | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_digit_serial_divider.v" 1
`default_nettype none
module tt_um_digit_serial_divider (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output w... | module controlpath (
input clk,
input rst,
output sel_rx,
output sel_ri,
output en_y,
output en_r,
output en_shift,
input carry,
input start,
output done
);
wire ovf, en_counter, clr_counter;
wire [4:0] counter_out, adder_out;
// Instantiate the FSM
fsm fsm0 (
.clk(clk),
... |
ttsky26b_0065 | ttsky26b | Chimmy-U-ttsky-verilog-fp24b-digit-serial-divider | task_datapath | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_digit_serial_divider.v" 1
`default_nettype none
module tt_um_digit_serial_divider (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output w... | module datapath (
input [23:0] x,
input [23:0] y,
output [23:0] q,
output carry,
input sel_rx,
input sel_ri,
input en_y,
input en_r,
input en_shift,
input clk,
input rst
);
wire [24:0] mux_rx_out, mux_ri_out, reg_r_out, reg_y_out, sub_out, internal_y;
wire not_internal_carry... |
ttsky26b_0066 | ttsky26b | Chimmy-U-ttsky-verilog-fp24b-digit-serial-divider | task_digit_serial_divider | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_digit_serial_divider.v" 1
`default_nettype none
module tt_um_digit_serial_divider (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output w... | module digit_serial_divider (
input wire x,
input wire y,
input wire start,
input wire clk,
input wire rst,
output wire q,
output reg done
);
localparam WIDTH = 24;
localparam [2:0]
S_IDLE = 3'd0,
S_LOAD = 3'd1,
S_RUN = 3'd2,
S_CAPTUR... |
ttsky26b_0067 | ttsky26b | Chimmy-U-ttsky-verilog-fp24b-digit-serial-divider | task_digit_serial_divider_core | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_digit_serial_divider.v" 1
`default_nettype none
module tt_um_digit_serial_divider (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output w... | module digit_serial_divider_core (
input [23:0] x,
input [23:0] y,
output [23:0] q,
input start,
output done,
input clk,
input rst
);
wire sel_rx, sel_ri, en_y, en_r, en_shift, carry;
datapath datapath0 (
.x(x),
.y(y),
.q(q),
.carry(carry),
.sel_rx(sel_rx),
.sel_ri(... |
ttsky26b_0068 | ttsky26b | Chimmy-U-ttsky-verilog-fp24b-digit-serial-divider | task_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_digit_serial_divider.v" 1
`default_nettype none
module tt_um_digit_serial_divider (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output w... | module fsm (
input clk,
input rst,
output reg sel_rx,
output reg sel_ri,
output reg en_y,
output reg en_r,
output reg en_shift,
output reg en_counter,
output reg clr_counter,
input ovf,
input carry,
input start
);
localparam start_state=2'b00;
localparam compute_state=2'... |
ttgf26a_0069 | ttgf26a | ColdC5-TinyTapeoutGFPong | task_Digit_Renderer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "main.sv" 1
`default_nettype none
`line 3 "main.sv" 0
`line 1 "hvsync_generator.sv" 1
`line 2 "hvsync_generator.sv" 0
/*
Video sync generator, used to drive a VGA monitor.
Timing from: https://en.wikipedia.org/wiki/Video_Graphics_Array
To use:
- Wire the hsync and vsync signals to top level outputs
- Ad... | module Digit_Renderer (
input wire [3:0] value,
input wire [6:0] x_offset,
input wire [5:0] y_offset,
input wire [6:0] xpos,
input wire [5:0] ypos,
output wire draw
);
reg [6:0] segments;
always @(*) begin
case (value)
4'd0: segments = 7'b1111110;
4'd1: segments = 7'b0110000;
4'd2:... |
ttgf26a_0070 | ttgf26a | ColdC5-TinyTapeoutGFPong | task_Schlaeger | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "main.sv" 1
`default_nettype none
`line 3 "main.sv" 0
`line 1 "hvsync_generator.sv" 1
`line 2 "hvsync_generator.sv" 0
/*
Video sync generator, used to drive a VGA monitor.
Timing from: https://en.wikipedia.org/wiki/Video_Graphics_Array
To use:
- Wire the hsync and vsync signals to top level outputs
- Ad... | module Schlaeger (
input wire clk,
input wire frame_tick,
input wire reset,
input wire move_down,
input wire move_up,
output reg [5:0] pos
);
always @(posedge clk) begin
if (reset) pos <= V_DISPLAY / 2 - 4;
else if (frame_tick) begin
if (move_down && (pos < V_DISPLAY - 9)) pos <= pos + 1;
... |
ttgf26a_0071 | ttgf26a | ColdC5-TinyTapeoutGFPong | task_Schlaeger_collide | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "main.sv" 1
`default_nettype none
`line 3 "main.sv" 0
`line 1 "hvsync_generator.sv" 1
`line 2 "hvsync_generator.sv" 0
/*
Video sync generator, used to drive a VGA monitor.
Timing from: https://en.wikipedia.org/wiki/Video_Graphics_Array
To use:
- Wire the hsync and vsync signals to top level outputs
- Ad... | module Schlaeger_collide (
input wire [5:0] pos,
input wire [5:0] mesure_pos,
output wire res
);
assign res = (mesure_pos >= pos) && ({1'b0, mesure_pos} < ({1'b0, pos} + 7'd9));
endmodule |
ttgf26a_0072 | ttgf26a | ColdC5-TinyTapeoutGFPong | task_hvsync_generator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "main.sv" 1
`default_nettype none
`line 3 "main.sv" 0
`line 1 "hvsync_generator.sv" 1
`line 2 "hvsync_generator.sv" 0
/*
Video sync generator, used to drive a VGA monitor.
Timing from: https://en.wikipedia.org/wiki/Video_Graphics_Array
To use:
- Wire the hsync and vsync signals to top level outputs
- Ad... | module hvsync_generator (
input wire clk,
input wire reset,
output reg hsync,
output reg vsync,
output wire display_on,
output reg [6:0] hpos,
output reg [5:0] vpos,
output wire frame_tick
);
// declarations for TV-simulator sync parameters
// horizontal constants
parameter H_DISPLAY = 64; // 64... |
ttgf26a_0073 | ttgf26a | DanielGabai-ttgf26a-memory-game | task_decoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "top.sv" 1
// `include "lfsr.sv"
// `include "reg_file.sv"
// `include "decoder.sv"
// `include "reg_file.sv"
/* Top level file for the game
Contains the game-state FSM
Input Switch Map:
0 - MSB of User Input | MSB of Seed Input | MSB of Delay Input
1 - User Input | Seed Input ... | module decoder (
input logic [2:0] counter,
output logic [6:0] segments
);
always_comb begin
case(counter)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111... |
ttgf26a_0074 | ttgf26a | DanielGabai-ttgf26a-memory-game | task_delay | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "top.sv" 1
// `include "lfsr.sv"
// `include "reg_file.sv"
// `include "decoder.sv"
// `include "reg_file.sv"
/* Top level file for the game
Contains the game-state FSM
Input Switch Map:
0 - MSB of User Input | MSB of Seed Input | MSB of Delay Input
1 - User Input | Seed Input ... | module delay (
input logic clk,
input logic rst_n,
input logic en,
input logic [7:0] ui_in, // switch input, uses switches 0-4
input logic load_delay,
output logic finish
);
logic [2:0] _unused = ui_in[7:5];
logic [31:0] counter;
logic [4:0] adj_delay;
always_ff @(posedge cl... |
ttgf26a_0075 | ttgf26a | DanielGabai-ttgf26a-memory-game | task_edge_detector | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "top.sv" 1
// `include "lfsr.sv"
// `include "reg_file.sv"
// `include "decoder.sv"
// `include "reg_file.sv"
/* Top level file for the game
Contains the game-state FSM
Input Switch Map:
0 - MSB of User Input | MSB of Seed Input | MSB of Delay Input
1 - User Input | Seed Input ... | module edge_detector (
input logic clk,
input logic rst_n,
input logic btn_in,
output logic pulse_out
);
logic current, prior;
always_ff @( posedge clk ) begin
if (!rst_n) begin
current <= 1'b0;
prior <= 1'b0;
end else begin
current <= btn_in;
prior <= current;
... |
ttgf26a_0076 | ttgf26a | DanielGabai-ttgf26a-memory-game | task_game_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "top.sv" 1
// `include "lfsr.sv"
// `include "reg_file.sv"
// `include "decoder.sv"
// `include "reg_file.sv"
/* Top level file for the game
Contains the game-state FSM
Input Switch Map:
0 - MSB of User Input | MSB of Seed Input | MSB of Delay Input
1 - User Input | Seed Input ... | module game_fsm (
input logic clk,
input logic rst_n,
// Inputs from User/Top
input logic start_btn, // ui_in[7]
input logic submit_pulse, // From edge_detector
// Status Inputs from Datapath
input logic delay_finish,
input logic match,
input logic ro... |
ttgf26a_0077 | ttgf26a | DanielGabai-ttgf26a-memory-game | task_lfsr | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "top.sv" 1
// `include "lfsr.sv"
// `include "reg_file.sv"
// `include "decoder.sv"
// `include "reg_file.sv"
/* Top level file for the game
Contains the game-state FSM
Input Switch Map:
0 - MSB of User Input | MSB of Seed Input | MSB of Delay Input
1 - User Input | Seed Input ... | module lfsr (
input logic clk,
input logic rst_n,
input logic load,
input logic en,
input logic [5:0] seed,
output logic [2:0] r_out
);
logic [5:0] r_store;
always_ff @(posedge clk) begin
if (!rst_n) begin
r_store <= 6'd1;
end else if (load && ~en) begin
r_store <= (seed... |
ttgf26a_0078 | ttgf26a | DanielGabai-ttgf26a-memory-game | task_reg_file | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "top.sv" 1
// `include "lfsr.sv"
// `include "reg_file.sv"
// `include "decoder.sv"
// `include "reg_file.sv"
/* Top level file for the game
Contains the game-state FSM
Input Switch Map:
0 - MSB of User Input | MSB of Seed Input | MSB of Delay Input
1 - User Input | Seed Input ... | module reg_file (
input logic clk,
input logic we,
input logic [2:0] in_reg,
input logic [3:0] in_sel,
input logic [3:0] out_sel,
output logic [2:0] out_reg
);
logic [2:0] registers [15:0];
always_ff @(posedge clk) begin
if (we) begin
registers[in_sel] <= in_reg;
end
end
... |
ttihp26a_0079 | ttihp26a | DelosReyesJordan-ttihp26a-FP8-SEM-Multiplier | task_exponent | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_DelosReyesJordan_SEM.v" 1
/*
* Copyright (c) 2026 Jordan Delos Reyes
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_DelosReyesJordan_SEM (
input wire [7:0] ui_in, // Dedicated inputs -> A
output wire [7:0] uo_out, // Dedicated outputs -> Result
input ... | module exponent (
input clk,
input reset,
input [3:0] A_Exp,
input [3:0] B_Exp,
// This is if we need to increment exponent from our Mantissa
input [1:0] Exp_Inc,
output reg [3:0] Exp_Out,
// This is for telling the Mantissa to Saturate if we set Exp_Unbiased to Saturation
... |
ttihp26a_0080 | ttihp26a | DelosReyesJordan-ttihp26a-FP8-SEM-Multiplier | task_mantissa | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_DelosReyesJordan_SEM.v" 1
/*
* Copyright (c) 2026 Jordan Delos Reyes
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_DelosReyesJordan_SEM (
input wire [7:0] ui_in, // Dedicated inputs -> A
output wire [7:0] uo_out, // Dedicated outputs -> Result
input ... | module mantissa (
input clk,
input reset,
input [2:0] A_Mant,
input [2:0] B_Mant,
// We need our exponents to check if we have a subnormal
input [3:0] A_Exp,
input [3:0] B_Exp,
// This is if we have saturation from our exponents
input Saturate_Mantissa,
output ... |
ttihp26a_0081 | ttihp26a | DelosReyesJordan-ttihp26a-FP8-SEM-Multiplier | task_sign | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_DelosReyesJordan_SEM.v" 1
/*
* Copyright (c) 2026 Jordan Delos Reyes
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_DelosReyesJordan_SEM (
input wire [7:0] ui_in, // Dedicated inputs -> A
output wire [7:0] uo_out, // Dedicated outputs -> Result
input ... | module sign (
input clk, reset,
input A_sign, B_sign,
output reg Sign_out
);
always @(posedge clk or posedge reset) begin
if (reset) begin
// Pressing Resets to 0
Sign_out <= 1'b0;
end
else begin
Sign_ou... |
ttihp26a_0082 | ttihp26a | DelosReyesJordan-ttihp26a-FP8-SEM-Multiplier | task_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_DelosReyesJordan_SEM.v" 1
/*
* Copyright (c) 2026 Jordan Delos Reyes
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_DelosReyesJordan_SEM (
input wire [7:0] ui_in, // Dedicated inputs -> A
output wire [7:0] uo_out, // Dedicated outputs -> Result
input ... | module top (
input clk,
input reset,
input [7:0] A,
input [7:0] B,
output reg [7:0] Result
);
// Break inputs into Sign, Exponent, and Mantissa portions
wire sign_A = A[7];
wire sign_B = B[7];
wire [3:0] exp_A = A[6:3];
wire [3:0] exp_B = B[6:3];
wire... |
ttsky25b_0083 | ttsky25b | DomnikBrandstetter-jku-sky-FunctionGenerator | task_CordicInterativ | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_FG_TOP_Dominik_Brandstetter.v" 1
// Copyright 2025 Dominik Brandstetter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE−2.0
//
... | module CordicInterativ(
input wire clk_i,
input wire rstn_i,
input wire strb_data_valid_i,
input wire signed [7:0] X_i,
input wire signed [7:0] Y_i,
input wire signed [7:0] Z_i,
output wire signed [7:0] X_o,
output wire signed [7:0] Y_o,
o... |
ttsky26b_0084 | ttsky26b | Edward2005lol-ttsky-verilog-template-Slot-Machine-Edward-Lei | task_display_slots | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Edward Lei
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Edward2005lol_Slot_Machine_Top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Inpu... | module display_slots
(
input logic clk,
input logic [1:0] symbol1,
input logic [1:0] symbol2,
input logic [1:0] symbol3,
input logic [9:0] hcount,
input logic [9:0] vcount,
output logic [1:0] red,
output logic [1:0] green,
output logic [1:0] blue
);
//Draw the slots
log... |
ttsky26b_0085 | ttsky26b | Edward2005lol-ttsky-verilog-template-Slot-Machine-Edward-Lei | task_horizontal_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Edward Lei
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Edward2005lol_Slot_Machine_Top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Inpu... | module horizontal_counter
(
input logic clk,
output reg [9:0] H_count_value,
output logic enable_V_counter
);
initial H_count_value = 0;
always @(posedge clk) begin
if (H_count_value < 799) begin
H_count_value <= H_count_value + 1;
enable_V_counter <= 0;
end
... |
ttsky26b_0086 | ttsky26b | Edward2005lol-ttsky-verilog-template-Slot-Machine-Edward-Lei | task_slot_spinner | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Edward Lei
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Edward2005lol_Slot_Machine_Top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Inpu... | module slot_spinner
(
input logic clk,
input logic reset_n,
input logic start,
output logic [1:0] symbol1,
output logic [1:0] symbol2,
output logic [1:0] symbol3
);
enum logic [2:0] {seed_state, start_state, spin_slots, stop_spinning_slot1, stop_spinning_slot2, stop_spinning_slot3} curr_s... |
ttsky26b_0087 | ttsky26b | Edward2005lol-ttsky-verilog-template-Slot-Machine-Edward-Lei | task_vertical_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Edward Lei
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Edward2005lol_Slot_Machine_Top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Inpu... | module vertical_counter
(
input logic clk,
input logic enable_V_counter,
output reg [9:0] V_count_value
);
initial V_count_value = 0;
always @(posedge clk) begin
if (enable_V_counter == 1'b1) begin
if (V_count_value < 524) begin
V_count_value <= V_count_value + 1;
... |
ttgf26b_0088 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_bissc_Barch | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module bissc... | module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [7:0] half_clk_period_i;
wire [7:0] half_clk_period_i;
input [5:0] n_rising_edges_i;
wire [5:0] n_rising_e... |
ttgf26b_0089 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_bissc_capture_Brtl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module bissc_capture_Brtl(clk_i, rst_i, go_i, samp_i, data_i, done_i, pos_o, valid_o, err_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input samp_i;
wire samp_i;
input data_i;
wire data_i;
input done_i;
wire done_i;
output [50:0] pos_o;
wire [50:0] pos_o;
ou... |
ttgf26b_0090 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_bissc_clock_Brtl_688934845f22049cb14668832efa33d45013b6b9 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module bissc_clock_Brtl_688934845f22049cb14668832efa33d45013b6b9(clk_i, rst_i, go_i, n_rising_edges_i, half_clk_period_i, data_i, busy_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [5:0] n_rising_edges_i;
wire [5:0] n_rising_edges_i;
input [7:0] half_clk_per... |
ttgf26b_0091 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_bissc_clock_Brtl_f70af62ee4cd5ae2b0ba027eb472ca7c56eacd2e | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module bissc_clock_Brtl_f70af62ee4cd5ae2b0ba027eb472ca7c56eacd2e(clk_i, rst_i, go_i, n_rising_edges_i, half_clk_period_i, data_i, busy_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [5:0] n_rising_edges_i;
wire [5:0] n_rising_edges_i;
input [7:0] half_clk_per... |
ttgf26b_0092 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_bissc_extended_clock_Brtl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module bissc_extended_clock_Brtl(clk_i, rst_i, go_i, n_rising_edges_i, half_clk_period_i, data_i, done_o, samp_o, data_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [5:0] n_rising_edges_i;
wire [5:0] n_rising_edges_i;
input [7:0] half_clk_period_i;
wire [7... |
ttgf26b_0093 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_pulse_stretch_Brtl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module pulse_stretch_Brtl(clk_i, rst_i, width_i, trig_i, pulse_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input [25:0] width_i;
wire [25:0] width_i;
input trig_i;
wire trig_i;
output pulse_o;
wire pulse_o;
wire _00_;
wire _01_;
wire [25:0] _02_;
wire [25:0] _03_;
wire _04_;
wi... |
ttgf26b_0094 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_pulsed_trigger_Brtl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module pulsed_trigger_Brtl(clk_i, rst_i, go_i, trig_period_i, ntrig_i, width_i, busy_o, trig_o, pulse_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [31:0] trig_period_i;
wire [31:0] trig_period_i;
input [31:0] ntrig_i;
wire [31:0] ntrig_i;
input [25:0] width_i;... |
ttgf26b_0095 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_spi_registers_Brtl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module spi_registers_Brtl(clk_i, rst_i, cs_i, sck_i, rx_i, trig_i, pos_i, pos_valid_i, error_event_i, io_in_i, tx_o, override_trig_o, ntrig_o, trig_period_o, width_o, pos_req_o, acq_start_o, bissc_half_clk_period_o, bissc_n_rising_edges_o, io_dir_o, io_out_o
);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
... |
ttgf26b_0096 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_sync_bit_Brtl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module sync_bit_Brtl(clk_i, bit_i, bit_o);
input clk_i;
wire clk_i;
input bit_i;
wire bit_i;
output bit_o;
wire bit_o;
reg _0_;
reg _1_ = 1'h0;
wire bit_meta;
always @(posedge clk_i)
_0_ <= bit_meta;
always @(posedge clk_i)
_1_ <= bit_i;
assign bit_meta = _1_;
assign bit_o = _0_;
endmo... |
ttgf26b_0097 | ttgf26b | EmilioPeJu-ttgf-lightscan | task_trigger_generator_Brtl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_emiliopeju_lightscan.v" 1
/* Generated by Yosys 0.62 (git sha1 v0.62, g++ 15.2.0 -fPIC -O3) */
module bissc_Barch(clk_i, rst_i, go_i, half_clk_period_i, n_rising_edges_i, data_i, pos_o, valid_o, err_o, clk_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [... | module trigger_generator_Brtl(clk_i, rst_i, go_i, trig_period_i, ntrig_i, busy_o, trig_o);
input clk_i;
wire clk_i;
input rst_i;
wire rst_i;
input go_i;
wire go_i;
input [31:0] trig_period_i;
wire [31:0] trig_period_i;
input [31:0] ntrig_i;
wire [31:0] ntrig_i;
output busy_o;
wire busy_o;
outp... |
ttsky26b_0098 | ttsky26b | Erenkriger-tt-basic-national-anthem-buzzer | task_melody_rom | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Eren Kaçmaz
* SPDX-License-Identifier: Apache-2.0
*
* basic_national_anthem_buzzer
* Plays the Turkish National Anthem (İstiklâl Marşı) as a square-wave melody.
* First 2 stanzas, based on Osman Zeki Üngör's arrangement.
* Connect a piezo buzzer to uo_out[0] through ... | module melody_rom (
input wire [6:0] addr,
output reg [3:0] note,
output reg [3:0] duration,
output wire done
);
localparam MELODY_LEN = 7'd90;
assign done = (addr >= MELODY_LEN);
// Note name aliases
localparam REST = 4'd0,
B3 = 4'd1,
C4 = 4... |
ttsky26b_0099 | ttsky26b | EvanGibsonSmith-ttsky-verilog-egs | task_bm_project | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_bn_lif_evan.sv" 1
`default_nettype none
// =============================================================================
// tt_um_bn_lif_evan — Tiny Tapeout top-level, three-block static select
//
// Pin allocation
// --------------
// ui_in[7:0] — shared data input to all blocks
//
// uio_in[7:6]... | module bm_project (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
output wire [15:0] count,
output wire stream,
input wire clk,
input wire rst_n
);
logic [15:0] count_r;
// Two LFSR instances — same polynomial, different seeds (phase offset)
logi... |
ttsky26b_0100 | ttsky26b | EvanGibsonSmith-ttsky-verilog-egs | task_mult4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_bn_lif_evan.sv" 1
`default_nettype none
// =============================================================================
// tt_um_bn_lif_evan — Tiny Tapeout top-level, three-block static select
//
// Pin allocation
// --------------
// ui_in[7:0] — shared data input to all blocks
//
// uio_in[7:6]... | module mult4 (
input wire [7:0] ui_in,
output wire [7:0] uo_out
);
wire [3:0] a = ui_in[7:4];
wire [3:0] b = ui_in[3:0];
// Full 8-bit product — synthesiser will infer an efficient multiplier
wire [7:0] product = a * b;
assign uo_out = product;
endmodule |
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