NotSoTiny: A Large, Living Benchmark for RTL Code Generation
Paper • 2512.20823 • Published
task_id string | shuttle_name string | project_name string | task_name string | system_message string | prompt string | golden_module string |
|---|---|---|---|---|---|---|
ttsky26b_0001 | ttsky26b | 5iri-tt-riscv-cpu | task_vga_sync | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_systolic_vga.v" 1
// Tiny Tapeout top: 8x8 ternary systolic-array demo rendered directly to VGA.
//
// The logical matrix is 8x8, but it is computed in two passes using a 4x8
// systolic slice so the hardware only contains 32 live PEs.
// ui_in[1:0] select one of four tiny matrix demos.
// VGA shows the ... | module vga_sync (
input wire clk,
input wire rst,
output reg hsync,
output reg vsync,
output wire active,
output wire [ 9:0] px, // pixel x (0..639 in active region)
output wire [ 8:0] py, // pixel y (0..479 in active region)
outpu... |
ttsky26b_0002 | ttsky26b | 5iri-tt-riscv-gpu | task_spi_slave | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_riscv_gpu.v" 1
`timescale 1ns/1ps
`default_nettype none
// TinyTapeout top wrapper for BitNet b1.58-style 4x4 matrix multiply accelerator (W1.58A8).
// Weights (B) are ternary {-1, 0, +1}; activations (A) are uint8. No multipliers needed.
//
// Pin map:
// ui_in[0] = SPI SCLK
// ui_in[1] = SPI CS_... | module spi_slave (
input wire clk, // system clock (must be >> spi_sclk)
input wire rst,
// SPI pins
input wire spi_sclk,
input wire spi_cs_n,
input wire spi_mosi,
output reg spi_miso,
// Register interface
output reg c... |
ttihp26a_0003 | ttihp26a | ADDTDR-tt-pwm-controller | task_PWM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_pwm_controller_atudoroi (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module PWM (
input clk,
input [7:0] PWM_in,
output PWM_out
);
reg [8:0] PWM_accumulator;
initial
PWM_accumulator = 0;
always @(posedge clk) begin
PWM_accumulator <= PWM_accumulator[7:0] + PWM_in;
end
assign PWM_out = PWM_accumulator[8];
endmodule |
ttihp26a_0004 | ttihp26a | ADDTDR-tt-pwm-controller | task_main | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_pwm_controller_atudoroi (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module main(
input CLK_i,
output D1,
output D2,
output D3,
output D4,
output D5,
output D6,
output D7,
output D8,
output TX_TO_FTDI,
input RX_FROM_FTDI
);
wire tx_busy;
wire RxD_data_ready;
wire [7:0] RxD_data;
reg [7:0] GPout;
reg [3:0] mem_address = 4'h0;
reg [7:0] mem [0:8];
... |
ttihp26a_0005 | ttihp26a | ADDTDR-tt-pwm-controller | task_uart_transmitter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_pwm_controller_atudoroi (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module uart_transmitter (
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
parameter ClkFrequency = 12000000; // 12MHz
parameter Baud = 115200;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incom... |
ttsky25b_0006 | ttsky25b | AG2048-tiny-calculator-asic | task_button_reader | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2025 Andy Gong
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_ag2048_tiny_calculator (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module button_reader (
input logic clk,
input logic rst_n,
output logic [3:0] o_word_lines,
input logic [3:0] i_bit_lines,
input logic i_ac_pin,
input logic i_add_pin,
input logic i_sub_pin,
input logic i_mul_pin,
input logic i_div_... |
ttsky26a_0007 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_alu | "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED) | "`line 1 \"project.v\" 1\n/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.(...TRUNCATED) | "module alu (\n //input data\n input wire [15:0] x,\n input wire [15:0] y,\n\n //control(...TRUNCATED) |
ttsky26a_0008 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_computer | "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED) | "`line 1 \"project.v\" 1\n/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.(...TRUNCATED) | "module computer (\n input reset,\n input clk,\n\n //GPIO\n input [7:0] gp_inputs, // D(...TRUNCATED) |
ttsky26a_0009 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_cpu | "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED) | "`line 1 \"project.v\" 1\n/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.(...TRUNCATED) | "module cpu (\n //from data memory\n input [15:0] inM, //RAM[A]\n //from instruction memory(...TRUNCATED) |
ttsky26a_0010 | ttsky26a | Acrazt05-Titan-Processing-Unit-TPU | task_gpio | "You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED) | "`line 1 \"project.v\" 1\n/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.(...TRUNCATED) | "module gpio (\n input clk,\n input reset,\n\n //being driven outside the chip\n input (...TRUNCATED) |
End of preview. Expand in Data Studio
NotSoTiny: A Large, Living Benchmark for RTL Code Generation
Summary
NotSoTiny is a large, structurally rich, and "living" benchmark designed to assess Large Language Models (LLMs) on the generation of context-aware RTL (Register-Transfer Level) code. Built from hundreds of real hardware designs produced by the Tiny Tapeout community, this benchmark overcomes the limitations of prior static datasets by periodically incorporating new designs, making it resilient to data contamination.
As part of the NotSoTiny benchmark's commitment to continuous updates, the dataset is refreshed every 6 months as new Tiny Tapeout shuttles become available.
🌐 Official Portal & Leaderboard: NotSoTiny now features a dedicated Benchmark Website to stay up to date with news, new dataset version releases, and model leaderboards alongside the main TuRTLe portal.
This repository contains the NST-26-07 release, which is the latest version of the benchmark dataset containing 1,146 deduplicated and curated tasks derived from real, taped-out hardware designs across 9 recent Tiny Tapeout shuttles:
ttgf0p3ttgf26bttgf26attsky26bttsky26attihp0p4ttihp26attgf0p2ttsky25b
Note on Previous Releases: If you are looking for the earlier baseline version of the benchmark, you can access the NotSoTiny-25-12 release on Hugging Face.
Unlike previous benchmarks which rely on standalone modules or explicit specifications, NotSoTiny focuses on contextual module completion. In this setup, models are presented with a full design context, where one module is masked. The LLM must infer the missing module's functionality and interface solely from the surrounding implementation, mirroring real-world development scenarios where new components must integrate into existing systems.
Supported Tasks and Leaderboards
- Task:
module-completion(Hardware (Verilog) Code Completion). - Leaderboard: Solutions are evaluated using syntax checks and functional correctness through Formal Equivalence Checking (via Yosys). You can check leaderboards and evaluation updates directly on the NotSoTiny Website or via the TuRTLe Leaderboard space.
Languages
The dataset contains:
- Verilog (for hardware designs, prompts, and golden modules).
- English (for system messages and metadata).
Dataset Structure
Data Instances
Each row in the dataset represents a single module completion task. The model is given a system_message and a prompt (containing the context file task.v), and is expected to generate the missing Verilog code that matches the functionality of the golden_module.
Data Fields
task_id(string): A unique identifier for the task, formatted as<shuttle_name>_<incremental_number>.shuttle_name(string): The identifier of the Tiny Tapeout shuttle from which the design originated (e.g., ttgf0p3, ttsky26c).project_name(string): The name of the original Tiny Tapeout project containing the task.task_name(string): The name of the task directory, corresponding to the specific design module being tested.system_message(string): A unified system prompt (same for all tasks) used to instruct the LLM.prompt(string): The content oftask.v. This contains the surrounding design context with the target module missing, serving as the input for the LLM.golden_module(string): The content oforiginal_module.v. This is the ground truth implementation of the masked module, used for formal verification.
Data Splits
The NST-26-07 release consists of a single split containing 1,146 validated tasks derived from 9 Tiny Tapeout shuttles (ttsky26c, ttgf0p3, ttgf26b, ttgf26a, ttsky26b, ttsky26a, ttihp0p4, ttihp26a, ttgf0p2, and ttsky25b).
Dataset Creation
Curation Rationale
Current RTL benchmarks suffer from insufficient scale, shallow verification protocols, and a high risk of training data contamination. NotSoTiny was created to address these issues by:
- Scale & Complexity: Providing tasks with deeper hierarchies and complex control/datapath interactions typical of real hardware.
- Living Nature: Utilizing the continuous release schedule of Tiny Tapeout shuttles to constantly refresh the benchmark every 6 months, keeping it ahead of LLM training data.
- Rigorous Verification: Using formal equivalence checking to ensure functional correctness, as simulation testbenches were found to have low coverage.
Source Data
The designs are sourced from the Tiny Tapeout project repositories on GitHub. These are open-source digital, mixed-signal, and analog circuits submitted by researchers and engineers for fabrication.
Data Processing
The dataset construction pipeline follows these steps:
- Filtering: Projects are filtered to ensure they contain valid
src/andtest/directories, aMakefile, and a validinfo.yaml. - Module Aggregation: The
vppreproctool is used to merge project files into a single self-contained Verilog file, preserving internal hierarchies. - Task Building: Each aggregated design is decomposed into multiple tasks. For each task, the body of one module is removed (to be generated), while the remaining modules serve as context.
- Temporal Deduplication: To prevent data leakage and redundancy, designs are deduplicated across shuttles using MinHash and Locality-Sensitive Hashing (LSH). If duplicates exist, only the version from the oldest shuttle is retained.
- Self-Verification: A final validation step ensures compatibility by verifying the golden solution against itself using the general Yosys formal verification script. Only tasks that pass this check are included.
Considerations for Using the Data
To use this dataset for benchmarking, it is highly recommended to integrate with the TuRTLe framework. TuRTLe is a unified evaluation framework designed to automate the entire benchmarking pipeline for RTL generation.
Specifically, the framework handles:
- Model Serving: It manages model interactions and generation requests.
- Processing & Verification: It executes all necessary processing steps, from initial syntax validation to rigorous Formal Equivalence Checking (using Yosys) against the
golden_module. - Final Reporting: It calculates and outputs the final performance results using standardized metrics.
Follow the latest updates on model evaluations and benchmarking news at razinemg.github.io/notsotiny-website.
Additional Information
License
The dataset is released under the Apache License 2.0.
Citation Information
@misc{ghorab2025notsotinylargelivingbenchmark,
title={NotSoTiny: A Large, Living Benchmark for RTL Code Generation},
author={Razine Moundir Ghorab and Emanuele Parisi and Cristian Gutierrez-Gomez and Miquel Albert\'i-Binimelis and Miquel Moreto and Dario Garcia-Gasulla and Gokcen Kestor},
year={2025},
eprint={2512.20823},
archivePrefix={arXiv},
primaryClass={cs.AR},
url={[https://arxiv.org/abs/2512.20823](https://arxiv.org/abs/2512.20823)},
}
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