Split (1)

train · 256k rows

text stringlengths 1 2.1M
/****************************************************************************** Data memory and interface Operation table: load/store sign size1 size0 \| Operation 7 0 1 1 1 \| LB 5 0 1 0 1 \| LH 0 0 X 0 0 \| LW 3 0...
// A FIFO is used for a non-duplex communication between a processor and another module fifo(clk,resetn,dataIn,dataOut,wr,rd,full,empty,overflow); parameter LOGSIZE = 2; //Default size is 4 elements (only 3 reqd) parameter WIDTH = 32; //Default width is 32 bits parameter SIZE = 1 << LOGSIZE; input clk,reset...
/************************************************************************** Generic Register **************************************************************************/ module hi_reg(d,clk,resetn,en,q); parameter WIDTH=32; input clk; input resetn; input en; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg ...
/************************************************************************** Fetch Unit op 0 Conditional PC write 1 UnConditional PC write **************************************************************************/ module ifetch(clk,resetn, en, squashn, we, op, ...
/************************************************************************** logic unit - note ALU must be able to increment PC for JAL type instructions Operation Table op 0 AND 1 OR 2 XOR 3 NOR **************************************************************************/ module l...
/************************************************************************** Generic Register **************************************************************************/ module lo_reg(d,clk,resetn,en,q); parameter WIDTH=32; input clk; input resetn; input en; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg ...
module merge26lo(in1, in2, out); input [31:0] in1; input [25:0] in2; output [31:0] out; assign out[31:0]={in1[31:28],in2[25:0],2'b0}; endmodule
/************************************************************************** MUL/DIV unit Operation table op 0 MULTU 1 MULT **************************************************************************/ module mul( opA, opB, op, //is_signed ...
module pcadder(pc, offset, result); parameter PC_WIDTH=32; input [PC_WIDTH-1:0] pc; input [PC_WIDTH-1:0] offset; output [PC_WIDTH-1:0] result; wire dum; assign {dum,result} = pc + {offset[PC_WIDTH-3:0],2'b0}; endmodule
/************************************************************************** Register File - Has two read ports (a and b) and one write port (c) - sel chooses the register to be read/written **************************************************************************/ module reg_file(clk,resetn, a_r...
/************************************************************************** Shifter unit Opcode Table: sign_ext dir 0 0 \| ShiftLeft 0 1 \| ShiftRightLogic 1 1 \| ShiftRightArith **************************************************************************/ modu...
module signext16 ( in, out); input [15:0] in; output [31:0] out; assign out={{16{in[15]}},in[15:0]}; endmodule
//Deepak: Commeted due to error: Module cannot be declared more than once //`include "lo_reg.v" //`include "hi_reg.v" //`include "data_mem_stall.v" //`include "mul.v" //`include "shifter_perbit_pipe.v" //`include "logic_unit.v" //`include "addersub_slt.v" //`include "merge26lo.v" //`include "branchresolve.v" //`includ...
`timescale 1ns / 1ns module system1(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select,wrGeneric,genericDataOut); input clk; input resetn; input [0:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0]...
`timescale 1ns / 1ns module system100(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select,wrGeneric); input clk; input resetn; input [7:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; ...
`timescale 1ns / 1ns module system16(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [4:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31:...
`timescale 1ns / 1ns module system6(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31:0...
`timescale 1ns / 1ns module system9(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31:0...
`define NO_PLI 1 `define TEST_BENCH 1 `timescale 1ms / 10us module test_bench ; parameter I_DATAWIDTH=32; parameter I_ADDRESSWIDTH=16; parameter I_SIZE=65536; parameter D_DATAWIDTH=32; parameter D_BYTEENAWIDTH=4; // usually should be D_DATAWIDTH/8 parameter D_ADDRESSWIDTH=16; parameter D_SIZE=65536; reg clk...
`define NO_PLI 1 `define TEST_BENCH 1 `timescale 1ns / 1ns `define POWER_POSTSYNTHESIS `ifdef POWER_POSTSYNTHESIS //Deepak Error system is already defined here //`include "system.vo" `else // Module system cannot be declared more than once //`include "system.v" //`include "C:/altera/61/modelsim_ae/a...
/**************************************************************************** AddSub unit - Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU is_slt signext addsub op[2] op[1] op[0] \| Operation 0 0 0 0 SUBU 2 0 1 0 SUB 1 0 0 1 ADDU 3 0 ...
// megafunction wizard: %RAM: 2-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: alt_ram_data.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ===========================...
// megafunction wizard: %RAM: 2-PORT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: alt_ram_data.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // =======================...
alt_ram_data alt_ram_data_inst ( .address_a ( address_a_sig ), .address_b ( address_b_sig ), .byteena_a ( byteena_a_sig ), .clock_a ( clock_a_sig ), .clock_b ( clock_b_sig ), .data_a ( data_a_sig ), .data_b ( data_b_sig ), .wren_a ( wren_a_sig ), .wren_b ( wren_b_sig ), .q_a ( q_a_sig ), .q_b ( q_b_sig ) );...
module branchresolve ( en, rs, rt, eq, ne, ltz, lez, gtz, gez, eqz); parameter WIDTH=32; //Deepak : Change from parameter to define input en; input [WIDTH-1:0] rs; input [WIDTH-1:0] rt; output eq; output ne; output ltz; output lez; output gtz; output gez; output eqz; assign eq=(en)&(rs==rt); assign ne=(en)&~eq; assig...
/************************************************************************** Generic Register **************************************************************************/ module register(d,clk,resetn,en,q); parameter WIDTH=32; input clk; input resetn; input en; input [WIDTH-1:0] d; output [WIDTH-1:0] q; re...
/****************************************************************************** Data memory and interface Operation table: load/store sign size1 size0 \| Operation 7 0 1 1 1 \| LB 5 0 1 0 1 \| LH 0 0 X 0 0 \| LW 3 0...
// A FIFO is used for a non-duplex communication between a processor and another module fifo(clk,resetn,dataIn,dataOut,wr,rd,full,empty,overflow); parameter LOGSIZE = 2; //Default size is 4 elements (only 3 reqd) parameter WIDTH = 32; //Default width is 32 bits parameter SIZE = 1 << LOGSIZE; input clk,reset...
/************************************************************************** Generic Register **************************************************************************/ module hi_reg(d,clk,resetn,en,q); parameter WIDTH=32; input clk; input resetn; input en; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg ...
/************************************************************************** Fetch Unit op 0 Conditional PC write 1 UnConditional PC write **************************************************************************/ module ifetch(clk,resetn, en, squashn, we, op, ...
/************************************************************************** logic unit - note ALU must be able to increment PC for JAL type instructions Operation Table op 0 AND 1 OR 2 XOR 3 NOR **************************************************************************/ module l...
/************************************************************************** Generic Register **************************************************************************/ module lo_reg(d,clk,resetn,en,q); parameter WIDTH=32; input clk; input resetn; input en; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg ...
module merge26lo(in1, in2, out); input [31:0] in1; input [25:0] in2; output [31:0] out; assign out[31:0]={in1[31:28],in2[25:0],2'b0}; endmodule
/************************************************************************** MUL/DIV unit Operation table op 0 MULTU 1 MULT **************************************************************************/ module mul( opA, opB, op, //is_signed ...
module pcadder(pc, offset, result); parameter PC_WIDTH=32; input [PC_WIDTH-1:0] pc; input [PC_WIDTH-1:0] offset; output [PC_WIDTH-1:0] result; wire dum; assign {dum,result} = pc + {offset[PC_WIDTH-3:0],2'b0}; endmodule
/************************************************************************** Register File - Has two read ports (a and b) and one write port (c) - sel chooses the register to be read/written **************************************************************************/ module reg_file(clk,resetn, a_r...
/************************************************************************** Shifter unit Opcode Table: sign_ext dir 0 0 \| ShiftLeft 0 1 \| ShiftRightLogic 1 1 \| ShiftRightArith **************************************************************************/ modu...
module signext16 ( in, out); input [15:0] in; output [31:0] out; assign out={{16{in[15]}},in[15:0]}; endmodule
//Deepak: Commeted due to error: Module cannot be declared more than once //`include "lo_reg.v" //`include "hi_reg.v" //`include "data_mem_stall.v" //`include "mul.v" //`include "shifter_perbit_pipe.v" //`include "logic_unit.v" //`include "addersub_slt.v" //`include "merge26lo.v" //`include "branchresolve.v" //`includ...
`timescale 1ns / 1ns module system1(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select,wrGeneric,genericDataOut); input clk; input resetn; input [0:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0]...
`timescale 1ns / 1ns module system100(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select,wrGeneric); input clk; input resetn; input [7:0] processor_select; output [31:0] reg_file_b_readdataout; input [7:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; ...
`timescale 1ns / 1ns module system12(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31...
`timescale 1ns / 1ns module system121(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [8:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [3...
`timescale 1ns / 1ns module system144(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [8:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [3...
`timescale 1ns / 1ns module system150(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [3...
`timescale 1ns / 1ns module system156(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [8:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [3...
`timescale 1ns / 1ns module system16(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [4:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31:...
`timescale 1ns / 1ns module system160(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [3...
`timescale 1ns / 1ns module system169(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [8:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [3...
`timescale 1ns / 1ns module system6(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31:0...
`timescale 1ns / 1ns module system8(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31:...
`timescale 1ns / 1ns module system81(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [8:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31...
`timescale 1ns / 1ns module system9(clk,resetn,boot_iaddr,boot_idata,boot_daddr,boot_ddata,reg_file_b_readdataout,processor_select); input clk; input resetn; input [3:0] processor_select; output [31:0] reg_file_b_readdataout; input [13:0] boot_iaddr; input [31:0] boot_idata; input [13:0] boot_daddr; input [31:0...
`define NO_PLI 1 `define TEST_BENCH 1 `timescale 1ms / 10us module test_bench ; parameter I_DATAWIDTH=32; parameter I_ADDRESSWIDTH=16; parameter I_SIZE=65536; parameter D_DATAWIDTH=32; parameter D_BYTEENAWIDTH=4; // usually should be D_DATAWIDTH/8 parameter D_ADDRESSWIDTH=16; parameter D_SIZE=65536; reg clk...
`define NO_PLI 1 `define TEST_BENCH 1 `timescale 1ns / 1ns `define POWER_POSTSYNTHESIS `ifdef POWER_POSTSYNTHESIS //Deepak Error system is already defined here //`include "system.vo" `else // Module system cannot be declared more than once //`include "system.v" //`include "C:/altera/61/modelsim_ae/a...
///////////////////////////////////////////////////////////////// // // CARPAT: // // This is a ray triangle intersection framework design capable // of rendering an arbitrary number of 3-D triangles on a VGA // monitor. // The Phong lighting model is evaluated by the ray tracer. // A rotation effect is achieved by cam...
module CCD_Capture( oDATA, oDVAL, oX_Cont, oY_Cont, oFrame_Cont, iDATA, iFVAL, iLVAL, iSTART, iEND, iCLK, iRST, oError ); input [9:0] iDATA; input iFVAL; input iLVAL; input iSTART; input iEND; input iCLK; input iRST; output [9:0] oDATA; outpu...
// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: cos_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ================================...
// megafunction wizard: %Shift register (RAM-based)% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altshift_taps // ============================================================ // File Name: Line_Buffer.v // Megafunction Name(s): // altshift_taps // ==========================================================...
module model (current_x, current_y, clk27, rst27, nleft, nright, nup, ndown, model_r, model_g, model_b); input [9:0] current_x, current_y; input nleft, nright, nup, ndown; input clk27, rst27; output [3:0] model_r, model_g, model_b; assign model_r = current_x; //model_rs; assign model_g = current_x; ...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
module multi_tri_debug(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_ed...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
// megafunction wizard: %ALTSQRT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsqrt // ============================================================ // File Name: mysqrt.v // Megafunction Name(s): // altsqrt // // Simulation Library Files(s): // altera_mf // ===========================================...
// megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: my_pll.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // altera_mf // ==============================================...
/* New multi tri -- this module assumes that the model is fully pipelined. It produces 1 triangle every sys_clk and expects an answer from the model every sys_clk (albeit for a triangle sent out ~70 cycles before) This module never produces any junk triangles since it knows exactly how many triangles exist in the ROM....
/* New multi tri -- this module assumes that the model is fully pipelined. It produces 1 triangle every sys_clk and expects an answer from the model every sys_clk (albeit for a triangle sent out ~70 cycles before) This module never produces any junk triangles since it knows exactly how many triangles exist in the ROM....
// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: num_of_triangles_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ===================...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
// megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: pll_sys.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // altera_mf // =============================================...
// megafunction wizard: %ALTPLL%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: pll_sys.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // altera_mf // =========================================...
module RAW2RGB( oRed, oGreen, oBlue, oDVAL, iX_Cont, iY_Cont, iDATA, iDVAL, iCLK, iRST ); input [9:0] iX_Cont; input [9:0] iY_Cont; input [9:0] iDATA; input iDVAL; input iCLK; input iRST; output [9:0] oRed; output [9:0] oGreen; output [9:0] oBlue; output oDVAL; wire [9:0] mD...
///////////////////////////////////////////////////////////////// // // CARPAT: // // This is a ray triangle intersection framework design capable // of rendering an arbitrary number of 3-D triangles on a VGA // monitor. // The Phong lighting model is evaluated by the ray tracer. // A rotation effect is achieved by cam...
module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2); input iCLK; input iRST; output reg oRST_0; output reg oRST_1; output reg oRST_2; reg [21:0] Cont; always@(posedge iCLK or negedge iRST) begin if(!iRST) begin Cont <= 0; oRST_0 <= 0; oRST_1 <= 0; oRST_2 <= 0; end else begin if(Cont!=22'h3FFFFF) Con...
module Sdram_Control_4Port( // HOST Side REF_CLK, RESET_N, CLK, CLK_18, WR1_DATA, WR1, WR1_ADDR, WR1_MAX_ADDR, WR1_LENGTH, WR1_LOAD, WR1_CLK, WR2_DATA, WR2, WR2_ADDR, WR2_MAX_ADDR, WR2_LENGTH, WR2_LOAD, WR2_CLK, RD1_DATA, RD1, RD1_ADDR, ...
// megafunction wizard: %FIFO% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: dcfifo // ============================================================ // File Name: Sdram_FIFO.v // Megafunction Name(s): // dcfifo // ============================================================ // *******************************...
// megafunction wizard: %ALTCLKLOCK% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: Sdram_PLL.v // Megafunction Name(s): // altpll // ============================================================ // **************************...
// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: sin_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ================================...
// megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: trigger_pll.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // altera_mf // =========================================...
// megafunction wizard: %ALTPLL%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: trigger_pll.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // altera_mf // =====================================...
module tri_reader(clk, reset, request_triangle, vertex_x, vertex_y, vertex_z, edge1_x, edge1_y, edge1_z, edge2_x, edge2_y, edge2_z, r, g, b, all_triangles_read, address_reg_out); input clk; input reset; input request_triangle; parameter COORD_SIZE = 12; parameter COLOR_SIZE = 4; parame...
// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: tri_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ================================...
// megafunction wizard: %ROM: 1-PORT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: tri_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================...
module VGA_DATA_REQ( oREQ, iADDR, iCLK, iRST ); input [9:0] iADDR; input iCLK; input iRST; output oREQ; reg [9:0] Pre_ADDR; reg REQ; assign oREQ = REQ; always@(posedge iCLK or negedge iRST) begin if(!iRST) begin Pre_ADDR <= 0; REQ <= 0; end else begin Pre_ADDR <= iADDR; if(Pr...
// Copyright 2007 Altera Corporation. All rights reserved. // Altera products are protected under numerous U.S. and foreign patents, // maskwork rights, copyrights and other intellectual property laws. // // This reference design file, and your use thereof, is subject to and governed // by the terms and conditions...
// Copyright 2007 Altera Corporation. All rights reserved. // Altera products are protected under numerous U.S. and foreign patents, // maskwork rights, copyrights and other intellectual property laws. // // This reference design file, and your use thereof, is subject to and governed // by the terms and conditions...
module vga_study ( //////////////////// Clock Input //////////////////// CLOCK_27, // 27 MHz CLOCK_50, // 50 MHz EXT_CLOCK, // External Clock //////////////////// Push Button //////////////////// // KEY[0] is used for reset KEY, // Pushbutton[3:0] //////////////////// DPDT Sw...
///////////////////////////////////////////////////////////////// // // CARPAT: // // This is a ray triangle intersection framework design capable // of rendering an arbitrary number of 3-D triangles on a VGA // monitor. // The Phong lighting model is evaluated by the ray tracer. // A rotation effect is achieved by cam...
module CCD_Capture( oDATA, oDVAL, oX_Cont, oY_Cont, oFrame_Cont, iDATA, iFVAL, iLVAL, iSTART, iEND, iCLK, iRST, oError ); input [9:0] iDATA; input iFVAL; input iLVAL; input iSTART; input iEND; input iCLK; input iRST; output [9:0] oDATA; outpu...
// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: cos_rom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ================================...
// megafunction wizard: %Shift register (RAM-based)% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altshift_taps // ============================================================ // File Name: Line_Buffer.v // Megafunction Name(s): // altshift_taps // ==========================================================...
module model (current_x, current_y, clk27, rst27, nleft, nright, nup, ndown, model_r, model_g, model_b); input [9:0] current_x, current_y; input nleft, nright, nup, ndown; input clk27, rst27; output [3:0] model_r, model_g, model_b; assign model_r = current_x; //model_rs; assign model_g = current_x; ...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
module multi_tri_debug(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_ed...
module multi_tri(vga_clk, sys_clk, sdram_refclk_50mhz, reset, intersected_tri, intersect_x, intersect_y, intersect_z, intersect_r, intersect_g, intersect_b, tri_reader_vertex_x, tri_reader_vertex_y, tri_reader_vertex_z, tri_reader_edge1_x, tri_reader_edge1_y,...
// megafunction wizard: %ALTSQRT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsqrt // ============================================================ // File Name: mysqrt.v // Megafunction Name(s): // altsqrt // // Simulation Library Files(s): // altera_mf // ===========================================...

Subsets and Splits

No community queries yet

The top public SQL queries from the community will appear here once available.