KlaraHDL/hardware_code_and_sec_small · Datasets at Hugging Face

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<reponame>ashoward/ipbus-firmware<filename>ci/publish.yml save_build_results: stage: publish image: gitlab-registry.cern.ch/ci-tools/ci-web-deployer:latest only: - /^pull-requests.[0-9]+$/ - master - tags - web variables: CI_OUTPUT_DIR: "build_results/" OUTPUT_ROOT_DIR: "/eos/user/i/ipb...
<filename>.github/workflows/main.yml name: 'main' on: push: pull_request: jobs: tests: runs-on: ubuntu-latest strategy: matrix: TEST_CASE: - onenet - OneNetModport - OneFF - OneAnd - OneDivider - OneNetInterf - OneNetR...
pip_test: - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 dst_wire: SLICE_X15Y93.SLICEL/D3 pip_chain_test: - wires: - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE - $CONSTANTS_X0Y0/$GND_NODE - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0 - INT_R_X3Y145/...
<reponame>CansWang/open-source-phy_SKY130 name: rtl commands: - \| mkdir -p outputs cp -r $VLOG_HOME/digital_top ./outputs cat "./outputs/digital_top/digital_top.sv" "./outputs/digital_top/prbs_generator_syn.sv" "./outputs/digital_top/qr_4t1_mux_top.sv" "./outputs/digital_top/hr_16t4_mux_top.sv" "./output...
title: pixhdl email: <EMAIL> description: >- # this means to ignore newlines until "baseurl:" A command-line tool that produces graphical representations of entities from VHDL source files. baseurl: "/pixhdl" # the subpath of your site, e.g. /blog url: "https://kokkonisd.github.io" # the base hostname & protocol for ...
--- category: - Object oriented note: Concurrency requires: - Concurrency - Objects - Mutable State
<gh_stars>1-10 theme: jekyll-theme-dinky title: APB4 Multiplexer description: Parameterized APB4 Slave multiplexer show_downloads: true show_license: true license: Non-Commercial License
<gh_stars>0 # Check NEORV32 software framework and test processor name: Processor on: push: branches: - master paths: - 'rtl/' - 'sw/' - 'sim/' pull_request: branches: - master paths: - 'rtl/' - 'sw/' - 'sim/' workflow_dispatch: jobs: Processor: ...
<filename>.travis.yml<gh_stars>0 matrix: include: - os: linux addons: apt: sources: - ubuntu-toolchain-r-test packages: - g++-7 - libgmp-dev - libmpfr-dev - libmpc-dev - verilator env: - CC=gcc-7 - CXX=g++-7 - os: osx osx_im...
<gh_stars>0 jobs: - single_inflight_00_01_sz_zero: variables: - MKDV_COCOTB_MODULE: fwnoc_tests.single_inflight_00_01_sz_zero - single_inflight_b2b_sz_zero: variables: - MKDV_COCOTB_MODULE: fwnoc_tests.single_inflight_b2b_sz_zero - single_inflight_b...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
<filename>vlog_netlist/osc/osc_design/rtl/configure.yml name: rtl commands: - \| mkdir -p outputs python gen_tcl.py outputs: - design.v - read_design.tcl
<filename>documentation/metadata/an002.yaml --- title: Standard Calling Convention author: - Felix "xq" Queißner date: April 28, 2020 abstract: The Standard Calling Convention (<i>SCC</i>) is the default calling convention used for all <i>SPU Mark II</i> code.
<gh_stars>100-1000 # .github/release.yml changelog: exclude: labels: - ignore-for-release categories: - title: Documentation Changes labels: - Component:Doc - title: RTL Changes labels: - Component:RTL
<gh_stars>1-10 KerasJson: /media/data/projects/landsat_soil_classifier/models/ANN100x100.json KerasH5: /media/data/projects/landsat_soil_classifier/models/ANN100x100_weights.h5 InputData: /media/data/projects/landsat_soil_classifier/data/Landsat_x_test.dat OutputPredictions: /media/data/projects/landsat_soil_classifi...
sim.inputs.top_module: "SVM" sim.inputs.tb_dut: "dut" sim.inputs.tb_name: "SVM_tb" sim.inputs.input_files_meta: "append" sim.inputs.input_files: - "src/SVM_SRAM/SVM.sv" - "src/SVM_SRAM/SVM_tb.sv" - "src/SVM_SRAM/multiply_quantize.sv" - "src/SVM_SRAM/SVM_memories_214.sv" sim.inputs: timescale: "1ns/1ps" ...
ariane: incdirs: [ include, ] files: [ include/riscv_pkg.sv, src/debug/dm_pkg.sv, include/ariane_pkg.sv, include/std_cache_pkg.sv, src/util/instruction_tracer_if.sv, src/util/instruction_tracer_pkg.sv, src/alu.sv, src/ariane.sv, src/branch_unit.sv, src/cache_ctrl.sv, ...
name: Kernel-Auto-Release on: workflow_dispatch: inputs: commit_id: description: 'Commit ID' required: true default: 'HEAD' version_number: description: 'Version Number (Ex. 10.4.4)' required: true default: '10.4.4' main_br_version: descri...
<reponame>WukLab/Clio<gh_stars>10-100 # # This workflow will compile the code and report compiling errors # name: C CI on: [pull_request] jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: prepare run: sudo apt-get -y install rdma-core libibverbs1 libibverbs-de...
from: latex to: markdown_github+table_captions+footnotes standalone: true atx-headers: true shift-heading-level-by: 1 # Added title will be level 1 default-image-extension: png file-scope: true toc: true toc-depth: 3 # Actual depth = 2 as Title added post processing include-in-header: config/frontmatter.md
# Copyright 2018 <NAME> # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, softw...
<gh_stars>0 package: name: mgr_soc author: - "<NAME> <<EMAIL>>" export_include_dirs: - uart - ibex sources: #level 0 - ibex/ibex_pkg.sv - ibex/addr_map_pkg.sv - i2c/i2c_package.sv #level 1 - ibex/ibex_if.sv - wishbone/wishbone_if.sv #level 2 #i2c - i2c/i2c_bit_controller.sv - i2c/i2c_b...
hier-icache: incdirs: [ ../../rtl/includes, ] files: [ RTL/TOP/icache_hier_top.sv, RTL/L1_CACHE/pri_icache_controller.sv, RTL/L1_CACHE/refill_arbiter.sv, RTL/L1_CACHE/pri_icache.sv, RTL/L1_CACHE/register_file_1w_multi_port_read.sv, RTL/L1_CACHE/register_file_1w_multi_port_read_test_wra...
<filename>ips/apb/apb_uart/src_files.yml apb_uart: files: [ apb_uart.vhd, slib_clock_div.vhd, slib_counter.vhd, slib_edge_detect.vhd, slib_fifo.vhd, slib_input_filter.vhd, slib_input_sync.vhd, slib_mv_filter.vhd, uart_baudgen.vhd, uart_interrupt.vhd, uart_receiver.vhd, ...
################################################################ # # Copyright (c) #YEAR# #LICENSOR#. All rights reserved. # # The information and source code contained herein is the # property of #LICENSOR#, and may not be disclosed or # reproduced in whole or in part without explicit written # authorization from ...
<filename>.github/workflows/test.yml name: 'test' on: push: pull_request: schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: fomu-toolchain: strategy: fail-fast: false max-parallel: 3 matrix: include: - { icon: 🐧, os: Ubuntu } - { icon: 🧊, os: Wi...
<reponame>Thales-RISC-V/fpnew package: name: FPnew authors: ["<NAME> <<EMAIL>>"] dependencies: common_cells: {git: "https://github.com/pulp-platform/common_cells.git", rev: 32dd115} fpu_div_sqrt_mvp: {git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", rev: e10ab86} sources: - src/fpnew_pkg.sv -...
# Copyright 2020 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 package: name: snitch_vm authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: common_cells: {path: ../../vendor/pulp_platform_common_...
<reponame>the-moog/hdlConvertor<filename>.circleci/config.yml version: 2.1 orbs: python: circleci/python@0.2.1 py: nic30/python-all-in-1@0.2.47 jobs: install-test-coverage: # executor: python/default resource_class: medium docker: - image: ubuntu:rolling steps: - checkout - run...
<filename>Lib/site-packages/wx-2.8-msw-unicode/wx/tools/Editra/tests/syntax/yaml.yaml # Syntax Highlighting Test file for YAML # Some Comments about this file ---!myDocument logEvent: Hello World date: 2007-08-06 customer: given: Joe family: Bazooka greet: &id001 location: \| I...
<filename>pythondata_cpu_cv32e41p/system_verilog/src_files.yml # Copyright 2020 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 #...
<gh_stars>10-100 name: CI on: # Triggers the workflow on push or pull request events but only for the master branch push: branches: [ master ] pull_request: branches: [ master ] # Allows you to run this workflow manually from the Actions tab workflow_dispatch: jobs: Deploy: runs-on: ubuntu-l...
<gh_stars>1-10 cryoAsicGen1: enable: True ForceWrite: False EpixHRGen1Cryo: enable: True CryoAsic0: enable: True TPS_DAC: 0x3c TPS_GR: 0x1 TPSMux: 0x0 Bias_TPS_Buffer: 0x5 Bias_TPS: 0x4 Bias_TPS_DAC: 0x4 Bias_LVDS_Rx: 0x0 Bias_LVDS_Tx: 0x0 RbiasE...
<filename>.github/workflows/vs.yml name: Visual Studio Build on: [push, pull_request] jobs: yosys-vcxsrc: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Cache sources id: cache-sources uses: actions/cache@v2 with: path: . key: cache-...
SA_BB: type: Path SA_OS: type: Path SA_RA: type: Path SA_CT: type: Path BB_LA: type: Path parameters: cell1_conduction_time: 0.03 cell2_conduction_time: 0.03 LA_LA1: type: Path parameters: cell1_conduction_time: 0.04 cell2_conduction_time: 0.04 RA_RA1: type: Path RA1_CS: type: Path C...
name: Tile_MemCore commands: - bash get_Tile_MemCore_outputs.sh inputs: - design.v outputs: - Tile_MemCore_tt.lib - Tile_MemCore_tt.db - Tile_MemCore.lef - Tile_MemCore.gds - Tile_MemCore.vcs.v - Tile_MemCore.vcs.pg.v - Tile_MemCore.lvs.v - Tile_MemCore.sdf - Tile_MemCore.pt.sdc - Tile_MemCo...
<filename>docs/_data/navigation.yml<gh_stars>10-100 docs_list_title: navigation docs: - title: Home url: index.html - title: Getting Started url: getting_started.html - title: Board Overview url: overview.html - title: Accessories url: accessories.html - title: Overlays url: overlays.html - t...
<gh_stars>0 mchan: incdirs: [ ./rtl/include, ] files: [ ./rtl/misc/mchan_arbiter.sv, ./rtl/misc/mchan_arb_primitive.sv, ./rtl/misc/mchan_rr_flag_req.sv, ./rtl/ctrl_unit/ctrl_fsm.sv, ./rtl/ctrl_unit/ctrl_if.sv, ./rtl/ctrl_unit/ctrl_unit.sv, ./rtl/ctrl_unit/synch_unit.sv, ./rtl/c...
module: test_stm sources: - ../../../interfaces/common/dii_channel.sv - ../../../blocks/regaccess/common/osd_regaccess.sv - ../../../blocks/regaccess/common/osd_regaccess_demux.sv - ../../../blocks/regaccess/common/osd_regaccess_layer.sv - ../../../interconnect/common/ring_router_mux.sv - ../../../blocks/t...
<filename>ivpm.yaml package: name: pybfms-spi version: 0.0.1 deps: - name: pybfms src: pypi - name: cocotb src: pypi dev-deps: - name: pybfms url: https://github.com/pybfms/pybfms.git - name: cocotb src: pypi
<reponame>antmicro/verible-coverage<gh_stars>1-10 image: name: ubuntu:18.04 variables: GIT_STRATEGY: clone before_script: - apt-get update -qq - apt-get install -y wget git build-essential - wget https://github.com/bazelbuild/bazel/releases/download/1.1.0/bazel_1.1.0-linux-x86_64.deb - apt install -y ...
package: name: generic_sram_bfms version: 0.0.1 deps: - name: cocotb type: python src: pypi - name: vlsim url: http://github.com/mballance/vlsim.git type: python - name: pybfms type: python src: pypi dev-deps: - ...
<gh_stars>100-1000 # Copyright cocotb contributors # Licensed under the Revised BSD License, see LICENSE for details. # SPDX-License-Identifier: BSD-3-Clause exclude: "^cocotb/_vendor" repos: - repo: "https://github.com/psf/black" rev: "22.3.0" hooks: - id: "black" args: - "." - repo: "https://github.co...
<reponame>mfkiwl/garnet # Build symlinks necessary to do "make postroute_hold" # using pre-cached collateral from dir $GOLD agents: { queue: "papers" } env: BUILD : /build/prh${BUILDKITE_BUILD_NUMBER}/full_chip GOLD : /sim/buildkite-agent/gold steps: - label: 'hold' commands: - echo "--- POSTROUTE_H...
# # Derived from # https://github.com/steveno/ctags/blob/master/.travis.yml # language: c os: - linux - osx compiler: - gcc - clang env: global: # The next declaration is the encrypted COVERITY_SCAN_TOKEN, created # via the "travis encrypt" command using the project repo's public key - secur...
name: gls-args commands: - echo "+sdfverbose +overlap +multisource_int_delays +neg_tchk -negdelay" > args - echo "-sdf max:Interconnect:inputs/design.sdf" >> args - for ((w=0; w<$array_width; w++)); do for ((h=1; h<=$array_height; h++)); do TILE=$(printf "Tile_X%02X_Y%02X\n" $w $h); if (($w...
<filename>rtl_list.yml<gh_stars>0 # # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # 'domain' refers to the two soc,cluster domains for FPGA # emulator synthesis # tb: path: tb vip: path: vip pulpissimo: path: pulpissimo quicklogic: path: quicklo...
verilog_sources: sim_ctrl: files: "sim_ctrl.sv" fileset: "sim" defines: DT_MSDSL: name: DT_MSDSL value: 0.1e-6 SIMULATION_MODE_MSDSL: name: SIMULATION_MODE_MSDSL fileset: "sim"
# Copyright Google LLC # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, softw...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
<filename>.github/workflows/python-static-analysis.yml name: python static analysis on: push: paths: - '**.py' - '.github/workflows/python-static-analysis.yml' jobs: analyze: runs-on: ubuntu-latest strategy: matrix: python-version: [3.6, 3.7, 3.8, 3.9] steps: - uses:...
<gh_stars>100-1000 name: Update opae-sdk on: repository_dispatch: types: update-opae-libs jobs: create_pr: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 with: fetch-depth: '0' - name: Update opae-libs subtree run: \| git c...
<gh_stars>10-100 name: CI on: push: pull_request: jobs: build: runs-on: ubuntu-20.04 steps: - name: Checkout Lemoncore uses: actions/checkout@v2 with: submodules: recursive - name: Update apt repository run: sudo apt-get update -y - name: Install package...
# Built-in variables set by the hammer-vlsi system. # These settings should not be overridden. vlsi.builtins: # Path to the hammer-vlsi directory. hammer_vlsi_path: ""
<reponame>mfkiwl/garnet<filename>mflowgen/full_chip/tile_array/configure.yml name: tile_array commands: - bash get_tile_array_outputs.sh inputs: - design.v outputs: - tile_array_tt.lib - tile_array.lef - tile_array.gds - tile_array.vcs.v - tile_array.sdf - tile_array.lvs.v - tile_array.sram.spi -...
<gh_stars>1-10 name: ci on: push: branches: - "*" tags: - "v" jobs: # This job builds and updates the docker images on the LibSV's Docker Hub. It will create and push a # new image if any of the following conditions apply: # 1. This is a new commit to the 'main' branch. # 2. If a t...
<filename>Lucee/docker-compose.yml version: "3.5" services: lucee-helloworld: build: context: ./lucee dockerfile: Dockerfile restart: always container_name: helloworld-lucee ports: - "8888:8888" # for multiple instances change 32770 to another port number
<gh_stars>10-100 digital_ctrl_inputs: t_lo: abspath: 'tb_i.t_lo' width: 32 t_hi: abspath: 'tb_i.t_hi' width: 32 digital_ctrl_outputs: clk_i: abspath: 'tb_i.clk_i'
hwpe-color-converter: vlog_opts: [ +nowarnSVCHK, ] incdirs: [ rtl, ] files: [ rtl/control/control.sv, rtl/control/control_registers.sv, rtl/rgb2ycbcr/rgb2ycbcr_package.sv, rtl/rgb2ycbcr/rgb2ycbcr.sv, rtl/rgb2ycbcr/hwpe_rgb2ycbcr.sv, rtl/streamer/streamer.sv, rtl/hwpe_color_...
apiVersion: "v1" kind: "Pod" metadata: name: "rss-site" labels: app: "web" spec: containers: - name: "front-end" image: "nginx" ports: - containerPort": "80" - name: "rss-reader" image: "nickchase/rss-php-nginx:v1" ports: - containerPort": "88"
<filename>ara/hardware/deps/tech_cells_generic/Bender.yml package: name: tech_cells_generic description: "Technology-agnostic building blocks." dependencies: common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } sources: - target: rtl files: # level...
<filename>.gitlab-ci.yml before_script: - git submodule update --init --recursive - export LIBRARY_PATH=$LIBRARY_PATH:$CI_PROJECT_DIR/tmp/lib - export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$CI_PROJECT_DIR/tmp/lib - export C_INCLUDE_PATH=$C_INCLUDE_PATH:$CI_PROJECT_DIR/tmp/include - export CPLUS_INCLUDE_PATH=$CPLUS...
package: name: event_unit_flex sources: include_dirs: ["."] files: - event_unit_core.sv - event_unit_interface_mux.sv - event_unit_top.sv - soc_periph_fifo.sv - interc_sw_evt_trig.sv - hw_barrier_unit.sv - hw_mutex_unit.sv - hw_dispatch.sv
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
--- name: check release on: workflow_dispatch: inputs: tag: description: Release tag required: true env: CM3RELEASE: https://github.com/modula3/cm3/releases/download/${{ github.event.inputs.tag }} jobs: AMD64_DARWIN: runs-on: macos-latest env: CM3DIST: cm3-dist-AMD64_LIN...
<reponame>josnelihurt/de10nano-dev<filename>docker-compose.yml<gh_stars>0 version: "3.5" services: builder: build: context: . target: builder_runner network: host image: de10-nano-builder:v1 container_name: de10nano-builder ports: - "4400:4000" environment: - PASSWORD...
<reponame>dpretet/bster name: smoke_tests on: [push] jobs: run-smoke-tests: runs-on: ubuntu-latest steps: - run: sudo apt-get install iverilog - run: cd ../../; ./flow.sh sim name: Run core's unit test suite shell: bash
language: rust os: linux dist: trusty addons: apt: packages: - libssl-dev cache: cargo rust: - stable - beta - nightly jobs: allow_failures: - rust: nightly script: - cargo clean - cargo build --all - cargo test --all - (cd c-api/bindings/c_cpp/cpp_example && make) after_success: \| if ...
<filename>src_files.yml per2axi: files: [ src/per2axi_busy_unit.sv, src/per2axi_req_channel.sv, src/per2axi_res_channel.sv, src/per2axi.sv, ]
name: vitis-ai-rnn channels: - pytorch - conda-forge - defaults dependencies: - python=3.6 - vai_c_rnn - tf_nndct_lstm - pytorch_nndct_lstm - torchvision==0.5.0
# # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # rtl: path: .. domain: [cluster] common_cells: path: ../../common_cells domain: [cluster]
<gh_stars>100-1000 # Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: snitch_dma authors: - <NAME> <<EMAIL>> dependencies: common_cells: {path: ../../vendor/pulp_platform_common_cells} ...
before_script: - echo start testing $CI_PROJECT_NAME. - git clone gits@xcdl190260:aisw/unilog - git clone gits@xcdl190260:aisw/target_factory - git clone gits@xcdl190260:aisw/xir - git clone gits@xcdl190260:aisw/vart build_on_host: tags: - aisw script: - source /opt/rh/devtoolset-9/e...
<filename>src/test/resources/samples/langs/YAML/vcr_cassette.yml<gh_stars>1000+ --- http_interactions: - request: method: get uri: http://example.com/ body: '' headers: {} response: status: code: 200 message: OK headers: Content-Type: - text/html;charset=utf-8 Con...
name: documentation on: push: branches: [main] jobs: build: name: Sphinx Pages runs-on: ubuntu-latest steps: - name: Checkout 🛎️ uses: actions/checkout@v2 - name: Setup and build 🔧 run: \| sudo apt-get install python3-pip pip3 install sphinx sphinx-...
package: name: ne16 authors: - "<NAME> <<EMAIL>>" dependencies: hwpe-stream: { git: "https://github.com/pulp-platform/hwpe-stream.git", version: 1.6 } hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.6 } hwpe-ctrl: { git: "https://github.com/pulp-platform/hwpe-ctrl.git", ver...
# Python environment and dependencies to build the documentation name: cocotb-docs dependencies: - python=3.8 - pip # Packages installed from PyPI - pip: - -r requirements.txt
<reponame>flasonil/pulp_cluster # # List of IPs and relative branch/commit-hash/tag. # Uses the YAML syntax. # axi/axi2mem: commit: d704c8beff729476d1dbfd7b60679afa796947d2 domain: [soc, cluster] group: pulp-platform axi/axi2per: commit: tags/v1.0.1 domain: [cluster] group: pulp-platform axi/per2axi: c...
name: CI/VHDLTest on: push: branches: [ master ] pull_request: branches: [ master ] jobs: build: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - uses: ghdl/setup-ghdl-ci@nightly with: backend: mcode - name: Setup Python uses: act...
title: AHB-Lite Multi-Layer Interconnect Switch description: Parameterised AHB-Lite Multi-layer Interconnect Switch #theme: jekyll-theme-dinky show_downloads: true show_license: true license: Non-Commercial License repository: RoaLogic/ahb3lite_interconnect url: https://roalogic.github.io baseurl: /ahb3lite_intercon...
timer_unit: incdirs: [ rtl, ] files: [ ./rtl/apb_timer_unit.sv, ./rtl/timer_unit.sv, ./rtl/timer_unit_counter.sv, ./rtl/timer_unit_counter_presc.sv, ]
<reponame>hito0512/Vitis-AI name: vitis-ai-pytorch channels: - pytorch - conda-forge - anaconda dependencies: - python=3.6 - pytorch_nndct_cpu - pyyaml - jupyter - ipywidgets - dill - progressbar2 - pytest - scikit-learn - pandas - matplotlib - vaic
<reponame>asb/opentitan # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # An example custom configuration that generates lots of loops (100 # times as many as the default config), but constrains them not to # take too lo...
--- title: Writing efficient code author: - Felix "xq" Queißner date: April 28, 2020 abstract: The <i>SPU Mark II</i> allows one to write very compact and efficient code. In this document, you learn about different tricks on how to do this.
udma_sdio: files: [ rtl/sdio_crc7.sv, rtl/sdio_crc16.sv, rtl/sdio_txrx_cmd.sv, rtl/sdio_txrx_data.sv, rtl/sdio_txrx.sv, rtl/udma_sdio_reg_if.sv, rtl/udma_sdio_top.sv, ]
ePixHr10kT: enable: True ForceWrite: False InitAfterConfig: False EpixHR: enable: True MMCMRegisters: enable: True CLKOUT0PhaseMux: 0 CLKOUT0HighTime: 2 CLKOUT0LowTime: 2 CLKOUT0Frac: 4 CLKOUT0FracEn: 1 CLKOUT0Edge: 0 CLKOUT0NoCount: 0 CLKOUT0DelayTi...
--- name: fft board: boards/red-pitaya version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/latched_mux_v1_0 - fpga/cores/axis_constant_v1_0 - fpga/cores/redp_adc_v1_0 - fpga/cores/redp_dac_v1_0 - fpga/cores/psd_counter_v1...
#this is a example of how ENC ip is used in our yaml PWM_OUT: IP: __PWM_OUT CMD: PWM pha: PIN: A34 DIRECTION: out phb: PIN: A33 DIRECTION: out
<filename>conda-recipe/meta.yaml package: name: lsst_pwr_ctrl_core version: {{ GIT_DESCRIBE_TAG }} source: path: .. build: number: {{ GIT_DESCRIBE_NUMBER\|int }} requirements: build: - python - rogue - git - gitpython - numpy run: - python - rogue - numpy abo...
os: linux dist: bionic language: generic env: jobs: - LISP=sbcl - LISP=sbcl32 - LISP=ccl - LISP=ccl32 - LISP=ecl - LISP=allegro - LISP=cmucl # - LISP=abcl jobs: allow_failures: - env: LISP=abcl - env: LISP=allegro - env: LISP=ccl32 - env: LISP=cmucl notifications: ...
<filename>.github/workflows/images.yml name: 'images' on: push: paths: - '.github/workflows/images.yml' - '.github/images.sh' schedule: - cron: '0 0 * * 5' env: DOCKER_BUILDKIT: '1' jobs: build: strategy: fail-fast: false max-parallel: 2 matrix: task: [ ...
<gh_stars>0 package: name: ara authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 } common_cells: { git: "...
<gh_stars>0 # Device description for the Agilent 33250A Function/Arbitrary Waveform Generator. # set_ function expect a parameter, get_ function return a parameter. # Just the very basic commands are imlemented here. identifier : Agilent Technologies,33250A set_burst : BURST:STAT get_burst : BURST:STAT? set_n_bursts :...
<reponame>mithro/hgdb name: Deployment Linux on: push: tags: - '*' jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Checkout submodules 🖥️ shell: bash run: \| auth_header="$(git config --local --get http.https://github.com/.extraheader)...
name: i2c_master_top clock_port: wb_clk_i verilog: - i2c_master_bit_ctrl.v - i2c_master_byte_ctrl.v - i2c_master_defines.v - i2c_master_top.v - timescale.v
<gh_stars>10-100 before_install: - sudo apt-get install scala verilator language: scala scala: - 2.12.6 jdk: - openjdk8 script: - make
--- networkRows: 1 networkCols: 1 foxNetworkStages: 1 foxNodeFifos: peToNetwork: 0 networkToPe: 0 resultNodeCoord: x: 0 y: 0 resultNodeFifos: peToNetwork: 0 networkToPe: 0 resultUartFifoDepth: 1024 romNodeCoord: x: 0 y: 0 packetFormat: multicastGroupBits: 1 multicastCoordBits: 1 readyFlagBi...
# TODO: Set number of vectors parameter in python file and testbench from yml name: testbench outputs: - testbench.sv - test_vectors.txt - design.args parameters: testbench_name: GcdUnitTb dut_name: GcdUnit_inst commands: - cp GcdUnitTb.sv outputs/testbench.sv - python3 generate_test_vectors.py - cp...
<filename>hw/ip/otbn/dv/rig/rig/configs/straight-line.yml # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # An custom configuration that doesn't generate any branches, and # increases the weight for BadCallStackRW. The i...
name: Export KiCAD Designs on: #push: # branches: [ main ] # paths: ['circuits/'] #pull_request: # branches: [ main ] # paths: ['circuits/'] # Allows you to run this workflow manually from the Actions tab workflow_dispatch: jobs: build: runs-on: ubuntu-latest steps: ...

<reponame>ashoward/ipbus-firmware<filename>ci/publish.yml save_build_results: stage: publish image: gitlab-registry.cern.ch/ci-tools/ci-web-deployer:latest only: - /^pull-requests.[0-9]+$/ - master - tags - web variables: CI_OUTPUT_DIR: "build_results/" OUTPUT_ROOT_DIR: "/eos/user/i/ipb...

<filename>.github/workflows/main.yml name: 'main' on: push: pull_request: jobs: tests: runs-on: ubuntu-latest strategy: matrix: TEST_CASE: - onenet - OneNetModport - OneFF - OneAnd - OneDivider - OneNetInterf - OneNetR...

pip_test: - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 dst_wire: SLICE_X15Y93.SLICEL/D3 pip_chain_test: - wires: - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE - $CONSTANTS_X0Y0/$GND_NODE - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0 - INT_R_X3Y145/...

<reponame>CansWang/open-source-phy_SKY130 name: rtl commands: - | mkdir -p outputs cp -r $VLOG_HOME/digital_top ./outputs cat "./outputs/digital_top/digital_top.sv" "./outputs/digital_top/prbs_generator_syn.sv" "./outputs/digital_top/qr_4t1_mux_top.sv" "./outputs/digital_top/hr_16t4_mux_top.sv" "./output...

title: pixhdl email: <EMAIL> description: >- # this means to ignore newlines until "baseurl:" A command-line tool that produces graphical representations of entities from VHDL source files. baseurl: "/pixhdl" # the subpath of your site, e.g. /blog url: "https://kokkonisd.github.io" # the base hostname & protocol for ...

--- category: - Object oriented note: Concurrency requires: - Concurrency - Objects - Mutable State

<gh_stars>1-10 theme: jekyll-theme-dinky title: APB4 Multiplexer description: Parameterized APB4 Slave multiplexer show_downloads: true show_license: true license: Non-Commercial License

<gh_stars>0 # Check NEORV32 software framework and test processor name: Processor on: push: branches: - master paths: - 'rtl/**' - 'sw/**' - 'sim/**' pull_request: branches: - master paths: - 'rtl/**' - 'sw/**' - 'sim/**' workflow_dispatch: jobs: Processor: ...

<filename>.travis.yml<gh_stars>0 matrix: include: - os: linux addons: apt: sources: - ubuntu-toolchain-r-test packages: - g++-7 - libgmp-dev - libmpfr-dev - libmpc-dev - verilator env: - CC=gcc-7 - CXX=g++-7 - os: osx osx_im...

<gh_stars>0 jobs: - single_inflight_00_01_sz_zero: variables: - MKDV_COCOTB_MODULE: fwnoc_tests.single_inflight_00_01_sz_zero - single_inflight_b2b_sz_zero: variables: - MKDV_COCOTB_MODULE: fwnoc_tests.single_inflight_b2b_sz_zero - single_inflight_b...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

<filename>vlog_netlist/osc/osc_design/rtl/configure.yml name: rtl commands: - | mkdir -p outputs python gen_tcl.py outputs: - design.v - read_design.tcl

<filename>documentation/metadata/an002.yaml --- title: Standard Calling Convention author: - Felix "xq" Queißner date: April 28, 2020 abstract: The Standard Calling Convention (SCC) is the default calling convention used for all SPU Mark II code.

<gh_stars>100-1000 # .github/release.yml changelog: exclude: labels: - ignore-for-release categories: - title: Documentation Changes labels: - Component:Doc - title: RTL Changes labels: - Component:RTL

<gh_stars>1-10 KerasJson: /media/data/projects/landsat_soil_classifier/models/ANN100x100.json KerasH5: /media/data/projects/landsat_soil_classifier/models/ANN100x100_weights.h5 InputData: /media/data/projects/landsat_soil_classifier/data/Landsat_x_test.dat OutputPredictions: /media/data/projects/landsat_soil_classifi...

sim.inputs.top_module: "SVM" sim.inputs.tb_dut: "dut" sim.inputs.tb_name: "SVM_tb" sim.inputs.input_files_meta: "append" sim.inputs.input_files: - "src/SVM_SRAM/SVM.sv" - "src/SVM_SRAM/SVM_tb.sv" - "src/SVM_SRAM/multiply_quantize.sv" - "src/SVM_SRAM/SVM_memories_214.sv" sim.inputs: timescale: "1ns/1ps" ...

ariane: incdirs: [ include, ] files: [ include/riscv_pkg.sv, src/debug/dm_pkg.sv, include/ariane_pkg.sv, include/std_cache_pkg.sv, src/util/instruction_tracer_if.sv, src/util/instruction_tracer_pkg.sv, src/alu.sv, src/ariane.sv, src/branch_unit.sv, src/cache_ctrl.sv, ...

name: Kernel-Auto-Release on: workflow_dispatch: inputs: commit_id: description: 'Commit ID' required: true default: 'HEAD' version_number: description: 'Version Number (Ex. 10.4.4)' required: true default: '10.4.4' main_br_version: descri...

<reponame>WukLab/Clio<gh_stars>10-100 # # This workflow will compile the code and report compiling errors # name: C CI on: [pull_request] jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: prepare run: sudo apt-get -y install rdma-core libibverbs1 libibverbs-de...

from: latex to: markdown_github+table_captions+footnotes standalone: true atx-headers: true shift-heading-level-by: 1 # Added title will be level 1 default-image-extension: png file-scope: true toc: true toc-depth: 3 # Actual depth = 2 as Title added post processing include-in-header: config/frontmatter.md

# Copyright 2018 <NAME> # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, softw...

<gh_stars>0 package: name: mgr_soc author: - "<NAME> <<EMAIL>>" export_include_dirs: - uart - ibex sources: #level 0 - ibex/ibex_pkg.sv - ibex/addr_map_pkg.sv - i2c/i2c_package.sv #level 1 - ibex/ibex_if.sv - wishbone/wishbone_if.sv #level 2 #i2c - i2c/i2c_bit_controller.sv - i2c/i2c_b...

hier-icache: incdirs: [ ../../rtl/includes, ] files: [ RTL/TOP/icache_hier_top.sv, RTL/L1_CACHE/pri_icache_controller.sv, RTL/L1_CACHE/refill_arbiter.sv, RTL/L1_CACHE/pri_icache.sv, RTL/L1_CACHE/register_file_1w_multi_port_read.sv, RTL/L1_CACHE/register_file_1w_multi_port_read_test_wra...

<filename>ips/apb/apb_uart/src_files.yml apb_uart: files: [ apb_uart.vhd, slib_clock_div.vhd, slib_counter.vhd, slib_edge_detect.vhd, slib_fifo.vhd, slib_input_filter.vhd, slib_input_sync.vhd, slib_mv_filter.vhd, uart_baudgen.vhd, uart_interrupt.vhd, uart_receiver.vhd, ...

################################################################ # # Copyright (c) #YEAR# #LICENSOR#. All rights reserved. # # The information and source code contained herein is the # property of #LICENSOR#, and may not be disclosed or # reproduced in whole or in part without explicit written # authorization from ...

<filename>.github/workflows/test.yml name: 'test' on: push: pull_request: schedule: - cron: '0 0 * * 5' workflow_dispatch: jobs: fomu-toolchain: strategy: fail-fast: false max-parallel: 3 matrix: include: - { icon: 🐧, os: Ubuntu } - { icon: 🧊, os: Wi...

<reponame>Thales-RISC-V/fpnew package: name: FPnew authors: ["<NAME> <<EMAIL>>"] dependencies: common_cells: {git: "https://github.com/pulp-platform/common_cells.git", rev: 32dd115} fpu_div_sqrt_mvp: {git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", rev: e10ab86} sources: - src/fpnew_pkg.sv -...

# Copyright 2020 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 package: name: snitch_vm authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: common_cells: {path: ../../vendor/pulp_platform_common_...

<reponame>the-moog/hdlConvertor<filename>.circleci/config.yml version: 2.1 orbs: python: circleci/python@0.2.1 py: nic30/python-all-in-1@0.2.47 jobs: install-test-coverage: # executor: python/default resource_class: medium docker: - image: ubuntu:rolling steps: - checkout - run...

<filename>Lib/site-packages/wx-2.8-msw-unicode/wx/tools/Editra/tests/syntax/yaml.yaml # Syntax Highlighting Test file for YAML # Some Comments about this file ---!myDocument logEvent: Hello World date: 2007-08-06 customer: given: Joe family: Bazooka greet: &id001 location: | I...

<filename>pythondata_cpu_cv32e41p/system_verilog/src_files.yml # Copyright 2020 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 #...

<gh_stars>10-100 name: CI on: # Triggers the workflow on push or pull request events but only for the master branch push: branches: [ master ] pull_request: branches: [ master ] # Allows you to run this workflow manually from the Actions tab workflow_dispatch: jobs: Deploy: runs-on: ubuntu-l...

<gh_stars>1-10 cryoAsicGen1: enable: True ForceWrite: False EpixHRGen1Cryo: enable: True CryoAsic0: enable: True TPS_DAC: 0x3c TPS_GR: 0x1 TPSMux: 0x0 Bias_TPS_Buffer: 0x5 Bias_TPS: 0x4 Bias_TPS_DAC: 0x4 Bias_LVDS_Rx: 0x0 Bias_LVDS_Tx: 0x0 RbiasE...

<filename>.github/workflows/vs.yml name: Visual Studio Build on: [push, pull_request] jobs: yosys-vcxsrc: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Cache sources id: cache-sources uses: actions/cache@v2 with: path: . key: cache-...

SA_BB: type: Path SA_OS: type: Path SA_RA: type: Path SA_CT: type: Path BB_LA: type: Path parameters: cell1_conduction_time: 0.03 cell2_conduction_time: 0.03 LA_LA1: type: Path parameters: cell1_conduction_time: 0.04 cell2_conduction_time: 0.04 RA_RA1: type: Path RA1_CS: type: Path C...

name: Tile_MemCore commands: - bash get_Tile_MemCore_outputs.sh inputs: - design.v outputs: - Tile_MemCore_tt.lib - Tile_MemCore_tt.db - Tile_MemCore.lef - Tile_MemCore.gds - Tile_MemCore.vcs.v - Tile_MemCore.vcs.pg.v - Tile_MemCore.lvs.v - Tile_MemCore.sdf - Tile_MemCore.pt.sdc - Tile_MemCo...

<filename>docs/_data/navigation.yml<gh_stars>10-100 docs_list_title: navigation docs: - title: Home url: index.html - title: Getting Started url: getting_started.html - title: Board Overview url: overview.html - title: Accessories url: accessories.html - title: Overlays url: overlays.html - t...

<gh_stars>0 mchan: incdirs: [ ./rtl/include, ] files: [ ./rtl/misc/mchan_arbiter.sv, ./rtl/misc/mchan_arb_primitive.sv, ./rtl/misc/mchan_rr_flag_req.sv, ./rtl/ctrl_unit/ctrl_fsm.sv, ./rtl/ctrl_unit/ctrl_if.sv, ./rtl/ctrl_unit/ctrl_unit.sv, ./rtl/ctrl_unit/synch_unit.sv, ./rtl/c...

module: test_stm sources: - ../../../interfaces/common/dii_channel.sv - ../../../blocks/regaccess/common/osd_regaccess.sv - ../../../blocks/regaccess/common/osd_regaccess_demux.sv - ../../../blocks/regaccess/common/osd_regaccess_layer.sv - ../../../interconnect/common/ring_router_mux.sv - ../../../blocks/t...

<filename>ivpm.yaml package: name: pybfms-spi version: 0.0.1 deps: - name: pybfms src: pypi - name: cocotb src: pypi dev-deps: - name: pybfms url: https://github.com/pybfms/pybfms.git - name: cocotb src: pypi

<reponame>antmicro/verible-coverage<gh_stars>1-10 image: name: ubuntu:18.04 variables: GIT_STRATEGY: clone before_script: - apt-get update -qq - apt-get install -y wget git build-essential - wget https://github.com/bazelbuild/bazel/releases/download/1.1.0/bazel_1.1.0-linux-x86_64.deb - apt install -y ...

package: name: generic_sram_bfms version: 0.0.1 deps: - name: cocotb type: python src: pypi - name: vlsim url: http://github.com/mballance/vlsim.git type: python - name: pybfms type: python src: pypi dev-deps: - ...

<gh_stars>100-1000 # Copyright cocotb contributors # Licensed under the Revised BSD License, see LICENSE for details. # SPDX-License-Identifier: BSD-3-Clause exclude: "^cocotb/_vendor" repos: - repo: "https://github.com/psf/black" rev: "22.3.0" hooks: - id: "black" args: - "." - repo: "https://github.co...

<reponame>mfkiwl/garnet # Build symlinks necessary to do "make postroute_hold" # using pre-cached collateral from dir $GOLD agents: { queue: "papers" } env: BUILD : /build/prh${BUILDKITE_BUILD_NUMBER}/full_chip GOLD : /sim/buildkite-agent/gold steps: - label: 'hold' commands: - echo "--- POSTROUTE_H...

# # Derived from # https://github.com/steveno/ctags/blob/master/.travis.yml # language: c os: - linux - osx compiler: - gcc - clang env: global: # The next declaration is the encrypted COVERITY_SCAN_TOKEN, created # via the "travis encrypt" command using the project repo's public key - secur...

name: gls-args commands: - echo "+sdfverbose +overlap +multisource_int_delays +neg_tchk -negdelay" > args - echo "-sdf max:Interconnect:inputs/design.sdf" >> args - for ((w=0; w<$array_width; w++)); do for ((h=1; h<=$array_height; h++)); do TILE=$(printf "Tile_X%02X_Y%02X\n" $w $h); if (($w...

<filename>rtl_list.yml<gh_stars>0 # # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # 'domain' refers to the two soc,cluster domains for FPGA # emulator synthesis # tb: path: tb vip: path: vip pulpissimo: path: pulpissimo quicklogic: path: quicklo...

verilog_sources: sim_ctrl: files: "sim_ctrl.sv" fileset: "sim" defines: DT_MSDSL: name: DT_MSDSL value: 0.1e-6 SIMULATION_MODE_MSDSL: name: SIMULATION_MODE_MSDSL fileset: "sim"

# Copyright Google LLC # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, softw...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

<filename>.github/workflows/python-static-analysis.yml name: python static analysis on: push: paths: - '**.py' - '.github/workflows/python-static-analysis.yml' jobs: analyze: runs-on: ubuntu-latest strategy: matrix: python-version: [3.6, 3.7, 3.8, 3.9] steps: - uses:...

<gh_stars>100-1000 name: Update opae-sdk on: repository_dispatch: types: update-opae-libs jobs: create_pr: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 with: fetch-depth: '0' - name: Update opae-libs subtree run: | git c...

<gh_stars>10-100 name: CI on: push: pull_request: jobs: build: runs-on: ubuntu-20.04 steps: - name: Checkout Lemoncore uses: actions/checkout@v2 with: submodules: recursive - name: Update apt repository run: sudo apt-get update -y - name: Install package...

# Built-in variables set by the hammer-vlsi system. # These settings should not be overridden. vlsi.builtins: # Path to the hammer-vlsi directory. hammer_vlsi_path: ""

<reponame>mfkiwl/garnet<filename>mflowgen/full_chip/tile_array/configure.yml name: tile_array commands: - bash get_tile_array_outputs.sh inputs: - design.v outputs: - tile_array_tt.lib - tile_array.lef - tile_array.gds - tile_array.vcs.v - tile_array.sdf - tile_array.lvs.v - tile_array.sram.spi -...

<gh_stars>1-10 name: ci on: push: branches: - "**" tags: - "v*" jobs: # This job builds and updates the docker images on the LibSV's Docker Hub. It will create and push a # new image if any of the following conditions apply: # 1. This is a new commit to the 'main' branch. # 2. If a t...

<filename>Lucee/docker-compose.yml version: "3.5" services: lucee-helloworld: build: context: ./lucee dockerfile: Dockerfile restart: always container_name: helloworld-lucee ports: - "8888:8888" # for multiple instances change 32770 to another port number

<gh_stars>10-100 digital_ctrl_inputs: t_lo: abspath: 'tb_i.t_lo' width: 32 t_hi: abspath: 'tb_i.t_hi' width: 32 digital_ctrl_outputs: clk_i: abspath: 'tb_i.clk_i'

hwpe-color-converter: vlog_opts: [ +nowarnSVCHK, ] incdirs: [ rtl, ] files: [ rtl/control/control.sv, rtl/control/control_registers.sv, rtl/rgb2ycbcr/rgb2ycbcr_package.sv, rtl/rgb2ycbcr/rgb2ycbcr.sv, rtl/rgb2ycbcr/hwpe_rgb2ycbcr.sv, rtl/streamer/streamer.sv, rtl/hwpe_color_...

apiVersion: "v1" kind: "Pod" metadata: name: "rss-site" labels: app: "web" spec: containers: - name: "front-end" image: "nginx" ports: - containerPort": "80" - name: "rss-reader" image: "nickchase/rss-php-nginx:v1" ports: - containerPort": "88"

<filename>ara/hardware/deps/tech_cells_generic/Bender.yml package: name: tech_cells_generic description: "Technology-agnostic building blocks." dependencies: common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } sources: - target: rtl files: # level...

<filename>.gitlab-ci.yml before_script: - git submodule update --init --recursive - export LIBRARY_PATH=$LIBRARY_PATH:$CI_PROJECT_DIR/tmp/lib - export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$CI_PROJECT_DIR/tmp/lib - export C_INCLUDE_PATH=$C_INCLUDE_PATH:$CI_PROJECT_DIR/tmp/include - export CPLUS_INCLUDE_PATH=$CPLUS...

package: name: event_unit_flex sources: include_dirs: ["."] files: - event_unit_core.sv - event_unit_interface_mux.sv - event_unit_top.sv - soc_periph_fifo.sv - interc_sw_evt_trig.sv - hw_barrier_unit.sv - hw_mutex_unit.sv - hw_dispatch.sv

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

--- name: check release on: workflow_dispatch: inputs: tag: description: Release tag required: true env: CM3RELEASE: https://github.com/modula3/cm3/releases/download/${{ github.event.inputs.tag }} jobs: AMD64_DARWIN: runs-on: macos-latest env: CM3DIST: cm3-dist-AMD64_LIN...

<reponame>josnelihurt/de10nano-dev<filename>docker-compose.yml<gh_stars>0 version: "3.5" services: builder: build: context: . target: builder_runner network: host image: de10-nano-builder:v1 container_name: de10nano-builder ports: - "4400:4000" environment: - PASSWORD...

<reponame>dpretet/bster name: smoke_tests on: [push] jobs: run-smoke-tests: runs-on: ubuntu-latest steps: - run: sudo apt-get install iverilog - run: cd ../../; ./flow.sh sim name: Run core's unit test suite shell: bash

language: rust os: linux dist: trusty addons: apt: packages: - libssl-dev cache: cargo rust: - stable - beta - nightly jobs: allow_failures: - rust: nightly script: - cargo clean - cargo build --all - cargo test --all - (cd c-api/bindings/c_cpp/cpp_example && make) after_success: | if ...

<filename>src_files.yml per2axi: files: [ src/per2axi_busy_unit.sv, src/per2axi_req_channel.sv, src/per2axi_res_channel.sv, src/per2axi.sv, ]

name: vitis-ai-rnn channels: - pytorch - conda-forge - defaults dependencies: - python=3.6 - vai_c_rnn - tf_nndct_lstm - pytorch_nndct_lstm - torchvision==0.5.0

# # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # rtl: path: .. domain: [cluster] common_cells: path: ../../common_cells domain: [cluster]

<gh_stars>100-1000 # Copyright 2020 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: snitch_dma authors: - <NAME> <<EMAIL>> dependencies: common_cells: {path: ../../vendor/pulp_platform_common_cells} ...

before_script: - echo start testing $CI_PROJECT_NAME. - git clone gits@xcdl190260:aisw/unilog - git clone gits@xcdl190260:aisw/target_factory - git clone gits@xcdl190260:aisw/xir - git clone gits@xcdl190260:aisw/vart build_on_host: tags: - aisw script: - source /opt/rh/devtoolset-9/e...

<filename>src/test/resources/samples/langs/YAML/vcr_cassette.yml<gh_stars>1000+ --- http_interactions: - request: method: get uri: http://example.com/ body: '' headers: {} response: status: code: 200 message: OK headers: Content-Type: - text/html;charset=utf-8 Con...

name: documentation on: push: branches: [main] jobs: build: name: Sphinx Pages runs-on: ubuntu-latest steps: - name: Checkout 🛎️ uses: actions/checkout@v2 - name: Setup and build 🔧 run: | sudo apt-get install python3-pip pip3 install sphinx sphinx-...

package: name: ne16 authors: - "<NAME> <<EMAIL>>" dependencies: hwpe-stream: { git: "https://github.com/pulp-platform/hwpe-stream.git", version: 1.6 } hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.6 } hwpe-ctrl: { git: "https://github.com/pulp-platform/hwpe-ctrl.git", ver...

# Python environment and dependencies to build the documentation name: cocotb-docs dependencies: - python=3.8 - pip # Packages installed from PyPI - pip: - -r requirements.txt

<reponame>flasonil/pulp_cluster # # List of IPs and relative branch/commit-hash/tag. # Uses the YAML syntax. # axi/axi2mem: commit: d704c8beff729476d1dbfd7b60679afa796947d2 domain: [soc, cluster] group: pulp-platform axi/axi2per: commit: tags/v1.0.1 domain: [cluster] group: pulp-platform axi/per2axi: c...

name: CI/VHDLTest on: push: branches: [ master ] pull_request: branches: [ master ] jobs: build: runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v2 - uses: ghdl/setup-ghdl-ci@nightly with: backend: mcode - name: Setup Python uses: act...

title: AHB-Lite Multi-Layer Interconnect Switch description: Parameterised AHB-Lite Multi-layer Interconnect Switch #theme: jekyll-theme-dinky show_downloads: true show_license: true license: Non-Commercial License repository: RoaLogic/ahb3lite_interconnect url: https://roalogic.github.io baseurl: /ahb3lite_intercon...

timer_unit: incdirs: [ rtl, ] files: [ ./rtl/apb_timer_unit.sv, ./rtl/timer_unit.sv, ./rtl/timer_unit_counter.sv, ./rtl/timer_unit_counter_presc.sv, ]

<reponame>hito0512/Vitis-AI name: vitis-ai-pytorch channels: - pytorch - conda-forge - anaconda dependencies: - python=3.6 - pytorch_nndct_cpu - pyyaml - jupyter - ipywidgets - dill - progressbar2 - pytest - scikit-learn - pandas - matplotlib - vaic

<reponame>asb/opentitan # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # An example custom configuration that generates lots of loops (100 # times as many as the default config), but constrains them not to # take too lo...

--- title: Writing efficient code author: - Felix "xq" Queißner date: April 28, 2020 abstract: The SPU Mark II allows one to write very compact and efficient code. In this document, you learn about different tricks on how to do this.

udma_sdio: files: [ rtl/sdio_crc7.sv, rtl/sdio_crc16.sv, rtl/sdio_txrx_cmd.sv, rtl/sdio_txrx_data.sv, rtl/sdio_txrx.sv, rtl/udma_sdio_reg_if.sv, rtl/udma_sdio_top.sv, ]

ePixHr10kT: enable: True ForceWrite: False InitAfterConfig: False EpixHR: enable: True MMCMRegisters: enable: True CLKOUT0PhaseMux: 0 CLKOUT0HighTime: 2 CLKOUT0LowTime: 2 CLKOUT0Frac: 4 CLKOUT0FracEn: 1 CLKOUT0Edge: 0 CLKOUT0NoCount: 0 CLKOUT0DelayTi...

--- name: fft board: boards/red-pitaya version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/latched_mux_v1_0 - fpga/cores/axis_constant_v1_0 - fpga/cores/redp_adc_v1_0 - fpga/cores/redp_dac_v1_0 - fpga/cores/psd_counter_v1...

#this is a example of how ENC ip is used in our yaml PWM_OUT: IP: __PWM_OUT CMD: PWM pha: PIN: A34 DIRECTION: out phb: PIN: A33 DIRECTION: out

<filename>conda-recipe/meta.yaml package: name: lsst_pwr_ctrl_core version: {{ GIT_DESCRIBE_TAG }} source: path: .. build: number: {{ GIT_DESCRIBE_NUMBER|int }} requirements: build: - python - rogue - git - gitpython - numpy run: - python - rogue - numpy abo...

os: linux dist: bionic language: generic env: jobs: - LISP=sbcl - LISP=sbcl32 - LISP=ccl - LISP=ccl32 - LISP=ecl - LISP=allegro - LISP=cmucl # - LISP=abcl jobs: allow_failures: - env: LISP=abcl - env: LISP=allegro - env: LISP=ccl32 - env: LISP=cmucl notifications: ...

<filename>.github/workflows/images.yml name: 'images' on: push: paths: - '.github/workflows/images.yml' - '.github/images.sh' schedule: - cron: '0 0 * * 5' env: DOCKER_BUILDKIT: '1' jobs: build: strategy: fail-fast: false max-parallel: 2 matrix: task: [ ...

<gh_stars>0 package: name: ara authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 } common_cells: { git: "...

<gh_stars>0 # Device description for the Agilent 33250A Function/Arbitrary Waveform Generator. # set_ function expect a parameter, get_ function return a parameter. # Just the very basic commands are imlemented here. identifier : Agilent Technologies,33250A set_burst : BURST:STAT get_burst : BURST:STAT? set_n_bursts :...

<reponame>mithro/hgdb name: Deployment Linux on: push: tags: - '*' jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Checkout submodules 🖥️ shell: bash run: | auth_header="$(git config --local --get http.https://github.com/.extraheader)...

name: i2c_master_top clock_port: wb_clk_i verilog: - i2c_master_bit_ctrl.v - i2c_master_byte_ctrl.v - i2c_master_defines.v - i2c_master_top.v - timescale.v

<gh_stars>10-100 before_install: - sudo apt-get install scala verilator language: scala scala: - 2.12.6 jdk: - openjdk8 script: - make

--- networkRows: 1 networkCols: 1 foxNetworkStages: 1 foxNodeFifos: peToNetwork: 0 networkToPe: 0 resultNodeCoord: x: 0 y: 0 resultNodeFifos: peToNetwork: 0 networkToPe: 0 resultUartFifoDepth: 1024 romNodeCoord: x: 0 y: 0 packetFormat: multicastGroupBits: 1 multicastCoordBits: 1 readyFlagBi...

# TODO: Set number of vectors parameter in python file and testbench from yml name: testbench outputs: - testbench.sv - test_vectors.txt - design.args parameters: testbench_name: GcdUnitTb dut_name: GcdUnit_inst commands: - cp GcdUnitTb.sv outputs/testbench.sv - python3 generate_test_vectors.py - cp...

<filename>hw/ip/otbn/dv/rig/rig/configs/straight-line.yml # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # An custom configuration that doesn't generate any branches, and # increases the weight for BadCallStackRW. The i...

name: Export KiCAD Designs on: #push: # branches: [ main ] # paths: ['circuits/**'] #pull_request: # branches: [ main ] # paths: ['circuits/**'] # Allows you to run this workflow manually from the Actions tab workflow_dispatch: jobs: build: runs-on: ubuntu-latest steps: ...