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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of aut... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; long long quick_pow(long long a, long long b, long long mod) { long long ans = 1, base = a; while (b) { if (b & 1) (ans *= base) %= mod; b >>= 1; (base *= base) %= mod; } return ans; } struct node { int pos, len; bool operat... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 10:33:24
// Design Name:
// Module Name: _2bit_up_counter_with_synch_load_enable_clear_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Descrip... |
#include <bits/stdc++.h> using namespace std; int n, deg[8010], type[8010], in[8010]; long long ans = 0; bool e[8010][8010]; char s[8010]; queue<int> q; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); for (int j = 1; j <= n / 4; j++) { int k = (... |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cx4_datrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// =============================... |
`include "lo_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SS... |
//-----------------------------------------------------------------------------
// system_xillyvga_0_wrapper.v
//-----------------------------------------------------------------------------
module system_xillyvga_0_wrapper
(
S_AXI_ACLK,
S_AXI_ARESETN,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WDATA,
... |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<bool> x; vector<bool> y; x.assign(n + 1, 1); y.assign(n + 1, 1); x[1] = 0; y[1] = 0; x[n] = 0; y[n] = 0; for (int i = 0; i < m; i++) { int tmp_x, tmp_y; scanf( %i %i , &... |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 + 17; int n, A[MAXN], L[7], R[7]; void Solve(int u) { bool st = true; for (int i = 1; i <= n; ++i) if (A[i] != i) st = false; if (st) { cout << u - 1 << n ; for (int i = u - 1; i >= 1; --i) cout << L[i] << <<... |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; struct DDMY { ostringstream o; template <class T> DDMY &operator,(const T &t) { o << t << , ; return *this; } string operator*() { return o.str().substr(0, o.str().size() - 1); } }; template <class T> std... |
// ALU implementation
`include "verilog/riscv_alu_defines.v"
module alu
(
input wire[31:0] opr_a_alu_i,
input wire[31:0] opr_b_alu_i,
input wire[5:0] op_alu_i,
output wire[31:0] res_alu_o,
output wire z_alu_o,
output wire n_alu_o
);
... |
module motor_speed_measurement(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [2:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
... |
// wasca_mm_interconnect_0_avalon_st_adapter_005.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0_avalon_st_adapter_005 #(
parameter inBits... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// synthesis verilog_version verilog_2001
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//------------------------------------------------------... |
#include <bits/stdc++.h> using namespace std; const int lala = 2e9 + 1; int max(int a, int b) { return a > b ? a : b; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; pair<int, int> arr[100005]; int dp[3][100005]; cin >> n; for (int i = 0; i < n; i++) cin >> arr[i].firs... |
#include <bits/stdc++.h> using namespace std; const int bigp = 1000000007; int N, K, ans; int a[105]; int dp[105][105][2]; int main() { scanf( %d , &K); N = 0; while (K > 0) { ++N, a[N] = K % 2, K /= 2; } for (int i = 1; i <= N / 2; i++) swap(a[i], a[N + 1 - i]); memset(dp, 0, ... |
//======================================================================
//
// sha512.v
// --------
// Top level wrapper for the SHA-512 hash function providing
// a simple memory like interface with 32 bit data access.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reser... |
#include <bits/stdc++.h> const long long INF = 2 * 1e9; const long long MOD = 1000000007; using namespace std; void solve() { long long n, k, m; cin >> n >> k >> m; vector<long long> a(n); vector<pair<long long, long long> > c; long long x; cin >> x; c.push_back({x, 1}); long lon... |
#include <bits/stdc++.h> using namespace std; mt19937 rng( (unsigned int)chrono::steady_clock::now().time_since_epoch().count()); const int MAGIC = 239; const int N = 100010; vector<int> g[N]; bool in_st[N]; bool was[N]; bool dfs(int v) { was[v] = true; in_st[v] = true; for (int u : g[... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:33 03/10/2015
// Design Name:
// Module Name: counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Depende... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
//////////////////////////////////////////////////////////////////////////////
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEME... |
#include <bits/stdc++.h> int main() { unsigned long long int n; scanf( %llu , &n); printf( %llu , (n / 2) + 1); } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e6 + 3; long long fastexp(long long a, long long b, long long n) { long long res = 1; while (b) { if (b & 1) res = res * a % n; a = a * a % n; b >>= 1; } return res; } int main() { vector<long long> p(11... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// R... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; const long double pi = acos(-1); const int MOD = 1e9 + 7; int main() { int n; scanf( %d , &n); set<int> tem = {1, 5, 10, 50}; vector<int> v = {1, 5, 10, 50}; if (n == 1)... |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:15:20 11/07/2015
// Design Name: Top_BackBox
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/Transflineal/TOP_Rotation_tst.v
// Project Name: Transflin... |
#include <bits/stdc++.h> using namespace std; const double inf = 1e10; inline int cmp(double x, double y = 0, double tol = 1e-7) { return (x <= y + tol) ? (x + tol < y) ? -1 : 0 : 1; } struct ball { double x, v, m; int id; ball(double x = 0.0, double v = 0.0, double m = 0.0) : x(x), v(v), m(m)... |
#include <bits/stdc++.h> const long long Inf = 1e18; const long double eps = 1e-7; long long LINF = (long long)2e18; using namespace std; long long mod = 1e9 + 7; long long mod5 = 1e9 + 9; long long mod3 = 998244353; long long mod4 = 1000003; long long mod2 = 1e9 + 123; const int MAXN = 4000001; c... |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a... |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_4kx32.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ================... |
#include<bits/stdc++.h> //#include<ext/pb_ds/assoc_container.hpp> //#include<ext/pb_ds/tree_policy.hpp> //#include <ext/pb_ds/trie_policy.hpp> //using namespace __gnu_pbds; using namespace std; #define ll long long int #define ld long double #define mod 1000000007 #define inf ... |
#include <bits/stdc++.h> using namespace std; int n, v[5000]; char a[5000][5050]; bool dfs(int x, int from) { v[x] = 1; for (int y = 0; y < n; y++) if (a[x][y] == 1 ) { if (!v[y]) { if (dfs(y, x)) return true; } else { if (a[y][from] == 1 ) { print... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
m3 m3_inst (.clk(clk));
defparam m3_inst.FROMDEFP = 19;
defparam m... |
#include <bits/stdc++.h> using namespace std; const long long MAX_N = 1e3 + 10, INF = 1e18; long long n, m, k, a[MAX_N][MAX_N], noe[MAX_N]; long long lab[MAX_N], dp[MAX_N][MAX_N]; pair<long long, long long> tar[MAX_N]; void filldp() { dp[m + n - 1][0] = 1; for (int i = m + n - 2; i >= 1; i--) { ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam int CHECKLIST_P [2:0] = '{0, 1... |
#include <bits/stdc++.h> using namespace std; long long rt(long long a) { long long p = 0, q = a; while (p < q) { long long s = (p + q + 1) / 2; long long sv = s * (s + 1) / 2; if (sv < a) p = s; if (sv > a) q = s - 1; if (sv == a) return s; } if (p * (p + 1) / 2 == a) ... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; int weight[n + 1]; int stacked[m + 1]; for (int i = 1; i <= n; i++) { cin >> weight[i]; } for (int i = 1; i <= m; i++) { cin >> stacked[i]; } bool... |
#include <bits/stdc++.h> using namespace std; int main() { int n, b, p; cin >> n >> b >> p; int m = n; long long int nb = 0; while (n > 1) { for (int i = 8; i >= 0; i--) { if (pow(2, i) <= n) { nb += b * pow(2, i) + pow(2, i) / 2; n = n - (pow(2, i)) + pow(2, i)... |
// niosII_system_tristate_conduit_pin_sharer_0.v
// This file was auto-generated from altera_tristate_conduit_pin_sharer_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 12.1sp1 243 at 2017.02.07.14:11:26
`timescale 1 ps / 1 ps
module niosII_system_tristate_conduit_pi... |
#include <bits/stdc++.h> using namespace std; const int MX = 10005; int n, m, x[11], acu[MX], cn[22]; long long sum[MX]; string s[11]; vector<int> res; void main_() { cin >> n >> m; for (int i = 0; i < int(n); i++) cin >> x[i]; for (int i = 0; i < int(n); i++) cin >> s[i]; long long mx = -... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; string bus[7]; bus[0] = +------------------------+ ; bus[1] = |#.#.#.#.#.#.#.#.#.#.#.|D|) ; bus[2] = |#.#.#.#.#.#.#.#.#.#.#.|.| ; bus[3] = |#.......................| ; ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> long double read() { int x; scanf( %d , &x); return x / 1000.0L; } const long double eps = 1e-9, Eps = 1e-7; const int N = 1e5 + 5, V = 4e7 + 5; int n, m, q, rb[N], vol, stc[V]; std::pair<int, int> p[N]; long double k, ox, oy, a[N], b[N], cx[N], cy[N]; long double an... |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const double eps = 1e-6; const int maxn = 1 << 17; int a[maxn]; void merge(int l, int r, int from, int to, int& res) { if (res <= 0 || l + 1 == r) { for (int i = l, j = from; i <= r; i++, j++) a[i]... |
#include <bits/stdc++.h> using namespace std; int main() { int n, z = 0; cin >> n; char *colours = new char[50]; for (int x = 0; x < n; x++) { cin >> colours[x]; } for (int i = 0; i < n - 1; i++) { if (colours[i] == colours[i + 1]) { z++; } } delete[] colour... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; string s; getline(cin >> ws, s); string one = 1 , two = 1 ; int prevOne = 1, prevTwo = 1; for (i... |
#include <bits/stdc++.h> using namespace std; void init() { return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); init(); int n; cin >> n; long long int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } long long int ans = 0ll, prev = 0ll; for (int ... |
module serial_tx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
output tx,
input block,
output busy,
input [7:0] data,
input new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
... |
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
//`define ENABLE_HPS
module DE0_NANO_SOC_ADC(
//////////// ADC //////////
output ADC_CONVST,
output ADC_SCK,
... |
#include <bits/stdc++.h> using namespace std; int n; string a; vector<pair<int, int> > v; void input() { cin >> a; n = a.size(); } void solve() { int i; for (i = 0; i < n; i++) { if (a[i] != a ) { v.push_back(make_pair((a[i] - a ), i)); } } int sz = v.size(); ... |
#include <bits/stdc++.h> using namespace std; long long Pow_Mod(long long a, long long b) { if (b == 0) return 1; long long tmp = Pow_Mod(a, b / 2); tmp = (tmp * tmp) % 1000003; if (b % 2) return (tmp * a) % 1000003; return tmp; } long long C(long long a, long long b) { if (b == 0 || b =... |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int32_t M = 1e9 + 7; const long long N = 1e6 + 5; void no() { cout << 0 0 0 << endl; } void cpc() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(NULL); } void solve() { long long n; cin >> n;... |
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> inline void chmin(A &a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A &a, B b) { if (a < b) a = b; } long long N, M; string S; signed main() { cin >> N >> M >> S; long l... |
#include <bits/stdc++.h> using namespace std; const int MAXN = 405; int a[MAXN], v[MAXN]; int n; void work(int x) { memset(v, 0, sizeof(v)); for (int i = 1; x != 0; i++) { v[i] = x / a[i]; x %= a[i]; } } int work2(int x) { int res = 0; for (int i = 1; x != 0; i++) { r... |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; inline long long int input() { long long int n; cin >> n; return n; } long long int pw(long long int a, long long int b) { return (!b ? 1 : (b & 1 ? a * pw(a * a, b / 2) : pw(a * a, b / 2))); } const long long int MAX... |
#include <bits/stdc++.h> using namespace std; const int MAXN = 101010; pair<int, int> arr[MAXN]; pair<int, int> a[MAXN], b[MAXN]; int N; bool cmp(const pair<int, int> &a, const pair<int, int> &b) { return a.second < b.second; } int main() { ios_base::sync_with_stdio(0); cin >> N; for (in... |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This model counts from 0 to 10. It is instantiated twice in concurrent
// threads to check for race conditions/signal interference.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020-2021 by Andreas Kuster.... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; string s; int a; int x = 0, y = n + 1; for (int i = 0; i < m; i++) { cin >> s; cin >> s; cin >> s; if (s[0] == r ) { cin >> s; cin >> a; if (a > x) x = a; ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns/1ns
// TODO: clean this up. it's pretty old.
module i2c_master
#(parameter LENWIDTH = 4)
( input c, // clock
// user interface
input req,
input [6:0] addr,
input [LENWIDTH-1:0] len, // # of bytes to xfer
input we,
output ack,
output err,
input ... |
#include <bits/stdc++.h> using namespace std; int a, b, n, i, x, y, v; double min1, ans, k; int main() { cin >> a >> b; cin >> n; min1 = 999999; for (i = 1; i <= n; i++) { cin >> x >> y >> v; k = (x - a) * (x - a) + (y - b) * (y - b); ans = sqrt(k) / v; min1 = min(min1, a... |
#include <bits/stdc++.h> using namespace std; const int maxn = 200000 + 1000; char s1[maxn]; char s2[maxn]; int judge(int st1, int en1, int st2, int en2) { int sign = 0; for (int i = st1, j = st2; i <= en1; i++, j++) { if (s1[i] != s2[j]) { sign = 1; break; } } if (... |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const string nl = n ; vector<int> readVector(int n) { vector<int> ret(n); for (int i = 0; i < n; i++) cin >> ret[i]; return ret; } void setIO(string name) { freopen((name + .in ).c_str(), r , stdin); freopen... |
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: IMG_BUFFER.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// =============... |
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int r = n + n - 1; int a = 0; int b = 0; int i; for (i = 0; i < n; i++) { scanf( %d , &a); if (a >= b) { r = r + (a - b); } else { r = r + (b - a); } b = a; } printf( %d , r)... |
#include <bits/stdc++.h> const int inf = 2000000000; using namespace std; vector<vector<int> > g; vector<int> color; vector<bool> on_cycle; vector<int> parent; int n; bool isexit = false; void dfs(int v, int p = -1) { if (isexit) return; color[v] = 1; parent[v] = p; for (int i = 0; i <... |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int INF = 1e9; int a[N], maxv[N << 2], addv[N << 2]; int dmax[N][21]; int n, ans; void maintain(int rt, int l, int r) { maxv[rt] = 0; if (l < r) maxv[rt] = max(maxv[rt << 1], maxv[rt << 1 | 1]); maxv[rt] += addv[rt]; ... |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associate... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
// psl c... |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the 32-bit program counter
module program_counter (next_pc,cur_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// =... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
#include <bits/stdc++.h> using namespace std; long long n, k; int main() { cin >> n >> k; cout << k * (6 * n - 1) << endl; for (int i = 1; i <= n; i++) { int x = (i - 1) * 6 + 1; cout << k * x << << k * (x + 1) << << k * (x + 2) << << k * (x + 4) << endl; } } ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SHA-256 ////
//// Secure Hash Algorithm (SHA-256) testbench ////
//// ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; int main() { int q; scanf( %d , &q); while (q--) { int n; scanf( %d , &n); int cnt = 0; int aa[1000]; for (int i = 1; i <= n; i++) { scanf( %d , &aa[i]); } sort(aa + 1, aa + 1 + n); int flag = 1; ... |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return (a ? gcd(b % a, a) : b); } bool des(int i, int j) { return i > j; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; if (n == 5) cout << 1; else cout <... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> a(n); { for (auto &e : (a)) cin >> e; } sort((a).begin(), (a).end()); vector<int> used(1, a[0]); for (auto e : a) { b... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; const int MN = 70010; vector<int> vs[MN]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<string> vs(n); for (int i = 0; i < n; i++) cin >> vs[i]; vector<string> ans(n); for (int len = 1; len < 10; l... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
* Stack
*
* (c) 2017 - Jesús Leganés-Combarro 'piranna' <>
*
* Based on https://github.com/whitequark/bfcpu2/blob/master/verilog/Stack.v
*/
`include "stack.vh"
`default_nettype none
module stack
#(
parameter WIDTH = 8, // bits
parameter DEPTH = 3 // frames (exponential)
)
(
input clk,
input rese... |
#include <bits/stdc++.h> using namespace std; int a[105][105]; int main() { vector<int> v; int n; cin >> n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) cin >> a[i][j]; v.push_back(i); } int cnt = 0; for (int i = 1; i <= n; i++) { int flag = 0; fo... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/28/2016 08:42:24 AM
// Design Name:
// Module Name: Testbench_FPU_multiplication
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dep... |
module counter_26bit (En, Clk, Clr, Q);
input En, Clk, Clr;
output [25:0] Q;
wire [25:0] T, Qs;
t_flipflop T0 (En, Clk, Clr, Qs[0]);
assign T[0] = En & Qs[0];
t_flipflop T1 (T[0], Clk, Clr, Qs[1]);
assign T[1] = T[0] & Qs[1];
t_flipflop T2 (T[1], Clk, Clr, Qs[2]);
assign T[2] = T[1] & Qs[2];
t_... |
`timescale 1ns / 1ps
module testbench;
//Inputs
reg mips_clk;
reg mips_rst;
reg [15:0] sw;
//Outputs
wire [15:0] led;
// SPI ports
reg sdo;
wire sck;
wire cs;
// SPI Test
reg [15:0] test_input = 16'b0001111011100000;
reg [3:0] ... |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:... |
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