text stringlengths 59 71.4k |
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1... |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ff_10x1024_fwft_async.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// =================================... |
#include <bits/stdc++.h> inline int in(); inline void wr(int); inline int gcd(int, int); int main(int argc, char** argv) { register int T = in(); while (T--) { register int p1 = in(), p2 = in(), k = in(); if (p1 > p2) p1 ^= p2 ^= p1 ^= p2; if (k == 1) { puts( REBEL ); c... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
//---------------------------------------------------------------------//
// Name: addrgen.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Generates addresses.
//---------------------------------------------------------------------//
module addrdecode(
clk,
addr_in,
bank0_addr,
bank1_addr... |
#include <bits/stdc++.h> using namespace std; int A[10000][2]; int main() { int N, M, K; cin >> N >> M >> K; int cur = 0; for (int i = 0; i < M; i++) for (int j = (i + 1); j < M; j++) { A[cur][K] = i + 1; A[cur][1 - K] = j + 1; cur++; } cout << cur << endl; ... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n, k; string x; cin >> n >> k >> x; string ans = ; int o = -1; for (int i = 1; i < x.size(); i++) { if (x.substr(i, x.size() - i) == x.substr(0, x.size(... |
#include <bits/stdc++.h> using namespace std; const int maxn = 55, maxm = 9; int loc[maxn][2], col[maxn]; char s[maxn][maxn], res[maxn][maxn]; int num[maxn][maxn], used[maxm][maxm]; int n, m, ans, cnt; void dfs(int u, int v) { int i, j, x, y; if (u > 14) { memset(used, 0, sizeof used); ... |
#include <bits/stdc++.h> using namespace std; const int MAX = 510; int n, m; double xa, ya, x2, y2; double v, vx1, vx2, vy1, vy2, t; int check(double k) { double x, y; x = xa + vx1 * min(k, t) + vx2 * max(0.0, k - t); y = ya + vy1 * min(k, t) + vy2 * max(0.0, k - t); double dist = sqrt((x - ... |
//////////////////////////////////////////////////////////////////////////////////
// d_BCH_SC_X.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Co... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
#include <bits/stdc++.h> using namespace std; int rdn() { int ret = 0; bool fx = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) fx = 0; ch = getchar(); } while (ch >= 0 && ch <= 9 ) ret = ret * 10 + ch - 0 , ch = getchar(); return fx ? ret : -ret; ... |
#include <bits/stdc++.h> using namespace std; const int maxn = 2.7e5 + 5; int m, n, k; int mod; int f[19][maxn]; vector<long long> g; int cnt[maxn]; int upd(const int &x) { if (x < 0) return x + mod; if (x >= mod) return x - mod; return x; } void add(int &x, const int &y) { x = upd(x + y... |
// dtb.v
module dtb
(
// where to connect ???
input reset_n,
input clkin_125,
// --- EPCS
output EPCS_DCLK,
output EPCS_nCSO,
output EPCS_ASDO,
input EPCS_DATA0,
// --- 40 MHz clock oscillator input
input clk40,
// --- ROC control
output Chip_HV, // High Voltage on
ou... |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 + 7, MAX_SUM = 10 * 1000 + 7, DELTA = 1000 * 1000 * 1000 + 7; long long inputArray[MAXN], numberOfSubarrays[MAXN][2 * MAX_SUM], PSum; int main() { int numberOfInput; cin >> numberOfInput; for (int i = 0; i < numberOfInpu... |
#include <bits/stdc++.h> using namespace std; vector<int> v; vector<int> primes; bool flag[100005]; bool flag2[100005]; void sieve(int n) { for (int i = 2; i <= n; i++) { if (!flag2[i]) { primes.push_back(i); for (int j = 2 * i; j <= n; j += i) { flag2[j] = true; ... |
//----------------------------------------------------------------------------
//-- Prueba de tranmision 1. Se transmite el caracter "K" con cada flanco de
//-- subida en la señal DTR. De esta forma controlamos la transmision desde
//-- el PC
//---------------------------------------------------------------------------... |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100050; int item[MAXN]; int main() { int dcnt; while (scanf( %d , &dcnt) == 1) { int discount = MAXN; for (int i = 0; i < dcnt; i++) { int tmp; scanf( %d , &tmp); discount = min(discount, tmp); } ... |
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulati... |
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulati... |
#include <bits/stdc++.h> template <class T_T> T_T gcd(T_T a, T_T b) { return b ? gcd(b, a % b) : a; } template <class T_T> T_T f_max(T_T a, T_T b) { return a > b ? a : b; } using namespace std; const int N = 100000; int a[105][105], r[105], c[105], cnt_r[105], cnt_c[105], ans; int main() { ... |
#include <bits/stdc++.h> using namespace std; long long n, m, i, j, k, it, t; long long r[101], rr[101], c[101], cc[101]; long long a[101][101]; long long R, C, x; vector<long long> ans, ans2; int main() { cin >> n >> m; int k = 1; x = 3; while (n != 0) { if (n % 2 == 1) { k ... |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long n, k; cin >> n >> k; long long ans = 0; for (int i = (int)0; i < (int)n; ++i) { long long l, r; cin >> l >> r; ans += r - l + 1; } int ted = 0; while (ans % k) { ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; struct SCIENT { int index; int k; int inv; long long a[200009]; } sc[3]; vector<pair<int, int> > v; int K[3]; int dynam[2100][2100][3]; int recurse(int k1, int k2, int which) { int last; if (k1 == K[1] && k2 == K[2]) last = INT_MI... |
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int LG_N = 20; struct node { int l, r, cnt; node *left, *right; node(int _l, int _r, int _c = 0) : l(_l), r(_r), cnt(_c) {} }; node *init(int l, int r) { node *p = new node(l, r); if (l < r) { int mid = (l + ... |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... |
#include <bits/stdc++.h> int n; char a[1000005], b[1000005], dic[130]; int main() { dic[ W ] = E ; dic[ E ] = W ; dic[ N ] = S ; dic[ S ] = N ; scanf( %d%s%s , &n, a, b); unsigned int ha = 0, hb = 0, rol = 1, mul = 233; for (int i = n - 2; i >= 0; i--) { if ((ha = a[i] * rol ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to test... |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int score = 0; string str; cin >> str; for (int j = 0; j < str.size(); ++j) { if (str[j] == A ) score += 1; if (str[j] == D ) { score -= 1; } } if (score > 0) cout << Anton ; ... |
module modexp_test_1_N();
parameter N = 8;
parameter CC = N;
reg clk;
reg rst1;
reg rst2;
reg [N-1:0] m;
reg [N-1:0] e;
reg [N-1:0] d;
reg [N-1:0] n;
wire [N-1:0] c;
reg [N-1:0] creg;
wire [N-1:0] mout;
function [N-1:0] modexp_f;
input [N-1:0] m;
input [N-1:0] e;
input [N-1:0] n;
... |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*... |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; const long double PI = 3.1415926535897932384626433832795; const long double EPS = 1e-11; int n; set<string> st; string s, ts; map<string, int> mapp; string tos(signed long long i) { string s = ; while (i > 0) { s = char(i % 10 + 0 ) + s; ... |
// -*- Mode: Verilog -*-
// Filename : uart_tasks.v
// Description : UART Tasks
// Author : Philip Tracton
// Created On : Mon Apr 20 16:12:43 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:12:43 2015
// Update Count : 0
// Status ... |
#include <bits/stdc++.h> using namespace std; int arr[10001]; int main() { int test; cin >> test; while (test--) { int n; cin >> n; vector<int> ans1, ans2; for (int i = 0; i < 2 * n; i++) cin >> arr[i]; vector<pair<int, int> > vp; for (int i = 0; i < 2 * n; i++) { ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// counters
int cnt;
int cnt_bit ;
int cnt_byte;
int cnt_int ;
int cnt_ar1d;
... |
#include <bits/stdc++.h> using namespace std; int main() { int n, dd, q; cin >> n >> dd >> q; int arr[200001]; for (int i = 0; i < 200001; i++) { arr[i] = 0; } for (int h = 0; h < n; h++) { int t1, t2; cin >> t1 >> t2; arr[t1]++; arr[t2 + 1]--; } int cou... |
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; bool prime[2000005]; vector<int> myarr; void myprime(int n) { for (long int i = 0; i < n; i++) prime[i] = true; for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[... |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_... |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 100; int n, sl, res; int c[maxn][27]; int d[maxn][2], trace[maxn]; vector<int> a[maxn]; vector<string> q; void init() { q.clear(); for (int i = 1; i <= sl; i++) { for (int j = 0; j < 26; j++) { c[i][j] = 0; ... |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocmc.v
*
* Date : 2012-11
*
* Description : Controller for OCM model
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ocmc(
rstn... |
//-------------------------------------------------------------------
//-- romnotes_tb.v
//-- Banco de pruebas para el reproductor de melodias
//-------------------------------------------------------------------
//-- BQ October 2015. Written by Juan Gonzalez (Obijuan)
//------------------------------------------------... |
#include <bits/stdc++.h> using namespace std; const int N = 400010; vector<int> g[N]; int pos[N], to[N]; int kw = 0, w[N]; void dfs(int v, int pr) { pos[v] = kw; w[kw++] = v; for (int j = 0; j < (int)g[v].size(); j++) { int u = g[v][j]; if (u != pr) { dfs(u, v); } }... |
#include <bits/stdc++.h> using namespace std; vector<int> a[100010], dp[100010]; int len[100010]; int main() { int n, m, i, j, k, l, r; while (~scanf( %d%d , &n, &m)) { for (i = 1; i <= n; i++) { a[i].resize(m + 1); for (j = 1; j <= m; j++) scanf( %d , &a[i][j]); } mems... |
//---------------------------------------------------------------------------------------
// uart receive module
//
//---------------------------------------------------------------------------------------
module uart_rx
(
clock, reset,
ce_16, ser_in,
rx_data, new_rx_data
);
//----------------------... |
#include <bits/stdc++.h> using namespace std; const int n = 10000000; bitset<n> b; vector<int> v; void sieve() { b.set(); b[0] = 0; b[1] = 0; for (long long i = 2; i <= n; i++) { if (b[i]) { v.push_back(i); for (long long j = i * i; j <= n; j = j + i) { b[j] = 0... |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, flag = 1; char ch = 0; while (!isdigit(ch)) { ch = getchar(); if (ch == - ) flag = -1; } while (isdigit(ch)) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x ... |
// amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module amm_master_qsys_with_pcie_mm_interconnect_0... |
#include <bits/stdc++.h> using namespace std; void solve() { pair<int, int> A[50007]; int n; cin >> n; for (int i = 0; i < (n); i++) cin >> A[i].first >> A[i].second; sort(A, A + n); int r1 = A[0].first, r2 = A[0].second; int r3, r4; for (int i = 1; i < n; i++) { if (A[i].first... |
#include <bits/stdc++.h> using namespace std; int main() { double n, m, a[1001], b[1001], litri = 0, ok = 1; cin >> n >> m; double copie = m; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; litri = m / (b[1] - 1); for (int i = n; i >= 1; i--) { m... |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed... |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:23:18 05/16/2016
// Design Name: controlador_teclado_ps2
// Module Name: C:/Users/Jafet/Documents/Proyectos Dis.Sist.Digitales/III_Proyecto_Laboratorio_Sistemas_Di... |
`include "constants.vh"
`default_nettype none
module btb(
input wire clk,
input wire reset,
input wire [`ADDR_LEN-1:0] pc,
output wire hit,
output wire [`ADDR_LEN-1:0] jmpaddr,
input wire we,
input wire [`ADDR_LEN-1:0] jmpsrc,
input wire [`ADDR_LEN-1... |
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module dc_download(//input
clk,
rst,
IN_flit_dc,
v_IN_flit_dc,
In_flit_ctrl_dc,
dc_done_access,
//output
v_dc_downlo... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; int answer = 1; while (k % 2 == 0) { k /= 2; answer++; } cout << answer; return 0; } |
#include <bits/stdc++.h> std::vector<int> ReadVector(size_t size) { std::vector<int> vector(size); for (auto& element : vector) { std::cin >> element; } return vector; } bool is_pal(const std::string& a) { for (size_t i = 0; i < a.size() / 2; ++i) { if (a[i] != a[a.size() - i - 1])... |
#include<bits/stdc++.h> using namespace std; const int N=500; int n,mod,xn[N]; long long dp[N*N]; #define id(x,y) *(xn+x)+y int main(){ cin>>n>>mod; dp[id(1,1)]=1; for(int i=2;i<=n;++i) xn[i]=xn[i-1]+n; xn[n+2]=(xn[n+1]=xn[n]+n)+n; for(int i=1;i<n;i++){ long long a=(dp[id(i,... |
/*
eTeak synthesiser for the Balsa language
Copyright (C) 2012- The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option)... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; long long a, b[1001], c, cnt1, cnt2, d, n, m; string s; int main() { cin >> a; if (a == 1) { cout << 1; return 0; } for (int i = 1; i <= a; i++) { cin >> b[i]; c += b[i]; } sort(b + 1, b + a + 1); reverse(b + 1, b ... |
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / ... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
... |
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module master_0_p2b_adapter (
// Interface: clk
input c... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:45:40 05/24/2015
// Design Name:
// Module Name: binary_to_BCD_fourteen_bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// D... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 1005; int main() { long long n; while (~scanf( %I64d , &n)) printf( 25 n ); return 0; } |
#include<bits/stdc++.h> using namespace std; using ll = long long; const ll nax = 1e5 + 69; int n; vector<ll>possible; void fun(ll *a,int l,int r,ll *pref){ if(l>r || l<0 || r>n) return; possible.push_back(pref[r+1]-pref[l]); if(a[r]==a[l]) return; int mid = (a[l] + a[r])/2; int ind =... |
#include <bits/stdc++.h> using namespace std; const int Z = (int)1e5 + 111; const int INF = (int)1e9 * 2 + 111; int n, m, k; bool can(long long x) { int u = k; int one = x, two = max(x - k + 1, (long long)1); long long p = ((long long)one + two) * ((long long)one - two + 1) / 2; p += (long lon... |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) #pragma GCC target( avx,avx2 ) using namespace std; long long mod = 1e9 + 7; const long long inf = 1e9; int main() { cin.tie(0), cout.tie(0), ios_base::sync_with_stdio(0); in... |
#include <bits/stdc++.h> using namespace std; long long powmod(long long a, long long b, long long MOD) { long long res = 1; a %= MOD; for (; b; b >>= 1) { if (b & 1) res = res * a % MOD; a = a * a % MOD; } return res; } const int N = 1e5 + 5; int a[N]; map<long long, int> m;... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:36:52 02/22/2015
// Design Name:
// Module Name: SpecialMult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dep... |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 01/12/09 revision
////////////////////////////... |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int _inf = 0xc0c0c0c0; const long long INF = 0x3f3f3f3f3f3f3f3f; const long long _INF = 0xc0c0c0c0c0c0c0c0; const long long mod = (int)1e9 + 7; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long l... |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000ll * 1000 * 1000 + 7; int main() { vector<string> name; string str; int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> str; name.push_back(str); } long long ans = 1ll; for (int i = 0; i <... |
`timescale 1ns / 1ps
/*
* File : IFID_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Ma... |
//==================================================================================================
// Filename : antares_multiplier.v
// Created On : Wed Sep 2 22:05:36 2015
// Last Modified : Sat Nov 07 12:11:51 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universid... |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> struct seg_tree_lazy { int S, H; T zero; std::vector<T> value; U noop; std::vector<bool> dirty; std::vector<U> prop; seg_tree_lazy<T, U>(int _S, T _zero = T(), U _noop = U()); void set_leaves(std::vecto... |
#include <bits/stdc++.h> using namespace std; int n, t; int visited[30009]; bool ok = false; vector<int> C[30009]; void dfs(int u) { if (u == t) { ok = true; return; } visited[u] = 1; if (C[u].size()) for (int i = 0; i <= C[u].size() - 1; i++) { int v = C[u][i]; ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
typedef e... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string cad1; string cad2; cin >> cad1 >> cad2; if (cad1 == cad2) { cout << YES ; } else { if (cad1.size() != cad2.size()) { cout << NO ; } els... |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulati... |
#include <bits/stdc++.h> using namespace std; const int N = 1e6; int L[N], R[N], sp[N], levsp[30], lev[N]; long long val[N], a[N]; void lazyUpdate(int node) { if (!L[node]) return; if (sp[node] ^ levsp[lev[node]]) { swap(L[node], R[node]); sp[node] ^= 1; } } long long build(int nod... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; int f(long long x) { long long i, j, cnt = 0; for (i = 1; i <= x; i *= 2) { for (j = i; j <= x; j *= 3) cnt++; } return cnt; } int main() { int l, r; cin >> l >> r; cout << f(r) - f(l - 1); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
/... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg [2:0] xor3;
reg [1:0] xor2;
reg [0:0] xor1;
reg [2:0] ma, mb;
... |
#include <bits/stdc++.h> using namespace std; const int LIM = 5e+5 + 10; int sz[LIM]; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; ++i) cin >> sz[i]; sort(sz, sz + n); int pairs = 0; int l = 0; int lb = n / 2 + (n % 2); int r = lb; ... |
#include <bits/stdc++.h> using namespace std; inline long long getnum() { char c = getchar(); long long num, sign = 1; for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) sign = -1; for (num = 0; c >= 0 && c <= 9 ;) { c -= 0 ; num = num * 10 + c; c = getchar(); } ... |
#include <bits/stdc++.h> using namespace std; const int N = 5010; struct T { int a, b, i; T() {} T(int a, int b, int i) : a(a), b(b), i(i) {} bool operator<(const T &other) const { return a > other.a; } }; const int inf = 1e9; int n, m, k, dp[N][N], f[N][N]; T a[N]; vector<int> ga, gb; ... |
#include <bits/stdc++.h> using namespace std; vector<long long> usedTrains; vector<vector<pair<long long, long long>>> gNoTrain; vector<vector<pair<long long, long long>>> gYesTrain; vector<long long> disNoTrain; vector<long long> disYesTrain; unordered_set<long long> tracks; void no_train_dijkstra(int ... |
`ifndef PIPELINE_DEF
`include "../define.v"
`endif
module ID_EX(
input clk,
input rst,
input is_hold,
// info input
input[`RegDataWidth-1:0] rdata_1_ID,
input[`RegDataWidth-1:0] rdata_2_ID,
input[`RegAddrWidth-1:0] raddr_1_ID,
input[`RegAddrWidth-1:0] raddr_2_ID,
input[`RegDat... |
#include <bits/stdc++.h> using namespace std; int n, x, y, d, T; int main() { cin >> T; while (T--) { cin >> n >> x >> y >> d; int sum; if ((abs(y - x)) % d == 0 || (n - y) % d == 0 || (y - 1) % d == 0) { if ((abs(y - x)) % d == 0) sum = (abs(y - x)) / d; else {... |
module FpuFpD_Add(
/* verilator lint_off UNUSED */
clk,
enable,
doSub,
srca,
srcb,
dst
);
input clk;
input enable;
input doSub;
input[63:0] srca;
input[63:0] srcb;
output[63:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[12:0] exa;
reg[12:0] exb;
reg[12:0] exc;
reg[12:0] exm;
reg[63:0] tFracA;
reg[63:0] t... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
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