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#include <bits/stdc++.h> #pragma comment(linker, /STACK:10000000 ) using namespace std; template <class T> T inline sqr(T x) { return x * x; } const double pi = 3.1415926535897932384626433832795; const double eps = 1e-8; long long ans = 0; bool f(long long x, long long y, long long n) { long ... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
#include <bits/stdc++.h> using namespace std; int n, k; int arr[1000008]; int l[1000008]; int mx[1000008 << 2], lazy[1000008 << 2]; void pushup(int rt) { mx[rt] = max(mx[rt << 1], mx[rt << 1 | 1]); } void build(int rt, int l, int r) { if (l > r) return; if (l == r) { mx[l] = arr[l]; re... |
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vi>; using vll = vector<ll>; using vvll = vector<vll>; using vb = vector<bool>; using vd = vector<double>; using vs = vector<string>; using pii = pair<int, int>; using pll = pair<ll, ll>;... |
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream &operator>>(istream &in, pair<T1, T2> &a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream &operator<<(ostream &out, pair<T1, T2> a) { out << a.first << << a.second;... |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n; cin >> n; vector<long long> sc(n); for (typeof(n) i = (0); i < (n); i++) cin >> sc[i]; int m; cin >> m; for (typeof(m) i = (0); i < (m); i++) { long long w, h; cin >> w >> h; ... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode = 0;
// verilator lint_off LITENDIAN
reg [7:0] mem_narrow... |
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
in... |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx ... |
#include <bits/stdc++.h> using namespace std; long long n; int resp; int ask(long long x) { printf( ? %lld n , x); fflush(stdout); scanf( %d , &resp); return resp; } void ans(long long x) { printf( = %lld n , x); fflush(stdout); } void solve() { scanf( %lld , &n); if (n =... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; long long t; cin >> t; while (t--) { long long n, m; cin >> n >> m; string s; cin >> s; vector<long long> p(m), arr(26, 0); vector... |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: dma_engine_pci_xfer.v
// Project: CPCI (PCI Control FPGA)
// Description: PCI interface for DMA engine
//
// Note: read and write are from the perspective of the driver.
... |
#include <bits/stdc++.h> using namespace std; long long w[2], b[2], q[2], mod = 998244353, fac[100001]; long long modpow(long long b, long long p) { long long ret = 1; while (p > 0) { if (p & 1) ret = ret * b % mod; b = b * b % mod; p >>= 1; } return ret; } long long choose(l... |
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* ... |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License... |
`include "sata_defines.v"
module sata_platform (
input rst,
input tx_comm_reset,
input tx_comm_wake,
output comm_init_detect,
output comm_wake_detect,
output rx_elec_idle,
input tx_elec_idle,
o... |
#include <bits/stdc++.h> using namespace std; long long a[15], y, k2, k3, r1, z, k4, r, max1, k5, k1, min1, b[1005], n1, n, m, k, i, j; vector<char> f; int main() { string s, s1; cin >> k >> n; cin >> s; for (i = 0; i < n; i++) { for (j = 0; j < 10; j++) a[j] = 0; cin >> k1 >> ... |
module cla32(a, b, ci, s, co);
input [31:0] a, b;
input ci;
output [31:0] s;
output co;
wire g_out, p_out;
cla_32 cla(a, b, ci, g_out, p_out, s);
assign co = g_out | p_out & ci;
endmodule
module cla_32(a, b, c_in, g_out, p_out, s);
input [31:0] a, b;
input c_in;
output g_out, p_out;
output [3... |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual prope... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> using namespace std; string tsize[] = { S , M , L , XL , XXL }; int a[6]; int main() { int n = 5; for (int i = 0; i < 5; i++) { cin >> a[i]; } int m; cin >> m; for (int k = 0; k < m; k++) { string tshirt; cin >> tshirt; int tcode = 0; ... |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... |
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// DRAM controller. performs accesses to DRAM.
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
... |
module RMON_dpram(
Reset ,
Clk ,
//port-a for Rmon
Addra,
Dina,
Douta,
Wea,
//port-b for CPU
Addrb,
Doutb
);
input Reset ;
input Clk ;
//port-a for Rmon
input [5:0] Addra;
input ... |
#include <bits/stdc++.h> using namespace std; int n; double x, y, ans; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> x >> y; ans = (ans * (i - 1) + y) / i; } ans += 5; printf( %.3lf , ans); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC RAMs ////
//// ////
//// This file is part of the Open... |
#include <bits/stdc++.h> using namespace std; set<int> s; map<int, int> mm; int a[500005]; int main() { int n, m, d; cin >> n >> m >> d; for (int i = 0; i < n; i++) { int k; cin >> k; s.insert(k); a[i] = k; } set<int>::iterator it1, it2, it3; int sum = 0; fo... |
module FULL_ADDER (
input wire wA,wB,wCi,
output wire wR ,
output wire wCo
);
assign {wCo,wR} = wA + wB + wCi;
endmodule
module gIMUL # (parameter SIZE = 8)(
input wire [SIZE-1:0] A,B,
output wire [(2*SIZE)-1:0] R
);
wire[(SIZE-1):0] wCarry[(SIZE-1):0];
wire [(SIZE-2):0] wResult[(SIZE-1):0];
wire [(SIZE-2):0] wIn... |
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_eng312_proj3.v
Design Description: Verilog Module that uses the following modules to operate: nsCounter, ewCounter, yellowCounter
... |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int len = 0, x, pre; long long ans = 0LL; for (int i = 0; i < n; i++) { scanf( %d , &x); if (i != 0) { if (pre == x) { len++; } else { ans += 1LL * (len + 1) * len /... |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a, b, k; cin >> n >> a >> b >> k; long long int skips_left = k; long long int win = 0; long long int h[n]; long long int skips_req[n]; for (long long int m = 0; m < n; m++) { skips_req[m] = 0; } for... |
#include <bits/stdc++.h> using namespace std; long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = 10 * x + ch - 0 ; ch = getchar(); } return x... |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if (n == k) { cout << -1; return 0; } int q = n - k; int a[n]; for (int i = 0; i < n; i++) a[i] = i + 1; if (!(q % 2)) { swap(a[0], a[n - 1]); q--; } for (int i = 1; i ... |
/**
File: controlers_ifaces_lib.v
Abstract: Контролирующая часть интерфейса эстафетной передачи.
*/
/**
Abstract:
Notes job:
- получает импульс, покрывающий первый элемент
потока данных
- вырабатывает окно работы блока
- и импульс покр. первый элем. получ. данных
Feature: Выходной сиг... |
#include <bits/stdc++.h> using namespace std; int T, n; int a[200010]; int sum; int ans[200010]; map<int, vector<pair<int, int> > > o; int exgcd(int a, int b, int &x, int &y) { if (!b) { x = 1, y = 0; return a; } int t = exgcd(b, a % b, y, x); y -= a / b * x; return t; } ... |
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
#include <bits/stdc++.h> const int MAX_N = 102; using namespace std; string s; int dp[52][11]; long long numberOfways(int i, int digit) { if (i == s.length()) return 1; if (dp[i][digit] != -1) return dp[i][digit]; dp[i][digit] = 0; int curDigit = s[i] - 0 ; int newDigit = curDigit + digit... |
#include <bits/stdc++.h> using namespace std; int main() { int q, n, sum, a; cin >> q; while (q--) { sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a; sum += a; } cout << (sum + n - 1) / n << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int a[N]; int n; int res[N]; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a * b / gcd(a, b); } void solve() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } if (n... |
`timescale 1ns / 1ps
module dmix_t;
// ins
reg rst;
reg signal;
parameter TclkSPDIF = 40; // 24.576MHz == 192Khz * 32 bit * 2 (biphase)
dmix_top uut(.rst(rst), .spdif_i(signal));
task recv_rawbit;
input wire b;
begin
signal = b;
#(TclkSPDIF);//*6);
end
endtask
task recv_B;
begin
... |
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) inpu... |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long ext_gcd(long long a, long long b, long long& x, long long& y) { long long t, ret; if (!b) { x = 1, y = 0; return a; } ret = ext_gcd(b, a % b, x, y); t =... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`include "hglobal.v"
`default_nettype none
module pakin
#(parameter
PSZ=`NS_PACKET_SIZE,
FSZ=`NS_PACKOUT_FSZ,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
`NS_DECLARE_GLB_CHNL(gch),
`NS_DECLARE_OUT_CHNL(snd0),
`NS_DECLARE_PAKIN_CHNL(rcv0)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
par... |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of ... |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// ... |
#include <bits/stdc++.h> using namespace std; constexpr long double pi{3.1415926535897932384}; constexpr long long mod{1000000007}; long long power(long long x, long long y) { long long res = 1; x = x % mod; while (y > 0) { if (y & 1) res = (res * x) % mod; y = y >> 1; x = (x * x) ... |
#include <bits/stdc++.h> using namespace std; long long gen(int order) { long long sum = 0; while (order != 0) { sum = (sum * 10) + 9; order--; } return sum; } int main() { long long l, r; cin >> l >> r; long long p = l, k = r; int order = 0, sorder = 0; while (k ... |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int MAX = 2e5 + 5; const long long MAX2 = 11; const int MOD = 1000000000 + 7; const long long INF = 20000; const int dr[] = {1, 0, -1, 0, 1, 1, -1, -1}; const int dc[] = {0, 1, 0, -1, 1, -1, 1, -1}; const double pi = acos(-... |
#include <bits/stdc++.h> int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); if (n == 1 || n == 2 || n == 4) { printf( -1 n ); continue; } if (!(n % 3)) printf( %d %d %d n , (n / 3), 0, 0); else if (n % 3 == 1) prin... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////////
module arduino_switch_digital_uart_bit(
// configuration
input gpio_sel, // 0=digital I/O, 1= uart
// Shield connector side
... |
#include <bits/stdc++.h> using namespace std; const int MD = 1000000007; inline void add(int &a, const int b) { a += b; if (a >= MD) a %= MD; } inline int mul(const int &a, const int &b) { long long r = 1ll * a * b; if (r >= MD) r %= MD; return r; } int a[9], n, k; bool vis[9]; boo... |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, x, y, i, s = 0, k = 0; vector<pair<long long int, long long int> > v; cin >> n >> m; for (i = 0; i < m; i++) { cin >> x >> y; v.push_back(make_pair(y, x)); } sort(v.begin(), v.end()); for (i = v.si... |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of... |
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> c; vector<bool> used; vector<vector<int> > e; vector<vector<int> > ices; int colors = 1; int cur = 1; int used_colors[1000000]; void dfs(int v) { if (used[v]) return; used[v] = 1; if (ices[v].size() > colors) { col... |
module erx (/*AUTOARG*/
// Outputs
rx_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
rxrr_access, rxrr_packet, erx_cfg_wait, rx_lclk_div4, erx_nreset,
mailbox_irq,
// Inputs
soft_reset, sys_nreset, sys_clk, tx_active, rxi_lclk... |
#include <bits/stdc++.h> using namespace std; int main() { int m, n; cin >> m >> n; double ans = m; double i = 1; while (1) { if (i >= m) break; double j = (m - i) / m; double k = 1; int q = n; while (q != 0) { if (q & 1 == 1) k *= j; q = q >> 1; ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
File: e_tx_protocol.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation,... |
// $Id: c_add_nto1.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of sou... |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007, dx[] = {0, 1, 0, -1}, dy[] = {1, 0, -1, 0}; const double eps = 1e-8; void read(int &k) { k = 0; char x = getchar(); while (x < 0 || x > 9 ) x = getchar(); while (x >= 0 && x <= 9 ) { k = k * 10 - 48 + x; ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
reg [2:0] value;
reg [31:0] rglobal;
reg [31:0] vec [1:0];
reg [31:0] n;
initial... |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distri... |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) an... |
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual proper... |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base... |
#include <bits/stdc++.h> using namespace std; int sz[100005]; long long pw[100005]; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; sz[a]++; sz[b]++; } int lf = 0; for (int i = 1; i <= ... |
#include <bits/stdc++.h> int main() { int n, start; char str[60]; scanf( %s , str); n = strlen(str); n = n % 2 ? n / 2 : n / 2 - 1; printf( %c , str[n]); for (int i = 1; i <= n; i++) printf( %c%c , str[n + i], str[n - i]); if (strlen(str) % 2 == 0 && strlen(str) > 1) printf( %c ,... |
#include <bits/stdc++.h> using namespace std; void FastInputOutput() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { int n, temp; map<int, int> idx; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &temp); idx[temp] = i; } int q... |
#include <bits/stdc++.h> using namespace std; long long x, y; int n; pair<long long, long long> a[200001]; vector<long long> numbers; map<long long, int> matchs; long long matchsReverse[400001]; int increase[400001]; int decrease[400001]; long long answer[400001]; int main() { cin >> n; fo... |
#include <bits/stdc++.h> using namespace std; struct Node { int s, e, d; }; int a[1010]; int in[1010]; int out[1010]; int vis[1010]; int d[1010][1010]; int n, p; int cnt = 0; int ans; Node node[1010]; void dfs(int x) { if (!out[x]) { node[cnt].e = x; node[cnt].d = ans; ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
data_out,
// Inputs
wr, wa, rst_l, rd, ra, data_in, clk
);
input clk;
/*AUTOINPUT*/
// Beginning of au... |
#include <bits/stdc++.h> using namespace std; long long ans[1000005]; long long n; struct cht { vector<pair<long long, long long> > v; long long pt = 0; long long val(long long pos, long long x) { return v[pos].first * x + v[pos].second; } bool lmao(pair<long long, long long> p0, pair<... |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: pci2net_dma_16x32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ==============================... |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_wr_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Writes between AFI and DDRC/OCM
*
*****************************************************************************/
module p... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////////////////////////////
// Company: Universidad de Costa Rica
// Engineer: jOSHUA tORRES mORALES (A76478)
//
// Create Date: 15:41:50 09/06/2015
// Design Name:
// Module Name: Fifo_Lifo
// Project Name:
... |
#include <bits/stdc++.h> using namespace std; int main() { long long H, L; scanf( %lld%lld , &H, &L); printf( %f , 0.5 * (L * L - H * H) / H); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAX = 101; long long mat[MAX][MAX], ans[MAX][MAX], arr1[MAX], arr2[MAX]; int main() { long long n, m, h; cin >> n >> m >> h; for (long long i = 0; i < m; i++) cin >> arr2[i]; for (long long i = 0; i < n; i++) cin >> arr1[i]; for (... |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin.tie(0); cout.tie(0); int n; cin >> n; int arr[n]; for (auto& elem : arr) { cin >> elem; } for (int i = 1; i <= n; ++i) { for (int j = 0; j < n; ++j) { ... |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire G... |
#include <bits/stdc++.h> using namespace std; const int N = 2e5; const int P = 1e9 + 7; char s[N + 10]; int dp[N + 10][4]; int main() { int n; cin >> n >> (s + 1); dp[0][0] = 1; for (int i = 1; i <= n; i++) { if (s[i] != ? ) { memcpy(dp[i], dp[i - 1], sizeof(dp[i])); (... |
#include <bits/stdc++.h> #pragma gcc optimize(o3) using namespace std; long long qpow(long long x, long long y) { return y ? (y & 1 ? x * qpow(x, y - 1) % 1000000007 : qpow(x * x % 1000000007, y / 2)) : 1; } template <typename T> inline void read(T& x) { x = 0; ... |
#include <bits/stdc++.h> using namespace std; int readint() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; }... |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// a... |
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, pub... |
`timescale 1 ns / 1 ps
module axis_alex
(
// System signals
input wire aclk,
input wire aresetn,
output wire [3:0] alex_data,
// Slave side
output wire s_axis_tready,
input wire [31:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg [15:0] int_data_reg, int_data_nex... |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute,... |
#include <bits/stdc++.h> const int maxn = 3e5 + 3; int n, a[maxn], b[maxn], m, l[maxn], r[maxn]; void solve() { scanf( %d , &n); m = 0; for (int i = 0; i < n; ++i) { scanf( %d , a + i); b[m++] = a[i]; } std::sort(b, b + m); m = std::unique(b, b + m) - b; for (int i = 0; i <... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:35:34 04/22/2016
// Design Name:
// Module Name: vgagame
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Depende... |
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ ********************************************************... |
module foo;
// for each additional in-air txmacphy byte
task nextTxByte();
TxByteCnt++;
TxLastByteTime = $time;
endtask // nextTxByte
task automatic blah();
t;
endtask // blah
function static foo();
foo = 1;
endfunction // foo
// start counting when txmacphy sees firs... |
#include <bits/stdc++.h> using namespace std; int n, i, j, p[3005], a; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &p[i]); for (i = 1; i < n; i++) for (j = i + 1; j <= n; j++) if (p[i] > p[j]) a++; printf( %d n , a * 2 - a % 2); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
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