text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; int arr[20]; int mem[20][20][20]; int n, a, b; int calc(int ind, int p, int c) { int x0 = arr[ind - 1] - p, x1 = arr[ind] - c, x2 = arr[ind + 1]; int& res = mem[ind][p][c]; if (res != -1) return res; if (ind == n - 2) { res = 0; while (x0 >= 0 || x1 >= 0 || x2 >= 0) { ++res; x0 -= b; x2 -= b; x1 -= a; } return res; } res = ((int)1e9); int cnt = 0; while (x0 >= 0) { ++cnt; x0 -= b; x2 -= b; x1 -= a; } res = min(res, cnt + calc(ind + 1, arr[ind] - x1, arr[ind + 1] - x2)); while (x0 >= 0 || x1 >= 0 || x2 >= 0) { ++cnt; x0 -= b; x2 -= b; x1 -= a; res = min(res, cnt + calc(ind + 1, arr[ind] - x1, arr[ind + 1] - x2)); } return res = min(res, cnt + calc(ind + 1, arr[ind] - x1, arr[ind + 1] - x2)); } int sol[20 * 20 * 20]; int sz; void build(int ind, int p, int c) { int x0 = arr[ind - 1] - p, x1 = arr[ind] - c, x2 = arr[ind + 1]; if (ind == n - 2) { while (x0 >= 0 || x1 >= 0 || x2 >= 0) { sol[sz++] = ind + 1; x0 -= b; x2 -= b; x1 -= a; } return; } int cnt = 0; while (x0 >= 0) { sol[sz++] = ind + 1; ++cnt; x0 -= b; x2 -= b; x1 -= a; } if (calc(ind, p, c) == cnt + calc(ind + 1, arr[ind] - x1, arr[ind + 1] - x2)) { build(ind + 1, arr[ind] - x1, arr[ind + 1] - x2); return; } while (x0 >= 0 || x1 >= 0 || x2 >= 0) { ++cnt; x0 -= b; x2 -= b; x1 -= a; sol[sz++] = ind + 1; if (calc(ind, p, c) == cnt + calc(ind + 1, arr[ind] - x1, arr[ind + 1] - x2)) { build(ind + 1, arr[ind] - x1, arr[ind + 1] - x2); return; } } if (calc(ind, p, c) == cnt + calc(ind + 1, arr[ind] - x1, arr[ind + 1] - x2)) { build(ind + 1, arr[ind] - x1, arr[ind + 1] - x2); return; } } int main() { while (scanf( %d%d%d , &n, &a, &b) != -1) { for (int i = 0; i < n; ++i) scanf( %d , arr + i); memset(mem, -1, sizeof mem); int res = calc(1, 0, 0); printf( %d n , res); sz = 0; build(1, 0, 0); for (int i = 0; i < sz; ++i) printf(i ? %d : %d , sol[i]); printf( n ); fflush(stdout); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; int n; long long a[N]; long long b[N]; int main() { int t; scanf( %d , &t); while (t--) { vector<pair<long long, long long> > v; scanf( %d , &n); v.clear(); for (int i = 0; i < n; i++) { long long x, y; scanf( %I64d%I64d , &x, &y); v.push_back(make_pair(x, y)); } long long ans = 0; long long maxx = 0, minn = 1e18 + 10; long long t; for (int i = 0; i < n; i++) { maxx = v[(i + 1) % n].first - v[i].second; if (maxx < 0) { maxx = 0; } ans += maxx; } for (int i = 0; i < n; i++) { t = v[(i + 1) % n].first - v[i].second; if (t < 0) { t = 0; } if (minn > ans + v[(i + 1) % n].first - t) { minn = ans + v[(i + 1) % n].first - t; } } cout << minn << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pl = pair<ll, ll>; using vll = vector<ll>; using vpl = vector<pl>; using mat = vector<vll>; const ll MAX = 1e5; const ll mod = 1e9 + 7; template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (auto &ele : v) { cout << ele << ; } return os; } template <typename T, typename U> ostream &operator<<(ostream &os, const pair<T, U> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> istream &operator>>(istream &in, vector<T> &v) { for (auto &ele : v) { cin >> ele; } return in; } template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string &s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <typename T> class graph { public: struct edge { int from; int to; T cost; }; vector<edge> edges; vector<vector<int>> g; int n; graph(int _n) : n(_n) { g.resize(n); } virtual int add(int from, int to, T cost) = 0; }; template <typename T> class forest : public graph<T> { public: using graph<T>::edges; using graph<T>::g; using graph<T>::n; forest(int _n) : graph<T>(_n) {} int add(int from, int to, T cost = 1) { assert(0 <= from && from < n && 0 <= to && to < n); int id = (int)edges.size(); assert(id < n - 1); g[from].push_back(id); g[to].push_back(id); edges.push_back({from, to, cost}); return id; } }; template <typename T> class dfs_forest : public forest<T> { public: using forest<T>::edges; using forest<T>::g; using forest<T>::n; vector<int> pv; vector<int> pe; vector<int> order; vector<int> pos; vector<int> end; vector<int> sz; vector<int> root; vector<int> depth; vector<T> dist; dfs_forest(int _n) : forest<T>(_n) {} void init() { pv = vector<int>(n, -1); pe = vector<int>(n, -1); order.clear(); pos = vector<int>(n, -1); end = vector<int>(n, -1); sz = vector<int>(n, 0); root = vector<int>(n, -1); depth = vector<int>(n, -1); dist = vector<T>(n); } void clear() { pv.clear(); pe.clear(); order.clear(); pos.clear(); end.clear(); sz.clear(); root.clear(); depth.clear(); dist.clear(); } private: void do_dfs(int v) { pos[v] = (int)order.size(); order.push_back(v); sz[v] = 1; for (int id : g[v]) { if (id == pe[v]) { continue; } auto &e = edges[id]; int to = e.from ^ e.to ^ v; depth[to] = depth[v] + 1; dist[to] = dist[v] + e.cost; pv[to] = v; pe[to] = id; root[to] = (root[v] != -1 ? root[v] : to); do_dfs(to); sz[v] += sz[to]; } end[v] = (int)order.size() - 1; } void do_dfs_from(int v) { depth[v] = 0; dist[v] = T{}; root[v] = v; pv[v] = pe[v] = -1; do_dfs(v); } public: void dfs(int v, bool clear_order = true) { if (pv.empty()) { init(); } else { if (clear_order) { order.clear(); } } do_dfs_from(v); } void dfs_all() { init(); for (int v = 0; v < n; v++) { if (depth[v] == -1) { do_dfs_from(v); } } assert((int)order.size() == n); } }; void solve() { ll N; cin >> N; dfs_forest<ll> g(N); for (ll i = (0); (1) > 0 ? i < (N - 1) : i >= (N - 1); i += (1)) { ll x, y; cin >> x >> y; x -= 1, y -= 1; g.add(x, y); } g.dfs(0); vll cnt(2, 0); cerr << [ << g.depth << ]: , debug_out(g.depth); for (ll i = (0); (1) > 0 ? i < (N) : i >= (N); i += (1)) { cnt[g.depth[i] % 2] += 1; } cout << min(cnt[0], cnt[1]) - 1 << endl; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ll tc = 1; while (tc--) { solve(); } return 0; } |
/**
* This file containsn the arithmetic logic unit with following features:
*
* - Addition => 0x0
* - Substraction => 0x1
* - Shift left => 0x2
* - Bitwise OR => 0x3
* - Bitwise AND => 0x4
* - Bitwise XOR => 0x5
* - Rotate right => 0x6
* - Equals => 0x7
* - Greater than => 0x8
* - Smaller than => 0x9
*/
module ArithmeticLogicUnit
#(parameter BUS_WIDTH = 8)
(input wire [BUS_WIDTH-1:0] a,
input wire [BUS_WIDTH-1:0] b,
input wire [3:0] command,
input wire clk,
input wire reset,
output wire [BUS_WIDTH-1:0] out,
output wire overflow
);
reg addcin;
wire addcout;
wire [BUS_WIDTH-1:0] adds;
reg [BUS_WIDTH-1:0] adda;
reg [BUS_WIDTH-1:0] addb;
reg overflow_register;
reg [BUS_WIDTH-1:0] output_register;
assign out = output_register;
assign overflow = overflow_register;
BitAdder #(.BUS_WIDTH(BUS_WIDTH)) adder(.a(adda),.b(addb),.substract(addcin),.out(adds),.carry(addcout));
always @(*)
begin
if(reset)
begin
addcin = 0;
adda = 0;
addb = 0;
overflow_register = 0;
output_register = 0;
end
case(command)
0: begin
addcin = 0;
adda = a;
addb = b;
overflow_register = addcout;
output_register = adds;
end
1: begin
addcin = 1;
adda = a;
addb = ~b;
// overflow_register = addcout;
output_register = adds;
end
2: output_register = a << b;
3: output_register = a | b;
4: output_register = a & b;
5: output_register = a ^ b;
6: output_register = (a << b) | (a >> ~b);
7: overflow_register = (a == b);
8: overflow_register = (a > b);
9: overflow_register = (a < b);
default:
begin
overflow_register = 0;
output_register = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> namespace in { char buf[1 << 21], *p1 = buf, *p2 = buf; inline int getc() { return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++; } template <typename T> inline void read(T &t) { t = 0; int f = 0; char ch = getc(); while (!isdigit(ch)) { if (ch == - ) f = 1; ch = getc(); } while (isdigit(ch)) { t = t * 10 + ch - 48; ch = getc(); } if (f) t = -t; } template <typename T, typename... Args> inline void read(T &t, Args &...args) { read(t); read(args...); } char getC() { char c = getc(); while (!isdigit(c) && !isalpha(c) && c != ( && c != ) && c != ? ) c = getc(); return c; } } // namespace in namespace out { char buffer[1 << 21]; int p1 = -1; const int p2 = (1 << 21) - 1; inline void flush() { fwrite(buffer, 1, p1 + 1, stdout), p1 = -1; } inline void putc(const char &x) { if (p1 == p2) flush(); buffer[++p1] = x; } template <typename T> void write(T x) { static char buf[15]; static int len = -1; if (x >= 0) { do { buf[++len] = x % 10 + 48, x /= 10; } while (x); } else { putc( - ); do { buf[++len] = -(x % 10) + 48, x /= 10; } while (x); } while (len >= 0) putc(buf[len]), --len; } void puts(char *str) { int now = 0; while (str[now] != 0) putc(str[now++]); putc( n ); } } // namespace out namespace Game { unsigned long long p1[64][3200], p2[64][3200]; inline void make(unsigned long long arr[64][3200], int pos) { int th = std::min(63, pos); for (int i = 0; i <= th; i++) arr[i][(pos - i) >> 6] |= 1ull << ((pos - i) & 63); } void solve(int n, int m, int q, char *s1, char *s2, int *qx, int *qy, int *qlen, unsigned int *ans) { for (int i = 0; i < n; i++) if (s1[i] - 0 ) make(p1, i); for (int i = 0; i < m; i++) if (s2[i] - 0 ) make(p2, i); for (int i = 0; i < q; i++) { unsigned int res1 = 0, res2 = 0, res3 = 0, res4 = 0, res5 = 0, res6 = 0, res7 = 0, res8 = 0; int x = qx[i], y = qy[i], l = qlen[i]; unsigned int block = l >> 6, c; unsigned long long *arr1 = p1[x & 63] + (x >> 6); unsigned long long *arr2 = p2[y & 63] + (y >> 6); for (c = 0; c + 8 < block; c += 8, arr1 += 8, arr2 += 8) { res1 += __builtin_popcountll(arr1[0] ^ arr2[0]); res2 += __builtin_popcountll(arr1[1] ^ arr2[1]); res3 += __builtin_popcountll(arr1[2] ^ arr2[2]); res4 += __builtin_popcountll(arr1[3] ^ arr2[3]); res5 += __builtin_popcountll(arr1[4] ^ arr2[4]); res6 += __builtin_popcountll(arr1[5] ^ arr2[5]); res7 += __builtin_popcountll(arr1[6] ^ arr2[6]); res8 += __builtin_popcountll(arr1[7] ^ arr2[7]); } int res = res1 + res2 + res3 + res4 + res5 + res6 + res7 + res8; for (; c < block; c++, arr1++, arr2++) res += __builtin_popcountll(arr1[0] ^ arr2[0]); ans[i] = res + __builtin_popcountll((arr1[0] ^ arr2[0]) & ((1ull << (l & 63)) - 1)); out::write(ans[i]); out::putc( n ); } } void main() { char *s1 = new char[200000 + 1]; char *s2 = new char[200000 + 1]; int n, m; s1[n = 0] = in::getC(); while (isdigit(s1[n])) s1[++n] = in::getc(); s2[m = 0] = in::getC(); while (isdigit(s2[m])) s2[++m] = in::getc(); int q; in::read(q); unsigned int *anss = new unsigned int[q]; int *q_x = new int[q]; int *q_y = new int[q]; int *q_len = new int[q]; for (int i = 0; i < q; i++) in::read(q_x[i], q_y[i], q_len[i]); solve(n, m, q, s1, s2, q_x, q_y, q_len, anss); } } // namespace Game int main() { Game::main(); out::flush(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int _inf = 0xc0c0c0c0; const long long INF = 0x3f3f3f3f3f3f3f3f; const long long _INF = 0xc0c0c0c0c0c0c0c0; const long long mod = (int)1e9 + 7; const int Z = 100; const int N = Z * Z; const int M = Z * Z * Z; int px[N], py[N]; int head[N], to[M], ct[M], w[M], nt[M]; int d[N], vis[N]; int pre[N], id[N]; int s, t, tot; void add(int u, int v, int flow, int cost) { to[tot] = v; ct[tot] = cost; w[tot] = flow; nt[tot] = head[u]; head[u] = tot++; to[tot] = u; ct[tot] = -cost; w[tot] = 0; nt[tot] = head[v]; head[v] = tot++; } void init() { memset(head, -1, sizeof(head)); tot = 0; } int spfa(int s, int t) { queue<int> q; memset(d, inf, sizeof(d)); memset(vis, 0, sizeof(vis)); memset(pre, -1, sizeof(pre)); d[s] = 0; q.push(s); while (!q.empty()) { int u = q.front(); q.pop(); vis[u] = 0; for (int i = head[u]; ~i; i = nt[i]) { if (w[i] > 0 && d[to[i]] > d[u] + ct[i]) { d[to[i]] = d[u] + ct[i]; pre[to[i]] = u; id[to[i]] = i; if (!vis[to[i]]) { vis[to[i]] = 1; q.push(to[i]); } } } } return d[t] < inf; } int MaxFlow(int s, int t) { int Mi = inf; int sum = 0; int tt = 0; while (spfa(s, t)) { Mi = inf; for (int i = t; i != s; i = pre[i]) Mi = min(Mi, w[id[i]]); for (int i = t; i != s; i = pre[i]) { w[id[i]] -= Mi; w[id[i] ^ 1] += Mi; } tt += Mi; sum += d[t] * Mi; } return sum; } int main() { init(); int n, m, k, c, d; scanf( %d%d%d%d%d , &n, &m, &k, &c, &d); int s = 0, t = n * 100 + 1; for (int i = 1; i <= 100; ++i) add(i, t, 100, 0); for (int i = 1, v; i <= k; ++i) { scanf( %d , &v); add(s, (v - 1) * 100 + 1, 1, 0); } for (int i = 1; i <= n; ++i) { for (int j = 1; j < 100; ++j) { add((i - 1) * 100 + j, (i - 1) * 100 + j + 1, 100, c); } } for (int i = 1, u, v; i <= m; ++i) { scanf( %d%d , &u, &v); for (int j = 1; j < 100; ++j) { int idx = (u - 1) * 100 + j; int idy = (v - 1) * 100 + j + 1; for (int k = 1; k <= 20; ++k) { add(idx, idy, 1, c + (k * k - (k - 1) * (k - 1)) * d); } } for (int j = 1; j < 100; ++j) { int idx = (v - 1) * 100 + j; int idy = (u - 1) * 100 + j + 1; for (int k = 1; k <= 20; ++k) { add(idx, idy, 1, c + (k * k - (k - 1) * (k - 1)) * d); } } } printf( %d n , MaxFlow(s, t)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_BLACKBOX_V
`define SKY130_FD_SC_MS__HA_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ha (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, x, ans, h[5010], a[5010][5010], b[5010][5010]; int main() { scanf( %d , &n); m = (n + 1) / 2; for (int i = (1); i <= (n); i++) scanf( %d , &h[i]); for (int i = (0); i <= (n); i++) for (int j = (0); j <= (m); j++) a[i][j] = b[i][j] = 1000000000; for (int i = (0); i <= (n); i++) b[i][0] = 0; for (int i = (2); i <= (n + 1); i++) for (int j = (1); j <= (m); j++) { x = ((h[i] - h[i - 1] + 1) > (0) ? (h[i] - h[i - 1] + 1) : (0)); a[i][j] = x + ((((h[i - 3] - 1) < (h[i - 2]) ? (h[i - 3] - 1) : (h[i - 2])) - h[i - 1] + 1) > (0) ? (((h[i - 3] - 1) < (h[i - 2]) ? (h[i - 3] - 1) : (h[i - 2])) - h[i - 1] + 1) : (0)) + a[i - 2][j - 1]; a[i][j] = ((a[i][j]) < (x + ((h[i - 2] - h[i - 1] + 1) > (0) ? (h[i - 2] - h[i - 1] + 1) : (0)) + b[i - 2][j - 1]) ? (a[i][j]) : (x + ((h[i - 2] - h[i - 1] + 1) > (0) ? (h[i - 2] - h[i - 1] + 1) : (0)) + b[i - 2][j - 1])); b[i][j] = ((a[i - 1][j]) < (b[i - 1][j]) ? (a[i - 1][j]) : (b[i - 1][j])); } for (int i = (1); i <= (m); i++) { ans = 1000000000; for (int j = (1); j <= (n + 1); j++) ans = ((ans) < (((a[j][i]) < (b[j][i]) ? (a[j][i]) : (b[j][i]))) ? (ans) : (((a[j][i]) < (b[j][i]) ? (a[j][i]) : (b[j][i])))); printf( %d , ans); } } |
///////////////////////////////////////////////////////////////////////////////
/// Andrew Mattheisen
/// Zhiyang Ong
///
/// EE-577b 2007 fall
/// VITERBI DECODER
/// pmsm module (Path Metric State Memory)
///
/**
* @modified by Zhiyang Ong on November 1, 2007
* The reset values for the 2nd to the 4th
* registers are modified to achieve a unique solution,
* and avoid a set of equivalent paths for the solution.
* See subsequent comments in the code for further
* elaboration
*/
/// @modified by AJM - uncommented the change mentioned above
///////////////////////////////////////////////////////////////////////////////
module pmsm (npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);
// outputs
output [3:0] pm0, pm1, pm2, pm3;
// inputs
input clk, reset;
input [3:0] npm0, npm1, npm2, npm3;
reg [3:0] pm0, pm1, pm2, pm3;
reg [3:0] npm0norm, npm1norm, npm2norm, npm3norm;
// Defining constants: parameter [name_of_constant] = value;
parameter saturating_value = 4'd15;
always @ (npm0 or npm1 or npm2 or npm3)
begin
if ((npm0 <= npm1)&&(npm0 <= npm2)&&(npm0 <= npm3))
begin
npm0norm <= 0;
npm1norm <= npm1-npm0;
npm2norm <= npm2-npm0;
npm3norm <= npm3-npm0;
end
else if ((npm1 <= npm0)&&(npm1 <= npm2)&&(npm1 <= npm3))
begin
npm0norm <= npm0-npm1;
npm1norm <= 0;
npm2norm <= npm2-npm1;
npm3norm <= npm3-npm1;
end
else if ((npm2 <= npm0)&&(npm2 <= npm1)&&(npm2 <= npm3))
begin
npm0norm <= npm0-npm2;
npm1norm <= npm1-npm2;
npm2norm <= 0;
npm3norm <= npm3-npm2;
end
else if ((npm3 <= npm0)&&(npm3 <= npm1)&&(npm3 <= npm2))
begin
npm0norm <= npm0-npm3;
npm1norm <= npm1-npm3;
npm2norm <= npm2-npm3;
npm3norm <= 0;
end
end // always @ (npm0 or npm1 or npm2 or npm3)
/**
* @modified by Zhiyang Ong, November 1, 2007
* Note that the first register is reset to zero,
* and the rest are reset to infinity, which is
* represented by the saturating value of 15
* = 2^n - 1 = 2^4 - 1.
*
* This prevents the solution from arriving at a
* set of false/incorrect set of equivalent
* paths in the Trellis diagram. Multiple paths
* with zero costs indicate no unique solution.
* Also, these infinite/saturated values will be
* "removed"/diminished in 2 clock cycles.
*/
always @ (posedge clk)
begin
if (reset)
begin
pm0 <= 4'd0;
pm1 <= saturating_value;
pm2 <= saturating_value;
pm3 <= saturating_value;
end
else
begin
pm0 <= npm0norm;
pm1 <= npm1norm;
pm2 <= npm2norm;
pm3 <= npm3norm;
end
end // always @ (posedge clk)
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; for (int i = 0; i < q; i++) { int a, b, c; cin >> a; cin >> b; cin >> c; int p1, p2; cin >> p1; cin >> p2; int min_no = min(b, c); if (a <= 1) { cout << 0 << n ; continue; } if (b * 2 + c * 2 > a) { int p = 0; if (p2 >= p1) { if (c * 2 > a) { cout << (a / 2) * p2 << n ; continue; } else { p += c * p2; if ((a - c * 2) <= 1) { cout << p << n ; continue; } p += ((a - c * 2) / 2) * p1; cout << p << n ; continue; } } else if (p1 > p2) { if (b * 2 > a) { cout << (a / 2) * p1 << n ; continue; } else { p += b * p1; if ((a - b * 2) <= 1) { cout << p << n ; continue; } p += ((a - b * 2) / 2) * p2; cout << p << n ; continue; } } } else { int p = 0; p += (p2 * c) + (p1 * b); cout << p << n ; continue; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 9; const int L = 301; const int INF = 1e9 + 239; int n; int a[N]; int cnt[N]; vector<int> pos[N]; int mn[2 * N]; void solve(vector<pair<int, int>> v, int &ans) { v.push_back({n - 1, 0}); int prev = -1; int c = 0; mn[N] = 0; for (auto [pos, val] : v) { if (abs(prev) < 2) ans = max(ans, (pos - 1) - mn[c + N] + 1); c += val; ans = max(ans, pos - mn[c + N] + 1); mn[c + N] = min(mn[c + N], pos + 1); prev = val; } c = 0; mn[0] = INF; for (auto [pos, val] : v) { c += val; mn[c + N] = INF; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); fill(mn, mn + 2 * N, INF); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; cnt[a[i]]++; pos[a[i]].push_back(i); } int ans = 0; int mx = max_element(cnt, cnt + N) - cnt; int pnt = -1; int sz = -1; vector<pair<int, int>> vplus, vminus; auto add = [&](int p) { int imx = lower_bound(pos[mx].begin(), pos[mx].end(), p) - pos[mx].begin(); int l = max(pnt + 1, imx - (sz + 3)); if (pnt + 1 < imx - (sz + 3)) { vplus.push_back({pos[mx][pnt + 1], imx - (sz + 3) - (pnt + 1)}); } for (int i = l; i <= imx + (sz + 3) && i < (int)pos[mx].size(); i++) { vplus.push_back({pos[mx][i], 1}); pnt = i; } }; auto relax_small = [&](int s) { if (pos[s].empty()) { return; } vplus.clear(); vminus.clear(); sz = (int)pos[s].size(); pnt = -1; { add(0); } for (auto p : pos[s]) { add(p); vminus.push_back({p, -1}); } { add(n - 1); } vector<pair<int, int>> vall(vplus.size() + vminus.size()); merge(vplus.begin(), vplus.end(), vminus.begin(), vminus.end(), vall.begin()); solve(vall, ans); }; auto relax_big = [&](int s) { if (pos[s].empty()) { return; } vplus.clear(); vminus.clear(); for (auto p : pos[mx]) { vplus.push_back({p, 1}); } for (auto p : pos[s]) { vminus.push_back({p, -1}); } vector<pair<int, int>> vall(vplus.size() + vminus.size()); merge(vplus.begin(), vplus.end(), vminus.begin(), vminus.end(), vall.begin()); solve(vall, ans); }; for (int other = 0; other < N; other++) { if (other == mx) { continue; } if (pos[other].size() > L) { relax_big(other); } else { relax_small(other); } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; int t, n, a[100005]; vector<int> v[100005]; int val[100005]; int k[100005]; int main() { for (int i = 2; i <= 100000; i++) { v[i].push_back(1); for (int j = i + i; j <= 100000; j += i) { v[j].push_back(i); } } scanf( %d , &t); while (t--) { memset(k, 0, sizeof(k)); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = n; i >= 1; i--) { if (k[i] == 0) k[i] = 1; int p = v[i].size(); for (int j = 0; j < p; j++) { if (a[i] > a[v[i][j]]) k[v[i][j]] = max(k[v[i][j]], k[i] + 1); } } int mx = 0; for (int i = 1; i <= n; i++) { mx = max(mx, k[i]); } printf( %d n , mx); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<string, string>> taken; int main() { int n; scanf( %d , &n); int ans = 0; for (int i = 1; i <= n; ++i) { string s, t; cin >> s >> t; bool flag = 1; for (auto [x, y] : taken) { if (x == s && y == t) { flag = 0; break; } } if (flag) { ans++; taken.push_back({s, t}); } } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; int a[100009]; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; int t = 0; long long sum1 = 0; sort(a, a + n); int m = 0, l = 0, token = 0; for (int i = n - 1; i >= 0; i--) { if (a[i] > k) { int temp = a[i] / k; token = temp; temp /= 2; if (a[i] % k != 0) { if (token % 2 == 1) temp++; token++; } if (token % 2 == 1) { if (l == 0) l = 1; else { t++; l = 0; } } t += temp; } else { if (m == 0) { m = 1; } else { t++; m = 0; } } if (l == 1 && m == 1 && i == 0) t++; else if (m == 1 && i == 0) t++; else if (l == 1 && i == 0) t++; } cout << t << n ; } |
// file: clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______123.073_____85.928
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________250.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v5_2_1,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_gen
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset
);
clk_gen_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_8_V
`define SKY130_FD_SC_HD__MUX2_8_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2_8 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2_8 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_8_V
|
#include <bits/stdc++.h> using namespace std; const int N = 50010; const int inf = 1e9; inline int read() { int p = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { p = p * 10 + ch - 0 ; ch = getchar(); } return p * f; } struct node { int x, y, d, c, next; } edge[N << 4]; int len, first[N]; void ins(int x, int y, int c, int d) { len++; edge[len].x = x; edge[len].y = y; edge[len].c = c; edge[len].d = d; edge[len].next = first[x]; first[x] = len; len++; edge[len].x = y; edge[len].y = x; edge[len].c = 0; edge[len].d = -d; edge[len].next = first[y]; first[y] = len; } bool v[N]; int d[N]; queue<int> q; int pre[N], pos[N]; int s, t; bool bfs() { while (!q.empty()) q.pop(); q.push(s); memset(d, -63, sizeof(d)); d[s] = 0; memset(v, 0, sizeof(v)); v[s] = 1; while (!q.empty()) { int x = q.front(); for (int k = first[x]; k != -1; k = edge[k].next) { int y = edge[k].y; if (d[y] < d[x] + edge[k].d && edge[k].c) { d[y] = d[x] + edge[k].d; pos[y] = x; pre[y] = k; if (!v[y]) { v[y] = 1; q.push(y); } } } q.pop(); v[x] = 0; } return d[t] >= 0; } int n, a[N]; int main() { len = 1; memset(first, -1, sizeof(first)); n = read(); for (int i = 1; i <= n; i++) a[i] = read(); int ss = 2 * n + 1; s = ss + 1; t = s + 1; ins(s, ss, 4, 0); for (int i = 1; i <= n; i++) { ins(ss, i + n, 1, 0); ins(i + n, i, 1, 1); ins(i, t, 1, 0); } for (int i = 1; i <= n; i++) { int cnt = 0; for (int j = i + 1; j <= n; j++) if ((a[i] - a[j] == 1) && cnt < 1) { ins(i, j + n, inf, 0); cnt++; } cnt = 0; for (int j = i + 1; j <= n; j++) if ((a[i] - a[j] == -1) && cnt < 1) { ins(i, j + n, inf, 0); cnt++; } cnt = 0; for (int j = i + 1; j <= n; j++) if ((a[i] % 7 == a[j] % 7) && cnt < 1) { ins(i, j + n, inf, 0); cnt++; } ins(i + n, i, inf, 0); } int ans = 0; while (bfs()) { for (int i = t; i != s; i = pos[i]) ans += edge[pre[i]].d, edge[pre[i]].c--, edge[pre[i] ^ 1].c++; } return printf( %d n , ans), 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; double gmin = 100000000000000017; int a, b; int Y1[100005], Y2[100005], L[100005]; double dist(double x1, double y1, double x2, double y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } double f(int i, int j) { return dist(0, 0, a, Y1[i]) + L[j] + dist(a, Y1[i], b, Y2[j]); } int main() { int t, i, j, c, d, idx1, idx2, m, n, idx; scanf( %d , &n); scanf( %d , &m); scanf( %d , &a); scanf( %d , &b); for (i = 0; i < n; i++) scanf( %d , &Y1[i]); for (i = 0; i < m; i++) scanf( %d , &Y2[i]); for (i = 0; i < m; i++) scanf( %d , &L[i]); for (i = 0; i < m; i++) { int low = 0, high = n - 1; while (high - low >= 3) { int m1 = low + (high - low) / 3; int m2 = high - (high - low) / 3; if (f(m1, i) < f(m2, i)) high = m2; else low = m1; } double mini = 1000000000000; for (j = low; j <= high; ++j) { if (f(j, i) < mini) { mini = f(j, i); idx = j; } } if (mini < gmin) { gmin = mini; idx1 = idx + 1; idx2 = i + 1; } } printf( %d , idx1); printf( %d , idx2); return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 4427 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w64,
w63,
w252,
w315,
w256,
w257,
w4112,
w4427;
assign w1 = i_data0;
assign w252 = w63 << 2;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w315 = w63 + w252;
assign w4112 = w257 << 4;
assign w4427 = w315 + w4112;
assign w63 = w64 - w1;
assign w64 = w1 << 6;
assign o_data0 = w4427;
//multiplier_block area estimate = 7125.14888406029;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/**
* Generic ROM memory
*
* (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
* GPL license
*
* Memory with the next parameters:
* - AW: Number of bits for directions
* - DW: Number of bits for data
* - ROMFILE: File to be used to load the memory
*/
module genrom #( // Parameters
parameter AW = 4, // Address width in bits
parameter DW = 8, // Data witdh in bits
parameter EXTRA = 4
)
( // Ports
input clk, // Global clock signal
input wire [ AW :0] addr, // Address
input wire [ EXTRA-1:0] extra, // Length of data to be fetch
input wire [ AW :0] lower_bound,
input wire [ AW :0] upper_bound,
output reg [2**EXTRA*DW-1:0] data=0, // Output data
output reg error=0 // none / out of limits
);
// Parameter: name of the file with the ROM content
parameter ROMFILE = "prog.list";
// Calc the number of total positions of memory
localparam NPOS = 1 << (AW+1);
// Memory
reg [DW-1: 0] rom [0: NPOS-1];
// Read the memory
always @(posedge clk) begin
error <= addr < lower_bound || addr > upper_bound;
case (extra)
0: data <= rom[addr ];
1: data <= {rom[addr ], rom[addr+ 1]};
2: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2]};
3: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3]};
4: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4]};
5: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5]};
6: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6]};
7: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7]};
8: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8]};
9: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9]};
10: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10]};
11: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11]};
12: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12]};
13: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13]};
14: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13], rom[addr+14]};
15: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3],
rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7],
rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11],
rom[addr+12], rom[addr+13], rom[addr+14], rom[addr+15]};
endcase
end
// Load in memory the `ROMFILE` file. Values must be given in hexadecimal
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
|
//-------------------------------------------------------------------
//-- txstr_tb.v
//-- Testbench for the simulation of the txstr.v example
//-------------------------------------------------------------------
//-- (c) BQ December 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`default_nettype none
`timescale 100 ns / 10 ns
`include "baudgen.vh"
module txstr_tb();
//-- Baudrate for the simulation
localparam BAUDRATE = `B115200;
//-- clock tics needed for sending one serial package
localparam SERIAL_CAR = (BAUDRATE * 10);
//-- System clock
reg clk = 1;
//-- Transmission line
wire tx;
//-- Reset
reg rstn = 0;
//-- Instantiate the entity the character transmitter
txstr #(
.BAUDRATE(BAUDRATE)
)
dut (
.clk(clk),
.rstn(rstn),
.tx(tx)
);
//-- Clock generator
always
# 0.5 clk <= ~clk;
initial begin
//-- File where to store the simulation
$dumpfile("txstr_tb.vcd");
$dumpvars(0, txstr_tb);
//-- Activate reset
#1 rstn <= 0;
//-- Disable the reset. The transmission begins!
#3 rstn <= 1;
//-- Wait for 3 characters and finish
#(SERIAL_CAR * 10) $display("END of simulation");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, maxn = 200007; const long long MOD = 998244353; const long long LINF = 0x3f3f3f3f3f3f3f3fLL; const long long P = 19260817; char nc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return x * f; } inline long long readll() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return x * f; } void write(int x) { if (!x) putchar( 0 ); if (x < 0) x = -x, putchar( - ); static int sta[20]; register int tot = 0; while (x) sta[tot++] = x % 10, x /= 10; while (tot) putchar(sta[--tot] + 48); } int mod1(int x) { if (x >= MOD) x -= MOD; return x; } int n, k; int a[maxn], c[maxn]; int lst[maxn]; struct mcmf { struct edge { int to, nxt, c, val; } e[maxn << 1]; int tot = 1, head[maxn]; void addedge(int u, int v, int val, int cost) { e[++tot] = (edge){v, head[u], cost, val}; head[u] = tot; e[++tot] = (edge){u, head[v], -cost, 0}; head[v] = tot; } int s, t; int dis[maxn], pre[maxn], vis[maxn]; bool spfa() { queue<int> q; while (!q.empty()) q.pop(); memset(dis, 0x3f, sizeof(dis)); memset(vis, 0, sizeof(vis)); memset(pre, 0, sizeof(pre)); q.push(s); dis[s] = 0; vis[s] = 1; while (!q.empty()) { int u = q.front(); q.pop(); vis[u] = 0; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (e[i].val && dis[v] > dis[u] + e[i].c) { dis[v] = dis[u] + e[i].c, pre[v] = i; if (!vis[v]) { vis[v] = true; q.push(v); } } } } return (pre[t] != 0); } int query() { int mc = 0, mf = 0; while (spfa()) { int flow = INF; for (int i = pre[t]; i; i = pre[e[i ^ 1].to]) flow = min(flow, e[i].val); mf += flow; for (int i = pre[t]; i; i = pre[e[i ^ 1].to]) { e[i].val -= flow, e[i ^ 1].val += flow, mc += flow * e[i].c; } } return mc; } } F; vector<int> v; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) scanf( %d , c + i); int sum = 0; v.push_back(0); for (int i = 1; i <= n; i++) if (a[i] != a[i - 1]) v.push_back(a[i]); n = v.size() - 1; for (int i = 1; i <= n; i++) { sum += c[v[i]]; if (lst[v[i]]) F.addedge(lst[v[i]] + 1, i, 1, -c[v[i]]); lst[v[i]] = i; if (i != n) F.addedge(i, i + 1, k - 1, 0); } F.s = n + 1, F.t = n + 2; F.addedge(F.s, 1, k - 1, 0); F.addedge(n, F.t, k - 1, 0); printf( %d , sum + F.query()); return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int sum = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) { sum = (sum << 1) + (sum << 3) + (c ^ 48); c = getchar(); } return sum; } int n, k, a, m; set<int> s; set<int>::iterator it; int main() { n = read(), k = read(), a = read(); s.insert(0), s.insert(n + 1); m = read(); int rest = (n + 1) / (a + 1); if (rest < k) { printf( 0 n ); return 0; } for (int i = 1; i <= m; i++) { int x = read(); it = s.lower_bound(x); int a1 = *it; it--; int a2 = *it; int dist = a1 - a2 - 1, dist1 = x - a2 - 1, dist2 = a1 - x - 1; int b = (dist + 1) / (a + 1), b1 = (dist1 + 1) / (a + 1), b2 = (dist2 + 1) / (a + 1); rest -= (b - (b1 + b2)); if (rest < k) { printf( %d n , i); return 0; } s.insert(x); } printf( -1 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; const long long mod = 1e9 + 7; const long long inf = 1e9; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; sort(v.begin(), v.end()); int sum = 0; for (int i = 0; i < min(n, m); i++) { if (v[i] < 0) sum += v[i] * -1; } cout << sum; } |
module modexp_test_2N_NN();
parameter N = 8;
parameter CC = 2*N*N;
reg clk;
reg rst1;
reg rst2;
reg [N-1:0] m;
reg [N-1:0] e;
reg [N-1:0] d;
reg [N-1:0] n;
wire [N-1:0] c;
reg [N-1:0] creg;
wire [N-1:0] mout;
function [N-1:0] modexp_f;
input [N-1:0] m;
input [N-1:0] e;
input [N-1:0] n;
reg [2*N-1:0] mm;
integer i, start;
begin
$display("modexp_f: m =%d e =%d n=%d", m, e, n);
start = -1;
for(i=N-1;i>=0;i=i-1)
begin
if(e[i] && start == -1)
begin
start = i;
end
end
modexp_f = m;
$display("%d", modexp_f);
for(i=start-1;i>=0;i=i-1)
begin
mm = modexp_f;
mm = mm*mm;
modexp_f = mm%n;
$display("%d", modexp_f);
if(e[i])
begin
mm = modexp_f;
mm = mm * m;
modexp_f = mm%n;
$display("* %d", modexp_f);
end
end
end
endfunction
modexp
#(
.N(N),
.CC(CC)
)
UUT1
(
.clk(clk),
.rst(rst1),
.m(m),
.e(e),
.n(n),
.c(c)
);
modexp
#(
.N(N),
.CC(CC)
)
UUT2
(
.clk(clk),
.rst(rst2),
.m(creg),
.e(d),
.n(n),
.c(mout)
);
integer i;
initial
begin
m = 'd57;
//e = 'd11;
//e = 8'b1111_1111;
//e = 8'b0011_1100;
e = 8'b1000_0001;
d = 'd35;
n = 'd221;
creg = 0;
$display("m = %d", m);
$display("e = %d", e);
$display("d = %d", d);
$display("n = %d", n);
clk = 0;
rst1 = 1;
rst2 = 1;
@(negedge clk);
rst1 = 0;
for(i=0;i<CC-1;i=i+1)
@(negedge clk);
$display("c = %d, modexp_f = %d", c, modexp_f(m,e,n));
$display("------------");
creg = c;
@(negedge clk);
@(negedge clk);
@(negedge clk);
rst1 = 1;
rst2 = 0;
for(i=0;i<CC-1;i=i+1)
@(negedge clk);
$display("mout = %d, modexp_f = %d", mout, modexp_f(creg,d,n));
if(mout == m)
$display("Correct!", mout);
else
$display("Error!", mout);
@(negedge clk);
rst2 = 1;
$stop;
end
always #5 clk=~clk;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:22 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/zynq_design_1_rst_ps7_0_100M_0_stub.v
// Design : zynq_design_1_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module zynq_design_1_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1P_LP_V
`define SKY130_FD_SC_LP__ISO1P_LP_V
/**
* iso1p: ????.
*
* Verilog wrapper for iso1p with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso1p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1p_lp (
X ,
A ,
SLEEP,
KAPWR,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1p_lp (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1P_LP_V
|
`timescale 1ns / 1ps
// This module implements the set of 31 64-bit wide registers for the CPU.
//
// Note that reading the register bank is _synchronous_, not asynchronous.
// This means you must present the desired register address prior to a clock
// edge, and the contents of the indicated register will appear after that
// edge.
//
// This module assumes you're targeting the iCE40HX series of FPGAs.
module xrs(
input clk_i,
input [4:0] ra_i,
input [63:0] rdat_i,
output [63:0] rdat_o,
input [3:0] rmask_i
);
wire [63:0] q;
reg [4:0] addr;
always @(posedge clk_i) addr <= ra_i;
assign rdat_o = (|addr) ? q : 0;
ram column3(
.din(rdat_i[63:48]),
.addr(ra_i),
.write_en(rmask_i[3]),
.clk(clk_i),
.dout(q[63:48])
);
ram column2(
.din(rdat_i[47:32]),
.addr(ra_i),
.write_en(rmask_i[2]),
.clk(clk_i),
.dout(q[47:32])
);
ram column1(
.din(rdat_i[31:16]),
.addr(ra_i),
.write_en(rmask_i[1]),
.clk(clk_i),
.dout(q[31:16])
);
ram column0(
.din(rdat_i[15:0]),
.addr(ra_i),
.write_en(rmask_i[0]),
.clk(clk_i),
.dout(q[15:0])
);
endmodule
module ram (din, addr, write_en, clk, dout);
parameter addr_width = 5;
parameter data_width = 16;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input write_en, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout; // Register for output.
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
always @(posedge clk)
begin
if (write_en) mem[(addr)] <= din;
dout = mem[addr]; // Output register controlled by clock.
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using uint = unsigned int; using ull = unsigned long long; template <typename T> using pair2 = pair<T, T>; using pii = pair<int, int>; using pli = pair<ll, int>; using pll = pair<ll, ll>; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); ll myRand(ll B) { return (ull)rng() % B; } clock_t startTime; double getCurrentTime() { return (double)(clock() - startTime) / CLOCKS_PER_SEC; } const double eps = 1e-7; bool eq(double x, double y) { return abs(x - y) < eps; } bool ls(double x, double y) { return x < y && !eq(x, y); } bool lseq(double x, double y) { return x < y || eq(x, y); } double sqr(double x) { return x * x; } struct Point { double x, y; Point() : x(), y() {} Point(double _x, double _y) : x(_x), y(_y) {} void scan() { scanf( %lf%lf , &x, &y); } void print() { printf( %.12lf %.12lf n , x, y); } Point operator+(const Point &a) const { return Point(x + a.x, y + a.y); } Point operator-(const Point &a) const { return Point(x - a.x, y - a.y); } Point operator*(const double &k) const { return Point(x * k, y * k); } Point operator/(const double &k) const { return Point(x / k, y / k); } double operator%(const Point &a) const { return x * a.x + y * a.y; } double operator*(const Point &a) const { return x * a.y - y * a.x; } double sqrLen() const { return *this % *this; } double len() const { return sqrt(sqrLen()); } Point norm() const { return *this / len(); } Point ort() const { return Point(-y, x); } }; double getAngle(Point v, Point u) { return atan2(v * u, v % u); } bool onLine(Point A, Point B, Point C) { return eq((A - B) * (A - C), 0); } bool onSegm(Point A, Point B, Point C) { if (!onLine(A, B, C)) return false; return lseq((A - B) % (C - B), 0); } bool intersectLines(Point A, Point a, Point B, Point b, Point &I) { if (eq(a * b, 0)) return false; double y = ((A - B) * a) / (b * a); I = B + b * y; return true; } Point getH(Point P, Point A, Point a) { return A + a * (((P - A) % a) / a.sqrLen()); } bool intersectLineCircle(Point A, Point a, Point O, double R, Point &I1, Point &I2) { Point H = getH(O, A, a); double x = (O - H).len(); if (ls(R, x)) return false; if (eq(R, x)) { I1 = I2 = H; return true; } a = a.norm(); x = sqrt(sqr(R) - sqr(x)); I1 = H + a * x; I2 = H - a * x; return true; } bool intersectCircles(Point O1, double R1, Point O2, double R2, Point &I1, Point &I2) { if (R1 < R2) { swap(O1, O2); swap(R1, R2); } double L = (O1 - O2).len(); if (ls(R1 + R2, L) || ls(L, R1 - R2) || eq(L, 0)) return false; if (eq(R1 + R2, L) || eq(L, R1 - R2)) { I1 = I2 = O1 + (O2 - O1).norm() * R1; return true; } double x = (sqr(R1) - sqr(R2) + sqr(L)) / (2 * L); Point a = (O2 - O1).norm(); Point H = O1 + a * x; a = a.ort(); x = sqrt(sqr(R1) - sqr(x)); I1 = H + a * x; I2 = H - a * x; return true; } bool isInside(Point P, Point O, double R) { return lseq((P - O).sqrLen(), sqr(R)); } vector<vector<Point>> a; vector<double> sz; bool insidePoly(Point P, vector<Point> w) { int m = (int)w.size() - 1; for (int i = 0; i < m; i++) if (onSegm(w[i], P, w[i + 1])) return true; double ang = 0; for (int i = 0; i < m; i++) ang += getAngle(w[i] - P, w[i + 1] - P); return abs(ang) > 1; } bool checkPoly(vector<Point> w, Point O, double R) { if (insidePoly(O, w)) return true; int m = (int)w.size() - 1; for (int i = 0; i < m; i++) { if (isInside(w[i], O, R)) return true; Point H = getH(O, w[i], w[i + 1] - w[i]); if (isInside(H, O, R) && onSegm(w[i], H, w[i + 1])) return true; } return false; } vector<Point> readPoly() { int n; scanf( %d , &n); vector<Point> a(n + 1); for (int i = 0; i < n; i++) a[i].scan(); a[n] = a[0]; return a; } double sizePoly(vector<Point> w) { double S = 0; int m = (int)w.size() - 1; for (int i = 0; i < m; i++) S += w[i] * w[i + 1]; return abs(S) / 2; } int main() { startTime = clock(); double R; int n, w; scanf( %lf%lf%d , &R, &R, &n); a.resize(n); sz.resize(n); for (int i = 0; i < n; i++) { a[i] = readPoly(); sz[i] = sizePoly(a[i]); } int q; scanf( %d , &q); while (q--) { Point O; O.scan(); scanf( %lf , &R); vector<int> res; double S = 0; for (int i = 0; i < n; i++) { if (checkPoly(a[i], O, R)) { res.push_back(i); S += sz[i]; } } printf( %.12lf %d , S, (int)res.size()); for (int x : res) printf( %d , x); printf( n ); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:06:59 11/16/2014
// Design Name:
// Module Name: serial
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module serial # (
parameter TRUE = 1'b1,
parameter FALSE = 1'b0,
parameter CLOCK_PER_BAUD_RATE = 5208,
parameter SERIAL_STATE_LAST = 8,
parameter SERIAL_STATE_SENT = 9,
parameter SERIAL_STATE_WAIT = 10
)(
input CLOCK_50M,
// input RX,
output TX,
input [63:0] send_buffer_in,
input [2:0] send_buffer_count_in,
// output [63:0] send_buffer_out,
output [2:0] send_buffer_count_out,
output LED1,
output LED2
);
reg [63:0] send_buffer;
reg [2:0] send_buffer_count;
assign send_buffer_out = send_buffer;
assign send_buffer_count_out = send_buffer_count;
/*
* CLOCK GENERATOR
*/
reg CLOCK = FALSE;
reg [15:0] clock_counter;
always @(posedge CLOCK_50M) begin
if (clock_counter < CLOCK_PER_BAUD_RATE) begin
CLOCK <= FALSE;
clock_counter <= clock_counter + 1;
end
else begin
CLOCK <= TRUE;
clock_counter <= 0;
end
end
/*
* TRANSMIT DATA
*/
// reg serial_state = SERIAL_STATE_WAIT;
reg [7:0] tx_buffer = "A";
reg [3:0] tx_counter = SERIAL_STATE_WAIT; // 0->start bit sent,1=>first bit sent,...8=>wight bit sent,9=>sent, 10=>not send yet
reg tx_state = TRUE;
assign TX = tx_state;
assign LED1 = tx_state;
assign LED2 = TRUE;
// wire send_buffer_input;
// wire send_buffer_count_input;
// assign send_buffer_input = send_buffer;
// assign send_buffer_count_input = send_buffer_count;
always @(posedge CLOCK) begin
if (tx_counter == SERIAL_STATE_WAIT) begin
tx_state <= FALSE;
tx_counter <= 0;
end
else if (tx_counter == SERIAL_STATE_LAST) begin
tx_state <= TRUE;
tx_counter <= SERIAL_STATE_SENT;
end
else if (tx_counter == SERIAL_STATE_SENT && send_buffer_count_in > 0) begin
tx_buffer <= send_buffer_in[7:0];
send_buffer <= send_buffer_in >> 8;
send_buffer_count <= send_buffer_count_in - 1;
end
else begin
tx_state <= tx_buffer[tx_counter];
tx_counter <= tx_counter + 1;
end
end
// function send (
// input dummy
// );
// begin
// tx_buffer = "A";
// tx_counter = SERIAL_STATE_WAIT;
// end
// endfunction
/*
* RECEIVE DATA
*/
// always @(posedge CLOCK) begin
// end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m, i, j; cin >> n >> m; int x, y; vector<vector<int> > adj(n); vector<int> ncon(n, 0); for (i = (0); i < (m); i++) { cin >> x >> y; adj[x - 1].push_back(y - 1); adj[y - 1].push_back(x - 1); ncon[x - 1]++; ncon[y - 1]++; } vector<int> onecon; for (i = (0); i < (n); i++) if (ncon[i] == 1) onecon.push_back(i); int maxd = 0; queue<int> q; vector<int> dist(n, 0), rem(n, 0); for (auto i : onecon) { q.push(i); dist[i] = 1; } if ((int)((onecon).size()) != 0) maxd = 1; while (!q.empty()) { int cur = q.front(); q.pop(); rem[cur] = 1; if (ncon[cur] == 1) maxd = max(maxd, dist[cur]); for (auto next : adj[cur]) { if (rem[next] == 1) continue; ncon[next]--; if (ncon[next] == 1) { dist[next] = dist[cur] + 1; q.push(next); } } } cout << maxd << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<int> > v(14 + 1); int go[1001][14], fail[1001], weight[1001], nxt, maxLength; pair<int, long long> a[1001]; long long dp[1001][(1 << 14)]; const long long negativeInfinity = LLONG_MIN / 2; void AddStringToAhoCorasick(string s, int val) { int i = 0; for (auto c : s) { int k = c - a ; if (go[i][k] == 0) { go[i][k] = ++nxt; } i = go[i][k]; } maxLength = max(maxLength, (int)s.size()); weight[i] += val; } void BuildAhoCorasick() { queue<int> Q; for (int x = 0; x < 14; ++x) { if (go[0][x]) { Q.push(go[0][x]); } } while (!Q.empty()) { const int i = Q.front(); Q.pop(); weight[i] += weight[fail[i]]; for (int x = 0; x < 14; ++x) { const int j = go[i][x]; if (j) { fail[j] = go[fail[i]][x]; Q.push(j); } else { go[i][x] = go[fail[i]][x]; } } } } void ResetTransitions() { for (int i = 0; i <= nxt; ++i) { a[i].first = -1; } } inline pair<int, long long> GetTransitionedNode(int i, const string &s) { int j = i; long long val = 0; for (auto c : s) { j = go[j][c - a ]; val += weight[j]; } a[i] = make_pair(j, val); return a[i]; } void ApplyStringTransitions(const string &s, const int n, const int qCount) { for (int i = 0; i <= n; ++i) { int j; long long val; tie(j, val) = GetTransitionedNode(i, s); for (int mask : v[qCount]) { if (dp[i][mask] < negativeInfinity) { continue; } val += dp[i][mask]; for (int x = 0; x < 14; ++x) { if ((mask & (1 << x)) > 0) { continue; } const int k = go[j][x], nmask = mask | (1 << x); dp[k][nmask] = max(dp[k][nmask], val + weight[k]); } val -= dp[i][mask]; } } } int Initialise() { int n; cin >> n; while (n--) { string s; int val; cin >> s >> val; AddStringToAhoCorasick(s, val); } BuildAhoCorasick(); for (int mask = 0; mask < (1 << 14); ++mask) { v[__builtin_popcount(mask)].push_back(mask); } return nxt; } int main() { int n = Initialise(); string t; cin >> t; int cur = 0; for (int i = 0; i <= n; ++i) { for (int mask = 0; mask < (1 << 14); ++mask) { dp[i][mask] = LLONG_MIN; } } dp[0][0] = 0; string s; int qCount = 0; for (auto c : t) { if (c != ? ) { s.push_back(c); continue; } ApplyStringTransitions(s, n, qCount); s.clear(); ++qCount; } long long ans = LLONG_MIN; for (int i = 0; i <= n; ++i) { int j; long long val; tie(j, val) = GetTransitionedNode(i, s); for (int mask : v[qCount]) { if (dp[i][mask] < negativeInfinity) { continue; } ans = max(ans, val + dp[i][mask]); } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int N = 2e5 + 6; int cnt[666], dp[777][777]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int _, n; cin >> _; while (_--) { cin >> n; for (int i = 0; i <= n - 1; i++) cin >> cnt[i]; for (int i = 0; i <= n; i++) for (int j = 0; j <= n * 2; j++) dp[i][j] = 1e9; sort(cnt, cnt + n); int ans = 1e9; dp[0][0] = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n * 2; j++) { for (int k = 0; k <= j - 1; k++) { dp[i][j] = min(dp[i - 1][k] + abs(cnt[i - 1] - j), dp[i][j]); if (n - i == 0) ans = min(ans, dp[i][j]); } } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t > 0) { string s1, s2; cin >> s1 >> s2; long long int f = 0; if (s1.length() > s2.length()) { cout << NO << endl; f = -1; } else { long long int i = 0, j = 0; while (i < s1.length() || j < s2.length()) { if (s2[j] == s1[i] && s2[j + 1] == s1[i + 1]) { j++; i++; } else if (s2[j] == s1[i]) j++; else if (s2[j] == s1[i + 1] && j > 0) i++; else { cout << NO << endl; f = -1; break; } } if (f != -1) cout << YES << endl; } t--; } } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) const long long INF = 0x3f3f3f3f3f3f3f3f; const long long llinf = LLONG_MAX; const int inf = INT_MAX; const int nmax = 1e6 + 5; const int mod = 1e9 + 7; using namespace std; int i, ans, x; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> s; for (i = 0; i < s.size(); i++) { if (s[i] == M ) x++; else if (x) ans = max(ans + 1, x); } cout << ans << endl; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_pad_mux
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_pad_mux.v,v 1.2 2007/03/05 16:41:13 wig Exp $
// $Date: 2007/03/05 16:41:13 $
// $Log: avfb_pad_mux.v,v $
// Revision 1.2 2007/03/05 16:41:13 wig
// Updated testcase: remove mux_sel_p and some loose mix_logic_0/1
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_pad_mux
//
// No user `defines in this module
module avfb_pad_mux
//
// Generated module i_avfb_pad_mux
//
(
BC_RA_02_fail_i
);
// Generated Module Inputs:
input BC_RA_02_fail_i;
// Generated Wires:
wire BC_RA_02_fail_i;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire BC_RA_02_fail; // __W_PORT_SIGNAL_MAP_REQ
// __I_IN_OPEN wire [4:4] cvbs_c_tbo_1 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] cvbs_c_tbo_2 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire i2s_ws_en_out1 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire i2s_ws_out1_in ; // __W_BAD_BRANCH
// __I_IN_OPEN wire i2s_ws_out1_out ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [5:0] iom_mux_control ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [2:2] kl_123456a2345b_c ; // __W_BAD_BRANCH
// __I_IN_OPEN wire lfsr_out_7 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] postproc_out_b_tbo ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] rgb_c_tbo_1 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] rgb_c_tbo_2 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire scan_out_7 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [6:6] test_in_0 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [6:6] test_out_0 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire test_pad_oen_0 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [2:2] ts_adc_samples_1 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [2:2] ts_adc_samples_2 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] ts_intsig1 ; // __W_BAD_BRANCH
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign BC_RA_02_fail = BC_RA_02_fail_i; // __I_I_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for iom_i2s_ws_out1
wire mix_dmy_open_0; //__I_OPEN_DUMMY
wire mix_dmy_open_1; //__I_OPEN_DUMMY
wire mix_dmy_open_2; //__I_OPEN_DUMMY
wire mix_dmy_open_3; //__I_OPEN_DUMMY
wire mix_dmy_open_4; //__I_OPEN_DUMMY
wire mix_dmy_open_5; //__I_OPEN_DUMMY
wire mix_dmy_open_6; //__I_OPEN_DUMMY
wire mix_dmy_open_7; //__I_OPEN_DUMMY
wire mix_dmy_open_8; //__I_OPEN_DUMMY
wire mix_dmy_open_9; //__I_OPEN_DUMMY
wire mix_dmy_open_10; //__I_OPEN_DUMMY
wire mix_dmy_open_11; //__I_OPEN_DUMMY
wire mix_dmy_open_12; //__I_OPEN_DUMMY
wire mix_dmy_open_13; //__I_OPEN_DUMMY
wire mix_dmy_open_14; //__I_OPEN_DUMMY
iom_24 iom_i2s_ws_out1 (
.dot_i({ 1'b0, lfsr_out_7, test_out_0, 1'b0, 1'b0, i2s_ws_out1_out, i2s_ws_out1_out, 1'b0, 1'b0, ts_intsig1, rgb_c_tbo_2, rgb_c_tbo_1, cvbs_c_tbo_2, cvbs_c_tbo_1, postproc_out_b_tbo, 1'b0, 1'b0, BC_RA_02_fail, scan_out_7, i2s_ws_out1_out }), // __W_PORT (x7) // __I_BIT_TO_BUSPORT (x13) // __I_COMBINE_SPLICES
.ena_i({ 1'b0, 1'b1, test_pad_oen_0, 1'b0, 1'b0, i2s_ws_en_out1, i2s_ws_en_out1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, i2s_ws_en_out1 }), // __I_BIT_TO_BUSPORT (x20) // __I_COMBINE_SPLICES
.ret_o({ mix_dmy_open_6, mix_dmy_open_5, test_in_0, ts_adc_samples_2, ts_adc_samples_1, mix_dmy_open_4, mix_dmy_open_3, mix_dmy_open_2, mix_dmy_open_1, mix_dmy_open_0, mix_dmy_open_14, mix_dmy_open_13, mix_dmy_open_12, mix_dmy_open_11, mix_dmy_open_10, kl_123456a2345b_c, mix_dmy_open_9, mix_dmy_open_8, mix_dmy_open_7, i2s_ws_out1_in }) // __W_PORT (x4) // __I_BIT_TO_BUSPORT (x16) // __I_COMBINE_SPLICES
);
// End of Generated Instance Port Map for iom_i2s_ws_out1
endmodule
//
// End of Generated Module rtl of avfb_pad_mux
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_1_V
`define SKY130_FD_SC_HD__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_1_V
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (n % 2 == 0) cout << a[n / 2 - 1]; else cout << a[(n + 1) / 2 - 1]; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_TB_V
`define SKY130_FD_SC_HD__DLYMETAL6S4S_TB_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlymetal6s4s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__dlymetal6s4s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_TB_V
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Content Addressable Memory
*/
module cam #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// CAM style (SRL, BRAM)
parameter CAM_STYLE = "SRL",
// width of data bus slices
parameter SLICE_WIDTH = 4
)
(
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire write_enable,
output wire write_busy,
input wire [DATA_WIDTH-1:0] compare_data,
output wire [2**ADDR_WIDTH-1:0] match_many,
output wire [2**ADDR_WIDTH-1:0] match_single,
output wire [ADDR_WIDTH-1:0] match_addr,
output wire match
);
generate
if (CAM_STYLE == "SRL") begin
cam_srl #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
)
cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
end else if (CAM_STYLE == "BRAM") begin
cam_bram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
)
cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int prime(int n) { int val = sqrt(n), counter = 0; ; if (n == 1) return false; for (int i = 2; i <= val; i++) { if (!(n % i)) counter++; } if (counter) return -1; return n; } int root(int n) { int val = sqrt(n); int x = n, flag = 0; ; for (int i = 2; i <= val; i++) { if (!(n % i)) { while (n > 1) { if (n % i != 0) { flag = 1; break; } n = n / i; } if (flag) return -1; return x; } } return -1; } int main() { int n, counter = 0, val, val1; vector<int> vec; ; cin >> n; for (int i = 2; i <= n; i++) { val = prime(i); val1 = root(i); if (val != -1) { counter++; vec.push_back(val); } else if (val1 != -1) { counter++; vec.push_back(val1); } } cout << counter << endl; for (int i = 0; i < counter; i++) cout << vec[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; string nb; int main() { int N; cin >> N; cin >> nb; string m; m.append(N, 9 ); string act = nb; for (int shift = 0; shift < N; shift++) { for (int p = 0; p <= 9; p++) { m = min(m, act); for (int i = 0; i < N; i++) act[i] = ((act[i] - 0 + 1) % 10 + 0 ); } char first = act[0]; for (int i = 1; i < N; i++) act[i - 1] = act[i]; act[N - 1] = first; } cout << m << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int k = 0; k < t; k++) { int x, y, d = 0; cin >> x >> y; if (x >= y || x > 3) { cout << YES << endl; d = 1; } if (d == 0) { if (x == 1) { cout << NO << endl; } else { if (y > 3) { cout << NO << endl; } else { cout << YES << endl; } } } } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e4 + 5; int a[MAXN]; int dp[MAXN][2005]; int solve(int n) { int len = 2005; for (int i = 1; i <= n; ++i) for (int j = 0; j < len; ++j) dp[i][j] = INT_MAX; for (int j = 0; j < len; ++j) dp[0][j] = j; for (int i = 1; i <= n; ++i) { for (int j = 0; j < len; ++j) { if (j >= a[i]) dp[i][j - a[i]] = min(dp[i][j - a[i]], dp[i - 1][j]); if (j + a[i] < len) dp[i][j + a[i]] = min(dp[i][j + a[i]], max(dp[i - 1][j], j + a[i])); } } int ans = INT_MAX; for (int j = 0; j < len; ++j) ans = min(ans, dp[n][j]); return ans; } int main() { int n, t; cin >> t; while (t--) { cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; cout << solve(n) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; string s; int x, y, len, a, b; int main() { cin >> s; len = s.length(); for (int i = 0; i < len; ++i) { if (s[i] == ( ) ++x; else if (s[i] == ) ) --x; else if (s[i] == # ) --x, ++y; if (x < 0) { puts( -1 ); exit(0); } } for (int i = 0; i < len; ++i) { if (s[i] == # ) { ++a; if (a == y) b -= x; --b; } if (s[i] == ( ) ++b; else if (s[i] == ) ) --b; if (b < 0) { puts( -1 ); exit(0); } } for (int i = 1; i < y; ++i) puts( 1 ); printf( %d , x + 1); return 0; } |
// Library - static, Cell - th22r, View - schematic
// LAST TIME SAVED: May 23 16:33:04 2014
// NETLIST TIME: May 23 16:33:10 2014
`timescale 1ns / 1ns
module th22r ( y, a, b, rsb );
output y;
input a, b, rsb;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th22r";
specparam CDS_VIEWNAME = "schematic";
endspecify
pfet_b P7 ( .b(cds_globals.vdd_), .g(rsb), .s(cds_globals.vdd_),
.d(net15));
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net24));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net24), .d(net15));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net24));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net35), .d(net15));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net35));
nfet_b N7 ( .d(net023), .g(rsb), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N4 ( .d(net22), .g(b), .s(net023), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net22), .g(a), .s(net023), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net15), .g(y), .s(net22), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net34), .g(a), .s(net023), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net15), .g(b), .s(net34), .b(cds_globals.gnd_));
inv I2 ( y, net15);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[500500], n, len, ans; int main() { scanf( %d , &n); ans = 0; for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < n; i++) { int k = i; len = 0; while (a[k + 1] != a[k] && k < n - 1) { len++; k++; } if (i != k) { if (a[i] == a[k]) for (i++; i < k; i++) a[i] = a[k]; else { int j; for (j = 1; j <= (k - i) / 2; j++) a[j + i] = a[i]; for (; j + i < k; j++) a[j + i] = a[k]; i = k; } } ans = (ans > len ? ans : len); } if (ans == n) ans--; printf( %d n , ans / 2); for (int i = 0; i < n; i++) { if (i == n - 1) cout << a[i] << endl; else cout << a[i] << ; } printf( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_2_V
`define SKY130_FD_SC_HS__MUX4_2_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 14:51:03 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_stub.v
// Design : RAT_Counter10bit_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Counter10bit,Vivado 2016.4" *)
module RAT_Counter10bit_0_0(Din, LOAD, INC, RESET, CLK, COUNT)
/* synthesis syn_black_box black_box_pad_pin="Din[0:9],LOAD,INC,RESET,CLK,COUNT[0:9]" */;
input [0:9]Din;
input LOAD;
input INC;
input RESET;
input CLK;
output [0:9]COUNT;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int MOD = 1e9 + 7; string ans = What are you doing at the end of the world? Are you busy? Will you save us? ; string a = What are you doing while sending ; string b = ? Are you busy? Will you send ; string c = ? ; vector<long long int> dp(N, 1e18 + 1); char get(long long int n, long long int k) { if (k >= dp[n]) return . ; if (n == 0) return ans[k]; if (k < a.size()) return a[k]; if (k < a.size() + dp[n - 1]) return get(n - 1, k - a.size()); if (k < a.size() + dp[n - 1] + b.size()) return b[k - a.size() - dp[n - 1]]; if (k < a.size() + dp[n - 1] + b.size() + dp[n - 1]) return get(n - 1, k - a.size() - dp[n - 1] - b.size()); if (k < a.size() + dp[n - 1] + b.size() + dp[n - 1] + c.size()) return c[k - a.size() - dp[n - 1] - b.size() - dp[n - 1]]; return . ; } void solve() { dp[0] = ans.size(); for (int i = 1; i < 60; ++i) { long long int k = (2 * dp[i - 1]) + a.size() + b.size() + c.size(); dp[i] = min(k, (long long int)1e18 + 1); } int q; cin >> q; while (q--) { long long int n, k; cin >> n >> k; cout << get(n, k - 1); } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) solve(); return 0; } |
module TestDriver();
//This module tests the driver module, which functions by listening for changes in the state, waiting for the state to settle, and then setting HIGH the level of the enable flag.
//
//Things to test are:
// (1) driver responds to changes in state and waits the appropriate number of clock cycles before setting enable
// (2) driver will continue to wait for state to settle as long as state changes before settle time is up.
// (3) enable remains HIGH for sufficient period of time
// (4) enable remains HIGH even if state changes while enable is HIGH.
//
//Ted Golfinopoulos, 20 Oct 2011
reg clk; //Clock
reg [6:0] state; //State input to driver.
wire enable; //Output from driver.
//Instantiate driver.
driver d(clk, state, enable);
initial begin
$dumpfile("driverTestBench.vcd");
$dumpvars;
end
initial begin
$display("\ttime\tstate\tenable");
$monitor("%d\t%b\t%b", $time, state, enable);
end
initial begin
#0 clk=1'b0; //Initialize clock.
state=7'b0; //Initialize state.
//Enable is not initialized.
//(1) check that driver responds to changes in state
//and waits the appropriate number of clock cycles before setting enable.
// (3) check that enable remains HIGH for sufficient period of time (2^5-1 clock posedges=31=62 time units)
#10 state=state+7'b1; //Change state.
#100 state=7'b1000; //Try a different state.
#100 state=7'b1000000; //Try a different state.
// (2) check that driver will continue to wait for state to settle
// as long as state changes before settle wait time (2^3-1=7 clock posedges=14 time units) is up.
repeat (10) #3 state=state+7'b1; //Keep changing state.
repeat (10) #13 state=state+7'b1; //Keep changing state.
// (4) enable remains HIGH even if state changes while enable is HIGH.
#100 state=state+7'b1;
repeat (3) #16 state=state+7'b1;
#100 $finish; //End the simulation.
end
always begin
#1 clk=~clk; //Invert clock.
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> bool mmax(T &m, const T q) { if (m < q) { m = q; return true; } else return false; } template <typename T> bool mmin(T &m, const T q) { if (m > q) { m = q; return true; } else return false; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long l, r, k; cin >> l >> r >> k; long long p = 1, f = 0; long long ans = 0; while (1) { if (p >= l) { if (p <= r) { f = 1; cout << p << ; } else break; } if ((p) > 1e18 / k) break; p *= k; } if (f == 0) cout << -1; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_0_V
`define SKY130_FD_SC_LP__MUX4_0_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_0 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_0 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_0_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } inline int read() { int res = 0, fl = 1; char r = getchar(); for (; !isdigit(r); r = getchar()) if (r == - ) fl = -1; for (; isdigit(r); r = getchar()) res = (res << 3) + (res << 1) + r - 48; return res * fl; } const int Maxn = 2e5 + 10; vector<pair<int, int> > g[Maxn]; long double val[Maxn]; int siz[Maxn]; void dfs(int now, int pa) { siz[now] = 1; for (int i = g[now].size() - 1; i >= 0; --i) { int nxt = g[now][i].first; if (pa == nxt) continue; val[nxt] += g[now][i].second; dfs(nxt, now); val[now] += val[nxt]; siz[now] += siz[nxt]; } } long long Time, t[Maxn]; bool cmp(pair<int, int> A, pair<int, int> B) { return val[A.first] > val[B.first]; } void Dfs(int now, int pa) { for (int i = g[now].size() - 1; i >= 0; --i) { int nxt = g[now][i].first; if (nxt == pa) continue; val[nxt] = 10000.00 * val[nxt] / siz[nxt]; } sort(g[now].begin(), g[now].end(), cmp); t[now] = Time; for (int i = g[now].size() - 1; i >= 0; --i) { int nxt = g[now][i].first; if (pa == nxt) continue; Time += g[now][i].second; Dfs(nxt, now); Time += g[now][i].second; } } int main() { int n = read(); for (int i = 1; i < n; ++i) { int x = read(), y = read(), z = read(); g[x].push_back(make_pair(y, z)); g[y].push_back(make_pair(x, z)); } dfs(1, 0); Dfs(1, 0); long double ans = 0; for (int i = 1; i <= n; ++i) ans += t[i]; printf( %.6Lf n , 1.00 * ans / (n - 1)); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__OR3B_BEHAVIORAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3b (
VPWR,
VGND,
X ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C_N ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_MS__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_ms__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_4TO2_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
wire [65:0] outData; // From fifo of fifo.v
wire [15:0] inData = crc[15:0];
wire [1:0] inWordPtr = crc[17:16];
wire wrEn = crc[20];
wire [1:0] wrPtr = crc[33:32];
wire [1:0] rdPtr = crc[34:33];
fifo fifo (
// Outputs
.outData (outData[65:0]),
// Inputs
.clk (clk),
.inWordPtr (inWordPtr[1:0]),
.inData (inData[15:0]),
.rdPtr (rdPtr),
.wrPtr (wrPtr),
.wrEn (wrEn));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop;
end
else if (cyc==91) begin
if (outData[63:0] != 64'hef77cd9b13a866f0) $stop;
end
else if (cyc==92) begin
if (outData[63:0] != 64'h2750cd9b13a866f0) $stop;
end
else if (cyc==93) begin
if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop;
end
else if (cyc==94) begin
if (outData[63:0] != 64'h9d41bc276f0984ea) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
outData,
// Inputs
clk, inWordPtr, inData, wrPtr, rdPtr, wrEn
);
parameter fifoDepthLog2 = 1;
parameter fifoDepth = 1<<fifoDepthLog2;
`define PTRBITS (fifoDepthLog2+1)
`define PTRBITSM1 fifoDepthLog2
`define PTRBITSM2 (fifoDepthLog2-1)
input clk;
input [1:0] inWordPtr;
input [15:0] inData;
input [`PTRBITSM1:0] wrPtr;
input [`PTRBITSM1:0] rdPtr;
output [65:0] outData;
input wrEn;
reg [65:0] outData;
// verilator lint_off VARHIDDEN
reg [65:0] fifo[0:fifoDepth-1];
// verilator lint_on VARHIDDEN
//reg [65:0] temp;
always @(posedge clk) begin
//$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]);
if (wrEn) begin
fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0];
// Equivelent to:
//temp = fifo[ wrPtr[`PTRBITSM2:0] ];
//temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0];
//fifo[ wrPtr[`PTRBITSM2:0] ] <= temp;
end
outData <= fifo[rdPtr[`PTRBITSM2:0]];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { long long ans = 1; while (b > 0) { if (b % 2 != 0) { ans = (ans * a) % 1000000007; } a = (a * a) % 1000000007; b >>= 1; } return ans; } int main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t = 1; cin >> t; while (t--) { long long d, m; cin >> d >> m; vector<int> v, p, q; long long z = 1, s = 1; v.push_back(1); for (int i = 2; i < 65; i++) { long long k = pow(2, i - 1); if (s + k < d) { v.push_back(k); s += k; } else { v.push_back(d - s); break; } } vector<long long> ha; ha.push_back(1); ha.push_back(0); for (int i = 0; i < v.size(); i++) { vector<long long> u; u.push_back(1); for (int j = 0; j < ha.size() - 1; j++) { u.push_back((ha[j] * v[i] + ha[j + 1]) % m); } u.push_back(0); ha = u; } long long sum = 0; for (int i = 1; i < ha.size(); i++) { sum += ha[i]; sum %= m; } cout << sum << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVER2_PP_BLACKBOX_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_BEHAVIORAL_V
`define SKY130_FD_SC_MS__OR4_BEHAVIORAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int a[6] = {3, 3, 3, 2, 2, 1}; const int b[6] = {2, 1, 0, 1, 0, 0}; const int inf = 1000000000; const double eps = 1e-6; int Dist[6]; double X[7]; int Round(double X) { int T = (int)X; if (T + 1 - X < eps) T++; return T; } bool Check(int Len) { static double G[7][7], A[7]; memset(G, 0, sizeof(G)); for (int i = 0; i < 6; i++) for (int j = 0; j < 7; j++) { bool F0 = (j + 1) & (1 << a[i]); bool F1 = (j + 1) & (1 << b[i]); G[i][j] = F0 ^ F1; } for (int i = 0; i < 7; i++) G[6][i] = 1; for (int i = 0; i < 6; i++) A[i] = Dist[i]; A[6] = Len; for (int i = 0; i < 7; i++) { if (!G[i][i]) { int P = i + 1; while (!G[P][i]) P++; for (int j = i; j < 7; j++) swap(G[i][j], G[P][j]); swap(A[i], A[P]); } for (int j = i + 1; j < 7; j++) if (G[j][i]) { double T = G[j][i] / G[i][i]; for (int k = i; k < 7; k++) G[j][k] -= G[i][k] * T; A[j] -= A[i] * T; } } for (int i = 6; i >= 0; i--) { X[i] = A[i] / G[i][i]; for (int j = 0; j < i; j++) A[j] -= X[i] * G[j][i]; } for (int i = 0; i < 7; i++) if (fabs(X[i] - Round(X[i])) > eps || X[i] < -eps) return false; return true; } int main() { for (int i = 0; i < 6; i++) scanf( %d , &Dist[i]); int Ans = -1, Sum = 0; for (int i = 0; i < 6; i++) Sum += Dist[i]; for (int i = Sum / 4; Ans == -1 && i <= Sum / 3; i++) if (Check(i)) Ans = i; printf( %d n , Ans); if (Ans == -1) return 0; string S[4]; for (int i = 0; i < 7; i++) { int M = Round(X[i]); for (int j = 0; j < M; j++) { S[0] += a ; for (int k = 1; k < 4; k++) S[k] += ((i + 1) & (1 << (3 - k))) ? b : a ; } } for (int i = 0; i < 4; i++) cout << S[i] << endl; return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sram_cs (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_V
`define SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void inp_out() {} int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); inp_out(); long long int n, w; cin >> n >> w; vector<long long int> a(n); for (long long int i = 0; i < n; ++i) { cin >> a[i]; } long long int val = 0, mx = w, mn = 0; for (long long int i = 0; i < n; ++i) { if (abs(a[i]) > w) { cout << 0; return 0; } val += a[i]; if (val > w) { cout << 0; return 0; } long long int val1 = min(w, w - val); long long int val2 = max(0ll, -val); mx = min(val1, mx); mn = max(val2, mn); } cout << max(0ll, mx - mn + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int l, r; cin >> l >> r; if (l * 2 <= r) { cout << l << << l * 2 << endl; } else { cout << -1 << << -1 << endl; } } return 0; } |
#include <bits/stdc++.h> void sort(int a[], int begin, int mid, int end) { int i = begin, j = mid + 1, k = 0, temp[end - begin + 1]; while (i <= mid && j <= end) { if (a[i] <= a[j]) temp[k++] = a[i++]; else temp[k++] = a[j++]; } for (; i <= mid; ++i) temp[k++] = a[i]; for (; j <= end; ++j) temp[k++] = a[j]; for (i = 0; i < k; ++i) a[begin + i] = temp[i]; } void partition(int a[], int begin, int end) { if (begin == end) return; int mid = (begin + end) / 2; partition(a, begin, mid); partition(a, mid + 1, end); sort(a, begin, mid, end); } int main() { int n; scanf( %d , &n); unsigned long long s = 0; int i, a[n + 1]; for (i = 1; i <= n; ++i) scanf( %d , &a[i]); partition(a, 1, n); for (i = 1; i <= n - 1; ++i) s = s + (a[i] * 1LL) * (i + 1); s = s + (a[n] * 1LL) * n; printf( %I64d n , s); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire sleepb ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
wire and0_out_X ;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, sleepb, DESTPWR, VGND );
and and0 (and0_out_X , pwrgood_pp1_out_sleepb, pwrgood_pp0_out_A);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp2 (X , and0_out_X, DESTPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int il[5]; int wyn = 0; void printState() {} int n; int main() { ios::sync_with_stdio(0); cin >> n; while (n--) { int tmp; cin >> tmp; il[tmp]++; } int tmp; if (il[1] > il[2]) { wyn += il[2]; il[3] += il[2]; il[1] -= il[2]; il[2] = 0; printState(); wyn += il[1] / 3 * 2; il[3] += il[1] / 3; il[1] = il[1] % 3; printState(); if (il[1] == 1 && il[3] > 0) { tmp = min(il[1], il[3]); wyn += tmp; il[1] -= tmp; il[3] -= tmp; il[4] += tmp; } else if (il[1] == 1) { printState(); tmp = min(1, il[4] / 2); il[1] -= tmp; il[4] -= 2 * tmp; wyn += 2 * tmp; } else if (il[1] == 2 && il[4] > 0) { wyn += il[1]; il[4] -= il[1]; il[3] += il[1] * 2; il[1] = 0; } else if (il[1] == 2) { tmp = min(il[1], il[3]); wyn += tmp; il[1] -= tmp; il[3] -= tmp; } printState(); } else { wyn += il[1]; il[3] += il[1]; il[2] -= il[1]; il[1] = 0; printState(); wyn += il[2] / 3 * 2; il[3] += il[2] / 3 * 2; il[2] = il[2] % 3; printState(); if (il[2] == 1 && il[4] > 0) { il[2] = 0; il[4] -= 1; il[3] += 2; wyn += 1; } else if (il[2] == 1 && il[3] >= 2) { il[3] -= 2; il[2] -= 1; il[4] += 2; wyn += 2; } else if (il[2] == 2) { il[4] += 1; il[2] -= 2; wyn += 2; } printState(); } cout << (il[2] + il[1] > 0 ? -1 : wyn) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 7; const int inf = 0x3f3f3f; char s[maxn]; char str[4] = RGB ; int main() { int q; scanf( %d , &q); while (q--) { int n, m; scanf( %d%d , &n, &m); scanf( %s , s); int minn = inf; n -= m; for (int i = 0; i <= n; i++) { for (int j = 0; j < 3; j++) { int jishu = 0, temp; temp = (j <= 1 ? j : 2); for (int k = 0; k < m; k++) { if (s[i + k] != str[(temp + k) % 3]) { jishu++; } } minn = min(minn, jishu); } } printf( %d n , minn); } } |
#include <bits/stdc++.h> using namespace std; int n, q; vector<int> l, r, x, y; vector<long long> sum; double ans(int x1, int y1, int x, int y) { long long a = y1 - y; long long b = x - x1; long long c = -a * x - b * y; double xs = -1.0 * c / a; int ll = 0, rr = n - 1; while (ll <= rr) { int md = (ll + rr) / 2; if (r[md] < xs) ll = md + 1; else rr = md - 1; } if (ll == n) return sum[n - 1]; double ans = 0; if (ll != 0) ans = sum[ll - 1]; if (l[ll] < xs) ans += xs - l[ll]; return ans; } int main() { int y1, a, b; cin >> y1 >> a >> b; cin >> n; l.resize(n); r.resize(n); for (int i = 0; i < n; ++i) cin >> l[i] >> r[i]; cin >> q; x.resize(q); y.resize(q); for (int i = 0; i < q; ++i) cin >> x[i] >> y[i]; sum.resize(n); sum[0] = r[0] - l[0]; for (int i = 1; i < n; ++i) sum[i] = sum[i - 1] + r[i] - l[i]; for (int i = 0; i < q; ++i) { cout << fixed << setprecision(10) << (ans(b, y1, x[i], y[i]) - ans(a, y1, x[i], y[i])) * (y[i] - y1) / y[i] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct candy { candy(int t, int h, int m) { this->type = t; this->height = h; this->mass = m; } int type; int height; int mass; bool operator<(const candy &c) const { return this->mass < c.mass; } bool operator>(const candy &c) const { return this->height < c.height; } }; int amount(int first, vector<candy> &all_candies, int x) { priority_queue<candy> candies0, candies1; int all_candies_index = 0; int max_height = x; int last_taken = 1 - first; int amount_taken = 0; while (true) { while (all_candies_index < all_candies.size()) { if (all_candies[all_candies_index].height > max_height) { break; } if (all_candies[all_candies_index].type == 0) { candies0.push(all_candies[all_candies_index]); } else { candies1.push(all_candies[all_candies_index]); } all_candies_index++; } if (last_taken) { if (candies0.empty()) { break; } amount_taken++; max_height += candies0.top().mass; candies0.pop(); last_taken = 0; } else { if (candies1.empty()) { break; } amount_taken++; max_height += candies1.top().mass; candies1.pop(); last_taken = 1; } } return amount_taken; } int main() { int n, x; scanf( %d%d , &n, &x); vector<candy> all_candies; for (int i = 0; i < n; ++i) { int t, h, m; scanf( %d%d%d , &t, &h, &m); all_candies.push_back(candy(t, h, m)); } sort(all_candies.begin(), all_candies.end(), std::greater<candy>()); printf( %d n , max(amount(0, all_candies, x), amount(1, all_candies, x))); return 0; } |
#include <bits/stdc++.h> using namespace std; string doen() { char c; string waarde; while (cin.get(c) && c != n ) { waarde += c; } int aantal = stoi(waarde); string iets; getline(cin, iets); for (int i = 0; i < iets.length(); i = i + 2) { if (iets[i] == 1 ) { return HARD ; } } return EASY ; } int main() { cout << doen(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAXN = 5e5 + 5; struct Node { long long t, h, m; } a[MAXN]; bool cmp(Node x, Node y) { return x.m > y.m; } long long n, x; long long vis[MAXN]; long long solve(long long now) { memset(vis, 0, sizeof(vis)); long long ans = 0; long long h = x; while (1) { long long f = 0; for (long long i = 1; i <= n; i++) { if (vis[i] == 0 && now != a[i].t && h >= a[i].h) { f = 1; now = 1 - now; vis[i] = 1; ans++; h += a[i].m; break; } } if (f == 0) { break; } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> x; for (long long i = 1; i <= n; i++) { cin >> a[i].t >> a[i].h >> a[i].m; } sort(a + 1, a + n + 1, cmp); long long ans = max(solve(1), solve(0)); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, x, y, i, j, k, l; cin >> n >> m >> x >> y; cout << x << << y << n ; for (i = 1; i <= m; i++) if (i != y) cout << x << << i << n ; int c; for (i = 1, j = m; i <= n; i++) if (i != x) for (k = 1; k <= m; k++) { cout << i << << j << n ; if (j == m) c = -1; else if (j == 1) c = 1; if (k != m) j += c; } return 0; } |
module Mux4_1(
input [31:0] Data0,Data1,Data2,Data3,
input [1:0] Sel,
output [31:0]Data
);
assign Data = (Sel[1] == 1'b0)?((Sel[0] == 1'b0)?(Data0):(Data1)):((Sel[0] == 1'b0)?(Data2):(Data3));
endmodule
module MIPS_Shifter(
input[31:0] Data_in,
input [4:0] Count,
input [1:0] Sel,
output [31:0]Data_out
);
wire[31:0] ShiftData0,ShiftData1,ShiftData2,ShiftData3;
wire[1:0] Select;
wire HighBit;
assign HighBit = (Sel[1] == 1'b1)?(Data_in[31]):(1'b0);
assign Select[1] = Sel[1]|Sel[0];
assign Select[0] = ~(Sel[1]^Sel[0]);
Mux4_1 Mux1(Data_in,{Data_in[30:0],1'b0},{HighBit,Data_in[31:1]},{Data_in[0],Data_in[31:1]},{Select[1]&Count[0],Select[0]&Count[0]},ShiftData0);
Mux4_1 Mux2(ShiftData0,{ShiftData0[29:0],2'b0},{HighBit,HighBit,ShiftData0[31:2]},{ShiftData0[1:0],ShiftData0[31:2]},{Select[1]&Count[1],Select[0]&Count[1]},ShiftData1);
Mux4_1 Mux3(ShiftData1,{ShiftData1[27:0],4'b0},{{4{HighBit}},ShiftData1[31:4]},{ShiftData1[3:0],ShiftData1[31:4]},{Select[1]&Count[2],Select[0]&Count[2]},ShiftData2);
Mux4_1 Mux4(ShiftData2,{ShiftData2[23:0],8'b0},{{8{HighBit}},ShiftData2[31:8]},{ShiftData2[7:0],ShiftData2[31:8]},{Select[1]&Count[3],Select[0]&Count[3]},ShiftData3);
Mux4_1 Mux5(ShiftData3,{ShiftData3[15:0],16'b0},{{16{HighBit}},ShiftData3[31:16]},{ShiftData3[15:0],ShiftData3[31:16]},{Select[1]&Count[4],Select[0]&Count[4]},Data_out);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 9; set<pair<int, int> > len, pos; int n, m; void add_seg(int L, int R) { if (L > R) return; int sz = R - L + 1; pos.insert(make_pair(L, sz)); if (L != 1 && R != n) sz = (sz + 1) / 2; len.insert(make_pair(sz, L)); } void rem_seg(int L, int R) { if (L > R) return; int sz = R - L + 1; pos.erase(make_pair(L, sz)); if (L != 1 && R != n) sz = (sz + 1) / 2; len.erase(make_pair(sz, L)); } int loc[N]; void add(int x) { auto it = len.end(); --it; int opt = it->first; it = len.lower_bound(make_pair(opt, -1)); auto segt = pos.lower_bound(make_pair(it->second, -1)); int L = segt->first; int R = L + (segt->second) - 1; rem_seg(L, R); int M = (L + R) / 2; if (L == 1) M = 1; else if (R == n) M = R; cout << M << n ; loc[x] = M; add_seg(L, M - 1); add_seg(M + 1, R); } void rem(int x) { int pp = loc[x]; loc[x] = 0; int L = pp, R = pp; auto v2 = pos.lower_bound(make_pair(pp + 1, -1)); if (v2 != pos.end() && v2->first == pp + 1) { R = (v2->first) + (v2->second) - 1; rem_seg(v2->first, (v2->first) + (v2->second) - 1); } v2 = pos.lower_bound(make_pair(pp + 1, -1)); if (v2 != pos.begin()) { --v2; if ((v2->first) + (v2->second) - 1 == pp - 1) { L = v2->first; rem_seg(v2->first, pp - 1); } } add_seg(L, R); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n >> m; add_seg(1, n); int typ; int id; for (int i = 0; i < m; i++) { cin >> typ >> id; if (typ == 1) add(id); else rem(id); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int B = 250; int p1 = 5000000, p2 = 0; char buf[5000005], wbuf[5000005]; int gc() { if (p1 >= 5000000) fread(buf, 1, 5000000, stdin), p1 = 0; return buf[p1++]; } int rd() { int x = 0, ch = gc(); while (!isdigit(ch)) ch = gc(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = gc(); return x; } struct T { int x, id; } tmp[100005]; int bx[100005], bid[100005], cx[100005], cid[100005], nowans[100005]; int a[100005], pre[100005], bel[100005], S[100005], E[100005], dfn[100005], tag[100005]; int size[100005], son[100005], n, m, fa[100005], is[100005], top[100005], sign, sum = 1, ts = 0; vector<int> g[100005]; const bool operator<(const T i, const T j) { return i.x < j.x; } void dfs(int x) { size[x] = 1; for (int y : g[x]) { dfs(y), size[x] += size[y]; if (size[y] > size[son[x]]) son[x] = y; } } void dfs2(int x, int tp) { top[x] = tp, dfn[x] = ++sign; if (son[x]) dfs2(son[x], tp); else { int l = dfn[top[x]], r = dfn[x], t = 100; if (r - l < 10) { for (int i = l; i <= r; i++) bel[i] = sum; if (r - ts >= 250) sum++, ts = r; return; } if (sqrt(r - l + 1) >= t) t = sqrt(r - l + 1), t = min(t, 250); for (int i = l; i <= r; i++) bel[i] = (i - l) / t + sum; sum = bel[r] + 1, ts = r; } for (int y : g[x]) if (y ^ son[x]) dfs2(y, y); } void Make(int x) { for (int s = S[bel[x]], e = E[bel[x]], i = s; i <= e; i++) { if (bid[i] == x) { int dlt = 1 - 2 * is[x]; while (i <= e) pre[i] += dlt, i++; } } is[x] ^= 1; } void Addb(int p, int l, int r, int x) { int tc = 0, s = S[p], e = E[p]; for (int i = s; i <= e; i++) bx[i] += tag[p]; tag[p] = 0, nowans[p] = -1; int L = s, R = e; while (bid[L] < l || bid[L] > r) L++; while (bid[R] < l || bid[R] > r) R--; while (L > s && bx[L - 1] == bx[L]) L--; while (R < e && bx[R + 1] == bx[R]) R++; for (int i = L, j; i <= R; i = j + 1) { j = i; while (j < R && bx[j + 1] == bx[i]) j++; if (x == 1) { for (int k = i; k <= j; k++) if (bid[k] < l || bid[k] > r) cid[++tc] = bid[k], cx[tc] = bx[k]; for (int k = i; k <= j; k++) if (bid[k] >= l && bid[k] <= r) cid[++tc] = bid[k], cx[tc] = bx[k] + 1; } else { for (int k = i; k <= j; k++) if (bid[k] >= l && bid[k] <= r) cid[++tc] = bid[k], cx[tc] = bx[k] - 1; for (int k = i; k <= j; k++) if (bid[k] < l || bid[k] > r) cid[++tc] = bid[k], cx[tc] = bx[k]; } } for (int i = L; i <= R; i++) bx[i] = cx[i - L + 1], bid[i] = cid[i - L + 1]; for (int i = L; i <= e; i++) pre[i] = (i == s ? 0 : pre[i - 1]) + is[bid[i]]; } void Add(int l, int r, int x) { Addb(bel[l], l, r, x); if (bel[l] == bel[r]) return; Addb(bel[r], l, r, x); for (int i = bel[l] + 1; i < bel[r]; i++) tag[i] += x, nowans[i] = -1; } int Query() { int ans = 0; for (int i = 1; i <= bel[n]; i++) { if (nowans[i] != -1) { ans += nowans[i]; continue; } int pos = lower_bound(bx + S[i], bx + E[i] + 1, -tag[i]) - bx - 1; if (pos >= S[i]) ans += pre[pos], nowans[i] = pre[pos]; else nowans[i] = 0; } return ans; } void Upd(int x) { int p = dfn[x]; while (x) Add(dfn[top[x]], dfn[x], 1 - 2 * is[p]), x = fa[top[x]]; Make(p); } int main() { n = rd(), m = rd(); for (int i = 2, x; i <= n; i++) x = rd(), fa[i] = x, g[x].push_back(i); dfs(1), dfs2(1, 1); for (int i = 1; i <= n; i++) a[i] = rd(), is[i] = 1, tmp[dfn[i]] = {a[i], dfn[i]}; for (int i = 1; i <= n; i++) E[bel[i]] = i; for (int i = n; i >= 1; i--) S[bel[i]] = i; for (int i = 1; i <= bel[n]; i++) { nowans[i] = -1; int s = S[i], e = E[i]; sort(tmp + s, tmp + e + 1); for (int j = s; j <= e; j++) pre[j] = j - s + 1, bx[j] = tmp[j].x, bid[j] = tmp[j].id; } while (m--) { int x = rd(); Upd(x); printf( %d , Query()); } } |
#include <bits/stdc++.h> using namespace std; int main() { bool v[60], h[60]; int a, b, n; while (cin >> n) { memset(v, false, sizeof(v)); memset(h, false, sizeof(h)); for (int i = 1; i <= n * n; i++) { cin >> a >> b; if (i == 1) { cout << 1; h[a] = true; v[b] = true; } else if (h[a] == false && v[b] == false) { h[a] = true; v[b] = true; cout << << i; } } cout << endl; } return 0; } |
/**************************************************************************
Async Fifo
-parameter N
Queue data vector width
Example : DATA[3:0] is N=4
-parameter DEPTH
Queue entry depth
Example DEPTH 16 is DEPTH=16
-parameter D_N
Queue entry depth n size
Example PARAMETER_DEPTH16 is 4
-SDF Settings
Asynchronus Clock : iWR_CLOCK - iRD_CLOCK
-Make : 2013/2/13
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032sa_async_fifo
#(
parameter N = 16,
parameter DEPTH = 4,
parameter D_N = 2
)
(
//System
input wire inRESET,
//Remove
input wire iREMOVE,
//WR
input wire iWR_CLOCK,
input wire iWR_EN,
input wire [N-1:0] iWR_DATA,
output wire oWR_FULL,
//RD
input wire iRD_CLOCK,
input wire iRD_EN,
output wire [N-1:0] oRD_DATA,
output wire oRD_EMPTY
);
//Full
wire [D_N:0] full_count;
wire full;
wire [D_N:0] empty_count;
wire empty;
//Memory
reg [N-1:0] b_memory[0:DEPTH-1];
//Counter
reg [D_N:0] b_wr_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
reg [D_N:0] b_rd_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
wire [D_N:0] gray_d_fifo_rd_counter;
wire [D_N:0] binary_d_fifo_rd_counter;
wire [D_N:0] gray_d_fifo_wr_counter;
wire [D_N:0] binary_d_fifo_wr_counter;
//Assign
assign full_count = b_wr_counter - binary_d_fifo_rd_counter;
assign full = full_count[D_N] || (full_count[D_N-1:0] == {D_N{1'b1}})? 1'b1 : 1'b0;
//Empty
assign empty_count = binary_d_fifo_wr_counter - (b_rd_counter);
assign empty = (empty_count == {D_N+1{1'b0}})? 1'b1 : 1'b0;
/***************************************************
Memory
***************************************************/
//Write
always@(posedge iWR_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_wr_counter <= {D_N{1'b0}};
end
else if(iREMOVE)begin
b_wr_counter <= {D_N{1'b0}};
end
else begin
if(iWR_EN && !full)begin
b_memory[b_wr_counter[D_N-1:0]] <= iWR_DATA;
b_wr_counter <= b_wr_counter + {{D_N-1{1'b0}}, 1'b1};
end
end
end
//Read Pointer
always@(posedge iRD_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_rd_counter <= {D_N{1'b0}};
end
else if(iREMOVE)begin
b_rd_counter <= {D_N{1'b0}};
end
else begin
if(iRD_EN && !empty)begin
b_rd_counter <= b_rd_counter + {{D_N-1{1'b0}}, 1'b1};
end
end
end
/***************************************************
Counter Buffer
***************************************************/
mist1032sa_async_fifo_double_flipflop #(D_N+1) D_FIFO_READ(
.iCLOCK(iWR_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_rd_counter)),
.oOUT_DATA(gray_d_fifo_rd_counter)
);
assign binary_d_fifo_rd_counter = gray2bin(gray_d_fifo_rd_counter);
mist1032sa_async_fifo_double_flipflop #(D_N+1) D_FIFO_WRITE(
.iCLOCK(iRD_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_wr_counter)),
.oOUT_DATA(gray_d_fifo_wr_counter)
);
assign binary_d_fifo_wr_counter = gray2bin(gray_d_fifo_wr_counter);
/***************************************************
Function
***************************************************/
function [D_N:0] bin2gray;
input [D_N:0] binary;
begin
bin2gray = binary ^ (binary >> 1'b1);
end
endfunction
function[D_N:0] gray2bin(input[D_N:0] gray);
integer i;
for(i=D_N; i>=0; i=i-1)begin
if(i==D_N)begin
gray2bin[i] = gray[i];
end
else begin
gray2bin[i] = gray[i] ^ gray2bin[i+1];
end
end
endfunction
/***************************************************
Output Assign
***************************************************/
assign oWR_FULL = full;
assign oRD_EMPTY = empty;
assign oRD_DATA = b_memory[b_rd_counter[D_N-1:0]];
endmodule
`default_nettype wire
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_down_converter(clock, resetn, i_start,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATAIN_WIDTH = 32;
parameter DATAOUT_WIDTH = 8;
input clock, resetn, i_start;
input [DATAIN_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATAOUT_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
// Specify state machine states.
parameter s_IDLE = 3'b100;
parameter s_SEND_B1 = 3'b000;
parameter s_SEND_B2 = 3'b001;
parameter s_SEND_B3 = 3'b010;
parameter s_SEND_B4 = 3'b011;
// State and next_state variables
reg [2:0] present_state, next_state;
reg [DATAIN_WIDTH-1:0] data_to_send;
wire latch_new_data;
// Simple state machine to output 1 byte per cycle
always@(*)
begin
case (present_state)
s_IDLE: if (i_datain_valid)
next_state <= s_SEND_B1;
else
next_state <= s_IDLE;
s_SEND_B1: if (!i_dataout_stall)
next_state <= s_SEND_B2;
else
next_state <= s_SEND_B1;
s_SEND_B2: if (!i_dataout_stall)
next_state <= s_SEND_B3;
else
next_state <= s_SEND_B2;
s_SEND_B3: if (!i_dataout_stall)
next_state <= s_SEND_B4;
else
next_state <= s_SEND_B3;
s_SEND_B4: if (!i_dataout_stall)
next_state <= i_datain_valid ? s_SEND_B1 : s_IDLE;
else
next_state <= s_SEND_B4;
default: next_state <= 3'bxxx;
endcase
end
// Simple state machine to output 1 byte per cycle
always@(posedge clock or negedge resetn)
begin
if (~resetn)
data_to_send <= {DATAIN_WIDTH{1'b0}};
else
data_to_send <= (latch_new_data & i_datain_valid) ?
i_datain : data_to_send;
end
// State assignment
always@(posedge clock or negedge resetn)
begin
if (~resetn)
present_state <= s_IDLE;
else
present_state <= (i_start) ? next_state : s_IDLE;
end
//assign o_dataout = (present_state == s_SEND_B1) ? data_to_send[DATAOUT_WIDTH-1:0] :
// ((present_state == s_SEND_B2) ? data_to_send[2*DATAOUT_WIDTH-1:DATAOUT_WIDTH] :
// ((present_state == s_SEND_B3) ? data_to_send[3*DATAOUT_WIDTH-1:2*DATAOUT_WIDTH] :
// data_to_send[4*DATAOUT_WIDTH-1:3*DATAOUT_WIDTH] ));
assign o_dataout = data_to_send[present_state[1:0]*DATAOUT_WIDTH +: DATAOUT_WIDTH];
//assign o_dataout_valid = (present_state != s_IDLE);
assign o_dataout_valid = ~present_state[2] & i_start;
//we latch data in the idle state, or if we're in the send_b4 state,
// and downstream is not stalling back
assign latch_new_data = (present_state == s_IDLE) ||
((present_state == s_SEND_B4) & ~i_dataout_stall);
// we want to lower the stall to the inputs when we want to latch new data
assign o_datain_stall = (i_start) ? ~latch_new_data : 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:41 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_zed_hdmi_0_0 -prefix
// system_zed_hdmi_0_0_ system_zed_hdmi_0_0_stub.v
// Design : system_zed_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_hdmi,Vivado 2016.4" *)
module system_zed_hdmi_0_0(clk, clk_x2, clk_100, active, hsync, vsync, rgb888,
hdmi_clk, hdmi_hsync, hdmi_vsync, hdmi_d, hdmi_de, hdmi_scl, hdmi_sda)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda" */;
input clk;
input clk_x2;
input clk_100;
input active;
input hsync;
input vsync;
input [23:0]rgb888;
output hdmi_clk;
output hdmi_hsync;
output hdmi_vsync;
output [15:0]hdmi_d;
output hdmi_de;
output hdmi_scl;
inout hdmi_sda;
endmodule
|
#include <bits/stdc++.h> int compare(const void *a, const void *b) { return *(int *)a - *(int *)b; } int main() { int n, k; scanf( %d%d , &n, &k); int i; if ((n == 1 && k == 1)) { printf( -1 n ); return 0; } if (n == k) { printf( -1 n ); return 0; } if ((n - k) % 2 != 0) { printf( 1 ); for (i = 2; i <= ((n - k) - (n - k) % 2); i += 2) { printf( %d %d , i + 1, i); } for (i = n - k + 1; i <= n; i++) printf( %d , i); } else { for (i = 1; i <= (n - k); i += 2) { printf( %d %d , i + 1, i); } for (i = n - k + 1; i <= n; i++) printf( %d , i); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; struct hashed_str { long long n; vector<long long> hs; vector<long long> pows; long long p = 61; long long mod = 1e9 + 7; hashed_str(string &s) { n = s.size(); long long n1 = (int)s.size(); pows = {1}; for (int i = 1; i < n; i++) { pows.push_back((pows.back() * p) % mod); } hs.resize(n1); hs[0] = (long long)((s[0] - a ) + 1); for (int i = 1; i < n1; i++) { hs[i] = (hs[i - 1] % mod + (pows[i] * (long long)(s[i] - a + 1ll)) % mod) % mod; } } long long get(long long l, long long r) { if (l > r) { return 0; } long long a = (l ? hs[l - 1] : 0); long long b = hs[r]; long long s = (b - a + mod) % mod; return (s * pows[n - l - 1]) % mod; } }; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; string t; string s; cin >> s >> t; long long n = t.size(); hashed_str hs(t); long long cnt_0 = 0, cnt_1 = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == 0 ) { cnt_0++; } else { cnt_1++; } } char aa = 0 ; char bb = 1 ; long long a = cnt_0; long long b = cnt_1; if (s[0] == 1 ) { swap(a, b); swap(aa, bb); } if (b == 0) { if (n % a != 0) { cout << 0; return 0; } long long len_a = n / a; long long hash_a = hs.get(0, len_a - 1); long long hash_b = -1; long long ptr = len_a; bool ok = 1; for (int i = 1; i < s.size(); i++) { long long cur_h = hs.get(ptr, ptr + len_a - 1); if (cur_h != hash_a) { ok = 0; break; } ptr += len_a; } cout << ok; return 0; } long long answ = 0; for (int i = 0; i < t.size(); i++) { long long len_a = i + 1; if ((n - len_a * a) % b != 0 || n - len_a * a <= 0) { continue; } long long len_b = (n - len_a * a) / b; long long hash_a = hs.get(0, len_a - 1); long long hash_b = -1; long long ptr = len_a; bool ok = 1; for (int j = 1; j < s.size(); j++) { if (s[j] == aa) { long long cur_h = hs.get(ptr, ptr + len_a - 1); if (cur_h != hash_a) { ok = 0; break; } ptr += len_a; } else { long long cur_h = hs.get(ptr, ptr + len_b - 1); if (hash_b == -1) { hash_b = cur_h; } if (cur_h != hash_b) { ok = 0; break; } ptr += len_b; } } if (hash_a == hash_b) { ok = 0; } answ += ok; } cout << answ; } |
#include <bits/stdc++.h> using namespace std; int x[2000], y[2000], c[2000]; vector<int> poss; multiset<int> xx[2000]; vector<pair<int, int> > events; map<pair<int, int>, int> M; long long int sum = 0, ans = 0; int update(int e, int m) { if (e < 0) return 0; auto it = M.upper_bound(make_pair(e, 2e9)); it--; if (it->first.second != e) { pair<int, int> p = it->first; int v = it->second; M.erase(it); M[make_pair(p.first, e)] = v; M[make_pair(e + 1, p.second)] = v; } it = M.upper_bound(make_pair(e, 2e9)); it--; if (it->second < m) return 0; pair<int, int> p = make_pair(e, e); while (it->second >= m) { p.first = it->first.first; sum -= (long long int)(it->first.second - it->first.first + 1) * it->second; it = M.erase(it); if (it == M.begin()) break; else it--; } M[p] = m; sum += (long long int)(p.second - p.first + 1) * m; return 0; } int main() { int i; int n, k, L; scanf( %d %d %d , &n, &k, &L); poss.push_back(-1), poss.push_back(L); for (i = 0; i < n; i++) { scanf( %d %d %d , &x[i], &y[i], &c[i]), c[i]--; poss.push_back(y[i]); } sort(poss.begin(), poss.end()); poss.resize(unique(poss.begin(), poss.end()) - poss.begin()); int j; for (i = 1; i < poss.size(); i++) { int yy = poss[i] - poss[i - 1]; for (j = 0; j < n; j++) { if (y[j] > poss[i - 1]) { events.push_back(make_pair(y[j], j)); xx[c[j]].insert(x[j]); } } M.clear(); M[make_pair(0, L - 1)] = L, sum = (long long int)L * L; for (j = 0; j < k; j++) { if (xx[j].empty()) break; int p = -1; for (auto it = xx[j].begin(); it != xx[j].end(); it++) update(*it - 1, p + 1), p = *it; update(L - 1, p + 1); } if (j < k) break; sort(events.begin(), events.end(), greater<pair<int, int> >()); int l = L; for (j = 0; j < events.size(); j++) { int u = events[j].second; long long int nn = (long long int)yy * (l - events[j].first); nn %= 1000000007; ans += nn * (sum % 1000000007), ans %= 1000000007; auto it = xx[c[u]].lower_bound(x[u]); it = xx[c[u]].erase(it); int a = (it == xx[c[u]].end()) ? L - 1 : *it - 1; int b = (it == xx[c[u]].begin()) ? 0 : *(--it) + 1; update(a, b); if (xx[c[u]].empty()) break; l = events[j].first; } for (j = 0; j < k; j++) xx[j].clear(); events.clear(); } printf( %I64d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2B_2_V
`define SKY130_FD_SC_HDLL__OR2B_2_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2b_2 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2B_2_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> h[100010], h1[100010]; long long cnt[100010], pre[100010], sum[100010]; int num[100010], mx[100010], n, tt, t1; inline int rd() { int x = 0; char ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) ; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return x; } inline int gcd(int x, int y) { return (!y) ? x : gcd(y, x % y); } inline long long calc(long long l, long long r) { return (l + r) * (r - l + 1) / 2; } inline long long anol_gcd(long long n, long long a, long long b, long long c) { if (n < 0) return 0; if (!a) return (b / c) * (n + 1); if (a >= c || b >= c) return (a / c) * n * (n + 1) / 2 + (b / c) * (n + 1) + anol_gcd(n, a % c, b % c, c); long long hh = (a * n + b) / c; return n * hh - anol_gcd(hh - 1, c, c - b - 1, a); } inline long long gao(int x, int y, long long mid) { if (!cnt[x] || !cnt[y]) return 0; mid -= pre[y - 1] - pre[x]; if (mid < 0) return 0; long long mn = (mid - cnt[y] * y) / x; mn = max(mn, 0LL); if (mn >= cnt[x]) return cnt[x] * cnt[y]; long long res = mn * cnt[y]; mn++; long long mx = mid / x; mx = min(mx, cnt[x]); if (mn <= mx) res += anol_gcd(mx - mn, x, mid - mx * x, y); return res; } inline long long check(long long mid) { long long res = 0; int now = 1; for (int i = 1; i <= 100000; i++) { now = max(now, i); long long hh = min(mid / i, cnt[i]); if (cnt[i]) res += calc(cnt[i] - hh + 1, cnt[i]); while (now + 1 <= 100000 && pre[now + 1] - pre[i - 1] <= mid) now++; res += (sum[now] - sum[i]) * cnt[i]; mx[i] = now; } for (int i = 1; i <= 100000; i++) for (int j = mx[i] + 1; j <= min(mx[i + 1] + 1, 100000); j++) res += gao(i, j, mid); return res; } int main() { n = rd(); for (int i = 1; i <= n; i++) num[i] = rd(); cnt[num[1]]++; h[tt = 1] = pair<int, int>(1, num[1]); for (int i = 2; i <= n; i++) { t1 = tt; for (int j = 1; j <= t1; j++) h1[j] = h[j], h1[j].second = gcd(h1[j].second, num[i]); h1[++t1] = pair<int, int>(1, num[i]); tt = 0; for (int j = 1; j <= t1;) { int k = j, now = 0; for (; k <= t1 && h1[k].second == h1[j].second; k++) now += h1[k].first; h[++tt] = pair<int, int>(now, h1[j].second); j = k; } for (int j = 1; j <= tt; j++) cnt[h[j].second] += h[j].first; } for (int i = 1; i <= 100000; i++) pre[i] = pre[i - 1] + cnt[i] * i, sum[i] = sum[i - 1] + cnt[i]; long long all = (long long)n * (n + 1) / 2; all = all * (all + 1) / 2; all = (all + 1) / 2; long long l = 0, r = (long long)n * (n + 1) / 2 * 100000; while (l < r) { long long mid = (l + r) >> 1; if (check(mid) >= all) r = mid; else l = mid + 1; } printf( %lld n , l); return 0; } |
`define MAXQ 2
module uut (
input clk,
input d, r, e,
output [`MAXQ:0] q
);
reg q0;
always @(posedge clk) begin
if (r)
q0 <= 0;
else if (e)
q0 <= d;
end
reg q1;
always @(posedge clk, posedge r) begin
if (r)
q1 <= 0;
else if (e)
q1 <= d;
end
reg q2;
always @(posedge clk, negedge r) begin
if (!r)
q2 <= 0;
else if (!e)
q2 <= d;
end
assign q = {q2, q1, q0};
endmodule
`ifdef TESTBENCH
module \$ff #(
parameter integer WIDTH = 1
) (
input [WIDTH-1:0] D,
output reg [WIDTH-1:0] Q
);
wire sysclk = testbench.sysclk;
always @(posedge sysclk)
Q <= D;
endmodule
module testbench;
reg sysclk;
always #5 sysclk = (sysclk === 1'b0);
reg clk;
always @(posedge sysclk) clk = (clk === 1'b0);
reg d, r, e;
wire [`MAXQ:0] q_uut;
uut uut (.clk(clk), .d(d), .r(r), .e(e), .q(q_uut));
wire [`MAXQ:0] q_syn;
syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn));
wire [`MAXQ:0] q_prp;
prp prp (.clk(clk), .d(d), .r(r), .e(e), .q(q_prp));
wire [`MAXQ:0] q_a2s;
a2s a2s (.clk(clk), .d(d), .r(r), .e(e), .q(q_a2s));
wire [`MAXQ:0] q_ffl;
ffl ffl (.clk(clk), .d(d), .r(r), .e(e), .q(q_ffl));
task printq;
reg [5*8-1:0] msg;
begin
msg = "OK";
if (q_uut !== q_syn) msg = "SYN";
if (q_uut !== q_prp) msg = "PRP";
if (q_uut !== q_a2s) msg = "A2S";
if (q_uut !== q_ffl) msg = "FFL";
$display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg);
if (msg != "OK") $finish;
end
endtask
initial if(0) begin
$dumpfile("async.vcd");
$dumpvars(0, testbench);
end
initial begin
@(posedge clk);
d <= 0;
r <= 0;
e <= 0;
@(posedge clk);
e <= 1;
@(posedge clk);
e <= 0;
repeat (10000) begin
@(posedge clk);
printq;
d <= $random;
r <= $random;
e <= $random;
end
$display("PASS");
$finish;
end
endmodule
`endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_0_0 (
dout
);
output wire [4-1 : 0] dout;
xlconstant #(
.CONST_VAL(4'd3),
.CONST_WIDTH(4)
) inst (
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int max(int a, int b) { return a > b ? a : b; } inline int min(int a, int b) { return a < b ? a : b; } map<int, int> mp; int main() { int n, x; cin >> n; mp.clear(); for (int i(0); i < (n); ++i) { cin >> x; ++mp[x]; } long long ans(0); for (map<int, int>::iterator it = mp.begin(); it != mp.end() && it->first < 0; ++it) ans += (long long)it->second * (long long)mp[-it->first]; ans += (long long)mp[0] * ((long long)mp[0] - 1ll) / 2ll; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; void solve() { int n, m; cin >> n >> m; vector<string> f(n); for (int i = 0; i < n; ++i) { cin >> f[i]; } vector<int> v(m); for (int j = 1; j < m; ++j) { for (int i = 1; i < n; ++i) { if (f[i - 1][j] == X && f[i][j - 1] == X ) { v[j] = 1; } } } for (int i = 1; i < m; ++i) { v[i] += v[i - 1]; } int q; cin >> q; for (int i = 0; i < q; ++i) { int a, b; cin >> a >> b; if (v[b - 1] - v[a - 1] > 0) { cout << NO n ; } else { cout << YES n ; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); solve(); } |
#include <bits/stdc++.h> using namespace std; void input(vector<int>& v, int n) { int i, io; for (i = 0; i < n; i++) { cin >> io; v.push_back(io); } } void output(vector<long long> v) { long long i; for (i = 0; i < v.size(); i++) cout << v.at(i) << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); vector<int> v; int i; long long sum = 0; input(v, 4); string str; cin >> str; int n = str.length(); for (i = 0; i < n; i++) sum += v[str[i] - 0 - 1]; cout << sum << endl; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const int N = 100005; int i, n, k, x, y, lvl[N]; vector<int> g[N]; queue<int> q; int main() { ios_base::sync_with_stdio(0); memset(lvl, -1, sizeof(lvl)); cin >> n >> k; for (i = 1; i < n; ++i) { cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } for (i = 1; i <= n; ++i) if (g[i].size() == 1) q.push(i), lvl[i] = 0; for (; !q.empty(); q.pop()) { x = q.front(); if (lvl[x] == k) continue; vector<int> now; for (int to : g[x]) if (lvl[to] == -1 || lvl[to] == lvl[x] + 1) now.push_back(to); if (now.size() > 1) return cout << No n , 0; if (!now.size()) return cout << No n , 0; if (g[now[0]].size() < 4 - (lvl[x] + 1 == k)) return cout << No n , 0; if (lvl[now[0]] == -1) lvl[now[0]] = lvl[x] + 1, q.push(now[0]); } int cnt = 0; for (i = 1; i <= n; ++i) { if (lvl[i] > k) return cout << No n , 0; if (lvl[i] == k) ++cnt; if (cnt > 1) return cout << No n , 0; } cout << (!cnt ? No : Yes ) << n ; return 0; } |
#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef pair<int,int> pii; typedef vector<int> vi; typedef vector<vi> vvi; typedef vector<ll> vl; typedef vector<vl> vvl; typedef vector<string> vs; typedef vector<vs> vvs; typedef vector<pii> vpii; typedef set<int> si; typedef unordered_set<int> usi; typedef multiset<int> msi; typedef map<int,int> mi; typedef unordered_map<int,int> umi; typedef multimap<int,int> mmi; #define f1(a,b,c) for(int(a)=(b);(a)<(c);(a)++) #define f2(a,b,c) for(int(a)=(b);(a)<=(c);(a)++) #define f3(a,b,c) for(int(a)=(b);(a)>(c);(a)--) #define f4(a,b,c) for(int(a)=(b);(a)>=(c);(a)--) #define fi(a,b) for(auto(a)=b.begin();(a)!=b.end();(a)++) #define pb push_back #define all(v) v.begin(),v.end() #define nper next_permutation #define pper prev_permutation #define mp make_pair #define F first #define S second int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin>>t; f1(i,0,t) { int n,k,x=1; cin>>n>>k; f1(j,0,(2*k)-n-1) { cout<<x<< ;x++; } x=k; f1(j,0,n-k+1) { cout<<x<< ;x--; } cout<< n ; } /*f1(i,0,t) { cout<<v[i]<< n ; }*/ return 0; } |
#include <bits/stdc++.h> using namespace std; int i, t, n, ciel, jiro, aux, a[10005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); for (cin >> t; t; --t) { cin >> n; for (i = 1; i <= n; ++i) { cin >> aux; if (n & 1) if (i == n / 2 + 1) a[++a[0]] = aux; else if (i <= n / 2) ciel += aux; else jiro += aux; else if (i <= n / 2) ciel += aux; else jiro += aux; } } sort(a + 1, a + a[0] + 1); for (i = a[0]; i; --i) if ((a[0] - i) & 1) jiro += a[i]; else ciel += a[i]; cout << ciel << << jiro << n ; return 0; } |
//================================================================--
// Design Unit : sn74151 (behaviour)
//
// File Name : sn74151.v
//
// Purpose : SN74151
//
// Author : Daniel Guenther, Vancouver Island University
//
// Environmant : Icarus
//-------------------------------------------------------------------
// Revision List
// Version Author Date Changes
// 1.0 Daniel Guenther 2016-11-09 Filled in wires
//================================================================--
module sn74151 (P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16);
input wire P4, P3, P2, P1, P15, P14, P13, P12, P7, P11, P10, P9, P8, P16;
// I0 I1 I2 I3 I4 I5 I6 I7 E S0 S1 S2 GND VCC
output reg P5; // Z
output wire P6; // Z_BAR
assign P6 = ~P5;
always @(P1, P2, P3, P4, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16) begin
if ((P16 == 1'b 1) && (P8 == 1'b 0) && (P7 == 1'b 0)) begin
case ({P11,P10,P9})
3'b000: P5=P4;
3'b001: P5=P3;
3'b010: P5=P2;
3'b011: P5=P1;
3'b100: P5=P15;
3'b101: P5=P14;
3'b110: P5=P13;
3'b111: P5=P12;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; using pii = pair<int, int>; constexpr int ALPHABET_SIZE = z - a + 1; constexpr int MAX_SIZE = 256; constexpr int INF = 1e8; int n; string s; string as, bs, cs; vector<int> next_pos[ALPHABET_SIZE]; int calced_pos[MAX_SIZE][MAX_SIZE][MAX_SIZE]; int calced_mark[MAX_SIZE][MAX_SIZE][MAX_SIZE]; int added_mark[MAX_SIZE][MAX_SIZE][MAX_SIZE]; int dda[(int)3e5]; int ddb[(int)3e5]; int ddc[(int)3e5]; void promote(int s_pos, int mark, int type) { int dsize = 0; int dptr = 0; if (type == 1) { for (int bb = 0; bb <= bs.size(); bb++) { for (int cc = 0; cc <= cs.size(); cc++) { dda[dsize] = s_pos; ddb[dsize] = bb; ddc[dsize] = cc; dsize++; calced_mark[s_pos][bb][cc] = mark; added_mark[s_pos][bb][cc] = mark; } } } else if (type == 2) { for (int aa = 0; aa <= as.size(); aa++) { for (int cc = 0; cc <= cs.size(); cc++) { dda[dsize] = aa; ddb[dsize] = s_pos; ddc[dsize] = cc; dsize++; calced_mark[aa][s_pos][cc] = mark; added_mark[aa][s_pos][cc] = mark; } } } else { for (int aa = 0; aa <= as.size(); aa++) { for (int bb = 0; bb <= bs.size(); bb++) { dda[dsize] = aa; ddb[dsize] = bb; ddc[dsize] = s_pos; dsize++; calced_mark[aa][bb][s_pos] = mark; added_mark[aa][bb][s_pos] = mark; } } } while (dptr < dsize) { int a = dda[dptr]; int b = ddb[dptr]; int c = ddc[dptr]; dptr++; int &m = calced_mark[a][b][c]; m = mark; added_mark[a][b][c] = mark; int &pos = calced_pos[a][b][c]; if (a == 0 && b == 0 && c == 0) { pos = 0; } if (a < as.size()) { int &p = calced_pos[a + 1][b][c]; int &mm = calced_mark[a + 1][b][c]; int &am = added_mark[a + 1][b][c]; if (am != mark) { if (mm != mark) { p = INF; mm = mark; dda[dsize] = a + 1; ddb[dsize] = b; ddc[dsize] = c; dsize++; } if (pos < n) p = min(p, next_pos[as[a] - a ][pos] + 1); } } if (b < bs.size()) { int &p = calced_pos[a][b + 1][c]; int &mm = calced_mark[a][b + 1][c]; int &am = added_mark[a][b + 1][c]; if (am != mark) { if (mm != mark) { p = INF; mm = mark; dda[dsize] = a; ddb[dsize] = b + 1; ddc[dsize] = c; dsize++; } if (pos < n) p = min(p, next_pos[bs[b] - a ][pos] + 1); } } if (c < cs.size()) { int &p = calced_pos[a][b][c + 1]; int &mm = calced_mark[a][b][c + 1]; int &am = added_mark[a][b][c + 1]; if (am != mark) { if (mm != mark) { p = INF; mm = mark; dda[dsize] = a; ddb[dsize] = b; ddc[dsize] = c + 1; dsize++; } if (pos < n) p = min(p, next_pos[cs[c] - a ][pos] + 1); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int q; cin >> n >> q; cin >> s; memset(calced_mark, 0, sizeof(calced_mark)); memset(added_mark, 0, sizeof(added_mark)); for (int i = 0; i < ALPHABET_SIZE; i++) { next_pos[i].resize(n, INF); } for (int i = n - 1; i >= 0; i--) { if (i + 1 < n) { for (int z = 0; z < ALPHABET_SIZE; z++) { next_pos[z][i] = next_pos[z][i + 1]; } } int c = s[i] - a ; next_pos[c][i] = i; } int mark = 228; char c, which; int num; while (q--) { mark++; cin >> c >> num; if (c == - ) { if (num == 1) { as.pop_back(); } else if (num == 2) { bs.pop_back(); } else if (num == 3) { cs.pop_back(); } } else { cin >> which; if (num == 1) { as.push_back(which); promote(as.size() - 1, mark, num); } else if (num == 2) { bs.push_back(which); promote(bs.size() - 1, mark, num); } else if (num == 3) { cs.push_back(which); promote(cs.size() - 1, mark, num); } } cout << (calced_pos[as.size()][bs.size()][cs.size()] <= s.size() ? YES : NO ) << endl; } } |
#include <bits/stdc++.h> char T[1 << 21]; int n, m, ar[21][21]; int U[21], V[21], P[21], way[21], minv[21]; int hungarian(int n, int m, int ar[21][21]) { memset(way, 0, sizeof(way)), memset(U, 0, sizeof(U)), memset(V, 0, sizeof(V)), memset(P, 0, sizeof(P)); int i, j, i0, i1, j0, j1, x, y, cur, delta, used, lim = (1 << (m + 1)) - 1; for (i = 1; i <= n; i++) { used = 0; P[0] = i, j0 = 0; for (j = 0; j <= m; j++) minv[j] = (1 << 27); do { used |= (1 << j0); i0 = P[j0], j1 = 0, delta = (1 << 27), x = (used | 1) ^ lim; while (x) { y = (-x & x); j = T[y]; x ^= y; cur = ar[i0][j] - U[i0] - V[j]; if (cur < minv[j]) { minv[j] = cur; way[j] = j0; } if (minv[j] < delta) { delta = minv[j]; j1 = j; } } for (j = 0; j <= m; j++) { if (used & (1 << j)) { U[P[j]] += delta; V[j] -= delta; } else minv[j] -= delta; } j0 = j1; } while (P[j0] != 0); do { j1 = way[j0]; P[j0] = P[j1]; j0 = j1; } while (j0 != 0); } return -V[0]; } int fri[21][21], sat[21][21]; int main() { int i, j, k, x, res, lim, mask; for (i = 0; i < 21; i++) T[1 << i] = i; while (scanf( %d , &n) != EOF) { for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { scanf( %d , &fri[i][j]); } } for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { scanf( %d , &sat[i][j]); } } res = 0, lim = 1 << n; for (mask = 0; mask < lim; mask++) { if (__builtin_popcount(mask) == (n >> 1)) { for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (mask & (1 << i)) ar[i + 1][j + 1] = -fri[i][j]; else ar[i + 1][j + 1] = -sat[i][j]; } } x = -hungarian(n, n, ar); if (x > res) res = x; } } printf( %d n , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct event { int t, l, r, v; }; void solve() { int n, q; cin >> n >> q; vector<event> e(q); vector<int64_t> a(n, INT_MAX), upd(n, 0); for (int i = 0; i < q; ++i) { cin >> e[i].t; cin >> e[i].l; cin >> e[i].r; cin >> e[i].v; --e[i].l; --e[i].r; if (e[i].t == 1) { for (int j = e[i].l; j < e[i].r + 1; ++j) { upd[j] += e[i].v; } } } for (int i = q - 1; i >= 0; --i) { if (e[i].t == 2) { for (int j = e[i].l; j < e[i].r + 1; ++j) { a[j] = min(a[j], e[i].v - upd[j]); } } else { for (int j = e[i].l; j < e[i].r + 1; ++j) { upd[j] -= e[i].v; } } } vector<int64_t> tmp(a); for (int i = 0; i < q; ++i) { if (e[i].t == 1) { for (int j = e[i].l; j < e[i].r + 1; ++j) { tmp[j] += e[i].v; } } else { int64_t here = INT_MIN; for (int j = e[i].l; j < e[i].r + 1; ++j) { here = max(here, tmp[j]); } if (here != e[i].v) { cout << NO n ; return; } } } cout << YES n ; for (int64_t i : a) { if (i == INT_MAX) cout << rand() % 1000 << ; else cout << i << ; } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { int in, x = 0; int cnt = 0, p = 1, ans = 0; cin >> in; for (int i = in; i > 0; i /= 10) { if (i % 10 == 7) ans += p; p *= 2; cnt++; } if (cnt != 0) x = pow(2, cnt) - 2; cout << ans + x + 1; } |
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