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#include <bits/stdc++.h> using namespace std; template <typename S, typename T> ostream& operator<<(ostream& out, pair<S, T> const& p) { out << ( << p.first << , << p.second << ) ; return out; } template <typename T> ostream& operator<<(ostream& out, vector<T> const& v) { long long l = v.size(); for (long long i = 0; i < l - 1; i++) out << v[i] << ; if (l > 0) out << v[l - 1]; return out; } template <typename T> void trace(const char* name, T&& arg1) { cout << name << : << arg1 << n ; } template <typename T, typename... Args> void trace(const char* names, T&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; trace(comma + 1, args...); } const int N = 202; const int K = 1010; const int MOD = 1e9 + 7; int dp[N][N][K]; int n, kk, arr[N]; int pre[N]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> kk; for (int i = 1; i <= n; i++) { cin >> arr[i]; } sort(arr + 1, arr + 1 + n); dp[0][0][0] = 1; for (int i = 0; i < n; i++) { for (int j = 0; j <= n; j++) { for (int k = 0; k < K; k++) { int nk = k + (j) * (arr[i + 1] - arr[i]); if (nk <= kk) { dp[i + 1][j][nk] = (0LL + (1LL * dp[i][j][k] * (j + 1)) % MOD + dp[i + 1][j][nk]) % MOD; dp[i + 1][j + 1][nk] = (0LL + dp[i + 1][j + 1][nk] + dp[i][j][k]) % MOD; if (j) dp[i + 1][j - 1][nk] = (0LL + dp[i + 1][j - 1][nk] + 1LL * dp[i][j][k] * j) % MOD; } } } } int ans = 0; for (int i = 0; i <= kk; i++) { ans = (ans + dp[n][0][i]) % MOD; } cout << ans << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFSBP_PP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfsbp (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> const int N = 517; const int mod = 998244353; using namespace std; inline int read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + ch - 0 , ch = getchar(); return x; } int n, k; long long dp[N][N], ans; int main() { n = read(), k = read(); dp[0][0] = 1; for (int i = 1, I = (n) + 1; i < I; ++i) for (int j = 1, I = (i) + 1; j < I; ++j) for (int k = i - j, I = (i - 1) + 1; k < I; ++k) dp[i][j] = (dp[i][j] + dp[k][min(j, k)]) % mod; for (int i = n, I = (1) - 1; i > I; --i) dp[n][i] = (dp[n][i] - dp[n][i - 1] + mod) % mod; for (int i = 1, I = (n) + 1; i < I; ++i) for (int j = 1, I = (n) + 1; j < I; ++j) if (i * j < k) ans = (ans + dp[n][i] * dp[n][j]) % mod; printf( %lld n , (ans << 1) % mod); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDLCLKP_PP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, matrica[101][101], pas = 0; cin >> n; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { cin >> a; matrica[i][j] = a; } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { if (i == j || i == ((n + 1) / 2) - 1 && j != ((n + 1) / 2) - 1 || j == ((n + 1) / 2) - 1 && i != ((n + 1) / 2) - 1 || i == n - j - 1 && j != ((n + 1) / 2) - 1) pas += matrica[i][j]; } cout << pas << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int nn, mm; struct Dinic { struct edge { int to, flow, cap; }; const static int N = 20007; vector<edge> e; vector<int> g[N + 7]; int dp[N + 7]; int ptr[N + 7]; void clear() { for (int i = 0; i < N + 7; i++) g[i].clear(); e.clear(); } void addEdge(int a, int b, int cap) { g[a].push_back(e.size()); e.push_back({b, 0, cap}); g[b].push_back(e.size()); e.push_back({a, 0, 0}); } int minFlow, start, finish; bool bfs() { for (int i = 0; i < N; i++) dp[i] = -1; dp[start] = 0; vector<int> st; int uk = 0; st.push_back(start); while (uk < st.size()) { int v = st[uk++]; for (int to : g[v]) { auto ed = e[to]; if (ed.cap - ed.flow >= minFlow && dp[ed.to] == -1) { dp[ed.to] = dp[v] + 1; st.push_back(ed.to); } } } return dp[finish] != -1; } int dfs(int v, int flow) { if (v == finish) return flow; for (; ptr[v] < g[v].size(); ptr[v]++) { int to = g[v][ptr[v]]; edge ed = e[to]; if (ed.cap - ed.flow >= minFlow && dp[ed.to] == dp[v] + 1) { int add = dfs(ed.to, min(flow, ed.cap - ed.flow)); if (add) { e[to].flow += add; e[to ^ 1].flow -= add; return add; } } } return 0; } int dinic(int start, int finish) { Dinic::start = start; Dinic::finish = finish; int flow = 0; for (minFlow = (1 << 30); minFlow; minFlow >>= 1) { while (bfs()) { for (int i = 0; i < N; i++) ptr[i] = 0; while (int now = dfs(start, (int)2e9 + 7)) flow += now; } } return flow; } } dinic; pair<int, int> aa[5555]; bool can(int val) { dinic.clear(); for (int i = 0; i < nn; i++) { dinic.addEdge(nn + mm, i, val); } for (int i = 0; i < mm; i++) { dinic.addEdge(nn + i, nn + mm + 1, 1); } for (int i = 0; i < mm; i++) { dinic.addEdge(aa[i].first, nn + i, 1); dinic.addEdge(aa[i].second, nn + i, 1); } int ans = dinic.dinic(nn + mm, nn + mm + 1); return ans == mm; } int main() { cin >> nn >> mm; for (int i = 0; i < mm; i++) cin >> aa[i].first >> aa[i].second; for (int i = 0; i < mm; i++) aa[i].first--, aa[i].second--; int vl = 0, vr = mm; while (vl + 1 < vr) { int vm = (vl + vr) >> 1; if (can(vm)) vr = vm; else vl = vm; } cout << vr << n ; can(vr); for (int i = 0; i < nn; i++) { for (int to : dinic.g[i]) { if (dinic.e[to].flow == 1) { cout << i + 1 << << aa[dinic.e[to].to - nn].first + aa[dinic.e[to].to - nn].second - i + 1 << n ; } } } } |
/*
File: ewrapper_link_receiver.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_link_receiver (/*AUTOARG*/
// Outputs
rxo_wr_wait, rxo_rd_wait, emesh_clk_inb, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
// Inputs
reset, rxi_data, rxi_lclk, rxi_frame, emesh_wr_wait_outb,
emesh_rd_wait_outb
);
//#########
//# INPUTS
//#########
input reset; //reset input
//# From the lvds-serdes
input [63:0] rxi_data; //Eight Parallel Byte words
input rxi_lclk; //receive clock (synchronized to the data)
input [7:0] rxi_frame; //Parallel frame signals representing
// 4 transmission clock cycles
//# From the emesh interface
input emesh_wr_wait_outb;
input emesh_rd_wait_outb;
//##########
//# OUTPUTS
//##########
//# To the transmitter
output rxo_wr_wait; //wait indicator
output rxo_rd_wait; //wait indicator
//# To the emesh interface
output emesh_clk_inb;
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Wires
//#########
wire emesh_wr_access_inb;
wire emesh_wr_write_inb;
wire [1:0] emesh_wr_datamode_inb;
wire [3:0] emesh_wr_ctrlmode_inb;
wire [31:0] emesh_wr_dstaddr_inb;
wire [31:0] emesh_wr_srcaddr_inb;
wire [31:0] emesh_wr_data_inb;
wire emesh_rd_access_inb;
wire emesh_rd_write_inb;
wire [1:0] emesh_rd_datamode_inb;
wire [3:0] emesh_rd_ctrlmode_inb;
wire [31:0] emesh_rd_dstaddr_inb;
wire [31:0] emesh_rd_srcaddr_inb;
wire [31:0] emesh_rd_data_inb;
wire select_write_tran;
wire wr_wait;
wire rd_wait;
wire emesh_access_tmp;
//###############
//# Emesh clock
//###############
assign emesh_clk_inb = rxi_lclk;
//######################################
//# Write-Read Transactions Arbitration
//# Write has a higher priority ALWAYS
//######################################
assign select_write_tran = emesh_wr_access_inb & ~emesh_wr_wait_outb;
assign emesh_access_inb = emesh_access_tmp & ~emesh_wr_wait_outb;
assign wr_wait = emesh_wr_wait_outb;
assign rd_wait = emesh_rd_access_inb & select_write_tran |
(emesh_wr_wait_outb | emesh_rd_wait_outb);
assign emesh_srcaddr_inb[31:0] =
select_write_tran ? emesh_wr_srcaddr_inb[31:0] :
emesh_rd_srcaddr_inb[31:0];
assign emesh_dstaddr_inb[31:0] =
select_write_tran ? emesh_wr_dstaddr_inb[31:0] :
emesh_rd_dstaddr_inb[31:0];
assign emesh_datamode_inb[1:0] =
select_write_tran ? emesh_wr_datamode_inb[1:0] :
emesh_rd_datamode_inb[1:0];
assign emesh_ctrlmode_inb[3:0] =
select_write_tran ? emesh_wr_ctrlmode_inb[3:0] :
emesh_rd_ctrlmode_inb[3:0];
assign emesh_data_inb[31:0] = select_write_tran ? emesh_wr_data_inb[31:0] :
emesh_rd_data_inb[31:0];
assign emesh_access_tmp = select_write_tran ? emesh_wr_access_inb :
emesh_rd_access_inb;
assign emesh_write_inb = select_write_tran ? emesh_wr_write_inb :
emesh_rd_write_inb;
//############################################
//# Write Transactions Receiver Instantiation
//############################################
/*ewrapper_link_rxi AUTO_TEMPLATE(
.rxi_rd (1'b0),
.emesh_wait_outb (wr_wait),
.rxo_wait (rxo_wr_wait),
.emesh_\(.*\) (emesh_wr_\1[]),
);
*/
ewrapper_link_rxi wr_rxi(/*AUTOINST*/
// Outputs
.rxo_wait (rxo_wr_wait), // Templated
.emesh_access_inb (emesh_wr_access_inb), // Templated
.emesh_write_inb (emesh_wr_write_inb), // Templated
.emesh_datamode_inb (emesh_wr_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emesh_wr_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
// Inputs
.reset (reset),
.rxi_data (rxi_data[63:0]),
.rxi_lclk (rxi_lclk),
.rxi_frame (rxi_frame[7:0]),
.emesh_wait_outb (wr_wait), // Templated
.rxi_rd (1'b0)); // Templated
//############################################
//# Read Transactions Receiver Instantiation
//############################################
/*ewrapper_link_rxi AUTO_TEMPLATE(
.rxi_rd (1'b1),
.emesh_wait_outb (rd_wait),
.rxo_wait (rxo_rd_wait),
.emesh_\(.*\) (emesh_rd_\1[]),
);
*/
ewrapper_link_rxi rd_rxi(/*AUTOINST*/
// Outputs
.rxo_wait (rxo_rd_wait), // Templated
.emesh_access_inb (emesh_rd_access_inb), // Templated
.emesh_write_inb (emesh_rd_write_inb), // Templated
.emesh_datamode_inb (emesh_rd_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emesh_rd_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
// Inputs
.reset (reset),
.rxi_data (rxi_data[63:0]),
.rxi_lclk (rxi_lclk),
.rxi_frame (rxi_frame[7:0]),
.emesh_wait_outb (rd_wait), // Templated
.rxi_rd (1'b1)); // Templated
endmodule // ewrapper_link_receiver
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using pii = array<ll, 3>; vector<vector<pii>> adj; vi sz, parent; int fill(int cur, int par = -1) { parent[cur] = par; for (auto [v, _, __] : adj[cur]) if (v != par) sz[cur] += fill(v, cur); sz[cur] = max(1, sz[cur]); return sz[cur]; } int main(int argc, char* argv[]) { std::ios::sync_with_stdio(false); cin.tie(nullptr); cout.precision(10); int t; cin >> t; while (t--) { ll n, s; cin >> n >> s; adj.assign(n, {}); sz.assign(n, 0); parent.assign(n, -1); for (int i = (0); i < (n - 1); ++i) { ll u, v, w, c; cin >> u >> v >> w >> c; u--, v--; adj[u].push_back({v, w, c}); adj[v].push_back({u, w, c}); } fill(0); priority_queue<array<ll, 3>> prePQ[2]; ll start_sum = 0; for (int u = (0); u < (n); ++u) for (auto [v, w, c] : adj[u]) { if (parent[v] == u) { start_sum += w * sz[v]; if (c == 1) { prePQ[0].push({sz[v] * (w - w / 2), w, sz[v]}); prePQ[0].push({sz[v] * (w / 2 - w / 4), w / 2, sz[v]}); } else { prePQ[1].push({sz[v] * (w - w / 2), w, sz[v]}); } } } ll mi = 1e18; for (int p = (0); p < (2); ++p) { ll steps = 0, cur_sum = start_sum; priority_queue<array<ll, 3>> pqOne = prePQ[0], pqTwo = prePQ[1]; if (p && pqOne.size()) { steps++; auto [g, w, s] = pqOne.top(); w /= 4; cur_sum -= g; pqOne.pop(); pqOne.push({s * (w - w / 2), w, s}); } while (cur_sum > s) { if (pqOne.empty()) { steps += 2; auto [g, w, s] = pqTwo.top(); w /= 2; cur_sum -= g; pqTwo.pop(); pqTwo.push({s * (w - w / 2), w, s}); } else if (pqTwo.empty()) { steps += 1; auto [g, w, s] = pqOne.top(); w /= 4; cur_sum -= g; pqOne.pop(); pqOne.push({s * (w - w / 2), w, s}); } else { steps += 2; auto [g11, w11, s11] = pqOne.top(); pqOne.pop(); auto [g12, w12, s12] = pqOne.top(); pqOne.pop(); auto [g2, w2, s2] = pqTwo.top(); pqTwo.pop(); if (g11 + g12 > g2) { pqTwo.push({g2, w2, s2}); cur_sum -= g11 + g12; w11 /= 4; w12 /= 4; pqOne.push({s11 * (w11 - w11 / 2), w11, s11}); pqOne.push({s12 * (w12 - w12 / 2), w12, s12}); } else { pqOne.push({g11, w11, s11}); pqOne.push({g12, w12, s12}); cur_sum -= g2; w2 /= 2; pqTwo.push({s2 * (w2 - w2 / 2), w2, s2}); } } } mi = min(mi, steps); } cout << mi << n ; } cout.flush(); return 0; } |
#include <bits/stdc++.h> using namespace std; struct ele { long long next, prev, delta, y; }; long long r, c, k, n, curcnt = 0, ans = 0; vector<ele> a; vector<long long> deltaleft, deltaright; vector<vector<long long> > X, id; vector<pair<long long, long long> > tmp; void init() { X.clear(); X.resize(r + 1); id.resize(r + 1); } void remove(long long id) { long long cur = id; deltaleft.clear(); deltaright.clear(); for (long long i = 0; i <= k; i++) { if (cur == -1 || a[cur].delta == -1) break; deltaleft.push_back(a[cur].delta); cur = a[cur].prev; } cur = a[id].next; for (long long i = 0; i <= k; i++) { if (cur == -1 || a[cur].delta == -1) break; deltaright.push_back(a[cur].delta); cur = a[cur].next; } curcnt -= deltaright[0] * deltaleft[0]; curcnt -= deltaright[0] * (deltaright[0] - 1) / 2 + deltaleft[0] * (deltaleft[0] - 1) / 2; curcnt += (deltaright[0] + deltaleft[0]) * (deltaright[0] + deltaleft[0] - 1) / 2; for (long long i = 0; i <= k; i++) { if (i < deltaleft.size() && k - i < deltaright.size()) curcnt += deltaleft[i] * deltaright[k - i]; } a[a[id].prev].next = a[id].next; a[a[id].next].prev = a[id].prev; a[a[id].next].delta += a[id].delta; } long long cmp(pair<long long, long long> a, pair<long long, long long> b) { return X[a.first][a.second] < X[b.first][b.second]; } void solve(long long r1) { tmp.clear(); for (long long i = r1; i <= r; i++) { for (long long j = 0; j < X[i].size(); j++) { tmp.push_back({i, j}); } } sort(tmp.begin(), tmp.end(), cmp); a.resize(tmp.size() + 2); a[0].prev = -1; a[0].next = 1; a[0].y = 0; a[tmp.size() + 1].prev = (long long)tmp.size(); a[tmp.size() + 1].next = -1; a[tmp.size() + 1].y = c + 1; for (long long i = 0; i < tmp.size(); i++) { id[tmp[i].first][tmp[i].second] = i + 1; a[i + 1].y = X[tmp[i].first][tmp[i].second]; a[i + 1].prev = i; a[i + 1].next = i + 2; } a[0].delta = -1; for (long long i = 1; i < a.size(); i++) { a[i].delta = a[i].y - a[i - 1].y; } curcnt = 0; for (long long i = 1; i < a.size(); i++) { curcnt += (a[i].delta - 1) * a[i].delta / 2; for (long long j = 1; j <= k; j++) { if (i - j <= 0) break; curcnt += a[i].delta * a[i - j].delta; } } for (long long i = r; i >= r1; i--) { ans += curcnt; for (long long j = 0; j < X[i].size(); j++) { remove(id[i][j]); } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> r >> c >> n >> k; k--; init(); for (long long i = 1; i <= n; i++) { long long u, v; cin >> u >> v; X[u].push_back(v); } for (long long i = 1; i <= r; i++) { id[i].resize(X[i].size()); } for (long long i = 1; i <= r; i++) { solve(i); } ans = (r + 1) * r / 2 * (c + 1) * c / 2 - ans; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma Optimize( O3 ) using namespace std; int n, x, a, b, y, m, ans; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; vector<int> v(n); vector<int> a; for (int i = 0; i < n; i++) cin >> v[i]; for (int i = 0; i < n; i += 2) a.push_back(v[i]); for (int i = 1; i < n; i += 2) a.push_back(v[i]); a.insert(a.end(), a.begin(), a.end()); long long sumtmp = 0; for (int i = 0; i < (n + 1) / 2; i++) sumtmp += a[i]; long long sum = sumtmp; for (int i = (n + 1) / 2; i < a.size(); i++) { sumtmp += a[i] - a[i - (n + 1) / 2]; sum = max(sum, sumtmp); } cout << sum << n ; return 0; } |
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_iface_address_to_bankaddress #(
parameter integer ADDRESS_W = 32, // > 0
parameter integer NUM_BANKS = 2, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS)
)
(
input logic [ADDRESS_W-1:0] address,
output logic [NUM_BANKS-1:0] bank_sel_1hot, // one-hot
output logic [$clog2(NUM_BANKS)-1:0] bank_sel_fe, // full encoded
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] bank_address
);
integer i;
// To support NUM_BANKS=1 we need a wider address
logic [ADDRESS_W:0] wider_address;
assign wider_address = {1'b0,address};
always@*
begin
for (i=0; i<NUM_BANKS; i=i+1)
bank_sel_1hot[i] = (wider_address[BANK_SEL_BIT+$clog2(NUM_BANKS)-1 : BANK_SEL_BIT] == i);
end
always@*
begin
bank_sel_fe = (wider_address>>BANK_SEL_BIT) & ~(64'b1<<$clog2(NUM_BANKS));
end
assign bank_address = ((address>>(BANK_SEL_BIT+$clog2(NUM_BANKS)))<<(BANK_SEL_BIT)) |
address[BANK_SEL_BIT-1:0];
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module RAMB16_S1_S2 (
CLKA, CLKB, ENB, WEA, WEB, ENA, SSRA, SSRB, DIPB, ADDRA, ADDRB, DIA, DIB, DOA, DOB, DOPB
);
input wire CLKA;
input wire CLKB;
output reg [1 : 0] DOB;
output reg [0 : 0] DOA;
input wire [0 : 0] WEA;
input wire [0 : 0] WEB;
input wire [12 : 0] ADDRB;
input wire [13 : 0] ADDRA;
input wire [1 : 0] DIB;
input wire [0 : 0] DIA;
input wire ENB;
input wire ENA;
input wire SSRA;
input wire SSRB;
input wire DIPB;
output wire DOPB;
parameter WIDTHA = 1;
parameter SIZEA = 16384;
parameter ADDRWIDTHA = 14;
parameter WIDTHB = 2;
parameter SIZEB = SIZEA/2;
parameter ADDRWIDTHB = 13;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
`include "../includes/log2func.v"
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = `CLOG2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
always @(posedge CLKA)
if (WEA)
RAM[ADDRA] <= DIA;
else
DOA <= RAM[ADDRA];
genvar i;
generate for (i = 0; i < RATIO; i = i+1)
begin: portA
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge CLKB)
if (WEB)
RAM[{ADDRB, lsbaddr}] <= DIB[(i+1)*minWIDTH-1:i*minWIDTH];
else
DOB[(i+1)*minWIDTH-1:i*minWIDTH] <= RAM[{ADDRB, lsbaddr}];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int INF = 1000000005; long long INFF = 1000000000000000005LL; int main() { long long s, n; cin >> s >> n; long long x, y; vector<pair<long long, long long>> strengths; for (long long i = 0; i < n; i++) { cin >> x >> y; strengths.push_back(make_pair(x, y)); } sort(strengths.begin(), strengths.end()); bool win = true; for (long long i = 0; i < n; i++) { if (s <= strengths[i].first) { win = false; break; } s += strengths[i].second; } if (win) { cout << YES << n ; ; } else { cout << NO << n ; ; } return 0; } |
// file: Clk_Wizard.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// VGA_clock___108.025______0.000______50.0______144.053____157.495
// Main_clock____99.432______0.000______50.0______146.499____157.495
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clk_Wizard,clk_wiz_v5_3_3_0,{component_name=Clk_Wizard,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module Clk_Wizard
(
// Clock out ports
output VGA_clock,
output Main_clock,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input Clock_Board
);
Clk_Wizard_clk_wiz inst
(
// Clock out ports
.VGA_clock(VGA_clock),
.Main_clock(Main_clock),
// Status and control signals
.resetn(resetn),
.locked(locked),
// Clock in ports
.Clock_Board(Clock_Board)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_iobuf (
dio_t,
dio_i,
dio_o,
dio_p);
parameter DATA_WIDTH = 1;
input [(DATA_WIDTH-1):0] dio_t;
input [(DATA_WIDTH-1):0] dio_i;
output [(DATA_WIDTH-1):0] dio_o;
inout [(DATA_WIDTH-1):0] dio_p;
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
assign dio_o[n] = dio_p[n];
assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
//////////////////////////////////////////////////////////////////////
//// ////
//// sm_fifoRTL.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// parameterized dual clock domain fifo.
//// fifo depth is restricted to 2^ADDR_WIDTH
//// No protection against over runs and under runs.
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module sm_fifoDMA(fifoClk, reset, dataIn,
dataOut, fifoWEn, fifoREn,
forceEmptyWr, forceEmptyRd,
do_peri, di_peri, addr_peri, mem_clk, mem_access, store_access, addr_high);
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
parameter DMA_ADR = 18'h19c00; //1024 addresses below IO ports
parameter FIFO_WIDTH = 8;
// Two clock domains within this module, DMA and fifo clocks
input fifoClk;
input reset;
input [FIFO_WIDTH-1:0] dataIn;
input fifoWEn;
input forceEmptyWr;
output [FIFO_WIDTH-1:0] dataOut;
input fifoREn;
input forceEmptyRd;
//*** Connections to SpartanMC Core (do not change) ***
input [17:0] do_peri; //Data Bus from MC
output [17:0] di_peri; //Data Bus to MC
input [9:0] addr_peri; //Address Bus from MC
// BlockRAM interface
input mem_clk; //BRAM clk
input mem_access;
input store_access;
input [7:0] addr_high;
wire fifoClk;
wire reset;
wire [FIFO_WIDTH-1:0] dataIn;
reg [FIFO_WIDTH-1:0] dataOut;
wire fifoWEn;
wire fifoREn;
wire forceEmpty;
reg [15:0]numElementsInFifo;
// local registers
reg [ADDR_WIDTH:0]bufferInIndex;
reg [ADDR_WIDTH:0]bufferOutIndex;
reg [ADDR_WIDTH-1:0]bufferIndexToMem;
reg fifoREnDelayed;
wire [FIFO_WIDTH-1:0] dataFromMem;
always @(posedge fifoClk)
begin
if (reset == 1'b1 || forceEmptyWr == 1'b1)
begin
bufferInIndex <= 0;
end
else
begin
if (fifoWEn == 1'b1) begin
bufferInIndex <= bufferInIndex + 1'b1;
end
end
end
always @(posedge fifoClk)
begin
if (reset == 1'b1 || forceEmptyRd == 1'b1)
begin
bufferOutIndex <= 0;
fifoREnDelayed <= 1'b0;
end
else
begin
fifoREnDelayed <= fifoREn;
if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
dataOut <= dataFromMem;
bufferOutIndex <= bufferOutIndex + 1'b1;
end
end
end
always @(bufferInIndex or bufferOutIndex or fifoWEn) begin
if (fifoWEn) begin
bufferIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
end else begin
bufferIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
end
end
wire activ_dma0;
pselect #(
.ADDR_WIDTH (8 ),
.BASE_WIDTH (8 ),
.BASE_ADDR (DMA_ADR >> 10 ) // using upper 8 bit of address
)
dmasel0 (
.addr (addr_high[7:0] ),
.activ_peri (mem_access ),
.select (activ_dma0 )
);
RAMB16_S9_S9 fifo_mem (
// Port A, access from SD card module
.DIA (dataIn[7:0] ),
.DIPA (1'd0 ),
.ADDRA ({2'b0, bufferIndexToMem} ),
.ENA (1'b1 ),
.WEA (fifoWEn ),
.SSRA (1'b0 ),
.CLKA (fifoClk ),
.DOA (dataFromMem[7:0] ),
// .DOPA (dataFromMem[8] ),
// Port B, access from SpartanMC
.DIB (do_peri[7:0] ),
.DIPB (do_peri[8] ),
.ADDRB ({1'b0, addr_peri[9:0]} ),
.ENB (1'b1 ),
.WEB (store_access & activ_dma0 ),
.SSRB (! activ_dma0 ),
.CLKB (mem_clk ),
.DOB (di_peri[7:0] ),
.DOPB (di_peri[8] )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int h = 17, N = 1 << h; long long t[2 * N]; long long k; long long product(int a, int b) { if (a > b) return 1; if (a % 2 == 1) return (t[a] * product(a + 1, b)) % k; if (b % 2 == 0) return (t[b] * product(a, b - 1)) % k; return product(a / 2, b / 2); } int main() { int n; scanf( %d%lld , &n, &k); for (int i = 1; i < 2 * N; ++i) t[i] = 1; for (int i = 0; i < n; ++i) { scanf( %lld , &t[N + i]); t[N + i] = t[N + i] % k; } for (int i = N - 1; i >= 1; --i) t[i] = (t[2 * i] * t[2 * i + 1]) % k; long long m = 0; for (int i = 0; i < n; ++i) { int lo = i, hi = n - 1; while (lo < hi) { int mid = lo + (hi - lo) / 2; if (product(N + i, N + mid) == 0) hi = mid; else lo = mid + 1; } if (lo >= n || product(N + i, N + lo) != 0) break; m += static_cast<long long>(n) - lo; } printf( %lld n , m); return 0; } |
#include <algorithm> #include <iostream> #include <climits> #include <iomanip> #include <cstring> #include <string> #include <vector> #include <queue> #include <cmath> #include <set> #include <map> using namespace std; template <typename T> istream &operator>> (istream &is, vector<T> &vec) { for (auto &v : vec) is >> v; return is; } #define all(x) (x).begin(),(x).end() #define rall(x) (x).rbegin(),(x).rend() #define ll long long #define mod 1000000007 #define nod 1000000007 #define vi vector<int> #define vll vector<ll> #define pb push_back // D R U L int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; const int mx = 1e6 + 5; const int INF = mod; ll power(ll x, ll y){ ll res = 1; while(y > 0){ if(y & 1) res = (res * x) % nod; y >>= 1; x = (x * x) % nod; } return (res % nod); } // Check for number of Cases!! void solve() { ll n; cin >> n; string str; cin >> str; str += $ ; vector<int> freq(26, -1); for(int i = 1; i < str.length(); i++) { if(str[i] != str[i - 1]) { if(freq[str[i - 1] - A ] == -1) { freq[str[i - 1] - A ] = i; }else { cout << NO n ; return; } } } cout << YES n ; } int main(){ #ifndef ONLINE_JUDGE freopen( /ATOMCODES/input.txt , r , stdin); freopen( /ATOMCODES/output.txt , w , stdout); freopen( /ATOMCODES/err_output.txt , w , stderr); #endif ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; cin >> t; while(t--) { solve(); } } |
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// Connects a buffer_BB to a stage and an mstore and takes care of
// transfering data.
module buffer_BB_to_stage
#(
parameter N = 8,
parameter LOG_N = 3,
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
// Start signals
input wire start,
// From buffer_BB
input wire read_full,
input wire [WIDTH+MWIDTH-1: 0] read_data,
output reg read_delete,
// To Stage
output wire [LOG_N-1:0] out_addr0,
output wire [LOG_N-1:0] out_addr1,
output reg out_nd,
output reg [WIDTH-1:0] out_data0,
output reg [WIDTH-1:0] out_data1,
// To mStore
output reg out_mnd,
output reg [MWIDTH-1:0] out_m,
// Whether it is active
output wire active,
output reg error
);
reg [LOG_N-1:0] addr;
assign out_addr0 = addr;
assign out_addr1 = addr + 1;
reg read_counter;
wire [WIDTH-1:0] read_data_s;
wire [MWIDTH-1:0] read_data_m;
assign {read_data_s, read_data_m} = read_data;
reg first_read;
reg active_o;
assign active = active_o | start;
always @ (posedge clk)
begin
// Set the default values;
out_nd <= 1'b0;
read_delete <= 1'b0;
out_mnd <= 1'b0;
if (~rst_n)
begin
active_o <= 1'b0;
addr <= {LOG_N{1'b0}};
read_counter <= 1'b0;
error <= 1'b0;
end
else if (start)
begin
if (active_o)
error <= 1'b1;
else
begin
active_o <= 1'b1;
addr <= {LOG_N{1'b0}};
read_counter <= 1'b0;
first_read <= 1'b1;
end
end
else if (active_o & read_full)
begin
out_mnd <= 1'b1;
out_m <= read_data_m;
// We can only read one item from the buffer each block
// cycle. But we write to the stage two at a time
// so we have to save values and only write every second
// clock cycle.
read_counter <= ~read_counter;
read_delete <= 1'b1;
if (~read_counter)
begin
out_data0 <= read_data_s;
if (~first_read)
addr <= addr + 2;
first_read <= 1'b0;
end
else
begin
out_data1 <= read_data_s;
out_nd <= 1'b1;
if (addr == N-2)
begin
active_o <= 1'b0;
end
end
end
end
endmodule |
module autotieoff_signed (/*AUTOARG*/);
/*AUTO_LISP(setq my-nc-output "\/*NC*\/" my-nc-input-scalar "1'b0" my-nc-input-vector "'0" my-nc-input-mdv "'{default:'0}" my-space "|")*/
/* sub AUTO_TEMPLATE (
.\(.*\) (@"(concat (if (equal vl-dir \\"output\\") my-nc-output (if (not vl-memory) my-nc-input-vector my-nc-input-mdv) ) my-space vl-width my-space vl-bits my-space vl-mbits my-space vl-memory )"),
) */
// Value | vl-width | vl-bits | vl-mbits | vl-memory
sub sub (/*AUTOINST*/
// Outputs
.outvar (/*NC*/|1|||), // Templated
// Inputs
.scalar_var ('0|1|||), // Templated
.packed1_var ('0|2|[1:0]||), // Templated
.packed2_var ('0|3|[2:0]|[1:0]|), // Templated
.packed1_unpacked1_var ('{default:'0}|2|[1:0]||[2]), // Templated
.packed1_unpacked2_var ('{default:'0}|2|[1:0]||[2][3]), // Templated
.packed2_unpacked1_var ('{default:'0}|3|[2:0]|[1:0]|[2]), // Templated
.packed2_unpacked2_var ('{default:'0}|3|[2:0]|[1:0]|[2][3]), // Templated
.unpacked1_var ('{default:'0}|1|||[2]), // Templated
.unpacked2_var ('{default:'0}|1|||[2][3])); // Templated
endmodule
module sub
(
output outvar,
input wire scalar_var,
input wire [1:0] packed1_var,
input wire [1:0][2:0] packed2_var,
input wire [1:0] packed1_unpacked1_var [2],
input wire [1:0] packed1_unpacked2_var [2][3],
input wire [1:0][2:0] packed2_unpacked1_var [2],
input wire [1:0][2:0] packed2_unpacked2_var [2][3],
input wire unpacked1_var [2]
input wire unpacked2_var [2][3]
);
endmodule
// Local Variables:
// verilog-active-low-regexp: "_l$"
// verilog-auto-tieoff-ignore-regexp: "ignored"
// End:
|
#include <bits/stdc++.h> using namespace std; long long totalSum; long long check(long long a, long long b, long long c, long long r) { if (b + c > a) { return 0; } long long d = min(r, a - b - c); return (d + 2) * (d + 1) / 2; } int main() { long long a, b, c, l, total; cin >> a >> b >> c >> l; totalSum = a + b + c + l; total = (l + 3) * (l + 2) * (l + 1) / 6; for (long long i = 0; i <= l; i++) { total -= check(a + i, b, c, l - i); total -= check(b + i, a, c, l - i); total -= check(c + i, b, a, l - i); } cout << total << n ; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_errman_ftl.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
Description:
This module figures out what to do for fatal errors:
1) count up or count down,
2) how much to add or to subtract.
It returns the number and a add/subtract_b signals to the error
tracking counter. The outputs are based on how many errors are
asserted by the error reporting modules.
***********************************************************************/
module cmm_errman_ftl (
ftl_num, // Output
inc_dec_b,
cmmp_training_err, // Inputs
cmml_protocol_err_n,
cmmt_err_rbuf_overflow,
cmmt_err_fc,
cmmt_err_tlp_malformed,
decr_ftl,
rst,
clk
);
output [2:0] ftl_num;
output inc_dec_b; // 1 = increment, 0 = decrement
input cmmp_training_err;
input cmml_protocol_err_n;
input cmmt_err_rbuf_overflow;
input cmmt_err_fc;
input cmmt_err_tlp_malformed;
input decr_ftl;
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter FFD = 1; // clock to out delay model
//******************************************************************//
// Figure out how many errors to increment. //
//******************************************************************//
reg [2:0] to_incr;
reg add_sub_b;
always @(cmmt_err_tlp_malformed or
cmmp_training_err or
cmml_protocol_err_n or
cmmt_err_rbuf_overflow or cmmt_err_fc or
decr_ftl) begin
case ({cmmt_err_tlp_malformed, cmml_protocol_err_n, cmmt_err_rbuf_overflow, cmmp_training_err, cmmt_err_fc,
decr_ftl}) // synthesis full_case parallel_case
6'b000000: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b000001: begin to_incr = 3'b000; add_sub_b = 1'b1; end
6'b000010: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b000011: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b000100: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b000101: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b000110: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b000111: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b001000: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b001001: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b001010: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b001011: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b001100: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b001101: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b001110: begin to_incr = 3'b100; add_sub_b = 1'b1; end
6'b001111: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b010000: begin to_incr = 3'b000; add_sub_b = 1'b1; end
6'b010001: begin to_incr = 3'b001; add_sub_b = 1'b0; end
6'b010010: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b010011: begin to_incr = 3'b000; add_sub_b = 1'b1; end
6'b010100: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b010101: begin to_incr = 3'b000; add_sub_b = 1'b1; end
6'b010110: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b010111: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b011000: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b011001: begin to_incr = 3'b000; add_sub_b = 1'b1; end
6'b011010: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b011011: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b011100: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b011101: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b011110: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b011111: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b100000: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b100001: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b100010: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b100011: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b100100: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b100101: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b100110: begin to_incr = 3'b100; add_sub_b = 1'b1; end
6'b100111: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b101000: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b101001: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b101010: begin to_incr = 3'b100; add_sub_b = 1'b1; end
6'b101011: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b101100: begin to_incr = 3'b100; add_sub_b = 1'b1; end
6'b101101: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b101110: begin to_incr = 3'b101; add_sub_b = 1'b1; end
6'b101111: begin to_incr = 3'b100; add_sub_b = 1'b1; end
6'b110000: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b110001: begin to_incr = 3'b000; add_sub_b = 1'b1; end
6'b110010: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b110011: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b110100: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b110101: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b110110: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b110111: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b111000: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b111001: begin to_incr = 3'b001; add_sub_b = 1'b1; end
6'b111010: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b111011: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b111100: begin to_incr = 3'b011; add_sub_b = 1'b1; end
6'b111101: begin to_incr = 3'b010; add_sub_b = 1'b1; end
6'b111110: begin to_incr = 3'b100; add_sub_b = 1'b1; end
6'b111111: begin to_incr = 3'b011; add_sub_b = 1'b1; end
default: begin to_incr = 3'b000; add_sub_b = 1'b1; end
endcase
end
//******************************************************************//
// Register the outputs. //
//******************************************************************//
reg [2:0] reg_ftl_num;
reg reg_inc_dec_b;
always @(posedge clk or posedge rst) begin
if (rst) begin
reg_ftl_num <= #FFD 3'b000;
reg_inc_dec_b <= #FFD 1'b0;
end
else begin
reg_ftl_num <= #FFD to_incr;
reg_inc_dec_b <= #FFD add_sub_b;
end
end
assign ftl_num = reg_ftl_num;
assign inc_dec_b = reg_inc_dec_b;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_PP_SYMBOL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd3 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_PP_SYMBOL_V
|
#include <iostream> #include <algorithm> #include<cmath> #include<cstring> #include<cstdio> #include<cstdlib> #include<vector> #include<iomanip> #include<ctime> #include<set> #include<map> #include<queue> #include<stack> #include<bitset> #define sqr(x) ((x)*(x)) #define fz1(i,n) for ((i)=1;(i)<=(n);(i)++) #define fd1(i,n) for ((i)=(n);(i)>=1;(i)--) #define fz0g(i,n) for ((i)=0;(i)<=(n);(i)++) #define fd0g(i,n) for ((i)=(n);(i)>=0;(i)--) #define fz0k(i,n) for ((i)=0;(i)<(n);(i)++) #define fd0k(i,n) for ((i)=(long long)((n)-1);(i)>=0;(i)--) #define fz(i,x,y) for ((i)=(x);(i)<=(y);(i)++) #define fd(i,y,x) for ((i)=(y);(i)>=(x);(i)--) #define fzin fz1(i,n) #define fzim fz1(i,m) #define fzjn fz1(j,n) #define fzjm fz1(j,m) #define ff(c,itr) for (__typeof((c).begin()) itr=(c).begin();itr!=(c).end();++itr) #define rdst(st,len){static char ss[len];scanf( %s ,ss);(st)=ss;} #define incm(x,y) {x=((x)+(y))%mod;} #define spln(i,n) (i==n? n : ) #define fac_init(n){fac[0]=fac[1]=inv[1]=fi[0]=fi[1]=1;fz(i,2,n){fac[i]=1ll*fac[i-1]*i%mod;inv[i]=1ll*(mod-mod/i)*inv[mod%i]%mod;fi[i]=1ll*fi[i-1]*inv[i]%mod;}} #define fi first #define se second #define mk make_pair using namespace std; inline void read(int &x) { char c;int f=1; while(!isdigit(c=getchar()))if(c== - )f=-1; x=(c&15);while(isdigit(c=getchar()))x=(x<<1)+(x<<3)+(c&15); x*=f; } int n,m,q,i,j,cur; vector<unsigned long long> all; unsigned long long a[200005],op[200005],b[200005]; struct bit { int b[400005]; unsigned long long a[400005]; void add(int x,int y) { unsigned long long t=y*all[x-1]; while(x<=m){ a[x]+=t; b[x]+=y; x+=(x&-x); } } unsigned long long query1(int x) { unsigned long long s=0; while(x){ s+=a[x]; x-=(x&-x); } return s; } int query0(int x) { int s=0; while(x){ s+=b[x]; x-=(x&-x); } return s; } int kth(int x) { int s=0,i; for(i=18;i>=0;i--){ if(s+(1<<i)>m) continue; if(b[s+(1<<i)]<x){ x-=b[s+(1<<i)]; s+=(1<<i); } } return s+1; } }tr1; struct nd { unsigned long long s1,s2; int sz; }; struct seg { nd s[1600005]; nd merge(nd x,nd y) { nd z; z.sz=x.sz+y.sz; z.s1=x.s1+y.s1; z.s2=x.s2+y.s2+y.s1*(unsigned long long)x.sz; return z; } void pushup(int x) { s[x]=merge(s[x+x],s[x+x+1]); } void update(int x,int l,int r,int y,int c) { if(l==r){ s[x].s1+=((unsigned long long)c)*all[l-1]; s[x].s2+=((unsigned long long)c)*all[l-1]; s[x].sz+=c; return; } int mid=(l+r)/2; if(y<=mid)update(x+x,l,mid,y,c); else update(x+x+1,mid+1,r,y,c); pushup(x); } nd query(int x,int l,int r,int ql,int qr) { if(ql<=l&&r<=qr) return s[x]; int mid=(l+r)/2; if(qr<=mid) return query(x+x,l,mid,ql,qr); if(ql>mid) return query(x+x+1,mid+1,r,ql,qr); return merge(query(x+x,l,mid,ql,qr),query(x+x+1,mid+1,r,ql,qr)); } }tr2; void ins(int x) { cur++; tr1.add(x,1); tr2.update(1,1,m,x,1); } void del(int x) { cur--; tr1.add(x,-1); tr2.update(1,1,m,x,-1); } unsigned long long gsum1(int r) { if(r==0) return 0; if(r==cur) return tr1.query1(m); int t=tr1.kth(r); unsigned long long s1=tr1.query1(t),s0=tr1.query0(t); return s1-(s0-r)*all[t-1]; } unsigned long long gsum1(int l,int r) { return gsum1(r)-gsum1(l-1); } unsigned long long c2(unsigned long long x) { unsigned long long y=x+1; if(x%2==0)x/=2;else y/=2; return x*y; } unsigned long long gsuml(int len) { if(len==0) return 0; int t=tr1.kth(len); nd s=tr2.query(1,1,m,1,t); return s.s2-(c2(s.sz)-c2(len))*all[t-1]-(s.s1-(s.sz-len)*all[t-1])*(len+1); } unsigned long long gsumr(int len) { if(len==0) return 0; int t=tr1.kth(cur-len); nd s=tr2.query(1,1,m,t,m); unsigned long long res=s.s2-(c2(s.sz-len))*all[t-1]-(s.s1-(s.sz-len)*all[t-1])*(s.sz-len); return res; } void query() { if(cur<=1){ puts( 0 ); return; } unsigned long long ans=tr2.s[1].s2*2; int s=0,l=0,r=cur/2+1,mid; while(l<r){ mid=(l+r)/2; unsigned long long sl=gsum1(1,mid+1); unsigned long long sr=gsum1(cur-mid+1,cur); if(sl>=sr){ s=mid; l=mid+1; } else r=mid; } ans+=gsuml(s+1); ans+=gsumr(s); s=cur,l=cur/2,r=cur-1,mid; while(l<r){ mid=(l+r+1)/2; unsigned long long sl=gsum1(1,mid+1); unsigned long long sr=gsum1(cur-mid+1,cur); if(sl>=sr){ s=mid; r=mid-1; } else l=mid; } ans-=gsuml(s); ans-=gsumr(s-1); ans-=tr2.s[1].s1*(cur+1); printf( %I64u n ,ans); } int main() { scanf( %d%d ,&n,&q); fz1(i,n){ scanf( %I64u ,&a[i]); all.push_back(a[i]); } fz1(i,q){ scanf( %d%I64u ,&op[i],&b[i]); all.push_back(b[i]); } sort(all.begin(),all.end()); all.resize(unique(all.begin(),all.end())-all.begin()); m=all.size(); fz1(i,n){ ins(upper_bound(all.begin(),all.end(),a[i])-all.begin()); } query(); fz1(i,q){ if(op[i]==1) ins(upper_bound(all.begin(),all.end(),b[i])-all.begin()); else del(upper_bound(all.begin(),all.end(),b[i])-all.begin()); query(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__inv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_FUNCTIONAL_PP_V |
`timescale 1ps / 1ps
module ADC_interface_AXI_test (
);
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
localparam tries = 4;
localparam sword = 32;
localparam impl = 0;
localparam syncing = 0;
// Autogen localparams
reg CLK = 1'b0;
reg RST;
// AXI4-lite master memory interfaces
reg axi_awvalid;
wire axi_awready;
reg [sword-1:0] axi_awaddr;
reg [3-1:0] axi_awprot;
reg axi_wvalid;
wire axi_wready;
reg [sword-1:0] axi_wdata;
reg [4-1:0] axi_wstrb;
wire axi_bvalid;
reg axi_bready;
reg axi_arvalid;
wire axi_arready;
reg [sword-1:0] axi_araddr;
reg [3-1:0] axi_arprot;
wire axi_rvalid;
reg axi_rready;
wire [sword-1:0] axi_rdata;
//integer fd1, tmp1, ifstop;
integer PERIOD = 5000 ;
integer i, error;
ADC_interface_AXI
inst_ADC_interface_AXI (
.CLK(CLK),
.RST(RST),
.axi_awvalid(axi_awvalid),
.axi_awready(axi_awready),
.axi_awaddr(axi_awaddr),
.axi_awprot(axi_awprot),
.axi_wvalid(axi_wvalid),
.axi_wready(axi_wready),
.axi_wdata(axi_wdata),
.axi_wstrb(axi_wstrb),
.axi_bvalid(axi_bvalid),
.axi_bready(axi_bready),
.axi_arvalid(axi_arvalid),
.axi_arready(axi_arready),
.axi_araddr(axi_araddr),
.axi_arprot(axi_arprot),
.axi_rvalid(axi_rvalid),
.axi_rready(axi_rready),
.axi_rdata(axi_rdata),
.VP(0),
.VN(1)
);
always
begin #(PERIOD/2) CLK = ~CLK; end
task aexpect;
input [sword-1:0] av, e;
begin
if (av == e)
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e);
else
begin
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e);
error = error + 1;
end
end
endtask
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
task axi_write;
input [sword-1:0] waddr, wdata;
begin
#(PERIOD*8);
// WRITTING TEST
axi_awvalid = 1'b1;
axi_awaddr = waddr;
#PERIOD;
while(!axi_awready) begin
#PERIOD;
end
axi_awvalid = 1'b0;
axi_wvalid = 1'b1;
axi_wdata = wdata;
#PERIOD;
while(!axi_wready) begin
#PERIOD;
end
axi_wvalid = 1'b0;
while(!axi_bvalid) begin
#PERIOD;
end
//axi_bready = 1'b1;
#PERIOD;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
//axi_bready = 1'b0;
end
endtask
task axi_read;
input [sword-1:0] raddr;
begin
// READING TEST
#(PERIOD*8);
axi_arvalid = 1'b1;
axi_araddr = raddr;
#PERIOD;
while(!axi_arready) begin
#PERIOD;
end
axi_arvalid = 1'b0;
while(!axi_rvalid) begin
#PERIOD;
end
//axi_rready = 1'b1;
#PERIOD;
axi_arvalid = 1'b0;
//axi_rready = 1'b0;
end
endtask
initial begin
//$sdf_annotate("AXI_SRAM.sdf",AXI_SRAM);
CLK = 1'b0;
RST = 1'b0;
error = 0;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
axi_bready = 1'b1;
axi_arvalid = 1'b0;
axi_rready = 1'b1;
axi_awaddr = {sword{1'b0}};
axi_awprot = {3{1'b0}};
axi_wdata = {sword{1'b0}};
axi_wstrb = 4'b1111;
axi_araddr = {sword{1'b0}};
axi_arprot = {3{1'b0}};
#101000;
RST = 1'b1;
while(1) begin
axi_read(32'h00000000 << 2);
axi_read(32'h00000001 << 2);
axi_read(32'h00000002 << 2);
axi_read(32'h00000006 << 2);
axi_read(32'h00000010 << 2);
axi_read(32'h00000011 << 2);
axi_read(32'h00000012 << 2);
axi_read(32'h00000013 << 2);
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int q, k; cin >> q; long long l, r, d, x; for (k = 0; k < q; ++k) { cin >> l >> r >> d; if (d < l || d > r) x = d; else { if (r % d == 0) x = r + d; else x = r + (d - (r % d)); } cout << x << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<bool> visited; vector<vector<int>> adj; vector<int> depth; void dfs(int v, int d) { if (visited[v]) { return; } visited[v] = true; depth[d]++; for (int i : adj[v]) { dfs(i, d + 1); } } int main() { int n; cin >> n; visited.resize(n + 1); adj.resize(n + 1); for (int i = 2; i <= n; i++) { int to; cin >> to; adj[to].push_back(i); } depth.resize(n + 1); dfs(1, 0); int collected = 0; for (int i : depth) { collected += i % 2; } cout << collected << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char str[1010]; int pri[510][510]; int pre[510][510]; int f[510][510]; bool v[510] = {0}; int N; void init() { gets(str); scanf( %d , &N); } void prework() { int len = strlen(str); for (int i = 0; i < len; ++i) for (int j = 0; j < len; ++j) { int p = 0; int tmp = 0; while (i + p < j - p) { if (str[i + p] != str[j - p]) tmp++; p++; } pri[i + 1][j + 1] = tmp; } } void dp() { int len = strlen(str); memset(f, 10, sizeof(f)); f[0][0] = 0; for (int i = 1; i <= len; ++i) { for (int j = 1; j <= N; ++j) for (int k = 0; k < i; ++k) { if (f[i][j] > f[k][j - 1] + pri[k + 1][i]) { f[i][j] = f[k][j - 1] + pri[k + 1][i]; pre[i][j] = k; } } } int Ans = 1000000000; int p; for (int i = 1; i <= N; ++i) if (f[len][i] < Ans) { Ans = f[len][i]; p = i; } printf( %d n , Ans); int q = len; while (q != 0) { v[pre[q][p]] = 1; int x = 0; while (pre[q][p] + x < q - 1 - x) { str[pre[q][p] + x] = str[q - 1 - x]; x++; } q = pre[q][p]; p--; } v[0] = 0; for (int i = 0; i < len; ++i) { if (v[i]) putchar( + ); putchar(str[i]); } } int main() { init(); prework(); dp(); return 0; } |
#include <bits/stdc++.h> using namespace std; set<int> s[400000]; int bl[400000], S[400000], sz, n, m; void dfs(int x, int y) { bl[x] = y; ++sz; for (int z : s[x]) if (z != 1 && !bl[z]) dfs(z, y); } void dft(int x) { S[x] = sz; for (int y : s[x]) if (y != 1 && !S[y]) dft(y); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); s[x].insert(y); s[y].insert(x); } if (s[1].count(n)) return printf( 1 n1 %d n , n), 0; for (int x : s[1]) if (s[x].count(n)) return printf( 2 n1 %d %d n , x, n), 0; for (int x : s[1]) for (int y : s[x]) if (s[y].count(n)) return printf( 3 n1 %d %d %d n , x, y, n), 0; for (int x : s[1]) for (int y : s[x]) if (y != 1 && !s[1].count(y)) return printf( 4 n1 %d %d 1 %d n , x, y, n), 0; if (!s[1].size()) return puts( -1 ), 0; for (int x : s[1]) if (!bl[x]) { sz = 0; dfs(x, x); dft(x); } int mn = n + 10, mid = 0; for (int x : s[1]) if (S[x] != s[x].size()) { if (s[x].size() < mn) { mn = s[x].size(); mid = x; } } if (mid) { puts( 5 ); for (int y : s[mid]) if (y != 1) for (int z : s[y]) if (z != 1 && z != mid && !s[mid].count(z)) return printf( 1 %d %d %d %d %d n , mid, y, z, mid, n), 0; } puts( -1 ); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_spi (
spi_cs0n,
spi_cs1n,
spi_clk,
spi_sd_en,
spi_sd_o,
spi_sd_i,
up_rstn,
up_clk,
up_spi_start,
up_spi_devsel,
up_spi_wdata,
up_spi_rdata,
up_spi_status,
debug_data,
debug_trigger);
output spi_cs0n;
output spi_cs1n;
output spi_clk;
output spi_sd_en;
output spi_sd_o;
input spi_sd_i;
input up_rstn;
input up_clk;
input up_spi_start;
input up_spi_devsel;
input [23:0] up_spi_wdata;
output [ 7:0] up_spi_rdata;
output up_spi_status;
output [63:0] debug_data;
output [ 7:0] debug_trigger;
reg spi_cs0n;
reg spi_cs1n;
reg spi_clk;
reg spi_sd_en;
reg spi_sd_o;
reg spi_count_5_d;
reg [ 2:0] spi_clk_count;
reg [ 5:0] spi_count;
reg spi_rwn;
reg [23:0] spi_data_out;
reg [ 7:0] spi_data_in;
reg up_spi_start_d;
reg up_spi_status;
reg [ 7:0] up_spi_rdata;
wire spi_cs_en_s;
assign debug_trigger[7] = spi_cs0n;
assign debug_trigger[6] = spi_cs1n;
assign debug_trigger[5] = spi_sd_en;
assign debug_trigger[4] = spi_count[5];
assign debug_trigger[3] = up_spi_devsel;
assign debug_trigger[2] = up_spi_start;
assign debug_trigger[1] = up_spi_start_d;
assign debug_trigger[0] = up_spi_status;
assign debug_data[63:62] = 'd0;
assign debug_data[61:61] = spi_cs_en_s;
assign debug_data[60:60] = up_spi_start_d;
assign debug_data[59:52] = up_spi_rdata;
assign debug_data[51:44] = spi_data_in;
assign debug_data[43:20] = spi_data_out;
assign debug_data[19:19] = spi_rwn;
assign debug_data[18:18] = spi_count_5_d;
assign debug_data[17:12] = spi_count;
assign debug_data[11: 9] = spi_clk_count;
assign debug_data[ 8: 8] = up_spi_status;
assign debug_data[ 7: 7] = up_spi_devsel;
assign debug_data[ 6: 6] = up_spi_start;
assign debug_data[ 5: 5] = spi_sd_i;
assign debug_data[ 4: 4] = spi_sd_o;
assign debug_data[ 3: 3] = spi_sd_en;
assign debug_data[ 2: 2] = spi_clk;
assign debug_data[ 1: 1] = spi_cs1n;
assign debug_data[ 0: 0] = spi_cs0n;
assign spi_cs_en_s = spi_count_5_d | spi_count[5];
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
spi_cs0n <= 'd1;
spi_cs1n <= 'd1;
spi_clk <= 'd0;
spi_sd_en <= 'd0;
spi_sd_o <= 'd0;
spi_count_5_d <= 'd0;
spi_clk_count <= 'd0;
spi_count <= 'd0;
spi_rwn <= 'd0;
spi_data_out <= 'd0;
spi_data_in <= 'd0;
up_spi_start_d <= 'd0;
up_spi_status <= 'd0;
up_spi_rdata <= 'd0;
end else begin
spi_cs0n <= up_spi_devsel | (~spi_cs_en_s);
spi_cs1n <= (~up_spi_devsel) | (~spi_cs_en_s);
spi_clk <= spi_clk_count[2] & spi_count[5];
spi_sd_en <= (spi_count[5:3] == 3'b111) ? spi_rwn : 1'b0;
spi_sd_o <= spi_data_out[23];
if (spi_clk_count == 3'b100) begin
spi_count_5_d <= spi_count[5];
end
spi_clk_count <= spi_clk_count + 1'b1;
if (spi_count[5] == 1'b1) begin
if (spi_clk_count == 3'b111) begin
spi_count <= spi_count + 1'b1;
end
spi_rwn <= spi_rwn;
if (spi_clk_count == 3'b111) begin
spi_data_out <= {spi_data_out[22:0], 1'b0};
end
if ((spi_clk_count == 3'b100) && (spi_rwn == 1'b1) && (spi_count[5:3] == 3'b111)) begin
spi_data_in <= {spi_data_in[6:0], spi_sd_i};
end
end else if ((spi_clk_count == 3'b111) && (up_spi_start == 1'b1) &&
(up_spi_start_d == 1'b0)) begin
spi_count <= 6'h28;
spi_rwn <= up_spi_wdata[23];
spi_data_out <= up_spi_wdata;
spi_data_in <= 8'd0;
end
if (spi_clk_count == 3'b111) begin
up_spi_start_d <= up_spi_start;
end
up_spi_status <= ~(spi_count[5] | (up_spi_start & ~up_spi_start_d));
up_spi_rdata <= spi_data_in;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/* lab2_part6.v
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab2_part6 (SW, LEDG, LEDR, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0);
input [17:0] SW;
output [8:0] LEDR, LEDG;
output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
assign LEDR[8:0] = SW[8:0];
reg [4:0] T1, T0;
reg [3:0] Z1, Z0, S2, S1, S0;
reg c2, c1;
always begin
T0 = SW[3:0] + SW[11:8];
if (T0 > 9) begin
Z0 = 10;
c1 = 1;
end else begin
Z0 = 0;
c1 = 0;
end
S0 = T0 - Z0;
T1 = SW[7:4] + SW[15:12] + c1;
if (T1 > 9) begin
Z1 = 10;
c2 = 1;
end else begin
Z1 = 0;
c2 = 0;
end
S1 = T1 - Z1;
S2 = c2;
end
b2d_7seg H0 (S0, HEX0);
b2d_7seg H1 (S1, HEX1);
b2d_7seg H2 (S2, HEX2);
assign HEX3 = 7'b1111111;
b2d_7seg H4 (SW[3:0], HEX4);
b2d_7seg H5 (SW[7:4], HEX5);
b2d_7seg H6 (SW[11:8], HEX6);
b2d_7seg H7 (SW[15:12], HEX7);
endmodule
module b2d_7seg (X, SSD);
input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]));
assign SSD[2] = (~X[3] & ~X[2] & X[1] & ~X[0]);
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
endmodule
|
module I2C_AV_Config ( // Host Side
iCLK,
iRST_N,
// I2C Side
I2C_SCLK,
I2C_SDAT );
// Host Side
input iCLK;
input iRST_N;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 51;
// Audio Data Index
parameter Dummy_DATA = 0;
parameter SET_LIN_L = 1;
parameter SET_LIN_R = 2;
parameter SET_HEAD_L = 3;
parameter SET_HEAD_R = 4;
parameter A_PATH_CTRL = 5;
parameter D_PATH_CTRL = 6;
parameter POWER_ON = 7;
parameter SET_FORMAT = 8;
parameter SAMPLE_CTRL = 9;
parameter SET_ACTIVE = 10;
// Video Data Index
parameter SET_VIDEO = 11;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
if(LUT_INDEX<SET_VIDEO)
mI2C_DATA <= {8'h34,LUT_DATA};
else
mI2C_DATA <= {8'h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
Dummy_DATA : LUT_DATA <= 16'h0000;
SET_LIN_L : LUT_DATA <= 16'h001A;
SET_LIN_R : LUT_DATA <= 16'h021A;
SET_HEAD_L : LUT_DATA <= 16'h047B;
SET_HEAD_R : LUT_DATA <= 16'h067B;
A_PATH_CTRL : LUT_DATA <= 16'h08F8;
D_PATH_CTRL : LUT_DATA <= 16'h0A06;
POWER_ON : LUT_DATA <= 16'h0C00;
SET_FORMAT : LUT_DATA <= 16'h0E01;
SAMPLE_CTRL : LUT_DATA <= 16'h1002;
SET_ACTIVE : LUT_DATA <= 16'h1201;
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0860;
SET_VIDEO+31: LUT_DATA <= 16'h0a18;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df2;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
default: LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule |
#include <bits/stdc++.h> using namespace std; const int dx[] = {0, 1, -1, 0, 0}; const int dy[] = {0, 0, 0, 1, -1}; struct MinCostMaxFlow { int head[20010], total; int next[1000010], aim[1000010], flow[1000010], cost[1000010]; int f[20010], from[20010], p[20010]; bool v[20010]; MinCostMaxFlow() : total(1) {} void Add(int x, int y, int f, int c) { next[++total] = head[x]; aim[total] = y; flow[total] = f; cost[total] = c; head[x] = total; } void Insert(int x, int y, int f, int c) { Add(x, y, f, c); Add(y, x, 0, -c); } bool SPFA() { static queue<int> q; while (!q.empty()) q.pop(); memset(f, 0x3f, sizeof(f)); memset(v, false, sizeof(v)); f[0] = 0; q.push(0); while (!q.empty()) { int x = q.front(); q.pop(); v[x] = false; for (int i = head[x]; i; i = next[i]) if (flow[i] && f[aim[i]] > f[x] + cost[i]) { f[aim[i]] = f[x] + cost[i]; if (!v[aim[i]]) v[aim[i]] = true, q.push(aim[i]); from[aim[i]] = x; p[aim[i]] = i; } } return f[(20010 - 1)] != 0x3f3f3f3f; } int EdmondsKarp() { int re = 0; while (SPFA()) { int max_flow = 0x3f3f3f3f; for (int i = (20010 - 1); i != 0; i = from[i]) max_flow = ((max_flow) < (flow[p[i]]) ? (max_flow) : (flow[p[i]])); for (int i = (20010 - 1); i != 0; i = from[i]) { flow[p[i]] -= max_flow; flow[p[i] ^ 1] += max_flow; } re += f[(20010 - 1)] * max_flow; } return re; } } solver; int m, n; int src[110][110]; int main() { cin >> m >> n; for (int i = 1; i <= m; ++i) for (int j = 1; j <= n; ++j) scanf( %d , &src[i][j]); for (int i = 1; i <= m; ++i) for (int j = 1; j <= n; ++j) { if (i + j & 1) { solver.Insert(0, ((i - 1) * n + j), 1, 0); for (int k = 1; k <= 4; ++k) { int fx = i + dx[k], fy = j + dy[k]; if (!fx || !fy || fx > m || fy > n) continue; solver.Insert(((i - 1) * n + j), ((fx - 1) * n + fy), 1, src[i][j] != src[fx][fy]); } } else solver.Insert(((i - 1) * n + j), (20010 - 1), 1, 0); } cout << solver.EdmondsKarp() << endl; return 0; } |
/* ctrl_clk_xilinx.v */
/* 2012, */
module ctrl_clk_xilinx (
input wire inclk0,
output wire c0,
output wire c1,
output wire c2,
output wire locked
);
// internal wires
wire pll_50;
wire dll_50;
wire dll_100;
reg clk_25 = 0;
// pll
DCM #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(32), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(24), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(15.015), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) pll (
.CLKIN(inclk0), // Clock input (from IBUFG, BUFG or DCM)
.CLKFX(pll_50) // DCM CLK synthesis out (M/D) (49.950 MHz)
);
// dll
DCM #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20.020), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) dll (
.CLKIN(pll_50), // Clock input (from IBUFG, BUFG or DCM)
.CLK0(dll_50),
.CLK2X(dll_100),
.CLKFB(c1),
.LOCKED(locked)
);
// 25MHz clock
always @ (posedge c0) begin
clk_25 <= #1 ~clk_25;
end
// global clock buffers
BUFG BUFG_100 (.I(dll_100), .O(c0));
BUFG BUFG_50 (.I(dll_50), .O(c1));
BUFG BUFG_25 (.I(clk_25), .O(c2));
endmodule
|
#include <bits/stdc++.h> struct Candidate { std::vector<int> d; Candidate(std::vector<int> d_) { d = d_; std::sort(d.begin(), d.end()); std::reverse(d.begin(), d.end()); } inline bool operator<(const Candidate &rhs) { if (d[0] < 0 || rhs.d[0] < 0) return d[0] < rhs.d[0]; for (int i = 0; i < static_cast<int>(d.size()); ++i) if (d[i] != rhs.d[i]) return d[i] < rhs.d[i]; return false; } }; int get_enemy_pos(std::vector<int> locations, bool mate) { std::cout << locations[0] + 1 << << locations[1] + 1 << << locations[2] + 1 << std::endl; if (!mate) { int pos; std::cin >> pos; return pos - 1; } else { return -1; } } std::vector<int> get_dist(std::vector<std::vector<int> > &adj, int src) { auto d = std::vector<int>(adj.size(), -1); auto q = std::queue<int>(); q.push(src); d[src] = 0; while (!q.empty()) { int at = q.front(); q.pop(); for (auto &next : adj[at]) { if (d[next] < 0) { d[next] = d[at] + 1; q.push(next); } } } return d; } int main() { int nodes, edges; std::cin >> nodes >> edges; auto adj = std::vector<std::vector<int> >(nodes, std::vector<int>()); for (int edge = 0; edge < edges; ++edge) { int src, dst; std::cin >> src >> dst; adj[src - 1].push_back(dst - 1); adj[dst - 1].push_back(src - 1); } srand(time(NULL)); auto dists = std::vector<std::vector<int> >(static_cast<int>(adj.size()), std::vector<int>()); int best_dist = nodes + 1; auto best_locs = std::vector<int>(3, -1); for (int iter = 0; iter < 5000; ++iter) { auto locs = std::vector<int>(3); for (int i = 0; i < static_cast<int>(locs.size()); ++i) { locs[i] = -1; bool ok = true; do { ok = true; locs[i] = rand() % nodes; for (int j = 0; j < i; ++j) { if (locs[i] == locs[j]) ok = false; } } while (!ok); if (dists[locs[i]].size() == 0) { dists[locs[i]] = get_dist(adj, locs[i]); } } int cand_dist = 1; for (int i = 0; i < nodes; ++i) { cand_dist = std::max( cand_dist, std::min(dists[locs[0]][i], std::min(dists[locs[1]][i], dists[locs[2]][i]))); } if (cand_dist < best_dist) { best_dist = cand_dist; best_locs = locs; } } auto locs = best_locs; auto enemy_pos = get_enemy_pos(locs, false); while (enemy_pos >= 0) { if (enemy_pos == locs[0] || enemy_pos == locs[1] || enemy_pos == locs[2]) { break; } auto targets = std::vector<int>(); targets.push_back(enemy_pos); for (int repeats = 0; repeats < 0; ++repeats) { auto ntargets = std::vector<int>(); for (auto &t : targets) for (auto &x : adj[t]) { ntargets.push_back(x); } for (auto &nt : ntargets) targets.push_back(nt); std::sort(targets.begin(), targets.end()); targets.resize(std::unique(targets.begin(), targets.end()) - targets.begin()); } for (auto &x : targets) { if (dists[x].size() == 0) { dists[x] = get_dist(adj, x); } } auto d = std::vector<int>(static_cast<int>(locs.size())); auto best = Candidate(std::vector<int>(static_cast<int>(locs.size()), nodes + 1)); static int best_locs[] = {-1, -1, -1}; static int by[3]; static int choice[3]; for (int i = 0; i < 3; ++i) { std::random_shuffle(adj[locs[i]].begin(), adj[locs[i]].end()); } for (choice[0] = 0; choice[0] <= adj[locs[0]].size(); ++choice[0]) for (choice[1] = 0; choice[1] <= adj[locs[1]].size(); ++choice[1]) for (choice[2] = 0; choice[2] <= adj[locs[2]].size(); ++choice[2]) { bool mate = false; for (int i = 0; i < 3; ++i) { by[i] = (choice[i] == 0 ? locs[i] : adj[locs[i]][choice[i] - 1]); if (by[i] == enemy_pos) mate = true; } if (by[0] == by[1] || by[1] == by[2] || by[0] == by[2]) { continue; } for (int j = 0; j < 3; ++j) d[j] = dists[targets[0]][by[j]]; auto cand = Candidate(d); if (mate) { cand.d[0] = -1; } if (cand < best) { best = cand; for (int i = 0; i < 3; ++i) { best_locs[i] = by[i]; } } } locs = std::vector<int>(best_locs, best_locs + 3); enemy_pos = get_enemy_pos(locs, best.d[0] < 0); } return 0; } |
#include <bits/stdc++.h> std::vector<std::vector<int>> ad; std::vector<int> fm; std::vector<bool> tmp; int f(int x) { if (fm[x] >= 0) return fm[x]; for (int y : ad[x]) f(y); for (int y : ad[x]) tmp[fm[y]] = true; fm[x] = int(std::find(begin(tmp), end(tmp), false) - begin(tmp)); for (int y : ad[x]) { tmp[fm[y]] = false; } return fm[x]; } int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); int n, m; std::cin >> n >> m; std::vector<int> h(n); for (int& x : h) std::cin >> x; ad.resize(n); for (int z = m; z--;) { int u, v; std::cin >> u >> v; --u; --v; ad[u].push_back(v); } std::vector<int> val(n); fm.assign(n, -1); tmp.resize(n); for (int i = n; i--;) val[f(i)] ^= h[i]; while (!val.empty() && val.back() == 0) val.pop_back(); if (val.empty()) { std::cout << LOSE n ; return 0; } std::cout << WIN n ; int i = 0; while (fm[i] != val.size() - 1 || (h[i] ^ val.back()) > h[i]) { ++i; } h[i] ^= val.back(); std::vector<bool> ok(val.size() - 1); for (int j : ad[i]) if ((unsigned)fm[j] < ok.size() && !ok[fm[j]]) { ok[fm[j]] = true; h[j] ^= val[fm[j]]; } for (auto x : h) std::cout << x << ; std::cout << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { double x, y, a, b, t; while (cin >> a >> b) { int n; cin >> n; double p = 1e18; for (int i = 0; i < n; i++) { cin >> x >> y >> t; p = min(p, hypot((x - a), (y - b)) / t); } printf( %.20lf , p); } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_0_rows_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_0_rows_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_0_rows_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_0_rows_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_uart_tx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 8'd0;
reg s_axis_tvalid = 1'b0;
reg [15:0] prescale = 0;
// Outputs
wire s_axis_tready;
wire txd;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
prescale);
$to_myhdl(s_axis_tready,
txd,
busy);
// dump file
$dumpfile("test_uart_tx.lxt");
$dumpvars(0, test_uart_tx);
end
uart_tx #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
// output
.txd(txd),
// status
.busy(busy),
// configuration
.prescale(prescale)
);
endmodule
|
`include "timescale.v"
module fb_slave_counters (MRxClk, Reset, MRxDEqDataSoC,
StateIdle, StatePreamble, StateData, StateSlaveData, StateSlaveCrc, StateFrmCrc,
TotalNibCnt, NibCnt, SlaveCrcEnd, FrmCrcStateEnd, TxRamAddr, RxRamAddr, SlaveByteCntEq0, IncrementTotalNibCnt
);
input MRxClk; // Tx clock
input Reset; // Reset
input StateIdle; // Idle state
input StatePreamble; // Preamble state
input StateData; // Data state
input [1:0] StateSlaveData; // StateSlaveData state
input StateSlaveCrc; // slave CRC state
input StateFrmCrc;
input MRxDEqDataSoC;
output [15:0] TotalNibCnt; // total Nibble counter
output [15:0] NibCnt; // Nibble counter
output SlaveCrcEnd;
output FrmCrcStateEnd;
output [7: 0] TxRamAddr;
output [7: 0] RxRamAddr;
output SlaveByteCntEq0;
output IncrementTotalNibCnt;
wire SlaveByteCntEq0;
wire [3:0] CrcNibbleCnt;
reg [15:0] TotalNibCnt;
reg [15:0] NibCnt;
reg [3: 0] CrcNibCnt;
reg [3: 0] PreambleNibCnt;
reg [3: 0] FrmCrcNibCnt;
reg [7: 0] TxRamAddr;
reg [7: 0] RxRamAddr;
assign CrcNibbleCnt = 4'd2;
wire ResetNibCnt;
wire IncrementNibCnt;
assign IncrementNibCnt = (|StateSlaveData) ;
assign ResetNibCnt = StateIdle | StateData ;
// Nibble Counter started from each slave data( only for data, no SoC no CRC)
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
NibCnt <= 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 16'd1;
end
end
wire ResetTotalNibCnt;
wire IncrementTotalNibCnt;
assign IncrementTotalNibCnt = StatePreamble | StateData | (|StateSlaveData) | StateSlaveCrc ;
assign ResetTotalNibCnt = StateIdle;
// Total Nibble Counter for the whole frame incl.( Preamble, SlaveDate, SlaveCRC, NO FrameCRC)
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TotalNibCnt <= 16'h0;
else
begin
if(ResetTotalNibCnt)
TotalNibCnt <= 16'h0;
else
if(IncrementTotalNibCnt)
TotalNibCnt <= TotalNibCnt + 16'd1;
end
end
wire IncrementCrcNibCnt;
wire ResetCrcNibCnt;
assign IncrementCrcNibCnt = StateSlaveCrc ;
assign ResetCrcNibCnt = |StateSlaveData ;
assign SlaveCrcEnd = CrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
CrcNibCnt <= 4'b0;
else
begin
if(ResetCrcNibCnt)
CrcNibCnt <= 4'b0;
else
if(IncrementCrcNibCnt)
CrcNibCnt <= CrcNibCnt + 4'b0001;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateIdle | StatePreamble | StateData | (|StateSlaveData) | StateSlaveCrc;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
wire IncrementTxRamAddr;
wire ResetTxRamAddr;
assign ResetTxRamAddr = StateIdle | StatePreamble | StateData;
assign IncrementTxRamAddr = StartSlaveData[0];
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TxRamAddr <= 8'b0;
else
begin
if(ResetTxRamAddr)
TxRamAddr <= 8'b0;
else
if(IncrementTxRamAddr)
TxRamAddr <= TxRamAddr + 8'b0001;
end
end
wire ResetRxRamAddr;
wire IncrementRxRamAddr;
assign ResetRxRamAddr = StateIdle | StateFFS | StatePreamble | StateData;
assign IncrementRxRamAddr = RxValid ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxRamAddr[7:0] <= 8'd0;
else
begin
if(ResetRxRamAddr)
RxRamAddr[7:0] <= 8'd0;
else
if(IncrementRxRamAddr)
RxRamAddr[7:0] <= RxRamAddr[7:0] + 8'd1;
end
end
wire ResetByteCounter;
wire IncrementByteCounter;
wire ByteCntMax;
assign ResetByteCounter = MRxDV & StatePreamble & MRxDEqDataSoC | StateData;
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &( StateSlaveData[1] & ~ByteCntMax ) ;
assign SlaveByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntMax = ByteCnt == 16'hffff;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: mem_1k.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mem_1k (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [63:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL rdaddress[9..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL wraddress[9..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 22:59:47 05/31/2016
// Design Name:
// Module Name: top_reloj_digital_v2.0
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_reloj_digital_v2
(
input wire clk, reset,
input wire ps2data,
input wire ps2clk,
inout [7:0] dato,
output wire AD, CS, WR, RD,
output wire alarma_sonora,
output wire [7:0] RGB,
output wire hsync, vsync
);
//Conexiones internas
reg [7:0]in_port;
wire [7:0]out_port;
wire [7:0]port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha;
wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
wire fin_lectura_escritura;
wire [7:0] out_dato;
wire [7:0] ascii_code;
assign interrupt = 1'b0;
microcontrolador instancia_microcontrolador
(
.clk(clk),
.reset(reset),
.interrupt(interrupt),
.in_port(in_port),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.interrupt_ack(),
.port_id(port_id),
.out_port(out_port)
);
escritor_lector_rtc_2 instancia_escritor_lector_rtc_2
(
.clk(clk),
.reset(reset),
.in_dato(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.reg_a_d(AD),
.reg_cs(CS),
.reg_rd(RD),
.reg_wr(WR),
.out_dato(out_dato),
.flag_done(fin_lectura_escritura),
.dato(dato)
);
controlador_teclado_ps2 instancia_controlador_teclado_ps2
(
.clk(clk),
.reset(reset),
.ps2data(ps2data),
.ps2clk(ps2clk),
.port_id(port_id),
.read_strobe(read_strobe),
.ascii_code(ascii_code)
);
controlador_VGA instancia_controlador_VGA
(
.clock(clk),
.reset(reset),
.in_dato(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.out_seg_hora(out_seg_hora),
.out_min_hora(out_min_hora),
.out_hora_hora(out_hora_hora),
.out_dia_fecha(out_dia_fecha),
.out_mes_fecha(out_mes_fecha),
.out_jahr_fecha(out_jahr_fecha),
.out_seg_timer(out_seg_timer),
.out_min_timer(out_min_timer),
.out_hora_timer(out_hora_timer),
.alarma_sonora(alarma_sonora),
.hsync(hsync),
.vsync(vsync),
.RGB(RGB)
);
//Decodificación del puerto de entrada del microcontrolador
always@(posedge clk)
begin
case (port_id)
8'h0F : in_port <= fin_lectura_escritura;
8'h10 : in_port <= out_dato;
8'h02 : in_port <= ascii_code;
8'h12 : in_port <= out_seg_hora;
8'h13 : in_port <= out_min_hora;
8'h14 : in_port <= out_hora_hora;
8'h15 : in_port <= out_dia_fecha;
8'h16 : in_port <= out_mes_fecha;
8'h17 : in_port <= out_jahr_fecha;
8'h18 : in_port <= out_seg_timer;
8'h19 : in_port <= out_min_timer;
8'h1A : in_port <= out_hora_timer;
default : in_port <= 8'bXXXXXXXX;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 5e3; const double eps = 1e-14; double dp[NMAX + 5][NMAX + 5]; int n, k; double p[NMAX + 5]; double np[NMAX + 5]; int t[NMAX + 5]; int main() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) { int x; scanf( %d %d , &x, &t[i]); p[i] = x / 100.0; np[i] = (100 - x) / 100.0; } dp[0][0] = 1; for (int i = 0; i <= n; i++) { double prob = 1; for (int j = 1; j <= t[i + 1]; j++) { prob *= np[i + 1]; } for (int j = i; j <= k; j++) { if (dp[i][j] < eps) { continue; } if (j < k) { dp[i][j + 1] += dp[i][j] * np[i]; dp[i + 1][j + 1] += dp[i][j] * p[i + 1]; if (j <= k - t[i + 1]) { dp[i + 1][j + t[i + 1]] += dp[i][j] * prob; if (j <= k - t[i + 1] - 1) { dp[i + 1][j + t[i + 1] + 1] -= dp[i][j] * prob; } } } } } double ans = 0; for (int i = 1; i < n; i++) { double prob = 1; for (int j = k; j > k - t[i + 1]; j--) { ans += i * dp[i][j] * prob; prob *= (1 - p[i + 1]); } } for (int j = 1; j <= k; j++) { ans += n * dp[n][j]; } printf( %.9f n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2501; int dp[N][3], a[N << 1]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; memset(dp, 0x3f, sizeof(dp)); dp[0][0] = dp[1][1] = 0; for (int i = 2; i <= n; i++) for (int j = i + 1 >> 1; j; j--) { dp[j][0] = min(dp[j][0], dp[j][2]); dp[j][2] = dp[j][1] + max(0, a[i] - a[i - 1] + 1); dp[j][1] = min(dp[j - 1][0] + max(0, a[i - 1] - a[i] + 1), dp[j - 1][2] + max(0, min(a[i - 1], a[i - 2] - 1) - a[i] + 1)); } for (int j = 1; j <= n + 1 >> 1; j++) cout << min(dp[j][0], min(dp[j][1], dp[j][2])) << ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3000 + 12; int p[maxn]; int Et[maxn]; int mark[maxn][maxn]; queue<pair<int, int> > act; void input(int n) { for (int i = 0; i < n; i++) cin >> p[i]; } void solve(int n, int k) { int sef = 0; bool yek = 0; for (int j = n - 1; j >= 0; j--) { if (p[j] == 0) sef++; if (p[j] == 100) yek = 1; if (sef == n - j) Et[j] = 1; if (yek) Et[j] = 2; } act.push(make_pair(0, 1)); mark[0][1] = 0; int ans = 0; int x = 0, y = 1; while (act.size() && mark[x][y] <= k) { pair<int, int> a = act.front(); x = a.first, y = a.second; if (mark[x][y] <= k) ans++; if (Et[y] != 1 && p[x] != 0 && y + 2 <= n + 1 && mark[y + 1][y + 2] > mark[x][y] + 1) act.push(make_pair(y + 1, y + 2)), mark[y + 1][y + 2] = mark[x][y] + 1; if (Et[y] != 2 && p[x] != 0 && y + 1 <= n && mark[x][y + 1] > mark[x][y] + 1) act.push(make_pair(x, y + 1)), mark[x][y + 1] = mark[x][y] + 1; if (Et[y] != 1 && p[x] != 100 && y + 1 <= n && mark[y][y + 1] > mark[x][y] + 1) act.push(make_pair(y, y + 1)), mark[y][y + 1] = mark[x][y] + 1; act.pop(); } cout << ans; } int main() { int n, k; cin >> n >> k; input(n); memset(mark, 31, sizeof mark); solve(n, k); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_PP_SYMBOL_V
`define SKY130_FD_SC_LS__FA_PP_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int x[2000][10], y[2000][10]; double Ab(int x) { if (x >= 0) return x; return -x; }; double q(double x) { return x * x; }; double d(int i, int j) { double X, Y; if (x[i][0] == x[i][1] && y[j][0] == y[j][1]) { Y = min(Ab(y[i][0] - y[j][0]), Ab(y[i][1] - y[j][0])); if (y[j][0] <= y[i][1] && y[j][0] >= y[i][0]) Y = 0; X = min(Ab(x[j][0] - x[i][0]), Ab(x[j][1] - x[i][0])); if (x[i][0] <= x[j][1] && x[i][0] >= x[j][0]) X = 0; } else if (x[j][0] == x[j][1] && y[i][0] == y[i][1]) { Y = min(Ab(y[i][0] - y[j][0]), Ab(y[i][1] - y[j][1])); if (y[i][0] <= y[j][1] && y[i][0] >= y[j][0]) Y = 0; X = min(Ab(x[j][0] - x[i][0]), Ab(x[j][1] - x[i][1])); if (x[j][0] <= x[i][1] && x[j][0] >= x[i][0]) X = 0; } else if (x[i][0] == x[i][1]) { X = Ab(x[i][0] - x[j][0]); Y = min(min(Ab(y[i][1] - y[j][0]), Ab(y[i][1] - y[j][1])), min(Ab(y[i][0] - y[j][0]), Ab(y[i][0] - y[j][1]))); if (y[i][1] <= y[j][1] && y[i][1] >= y[j][0]) Y = 0; if (y[i][0] <= y[j][1] && y[i][0] >= y[j][0]) Y = 0; } else { Y = Ab(y[i][0] - y[j][0]); X = min(min(Ab(x[i][1] - x[j][0]), Ab(x[i][1] - x[j][1])), min(Ab(x[i][0] - x[j][0]), Ab(x[i][0] - x[j][1]))); if (x[i][1] <= x[j][1] && x[i][1] >= x[j][0]) X = 0; if (x[i][0] <= x[j][1] && x[i][0] >= x[j][0]) X = 0; } return (sqrt(q(X) + q(Y))); }; int main() { double a, b; cin >> a >> b; int xk, yk; scanf( %d%d%d%d , &x[0][0], &y[0][0], &xk, &yk); x[0][1] = x[0][0]; y[0][1] = y[0][0]; int n; scanf( %d , &n); x[n + 1][0] = xk; y[n + 1][0] = yk; x[n + 1][1] = xk; y[n + 1][1] = yk; for (int i = 1; i <= n; i++) { scanf( %d%d%d%d , &x[i][0], &y[i][0], &x[i][1], &y[i][1]); if (y[i][0] > y[i][1]) swap(y[i][0], y[i][1]); if (x[i][0] > x[i][1]) swap(x[i][0], x[i][1]); } queue<pair<int, int> > q; q.push(make_pair(0, 0)); bool was[2000]; for (int i = 0; i <= n + 1; i++) was[i] = false; was[0] = true; double ans = -1; while (!q.empty()) { pair<int, int> A = q.front(); q.pop(); int i = A.first; int k = A.second; if (d(n + 1, i) - a <= 1e-7) { double X = d(n + 1, i) + (a + b) * k; if (ans == -1) ans = X; else ans = min(ans, X); } for (int j = 0; j <= n; j++) { if (was[j]) continue; if (d(i, j) - a > 1e-7) continue; q.push(make_pair(j, k + 1)); was[j] = true; } } cout << fixed << setprecision(10); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> int T; int n, m; bool get() { char ch = getchar(); while (ch != O && ch != X ) ch = getchar(); return (ch == X ); } int map[21][21], con[4001][2], top, cnt[4001], head[401], nxt[100001], b[100001], k = 1, dis[4001], pre[4001]; char ans[41][41]; int q[4001], h, t; void push(int s, int t) { nxt[++k] = head[s]; head[s] = k; b[k] = t; } bool iscut[4001], chosen[4001], lim[4001], good[4001][4001]; std::vector<int> vec[4001]; int Cnt; int hash(int i, int j) { return (i - 1) * m + j; } void dfs(int x, bool *vis) { if (vis[x]) return; ++Cnt; vis[x] = 1; for (int i = head[x]; i; i = nxt[i]) if (!chosen[i >> 1]) dfs(b[i], vis); } int main() { scanf( %d , &T); for (int fd = 1; fd <= T; fd++) { scanf( %d%d , &n, &m); int all = 0; top = 0; memset(chosen, 0, sizeof chosen); memset(lim, 0, sizeof lim); memset(head, 0, sizeof head); k = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) map[i][j] = get(), all += (!map[i][j]); for (int i = 1; i < n; i++) for (int j = 1; j <= m; j++) if (!map[i][j] && !map[i + 1][j]) { ++top; con[top][0] = hash(i, j); con[top][1] = hash(i + 1, j); push(hash(i, j), hash(i + 1, j)); push(hash(i + 1, j), hash(i, j)); } for (int i = 1; i <= n; i++) for (int j = 1; j < m; j++) if (!map[i][j] && !map[i][j + 1]) { ++top; con[top][0] = hash(i, j); con[top][1] = hash(i, j + 1); push(hash(i, j), hash(i, j + 1)); push(hash(i, j + 1), hash(i, j)); } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if ((i + j) % 2 == 0 && (i > 1 || j > 1)) lim[hash(i, j)] = 1; memset(cnt, 0, sizeof cnt); for (int i = 1; i <= top; i++) { ++cnt[con[i][0]], ++cnt[con[i][1]]; } bool cando = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (lim[hash(i, j)] && cnt[hash(i, j)] <= 1 && !map[i][j]) { cando = 0; } memset(good[0], 0, sizeof good[0]); Cnt = 0; dfs(1, good[0]); if (Cnt < all) cando = 0; if (!cando) puts( NO ); else { for (;;) { memset(cnt, 0, sizeof cnt); for (int i = 1; i <= top; i++) if (!chosen[i]) { if (lim[con[i][0]]) ++cnt[con[i][0]]; else ++cnt[con[i][1]]; Cnt = 0; chosen[i] = 1; memset(good[i], 0, sizeof good[i]); dfs(1, good[i]); iscut[i] = (Cnt < all); chosen[i] = 0; } for (int i = 1; i <= top; i++) vec[i].clear(); for (int i = 1; i <= top; i++) if (chosen[i]) for (int j = 1; j <= top; j++) if (!chosen[j]) { int u = (lim[con[i][0]] ? con[i][0] : con[i][1]), v = (lim[con[j][0]] ? con[j][0] : con[j][1]); if (u == v || cnt[v] >= 3) { vec[j].push_back(i); } if (!iscut[j] || good[j][con[i][0]] != good[j][con[i][1]]) { vec[i].push_back(j); } } h = t = 0; for (int i = 1; i <= top; i++) { dis[i] = 0x7f7f7f7f; pre[i] = 0; if (!chosen[i] && !iscut[i]) dis[i] = 0, q[++t] = i; } while (h < t) { ++h; for (int i = 0; i < vec[q[h]].size(); i++) if (dis[vec[q[h]][i]] == 0x7f7f7f7f) { dis[vec[q[h]][i]] = dis[q[h]] + 1; q[++t] = vec[q[h]][i]; pre[vec[q[h]][i]] = q[h]; } } int p = 0; for (int i = 1; i <= top; i++) { if (!chosen[i] && (cnt[con[i][0]] >= 3 || !lim[con[i][0]]) && (cnt[con[i][1]] >= 3 || !lim[con[i][1]]) && dis[i] != 0x7f7f7f7f) { if (!p || dis[p] > dis[i]) p = i; } } if (!p) break; while (p) { chosen[p] ^= 1; p = pre[p]; } } Cnt = 0; for (int i = 1; i <= top; i++) Cnt += (!chosen[i]); if (Cnt != all - 1) puts( NO ); else { puts( YES ); for (int i = 1; i <= (n << 1); i++) for (int j = 1; j <= (m << 1); j++) ans[i][j] = ; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) ans[(i << 1) - 1][(j << 1) - 1] = (map[i][j]) ? X : O ; for (int i = 1; i <= top; i++) if (!chosen[i]) { int u = con[i][0], v = con[i][1]; if (v == u + 1) ans[(((u - 1) / m + 1) << 1) - 1][((u - 1) % m + 1) << 1] = O ; else ans[(((u - 1) / m + 1) << 1)][(((u - 1) % m + 1) << 1) - 1] = O ; } for (int i = 1; i < (n << 1); i++, putchar( n )) for (int j = 1; j < (m << 1); j++) putchar(ans[i][j]); } } } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100001; int q, n; int d[MAXN], p[MAXN]; int main() { cin >> q; int small = 1 << 30; for (int i = 0; i < q; ++i) { cin >> d[i]; small = ((small) > (d[i]) ? (d[i]) : (small)); } cin >> n; for (int i = 0; i < n; ++i) { cin >> p[i]; } sort(p, p + n, greater<int>()); int cost = 0; for (int i = 0; i < n; i++) { if (i % (small + 2) < small) { cost += p[i]; } } cout << cost << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100500; int n, m; int a[30]; string s, t; char ans[5500]; void po_poryadky(int x) { for (int i = x; i < n; i++) { for (int j = 0; j < 30; j++) if (a[j]) { ans[i] = (char)( a + j); a[j]--; break; } } } void ubiraem(int x) { for (int i = x; i >= 0; i--) { int num = ans[i] - a ; a[num]++; for (int j = num + 1; j < 30; j++) if (a[j]) { ans[i] = (char)( a + j); a[j]--; po_poryadky(i + 1); return; } } cout << -1; exit(0); } void v_roven() { for (int i = 0; i < m; i++) { int num = t[i] - a ; if (a[num] != 0) { ans[i] = t[i]; a[num]--; continue; } for (int j = num + 1; j < 30; j++) if (a[j]) { a[j]--; ans[i] = (char)( a + j); po_poryadky(i + 1); return; } ubiraem(i - 1); return; } if (n == m) ubiraem(m - 1); else po_poryadky(m); } int main() { cin >> s >> t; n = s.size(); m = t.size(); for (int i = 0; i < n; i++) a[(int)(s[i] - a )]++; v_roven(); ans[n] = 0 ; cout << ans; return 0; } |
#include<bits/stdc++.h> #define ll long long using namespace std; int x[100005]; int idx=0; int d[100005]; int main() { int t; cin>>t; while(t--){ int n; cin>>n; idx=0; for(int i=1;i<=n;i++){ scanf( %d ,&x[i]); } for(int i=n;i>=1;i--){ if(idx==0){ d[++idx]=i; } else{ while(idx>0&&x[i]>x[d[idx]]){ idx--; } d[++idx]=i; } } for(int i=1;i<=idx;i++){ int ma; if(i==1) ma=n+1; else ma=d[i-1]; for(int j=d[i];j<ma;j++){ cout<<x[j]<< ; } } cout<<endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; typedef struct line { int k; int b; long double x; } line; bool com(line l1, line l2) { if (l1.x < l2.x) return true; else return false; } int main() { long long k, b, n, t; cin >> k >> b >> n >> t; long long x = 1; int t1 = 0; while (x < t) { x = k * x + b; t1++; } if (x != t) t1--; if (t1 < n) { cout << n - t1; } else cout << 0; return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Conversion_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Conversion_ROM (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../ADC.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../ADC.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../ADC.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int M, N, maxH[100009], d[100009]; void dfs(int nod) { if (nod >= (1 << N)) { maxH[nod] = 0; return; } int f1 = nod << 1, f2 = f1 | 1; dfs(f1), dfs(f2); maxH[nod] = max(maxH[f1] + d[f1], maxH[f2] + d[f2]); } int ans = 0; void solve(int nod) { if (nod >= (1 << N)) return; int f1 = nod << 1, f2 = f1 | 1; if (maxH[f1] + d[f1] < maxH[f2] + d[f2]) swap(f1, f2); solve(f1); ans += maxH[nod] - (maxH[f2] + d[f2]); solve(f2); } int main() { scanf( %d , &N), M = (1 << (N + 1)) - 1; for (int i = 2; i <= M; i++) scanf( %d , &d[i]); dfs(1); solve(1); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int dp[50][50]; int m, n; int main() { for (int x = 0; x < 36; x++) { dp[0][x] = 1; } for (int x = 1; x < 36; x++) for (int y = 1; y < 36; y++) for (int z = 0; z < x; z++) { dp[x][y] += dp[z][y - 1] * dp[x - z - 1][y - 1]; } cin >> m >> n; cout << dp[m][35] - dp[m][n - 1] << endl; } |
module pi2c (/*AUTOARG*/
// Outputs
i2c_sda_i, i2c_scl_i,
// Inouts
i2c_sda, i2c_scl,
// Inputs
i2c_sda_o, i2c_sda_t, i2c_scl_o, i2c_scl_t
);
parameter PORTABLE = 0;
input i2c_sda_o;
input i2c_sda_t;
output i2c_sda_i;
input i2c_scl_o;
input i2c_scl_t;
output i2c_scl_i;
inout i2c_sda;
inout i2c_scl;
generate
if(PORTABLE==1) begin
wire i2c_sda = i2c_sda_t ? 1'bz: i2c_sda_o;
wire i2c_sda_i = i2c_sda;
wire i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
wire i2c_scl_i = i2c_scl;
end
else
begin
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) i_sda (
.O(i2c_sda_i), // Buffer output
.IO(i2c_sda), // Buffer inout port (connect directly to top-level port)
.I(i2c_sda_o), // Buffer input
.T(i2c_sda_t) // 3-state enable input, high=input, low=output
);
IOBUF #(
.DRIVE(8),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) i_scl (
.O(i2c_scl_i),
.IO(i2c_scl),
.I(i2c_scl_o),
.T(i2c_scl_t)
);
end
endgenerate
endmodule // pi2c
|
#include <bits/stdc++.h> using namespace std; int a[100000], b[100000], n, i, x, y; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } sort(b, b + n); for (i = 0; i < n; i++) { if (a[i] != b[i]) { x = i; break; } } for (i = n - 1; i >= 0; i--) { if (a[i] != b[i]) { y = i; break; } } reverse(a + x, a + y + 1); for (i = 0; i < n; i++) { if (a[i] != b[i]) { cout << no ; return 0; } } cout << yes << endl << x + 1 << << y + 1; } |
#include <bits/stdc++.h> using namespace std; string s; long long int dp[510][501]; long long int solve(long long int l, long long int r) { if (dp[l][r] != -1) { return dp[l][r]; } if (l > r) return 0; long long int a = 1 + solve(l + 1, r); for (long long int i = l + 1; i <= r; i++) { if (s[i] != s[l]) continue; a = min(a, solve(l + 1, i - 1) + solve(i, r)); } dp[l][r] = a; return a; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, i; cin >> n; cin >> s; memset(dp, -1, sizeof dp); cout << solve(0, s.size() - 1); } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test caught a problem with the addition with different size
* operands was an operand of the shift.
*/
module main;
reg [3:0] a;
reg [4:0] result, b;
initial begin
a = 5;
b = 6;
result = (a + b) >> 1;
if (result !== 5) begin
$display("FAILED: result === %b", result);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "ge_1000baseX_mdio.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { , } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 22 "Reconcilliation Sublayer (RS) ////
//// Media Independent Interface (MII)"; see ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// and ////
//// doc/802.3-2008_section2.pdf, Clause/Section 36. ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "ge_1000baseX_constants.v"
`include "timescale.v"
module ge_1000baseX_mdio #(
parameter PHY_ADDR = 5'b00000
) (
// reset
input reset,
// clock
input mdc,
input mdio,
output mdio_out,
output mdio_oe,
output [4:0] data_addr,
input [15:0] data_rd,
output [15:0] data_wr,
output reg strobe_wr
);
`ifdef MODEL_TECH
enum logic [3:0] {
`else
localparam
`endif
S_PREAMBLE = 0,
S_ST = 1,
S_OP_CODE = 2,
S_PHY_ADDR = 3,
S_REG_ADDR = 4,
S_TA = 5,
S_WR_DATA = 6,
S_RD_DATA = 7,
S_WR_COMMIT = 8
`ifdef MODEL_TECH
} present, next;
`else
; reg [3:0] present, next;
`endif
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg [5:0] preamble_cnt;
assign preamble_match = (preamble_cnt == 31);
always @(posedge mdc or posedge reset)
if (reset)
preamble_cnt <= 0;
else
preamble_cnt <= (mdio & ~preamble_match) ? preamble_cnt + 1 :
(mdio & preamble_match) ? preamble_cnt : 0;
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg pos_cnt_inc; reg [4:0] pos_cnt;
always @(posedge mdc or posedge reset)
if (reset)
pos_cnt <= 0;
else
pos_cnt <= (pos_cnt_inc) ? pos_cnt + 1 : 0;
assign op_code_done = (pos_cnt == 1);
assign phy_addr_done = (pos_cnt == 6);
assign reg_addr_done = (pos_cnt == 11);
assign ta0_done = (pos_cnt == 12);
assign ta1_done = (pos_cnt == 13);
assign data_done = (pos_cnt == 29);
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg st; reg st_latch;
always @(posedge mdc or posedge reset)
if (reset)
st <= 0;
else
if (st_latch) st <= mdio;
assign st_match = ~st & mdio;
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg [1:0] op_code; reg op_code_shift;
always @(posedge mdc or posedge reset)
if (reset)
op_code <= 0;
else
if (op_code_shift) op_code <= { op_code[0], mdio};
assign op_is_rd = (op_code == 2'b10); assign op_is_wr = (op_code == 2'b01);
assign op_is_invalid = ~op_is_rd & ~op_is_wr;
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg [4:0] phy_addr; reg phy_addr_shift;
always @(posedge mdc or posedge reset)
if (reset)
phy_addr <= 0;
else
if (phy_addr_shift) phy_addr <= { phy_addr[3:0], mdio};
assign phy_addr_match = (phy_addr == PHY_ADDR);
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg [4:0] reg_addr; reg reg_addr_shift;
always @(posedge mdc or posedge reset)
if (reset)
reg_addr <= 0;
else
if (reg_addr_shift) reg_addr <= { reg_addr[3:0], mdio};
assign data_addr = reg_addr;
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg [15:0] data_in; reg data_in_shift;
always @(posedge mdc or posedge reset)
if (reset)
data_in <= 0;
else
if (data_in_shift) data_in <= { data_in[14:0], mdio};
assign data_wr = data_in;
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg [15:0] data_out; reg data_out_load, data_out_shift;
always @(posedge mdc or posedge reset)
if (reset)
data_out <= 0;
else
if (data_out_load) data_out <= data_rd;
else if (data_out_shift) data_out <= { data_out[14:0], 1'b0 };
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
assign mdio_oe = (ta1_done & op_is_rd) | data_out_shift;
assign mdio_out = (ta0_done & op_is_rd) ? 1'bz : ((ta1_done & op_is_rd) ? 1'b0 : data_out[15]);
//////////////////////////////////////////////////////////////////////////////
// mdio/mdc state machine registered part.
//////////////////////////////////////////////////////////////////////////////
always @(posedge mdc or posedge reset)
present <= (reset) ? S_PREAMBLE : next;
//////////////////////////////////////////////////////////////////////////////
// IEEE Std 802.3-2008 Clause 22 "Reconcilliation Sublayer (RS) and
// Media Independent Interface (MII)IEEE 802.3-2005 Clause 22
//////////////////////////////////////////////////////////////////////////////
always @*
begin
next = present;
pos_cnt_inc = 0; st_latch = 0;
op_code_shift = 0; phy_addr_shift = 0; reg_addr_shift = 0;
data_in_shift = 0; data_out_load = 0; data_out_shift = 0;
strobe_wr = 0;
case (present)
S_PREAMBLE:
begin
next = (preamble_match & ~mdio) ? S_ST : S_PREAMBLE;
end
S_ST:
begin
next = (mdio) ? S_OP_CODE: S_PREAMBLE;
end
S_OP_CODE:
begin
pos_cnt_inc = 1; op_code_shift = 1;
next = (op_code_done) ? S_PHY_ADDR : S_OP_CODE;
end
S_PHY_ADDR:
begin
pos_cnt_inc = 1; phy_addr_shift = 1;
next = (phy_addr_done) ? S_REG_ADDR : S_PHY_ADDR;
end
S_REG_ADDR:
begin
if (phy_addr_match) begin
pos_cnt_inc = 1; reg_addr_shift = 1;
next = (reg_addr_done) ? S_TA : S_REG_ADDR;
end
else
next = S_PREAMBLE;
end
S_TA:
begin
pos_cnt_inc = 1;
if (ta1_done) begin
data_out_load = op_is_rd;
next = (op_is_rd) ? S_RD_DATA :
(op_is_wr) ? S_WR_DATA : S_PREAMBLE;
end
end
S_WR_DATA:
begin
pos_cnt_inc = 1; data_in_shift = 1;
next = (data_done) ? S_WR_COMMIT : S_WR_DATA;
end
S_RD_DATA:
begin
pos_cnt_inc = 1; data_out_shift = 1;
next = (data_done) ? S_PREAMBLE : S_RD_DATA;
end
S_WR_COMMIT:
begin
strobe_wr = 1; next = S_PREAMBLE;
end
endcase
end
endmodule
|
module fifo(
clk,
reset,
wr_en,
rd_en,
wr_data,
rd_data,
not_full,
not_empty,
error
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 4;
localparam FIFO_SIZE = {1'b1, {(ADDR_WIDTH){1'b0}}};
input clk;
input reset;
input wr_en;
input rd_en;
input [DATA_WIDTH-1:0] wr_data;
output [DATA_WIDTH-1:0] rd_data;
output not_full;
output not_empty;
output error;
reg [DATA_WIDTH-1:0] queue[0:FIFO_SIZE-1];
reg [ADDR_WIDTH-1:0] rd_index;
reg [ADDR_WIDTH-1:0] wr_index;
reg [ADDR_WIDTH:0] count;
// Precompute several reused things
wire [ADDR_WIDTH-1:0] next_rd_index = rd_index + 1'b1;
wire [ADDR_WIDTH-1:0] next_wr_index = wr_index + 1'b1;
wire [ADDR_WIDTH:0] increase_count = count + 1'b1;
wire [ADDR_WIDTH:0] decrease_count = count - 1'b1;
`ifdef USE_SEQUENTIAL
reg rd_buffer;
reg not_empty_buffer;
reg not_full_buffer;
always @(posedge clk)
begin
rd_buffer <= queue[rd_index];
not_empty_buffer <= |count;
not_full_buffer <= ~count[ADDR_WIDTH];
end
assign not_full = not_full_buffer;
assign not_empty = not_empty_buffer;
assign rd_data = rd_buffer;
`else
assign not_full = ~count[ADDR_WIDTH];
assign not_empty = |count;
assign rd_data = queue[rd_index];
`endif
always @(posedge clk or posedge reset)
begin
if (reset)
begin
wr_index <= 1'b0;
rd_index <= 1'b0;
count <= 1'b0;
end
else if (rd_en & wr_en)
begin
// Read and write at the same time
queue[wr_index] <= wr_data;
rd_index <= next_rd_index;
wr_index <= next_wr_index;
end
else if (wr_en)
begin
// Only write
queue[wr_index] <= wr_data;
wr_index <= next_wr_index;
count <= increase_count;
end
else if (rd_en)
begin
// Only read
rd_index <= next_rd_index;
count <= decrease_count;
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* *** NOT FOR SYNTHESIS ***
*
* Random Packet Source for Open-Loop Measurement (see Dally/Towles p.450 and p.488)
*
* - The injection time appended to packets is independent of activity in the network.
*
* - The random packet injection process is not paused while a packet is written to the
* input FIFO (which may take a number of cycles). If a new packet is generated
* during this time it is copied to the FIFO as soon as possible.
*
*/
`timescale 1 ps/ 1 ps
`include "types.v"
`include "LAG_fifo_.v"
`include "LAG_route_.v"
`include "LAG_functions.v"
module LAG_random_traffic_source(flit_out, network_ready, clk, rst_n);
parameter nv = 4; // number of virtual-channels available on entry to network
parameter xdim = 4; // mesh network size
parameter ydim = 4;
parameter xpos = 0; // random source is connected to which router in mesh?
parameter ypos = 0;
parameter packet_length = 3;
parameter rate = 0.1234; // flit injection rate (flits/cycle/random source)
//
// set flit priority prior to injection
//
// 1. by flit id (e.g. head lowest priority, tail highest)
// 2. by journey length
// 3....
//
parameter priority_switch_alloc_byflitid = 0;
parameter priority_switch_alloc_byjourneylength = 0;
// add the following parameter to 'flit_priority' field, if packet is a single flit packet
parameter priority_singleflitpacketboost = 0;
parameter fixed_length = 1;
// if packetAB=1, a mixture of two packet lengths is generated
// packets of type A: length=packetA_length, probability = packetA_prob
// packets of type B: length=packetB_length, probability = 1-packetA_prob
parameter packetAB = 0;
parameter packetA_length = 1;
parameter packetA_prob = 0.67;
parameter packetB_length = 5;
parameter packetB_prob = (1-packetA_prob);
parameter packetAB_av_length = ((packetA_length*packetA_prob)+(packetB_length*packetB_prob));
parameter pAB = 10000*rate/packetAB_av_length;
parameter p = (packetAB) ? pAB : (10000*rate/packet_length);
parameter flit_count_width = 8; //clogb2(packet_length + 1);
parameter inject_count_width = 16;
// parameter p = 10000*rate/packet_length;
output flit_t flit_out;
input [nv-1:0] network_ready;
input clk, rst_n;
//==========
integer seed;
flit_t flit_out_;
logic [flit_count_width - 1:0] flit_count; //in test version we decide use 8 bit flit count
logic [inject_count_width - 1:0] inject_count;
logic [31:0] sys_time, i_time, i_time_tmp;
logic fifo_ready;
logic push, pop;
flit_t data_in, data_out, routed, d;
fifov_flags_t fifo_flags;
logic fifo_empty;
integer xdest, ydest;
integer injecting_packet;
integer flits_buffered, flits_sent;
integer length, len_sum, r;
integer current_pl, blocked;
logic [31:0] crc;
//
// FIFO connected to network input
//
LAG_fifo_v_ #(.size(2+packet_length*4))
source_fifo
(.push(push),
// dequeue if network was ready and fifo had a flit
.pop(!fifo_flags.empty && network_ready[current_pl]),
.data_in(data_in),
.data_out(data_out),
.flags(fifo_flags), .clk, .rst_n);
LAG_route_ rfn (.flit_in(data_out), .flit_out(routed), .clk, .rst_n);
always_comb
begin
if (data_out.control.head) begin
flit_out_ = routed;
end else begin
flit_out_ = data_out;
end
//flit_out_.control.valid = network_ready[current_pl] && !fifo_flags.empty;
end
always @(flit_out_) begin
flit_out.data <= #3000 flit_out_.data;
flit_out.control.head <= #3000 flit_out_.control.head;
flit_out.control.tail <= #3000 flit_out_.control.tail;
end
always @(fifo_flags.empty) begin
fifo_empty <= #3000 fifo_flags.empty;
end
always @(network_ready[current_pl] or fifo_empty) begin
flit_out.control.valid <= network_ready[current_pl] && !fifo_empty;
end
//
// Generate and Inject Packets at Random Intervals to Random Destinations
//
always@(posedge clk) begin
if (!rst_n) begin
i_time_tmp = 0;
current_pl=0;
flits_buffered=0;
flits_sent=0;
injecting_packet=0;
sys_time=0;
i_time=0;
inject_count=0;
flit_count=0;
fifo_ready=1;
push=0;
crc = '0;
end else begin
if (network_ready[current_pl]===1'bx) begin
$write ("Error: network_ready=%b", network_ready[current_pl]);
$finish;
end
if (!fifo_flags.empty && network_ready[current_pl]) flits_sent++;
if (push) flits_buffered++;
//
// start buffering next flit when there is room in FIFO
//
if ( ( flits_buffered - flits_sent ) <= packet_length ) begin
fifo_ready = 1;
end
if (fifo_ready) begin
while ((i_time!=sys_time)&&(injecting_packet==0)) begin
// **********************************************************
// Random Injection Process
// **********************************************************
// (1 and 10000 are possible random values)
if ($dist_uniform(seed, 1, 10000)<= p) begin
injecting_packet++;
end
i_time++;
end // while (!injecting_packet && (i_time!=sys_time))
end
if (injecting_packet && !fifo_ready) begin
assert (flit_count==0) else $fatal;
end
if (fifo_ready && injecting_packet) begin
// random source continues as we buffer flits in FIFO
if ($dist_uniform(seed, 1, 10000)<=p) begin
injecting_packet++;
end
i_time++;
flit_count++;
push<=1'b1;
//
// Send Head Flit
//
if (flit_count == 1) begin
d = '0;
crc = '0;
inject_count++;
i_time_tmp = i_time;
//
// set random displacement to random destination
//
xdest = $dist_uniform (seed, 0, xdim-1);
ydest = $dist_uniform (seed, 0, ydim-1);
while ((xpos==xdest)&&(ypos==ydest)) begin
// don't send to self...
xdest = $dist_uniform (seed, 0, xdim-1);
ydest = $dist_uniform (seed, 0, ydim-1);
end
d.data[router_radix + `X_ADDR_BITS : router_radix] = x_displ_t'(xdest-xpos);
d.data[router_radix + `X_ADDR_BITS + `Y_ADDR_BITS + 1 : router_radix + `X_ADDR_BITS + 1] = y_displ_t'(ydest-ypos);
d.control.head = 1'b1;
end else if(flit_count == 2) begin
d.control.head = 1'b0;
d.data[7:0] = flit_count;//flit number
d.data[15:8] = inject_count[7:0]; //low 8 bits of packet number
end else if(flit_count == 3) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = inject_count[15:8]; //high 8 bits of packet number
end else if(flit_count == 4) begin
d.data[7:0] = flit_count;//flit number
d.data[11:8] = xdest[3:0]; //x destination address
d.data[15:12] = ydest[3:0]; //y destination address
end else if(flit_count == 5) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = i_time_tmp[7:0]; //low 8 bits of ingection time
end else if(flit_count == 6) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = i_time_tmp[15:8];
end else if(flit_count == 7) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = i_time_tmp[23:16];
end else if(flit_count == 8) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = i_time_tmp[31:24];
end else if(flit_count == 9) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = crc[7:0];
end else if(flit_count == 10) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = crc[15:8];
end else if(flit_count == 11) begin
d.data[7:0] = flit_count;//flit number
d.data[15:8] = crc[23:16];
end else if(flit_count == 12) begin
//tail flit
d.data[7:0] = flit_count;//flit number
d.data[15:8] = crc[31:24];
d.control.tail = 1'b1;
injecting_packet--;
flit_count=0;
fifo_ready = 0;
/*$display($time, " ---------> Packet injected into fifo");
$display("Packet destined from x[%1d]y[%1d] to x[%1d]y[%1d]", xpos, ypos, xdest, ydest);
$display("****************************************************************************"); */
end
/*$display($time, " -----> Flit %1d is injected into fifo", flit_count);
$display("Flit destined from x[%1d]y[%1d] to x[%1d]y[%1d]", xpos, ypos, xdest, ydest);
$display("****************************************************************************"); */
if(flit_count < 9 && flit_count > 1) crc = crc32(d.data, crc);
end else begin // if (injecting_packet)
push <= 1'b0;
end
sys_time++;
data_in <= d;
end // else: !if(!rst_n)
end
initial begin
// we don't want any traffic sources to have the same
// random number seed!
seed = xpos*50+ypos;
len_sum=0;
r= $dist_uniform(seed, 1, 10000);
r= $dist_uniform(seed, 1, 10000);
if ((xpos==0)&&(ypos==0)) begin
if (packetAB) begin
$display ("-- Random Traffic Source with two packet lengths:");
$display ("-- Packet Length A = %1d, with probability %1.2f", packetA_length, packetA_prob);
$display ("-- Packet Length B = %1d, with probability %1.2f", packetB_length, packetB_prob);
end
end
end
endmodule // LAG_random_source
|
#include <bits/stdc++.h> using namespace std; int h[100010], res[100010]; int main() { int n, i; while (scanf( %d , &n) != EOF) { memset(h, 0, sizeof(h)); memset(res, 0, sizeof(res)); for (i = 1; i <= n; i++) { scanf( %d , &h[i]); } int temp = 0; for (i = 1; i <= n; i++) { temp = min(temp, h[i] - i); res[i] = i + temp; } temp = n + 1; for (i = n; i >= 1; i--) { temp = min(temp, h[i] + i); res[i] = min(res[i], temp - i); } int ans = 0; for (i = 1; i <= n; i++) { ans = max(ans, res[i]); } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> a; void printall(int x, int y, bool paren = false) { if (paren) printf( ( ); for (int i = x; i < y; i++) printf( %d-> , a[i]); printf( %d , a[y]); if (paren) printf( ) ); } int main() { scanf( %d , &n); a.resize(n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); if (a.back() != 0) { puts( NO ); } else { if (n == 1 or a[n - 2] == 1) { puts( YES ); printall(0, n - 1); } else { int i; for (i = n - 3; i >= 0; i--) if (a[i] == 0) break; if (i < 0) { puts( NO ); } else { puts( YES ); if (i - 1 >= 0) { printall(0, i - 1); printf( -> ); } printf( (0-> ); printall(i + 1, n - 2, true); printf( )->0 ); } } } } |
#include <bits/stdc++.h> using namespace std; int main() { set<char> deputi; vector<vector<char> > off; int m, n; char boss; cin >> n >> m >> boss; off.resize(n); for (int i = 0; i < n; i++) off[i].resize(m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) do { cin >> off[i][j]; } while (off[i][j] == n ); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (off[i][j] == boss) { if (i > 0) deputi.insert(off[i - 1][j]); if (i < n - 1) deputi.insert(off[i + 1][j]); if (j > 0) deputi.insert(off[i][j - 1]); if (j < m - 1) deputi.insert(off[i][j + 1]); } deputi.erase( . ); deputi.erase(boss); cout << deputi.size() << endl; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9361_tdd_if(
// clock
clk,
rst,
// control signals from the tdd control
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
// device interface
ad9361_txnrx,
ad9361_enable,
// interface status
ad9361_tdd_status
);
// parameters
parameter MODE_OF_ENABLE = 0;
localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1;
// clock
input clk;
input rst;
// control signals from the tdd control
input tdd_rx_vco_en;
input tdd_tx_vco_en;
input tdd_rx_rf_en;
input tdd_tx_rf_en;
// device interface
output ad9361_txnrx;
output ad9361_enable;
// interface status
output [ 7:0] ad9361_tdd_status;
// internal registers
reg tdd_rx_rf_en_d = 1'b0;
reg tdd_tx_rf_en_d = 1'b0;
reg tdd_vco_overlap = 1'b0;
reg tdd_rf_overlap = 1'b0;
wire ad9361_txnrx_s;
wire ad9361_enable_s;
// just one VCO can be enabled at a time
assign ad9361_txnrx_s = tdd_tx_vco_en & ~tdd_rx_vco_en;
always @(posedge clk) begin
tdd_rx_rf_en_d <= tdd_rx_rf_en;
tdd_tx_rf_en_d <= tdd_tx_rf_en;
end
assign ad9361_enable_s = (MODE_OF_ENABLE == PULSE_MODE) ?
((~tdd_rx_rf_en_d & tdd_rx_rf_en) | (tdd_rx_rf_en_d & ~tdd_rx_rf_en) |
(~tdd_tx_rf_en_d & tdd_tx_rf_en) | (tdd_tx_rf_en_d & ~tdd_tx_rf_en)) :
(tdd_rx_rf_en | tdd_tx_rf_en);
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_vco_overlap <= 1'b0;
tdd_rf_overlap <= 1'b0;
end else begin
tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
end
end
assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
assign ad9361_txnrx = ad9361_txnrx_s;
assign ad9361_enable = ad9361_enable_s;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> start_years; vector<long long> start_numbers; vector<long long> mods; void init() { long long start = 1989; start_years.resize(10); start_numbers.resize(10); mods.resize(10); start_years[0] = start; start_numbers[0] = 9; mods[0] = 10; long long p = 10; for (int i = 1; i < 10; ++i) { start_years[i] = start_years[i - 1] + p; p *= 10; start_numbers[i] = start_years[i] % p; mods[i] = p; } } long long solve(int i, long long num) { long long pos = num - start_numbers[i] + mods[i]; pos %= mods[i]; return start_years[i] + pos; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); init(); int n = 0; cin >> n; for (int i = 0; i < (n); ++i) { string str; cin >> str; int len = str.size() - 4; stringstream ss(str.substr(4, len)); long long num; ss >> num; cout << solve(len - 1, num) << endl; } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC TAG RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of data cache tag rams. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dc_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_DCTAG_W;
parameter aw = `OR1200_DCTAG;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_256x21 dc_tag0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_512x20 dc_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_1_V
`define SKY130_FD_SC_LS__A222OI_1_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a222oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a222oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a222oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_1_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int MOD = 1e6 + 3; const int N = 1e2 + 5; int n, wid, hei; long long f[N], phei[N]; struct matrix { long long a[N][N]; matrix() { memset(a, 0, sizeof(a)); } } base, cur; matrix operator*(matrix a, matrix b) { matrix ans; for (auto i = (0); i <= (wid); i++) for (auto j = (0); j <= (wid); j++) for (auto k = (0); k <= (wid); k++) ans.a[i][j] = (ans.a[i][j] + a.a[i][k] * b.a[k][j]) % MOD; return ans; } void prepare() { cin >> n >> wid >> hei; phei[0] = 1; for (auto i = (1); i <= (wid); i++) phei[i] = phei[i - 1] * hei % MOD; f[0] = 1; for (auto i = (1); i <= (wid); i++) for (int j = 1; j <= min(i, wid); j++) f[i] = (f[i] + f[i - j] * phei[j - 1]) % MOD; for (auto i = (1); i <= (wid); i++) base.a[i][i - 1] = 1; for (auto i = (0); i <= (wid); i++) base.a[i][wid] = phei[wid - i]; } long long solve() { n++; if (n <= wid) return f[n]; n -= wid; for (auto i = (0); i <= (wid); i++) cur.a[i][i] = 1; while (n) { if (n & 1) cur = cur * base; base = base * base; n >>= 1; } long long ans = 0; for (auto i = (0); i <= (wid); i++) ans = (ans + f[i] * cur.a[i][wid]) % MOD; return ans; } int main() { prepare(); cout << solve(); } |
#include <bits/stdc++.h> using namespace std; long long n, m, k; string s; int a[4][100]; vector<int> seq; vector<pair<int, int> > poseq; bool check() { for (int i = 0; i < n; i++) { if (a[1][i] != 0 || a[2][i] != 0) { return true; } } return false; } pair<int, int> next(pair<int, int> pos) { if (pos.first == 1) { if (pos.second != 0) { pos.second -= 1; } else { pos.first = 2; } } else { if (pos.second < n - 1) { pos.second += 1; } else { pos.first = 1; } } return pos; } void rotate() { int r, c; for (int i = 0; i < n; i++) { if (a[1][i] == 0) { r = 1; c = i; } if (a[2][i] == 0) { r = 2; c = i; } } pair<int, int> init = make_pair(r, c), prev = init, curr = next(init); while (init != curr) { if (a[curr.first][curr.second] != 0) { a[prev.first][prev.second] = a[curr.first][curr.second]; seq.push_back(a[curr.first][curr.second]); a[curr.first][curr.second] = 0; poseq.push_back(prev); } prev = curr; curr = next(prev); } } void park() { for (int i = 0; i < n; i++) { if (a[1][i] > 0 && a[1][i] == a[0][i]) { seq.push_back(a[1][i]); poseq.push_back(make_pair(0, i)); a[1][i] = 0; } if (a[2][i] > 0 && a[2][i] == a[3][i]) { seq.push_back(a[2][i]); poseq.push_back(make_pair(3, i)); a[2][i] = 0; } } } void run() { cin >> n >> k; for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { cin >> a[i][j]; } } if (k == 2 * n) { bool allfull = true; for (int i = 0; i < n; i++) { if (a[1][i] == a[0][i] || a[2][i] == a[3][i]) { allfull = false; break; } } if (allfull) { cout << setprecision(30) << -1 << endl; return; ; } } park(); while (check()) { rotate(); park(); } cout << setprecision(30) << seq.size() << endl; ; for (int i = 0; i < (int)seq.size(); i++) { cout << setprecision(30) << seq[i] << ; ; cout << setprecision(30) << poseq[i].first + 1 << ; ; cout << setprecision(30) << poseq[i].second + 1 << endl; ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int tests = 1; for (int i = 1; i <= tests; i++) run(); return 0; } |
module test;
reg fail = 1'b0;
reg [3:0] in = 4'b0;
wire [3:0] bus;
wire [3:0] val;
assign (pull1, pull0) bus = in;
assign val = bus;
initial begin
// Check the initial value.
#1 if (val !== 4'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", val);
fail = 1'b1;
end
// Check a bit force and verify a normal bit assign does nothing.
#1 force bus[0] = 1'b1;
#1 in[0] = 1'bz;
#1 if (val !== 4'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", val);
fail = 1'b1;
end
// Check a part force.
#1 force bus[3:2] = 2'b11;
#1 if (val !== 4'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", val);
fail = 1'b1;
end
// Check that we can change an unforced bit.
#1 in[1] = 1'bz;
#1 if (val !== 4'b11z1) begin
$display("FAILED: assignment of bus[1], got %b, expected 11z1.", val);
fail = 1'b1;
end
#1 in[1] = 1'b0;
// Check a bit release.
#1 release bus[0];
#1 if (val !== 4'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", val);
fail = 1'b1;
end
// Check a part release.
#1 release bus[3:2];
#1 if (val !== 4'b000z) begin
$display("FAILED: release of bus[3:2], got %b, expected 000z.", val);
fail = 1'b1;
end
// Check a force from the upper thread bits (>= 8).
#1 force bus[2:1] = 2'bx1;
#1 if (val !== 4'b0x1z) begin
$display("FAILED: force of bus[2:1], got %b, expected 0x1z.", val);
fail = 1'b1;
end
if (!fail) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; char c[n][n]; for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { cin >> c[i][j]; } } bool re = 1, ce = 1; for (long long i = 0; i < n; i++) { re = 1; for (long long j = 0; j < n; j++) { if (c[i][j] != E ) { re = 0; } } if (re == 1) { break; } } for (long long j = 0; j < n; j++) { ce = 1; for (long long i = 0; i < n; i++) { if (c[i][j] != E ) { ce = 0; } } if (ce == 1) { break; } } if (re == 1 && ce == 1) { cout << -1 ; return 0; } if (re == 1) { for (long long j = 0; j < n; j++) { for (long long i = 0; i < n; i++) { if (c[i][j] != E ) { cout << i + 1 << << j + 1 << n ; break; } } } } else { for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { if (c[i][j] != E ) { cout << i + 1 << << j + 1 << n ; break; } } } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; string t, s; cin >> n >> s; t = s; sort(s.begin(), s.end()); int ret = (1 << 21); for (int i = 0; i < s.length() + 1; i++) { int dif = 0; for (int i = 0; i < s.length(); i++) { if (t[i] != s[i]) dif++; } ret = min(ret, dif); rotate(s.begin(), s.begin() + 1, s.end()); } cout << ret / 2 << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_1_V
`define SKY130_FD_SC_HD__A211OI_1_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int dr8[] = {0, 0, 1, -1, 1, 1, -1, -1}; int dc8[] = {1, -1, 0, 0, -1, 1, -1, 1}; int dr4[] = {0, 1, -1, 0}; int dc4[] = {1, 0, 0, -1}; int n; int a[N]; set<pair<int, int> > s; set<int> end_idx; int sz[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i + 1]; } int c = 1; for (int i = 2; i <= n; i++) { if (a[i] != a[i - 1]) { s.insert({-c, i - 1}); end_idx.insert(i - 1); sz[i - 1] = c; c = 1; } else c++; } s.insert({-c, n}); end_idx.insert(n); sz[n] = c; int ans = 0; while (!s.empty()) { auto it = *s.begin(); s.erase(s.begin()); end_idx.erase(it.second); ans++; auto idx = end_idx.lower_bound(it.second); if (idx != end_idx.begin() && idx != end_idx.end()) { int rgt = *idx; idx--; int lft = *idx; if (a[lft] == a[rgt]) { s.erase(s.find({-sz[lft], lft})); s.erase(s.find({-sz[rgt], rgt})); end_idx.erase(lft); sz[rgt] += sz[lft]; s.insert({-sz[rgt], rgt}); } } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int getcom(pair<int, int> a, pair<int, int> b) { vector<int> all; all.push_back(a.first); all.push_back(a.second); all.push_back(b.first); all.push_back(b.second); sort(all.begin(), all.end()); int com = -1; for (int k = 1; k < 4; k++) { if (all[k] == all[k - 1]) { com = all[k]; } } return com; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; vector<pair<int, int> > a; vector<pair<int, int> > b; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; if (x > y) { swap(x, y); } a.push_back(make_pair(x, y)); } for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; if (x > y) { swap(x, y); } b.push_back(make_pair(x, y)); } vector<int> possible; bool theyknow = true; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i] == b[j]) { continue; } int com = getcom(a[i], b[j]); if (com == -1) { continue; } if (com != -1) { possible.push_back(com); } for (int k = 0; k < m; k++) { if (a[i] == b[k]) { continue; } int com2 = getcom(a[i], b[k]); if (com2 != -1 && com2 != com) { theyknow = false; } } for (int k = 0; k < n; k++) { if (a[k] == b[j]) { continue; } int com2 = getcom(a[k], b[j]); if (com2 != -1 && com2 != com) { theyknow = false; } } } } sort(possible.begin(), possible.end()); if (possible[0] == possible[possible.size() - 1]) { cout << possible[0] << endl; return 0; } if (theyknow) { cout << 0 << endl; } else { cout << -1 << endl; } } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int MOD = 1e9 + 7; const int MAXN = 1e6 + 3; struct Rcompare { bool operator()(pair<int, int> lhs, pair<int, int> rhs) { return lhs.first > rhs.first; } }; struct compare { bool operator()(pair<int, int> lhs, pair<int, int> rhs) { return lhs.first < rhs.first; } }; int solve(int x) { if (x < 4 || x == 5 || x == 7 || x == 11) { return -1; } if (x % 4 == 0) { return x / 4; } if (x % 4 == 2) { return x / 4; } if (x % 4 == 1) { return x / 4 - 1; } return x / 4 - 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; for (int i = 0; i < (n); ++i) { int x; cin >> x; cout << solve(x) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; int main() { int n, k, m, t, i, c[N]; scanf( %d%d , &n, &k); int ans = 0; while (k--) { scanf( %d , &m); for (i = 0; i < m; i++) { scanf( %d , &c[i]); } if (c[0] == 1) { for (i = 0; i < m; i++) { if (c[i] != i + 1) break; } ans += m - i; t = i; } else if (c[0] != 1) ans += m - 1; } ans += n - t; printf( %d n , ans); return 0; } |
// iverilog -y .. -o tb-DataPipe.vvp tb-DataPipe.v
// vvp tb-DataPipe.vvp
`timescale 1ns/1ns
module tb;
localparam W = 8;
localparam CYC = 10;
reg clk, rst;
reg idata_vld;
wire idata_rdy;
reg [W-1:0] idata;
wire odata_vld;
reg odata_rdy;
wire [W-1:0] odata;
DataPipe#(W) dut(clk, rst, idata_vld, idata_rdy, idata, odata_vld, odata_rdy, odata);
initial begin
#0;
rst = 1'b1;
#(10*CYC+CYC/3);
rst = 1'b0;
end
initial begin
#0;
clk = 1'b0;
#(CYC);
forever begin
clk = 1'b1;
#(CYC/2);
clk = 1'b0;
#(CYC-CYC/2);
end
end
task wait_reset_release;
begin
@(posedge clk);
while (rst) @(posedge clk);
end
endtask
event idata_update_event;
reg idata_update_ctrl;
initial begin :ivld
reg [31:0] rngseed, rnum;
integer n;
#0;
idata_vld = 1'b0;
wait_reset_release;
rngseed = 32'h01234567;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
idata_vld <= 1'b0;
idata_update_ctrl = 1'b0;
-> idata_update_event;
repeat (n) @(posedge clk);
end
idata_vld <= 1'b1;
idata_update_ctrl = 1'b1;
-> idata_update_event;
@(posedge clk);
while (~idata_rdy) @(posedge clk);
end
end
initial begin :idat
reg [31:0] rngseed, rnum;
#0;
idata = {W{1'b0}};
rngseed = 32'h23456789;
forever begin
@(idata_update_event);
if (idata_update_ctrl) begin
rnum = $random(rngseed);
idata <= rnum[W-1:0];
end else begin
idata <= {W{1'bx}};
end
end
end
initial begin :ordy
reg [31:0] rngseed, rnum;
integer n;
#0;
odata_rdy = 1'b0;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
odata_rdy <= 1'b0;
repeat (n) @(posedge clk);
end
odata_rdy <= 1'b1;
@(posedge clk);
end
end
initial begin
$dumpfile("tb-DataPipe.vcd");
$dumpvars(0, dut);
#(1000*CYC);
$display("Simulated 1000 cycles.");
$finish;
end
initial begin :verify_idata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (idata_vld & idata_rdy) begin
rnum = $random(rngseed);
if (idata !== rnum[W-1:0]) begin
$display("%0t: Error: idata %h != %h", $time, idata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, idata);
end
@(posedge clk);
end
end
initial begin :verify_odata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (odata_vld & odata_rdy) begin
rnum = $random(rngseed);
if (odata !== rnum[W-1:0]) begin
$display("%0t: Error: odata %h != %h", $time, odata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, odata);
end
@(posedge clk);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_SIO_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_SIO_PP_BLACKBOX_V
/**
* top_sio: Special I/O PAD that provides additionally a
* regulated output buffer and a differential input buffer.
* SIO cells are ONLY available IN pairs (see top_sio_macro).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_sio (
IN_H ,
PAD_A_NOESD_H,
PAD ,
DM ,
HLD_H_N ,
INP_DIS ,
IN ,
ENABLE_H ,
OE_N ,
SLOW ,
VTRIP_SEL ,
VINREF ,
VOUTREF ,
VREG_EN ,
IBUF_SEL ,
REFLEAK_BIAS ,
PAD_A_ESD_0_H,
TIE_LO_ESD ,
HLD_OVR ,
OUT ,
PAD_A_ESD_1_H,
VSSIO ,
VSSIO_Q ,
VSSD ,
VCCD ,
VDDIO ,
VCCHIB ,
VDDIO_Q
);
output IN_H ;
inout PAD_A_NOESD_H;
inout PAD ;
input [2:0] DM ;
input HLD_H_N ;
input INP_DIS ;
output IN ;
input ENABLE_H ;
input OE_N ;
input SLOW ;
input VTRIP_SEL ;
input VINREF ;
input VOUTREF ;
input VREG_EN ;
input IBUF_SEL ;
input REFLEAK_BIAS ;
inout PAD_A_ESD_0_H;
output TIE_LO_ESD ;
input HLD_OVR ;
input OUT ;
inout PAD_A_ESD_1_H;
inout VSSIO ;
inout VSSIO_Q ;
inout VSSD ;
inout VCCD ;
inout VDDIO ;
inout VCCHIB ;
inout VDDIO_Q ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_SIO_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
/**
* YL-3 Interface (http://www.dx.com/p/diy8-x-seven-segment-displays-module-for-arduino-595-driver-250813#.VoG5SPkrKHs)
* Modules based on diver_74hc595.v from Crazy_Bingo
* CLK = Clock from FPGA (50 MHz - Mojo V3)
* nRST = reset (inverted)
* DATA = 8x8 (64 bits of the array)
* LOAD = load the data
*
* READY = Ready for data to be loaded
* DIO = Serial Data
* SCK = Serial Clock
* RCK = Serial Latch
*/
module yl3_interface(
input CLK, // External Clock (50Mhz in my project)
input nRST, // Inverted Reset
input [63:0] DATA, // All 8 Characters (8 x 8 bits)
input LOAD, // Load the data in
output READY, // Ready for input to be loaded
output DIO, // Serial data output
output SCK, // Serial data clock
output RCK // Serial latch
);
localparam ST_READY = 2'b00; // Ready to load data
localparam ST_READCHR = 2'b01; // Read Character
localparam ST_SHIFT = 2'b10; // Shift Character
reg [7:0] chrarr [0:7]; // 8 Character array
reg [3:0] aidx; // Index of our array
reg [7:0] posreg; // Position on display
reg [7:0] chrreg; // Character in .GFEDBC inverse binary
reg [15:0] dataout; // Concatinated position and character data to output to YL-3
reg [3:0] delaycnt; // Clock divider
reg [4:0] bitcnt; // Counter / state-machine for which bit has been shifted
reg [2:0] lchcnt; // Counter for holding the latch high.
reg [1:0] state; // Our current state
reg loaded; // Data is loaded
reg EN;
reg ENA;
reg ENB;
wire RDY;
// Connect Dual SN74HC595 interface
YL3_Shift_Register ShiftReg(
.CLK(CLK),
.DATA_IN(dataout),
.EN_IN(EN),
.RDY(RDY),
.RCLK(RCK),
.SRCLK(SCK),
.SER_OUT(DIO)
);
// Load our data
always @(negedge RDY)
begin
ENA <= 0;
end
always @(posedge CLK)
begin
if(!nRST)
begin
state <= ST_READY;
chrarr[0] = 0;
chrarr[1] = 0;
chrarr[2] = 0;
chrarr[3] = 0;
chrarr[4] = 0;
chrarr[5] = 0;
chrarr[6] = 0;
chrarr[7] = 0;
aidx <= 4'b0;
posreg <= 8'b0;
chrreg <= 8'b0;
dataout <= 16'b1111_1111_1111_1111;
delaycnt <= 4'b0;
lchcnt <= 3'b0;
bitcnt <= 5'b0;
loaded <= 1'b0;
end
else
begin
if(state != ST_SHIFT)
begin
end
// Deal with the states
case(state)
ST_READY:
begin
// Read to Load data, so lets do so
if(LOAD == 1)
begin
//$display("ST_READY STATE - LOAD = 1");
if({chrarr[0], chrarr[1], chrarr[2], chrarr[3], chrarr[4], chrarr[5], chrarr[6], chrarr[7]} != DATA)
begin
//$display("NEEDS TO LOAD DATA");
chrarr[0] = DATA[63:56];
chrarr[1] = DATA[55:48];
chrarr[2] = DATA[47:40];
chrarr[3] = DATA[39:32];
chrarr[4] = DATA[31:24];
chrarr[5] = DATA[23:16];
chrarr[6] = DATA[15:8];
chrarr[7] = DATA[7:0];
end
else
begin
//$display("DATA: %h", data);
//$display("ARRY: %h", {chrarr[0], chrarr[1], chrarr[2], chrarr[3], chrarr[4], chrarr[5], chrarr[6], chrarr[7]});
//$display("DATA LOADED");
loaded <= 1'b1;
state <= ST_READCHR;
end
end
end
ST_READCHR:
begin
// Read the character from memory, convert it to 16 bit binary for position and 7-Segment leds.
//$display("DATAOUT: %b", dataout);
//$display("POSCHR : %b", {posreg, chrreg});
delaycnt <= 4'b0;
if({posreg, chrreg} != dataout)
begin
//$display("DATAOUT NEEDS TO BE CREATED!");
case (aidx)
0:
begin
posreg <= 8'b0000_0001;
end
1:
begin
posreg <= 8'b0000_0010;
end
2:
begin
posreg <= 8'b0000_0100;
end
3:
begin
posreg <= 8'b0000_1000;
end
4:
begin
posreg <= 8'b0001_0000;
end
5:
begin
posreg <= 8'b0010_0000;
end
6:
begin
posreg <= 8'b0100_0000;
end
7:
begin
posreg <= 8'b1000_0000;
end
default:
begin
//posreg <= 8'b0000_0001;
end
endcase
case (chrarr[aidx])
"0", "O":
begin
chrreg <= 8'b1100_0000;
end
"1":
begin
chrreg <= 8'b1111_1001;
end
"2":
begin
chrreg <= 8'b1010_0100;
end
"3":
begin
chrreg <= 8'b1011_0000;
end
"4":
begin
chrreg <= 8'b1001_1001;
end
"5", "S", "s":
begin
chrreg <= 8'b1001_0010;
end
"6":
begin
chrreg <= 8'b1000_0010;
end
"7":
begin
chrreg <= 8'b1111_1000;
end
"8":
begin
chrreg <= 8'b1000_0000;
end
"9":
begin
chrreg <= 8'b1001_1000;
end
"A":
begin
chrreg <= 8'b1000_1000;
end
"a":
begin
chrreg <= 8'b1010_0000;
end
"B", "b":
begin
chrreg <= 8'b1000_0011;
end
"C":
begin
chrreg <= 8'b1100_0110;
end
"c":
begin
chrreg <= 8'b1010_0111;
end
"D", "d":
begin
chrreg <= 8'b1010_0001;
end
"E":
begin
chrreg <= 8'b1000_0110;
end
"e":
begin
chrreg <= 8'b1000_0100;
end
"F", "f":
begin
chrreg <= 8'b1000_1110;
end
"G", "g":
begin
chrreg <= 8'b1001_0000;
end
"H":
begin
chrreg <= 8'b1000_1001;
end
"h":
begin
chrreg <= 8'b1000_1011;
end
"J":
begin
chrreg <= 8'b1111_0001;
end
"j":
begin
chrreg <= 8'b1111_0011;
end
"L":
begin
chrreg <= 8'b1100_0111;
end
"l":
begin
chrreg <= 8'b1110_0111;
end
"N", "n":
begin
chrreg <= 8'b1010_1011;
end
"o":
begin
chrreg <= 8'b1010_1011;
end
"P", "p":
begin
chrreg <= 8'b1000_1100;
end
"Q":
begin
chrreg <= 8'b0100_0000;
end
"q":
begin
chrreg <= 8'b0010_0011;
end
"R":
begin
chrreg <= 8'b1100_1110;
end
"r":
begin
chrreg <= 8'b1010_1111;
end
"T", "t":
begin
chrreg <= 8'b1000_0111;
end
"U":
begin
chrreg <= 8'b1100_0001;
end
"u":
begin
chrreg <= 8'b1110_0011;
end
"°":
begin
chrreg <= 8'b1001_1100;
end
".":
begin
chrreg <= 8'b0111_1111;
end
default:
begin
chrreg <= 8'b1111_1111;
end
endcase
dataout <= {posreg, chrreg};
end
else
begin
//$display("DATAOUT GOOD");
//$display("DATAOUT: %b", dataout);
aidx <= aidx + 1'b1;
state <= ST_SHIFT;
end
end
ST_SHIFT:
begin
if(RDY)
begin
if(aidx < 8)
begin
// Not done with our array (string), get next character
//$display("ST_LATCH -> ST_READCHR");
posreg <= 8'b0;
chrreg <= 8'b0;
dataout <= 16'b1;
state <= ST_READCHR;
end
else
begin
// We are done with our array (string) and let go back into ready mode.
//$display("ST_LATCH -> ST_READY");
loaded <= 1'b0;
state <= ST_READY;
end
end
end
endcase
end
end
always @(state)
begin
if(state == ST_SHIFT)
begin
if(RDY)
begin
ENB <= 1;
end
else
begin
ENB <= 0;
end
end
end
always @(*)
begin
EN <= (ENA || ENB);
end
// Assign the ready state output.
assign READY = (state == ST_READY && loaded == 0) ? 1'b1 : 1'b0;
endmodule |
//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module out_arbiter
(// --- data path interface
output [63:0] out_data,
output [7:0] out_ctrl,
output reg out_wr,
input out_rdy,
input [63:0] in_data0,
input in_wr0,
input in_req0,
output in_ack0,
input in_bop0,
input in_eop0,
output in_outrdy0,
input [63:0] in_data1,
input in_wr1,
input in_req1,
output in_ack1,
input in_bop1,
input in_eop1,
output in_outrdy1,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [1:0] reg_src_out,
// --- Misc
input clk,
input reset
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
reg [1:0] in_ack;
assign in_ack0 = in_ack[0];
assign in_ack1 = in_ack[1];
wire [1:0] in_req;
assign in_req[0] = in_req0;
assign in_req[1] = in_req1;
wire [1:0] in_wr;
assign in_wr[0] = in_wr0;
assign in_wr[1] = in_wr1;
wire [63:0] in_data[1:0];
assign in_data[0] = in_data0;
assign in_data[1] = in_data1;
wire [1:0] in_bop;
assign in_bop[0] = in_bop0;
assign in_bop[1] = in_bop1;
wire [1:0] in_eop;
assign in_eop[0] = in_eop0;
assign in_eop[1] = in_eop1;
//reg [1:0] in_outrdy;
//assign in_outrdy0 = in_outrdy[0];
//assign in_outrdy1 = in_outrdy[1];
assign in_outrdy0 = out_rdy;
assign in_outrdy1 = out_rdy;
reg curr_input;
reg curr_input_next;
wire curr_input_plus_1;
assign curr_input_plus_1 = (curr_input == 1) ? 0 : 1;
parameter OA_STATE_IDLE = 1'b0,
OA_STATE_TX = 1'b1;
reg oa_state;
reg oa_state_next;
always @(*) begin
in_ack = 0;
curr_input_next = curr_input;
oa_state_next = oa_state;
case(oa_state)
OA_STATE_IDLE: begin
if(in_req[curr_input]) begin
oa_state_next = OA_STATE_TX;
end else begin
curr_input_next = curr_input_plus_1;
end
end
OA_STATE_TX: begin
if(in_req[curr_input]) begin
in_ack[curr_input] = 1;
end else begin
oa_state_next = OA_STATE_IDLE;
curr_input_next = curr_input_plus_1;
end
end
default: begin
oa_state_next = OA_STATE_IDLE;
end
endcase
end
wire [63:0] fifo_in_data;
wire [7:0] fifo_in_ctrl;
wire [7:0] fifo_in_ctrl0;
wire [7:0] fifo_in_ctrl1;
wire fifo_prog_full;
wire fifo_empty;
wire fifo_wr;
wire fifo_rd;
always @(posedge clk) begin
if(reset) begin
oa_state <= 0;
curr_input <= 0;
end else begin
oa_state <= oa_state_next;
curr_input <= curr_input_next;
out_wr <= fifo_rd;
end
end
assign fifo_in_data = (curr_input == 0) ? in_data0 : in_data1;
assign fifo_in_ctrl0 = (in_bop0) ? 8'b11111111 : (in_eop0) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl1 = (in_bop1) ? 8'b11111111 : (in_eop1) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl = (curr_input == 0) ? fifo_in_ctrl0 : fifo_in_ctrl1;
assign fifo_wr = (curr_input == 0) ? in_wr0 : in_wr1;
assign fifo_rd = (fifo_empty == 1) ? 0 : out_rdy;
small_fifo_test input_fifo(
.data ({fifo_in_ctrl, fifo_in_data}), // Data in
.wrreq (fifo_wr), // Write enable
.rdreq (fifo_rd), // Read the next word
.q ({out_ctrl, out_data}),
.full (),
.empty (fifo_empty),
.sclr (reset),
.clock (clk),
.usedw ()
);
//assign out_wr = (out_rdy == 0) ? 0 : (fifo_empty == 1) ? 0 : 1;
/*
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_single cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[63:0] = out_data;
assign TRIG0[71:64] = out_ctrl;
assign TRIG0[80] = out_wr;
assign TRIG0[81] = out_rdy;
assign TRIG0[163:100] = in_data0;
assign TRIG0[170] = in_wr0;
assign TRIG0[171] = in_req0;
assign TRIG0[172] = in_ack0;
assign TRIG0[173] = in_bop0;
assign TRIG0[174] = in_eop0;
assign TRIG0[175] = in_outrdy0;
assign TRIG0[180] = oa_state;
assign TRIG0[181] = curr_input;
assign TRIG0[182] = fifo_empty;
assign TRIG0[183] = fifo_wr;
assign TRIG0[184] = fifo_rd;
assign TRIG0[207:200] = fifo_in_ctrl;
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_TB_V
`define SKY130_FD_SC_LP__INPUTISO1N_TB_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputiso1n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__inputiso1n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_TB_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Synthesized Netlist Wrapper
// This file is provided to wrap around the synthesized netlist (if appropriate)
// Interfaces:
// CLK.ACLK
// AXI4 Interconnect Clock Input
// RST.ARESETN
// AXI4 Interconnect Reset Input
// AXI_SLAVE_S_AXI
// AXI_SLAVE
// AXILite_SLAVE_S_AXI
// AXILite_SLAVE
// BRAM_PORTA
// BRAM_PORTA
// BRAM_PORTB
// BRAM_PORTB
module ram_16x8k_dp (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [1 : 0] wea;
input [12 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input enb;
input [1 : 0] web;
input [12 : 0] addrb;
input [15 : 0] dinb;
output [15 : 0] doutb;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXS = 100000; inline long long get(long long n, long long ma, long long b) { return max(ma, (6 * n + b - 1) / b) * b; } int main() { long long n, a, b; cin >> n >> a >> b; if (a * b >= 6 * n) { cout << a * b << endl; cout << a << << b << endl; } else { long long best = b; for (int i = b; i <= MAXS; i++) if (get(n, a, best) > get(n, a, i)) best = i; long long best2 = a; for (int i = a; i <= MAXS; i++) if (get(n, b, best2) > get(n, b, i)) best2 = i; if (get(n, a, best) < get(n, b, best2)) { a = max(a, (6 * n + best - 1) / best); b = best; } else { a = best2; b = max(b, (6 * n + best2 - 1) / best2); } cout << a * b << endl; cout << a << << b << endl; } } |
#include <bits/stdc++.h> using namespace std; long long N, M, K, ans; long long a[105][21005]; long long sum[105][21005]; long long tree[21005 * 8]; long long lazy[21005 * 8]; long long dp[21005 * 8]; void updLazy(long long x, long long l, long long r) { if (!lazy[x]) return; tree[x] += lazy[x]; lazy[2 * x + 1] += lazy[x]; lazy[2 * x + 2] += lazy[x]; lazy[x] = 0; } void upd(long long x, long long l, long long r, long long lq, long long rq, long long v, bool t) { if (r < l) return; updLazy(x, l, r); if (l > rq or r < lq) return; if (l >= lq && r <= rq) { if (t) tree[x] = lazy[x] = 0; lazy[x] += v; updLazy(x, l, r); return; } long long mid = (l + r) / 2; upd(2 * x + 1, l, mid, lq, rq, v, t); upd(2 * x + 2, mid + 1, r, lq, rq, v, t); tree[x] = max(tree[2 * x + 1], tree[2 * x + 2]); } long long suma2(long long i, long long j) { return sum[i][j + K - 1] - sum[i][j - 1] + sum[i + 1][j + K - 1] - sum[i + 1][j - 1]; } int main() { cin >> N >> M >> K; for (long long i = 1; i <= N; i++) for (long long j = 1; j <= M; j++) { cin >> a[i][j]; sum[i][j] = sum[i][j - 1] + a[i][j]; } for (long long i = 1; i <= N; i++) for (long long j = M + 1; j <= M; j++) sum[i][j] = sum[i][j - 1]; for (long long i = N; i >= 1; i--) { for (long long j = 1; j + K - 1 <= M; j++) { if (j <= K) upd(0, 1, M, j, j, dp[j] - sum[i + 1][K] + sum[i + 1][j - 1], 1); else upd(0, 1, M, j, j, dp[j], 1); } for (long long j = 1; j + K - 1 <= M; j++) { dp[j] = suma2(i, j) + tree[0]; ans = max(ans, dp[j]); upd(0, 1, M, max(1LL, j - K + 1), j, a[i + 1][j], 0); upd(0, 1, M, j + 1, min(M, j + K), -a[i + 1][j + K], 0); ans = max(ans, dp[j]); } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, temp; int first = -1, sec = -1; int ifirst = -1, isec = -1; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> temp; if (temp > first) { sec = first; isec = ifirst; first = temp; ifirst = i + 1; } else if (temp > sec) { sec = temp; isec = i + 1; } } cout << ifirst << << sec << endl; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_Mat2AXIkbM_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_Mat2AXIkbM (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Mat2AXIkbM_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_Mat2AXIkbM_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the Viterbi decoder
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "viterbidec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_viterbi_decoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the Viterbi decoder
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire data; // Output signal d
// Declare "reg" signals: inputs to the DUT
reg [1:0] encoded_input; // Input signal - cx
reg clock; // Input signal - clk
reg reset_sig; // Input signal - reset
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
data,encoded_input,clock,reset_sig);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=10,
#10
reset_sig = 1'd1;
encoded_input = 2'd0;
// @t=20,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=30,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=40,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=50,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=60,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=70,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=80,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=90,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=100,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=110,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=120,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=130,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=140,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=150,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=160,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=170,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=180,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=190,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=200,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=210,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=220,
#10
reset_sig = 0;
encoded_input = $random;
// @t=230,
#10
reset_sig = 0;
encoded_input = $random;
// @t=240,
#10
reset_sig = 0;
encoded_input = $random;
// @t=250,s
#10
reset_sig = 0;
encoded_input = $random;
// @t=260,
#10
reset_sig = 0;
encoded_input = $random;
// @t=270,
#10
reset_sig = 0;
encoded_input = $random;
// @t=280,
#10
reset_sig = 0;
encoded_input = $random;
// @t=290,
#10
reset_sig = 0;
encoded_input = $random;
// @t=300,
#10
reset_sig = 0;
encoded_input = $random;
// @t=310,
#10
reset_sig = 0;
encoded_input = $random;
// @t=320,
#10
reset_sig = 0;
encoded_input = $random;
// @t=330,
#10
reset_sig = 0;
encoded_input = $random;
// @t=340,
#10
reset_sig = 0;
encoded_input = $random;
// @t=350,
#10
reset_sig = 0;
encoded_input = $random;
// @t=360,
#10
reset_sig = 0;
encoded_input = $random;
// @t=370,
#10
reset_sig = 0;
encoded_input = $random;
// @t=380,
#10
reset_sig = 0;
encoded_input = $random;
// @t=390,
#10
reset_sig = 0;
encoded_input = $random;
// @t=400,
#10
reset_sig = 1;
encoded_input = $random;
// @t=410,
#10
reset_sig = 0;
encoded_input = $random;
// @t=420,
#10
reset_sig = 0;
encoded_input = $random;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 0x3f3f3f3f; const double PI = acos(-1.0); const double eps = 1e-10; const long long M = 1e9 + 7; const long long N = 1e5 + 5; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long a, b, c, s[5]; cin >> a >> b >> c; long long minx = INF; for (long long i = 1; i <= 11000; i++) { for (long long j = i; j <= 11000; j += i) { for (long long k = j; k <= 11000; k += j) { long long tmp = abs(a - i) + abs(b - j) + abs(c - k); if (tmp < minx) { minx = tmp; s[1] = i; s[2] = j; s[3] = k; } } } } cout << minx << endl; cout << s[1] << << s[2] << << s[3] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> v; int n, x, now; long long ans; char a[3]; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a; if (a[0] == a ) { cin >> x; v.insert(lower_bound(v.begin(), v.end(), x), x); } if (a[0] == d ) { cin >> x; v.erase(lower_bound(v.begin(), v.end(), x)); } if (a[0] == s ) { ans = 0; for (int i = 2; i < v.size(); i += 5) ans += v[i]; cout << ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, int> Map; int n, m, i, j; long long ans; string s; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> s; m = s.size(); bool cnt[30]; for (j = 0; j < 26; j++) cnt[j] = 0; for (j = 0; j < m; j++) cnt[s[j] - a ] ^= 1; int aux1 = 0; for (j = 0; j < 26; j++) { aux1 <<= 1; aux1 |= cnt[j]; } for (j = 0; j < 26; j++) ans += Map[aux1 ^ (1 << j)]; ans += Map[aux1]; Map[aux1]++; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; template <typename A> ostream &operator<<(ostream &cout, vector<A> const &v); template <typename A, typename B> ostream &operator<<(ostream &cout, pair<A, B> const &p) { return cout << ( << p.first << , << p.second << ) ; } template <typename A> ostream &operator<<(ostream &cout, vector<A> const &v) { cout << [ ; for (int i = 0; i < v.size(); i++) { if (i) cout << , ; cout << v[i]; } return cout << ] ; } template <typename A, typename B> istream &operator>>(istream &cin, pair<A, B> &p) { cin >> p.first; return cin >> p.second; } mt19937 rng(61378913); void usaco(string filename) { freopen((filename + .in ).c_str(), r , stdin); freopen((filename + .out ).c_str(), w , stdout); } const long double pi = 3.14159265358979323846; const long long mod = 1000000007; namespace modop { long long madd(long long a, long long b) { return (a + b) % mod; } long long msub(long long a, long long b) { return (((a - b) % mod) + mod) % mod; } long long mmul(long long a, long long b) { return ((a % mod) * (b % mod)) % mod; } long long mpow(long long base, long long exp) { long long res = 1; while (exp) { if (exp % 2 == 1) { res = (res * base) % mod; } exp >>= 1; base = (base * base) % mod; } return res; } long long minv(long long base) { return mpow(base, mod - 2); } long long mdiv(long long a, long long b) { return mmul(a, minv(b)); } } // namespace modop using namespace modop; long long n, m, k, q, l, r, x, y, z; long long a[1000005]; long long b[1000005]; long long c[1000005]; string second, t; long long ans = 0; map<long long, long long> cnt; pair<long long, long long> vals[1000005]; void solve(int tc) { cin >> n >> k; cnt.clear(); for (int ele = 0; ele < n; ele++) cin >> a[ele]; ; if (k == 1) { cout << (n & 1) << n ; return; } for (long long i = 0; i < (n); ++i) ++cnt[a[i]]; long long second = cnt.size(); int pos = 0; for (pair<long long, long long> x : cnt) vals[pos++] = x; reverse(vals, vals + second); long long req = 0, last = vals[0].first, ans = 0; bool fin = 0; for (long long i = 0; i < (second); ++i) { long long diff = last - vals[i].first; last = vals[i].first; for (long long j = 0; j < (diff); ++j) { if (req == 0) break; if (req > 1000000) { fin = 1; break; } req *= k; if (req > 1000000) { fin = 1; break; } } long long c = vals[i].second; if (fin) { ans = msub(ans, c * mpow(k, vals[i].first)); continue; } if (c <= req) { req -= c; ans = msub(ans, c * mpow(k, vals[i].first)); } else { c -= req; ans = 0; req = 0; if (c & 1) { req = 1; ans = (ans + mpow(k, vals[i].first)) % mod; } } } cout << (ans % mod) << n ; } int main() { { ios_base::sync_with_stdio(false); } { cin.tie(NULL); cout.tie(NULL); } int tc = 1; cin >> tc; for (int t = 0; t < tc; t++) solve(t); } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_async_edgelogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_async_edgelogic(/*AUTOARG*/
// Outputs
to_pad,
// Inputs
data
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
input data;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
output to_pad;
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
wire n0 = data;
assign to_pad = n0;
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int main() { int n, i, j, k, l, m; cin >> n; cin >> s; int cnt, ans; char c, c1, c2, c3; ans = 0; for (i = 0; i < n - 1; i++) { cnt = 0; if (s[i] == s[i + 1] && i < n - 1) { c = s[i]; while (s[i] == c) { i++; cnt++; } ans += (cnt / 2); if (i < n) c2 = s[i]; if (c2 == R && c == B ) c1 = G ; else if (c2 == R && c == G ) c1 = B ; else if (c2 == B && c == G ) c1 = R ; else if (c2 == B && c == R ) c1 = G ; else if (c2 == G && c == B ) c1 = R ; else if (c2 == G && c == R ) c1 = B ; if (i >= n) { if (c == R ) c1 = B ; else if (c == B ) c1 = G ; else c1 = R ; } for (j = i - cnt + 1; j < i; j += 2) s[j] = c1; i--; } } printf( %d n , ans); cout << s << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, d = 0; cin >> n >> a >> b; n = n - a; if (n <= b) { cout << n; } else { cout << b + 1; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, x, y; cin >> n >> x >> y; int dif = y - x; int minb = 1e9; for (int i = 1; i * i <= dif; ++i) { if (dif % i != 0) continue; if (dif / i + 1 <= n) { minb = min(minb, i); } if (i + 1 <= n) { minb = min(minb, dif / i); } } if (y - minb * (n - 1) > 0) { int res = y - minb * (n - 1); for (int i = 1; i <= n; ++i) { cout << res; if (i < n) cout << ; res += minb; } cout << endl; } else { int cnt = (y - 1) / minb; int res = y - cnt * minb; for (int i = 1; i <= n; ++i) { cout << res; if (i < n) cout << ; res += minb; } cout << endl; } } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_timer.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_timer -- Simple timer.
// _____________________________________________________________________________
//
`include "sys.h"
module jbi_timer (/*AUTOARG*/
// Outputs
busy, error,
// Inputs
start, stopnclear, tick, clk, rst_l
);
`include "jbi_mout.h"
input start; //
input stopnclear; //
output busy; //
output error; //
input tick; // Count timer by 1.
input clk; // Clock.
input rst_l; // Reset.
// Wires and Regs.
wire [1:0] state;
reg busy, error;
reg [1:0] next_state;
// States.
parameter UNUSED = 2'b00;
parameter COUNT_0 = 2'b01;
parameter COUNT_1 = 2'b10;
parameter OVERFLOW = 2'b11;
parameter STATE_x = 2'bxx;
// Machine State (initialize to IDLE).
dffrl_ns #(2) state_reg (.din(next_state), .q(state), .rst_l(rst_l), .clk(clk));
always @(/*AS*/start or state or stopnclear or tick) begin
`define out { next_state, error, busy }
casex ({ state, start, stopnclear, tick })
//
// stop ][
// Current n ][ Next
// State start clear tick ][ State error busy
// -----------------------------------++----------------------------------
// Counter not being used.
{ UNUSED, N, x, x }: `out = { UNUSED, N, N };
{ UNUSED, Y, x, x }: `out = { COUNT_0, N, N };
// Counter started. No counts yet.
{ COUNT_0, x, N, N }: `out = { COUNT_0, N, Y };
{ COUNT_0, x, Y, x }: `out = { UNUSED, N, Y };
{ COUNT_0, x, N, Y }: `out = { COUNT_1, N, Y };
// Counter started. Have seen one "tick".
{ COUNT_1, x, N, N }: `out = { COUNT_1, N, Y };
{ COUNT_1, x, Y, x }: `out = { UNUSED, N, Y };
{ COUNT_1, x, N, Y }: `out = { OVERFLOW, N, Y };
// Saw two "tick"s and have reported the overflow.
{ OVERFLOW, x, N, x }: `out = { OVERFLOW, Y, Y };
{ OVERFLOW, x, Y, x }: `out = { UNUSED, Y, Y };
default: `out = { STATE_x, x, x };
endcase
`undef out
end
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Check: 'Start' never asserted when in OVERFLOW state.
always @(posedge clk) begin
if (!(~rst_l) && state == OVERFLOW && start) begin
$dispmon ("jbi_mout_jbi_timer", 49, "%d %m: ERROR - JID reused before being released!", $time, state);
end
end
// Check: State machine has valid state.
always @(posedge clk) begin
if (!(~rst_l) && next_state === STATE_x) begin
$dispmon ("jbi_mout_jbi_timer", 49, "%d %m: ERROR - No state asserted! (state=%b)", $time, state);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-auto-read-includes:t
// verilog-module-parents:("jbi_ncrd_timeout")
// End:
|
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