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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_cplerr_lmi.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module drives the cpl_err/err_desc signalling from the application
// to the PCIe Hard IP via the LMI interface.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cplerr_lmi (
input clk_in,
input rstn,
input [127:0] err_desc, // TLP descriptor corresponding to cpl_err bits. Written to AER header log when cpl_err[6] is asserted.
input [6:0] cpl_err_in, // cpl_err bits from application. edge sensitive inputs.
input lmi_ack, // lmi read/write request acknowledge from core
output reg[31:0] lmi_din, // lmi write data to core
output reg[11:0] lmi_addr, // lmi address to core
output reg lmi_wren, // lmi write request to core
output reg [6:0] cpl_err_out, // cpl_err signal to core
output lmi_rden, // lmi read request to core
output reg cplerr_lmi_busy // 1'b1 means this module is busy writing cpl_err/err_desc to the core.
// transitions on cpl_err while this signal is high are ignored.
);
// cplerr_lmi_sm State Machine
localparam IDLE = 3'h0;
localparam WAIT_LMI_WR_AER81C = 3'h1;
localparam WAIT_LMI_WR_AER820 = 3'h2;
localparam WAIT_LMI_WR_AER824 = 3'h3;
localparam WAIT_LMI_WR_AER828 = 3'h4;
localparam DRIVE_CPL_ERR = 3'h5;
reg [2:0] cplerr_lmi_sm;
reg [6:0] cpl_err_reg;
reg [127:0] err_desc_reg;
reg lmi_ack_reg; // boundary register
assign lmi_rden = 1'b0; // not used
wire[6:0] cpl_err_in_assert;
assign cpl_err_in_assert = ~cpl_err_reg & cpl_err_in;
always @ (posedge clk_in or negedge rstn) begin
if (rstn==1'b0) begin
cplerr_lmi_sm <= IDLE;
cpl_err_reg <= 7'h0;
lmi_din <= 32'h0;
lmi_addr <= 12'h0;
lmi_wren <= 1'b0;
cpl_err_out <= 7'h0;
err_desc_reg <= 128'h0;
cplerr_lmi_busy <= 1'b0;
lmi_ack_reg <= 1'b0;
end
else begin
lmi_ack_reg <= lmi_ack;
// This State Machine controls LMI/cpl_err signalling to core.
// When cpl_err[6] asserts, the err_desc is written to the
// core's configuration space AER register via the LMI.
// And then cpl_err is driven to the core.
case (cplerr_lmi_sm)
IDLE: begin
lmi_addr <= 12'h81C;
lmi_din <= err_desc[127:96];
cpl_err_reg <= cpl_err_in;
err_desc_reg <= err_desc;
cpl_err_out <= 7'h0;
// level sensitive
if (cpl_err_in_assert[6]==1'b1) begin
// log header via LMI
// in 1DW accesses
cplerr_lmi_sm <= WAIT_LMI_WR_AER81C;
lmi_wren <= 1'b1;
cplerr_lmi_busy <= 1'b1;
end
else if (cpl_err_in_assert != 7'h0) begin
// cpl_err to core
// without logging header
cplerr_lmi_sm <= DRIVE_CPL_ERR;
lmi_wren <= 1'b0;
cplerr_lmi_busy <= 1'b1;
end
else begin
cplerr_lmi_sm <= cplerr_lmi_sm;
lmi_wren <= 1'b0;
cplerr_lmi_busy <= 1'b0;
end
end
WAIT_LMI_WR_AER81C: begin
// wait for core to accept last LMI write
// before writing 2nd DWord of err_desc
if (lmi_ack_reg==1'b1) begin
cplerr_lmi_sm <= WAIT_LMI_WR_AER820;
lmi_addr <= 12'h820;
lmi_din <= err_desc_reg[95:64];
lmi_wren <= 1'b1;
end
else begin
cplerr_lmi_sm <= cplerr_lmi_sm;
lmi_addr <= lmi_addr;
lmi_din <= lmi_din;
lmi_wren <= 1'b0;
end
end
WAIT_LMI_WR_AER820: begin
// wait for core to accept last LMI write
// before writing 3rd DWord of err_desc
if (lmi_ack_reg==1'b1) begin
cplerr_lmi_sm <= WAIT_LMI_WR_AER824;
lmi_addr <= 12'h824;
lmi_din <= err_desc_reg[63:32];
lmi_wren <= 1'b1;
end
else begin
cplerr_lmi_sm <= cplerr_lmi_sm;
lmi_addr <= lmi_addr;
lmi_din <= lmi_din;
lmi_wren <= 1'b0;
end
end
WAIT_LMI_WR_AER824: begin
// wait for core to accept last LMI write
// before writing 4th DWord of err_desc
if (lmi_ack_reg==1'b1) begin
cplerr_lmi_sm <= WAIT_LMI_WR_AER828;
lmi_addr <= 12'h828;
lmi_din <= err_desc_reg[31:0];
lmi_wren <= 1'b1;
end
else begin
cplerr_lmi_sm <= cplerr_lmi_sm;
lmi_addr <= lmi_addr;
lmi_din <= lmi_din;
lmi_wren <= 1'b0;
end
end
WAIT_LMI_WR_AER828: begin
// wait for core to accept last LMI write
// before driving cpl_err bits
lmi_addr <= lmi_addr;
lmi_din <= lmi_din;
lmi_wren <= 1'b0;
if (lmi_ack_reg==1'b1) begin
cplerr_lmi_sm <= DRIVE_CPL_ERR;
end
else begin
cplerr_lmi_sm <= cplerr_lmi_sm;
end
end
DRIVE_CPL_ERR: begin
// drive cpl_err bits to core
cpl_err_out <= cpl_err_reg;
cplerr_lmi_sm <= IDLE;
cplerr_lmi_busy <= 1'b0;
end
endcase
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; string a, b; bool ok(string s) { if (s == ) return false; if (s.length() == 1 && s[0] == 0 ) return true; if (s[0] == 0 ) return false; for (char c : s) { if (c < 0 || c > 9 ) return false; } return true; } void cal(string s) { if (ok(s)) a += s + , ; else b += s + , ; } void go(string &ret) { if (ret == ) ret = - ; else { ret = + ret; ret[ret.length() - 1] = ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); string s, t = ; cin >> s; for (char c : s) { if (c == , || c == ; ) { cal(t); t = ; } else { t += c; } } cal(t); go(a); go(b); cout << a << n << b; return 0; }
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#include <bits/stdc++.h> using namespace std; long long fast_pow(long long a, long long p) { long long res = 1; while (p) { if (p % 2 == 0) { a = a * 1LL * a % 1000000007; p /= 2; } else { res = res * 1LL * a % 1000000007; p--; } } return res; } long long fact(long long n) { long long res = 1; for (long long i = 1; i <= n; i++) { res = res * 1LL * i % 1000000007; } return res; } long long C(long long n, long long k) { return fact(n) * 1LL * fast_pow(fact(k), 1000000007 - 2) % 1000000007 * 1LL * fast_pow(fact(n - k), 1000000007 - 2) % 1000000007; } vector<long long> sieveOfEratosthenes(long long n) { vector<long long> primes; vector<bool> prime(n + 1, true); for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } for (long long p = 2; p <= n; p++) if (prime[p]) primes.push_back(p); return primes; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } bool isPerfectSquare(long double x) { if (x >= 0) { long long sr = sqrt(x); return (sr * sr == x); } return false; } long long sum(long long n) { long long res = 0; while (n > 0) { res += n % 10; n = n / 10; } return res; } vector<long long> adj[10001]; vector<long long> vis(10001); vector<long long> col(10001); void dfs(long long v) { vis[v] = 1; for (auto ch : adj[v]) { if (vis[ch] == 0) { dfs(ch); } } } bool bptdfs(long long v, long long c) { vis[v] = 1; col[v] = c; for (auto ch : adj[v]) { if (vis[ch] == 0) { if (bptdfs(ch, c ^ 1) == false) { return false; } } else { if (col[v] == col[ch]) { return false; } } } return true; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long t = 1; while (t--) { long long n, M; cin >> n >> M; vector<long long> t(n); for (long long i = (0); i <= (n - 1); i++) { cin >> t[i]; } vector<long long> ans(n, 0); for (long long i = (1); i <= (n - 1); i++) { long long c = 0, sum = 0; priority_queue<long long> q; for (long long j = (0); j <= (i); j++) { sum += t[j]; if (j != i) { q.push(t[j]); } } if (sum > M) { while (sum > M) { long long x = q.top(); q.pop(); sum -= x; c++; } } ans[i] = c; } for (auto x : ans) { cout << x << ; } cout << endl; } }
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#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int IT_MAX = 1 << 17; const long long MOD = 5000000; const int INF = 1034567891; const long long LL_INF = 1234567890123456789ll; const double PI = 3.141592653589793238; const double ERR = 1E-11; int in[200050]; int lr[200050][2]; int v[200050]; int main() { int N, T, K, i, j; scanf( %d %d %d , &N, &T, &K); for (i = 1; i <= T; i++) scanf( %d , &in[i]); in[0] = 1; for (i = 1; i < T; i++) { lr[i][1] = in[i] - 1; lr[i][0] = max(0, in[i] - in[i + 1]); } lr[T][0] = lr[T][1] = in[T]; int mn = 0, mx = 0; for (i = 1; i <= T; i++) mn += lr[i][0], mx += lr[i][1]; if (K < mn || mx < K) return !printf( -1 n ); int t = K - mn; for (i = 1; i <= T; i++) { int t2 = min(t, lr[i][1] - lr[i][0]); t -= t2; v[i] = in[i] - (lr[i][0] + t2); } v[0] = 1; printf( %d n , N); int pst = 1; for (i = 1; i <= T; i++) { int st = pst + in[i - 1]; for (j = 0; j < v[i - 1]; j++) printf( %d %d n , pst + j, st + j); for (j = v[i - 1]; j < in[i]; j++) printf( %d %d n , pst, st + j); pst = st; } return 0; }
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#include <bits/stdc++.h> using namespace std; int cnt[1000010] = {}; void pre() { for (int i = 1; i < 1000010; i++) { for (int j = i; j < 1000010; j += i) { cnt[j]++; } } } long long int tree[2 * 1000010]; int n; void build() { for (int i = n - 1; i > 0; i--) { tree[i] = tree[i << 1] + tree[(i << 1) | 1]; } } void update(int idx, long long int val) { tree[idx + n] = val; for (int i = idx + n; i > 0; i >>= 1) { tree[i >> 1] = tree[i] + tree[i ^ 1]; } } long long int query(int l, int r) { long long int ans = 0; l += n; r += n; for (; l < r; l >>= 1, r >>= 1) { if (l & 1) { ans += tree[l]; l++; } if (r & 1) { r--; ans += tree[r]; } } return ans; } int main() { pre(); int m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %lld , &tree[n + i]); } build(); set<int> s; for (int i = 0; i < n; i++) { if (tree[n + i] > 2) { s.insert(i); } } while (m--) { int t, l, r; scanf( %d %d %d , &t, &l, &r); l--; r--; if (t == 2) { printf( %lld n , query(l, r + 1)); } else { l--; vector<int> v; if (s.empty()) { continue; } if (s.upper_bound(l) == s.end()) { continue; } int idx = *s.upper_bound(l); while (idx <= r) { s.erase(idx); long long int x = tree[n + idx]; update(idx, (long long int)cnt[x]); if (cnt[x] > 2) { v.push_back(idx); } if (s.empty()) { break; } if (s.upper_bound(l) == s.end()) { break; } idx = *s.upper_bound(l); } for (int u : v) { s.insert(u); } } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; int n, m; vector<string> v(maxn); int func(int x, vector<vector<int>> &s) { vector<vector<int>> t(n + 3, vector<int>(m + 3, 0)); int i, j; for (i = 1; i <= n - 2 * x; i++) { for (j = 1; j <= m - 2 * x; j++) if (s[i + 2 * x][j + 2 * x] - s[i - 1][j + 2 * x] - s[i + 2 * x][j - 1] + s[i - 1][j - 1] == (2 * x + 1) * (2 * x + 1)) { t[i][j]++, t[i + 2 * x + 1][j + 2 * x + 1]++; t[i][j + 2 * x + 1]--, t[i + 2 * x + 1][j]--; } } for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { t[i][j] = t[i][j] + t[i - 1][j] + t[i][j - 1] - t[i - 1][j - 1]; if (v[i][j - 1] == X && t[i][j] <= 0) return 0; } return 1; } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int i, j; cin >> n >> m; vector<vector<int>> s(n + 2, vector<int>(m + 2, 0)); for (i = 1; i <= n; i++) { cin >> v[i]; for (j = 1; j <= m; j++) s[i][j] = s[i - 1][j] + s[i][j - 1] - s[i - 1][j - 1] + (v[i][j - 1] == X ); } int l = 0, r = n, mid; while (l < r) { mid = (l + r + 1) >> 1; if (func(mid, s)) l = mid; else r = mid - 1; } if (l == 0) { cout << 0 << n ; for (i = 1; i <= n; i++) cout << v[i] << n ; return 0; } cout << l << n ; vector<string> ans(n + 1, string(m, . )); for (i = 1; i <= n - 2 * l; i++) { for (j = 1; j <= m - 2 * l; j++) { if (s[i + 2 * l][j + 2 * l] - s[i - 1][j + 2 * l] - s[i + 2 * l][j - 1] + s[i - 1][j - 1] == (2 * l + 1) * (2 * l + 1)) ans[i + l][j + l - 1] = X ; } } for (i = 1; i <= n; i++) cout << ans[i] << n ; return 0; }
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// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_jumplogic(
ck,
reset_n,
cntr_value,
cntr_load,
reg_select,
reg_load_select,
jump_value,
jump_load,
jump_check,
jump_taken,
jump_address,
cntr_3,
jump_ptr_0_export,
jump_ptr_1_export,
jump_cntr_0_export,
jump_cntr_1_export
);
parameter DATA_WIDTH = 8;
input ck;
input reset_n;
input [DATA_WIDTH-1:0] cntr_value;
input cntr_load;
input [1:0] reg_select;
input [1:0] reg_load_select;
input [DATA_WIDTH-1:0] jump_value;
input jump_load;
input jump_check;
output jump_taken;
output [DATA_WIDTH-1:0] jump_address;
output [DATA_WIDTH-1:0] cntr_3;
output [7:0] jump_ptr_0_export;
output [7:0] jump_ptr_1_export;
output [7:0] jump_cntr_0_export;
output [7:0] jump_cntr_1_export;
reg [7:0] cntr [0:3];
reg [7:0] cntr_shadow [0:3];
reg [7:0] jump_pointers [0:3];
assign jump_ptr_0_export = jump_pointers [0];
assign jump_ptr_1_export = jump_pointers [1];
assign jump_cntr_0_export = cntr [0];
assign jump_cntr_1_export = cntr [1];
wire [3:0] comparisons;
assign jump_address = jump_pointers[reg_select];
assign jump_taken = (jump_check & ~comparisons[reg_select]);
assign cntr_3 = cntr[3];
genvar c;
generate
for(c = 0; c < 4; c = c + 1)
begin : jumpcounter
assign comparisons[c] = (cntr[c] == {DATA_WIDTH{1'b0}});
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
cntr[c] <= {DATA_WIDTH{1'b0}};
end
else if (cntr_load && reg_load_select == c) begin
cntr[c] <= cntr_value;
end
else if (jump_check && reg_select == c) begin
cntr[c] <= (comparisons[c]) ? cntr_shadow[c] : cntr[c] - 1'b1;
end
end
end
endgenerate
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
jump_pointers[0] <= {DATA_WIDTH{1'b0}};
jump_pointers[1] <= {DATA_WIDTH{1'b0}};
jump_pointers[2] <= {DATA_WIDTH{1'b0}};
jump_pointers[3] <= {DATA_WIDTH{1'b0}};
cntr_shadow[0] <= {DATA_WIDTH{1'b0}};
cntr_shadow[1] <= {DATA_WIDTH{1'b0}};
cntr_shadow[2] <= {DATA_WIDTH{1'b0}};
cntr_shadow[3] <= {DATA_WIDTH{1'b0}};
end
else begin
if(jump_load) begin
jump_pointers[0] <= (reg_load_select == 2'b00)? jump_value : jump_pointers[0];
jump_pointers[1] <= (reg_load_select == 2'b01)? jump_value : jump_pointers[1];
jump_pointers[2] <= (reg_load_select == 2'b10)? jump_value : jump_pointers[2];
jump_pointers[3] <= (reg_load_select == 2'b11)? jump_value : jump_pointers[3];
end
if(cntr_load) begin
cntr_shadow[0] <= (reg_load_select == 2'b00)? cntr_value : cntr_shadow[0];
cntr_shadow[1] <= (reg_load_select == 2'b01)? cntr_value : cntr_shadow[1];
cntr_shadow[2] <= (reg_load_select == 2'b10)? cntr_value : cntr_shadow[2];
cntr_shadow[3] <= (reg_load_select == 2'b11)? cntr_value : cntr_shadow[3];
end
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; string s, t; double ans; double solve(string s) { int a = 0, b = 0, c = 0, p = 0; for (int i = 0; i < s.size(); i++) { char e = (b % 2) ? R : L ; if (s[i] == X ) b++; else if (s[i] == e) a++, b++, p = 0; else a++, b += 2, c += p, p = !p; } if (b % 2) b++, c += p; if (a * 2 > b) a -= c, b -= 2 * c; return 100.0 * a / b; } int main() { cin >> t; for (int i = 0; i + 1 < t.size(); i++) { s += t[i]; if (t[i] == t[i + 1] && t[i] != X ) s += X ; } s += t.back(); if (s[0] == s.back() && s.back() != X ) ans = max(solve(s + X ), solve( X + s)); else ans = solve(s); int f = ans * 1000000; ans = f / 1000000.0; printf( %.6lf n , ans); return 0; }
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#include <bits/stdc++.h> #include <algorithm> using namespace std; #define int long long #define ll long long #define rep(i,a,b) for (int i = a; i < b; ++i) #define mod 1000000007 #define F first #define S second #define printer(v) for(auto f: v) cout<<f<< #define pb push_back #define mp make_pair #define all(c) c.begin(), c.end() #define ipair pair<int,int> #define tr(container, it) for(typeof(container.begin()) it = container.begin(); it != container.end(); it++) int bin_power(int x, unsigned int y){ // Modular Exponentiation (Power in Modular Arithmetic) int temp; if( y == 0) return 1; temp = bin_power(x, y / 2); if (y % 2 == 0) return (temp * temp)%mod; else return (x * temp * temp)%mod; // ll res = 1; // while(y){ // if(y & 1) res = (res * x)%mod; // y >>= 1; // x = (x * x)%mod; // } // return res; } int inverse_mod(int a){ return bin_power(a, mod-2); } vector<bool> isPrime_Seive_Of_Erastothenes(long n){ vector<bool> prime(n+1,true); prime[0] = prime[1] = false; for(long i=2;i*i<=n;i++){ if(prime[i]){ for(long j=i*i;j<=n;j+=i){ prime[j] = false; } } } return prime; } bool is_integer(float k){ return std::floor(k) == k; } int fact(int n); int nCr(int n, int r) { if(r > n - r) r = n - r; int ans = 1; int i; for(i = 1; i <= r; i++) { ans *= n - r + i; ans /= i; } return ans; } int fact(int n){ int res = 1; for (int i = 2; i <= n; i++){ res = res * i; res = res; } return res; } unsigned int gcd(unsigned int u, unsigned int v){ // Basic Euclidean Algorithm for GCD int shift; if (u == 0) return v; if (v == 0) return u; shift = __builtin_ctz(u | v); u >>= __builtin_ctz(u); do { v >>= __builtin_ctz(v); if (u > v) { unsigned int t = v; v = u; u = t; } v = v - u; } while (v != 0); return u << shift; } int gcdExtended(int a, int b, int *x, int *y){ // Extended Euclidean Algorithm if (a == 0){ *x = 0; *y = 1; return b; } int x1, y1; int gcd = gcdExtended(b%a, a, &x1, &y1); *x = y1 - (b/a) * x1; *y = x1; return gcd; } int binarySearch(int l, int r, int k){ if(l == r) return l; int mid = l + (r - l) / 2; cout<< ? << <<l+1<< <<mid+1<< n ; cout.flush(); int sum; cin>>sum; int x = mid - l + 1; if (x - sum >= k){ return binarySearch(l, mid, k); } else{ k -= (x - sum); return binarySearch(mid+1, r, k); } } bool isPrime(int n) { if (n <= 1) return false; if (n <= 3) return true; if (n%2 == 0 || n%3 == 0) return false; for (int i=5; i*i<=n; i=i+6) if (n%i == 0 || n%(i+2) == 0) return false; return true; } int nextPrime(int N) { if (N <= 1) return 2; int prime = N; bool found = false; while (!found) { prime++; if (isPrime(prime)) found = true; } return prime; } signed main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T; cin>>T; while(T--){ int n; cin>>n; vector<int> A(n); int ans = INT_MAX; int index = 0; for (int i = 0; i < n; ++i){ cin>>A[i]; if(A[i] < ans){ ans = A[i]; index = i; } } cout<<n - 1<<endl; for(int i = 0; i < index; i++){ A[i] = ans + abs(index - i); cout<<i + 1<< <<index + 1<< <<A[i]<< <<ans<<endl; } for(int i = index + 1; i < n; i++){ A[i] = ans + abs(index - i); cout<<i + 1<< <<index + 1<< <<A[i]<< <<ans<<endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int kN = 100 + 1; const int kA = 256; bool dp[kN][kN][kA]; bool used[kN][kN][kA]; vector<pair<int, int> > g[kN]; bool Dp(int u, int v, int mark) { if (!used[u][v][mark]) { used[u][v][mark] = true; dp[u][v][mark] = false; for (const auto& edge : g[u]) { if (edge.second < mark) { continue; } dp[u][v][mark] = dp[u][v][mark] || !Dp(v, edge.first, edge.second); } } return dp[u][v][mark]; } void Solve() { int n, m; cin >> n >> m; for (int i = 0; i < m; ++i) { int u, v; char ch; cin >> u >> v >> ch; g[u - 1].emplace_back(v - 1, int(ch)); } for (int u = 0; u < n; ++u) { for (int v = 0; v < n; ++v) { cout << (Dp(u, v, 0) ? A : B ); } cout << n ; } } int main() { std::ios_base::sync_with_stdio(false); cin.tie(NULL); int tests_count = 1; for (int test_index = 0; test_index < tests_count; ++test_index) { Solve(); } return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n", $time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
`ifdef ATTRIBUTES
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
`else
import "DPI-C" context function void mon_scope_name (input string formatted);
`endif
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
`ifdef ATTRIBUTES
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
`else
input int in;
output int fr_a;
output int fr_b;
`endif
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(this->name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\", &", in, ", false);");
$c("mon_register_a(\"fr_a\", &", fr_a, ", true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
//move some stuff to minitests/ncy0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
mux9_full # (.LOC("SLICE_X22Y240"))
c0 (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 16]));
endmodule
//Minimal MUX9 placement with actual LUTs
module mux9_full (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X22Y240";
wire lutho, lutgo, lutfo, luteo, lutdo, lutco, lutbo, lutao;
wire lut7do, lut7co, lut7bo, lut7ao;
wire lut8_bot_o, lut8_top_o;
wire lut9o;
assign dout[0] = lut9o;
(* LOC=LOC, BEL="F9MUX", KEEP, DONT_TOUCH *)
MUXF9 mux9 (.O(lut9o), .I0(lut8_top_o), .I1(lut8_bot_o), .S(din[6]));
(* LOC=LOC, BEL="F8MUX_TOP", KEEP, DONT_TOUCH *)
MUXF8 mux8top (.O(lut8_top_o), .I0(lut7do), .I1(lut7co), .S(din[6]));
(* LOC=LOC, BEL="F8MUX_BOT", KEEP, DONT_TOUCH *)
MUXF8 mux8bot (.O(lut8_bot_o), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7MUX_GH", KEEP, DONT_TOUCH *)
MUXF7 mux7d (.O(lut7do), .I0(lutho), .I1(lutgo), .S(din[6]));
(* LOC=LOC, BEL="F7MUX_EF", KEEP, DONT_TOUCH *)
MUXF7 mux7c (.O(lut7co), .I0(lutfo), .I1(luteo), .S(din[6]));
(* LOC=LOC, BEL="F7MUX_CD", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
(* LOC=LOC, BEL="F7MUX_AB", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
(* LOC=LOC, BEL="H6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) luth (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(lutho));
(* LOC=LOC, BEL="G6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutg (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(lutgo));
(* LOC=LOC, BEL="F6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutf (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(lutfo));
(* LOC=LOC, BEL="E6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) lute (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(luteo));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(lutdo));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(lutco));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(lutbo));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0000)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(),
.O6(lutao));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, x, rev; cin >> n; while (n % 10 == 0) n = n / 10; rev = 0; x = n; while (x > 0) { rev = rev * 10 + x % 10; x = x / 10; } if (rev == n) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; multiset<int> s; for (int v : a) s.insert(v); int ans = 0; for (int i = 0; i < n; ++i) { auto it = s.upper_bound(a[i]); if (it != s.end()) { ++ans; s.erase(it); } } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 16:47:01
// Design Name:
// Module Name: _32bit_adder_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _32bit_adder_tb(
);
reg [31:0] a;
reg [31:0] b;
reg cin;
wire cout;
wire [31:0] s;
integer i;
integer j;
_32bit_adder DUT (.a(a), .b(b), .cin(cin), .cout(cout), .s(s));
initial begin
#10000000 $finish;
end
initial begin
a = 0; b = 0; cin = 0;
for (i = 0 ; i < 500; i = i + 1) begin
#2 a = i;
#2
for (j = 0; j < 500; j = j + 1) begin
#2 b = j;
#3;
if ({cout, s} == (a + b + cin)) $display("Test Passed");
else $display("Test Failed: %b + %b + %b != %b%b", a, b, cin, cout, s);
end
end
#2 cin = 1;
#2
for (i = 0 ; i <500; i = i + 1) begin
#2 a = i;
#2
for (j = 0; j < 500; j = j + 1) begin
#2 b = j;
#3;
if ({cout, s} == (a + b + cin)) $display("Test Passed");
else $display("Test Failed: %b + %b + %b != %b%b", a, b, cin, cout, s);
end
end
#2 cin = 1;
#2
for (i = 200000 ; i <250000; i = i + 1) begin
#2 a = i;
#2
for (j = 0; j < 500; j = j + 1) begin
#2 b = j;
#3;
if ({cout, s} == (a + b + cin)) $display("Test Passed");
else $display("Test Failed: %b + %b + %b != %b%b", a, b, cin, cout, s);
end
end
#20;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_register_slice (
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_data
);
parameter DATA_WIDTH = 32;
parameter FORWARD_REGISTERED = 0;
parameter BACKWARD_REGISTERED = 0;
/*
s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data
s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid
s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
(1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
(2) BACKWARD_REGISTERED insters a FF before s_axi_ready
*/
wire [DATA_WIDTH-1:0] bwd_data_s;
wire bwd_valid_s;
wire bwd_ready_s;
wire [DATA_WIDTH-1:0] fwd_data_s;
wire fwd_valid_s;
wire fwd_ready_s;
generate if (FORWARD_REGISTERED == 1) begin
reg fwd_valid;
reg [DATA_WIDTH-1:0] fwd_data;
assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
fwd_valid <= 1'b0;
end
end
end else begin
assign fwd_data_s = bwd_data_s;
assign fwd_valid_s = bwd_valid_s;
assign fwd_ready_s = m_axi_ready;
end
endgenerate
generate if (BACKWARD_REGISTERED == 1) begin
reg bwd_ready;
reg [DATA_WIDTH-1:0] bwd_data;
assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (bwd_ready)
bwd_data <= s_axi_data;
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)
bwd_ready <= 1'b0;
end
end
end else begin
assign bwd_valid_s = s_axi_valid;
assign bwd_data_s = s_axi_data;
assign bwd_ready_s = fwd_ready_s;
end endgenerate
assign m_axi_data = fwd_data_s;
assign m_axi_valid = fwd_valid_s;
assign s_axi_ready = bwd_ready_s;
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef long double ld; typedef string str; #define pb push_back #define ppp pop_back #define pii pair<int,int> #define fi first #define se second #define stie std::tie #define vec vector #define forn(i, l, r) for (int i=l; i<=r; i++) #define forb(i, r, l) for (int i=r; i>=l; i--) #define emp empty #define beg begin #define ins insert #define cle clear #define era erase #define que queue #define pque priority_queue #define mset multiset #define deq deque #define sta stack #define con const #define rsz resize #define ass assign #define lowb lower_bound #define uppb upper_bound template<class T> void mini(T& a, T b) { a = min(a, b); } template<class T> void maxi(T& a, T b) { a = max(a, b); } template<class T1, class T2> ostream& operator<<(ostream &out, pair<T1, T2> a) { return out << a.first << << a.second; } template<class T> ostream& operator<<(ostream& out, vector<T> a) { for (auto& i : a) out << i << ; return out; } template<class T> ostream& operator<<(ostream& out, set<T> a) { for (auto& i : a) out << i << ; return out; } template<class T> ostream& operator<<(ostream& out, multiset<T> a) { for (auto& i : a) out << i << ; return out; } template<class T1, class T2> ostream& operator<<(ostream& out, map<T1, T2> a) { for (auto& i : a) out << i << n ; return out; } template<class T1, class T2> ostream& operator<<(ostream& out, unordered_map<T1, T2> a) { for (auto& i : a) out << i << n ; return out; } template<class T> ostream& operator<<(ostream& out, queue<T> a) { while (!a.empty()) { out << a.front() << ; a.pop(); } return out; } template<class T> ostream& operator<<(ostream& out, deque<T> a) { while (!a.empty()) { out << a.front() << ; a.pop_front(); } return out; } template<class T> ostream& operator<<(ostream& out, priority_queue<T> a) { while (!a.empty()) { out << a.top() << n ; a.pop(); } return out; } template<class T> void out(T a) { cout << a << endl; } template<class T1, class T2> void out(T1 a, T2 b) { cout << a << << b << endl; } template<class T1, class T2, class T3> void out(T1 a, T2 b, T3 c) { cout << a << << b << << c << endl; } template<class T1, class T2, class T3, class T4> void out(T1 a, T2 b, T3 c, T4 d) { cout << a << << b << << c << << d << endl; } template<class T> void out(vector<vector<T>> a) { for (vector<T> i : a) out(i); } template<class T> void out_(T a[], int l, int r) { for (int i = l; i <= r; i++) cout << a[i] << ; cout << endl; } void out() { cout << OK << endl; } template<class T> void sort(vector<T>& a) { sort(a.begin(), a.end()); } template<class T> void uniq(vector<T>& a) { sort(a); a.erase(unique(a.begin(), a.end()), a.end()); } template<class T> vector<T> set_int(vector<T> a, vector<T> b) { sort(a); sort(b); vector<T> res; set_intersection(a.begin(), a.end(), b.begin(), b.end(), back_inserter(res)); return res; } clock_t start_time; void start_timer() { start_time = clock(); } double get_time() { return (double)(clock() - start_time) / CLOCKS_PER_SEC; } #if __SIZEOF_INT128__ >= 16 typedef __int128 LL; istream& operator>>(istream& in, __int128& a) { int64_t b; cin >> b; a = b; return in; } ostream& operator<<(ostream& out, const __int128 a) { unsigned __int128 b = a < 0 ? -a : a; char buf[128]; char* c = end(buf); do { --c; *c = 0123456789 [b % 10]; b /= 10; } while (b); if (a < 0) { --c; *c = - ; } int len = end(buf) - c; out.rdbuf()->sputn(c, len); return out; } #endif con int N = 1e5 + 5; con int K = 25; int a[N]; vec<int> g[N]; int dp[N][2 * K]; bool ans[N]; int k; void dfs(int v = 1, int p = 0) { dp[v][0] = a[v]; for (int u : g[v]) { if (u == p) continue; dfs(u, v); forn(i, 1, k-1) { dp[v][i] ^= dp[u][i-1]; } dp[v][0] ^= dp[u][k-1]; } } void dfs2(int v = 1, int p = 0, vec<int> cur = vec<int>(2 * K, 0)) { forn(i, 0, k-1) { cur[i] ^= dp[v][i]; } int odd = 0; forn(i, k/2, k-1) { odd ^= cur[i]; } ans[v] = odd; for (int u : g[v]) { if (u == p) continue; vec<int> nxt = cur; forn(i, 1, k-1) { nxt[i] ^= dp[u][i-1]; } nxt[0] ^= dp[u][k-1]; int last = nxt[k-1]; forb(i, k-1, 1) { nxt[i] = nxt[i-1]; } nxt[0] = last; dfs2(u, v, nxt); } } void Solve() { int n; cin >> n >> k; k *= 2; forn(i, 1, n-1) { int u, v; cin >> u >> v; g[u].pb(v); g[v].pb(u); } forn(i, 1, n) cin >> a[i]; dfs(); dfs2(); forn(i, 1, n) { cout << ans[i] << ; } cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); #ifdef LOCAL freopen( input.txt , r , stdin); #endif start_timer(); Solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxlongint = 2147483647; const int P1 = 19260817, P2 = 1000000007, N = 100011, M = 1000011; long long mi1[M], mi2[M], ni1[M], ni2[M], s1[M], s2[M]; char st[M], Ans[M]; long long powder(int x, int a, const int& P) { if (!a) return 1; long long tot = powder(x, a >> 1, P); tot = (tot * tot) % P; if (a & 1) tot = (tot * x) % P; return tot; } inline long long num(char ch) { return ( 0 <= ch && ch <= 9 ) ? (ch - 0 ) : (( a <= ch && ch <= z ) ? (ch - a + 10) : (ch - A + 36)); } void pre(int n) { long long c = 62, nn1 = powder(c, P1 - 2, P1), nn2 = powder(c, P2 - 2, P2); if (nn1 * 62 % P1 != 1 || nn2 * 62 % P2 != 1) printf( Sfsf n ); mi1[0] = 1; for (int i = 1; i <= n; i++) { mi1[i] = (mi1[i - 1] * c) % P1; if (mi1[i] < 0) while (1) mi1[-154151564]; } mi2[0] = 1; for (int i = 1; i <= n; i++) { mi2[i] = (mi2[i - 1] * c) % P2; if (mi2[i] < 0) while (1) mi2[-134564522]; } ni1[0] = 1; for (int i = 1; i <= n; i++) ni1[i] = ni1[i - 1] * nn1 % P1; ni2[0] = 1; for (int i = 1; i <= n; i++) ni2[i] = ni2[i - 1] * nn2 % P2; } int main() { pre(1000000); int n; scanf( %d , &n); int totlen = 0; for (int i = 1; i <= n; i++) { scanf( %s , st + 1); int l = strlen(st + 1); int pos = 0; long long c = 62; long long sh1 = 0, sh2 = 0; for (int j = 1; j <= l && j <= totlen; j++) { sh1 = (sh1 * c + num(st[j])) % P1; sh2 = (sh2 * c + num(st[j])) % P2; if (sh1 < 0 || sh2 < 0) while (1) putchar( n ); if ((s1[totlen] - s1[totlen - j] * mi1[j] % P1 + P1) % P1 == sh1 && (s2[totlen] - s2[totlen - j] * mi2[j] % P2 + P2) % P2 == sh2) pos = j; } for (int j = pos + 1; j <= l; j++) { Ans[++totlen] = st[j]; s1[totlen] = (s1[totlen - 1] * c + num(Ans[totlen])) % P1; s2[totlen] = (s2[totlen - 1] * c + num(Ans[totlen])) % P2; if (s1[totlen] * c < 0 || s2[totlen] * c < 0) while (1) putchar( n ); } } for (int i = 1; i <= totlen; i++) putchar(Ans[i]); fclose(stdin); fclose(stdout); return 0; }
|
#include <bits/stdc++.h> using namespace std; void fast() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { int n, c = 0; char x; vector<pair<int, int> > v; cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> x; if (x == C ) { v.push_back(make_pair(i, j)); } } } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) { for (int j = i + 1; j < v.size(); j++) { if (v[i].first == v[j].first) c++; if (v[i].second == v[j].second) c++; } } cout << c; return 0; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Fri May 9 13:48:22 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_182/clk_182_funcsim.v
// Design : clk_182
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_182,clk_wiz_v5_1,{component_name=clk_182,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_182
(clk_200MHz,
clk_182MHz,
locked);
input clk_200MHz;
output clk_182MHz;
output locked;
wire clk_182MHz;
(* IBUF_LOW_PWR *) wire clk_200MHz;
wire locked;
clk_182clk_182_clk_wiz U0
(.clk_182MHz(clk_182MHz),
.clk_200MHz(clk_200MHz),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_182_clk_wiz" *)
module clk_182clk_182_clk_wiz
(clk_200MHz,
clk_182MHz,
locked);
input clk_200MHz;
output clk_182MHz;
output locked;
wire clk_182MHz;
wire clk_182MHz_clk_182;
(* IBUF_LOW_PWR *) wire clk_200MHz;
wire clk_200MHz_clk_182;
wire clkfbout_buf_clk_182;
wire clkfbout_clk_182;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_182),
.O(clkfbout_buf_clk_182));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_200MHz),
.O(clk_200MHz_clk_182));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_182MHz_clk_182),
.O(clk_182MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(9.125000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(5.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_182),
.CLKFBOUT(clkfbout_clk_182),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_200MHz_clk_182),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_182MHz_clk_182),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// file: main_pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____75.000______0.000______50.0______466.667_____50.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "main_pll,main_pll,{component_name=main_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module main_pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (15),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.15 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.12 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.11 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.10 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.8 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban ()
// Company: Flextronics Semiconductor
//
`include "uart_defines.v"
module uart_wb (clk, wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [2:0] wb_adr_i; //WISHBONE address line
input [7:0] wb_dat_i; //input WISHBONE bus
output [7:0] wb_dat_o;
reg [7:0] wb_dat_o;
wire [7:0] wb_dat_i;
reg [7:0] wb_dat_is;
output [2:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [2:0] wb_adr_int; // internal signal for address bus
reg [2:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
wire [3:0] wb_sel_i;
reg wre ;// timing control signal for write or read enable
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= 1'b0;
wbstate <= 0;
wre <= 1'b1;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= 0;
wbstate <= 1;
wb_ack_o <= 1;
end else begin
wre <= 1;
wb_ack_o <= 0;
end
end
1: begin
wb_ack_o <= 0;
wbstate <= 2;
wre <= 0;
end
2: begin
wb_ack_o <= 0;
wbstate <= 3;
wre <= 0;
end
3: begin
wb_ack_o <= 0;
wbstate <= 0;
wre <= 1;
end
endcase
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= 0;
wb_we_is <= 0;
wb_cyc_is <= 0;
wb_stb_is <= 0;
wb_dat_is <= 0;
end else begin
wb_adr_is <= wb_adr_i;
wb_we_is <= wb_we_i;
wb_cyc_is <= wb_cyc_i;
wb_stb_is <= wb_stb_i;
wb_dat_is <= wb_dat_i;
end
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= 0;
else
wb_dat_o <= wb_dat8_o;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
assign wb_adr_int = wb_adr_is;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_2_V
`define SKY130_FD_SC_LP__NOR3B_2_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_2 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_2 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int L[n]; for (int i = 0; i < n; ++i) scanf( %d , &L[i]); int imos[n + 1]; fill(imos, imos + n + 1, 0); for (int i = 0; i < n; ++i) { L[i] = min(L[i], i); ++imos[i - L[i]]; --imos[i]; } int t = 0, ans = n; for (int i = 0; i <= n; ++i) { t += imos[i]; if (t > 0) --ans; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool tu[305][305]; long long pri[305]; int d[305]; int n, m, t; int bg[1100000]; int top[110000]; int main() { scanf( %d%d%d , &n, &m, &t); for (int i = 1; i <= n; i++) scanf( %I64d , &pri[i]); for (int i = 1; i <= m; i++) { int b, c; scanf( %d%d , &b, &c); tu[b][c] = 1; d[c]++; } for (int kk = 1; kk <= n; kk++) { int now = 0; for (int i = 1; i <= n; i++) if (d[i] == 0) now = i; if (!now) { printf( 0 n ); return 0; } d[now] = -1; for (int i = 1; i <= n; i++) if (tu[now][i]) d[i]--; top[++top[0]] = now; } for (int i = 1; i <= top[0]; i++) { int x = top[i]; for (int j = 1; j <= n; j++) { if (tu[x][j]) pri[j] += pri[x], t -= pri[x]; if (t < 0) { printf( 0 n ); return 0; } } } if (t < 0) { printf( 0 n ); return 0; } bg[0] = 1; for (int i = 1; i <= n; i++) for (long long j = pri[i]; j <= t; j++) bg[j] = (bg[j] + bg[j - pri[i]]) % 1000000007; printf( %d n , t >= 0 ? bg[t] : 0); return 0; }
|
#include <bits/stdc++.h> inline int two(int n) { return 1 << n; } inline int test(int n, int b) { return (n >> b) & 1; } inline void set_bit(int& n, int b) { n |= two(b); } inline void unset_bit(int& n, int b) { n &= ~two(b); } inline int last_bit(int n) { return n & (-n); } inline int ones(int n) { int res = 0; while (n && ++res) n -= n & (-n); return res; } long long int gcd(long long int a, long long int b) { return (a ? gcd(b % a, a) : b); } long long int modPow(long long int a, long long int b, long long int MOD) { long long int x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = (x * y) % MOD; } b /= 2; y = (y * y) % MOD; } return x; } long long int modInverse(long long int a, long long int p) { return modPow(a, p - 2, p); } using namespace std; const int N = 1e3 + 3; int arr[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, i, j, l, r, taiyar, submit, ans, m; ans = 0; taiyar = 0; submit = 0; cin >> n; for (int i = 0; i < (n); i++) { cin >> arr[i]; taiyar += arr[i]; } cin >> m; while (m--) { cin >> l >> r; if (taiyar <= r) { cout << max(taiyar, l); return 0; } } cout << -1 ; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class TH> void _dbg(const char *sdbg, TH h) { cout << sdbg << = << h << endl; } template <class TH, class... TA> void _dbg(const char *sdbg, TH h, TA... a) { while (*sdbg != , ) cout << *sdbg++; cout << = << h << , ; _dbg(sdbg + 1, a...); } const long long mod = 1e9 + 7; const long long M = 1e6 + 5; const double pi = acos(-1.); const long long dx[] = {1, 0, -1, 0, -1, -1, 1, 1}; const long long dy[] = {0, 1, 0, -1, 1, -1, 1, -1}; long long x, y, z, maxi, mini, ans, mid, low, high, m, n, a, b; string s1, s2; bool check(long long p) { p = abs(p); while (p) { int k = p % 10; if (k == 8) return true; p /= 10; } return false; } void solve() { cin >> n; x = n; x++; while (!check(x)) x++; cout << abs(x - n); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int fastExpo(long long int a, long long int n, long long int mod) { long long int result = 1; while (n > 0) { if (n & 1) result = (result * a) % mod; a = (a * a) % mod; n >>= 1; } return result; } long long int modInverse(long long int n, long long int mod) { return fastExpo(n, mod - 2, mod); } vector<long long int> factorial(long long int n) { std::vector<long long int> fac(n + 2, 0); fac[0] = 1; for (long long int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % 1000000007; return fac; } long long int __nCr(long long int n, long long int r, vector<long long int>& Fact, long long int mod) { long long int ans = (((Fact[n] * modInverse(Fact[r], mod)) % mod) * modInverse(Fact[n - r], mod)) % mod; return ans; } void runcases(long long int T) { string s, p; cin >> s >> p; s = p + # + s; long long int n = s.size(); long long int m = p.size(); long long int count = 0; vector<long long int> lps(n, 0); long long int j = 0; for (long long int i = 1; i < n; i++) { j = lps[i - 1]; while (j > 0 && s[i] != s[j]) { j = lps[j - 1]; } if (s[i] == s[j]) { j++; } lps[i] = j; if (lps[i] == m) { s[i] = * ; count++; lps[i] = 0; } } cout << count << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int T = 1; for (long long int t = 1; t <= T; t++) { runcases(t); } return 0; }
|
module RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
wire [31:0] Q[15:0];
//Rd
wire [15:0] DecoderRd; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRd(.IN(RSLCT[15:12]),.OUT(DecoderRd)); //Decoder assembly
//Rn_CU
wire [3:0] _RN_CU;
//Multiplexer(input [31:0] IN1,IN2,input IR_CU,output [31:0] OUT);
Multiplexer mux(RSLCT[19:16],RSLCT[3:0],IR_CU,_RN_CU);
wire [15:0] DecoderRn_CU; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRn_CU(.IN(_RN_CU),.OUT(DecoderRn_CU));//Decoder assembly
//Rm
wire [15:0] DecoderRm; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRm(.IN(RSLCT[7:4]),.OUT(DecoderRm));//Decoder assembly
//Rs
wire [15:0] DecoderRs; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRs(.IN(RSLCT[11:8]),.OUT(DecoderRs));//Decoder assembly
wire [31:0] _pcin;
Buffer32_32 pcbufffer1(.IN(Pcin),.Store(LOADPC&!(DecoderRd[15]&LOAD)),.OUT(_pcin));
Buffer32_32 pcbufffer2(.IN(in),.Store((DecoderRd[15]&LOAD)),.OUT(_pcin));
generate
genvar i;
for (i=0; i<=15; i=i+1) begin : registers
if(i<15)
//Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register test_reg(.IN(in),
.Clk(Clk),
.Reset(RESET),
.Load(DecoderRd[i]&LOAD),
.OUT(Q[i]));
else
begin
//Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register test_reg(.IN(_pcin),
.Clk(Clk),
.Reset(RESET),
.Load((DecoderRd[i]&LOAD)||LOADPC),
.OUT(Q[i]));
end
end
for (i=0; i<=15; i=i+1) begin : buffers
//Buffer32_32(input [31:0] IN,input Store,output [31:0] OUT);
Buffer32_32 bufffer(.IN(Q[i]),.Store(DecoderRn_CU[i]),.OUT(Rn));
end
for (i=0; i<=15; i=i+1) begin : buffers2
//Buffer32_32(input [31:0] IN,input Store,output [31:0] OUT);
Buffer32_32 bufffer2(.IN(Q[i]),.Store(DecoderRm[i]),.OUT(Rm));
end
for (i=0; i<=15; i=i+1) begin : buffers3
//Buffer32_32(input [31:0] IN,input Store,output [31:0] OUT);
Buffer32_32 bufffer3(.IN(Q[i]),.Store(DecoderRs[i]),.OUT(Rs));
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//`define CHIPSCOPE
/***********************************************************************
This file is part of the OpenADC Project. See www.newae.com for more details,
or the codebase at http://www.assembla.com/spaces/openadc .
This file is the Partial Reconfiguration (using ICAP) interface.
Copyright (c) 2013, Colin O'Flynn <>. All rights reserved.
This project (and file) is released under the 2-Clause BSD License:
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*************************************************************************/
module reg_reconfig(
input reset_i,
input clk,
input [5:0] reg_address, // Address of register
input [15:0] reg_bytecnt, // Current byte count
input [7:0] reg_datai, // Data to write
output [7:0] reg_datao, // Data to read
input [15:0] reg_size, // Total size being read/write
input reg_read, // Read flag
input reg_write, // Write flag
input reg_addrvalid,// Address valid flag
output reg_stream,
input [5:0] reg_hypaddress,
output [15:0] reg_hyplen
);
wire icap_clk;
wire icap_ce;
wire icap_wr;
wire [15:0] icap_in;
reg fifo_wr_en;
reg fifo_rd_en;
wire [17:0] fifo_din;
wire [17:0] fifo_dout;
//Data ordering required by ICAP (same as SelectMAP) differs from .bit file
//assign icap_in[15:0] = {fifo_dout[8:15], fifo_dout[0:7]};
assign icap_in[15] = fifo_dout[8];
assign icap_in[14] = fifo_dout[9];
assign icap_in[13] = fifo_dout[10];
assign icap_in[12] = fifo_dout[11];
assign icap_in[11] = fifo_dout[12];
assign icap_in[10] = fifo_dout[13];
assign icap_in[9] = fifo_dout[14];
assign icap_in[8] = fifo_dout[15];
assign icap_in[7] = fifo_dout[0];
assign icap_in[6] = fifo_dout[1];
assign icap_in[5] = fifo_dout[2];
assign icap_in[4] = fifo_dout[3];
assign icap_in[3] = fifo_dout[4];
assign icap_in[2] = fifo_dout[5];
assign icap_in[1] = fifo_dout[6];
assign icap_in[0] = fifo_dout[7];
`define START_PATTERN 5'h1A
`define RECONFIG_ADDR 52
reg [7:0] icap_statusreg;
/*
[ 7 6 5 4 3 2 1 0 ]
x x R G G G G G
G G G G G = 1 1 0 1 0 (0x1A) start pattern
R = Reset bit
The first byte is written to the status register, remaining bytes written to FIFO.
To use interface:
* Split bitstream into byte chunks
* Write (1<<5) to reconfig addr
* Write 0x00 to reconfig addr
* Prepend a 0 to bitstream chunks (required as first byte will go into status/control register)
* Write chunks with prepended 0 into reconfig addr
* Write 0x1A to reconfig addr (start pattern)
* Write 0x00 to reconfig addr
*/
reg [15:0] reg_hyplen_reg;
assign reg_hyplen = reg_hyplen_reg;
always @(reg_hypaddress) begin
case (reg_hypaddress)
`RECONFIG_ADDR: reg_hyplen_reg <= 1;
default: reg_hyplen_reg<= 0;
endcase
end
wire fifo_rst;
reg [7:0] reg_datao_reg;
assign reg_datao = reg_datao_reg;
assign fifo_rst = icap_statusreg[5];
always @(posedge clk) begin
if (reg_read) begin
case (reg_address)
`RECONFIG_ADDR: begin reg_datao_reg <= icap_statusreg; end
default: begin reg_datao_reg <= 0; end
endcase
end
end
reg [15:0] data_in;
reg dowr;
always @(posedge clk)
fifo_wr_en <= dowr;
always @(posedge clk) begin
if (reset_i) begin
icap_statusreg <= 0;
end else if ((icap_statusreg[4:0] == `START_PATTERN) & (fifo_empty)) begin
icap_statusreg <= 0;
end else if (reg_write) begin
if (reg_bytecnt == 0) begin
case (reg_address)
`RECONFIG_ADDR: icap_statusreg <= reg_datai;
default: ;
endcase
end else begin
if (reg_bytecnt[0] == 1'b1) begin
data_in[15:8] <= reg_datai;
end else begin
data_in[7:0] <= reg_datai;
end
end
end
end
always @(posedge clk) begin
if (reset_i)
dowr <= 0;
else if ((reg_write) & (reg_bytecnt != 0) & (reg_bytecnt[0] == 1'b0) & (reg_address == `RECONFIG_ADDR))
dowr <= 1;
else
dowr <= 0;
end
assign fifo_din[15:0] = data_in;
assign fifo_din[17:16] = 2'b00;
reg do_config;
always @(posedge clk) begin
do_config <= (icap_statusreg[4:0] == `START_PATTERN) ? 1'b1 : 1'b0;
end
//Cross clock domain
reg icap_cfg;
reg icap_cfg2;
always @(posedge icap_clk) begin
icap_cfg2 <= do_config;
icap_cfg <= icap_cfg2;
end
reg [2:0] cnt;
always @(posedge clk)
cnt <= cnt + 3'b1;
assign icap_clk = cnt[2];
// ICAP_SPARTAN6: Internal Configuration Access Port
// Spartan-6
ICAP_SPARTAN6 #(
.DEVICE_ID('h04004093), // Specifies the pre-programmed Device ID value
.SIM_CFG_FILE_NAME("NONE") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
// model
)
ICAP_SPARTAN6_inst (
.BUSY(), // 1-bit Busy/Ready output
.O(), // 16-bit Configuartion data output bus
.CE(~icap_cfg), // 1-bit Active-Low ICAP Enable input
.CLK(icap_clk), // 1-bit Clock input
.I(icap_in), // 16-bit Configuration data input bus
.WRITE(1'b0) // 1-bit Read/Write control input
);
// End of ICAP_SPARTAN6_inst instantiation
//CoreGen FIFO. Default project ONLY for LX9 device, you'll have to regenerate for other families
//Be sure to verify FIFO length!!!!!!!!!!!
icap_fifo icap_fifo (
.rst(reset_i | fifo_rst),
.wr_clk(clk),
.rd_clk(icap_clk),
.din(fifo_din),
.wr_en(fifo_wr_en),
.rd_en(icap_cfg & ~fifo_empty),
.dout(fifo_dout),
.full(fifo_full),
.empty(fifo_empty),
.almost_empty()
);
`ifdef CHIPSCOPE
wire [127:0] cs_data;
wire [35:0] chipscope_control;
coregen_icon icon (
.CONTROL0(chipscope_control) // INOUT BUS [35:0]
);
coregen_ila ila (
.CONTROL(chipscope_control), // INOUT BUS [35:0]
.CLK(icap_clk), // IN
.TRIG0(cs_data) // IN BUS [127:0]
);
assign cs_data[15:0] = icap_in;
assign cs_data[16] = fifo_wr_en;
assign cs_data[17] = icap_cfg;
assign cs_data[18] = fifo_empty;
`endif
endmodule
`undef CHIPSCOPE
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 1, 0, -1}; int dy[] = {1, 0, -1, 0}; int dp[1005][1005]; bool vis[1005][1005]; int sx, sy, x, y; vector<string> v; bool valid(int xx, int yy) { if (xx >= 0 && yy >= 0 && xx < x && yy < y && v[xx][yy] != * ) return 1; return 0; } int bfs() { int wx, wy, ans = 0; vector<pair<int, int> > vaa; queue<pair<int, int> > q; q.push(make_pair(sx, sy)); vis[sx][sy] = 1; while (!q.empty()) { sx = q.front().first; sy = q.front().second; vaa.push_back(make_pair(sx, sy)); q.pop(); for (int i = 0; i < 4; i++) { wx = sx + dx[i]; wy = sy + dy[i]; if (!valid(wx, wy)) ans++; if (valid(wx, wy) && !vis[wx][wy]) { vis[wx][wy] = 1; q.push(pair<int, int>(wx, wy)); } } } for (int i = 0; i < vaa.size(); i++) dp[vaa[i].first][vaa[i].second] = ans; return ans; } int main() { memset(dp, -1, sizeof(dp)); for (int i = 0; i < 1005; i++) for (int j = 0; j < 1005; j++) vis[i][j] = 0; int t; string s; cin >> x >> y >> t; for (int i = 0; i < x; i++) { cin >> s; v.push_back(s); } while (t--) { cin >> sx >> sy; sx--; sy--; if (dp[sx][sy] != -1) printf( %d n , dp[sx][sy]); else printf( %d n , bfs()); } return 0; }
|
#include <bits/stdc++.h> int loya[8]; int tloyal[8]; int level[8]; double pb[1 << 8]; int N, K, A; void init_search(int state, int B, int deepth, int cnt) { if (deepth == N) { pb[state] = cnt > (N >> 1) ? 1.0 : A / (double)(A + B); } else { init_search(state | (1 << deepth), B, deepth + 1, cnt + 1); init_search(state, B + level[deepth], deepth + 1, cnt); } } double calcu(double prb, int state, int deepth) { return (deepth == N) ? prb * pb[state] : calcu(prb * (tloyal[deepth] / 10.0), state | (1 << deepth), deepth + 1) + calcu(prb * (1 - tloyal[deepth] / 10.0), state, deepth + 1); } double search(int candy, int deepth) { double ans = 0.0; if (deepth == N) { ans = calcu(1.0, 0, 0); } else { int i; for (i = 0; i <= candy && loya[deepth] + i <= 10; i++) { tloyal[deepth] = loya[deepth] + i; double tmp = search(candy - i, deepth + 1); ans = tmp > ans ? tmp : ans; } } return ans; } int main() { while (scanf( %d %d %d , &N, &K, &A) == 3) { int i; for (i = 0; i < N; i++) { scanf( %d %d , level + i, loya + i); loya[i] /= 10; } init_search(0, 0, 0, 0); printf( %.10f n , search(K, 0)); } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg (
address,
clock,
q);
input [9:0] address;
input clock;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../Desktop/bg.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "24"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../Desktop/bg.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_a 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* $Id: red_pitaya_pid_block.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya PID controller.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Proportional-integral-derivative (PID) controller.
*
*
* /---\ /---\ /-----------\
* IN --| - |----+--> | P | ---> | SUM & SAT | ---> OUT
* \---/ | \---/ \-----------/
* ^ | ^ ^
* | | /---\ | |
* set ---- +--> | I | --------- |
* point | \---/ |
* | |
* | /---\ |
* ---> | D | ------------
* \---/
*
*
* Proportional-integral-derivative (PID) controller is made from three parts.
*
* Error which is difference between set point and input signal is driven into
* propotional, integral and derivative part. Each calculates its own value which
* is then summed and saturated before given to output.
*
* Integral part has also separate input to reset integrator value to 0.
*
*/
module red_pitaya_pid_block #(
parameter PSR = 12 ,
parameter ISR = 18 ,
parameter DSR = 10
)
(
// data
input clk_i , // clock
input rstn_i , // reset - active low
input [ 14-1: 0] dat_i , // input data
output [ 14-1: 0] dat_o , // output data
// settings
input [ 14-1: 0] set_sp_i , // set point
input [ 14-1: 0] set_kp_i , // Kp
input [ 14-1: 0] set_ki_i , // Ki
input [ 14-1: 0] set_kd_i , // Kd
input int_rst_i // integrator reset
);
//---------------------------------------------------------------------------------
// Set point error calculation
reg [ 15-1: 0] error ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
error <= 15'h0 ;
end
else begin
error <= $signed(set_sp_i) - $signed(dat_i) ;
end
end
//---------------------------------------------------------------------------------
// Proportional part
reg [29-PSR-1: 0] kp_reg ;
wire [ 29-1: 0] kp_mult ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
kp_reg <= {29-PSR{1'b0}};
end
else begin
kp_reg <= kp_mult[29-1:PSR] ;
end
end
assign kp_mult = $signed(error) * $signed(set_kp_i);
//---------------------------------------------------------------------------------
// Integrator
reg [ 29-1: 0] ki_mult ;
wire [ 33-1: 0] int_sum ;
reg [ 32-1: 0] int_reg ;
wire [32-ISR-1: 0] int_shr ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
ki_mult <= {29{1'b0}};
int_reg <= {32{1'b0}};
end
else begin
ki_mult <= $signed(error) * $signed(set_ki_i) ;
if (int_rst_i)
int_reg <= 32'h0; // reset
else if (int_sum[33-1:33-2] == 2'b01) // positive saturation
int_reg <= 32'h7FFFFFFF; // max positive
else if (int_sum[33-1:33-2] == 2'b10) // negative saturation
int_reg <= 32'h80000000; // max negative
else
int_reg <= int_sum[32-1:0]; // use sum as it is
end
end
assign int_sum = $signed(ki_mult) + $signed(int_reg) ;
assign int_shr = int_reg[32-1:ISR] ;
//---------------------------------------------------------------------------------
// Derivative
wire [ 29-1: 0] kd_mult ;
reg [29-DSR-1: 0] kd_reg ;
reg [29-DSR-1: 0] kd_reg_r ;
reg [29-DSR : 0] kd_reg_s ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
kd_reg <= {29-DSR{1'b0}};
kd_reg_r <= {29-DSR{1'b0}};
kd_reg_s <= {29-DSR+1{1'b0}};
end
else begin
kd_reg <= kd_mult[29-1:DSR] ;
kd_reg_r <= kd_reg;
kd_reg_s <= $signed(kd_reg) - $signed(kd_reg_r);
end
end
assign kd_mult = $signed(error) * $signed(set_kd_i) ;
//---------------------------------------------------------------------------------
// Sum together - saturate output
wire [ 33-1: 0] pid_sum ; // biggest posible bit-width
reg [ 14-1: 0] pid_out ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
pid_out <= 14'b0 ;
end
else begin
if ({pid_sum[33-1],|pid_sum[32-2:13]} == 2'b01) //positive overflow
pid_out <= 14'h1FFF ;
else if ({pid_sum[33-1],&pid_sum[33-2:13]} == 2'b10) //negative overflow
pid_out <= 14'h2000 ;
else
pid_out <= pid_sum[14-1:0] ;
end
end
assign pid_sum = $signed(kp_reg) + $signed(int_shr) + $signed(kd_reg_s) ;
assign dat_o = pid_out ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, v; cin >> n >> v; vector<vector<int> > mat(n + 1, vector<int>(v + 1, INT_MAX)); for (int i = 1, j = 0; j <= v; j++) { mat[i][j] = j; } for (int i = 2; i <= n; i++) { for (int j = 0; j <= v; j++) { if (j < v) { mat[i][j] = mat[i - 1][j + 1]; } else { mat[i][j] = mat[i][j - 1] + i; } } } cout << mat[n][0] << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const long long infll = 0x3f3f3f3f3f3f3f3fLL; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } set<pair<long long, int> > s; pair<long long, long long> a[200005]; pair<pair<long long, long long>, int> brige[200005]; set<pair<long long, int> >::iterator it; int ans[200005]; int main() { int n = read(); int m = read(); for (int i = 1; i <= n; i++) { cin >> a[i].first >> a[i].second; } for (int i = 1; i < n; i++) { brige[i] = make_pair( make_pair(a[i].second - a[i + 1].first, a[i].first - a[i + 1].second), i); } sort(brige + 1, brige + n); for (int i = 1; i <= m; i++) { long long kiss; cin >> kiss; s.insert(make_pair(kiss, i)); } for (int i = 1; i < n; i++) { long long r = -brige[i].first.second; long long l = -brige[i].first.first; it = s.lower_bound(make_pair(r, inf)); if (it == s.begin()) { printf( No n ); return 0; } it--; if (it->first < l) { printf( No n ); return 0; } ans[brige[i].second] = it->second; s.erase(it); } printf( Yes n ); for (int i = 1; i < n; i++) { printf( %d , ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; int k; cin >> n >> k; int octr = 0; int a[n]; int sum = 0; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] % 2 != 0) octr++; sum = sum + a[i]; } if (octr >= k) { if ((sum % 2 != 0 && k % 2 != 0) || (sum % 2 == 0 && k % 2 == 0)) { cout << YES << endl; int f = 0; while (k > 1) { if (a[f] % 2 != 0) { cout << f + 1 << ; k--; } f++; } cout << n << ; cout << endl; } else cout << NO << endl; } else cout << NO << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 115 + 5; char s[maxn][maxn]; int main() { int n, m; while (~scanf( %d%d , &n, &m)) { int mini = inf, maxi = 0, minj = inf, maxj = 0; getchar(); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %c , &s[i][j]); if (s[i][j] == B ) { mini = min(mini, i); minj = min(minj, j); maxi = max(maxi, i); maxj = max(maxj, j); } } getchar(); } printf( %d %d n , (mini + maxi) / 2, (minj + maxj) / 2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int get() { int x = 0, f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } const int N = 1e6 + 5, Base = 19260817, Invb = 494863259, mod = 998244353; int n; char s[N]; struct Edge { int v, nxt; } edge[N << 1]; int head[N], tot; int base[N], invb[N]; int dfn[N], rev[N], tim, fa[N], top[N], sze[N], son[N], dep[N]; int hshu[N], hshd[N]; void add(int u, int v) { edge[++tot].v = v, edge[tot].nxt = head[u], head[u] = tot; } void init() { base[0] = invb[0] = 1; for (int i = 1; i <= n; i++) base[i] = 1ll * base[i - 1] * Base % mod, invb[i] = 1ll * invb[i - 1] * Invb % mod; } void dfs(int u, int lst) { fa[u] = lst, sze[u] = 1, dep[u] = dep[lst] + 1; hshu[u] = (1ll * hshu[lst] * Base % mod + s[u]) % mod; hshd[u] = (1ll * base[dep[u] - 1] * s[u] % mod + hshd[lst]) % mod; for (int i = head[u]; i; i = edge[i].nxt) if (edge[i].v != lst) dfs(edge[i].v, u), sze[u] += sze[edge[i].v], son[u] = sze[edge[i].v] > sze[son[u]] ? edge[i].v : son[u]; } void df5(int u, int lst) { top[u] = lst, dfn[u] = ++tim, rev[tim] = u; if (son[u]) df5(son[u], lst); for (int i = head[u]; i; i = edge[i].nxt) if (!top[edge[i].v]) df5(edge[i].v, edge[i].v); } int LCA(int x, int y) { while (top[x] ^ top[y]) dep[top[x]] > dep[top[y]] ? x = fa[top[x]] : y = fa[top[y]]; return dep[x] < dep[y] ? x : y; } int KthFa(int x, int k) { while (dep[x] - dep[top[x]] < k && x != 1) k -= dep[x] - dep[top[x]] + 1, x = fa[top[x]]; return rev[dfn[x] - k]; } int GetFa(int x, int y, int lca, int k) { int disl = dep[x] - dep[lca] + 1; if (k <= disl) return KthFa(x, k - 1); else return KthFa(y, dep[x] + dep[y] - 2 * dep[lca] + 1 - k); } int GetVal(int x, int y) { int lca = LCA(x, y), lcaf = fa[lca]; int disu = dep[x] - dep[lca] + 1, disd = dep[y] - dep[lca]; int resu = 1ll * (hshd[x] - hshd[lcaf] + mod) * invb[dep[lcaf]] % mod; int resd = (hshu[y] - 1ll * hshu[lca] * base[disd] % mod + mod) % mod; return (resd + 1ll * resu * base[disd] % mod) % mod; } signed main() { n = get(), scanf( %s , s + 1); for (int i = 1, u, v; i < n; i++) u = get(), v = get(), add(u, v), add(v, u); init(); dfs(1, 0), df5(1, 1); int q = get(); while (q--) { int a = get(), b = get(), c = get(), d = get(); int lca1 = LCA(a, b), lca2 = LCA(c, d); int len1 = dep[a] + dep[b] - 2 * dep[lca1] + 1, len2 = dep[c] + dep[d] - 2 * dep[lca2] + 1; int l = 1, r = min(len1, len2), ans = 0; while (l <= r) { int mid = l + r >> 1; int fa1 = GetFa(a, b, lca1, mid), fa2 = GetFa(c, d, lca2, mid); if ((GetVal(a, fa1) + mod) % mod == (GetVal(c, fa2) + mod) % mod) ans = mid, l = mid + 1; else r = mid - 1; } printf( %d n , ans); } return 0; }
|
//
// fixed for 9.1 jan 21 2010 cruben
//
`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
sda_pad_in, sda_pad_out , sda_pad_en, scl_pad_in, scl_pad_out, scl_pad_en
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
input sda_pad_in;
input scl_pad_in;
output sda_pad_out;
output scl_pad_out;
output sda_pad_en;
output scl_pad_en;
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_padoen_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_in;
assign sda_pad_i = sda_pad_in;
assign sda_pad_out = sda_pad_o;
assign scl_pad_out = scl_pad_o;
assign sda_pad_en = sda_padoen_o;
assign scl_pad_en = scl_padoen_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
`include "macro.v"
module if_id_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`INST_ADDR_BUS] if_program_counter,
input wire[`INST_DATA_BUS] if_instruction,
output reg[`INST_ADDR_BUS] id_program_counter,
output reg[`INST_DATA_BUS] id_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
id_program_counter <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
id_instruction <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (stall[1] == `ENABLE && stall[2] == `DISABLE) begin
id_program_counter <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
id_instruction <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (stall[1] == `DISABLE) begin
id_program_counter <= if_program_counter;
id_instruction <= if_instruction;
end
end
endmodule // if_id_buffer
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Texture address comparison
// File : de3d_tc_compare.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// TC compare compares the two incoming addresses with both the
// level two associative cache, and the level 1 cache outputs
// from the MUX's. This block will generate the opcodes used to load
// the RAMS on a miss.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
// U_HBI hbi_top Host interface (PCI)
// U_VGA vga_top IBM(TM) Compatible VGA core
// U_DE de_top Drawing engine
// U_DLP dlp_top Display List Processor
// U_DDR3 DDR3 DDR3 Memory interface
// u_crt crt_top Display interface
// u_ramdac ramdac Digital DAC
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_compare
(
input de_clk,
input de_rstn,
input tc_ack,
input [17:0] ur, /* Texel addresses to be compared */
input [17:0] ul, /* Texel addresses to be compared */
input [17:0] lr, /* Texel addresses to be compared */
input [17:0] ll, /* Texel addresses to be compared */
/* {u[8:0],v[8:0]} */
input [3:0] mipmap_in, /* incoming mipmap number */
input [26:0] ul_tag, /* tag ul data */
input [26:0] ll_tag, /* tag ll data */
input [26:0] ur_tag, /* tag ur data */
input [26:0] lr_tag, /* tag lr data */
/* {lru,val1,mm1,tag1,val0,mm0,tag0} */
input exception, /* Exception code. */
input [2:0] bpt,
input tc_exact, /* when set, only validate UL tex */
input clip,
output [3:0] tc_op, /* operation to perform */
output reg [3:0] set_sel, /* Set to be updated */
output reg [3:0] set_read, /* Set to read from. */
output [7:0] hit_bus
);
reg [7:0] ur_comp, ul_comp, /* formatted for comparison */
lr_comp, ll_comp;
wire lru_ul = ul_tag[26];
wire valid1_ul = ul_tag[25];
wire [3:0] mm1_ul = ul_tag[24:21];
wire [7:0] cache1_ul = ul_tag[20:13];
wire valid0_ul = ul_tag[12];
wire [3:0] mm0_ul = ul_tag[11:8];
wire [7:0] cache0_ul = ul_tag[7:0];
wire lru_ll = ll_tag[26];
wire valid1_ll = ll_tag[25];
wire [3:0] mm1_ll = ll_tag[24:21];
wire [7:0] cache1_ll = ll_tag[20:13];
wire valid0_ll = ll_tag[12];
wire [3:0] mm0_ll = ll_tag[11:8];
wire [7:0] cache0_ll = ll_tag[7:0];
wire lru_ur = ur_tag[26];
wire valid1_ur = ur_tag[25];
wire [3:0] mm1_ur = ur_tag[24:21];
wire [7:0] cache1_ur = ur_tag[20:13];
wire valid0_ur = ur_tag[12];
wire [3:0] mm0_ur = ur_tag[11:8];
wire [7:0] cache0_ur = ur_tag[7:0];
wire lru_lr = lr_tag[26];
wire valid1_lr = lr_tag[25];
wire [3:0] mm1_lr = lr_tag[24:21];
wire [7:0] cache1_lr = lr_tag[20:13];
wire valid0_lr = lr_tag[12];
wire [3:0] mm0_lr = lr_tag[11:8];
wire [7:0] cache0_lr = lr_tag[7:0];
wire tc_same;
wire exact;
wire ul0_hit, ul1_hit;
wire ll0_hit, ll1_hit;
wire ur0_hit, ur1_hit;
wire lr0_hit, lr1_hit;
wire [8:0] ulx = ul[17:9];
wire [8:0] uly = ul[8:0];
wire [8:0] llx = ll[17:9];
wire [8:0] lly = ll[8:0];
wire [8:0] urx = ur[17:9];
wire [8:0] ury = ur[8:0];
wire [8:0] lrx = lr[17:9];
wire [8:0] lry = lr[8:0];
/* Determine read addresses */
always @*
begin
case (bpt) /* synopsys parallel_case */
// 8 bpt
3:
begin
ul_comp = {2'b0,uly[8:6],ulx[8:6]};
ur_comp = {2'b0,ury[8:6],urx[8:6]};
ll_comp = {2'b0,lly[8:6],llx[8:6]};
lr_comp = {2'b0,lry[8:6],lrx[8:6]};
end
// 32 bpt
5:
begin
ul_comp = {uly[8:4],ulx[8:6]};
ur_comp = {ury[8:4],urx[8:6]};
ll_comp = {lly[8:4],llx[8:6]};
lr_comp = {lry[8:4],lrx[8:6]};
end
default:
begin
ul_comp = {1'b0,uly[8:5],ulx[8:6]};
ur_comp = {1'b0,ury[8:5],urx[8:6]};
ll_comp = {1'b0,lly[8:5],llx[8:6]};
lr_comp = {1'b0,lry[8:5],lrx[8:6]};
end
endcase
end
assign hit_bus = ({ul1_hit,ul0_hit,ll1_hit,ll0_hit,ur1_hit,ur0_hit,lr1_hit,lr0_hit} & {8{tc_ack}});
assign ul0_hit = (ul_comp == cache0_ul && mipmap_in == mm0_ul && valid0_ul); // UL set 0 compare.
assign ul1_hit = (ul_comp == cache1_ul && mipmap_in == mm1_ul && valid1_ul); // UL set 1 compare.
assign ll0_hit = (ll_comp == cache0_ll && mipmap_in == mm0_ll && valid0_ll); // LL set 0 compare.
assign ll1_hit = (ll_comp == cache1_ll && mipmap_in == mm1_ll && valid1_ll); // LL set 1 compare.
assign ur0_hit = (ur_comp == cache0_ur && mipmap_in == mm0_ur && valid0_ur); // UR set 0 compare.
assign ur1_hit = (ur_comp == cache1_ur && mipmap_in == mm1_ur && valid1_ur); // UR set 1 compare.
assign lr0_hit = (lr_comp == cache0_lr && mipmap_in == mm0_lr && valid0_lr); // LR set 0 compare.
assign lr1_hit = (lr_comp == cache1_lr && mipmap_in == mm1_lr && valid1_lr); // LR set 1 compare.
assign tc_same = (ul == ur) & (ll == lr) & (ul == lr);
assign exact = tc_exact || tc_same;
/* Determine opcode */
assign tc_op = (clip) ? 4'b0000 :
(exact && (ul1_hit | ul0_hit)) ? 4'b0000 :
(exact && !(ul1_hit | ul0_hit)) ? 4'b1000 :
(exception && !(ul[0] ^ ll[0])) ? {~(ul1_hit | ul0_hit), 1'b0, 1'b0, 1'b0} :
(!exception && !(ul[0] ^ ll[0])) ? {~(ul1_hit | ul0_hit), 1'b0, ~(ur1_hit | ur0_hit), 1'b0} :
(exception) ? {~(ul1_hit | ul0_hit), ~(ll1_hit | ll0_hit), 1'b0, 1'b0} :
{~(ul1_hit | ul0_hit), ~(ll1_hit | ll0_hit), ~(ur1_hit | ur0_hit), ~(lr1_hit | lr0_hit)};
/* store the set select info. */
/* this tells the tag module which set to update. */
always @(posedge de_clk or negedge de_rstn)
begin
if (!de_rstn) set_sel <= 0;
else if (tc_ack) set_sel <= {(ul1_hit | ul0_hit | lru_ul),
(ll1_hit | ll0_hit | lru_ll),
(ur1_hit | ur0_hit | lru_ur),
(lr1_hit | lr0_hit | lru_lr)};
end
/* store the set read info. */
always @(posedge de_clk or negedge de_rstn)
if (!de_rstn)
set_read <= 0;
else if (tc_ack && exception)
set_read <= {(ul1_hit | (~ul0_hit & lru_ul)),
(ll1_hit | (~ll0_hit & lru_ll)),
(ul1_hit | (~ul0_hit & lru_ul)),
(ll1_hit | (~ll0_hit & lru_ll))};
else if (tc_ack && !exception)
set_read <= {(ul1_hit | (~ul0_hit & lru_ul)),
(ll1_hit | (~ll0_hit & lru_ll)),
(ur1_hit | (~ur0_hit & lru_ur)),
(lr1_hit | (~lr0_hit & lru_lr))};
endmodule
|
/*
* File: lsu_reg2mem.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Description:
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module lsu_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// big-endian memory layout
//
reg [7:0] memdata_hh; // byte address 00
reg [7:0] memdata_hl; // byte address 01
reg [7:0] memdata_lh; // byte address 10
reg [7:0] memdata_ll; // byte address 11
//
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b00} : memdata_hh = regdata[7:0];
{`LSUOP_STH, 2'b00} : memdata_hh = regdata[15:8];
{`LSUOP_STHB, 2'b00} : memdata_hh = regdata[7:0];
{`LSUOP_STW, 2'b00} : memdata_hh = regdata[31:24];
{`LSUOP_STWB, 2'b00} : memdata_hh = regdata[7:0];
default : memdata_hh = regdata[31:24];
endcase
end
//
// Mux to memdata[23:16]
// [TBD] comment out unneccessary access pattern(same with default), to evaluate syn result
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b01} : memdata_hl = regdata[7:0];
{`LSUOP_STH, 2'b00} : memdata_hl = regdata[7:0];
{`LSUOP_STHB, 2'b00} : memdata_hl = regdata[15:8];
{`LSUOP_STW, 2'b00} : memdata_hl = regdata[23:16];
{`LSUOP_STWB, 2'b00} : memdata_hl = regdata[15:8];
default : memdata_hl = regdata[7:0];
endcase
end
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b10} : memdata_lh = regdata[7:0];
{`LSUOP_STH, 2'b10} : memdata_lh = regdata[15:8];
{`LSUOP_STHB, 2'b10} : memdata_lh = regdata[7:0];
{`LSUOP_STW, 2'b00} : memdata_lh = regdata[15:8];
{`LSUOP_STWB, 2'b00} : memdata_lh = regdata[23:16];
default : memdata_lh = regdata[15:8];
endcase
end
//
// Mux to memdata[7:0]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`LSUOP_STB, 2'b11} : memdata_ll = regdata[7:0];
{`LSUOP_STH, 2'b10} : memdata_ll = regdata[7:0];
{`LSUOP_STHB, 2'b10} : memdata_ll = regdata[15:8];
{`LSUOP_STW, 2'b00} : memdata_ll = regdata[7:0];
{`LSUOP_STWB, 2'b00} : memdata_ll = regdata[31:25];
default : memdata_ll = regdata[7:0];
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int T, n, a, b, c; string s; int shi, bu, jian; int main() { cin >> T; while (T--) { shi = bu = jian = 0; cin >> n; cin >> a >> b >> c; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == R ) shi++; else if (s[i] == P ) bu++; else jian++; } if (min(a, jian) + min(b, shi) + min(c, bu) < (n + 1) / 2) { cout << NO << endl; continue; } cout << YES << endl; string t = ; for (int i = 0; i < s.length(); i++) { if (s[i] == R && b) { t += P ; b--; } else if (s[i] == P && c) { t += S ; c--; } else if (s[i] == S && a) { a--; t += R ; } else { t += _ ; } } for (int i = 0; i != n; ++i) { if (t[i] != _ ) continue; if (a) { t[i] = R ; a--; } else if (b) { t[i] = P ; b--; } else { t[i] = S ; c--; } } cout << t << n ; } return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:22 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_gpio_0_0_stub.v
// Design : zynq_design_1_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; using i3 = pair<int, ii>; using li = pair<ll, int>; using lii = pair<ll, ii>; using pll = pair<ll, ll>; using vi = vector<int>; using vl = vector<ll>; using vii = vector<ii>; using vli = vector<li>; using vpll = vector<pll>; using vi3 = vector<i3>; using vlii = vector<lii>; const int N = 2e5 + 5, L = 20; const ll INF = 1e17 + 7, mod = 1e9 + 7; const double eps = 1e-9, PI = acos(-1); int n, m; vector<ii> adj[N]; vector<int> tree[N]; int down[N], level[N]; int cycleId[N]; int to[N][L]; int dep[N]; int cact[N]; void dfs(int u, int p) { cycleId[u] = u; level[u] = 1 + level[p]; for (ii A : adj[u]) { int v = A.second; int e = A.first; if (cycleId[v] == 0) { dfs(v, u); } else if (v != p) { if (level[v] < level[u]) cycleId[u] = e; else down[u]++; } } for (ii A : adj[u]) { int v = A.second; if (v == p) continue; if ((cycleId[v] != v) && (down[v] == 0)) { cycleId[u] = cycleId[v]; } } } void dfsTree(int u, int p) { to[u][0] = p; dep[u] = 1 + dep[p]; for (int i = 1; i < L; i++) { to[u][i] = to[to[u][i - 1]][i - 1]; } for (int v : tree[u]) { if (v != p) { cact[v] += cact[u]; dfsTree(v, u); } } } int jump(int u, int k) { for (int i = 0; i < L; i++) if (k & (1 << i)) u = to[u][i]; return u; } int LCA(int u, int v) { if (u == v) return u; if (dep[u] < dep[v]) swap(u, v); u = jump(u, dep[u] - dep[v]); if (u == v) return u; for (int i = L - 1; i >= 0; i--) { if (to[u][i] != to[v][i]) { u = to[u][i]; v = to[v][i]; } } return to[u][0]; } ll pow_mod(ll a, ll b) { ll ret = 1ll; a %= mod; for (; b; ret = ret * (b & 1 ? a : 1ll) % mod, a = a * a % mod, b >>= 1ll) ; return ret; } ll calc(int u, int v) { ll A = cact[u]; ll B = cact[v]; int lca = LCA(u, v); ll C = cact[lca]; return pow_mod(2, A + B - 2 * C + (lca > n)); } void solve(int testCase) { scanf( %d %d , &n, &m); vii edges; for (int i = 0; i < m; i++) { int u, v; scanf( %d %d , &u, &v); adj[u].push_back({i + n + 1, v}); adj[v].push_back({i + n + 1, u}); edges.push_back({u, v}); } level[1] = 0; dfs(1, 0); for (pair<int, int> E : edges) { int u = cycleId[E.first]; int v = cycleId[E.second]; if (u != v) { tree[u].push_back(v); tree[v].push_back(u); } } for (int i = 1; i <= n; i++) { cact[cycleId[i]] = (cycleId[i] != i); } dfsTree(cycleId[1], 0); int q; scanf( %d , &q); while (q--) { int u, v; scanf( %d %d , &u, &v); printf( %lld n , calc(cycleId[u], cycleId[v])); } } int main() { int t = 1; for (int testCase = 1; testCase <= t; testCase++) { solve(testCase); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_2_V
`define SKY130_FD_SC_LS__O2BB2AI_2_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const double eps = 1e-9; string words[100005]; int type[100005]; int gender[100005]; void reverse(string &c) { for (int i = (0); i < (int((c).size()) / 2); i++) { char tmp = c[i]; c[i] = c[int((c).size()) - i - 1]; c[int((c).size()) - i - 1] = tmp; } } int main() { string line; getline(cin, line); stringstream ss(line); int n = 0; while (true) { string word; ss >> word; if (ss.fail()) break; words[n++] = word; } for (int i = (0); i < (n); i++) reverse(words[i]); for (int i = (0); i < (n); i++) { if (words[i].find( soil ) == 0) { type[i] = 0; gender[i] = 0; continue; }; if (words[i].find( alail ) == 0) { type[i] = 0; gender[i] = 1; continue; }; if (words[i].find( rte ) == 0) { type[i] = 1; gender[i] = 0; continue; }; if (words[i].find( arte ) == 0) { type[i] = 1; gender[i] = 1; continue; }; if (words[i].find( sitini ) == 0) { type[i] = 2; gender[i] = 0; continue; }; if (words[i].find( setini ) == 0) { type[i] = 2; gender[i] = 1; continue; }; gender[i] = -1; } if (n == 1 && gender[0] != -1) { cout << YES n ; return 0; } bool SameGender = true; for (int i = (1); i < (n); i++) if (gender[i] != gender[0]) SameGender = false; if (!SameGender || gender[0] == -1) { cout << NO n ; return 0; } int p1, p2, p3; p1 = 0; while (p1 < n && type[p1] == 0) ++p1; p2 = p1; while (p2 < n && type[p2] == 1) ++p2; p3 = p2; while (p3 < n && type[p3] == 2) ++p3; if (p3 == n && p2 == p1 + 1) cout << YES n ; else cout << NO n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; unsigned long long hs[1050], hL[1 << 15], bs[50]; int main() { mt19937_64 rnd(time(0)); srand(time(0)); int n, s, d; scanf( %d%d%d , &n, &s, &d); for (int i = 0; i < 1050; i++) hs[i] = rnd(); random_shuffle(hs, hs + 1050); for (int i = 0; i < s; i++) { int c; scanf( %d , &c); while (c--) { int k; scanf( %d , &k); bs[i] ^= hs[k]; } } int mid = min(10, s / 2); for (int bits = 0; bits < (1 << mid); bits++) { for (int i = 0; i < mid; i++) { if (bits >> i & 1) { hL[bits] ^= bs[i]; } } } unordered_map<unsigned long long, int> mp; mp[0] = 0; for (int bits = 0; bits < (1 << (s - mid)); bits++) { unsigned long long val = 0; for (int i = 0; i < s - mid; i++) { if (bits >> i & 1) { val ^= bs[i + mid]; } } int cnt = __builtin_popcount(bits); if (!mp.count(val) || mp[val] > cnt) { mp[val] = cnt; } } while (d--) { int c; scanf( %d , &c); unsigned long long v = 0; while (c--) { int k; scanf( %d , &k); v ^= hs[k]; } int res = INT_MAX; for (int bits = 0; bits < (1 << mid); bits++) { unsigned long long val = hL[bits] ^ v; if (mp.count(val)) res = min(res, mp[val] + __builtin_popcount(bits)); } if (res == INT_MAX) puts( -1 ); else printf( %d n , res); } return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always @ (event_expression) ;
// D:
module main ;
reg [3:0] value1 ;
initial
begin
# 10 ;
value1 = 4'h5;
# 10 ;
$display("PASSED\n");
$finish;
end
always @ (value1) ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int N = 1000 + 10; int n, l, k; double dp[202][202][404]; double pro[300]; int a[N]; double solve(int i, int sofar, int cap) { if (i == n + 1) { return sofar >= l && cap >= 0; } double &ret = dp[i][sofar][cap + 200]; if (ret == ret) return ret; int toref = min(200, cap + a[i]); toref = max(toref, -200); double c1 = solve(i + 1, sofar + 1, toref) * pro[i]; double c2 = solve(i + 1, sofar, cap) * (1 - pro[i]); return ret = c1 + c2; } int main() { cin >> n >> l >> k; for (int i = 1; i <= n; ++i) { cin >> pro[i]; pro[i] /= 100.0; } for (int i = 1; i <= n; ++i) cin >> a[i]; memset(dp, -1, sizeof(dp)); cout << fixed << setprecision(10) << solve(1, 0, k) << endl; }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int N = 5005; int t[N], cnt[N], ans[N]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &t[i]); for (int i = 0; i < n; i++) { memset(cnt, 0, sizeof(cnt)); int mx = 0, mxi = 1; for (int j = i; j < n; j++) { cnt[t[j]]++; if (cnt[t[j]] > mx) { mx = cnt[t[j]]; mxi = t[j]; } else if (cnt[t[j]] == mx) { mxi = min(mxi, t[j]); } ans[mxi]++; } } for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << endl; return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter.
`timescale 1ns/100ps
module ad_iqcor (
// data interface
clk,
valid,
data_in,
data_iq,
valid_out,
data_out,
// control interface
iqcor_enable,
iqcor_coeff_1,
iqcor_coeff_2);
// select i/q if disabled
parameter Q_OR_I_N = 0;
// data interface
input clk;
input valid;
input [15:0] data_in;
input [15:0] data_iq;
output valid_out;
output [15:0] data_out;
// control interface
input iqcor_enable;
input [15:0] iqcor_coeff_1;
input [15:0] iqcor_coeff_2;
// internal registers
reg p1_valid = 'd0;
reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0;
reg [33:0] p1_data_p = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
reg [15:0] iqcor_coeff_1_r = 'd0;
reg [15:0] iqcor_coeff_2_r = 'd0;
// internal signals
wire [15:0] data_i_s;
wire [15:0] data_q_s;
wire [33:0] p1_data_p_i_s;
wire p1_valid_s;
wire [15:0] p1_data_i_s;
wire [33:0] p1_data_p_q_s;
wire [15:0] p1_data_q_s;
// swap i & q
assign data_i_s = (Q_OR_I_N == 1) ? data_iq : data_in;
assign data_q_s = (Q_OR_I_N == 1) ? data_in : data_iq;
// coefficients are flopped to remove warnings from vivado
always @(posedge clk) begin
iqcor_coeff_1_r <= iqcor_coeff_1;
iqcor_coeff_2_r <= iqcor_coeff_2;
end
// scaling functions - i
ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
.clk (clk),
.data_a ({data_i_s[15], data_i_s}),
.data_b ({iqcor_coeff_1_r[15], iqcor_coeff_1_r}),
.data_p (p1_data_p_i_s),
.ddata_in ({valid, data_i_s}),
.ddata_out ({p1_valid_s, p1_data_i_s}));
// scaling functions - q
ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
.clk (clk),
.data_a ({data_q_s[15], data_q_s}),
.data_b ({iqcor_coeff_2_r[15], iqcor_coeff_2_r}),
.data_p (p1_data_p_q_s),
.ddata_in (data_q_s),
.ddata_out (p1_data_q_s));
// sum
always @(posedge clk) begin
p1_valid <= p1_valid_s;
p1_data_i <= p1_data_i_s;
p1_data_q <= p1_data_q_s;
p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
end
// output registers
always @(posedge clk) begin
valid_out <= p1_valid;
if (iqcor_enable == 1'b1) begin
data_out <= p1_data_p[29:14];
end else if (Q_OR_I_N == 1) begin
data_out <= p1_data_q;
end else begin
data_out <= p1_data_i;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; long long mx, mi; int t, head[N], len, k, vis[N]; struct edge { int v, w, next; } e[N * 2]; void add(int u, int v, int w) { e[len].v = v; e[len].w = w; e[len].next = head[u]; head[u] = len++; } void dfs(int u, int fa) { vis[u] = 1; for (int j = head[u]; j; j = e[j].next) { int v = e[j].v; int w = e[j].w; if (v == fa) continue; dfs(v, u); if (vis[v] & 1) { mi += w; } mx += (long long)min(k - vis[v], vis[v]) * w; vis[u] += vis[v]; } } int main() { scanf( %d , &t); while (t--) { scanf( %d , &k); int u, v, w; k <<= 1; len = 1; memset(head, 0, sizeof(head)); memset(vis, 0, sizeof(vis)); for (int i = 1; i < k; i++) { scanf( %d%d%d , &u, &v, &w); add(u, v, w); add(v, u, w); } mi = 0, mx = 0; dfs(1, 0); printf( %lld %lld n , mi, mx); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int dx[8] = {-1, -1, -1, 0, 0, 1, 1, 1}; const int dy[8] = {-1, 0, 1, -1, 1, -1, 0, 1}; int t, ans, n, m; int a[256][256], u[256][256]; char c; void work(int x, int y) { int tx, ty; u[x][y] = 1; for (int i = 0; i <= 7; i++) { tx = x + dx[i]; ty = y + dy[i]; if ((a[tx][ty] == 1) and (u[tx][ty] == 0)) work(tx, ty); } } bool check1(int x, int y) { int d = x, r = y; while (a[x][r + 1] == 1) r++; while (a[d + 1][y] == 1) d++; if (((r - y) != (d - x)) or ((r - y) == 0)) return false; for (int j = y; j <= r; j++) if (a[d][j] == 0) return false; for (int i = x; i <= d; i++) if (a[i][r] == 0) return false; for (int j = y - 1; j <= r + 1; j++) if ((a[x - 1][j] == 1) or (a[d + 1][j] == 1)) return false; for (int i = x - 1; i <= d + 1; i++) if ((a[i][y - 1] == 1) or (a[i][r + 1] == 1)) return false; if ((r - y) == 1) return true; for (int j = y + 1; j <= r - 1; j++) if ((a[x + 1][j] == 1) or (a[d - 1][j] == 1)) return false; for (int i = x + 1; i <= d - 1; i++) if ((a[i][y + 1] == 1) or (a[i][r - 1] == 1)) return false; return true; } bool check2(int x, int y) { int li = x, lj = y; int ri = x, rj = y; int xx, yy; while (a[li + 1][lj - 1] == 1) { li++; lj--; } while (a[ri + 1][rj + 1] == 1) { ri++; rj++; } if ((li != ri) or (li == x)) return false; for (int i = 1; i <= li - x; i++) if ((a[li + i][lj + i] == 0) or (a[ri + i][rj - i] == 0)) return false; int d = x + 2 * (li - x); for (int i = 0; i <= li - x; i++) { xx = x + i; yy = y - i; if ((a[xx - 1][yy] == 1) or (a[xx - 1][yy - 1] == 1)) return false; yy = y + i; if ((a[xx - 1][yy] == 1) or (a[xx - 1][yy + 1] == 1)) return false; xx = d - i; yy = y - i; if ((a[xx + 1][yy] == 1) or (a[xx + 1][yy - 1] == 1)) return false; yy = y + i; if ((a[xx + 1][yy] == 1) or (a[xx + 1][yy + 1] == 1)) return false; } if ((a[li][lj - 1] == 1) or (a[li][rj + 1] == 1)) return false; if ((li - x) == 1) if (a[x + 1][y] == 1) return false; else return true; for (int i = 1; i < li - x; i++) { xx = x + i; yy = y - i; if ((a[xx + 1][yy] == 1) or (a[xx + 1][yy + 1] == 1)) return false; yy = y + i; if ((a[xx + 1][yy] == 1) or (a[xx + 1][yy - 1] == 1)) return false; xx = d - i; yy = y - i; if ((a[xx - 1][yy] == 1) or (a[xx - 1][yy + 1] == 1)) return false; yy = y + i; if ((a[xx - 1][yy] == 1) or (a[xx - 1][yy - 1] == 1)) return false; } if ((a[x + 1][y] == 1) or (a[d - 1][y] == 1)) return false; else return true; } bool judge(int x, int y) { work(x, y); if ((check1(x, y)) or (check2(x, y))) return true; else return false; } int main() { cin >> t; for (; t > 0; t--) { cin >> n >> m; memset(a, 0, sizeof(a)); memset(u, 0, sizeof(u)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> c; a[i][j] = (int)c - 48; } scanf( %*c ); } ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if ((a[i][j] == 1) and (u[i][j] == 0)) if (judge(i, j)) ans++; cout << ans << endl; } }
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#include <bits/stdc++.h> using namespace std; double l[10], b[10]; vector<int> kk(10, -1); vector<vector<int> > v; int k, n; void abc(int i, int sum) { if (i == 0 && sum == 0) { v.push_back(kk); return; } if (i == 0) { return; } for (int j = 0; j <= k; j++) { if (sum - j < 0) break; kk[i - 1] = j; abc(i - 1, sum - j); } } double A; double ans = 0.0; void solve(vector<int>& v) { double sum = 0.0; for (int i = 0; i < (1 << n); i++) { double cur = 1.0; int ed = 0; double B = 0.0; for (int j = 0; j < n; j++) { double z = (l[j] + v[j] * 10) * 0.01; z = min(z, 1.0); if (i & (1 << j)) { cur *= z; ed++; } else { cur *= 1.0 - z; B += b[j]; } } if (ed <= n / 2) cur *= A / (A + B); sum += cur; } ans = max(ans, sum); } int main() { cin >> n >> k >> A; abc(n, k); for (int i = 0; i < n; i++) { cin >> b[i] >> l[i]; } for (int i = 0; i < v.size(); i++) { solve(v[i]); } printf( %.9f , ans); }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_TB_V
`define SKY130_FD_SC_MS__DLXBN_TB_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxbn.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_ms__dlxbn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_TB_V
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//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ()
//
// Copyright (c) 2004 Guy Hutchison ()
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
module tv80n (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] do;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
reg nxt_mreq_n;
reg nxt_iorq_n;
reg nxt_rd_n;
reg nxt_wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.do (do),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @*
begin
nxt_mreq_n = 1;
nxt_rd_n = 1;
nxt_iorq_n = 1;
nxt_wr_n = 1;
if (mcycle[0])
begin
if (tstate[1] || tstate[2])
begin
nxt_rd_n = ~ intcycle_n;
nxt_mreq_n = ~ intcycle_n;
nxt_iorq_n = intcycle_n;
end
end // if (mcycle[0])
else
begin
if ((tstate[1] || tstate[2]) && !no_read && !write)
begin
nxt_rd_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write)
begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && !wait_n)) && write)
begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
end // always @ *
always @(negedge clk)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
end
else
begin
rd_n <= #1 nxt_rd_n;
wr_n <= #1 nxt_wr_n;
iorq_n <= #1 nxt_iorq_n;
mreq_n <= #1 nxt_mreq_n;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
always @(posedge clk)
begin
if (!reset_n)
begin
di_reg <= #1 0;
end
else
begin
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk)
endmodule // t80n
|
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long t; cin >> t; while (t--) { long long n, l, r; cin >> n >> l >> r; vector<long long> lol = {0}; for (long long i = n - 1; i >= 1; i--) { lol.push_back(lol.back() + 2 * i); } for (long long x = l; x <= r; x++) { if (x == n * (n - 1) + 1) { cout << 1 << ; } else { long long block = (long long)(lower_bound(lol.begin(), lol.end(), x) - lol.begin()); if (x % 2 == 1) { cout << block << ; } else { long long h = x - lol[block - 1]; cout << h / 2 + block << ; } } } cout << n ; } }
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#include <bits/stdc++.h> using namespace std; const signed long long INF = 1000000100; const long double EPS = 1e-9; const long double Pi = 2 * atanl(1.0); template <typename T, typename U> ostream &operator<<(ostream &os, const pair<T, U> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &V) { os << [ ; for (int(i) = (0); (i) < (int(V.size())); (i)++) os << V[i] << ((i == int(V.size()) - 1) ? : , ); return os << ] ; } template <typename T> ostream &operator<<(ostream &os, const set<T> &S) { os << ( ; for (T i : S) os << i << (i == *S.rbegin() ? : , ); return os << ) ; } template <typename T, typename U> ostream &operator<<(ostream &os, const map<T, U> &M) { os << { ; for (pair<T, U> i : M) os << i << (i.X == M.rbegin()->X ? : , ); return os << } ; } inline bool is_zero(const long double &first) { return first >= -EPS and first <= EPS; } inline int sign(const long double &first) { if (first < -EPS) return -1; else if (first > EPS) return 1; else return 0; } inline pair<long double, long double> operator+( const pair<long double, long double> &a, const pair<long double, long double> &b) { return pair<long double, long double>(a.first + b.first, a.second + b.second); } inline pair<long double, long double> operator-( const pair<long double, long double> &a, const pair<long double, long double> &b) { return pair<long double, long double>(a.first - b.first, a.second - b.second); } inline pair<long double, long double> operator*( const pair<long double, long double> &a, long double t) { return pair<long double, long double>(a.first * t, a.second * t); } inline pair<long double, long double> operator/( const pair<long double, long double> &a, long double t) { return pair<long double, long double>(a.first / t, a.second / t); } inline bool operator==(const pair<long double, long double> &a, const pair<long double, long double> &b) { return is_zero(a.first - b.first) and is_zero(a.second - b.second); } inline bool operator!=(const pair<long double, long double> &a, const pair<long double, long double> &b) { return !is_zero(a.first - b.first) or !is_zero(a.second - b.second); } pair<long double, long double> FAIL = make_pair(1e30, 1e30); inline long double cp(const pair<long double, long double> &a, const pair<long double, long double> &b) { return a.first * b.second - a.second * b.first; } inline long double dp(const pair<long double, long double> &a, const pair<long double, long double> &b) { return a.first * b.first + a.second * b.second; } inline long double pieprzu(const pair<long double, long double> &a, const pair<long double, long double> &b) { return sqrtl((b.first - a.first) * (b.first - a.first) + (b.second - a.second) * (b.second - a.second)); } inline long double distance_point_line( const pair<long double, long double> &p, const pair<pair<long double, long double>, pair<long double, long double> > &u) { return cp(p - u.first, p - u.second) / pieprzu(u.first, u.second); } inline bool on_right(const pair<long double, long double> &a, const pair<long double, long double> &b, const pair<long double, long double> &c) { return sign(cp(c - a, b - a)) == 1; } inline bool on_left(const pair<long double, long double> &a, const pair<long double, long double> &b, const pair<long double, long double> &c) { return sign(cp(c - a, b - a)) == -1; } inline double polygon_area(const vector<pair<long double, long double> > &A) { long double result = 0.0; if (int(A.size()) <= 2) return 0; for (int(i) = (2); (i) < (int(A.size())); (i)++) result += cp(A[i] - A[0], A[i - 1] - A[0]); return abs(result / 2); } inline pair<long double, long double> projection( const pair<long double, long double> &p, const pair<pair<long double, long double>, pair<long double, long double> > &u) { return u.first + ((u.second - u.first) * (dp(p - u.first, u.second - u.first) / dp(u.second - u.first, u.second - u.first))); } inline bool between(const pair<long double, long double> &a, const pair<long double, long double> &b, const pair<long double, long double> &c) { return sign(min(b.first, c.first) - a.first) <= 0 and sign(a.first - max(b.first, c.first)) <= 0 and sign(min(b.second, c.second) - a.second) <= 0 and sign(a.second - max(b.second, c.second)) <= 0; } inline bool on_segment(const pair<long double, long double> &p, const pair<pair<long double, long double>, pair<long double, long double> > &u) { return between(p, u.first, u.second) and pieprzu(p, projection(p, u)) < EPS; } inline long double distance_segment_point( const pair<pair<long double, long double>, pair<long double, long double> > &u, const pair<long double, long double> &p) { if (on_segment(projection(p, u), u)) return fabs(distance_point_line(p, u)); else return min(pieprzu(u.first, p), pieprzu(u.second, p)); } inline long double angle(const pair<long double, long double> &a, const pair<long double, long double> &o, const pair<long double, long double> &b) { long double result = atan2l(a.first - o.first, a.second - o.second) - atan2l(b.first - o.first, b.second - o.second); if (sign(result) == -1) result += 2 * Pi; return result; } inline pair<long double, long double> point_reflection( const pair<long double, long double> &s, const pair<long double, long double> &p) { return p + (s - p) * 2; } inline pair<long double, long double> axial_reflection( const pair<long double, long double> &p, const pair<pair<long double, long double>, pair<long double, long double> > &u) { return point_reflection(p, projection(p, u)); } inline int triangle_inequality(long double &p, long double q, long double r) { int a = sign(p + q - r); int b = sign(p + r - q); int c = sign(q + r - p); if (a == -1 or b == -1 or c == -1) return -1; if (a == 0 or b == 0 or c == 0) return 0; return 1; } vector<pair<long double, long double> > convex_hull( vector<pair<long double, long double> > A) { if (int(A.size()) <= 1) return A; sort(A.begin(), A.end()); vector<pair<long double, long double> > R{A[0], A[1]}; for (int(i) = (2); (i) < (int(A.size())); (i)++) { while (int(R.size()) >= 2 and !on_right(R[R.size() - 2], R[R.size() - 1], A[i])) R.pop_back(); R.push_back(A[i]); } int u = int(A.size()); for (int(i) = (int(A.size()) - 2); (i) >= (0); (i)--) { while (int(R.size()) > u and !on_right(R[R.size() - 2], R[R.size() - 1], A[i])) R.pop_back(); R.push_back(A[i]); } R.pop_back(); return move(R); } inline pair<long double, long double> rotate90_origin( const pair<long double, long double> &p) { return pair<long double, long double>(p.second, -p.first); } inline pair<long double, long double> rotate90( const pair<long double, long double> &p, const pair<long double, long double> &o) { return o + rotate90_origin(p - o); } inline pair<long double, long double> rotate_origin( const pair<long double, long double> &p, long double theta) { theta = -theta; long double s = sinl(theta); long double c = cosl(theta); return pair<long double, long double>(p.first * c - p.second * s, p.first * s + p.second * c); } inline pair<long double, long double> rotate( const pair<long double, long double> &p, const pair<long double, long double> &o, long double theta) { return o + rotate_origin(p - o, theta); } inline bool parallel(const pair<pair<long double, long double>, pair<long double, long double> > &u, const pair<pair<long double, long double>, pair<long double, long double> > &v) { return is_zero(cp(u.second - u.first, v.second - v.first)); } bool perpendicular(const pair<pair<long double, long double>, pair<long double, long double> > &u, const pair<pair<long double, long double>, pair<long double, long double> > &v) { return is_zero(dp(u.second - u.first, v.second - v.first)); } inline pair<pair<long double, long double>, pair<long double, long double> > segment_bisector(const pair<pair<long double, long double>, pair<long double, long double> > &u) { pair<long double, long double> p = (u.first + u.second) / 2; return pair<pair<long double, long double>, pair<long double, long double> >( p, rotate90(u.second, p)); } inline pair<pair<long double, long double>, pair<long double, long double> > angle_bisector(const pair<long double, long double> &a, const pair<long double, long double> &o, const pair<long double, long double> &b) { return pair<pair<long double, long double>, pair<long double, long double> >( o, rotate(b, o, angle(a, o, b) / 2)); } inline pair<long double, long double> intersection_line_line( const pair<pair<long double, long double>, pair<long double, long double> > &u, const pair<pair<long double, long double>, pair<long double, long double> > &v) { long double p = cp(u.second - v.first, u.second - u.first); long double q = cp(v.second - v.first, u.second - u.first); if (is_zero(q)) return FAIL; return v.first + (v.second - v.first) * (p / q); } const pair<pair<long double, long double>, long double> CFAIL = pair<pair<long double, long double>, long double>(FAIL, 0); pair<pair<long double, long double>, long double> incircle( const pair<long double, long double> &a, const pair<long double, long double> &b, const pair<long double, long double> &c) { if (is_zero(cp(b - a, c - a))) return CFAIL; pair<pair<long double, long double>, pair<long double, long double> > p = segment_bisector( pair<pair<long double, long double>, pair<long double, long double> >( a, b)); pair<pair<long double, long double>, pair<long double, long double> > q = segment_bisector( pair<pair<long double, long double>, pair<long double, long double> >( a, c)); pair<long double, long double> t = intersection_line_line(p, q); return pair<pair<long double, long double>, long double>(t, pieprzu(t, a)); } pair<long double, long double> intersection_segment_segment( const pair<pair<long double, long double>, pair<long double, long double> > &u, const pair<pair<long double, long double>, pair<long double, long double> > &v) { pair<long double, long double> r = intersection_line_line(u, v); if (on_segment(r, u) and on_segment(r, v)) return r; else return FAIL; } int main() { int N, X, Y; scanf( %d %d %d , &N, &X, &Y); vector<pair<long double, long double> > P; int max_a = 0; int max_b = 0; for (int(i) = (1); (i) <= (N); (i)++) { int a, b; scanf( %d %d , &a, &b); max_a = max(max_a, a); max_b = max(max_b, b); P.emplace_back(a, b); } P.emplace_back(max_a, 0); P.emplace_back(0, max_b); P = convex_hull(P); pair<long double, long double> n(X, Y); pair<long double, long double> z; for (int(i) = (1); (i) <= (1500000); (i)++) { if (X * i > 1490490 or Y * i > 1490010) { z = pair<long double, long double>(X * i, Y * i); break; } } pair<pair<long double, long double>, pair<long double, long double> > s( pair<long double, long double>(0, 0), z); long double result = INF; for (int(i) = (0); (i) < (int(P.size())); (i)++) { pair<long double, long double> a = P[i]; pair<long double, long double> b = P[(i + 1) % int(P.size())]; pair<pair<long double, long double>, pair<long double, long double> > t(a, b); pair<long double, long double> d = intersection_segment_segment(s, t); if (d == FAIL) continue; result = min(result, pieprzu(pair<long double, long double>(X, Y), pair<long double, long double>(0, 0)) / pieprzu(d, pair<long double, long double>(0, 0))); } cout << fixed << result << endl; return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE64_IDLE 2'b00
`define S_TXPORTGATE64_OPENING 2'b01
`define S_TXPORTGATE64_OPEN 2'b10
`define S_TXPORTGATE64_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_64 #(
parameter C_DATA_WIDTH = 9'd64,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
)
(
input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE64_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
case (rState)
`S_TXPORTGATE64_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE64_OPENING;
end
end
`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
else
_rState = `S_TXPORTGATE64_OPEN;
end
end
`S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
end
`S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE64_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:09:44 06/18/2014
// Design Name: washing_machine
// Module Name: F:/ISE/work/final_exp/washing_machine/washing_machine_test.v
// Project Name: washing_machine
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: washing_machine
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module washing_machine_test;
// Inputs
reg clk;
reg power_button;
reg pause_button;
reg mode_button;
reg stage_button;
// Outputs
wire power_led;
wire pause_led;
wire [2:0] wash_led;
wire [3:0] stage_led;
wire [4:0] time_led;
wire warning_led;
parameter PERIOD = 10;
// Instantiate the Unit Under Test (UUT)
washing_machine uut (
.clk(clk),
.power_button(power_button),
.pause_button(pause_button),
.mode_button(mode_button),
.stage_button(stage_button),
.power_led(power_led),
.pause_led(pause_led),
.wash_led(wash_led),
.stage_led(stage_led),
.time_led(time_led),
.warning_led(warning_led)
);
always begin
clk = 1;
#(PERIOD/2);
clk = 0;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
clk = 0;
power_button = 0;
pause_button = 0;
mode_button = 0;
stage_button = 0;
// Wait 100 ns for global reset to finish
#20;
power_button = 1;
#3;
power_button = 0;
#10;
pause_button = 1;
#3;
pause_button = 0;
#40;
pause_button = 1;
#3;
pause_button = 0;
//#3;
//mode_button = 1;
//#3;
//mode_button = 0;
#30;
pause_button = 1;
#3;
pause_button = 0;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p1, p2; cin >> n; cin >> p1; int a1[p1]; for (int i = 0; i < p1; i++) cin >> a1[i]; cin >> p2; int a2[p2]; for (int i = 0; i < p2; i++) cin >> a2[i]; sort(a1, a1 + p1); sort(a2, a2 + p2); vector<int>::iterator it; vector<int> res(100); it = set_union(a1, a1 + p1, a2, a2 + p2, res.begin()); res.resize(it - res.begin()); if (res.size() == n) cout << I become the guy. ; else cout << Oh, my keyboard! ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_4_V
`define SKY130_FD_SC_MS__EINVP_4_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvp_4 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvp_4 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_4_V
|
#include <bits/stdc++.h> using namespace std; struct Point { double x, y; Point(double x = 0, double y = 0) : x(x), y(y) {} Point operator+(Point b) { return Point(x + b.x, y + b.y); } Point operator-(Point b) { return Point(x - b.x, y - b.y); } double operator^(Point b) { return x * b.y - y * b.x; } Point operator*(double b) { return Point(x * b, y * b); } double operator*(Point b) { return x * b.x + y * b.y; } inline double dis() { return sqrt(*this * *this); } }; struct tcurts { double r; int type; bool operator<(const tcurts &b) const { return r < b.r; } } q[100010 * 2]; int main() { Point A, B, C; scanf( %lf%lf%lf%lf , &A.x, &A.y, &B.x, &B.y), C = (A + B) * 0.5; Point normal = (B - A) * (1 / (B - A).dis()); normal = Point(-normal.y, normal.x); int n, top = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { Point p; double R; scanf( %lf%lf%lf , &p.x, &p.y, &R); int flag = ((p - A) ^ (B - A)) > 0; double l = -1e12, r = 1e12; for (int times = 1; times <= 80; times++) { double mid = (l + r) / 2; Point O = C + normal * mid; if ((O - A).dis() + R < (p - O).dis()) (flag ? r : l) = mid; else (flag ? l : r) = mid; } q[++top] = (tcurts){l, flag ? -1 : 1}, l = -1e12, r = 1e12; for (int times = 1; times <= 80; times++) { double mid = (l + r) / 2; Point O = C + normal * mid; if ((O - A).dis() - R > (p - O).dis()) (flag ? l : r) = mid; else (flag ? r : l) = mid; } q[++top] = (tcurts){l, flag ? 1 : -1}; } q[++top] = (tcurts){-1e12, 0}, q[++top] = (tcurts){1e12, 0}, q[++top] = (tcurts){0, 0}, sort(q + 1, q + top + 1); double res = 1e12; bool flag = false; for (int i = 1, s = 0; i <= top; i++) { if (!s) res = min(res, fabs(q[i].r)), flag = true; s += q[i].type; if (!s) res = min(res, fabs(q[i].r)), flag = true; } if (!flag) puts( -1 ); else printf( %.10lf n , (C + normal * res - A).dis()); }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, x, y, z; cin >> a >> b >> c >> x >> y >> z; int ans; if ((a == 0 && b == 0 && c) || (x == 0 && y == 0 && z)) { ans = 0; } else if (a * y == b * x) { if (a * z == c * x && b * z == c * y) { ans = -1; } else { ans = 0; } } else { ans = 1; } cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SREGSBP_FUNCTIONAL_PP_V
/**
* sregsbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire set ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (set , ASYNC );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, set, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_FUNCTIONAL_PP_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not FALSE");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = (test_expr == 1'b1);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
wire fire_cover = 1'b0;
|
`timescale 1 ns / 1 ps
`include "vga_axi_buffer_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define SAXI_MAX_BURST_LENGTH 1
`define SAXI_DATA_BUS_WIDTH 32
`define SAXI_ADDRESS_BUS_WIDTH 32
`define SAXI_MAX_DATA_SIZE (`SAXI_DATA_BUS_WIDTH*`SAXI_MAX_BURST_LENGTH)/8
module vga_axi_buffer_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA SAXI AXI4 Lite Local Reg
reg [`SAXI_DATA_BUS_WIDTH-1:0] SAXI_rd_data_lite;
reg [`SAXI_DATA_BUS_WIDTH-1:0] SAXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] SAXI_lite_response;
reg [`SAXI_ADDRESS_BUS_WIDTH-1:0] SAXI_mtestAddress;
reg [3-1:0] SAXI_mtestProtection_lite;
integer SAXI_mtestvectorlite; // Master side testvector
integer SAXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic SAXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : SAXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
SAXI_mtestvectorlite = 0;
SAXI_mtestAddress = `SAXI_SLAVE_ADDRESS;
SAXI_mtestProtection_lite = 0;
SAXI_mtestdatasizelite = `SAXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (SAXI_mtestvectorlite = 0; SAXI_mtestvectorlite <= 3; SAXI_mtestvectorlite = SAXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( SAXI_mtestAddress,
SAXI_mtestProtection_lite,
SAXI_test_data_lite[SAXI_mtestvectorlite],
SAXI_mtestdatasizelite,
SAXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",SAXI_mtestvectorlite,SAXI_test_data_lite[SAXI_mtestvectorlite],SAXI_lite_response);
CHECK_RESPONSE_OKAY(SAXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(SAXI_mtestAddress,
SAXI_mtestProtection_lite,
SAXI_rd_data_lite,
SAXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",SAXI_mtestvectorlite,SAXI_rd_data_lite,SAXI_lite_response);
CHECK_RESPONSE_OKAY(SAXI_lite_response);
COMPARE_LITE_DATA(SAXI_test_data_lite[SAXI_mtestvectorlite],SAXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",SAXI_mtestvectorlite,SAXI_mtestvectorlite);
SAXI_mtestAddress = SAXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST SAXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
SAXI_test_data_lite[0] = 32'h0101FFFF;
SAXI_test_data_lite[1] = 32'habcd0001;
SAXI_test_data_lite[2] = 32'hdead0011;
SAXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
SAXI_TEST();
end
endmodule
|
/*
* Copyright (c) 2000 Guy Hutchison ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module pullupdown;
// declare several bussed wires
wire pull_up_1, pull_down_1;
wire [7:0] pull_up_8, pull_down_8;
reg error;
// assign pullups to each wire
pullup (pull_up_1);
pulldown (pull_down_1);
pullup u8 [7:0] (pull_up_8);
pulldown d8 [7:0] (pull_down_8);
// create tristate drivers for each wire
reg driver_1;
reg [7:0] driver_8;
assign pull_up_1 = driver_1;
assign pull_down_1 = driver_1;
assign pull_up_8 = driver_8;
assign pull_down_8 = driver_8;
initial
begin : test_block
integer i;
// turn off all drivers
driver_1 = 1'bz;
driver_8 = 8'bz;
error = 0;
#1;
// check default values
if ((pull_up_1 !== 1'b1) || (pull_down_1 !== 1'b0) ||
(pull_up_8 !== 8'hFF) || (pull_down_8 !== 8'h00)) begin
$display("driver_8=%b, pull_up_8=%b, pull_down_8=%b",
driver_8, pull_up_8, pull_down_8);
$display("driver_1=%b, pull_up_1=%b, pull_down_1=%b",
driver_1, pull_up_1, pull_down_1);
error = 1;
end
for (i=0; i<256; i=i+1)
begin
driver_1 = ~driver_1;
driver_8 = i;
$display ("Testing drivers with value %h", driver_8);
#1;
check_drivers;
#10;
end
if (error)
$display ("FAILED - pullupdown ");
else $display ("PASSED");
end // block: test_block
task check_drivers;
begin
if ((pull_up_1 !== driver_1) || (pull_down_1 !== driver_1) ||
(pull_up_8 !== driver_8) || (pull_down_8 !== driver_8)) begin
$display("driver_8=%b, pull_up_8=%b, pull_down_8=%b",
driver_8, pull_up_8, pull_down_8);
$display("driver_1=%b, pull_up_1=%b, pull_down_1=%b",
driver_1, pull_up_1, pull_down_1);
error = 1;
end
end
endtask // check_drivers
endmodule // pullupdown
|
//
// Module: DRAM16XN
//
// Description: Distributed SelectRAM example
// Dual Port 16 x N-bit
//
// Device: Spartan-3 Family
//---------------------------------------------------------------------------------------
module DRAM16XN #(parameter data_width = 20)
(
DATA_IN,
ADDRESS,
ADDRESS_DP,
WRITE_EN,
CLK,
O_DATA_OUT,
O_DATA_OUT_DP);
input [data_width-1:0]DATA_IN;
input [3:0] ADDRESS;
input [3:0] ADDRESS_DP;
input WRITE_EN;
input CLK;
output [data_width-1:0]O_DATA_OUT_DP;
output [data_width-1:0]O_DATA_OUT;
genvar i;
generate
for(i = 0 ; i < data_width ; i = i + 1) begin : dram16s
RAM16X1D i_RAM16X1D_U(
.D(DATA_IN[i]), //insert input signal
.WE(WRITE_EN), //insert Write Enable signal
.WCLK(CLK), //insert Write Clock signal
.A0(ADDRESS[0]), //insert Address 0 signal port SPO
.A1(ADDRESS[1]), //insert Address 1 signal port SPO
.A2(ADDRESS[2]), //insert Address 2 signal port SPO
.A3(ADDRESS[3]), //insert Address 3 signal port SPO
.DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
.DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
.DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
.DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
.SPO(O_DATA_OUT[i]), //insert output signal SPO
.DPO(O_DATA_OUT_DP[i]) //insert output signal DPO
);
end
endgenerate
endmodule
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* one AES round for every two clock cycles */
module one_round (state_in, key, state_out);
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (s0, p00, p01, p02, p03),
t1 (s1, p10, p11, p12, p13),
t2 (s2, p20, p21, p22, p23),
t3 (s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (*)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (state_in, key_in, state_out);
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (s0, {p00, p01, p02, p03}),
S4_2 (s1, {p10, p11, p12, p13}),
S4_3 (s2, {p20, p21, p22, p23}),
S4_4 (s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (*)
state_out <= {z0, z1, z2, z3};
endmodule
|
// fir8dec.v: 8x FIR decimator with TDM I/Q I/O
// 07-17-16 E. Brombaugh
module fir8dec #(
parameter isz = 16, // input data size
osz = 16, // output data size
psz = 8, // pointer size
csz = 16, // coeff data size
clen = 246, // coeff data length
agrw = 3 // accumulator growth
)
(
input clk, // System clock
input reset, // System POR
input ena, // New sample available on input
input signed [isz-1:0] iq_in, // Input data
output reg valid, // New output sample ready
output reg signed [osz-1:0] qi_out // Output data - reverse order
);
//------------------------------
// write address generator
//------------------------------
reg [psz:0] w_addr;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
w_addr <= {psz+1{1'd0}};
end
else
begin
if(ena == 1'b1)
begin
w_addr <= w_addr + 1;
end
end
end
//------------------------------
// MAC control state machine
//------------------------------
`define sm_wait 3'b000
`define sm_macq 3'b001
`define sm_maci 3'b010
`define sm_dmpq 3'b011
`define sm_dmpi 3'b100
reg [2:0] state;
reg mac_ena, dump;
reg [psz:0] r_addr;
reg [psz-1:0] c_addr;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
state <= `sm_wait;
mac_ena <= 1'b0;
dump <= 1'b0;
r_addr <= {psz+1{1'd0}};
c_addr <= {psz{1'd0}};
end
else
begin
case(state)
`sm_wait :
begin
// halt and hold
if(w_addr[3:0] == 4'b1111)
begin
// start a MAC sequence every 16 entries (8 samples)
state <= `sm_macq;
mac_ena <= 1'b1;
r_addr <= w_addr;
c_addr <= {psz{1'd0}};
end
end
`sm_macq :
begin
// Accumulate Q and advance to I
state <= `sm_maci;
r_addr <= r_addr - 1;
end
`sm_maci :
begin
// Accumulate I
if(c_addr != clen)
begin
// advance to next coeff
state <= `sm_macq;
r_addr <= r_addr - 1;
c_addr <= c_addr + 1;
end
else
begin
// finish mac and advance to dump Q
state <= `sm_dmpq;
mac_ena <= 1'b0;
dump <= 1'b1;
end
end
`sm_dmpq :
begin
// advance to dump 1
state <= `sm_dmpi;
end
`sm_dmpi :
begin
// finish dump and return to wait
state <= `sm_wait;
dump <= 1'b0;
end
default :
begin
state <= `sm_wait;
mac_ena <= 1'b0;
dump <= 1'b0;
end
endcase
end
end
//------------------------------
// input buffer memory
//------------------------------
reg signed [isz-1:0] buf_mem [511:0];
reg signed [isz-1:0] r_data;
always @(posedge clk) // Write memory.
begin
if(ena == 1'b1)
begin
buf_mem[w_addr] <= iq_in;
end
end
always @(posedge clk) // Read memory.
begin
r_data <= buf_mem[r_addr];
end
//------------------------------
// coeff ROM
//------------------------------
reg signed [csz-1:0] coeff_rom[0:255];
reg signed [csz-1:0] c_data;
initial
begin
$readmemh("../src/fir8dec_coeff.memh", coeff_rom);
end
always @(posedge clk)
begin
c_data <= coeff_rom[c_addr];
end
//------------------------------
// MAC
//------------------------------
reg [2:0] mac_ena_pipe;
reg [2:0] dump_pipe;
reg signed [csz+isz-1:0] mult;
reg signed [csz+isz+agrw-1:0] acc_a, acc_b;
wire signed [csz+isz+agrw-1:0] rnd_const = 1<<(csz+1);
wire signed [osz-1:0] qi_sat;
// Saturate accum output
sat #(.isz(agrw+osz-2), .osz(osz))
u_sat(.in(acc_b[csz+isz+agrw-1:csz+2]), .out(qi_sat));
always @(posedge clk)
begin
if(reset == 1'b1)
begin
mac_ena_pipe <= 3'b000;
dump_pipe <= 3'b000;
mult <= {csz+isz{1'b0}};
acc_a <= rnd_const;
acc_b <= rnd_const;
valid <= 1'b0;
qi_out <= {osz{1'b0}};
end
else
begin
// shift pipes
mac_ena_pipe <= {mac_ena_pipe[1:0],mac_ena};
dump_pipe <= {dump_pipe[1:0],dump};
// multiplier always runs
mult <= r_data * c_data;
// accumulator
if(mac_ena_pipe[1] == 1'b1)
begin
// two-term accumulate
acc_a <= acc_b + {{agrw{mult[csz+isz-1]}},mult};
acc_b <= acc_a;
end
else
begin
// clear to round constant
acc_a <= rnd_const;
acc_b <= acc_a;
end
// output
if(dump_pipe[1] == 1'b1)
begin
qi_out <= qi_sat;
end
// valid
valid <= dump_pipe[1];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O21A_BEHAVIORAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; using lint = long long; using pint = pair<int, int>; using plint = pair<lint, lint>; struct fast_ios { fast_ios() { cin.tie(nullptr), ios::sync_with_stdio(false), cout << fixed << setprecision(20); }; } fast_ios_; template <typename T, typename V> void ndarray(vector<T> &vec, const V &val, int len) { vec.assign(len, val); } template <typename T, typename V, typename... Args> void ndarray(vector<T> &vec, const V &val, int len, Args... args) { vec.resize(len), for_each(begin(vec), end(vec), [&](T &v) { ndarray(v, val, args...); }); } template <typename T> bool chmax(T &m, const T q) { return m < q ? (m = q, true) : false; } template <typename T> bool chmin(T &m, const T q) { return m > q ? (m = q, true) : false; } int floor_lg(long long x) { return x <= 0 ? -1 : 63 - __builtin_clzll(x); } template <typename T1, typename T2> pair<T1, T2> operator+(const pair<T1, T2> &l, const pair<T1, T2> &r) { return make_pair(l.first + r.first, l.second + r.second); } template <typename T1, typename T2> pair<T1, T2> operator-(const pair<T1, T2> &l, const pair<T1, T2> &r) { return make_pair(l.first - r.first, l.second - r.second); } template <typename T> vector<T> sort_unique(vector<T> vec) { sort(vec.begin(), vec.end()), vec.erase(unique(vec.begin(), vec.end()), vec.end()); return vec; } template <typename T> int arglb(const std::vector<T> &v, const T &x) { return std::distance(v.begin(), std::lower_bound(v.begin(), v.end(), x)); } template <typename T> int argub(const std::vector<T> &v, const T &x) { return std::distance(v.begin(), std::upper_bound(v.begin(), v.end(), x)); } template <typename T> istream &operator>>(istream &is, vector<T> &vec) { for (auto &v : vec) is >> v; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &vec) { os << [ ; for (auto v : vec) os << v << , ; os << ] ; return os; } template <typename T, size_t sz> ostream &operator<<(ostream &os, const array<T, sz> &arr) { os << [ ; for (auto v : arr) os << v << , ; os << ] ; return os; } template <typename T> ostream &operator<<(ostream &os, const deque<T> &vec) { os << deq[ ; for (auto v : vec) os << v << , ; os << ] ; return os; } template <typename T> ostream &operator<<(ostream &os, const set<T> &vec) { os << { ; for (auto v : vec) os << v << , ; os << } ; return os; } template <typename T, typename TH> ostream &operator<<(ostream &os, const unordered_set<T, TH> &vec) { os << { ; for (auto v : vec) os << v << , ; os << } ; return os; } template <typename T> ostream &operator<<(ostream &os, const multiset<T> &vec) { os << { ; for (auto v : vec) os << v << , ; os << } ; return os; } template <typename T> ostream &operator<<(ostream &os, const unordered_multiset<T> &vec) { os << { ; for (auto v : vec) os << v << , ; os << } ; return os; } template <typename T1, typename T2> ostream &operator<<(ostream &os, const pair<T1, T2> &pa) { os << ( << pa.first << , << pa.second << ) ; return os; } template <typename TK, typename TV> ostream &operator<<(ostream &os, const map<TK, TV> &mp) { os << { ; for (auto v : mp) os << v.first << => << v.second << , ; os << } ; return os; } template <typename TK, typename TV, typename TH> ostream &operator<<(ostream &os, const unordered_map<TK, TV, TH> &mp) { os << { ; for (auto v : mp) os << v.first << => << v.second << , ; os << } ; return os; } template <int md> struct ModInt { using lint = long long; static int mod() { return md; } static int get_primitive_root() { static int primitive_root = 0; if (!primitive_root) { primitive_root = [&]() { std::set<int> fac; int v = md - 1; for (lint i = 2; i * i <= v; i++) while (v % i == 0) fac.insert(i), v /= i; if (v > 1) fac.insert(v); for (int g = 1; g < md; g++) { bool ok = true; for (auto i : fac) if (ModInt(g).pow((md - 1) / i) == 1) { ok = false; break; } if (ok) return g; } return -1; }(); } return primitive_root; } int val; ModInt() : val(0) {} ModInt &_setval(lint v) { return val = (v >= md ? v - md : v), *this; } ModInt(lint v) { _setval(v % md + md); } explicit operator bool() const { return val != 0; } ModInt operator+(const ModInt &x) const { return ModInt()._setval((lint)val + x.val); } ModInt operator-(const ModInt &x) const { return ModInt()._setval((lint)val - x.val + md); } ModInt operator*(const ModInt &x) const { return ModInt()._setval((lint)val * x.val % md); } ModInt operator/(const ModInt &x) const { return ModInt()._setval((lint)val * x.inv() % md); } ModInt operator-() const { return ModInt()._setval(md - val); } ModInt &operator+=(const ModInt &x) { return *this = *this + x; } ModInt &operator-=(const ModInt &x) { return *this = *this - x; } ModInt &operator*=(const ModInt &x) { return *this = *this * x; } ModInt &operator/=(const ModInt &x) { return *this = *this / x; } friend ModInt operator+(lint a, const ModInt &x) { return ModInt()._setval(a % md + x.val); } friend ModInt operator-(lint a, const ModInt &x) { return ModInt()._setval(a % md - x.val + md); } friend ModInt operator*(lint a, const ModInt &x) { return ModInt()._setval(a % md * x.val % md); } friend ModInt operator/(lint a, const ModInt &x) { return ModInt()._setval(a % md * x.inv() % md); } bool operator==(const ModInt &x) const { return val == x.val; } bool operator!=(const ModInt &x) const { return val != x.val; } bool operator<(const ModInt &x) const { return val < x.val; } friend std::istream &operator>>(std::istream &is, ModInt &x) { lint t; return is >> t, x = ModInt(t), is; } friend std::ostream &operator<<(std::ostream &os, const ModInt &x) { return os << x.val; } ModInt pow(lint n) const { ModInt ans = 1, tmp = *this; while (n) { if (n & 1) ans *= tmp; tmp *= tmp, n >>= 1; } return ans; } static std::vector<ModInt> facs, facinvs, invs; static void _precalculation(int N) { int l0 = facs.size(); if (N > md) N = md; if (N <= l0) return; facs.resize(N), facinvs.resize(N), invs.resize(N); for (int i = l0; i < N; i++) facs[i] = facs[i - 1] * i; facinvs[N - 1] = facs.back().pow(md - 2); for (int i = N - 2; i >= l0; i--) facinvs[i] = facinvs[i + 1] * (i + 1); for (int i = N - 1; i >= l0; i--) invs[i] = facinvs[i] * facs[i - 1]; } lint inv() const { if (this->val < std::min(md >> 1, 1 << 21)) { while (this->val >= int(facs.size())) _precalculation(facs.size() * 2); return invs[this->val].val; } else { return this->pow(md - 2).val; } } ModInt fac() const { while (this->val >= int(facs.size())) _precalculation(facs.size() * 2); return facs[this->val]; } ModInt facinv() const { while (this->val >= int(facs.size())) _precalculation(facs.size() * 2); return facinvs[this->val]; } ModInt doublefac() const { lint k = (this->val + 1) / 2; return (this->val & 1) ? ModInt(k * 2).fac() / (ModInt(2).pow(k) * ModInt(k).fac()) : ModInt(k).fac() * ModInt(2).pow(k); } ModInt nCr(const ModInt &r) const { return (this->val < r.val) ? 0 : this->fac() * (*this - r).facinv() * r.facinv(); } ModInt nPr(const ModInt &r) const { return (this->val < r.val) ? 0 : this->fac() * (*this - r).facinv(); } ModInt sqrt() const { if (val == 0) return 0; if (md == 2) return val; if (pow((md - 1) / 2) != 1) return 0; ModInt b = 1; while (b.pow((md - 1) / 2) == 1) b += 1; int e = 0, m = md - 1; while (m % 2 == 0) m >>= 1, e++; ModInt x = pow((m - 1) / 2), y = (*this) * x * x; x *= (*this); ModInt z = b.pow(m); while (y != 1) { int j = 0; ModInt t = y; while (t != 1) j++, t *= t; z = z.pow(1LL << (e - j - 1)); x *= z, z *= z, y *= z; e = j; } return ModInt(std::min(x.val, md - x.val)); } }; template <int md> std::vector<ModInt<md>> ModInt<md>::facs = {1}; template <int md> std::vector<ModInt<md>> ModInt<md>::facinvs = {1}; template <int md> std::vector<ModInt<md>> ModInt<md>::invs = {0}; using mint = ModInt<998244353>; template <int LEN, class S, S (*op)(S, S), class F, S (*reversal)(S), S (*mapping)(F, S), F (*composition)(F, F), F (*id)()> struct lazy_rbst { inline uint32_t _rand() { static uint32_t x = 123456789, y = 362436069, z = 521288629, w = 88675123; uint32_t t = x ^ (x << 11); x = y; y = z; z = w; return w = (w ^ (w >> 19)) ^ (t ^ (t >> 8)); } struct Node { Node *l, *r; S val, sum; F lz; bool is_reversed; int sz; Node(const S &v) : l(nullptr), r(nullptr), val(v), sum(v), lz(id()), is_reversed(false), sz(1) {} Node() : l(nullptr), r(nullptr), lz(id()), is_reversed(false), sz(0) {} template <class OStream> friend OStream &operator<<(OStream &os, const Node &n) { os << [ ; if (n.l) os << *(n.l) << , ; os << n.val << , ; if (n.r) os << *(n.r); return os << ] ; } }; using Nptr = Node *; std::array<Node, LEN> data; int d_ptr; int size(Nptr t) const { return t != nullptr ? t->sz : 0; } lazy_rbst() : d_ptr(0) {} protected: Nptr update(Nptr t) { t->sz = 1; t->sum = t->val; if (t->l) { t->sz += t->l->sz; t->sum = op(t->l->sum, t->sum); } if (t->r) { t->sz += t->r->sz; t->sum = op(t->sum, t->r->sum); } return t; } void all_apply(Nptr t, F f) { t->val = mapping(f, t->val); t->sum = mapping(f, t->sum); t->lz = composition(f, t->lz); } void _toggle(Nptr t) { auto tmp = t->l; t->l = t->r, t->r = tmp; t->sum = reversal(t->sum); t->is_reversed ^= true; } void push(Nptr &t) { _duplicate_node(t); if (t->lz != id()) { if (t->l) { _duplicate_node(t->l); all_apply(t->l, t->lz); } if (t->r) { _duplicate_node(t->r); all_apply(t->r, t->lz); } t->lz = id(); } if (t->is_reversed) { if (t->l) _toggle(t->l); if (t->r) _toggle(t->r); t->is_reversed = false; } } virtual void _duplicate_node(Nptr &) {} Nptr _make_node(const S &val) { if (d_ptr >= LEN) throw; return &(data[d_ptr++] = Node(val)); } public: Nptr new_tree() { return nullptr; } int mem_used() const { return d_ptr; } bool empty(Nptr t) const { return t == nullptr; } Nptr merge(Nptr l, Nptr r) { if (l == nullptr or r == nullptr) return l != nullptr ? l : r; if (_rand() % uint32_t(l->sz + r->sz) < uint32_t(l->sz)) { push(l); l->r = merge(l->r, r); return update(l); } else { push(r); r->l = merge(l, r->l); return update(r); } } std::pair<Nptr, Nptr> split(Nptr &root, int k) { if (root == nullptr) return std::make_pair(nullptr, nullptr); push(root); if (k <= size(root->l)) { auto p = split(root->l, k); root->l = p.second; return std::make_pair(p.first, update(root)); } else { auto p = split(root->r, k - size(root->l) - 1); root->r = p.first; return std::make_pair(update(root), p.second); } } void insert(Nptr &root, int pos, const S &x) { auto p = split(root, pos); root = merge(p.first, merge(_make_node(x), p.second)); } void erase(Nptr &root, int pos) { auto p = split(root, pos); auto p2 = split(p.second, 1); root = merge(p.first, p2.second); } void set(Nptr &root, int pos, const S &x) { auto p = split(root, pos); auto p2 = split(p.second, 1); _duplicate_node(p2.first); *p2.first = Node(x); root = merge(p.first, merge(p2.first, p2.second)); } void apply(Nptr &root, int l, int r, const F &f) { auto p = split(root, l); auto p2 = split(p.second, r - l); all_apply(p2.first, f); root = merge(p.first, merge(p2.first, p2.second)); } S prod(Nptr &root, int l, int r) { auto p = split(root, l); auto p2 = split(p.second, r - l); if (p2.first != nullptr) push(p2.first); S res = p2.first->sum; root = merge(p.first, merge(p2.first, p2.second)); return res; } S get(Nptr &root, int pos) { return prod(root, pos, pos + 1); } void reverse(Nptr &root) { _duplicate_node(root), _toggle(root); } void reverse(Nptr &root, int l, int r) { auto p2 = split(root, r); auto p1 = split(p2.first, l); reverse(p1.second); root = merge(merge(p1.first, p1.second), p2.second); } void assign(Nptr &root, const std::vector<S> &init) { d_ptr = 0; int N = init.size(); root = N ? _assign_range(0, N, init) : new_tree(); } Nptr _assign_range(int l, int r, const std::vector<S> &init) { if (r - l == 1) { Nptr t = _make_node(init[l]); return update(t); } return merge(_assign_range(l, (l + r) / 2, init), _assign_range((l + r) / 2, r, init)); } void dump(Nptr &t, std::vector<S> &vec) { if (t == nullptr) return; push(t); dump(t->l, vec); vec.push_back(t->val); dump(t->r, vec); } void re_alloc(Nptr &root) { std::vector<S> mem; dump(root, mem); assign(root, mem); } }; using S = int; S op(S l, S r) { return l > r ? l : r; } using F = pair<bool, int>; S reversal(S x) { return x; } S mapping(F f, S x) { return f.first ? f.second + x : x; } F composition(F f, F g) { if (!f.first) return g; if (!g.first) return f; return {true, f.second + g.second}; } F id() { return {false, 0}; } lazy_rbst<2000000, S, op, F, reversal, mapping, composition, id> tree; mint solve() { int N, M; cin >> N >> M; vector<pint> xy(M); for (auto &[x, y] : xy) cin >> x >> y; auto root = tree.new_tree(); tree.assign(root, {0}); for (auto [x, y] : xy) { const int len = root->sz; int lo = 1, hi = len + 1; while (hi - lo > 1) { int c = (lo + hi) / 2; (tree.prod(root, 0, c) < y - 1 ? lo : hi) = c; } if (lo == len) { tree.insert(root, len, y); } else if (tree.get(root, lo) == y - 1) { tree.apply(root, lo, len, {true, 1}); } else { tree.apply(root, lo, len, {true, 1}); tree.insert(root, lo, y); } } int sz = root->sz; if (tree.get(root, 0) == 0) sz--; sz = N - 1 - sz; return mint(N + sz).nCr(sz); } int main() { int T; cin >> T; while (T--) cout << solve() << n ; }
|
#include <bits/stdc++.h> using namespace std; int T, n, m, sum, tot; struct P { int val, x, y; } a[500]; struct R { int x, y; } b[10]; bool cmp1(const P& a, const P& b) { return a.val > b.val; } bool cmp2(const R& a, const R& b) { return a.y > b.y; } bool Judge(int i, int j, int k, int u) { int num[5], tmp = 1; memset(num, 0, sizeof(num)); b[1].x = a[i].x, b[1].y = a[i].y; b[2].x = a[j].x, b[2].y = a[j].y; b[3].x = a[k].x, b[3].y = a[k].y; b[4].x = a[u].x, b[4].y = a[u].y; sort(b + 1, b + 4 + 1, cmp2); num[1]++; for (int l = 2; l <= 4; l++) if (b[l].y == b[l - 1].y) num[tmp]++; else num[tmp + 1]++, tmp++; if (num[1] > num[2]) swap(num[1], num[2]); if (tmp != 2 || num[1] == 1 && num[2] == 3) return true; int t1 = abs(b[1].x - b[2].x), t2 = abs(b[3].x - b[4].x); if (t1 < t2) swap(t1, t2); if (t1 == 3 && t2 == 2 || t1 == 2 && t2 == 1) return false; return true; } int main() { scanf( %d , &T); while (T--) { sum = tot = 0; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { scanf( %d , &a[++tot].val); a[tot].x = i; a[tot].y = j; } sort(a + 1, a + tot + 1, cmp1); if (n <= 3 || n == 4 && m == 1) { for (int i = 1; i <= n; i++) sum += a[i].val; printf( %d n , sum); continue; } for (int i = 1; i <= 8; i++) for (int j = i + 1; j <= 8; j++) for (int k = j + 1; k <= 8; k++) for (int u = k + 1; u <= 8; u++) if (Judge(i, j, k, u)) sum = max(sum, a[i].val + a[j].val + a[k].val + a[u].val); printf( %d n , sum); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DECAP_BEHAVIORAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:12:26 11/03/2014
// Design Name:
// Module Name: spi_bonus
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_bonus(clk, reset, din, dout, wren, rden, addr, mosi, miso, sclk);
input clk, reset, wren, rden;
input [7:0] din;
output [7:0] dout;
input [1:0] addr;
output mosi; //serial data out
input miso; //serial data in
output sclk; //SPI clock
`define TXreg 2'b00
`define RXreg 2'b01
`define control 2'b10 //8bit
`define TXFULL control[0]
`define DATARDY control[1]
`define WAIT 2'b00
`define SHIFT 2'b01
`define SHIFT1 2'b10
`define WRITE 2'b11
reg [7:0] control, shiftin, shiftout, dout;
reg wr_tx, wr_rx, rd_tx, sout, sin, spi, wr_control, enspi, clr_count, rd_rx;
reg [6:0] spiclk;
reg [1:0] pstate, nstate;
reg [3:0] counter;
wire rx_empty, tx_full, tx_empty;
wire [7:0] txout, dout_rx;
assign mosi = shiftout[7];
assign sclk = spi;
txreg txfifo(
.clk (clk),
.rst (reset),
.din (din),
.wr_en (wr_tx),
.rd_en (rd_tx),
.dout (txout),
.full (tx_full),
.empty (tx_empty)
);
txreg rxfifo(
.clk (clk),
.rst (reset),
.din (shiftin),
.wr_en (wr_rx),
.rd_en (rd_rx),
.dout (dout_rx),
.full (rx_full),
.empty (rx_empty)
);
//1MHZ clock
always @(posedge clk or posedge reset) begin
if(reset) begin
spiclk <= 6'b00000;
spi <= 0;
end
else begin
begin
if(enspi) begin
if(spiclk >= 0 & spiclk <= 24) begin
spi <= 1;
spiclk <= spiclk + 1;
end
if(spiclk >=25 & spiclk <= 49) begin
spi <= 0;
spiclk <= spiclk + 1;
end
if(spiclk == 50)begin
spiclk <= 6'b00000;
end
end
else begin
spiclk <= 5'b00000;
spi <= 0;
end
end
end
end
//read mux
always @* begin
dout = 8'b00000000;
rd_rx = 0;
case(addr)
`RXreg: begin
if(rden)
rd_rx = 1;
dout = dout_rx;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
always @* begin
wr_tx = 0;
case(addr)
`TXreg: begin
if(wren)
wr_tx = 1;
end
endcase
end
//control reg
always @(posedge clk or posedge reset) begin
if(reset)
control <= 8'b00000000;
else begin
`DATARDY <= ~rx_empty;
`TXFULL <= tx_full;
if(wr_control)
control <= din;
end
end
//counter
always@(posedge spi or posedge reset)begin
if(reset)
counter <= 4'b0000;
else begin
if(enspi) counter <= counter + 1;
if(counter >= 8) counter <= 4'b0001;
end
end
////shift out reg
always @(posedge clk or posedge reset) begin
if(reset)
shiftout <= 8'b00000000;
else begin
if(sout)
shiftout <= {shiftout[6:0], 1'b0};
if(rd_tx)
shiftout <= txout;
end
end
// shift in reg
always @(posedge clk or posedge reset) begin
if(reset)
shiftin <= 8'b00000000;
else begin
if(sin)
shiftin <= {shiftin[6:0], miso};
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if(reset) pstate = `WAIT;
else pstate = nstate;
end
// fsm
always @* begin
rd_tx = 0; sout = 0;
enspi = 0; clr_count = 0;
wr_rx = 0; sin = 0;
nstate = pstate;
case(pstate)
`WAIT: begin
if(~tx_empty) begin
rd_tx = 1;
enspi = 1;
nstate = `SHIFT;
end
end
`SHIFT: begin
enspi = 1;
if(~spi) begin
nstate = `SHIFT1;
sin = 1;
if(counter == 4'b1000) begin
nstate = `WRITE;
end
end
end
`SHIFT1: begin
enspi = 1;
if(spi) begin
sout = 1;
nstate = `SHIFT;
end
end
`WRITE: begin
wr_rx = 1;
nstate = `WAIT;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O31A_PP_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int a[11][5]; bool ok(int l, int j, int k) { int i, an = 0; for (i = 0; i < 5; i++) { an = an + (a[j][i] - a[l][i]) * (a[k][i] - a[l][i]); } if (an > 0) return false; return true; } int main() { ios::sync_with_stdio(false); int i, j, k, n; cin >> n; if (n > 11) { n *= 5; while (n--) cin >> i; cout << 0; } else { for (i = 0; i < n; i++) cin >> a[i][0] >> a[i][1] >> a[i][2] >> a[i][3] >> a[i][4]; vector<int> v; k = n; j = n; for (i = 0; i < n; i++) { k = n; for (j = 0; j < n && k == n; j++) for (k = j + 1; k < n; k++) { if (!ok(i, j, k)) { break; } } if (j == n && k == n) v.push_back(i + 1); } cout << v.size() << endl; for (i = 0; i < v.size(); i++) cout << v[i] << << endl; ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_LP_V
`define SKY130_FD_SC_LP__A311O_LP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_lp (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_LP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, count1 = 0, count2 = 0, sum = 0; scanf( %d , &n); vector<pair<int, int> > v1; vector<pair<int, int> > v2; for (int i = 0; i < n; i++) { int x, a; scanf( %d %d , &x, &a); if (x < 0) { v1.push_back(make_pair(x, a)); count1++; } else { v2.push_back(make_pair(x, a)); count2++; } } sort(v1.begin(), v1.end()); reverse(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); vector<pair<int, int> >::iterator it1 = v1.begin(); vector<pair<int, int> >::iterator it2 = v2.begin(); vector<pair<int, int> >::iterator it3 = v1.end(); vector<pair<int, int> >::iterator it4 = v2.end(); if (count1 > count2) { while (it1 != v1.end()) { sum += it1->second; it1++; if (it2 != v2.end()) { sum += it2->second; it2++; } else break; } } else if (count1 < count2) { while (it2 != v2.end()) { sum += it2->second; it2++; if (it1 != v1.end()) { sum += it1->second; it1++; } else break; } } else if (count1 == count2) { if ((it3->second) > (it4->second)) { while (it1 != v1.end()) { sum += it1->second; it1++; sum += it2->second; it2++; } } else { while (it2 != v2.end()) { sum += it2->second; it2++; sum += it1->second; it1++; } } } printf( %d n , sum); }
|
module wildcard_tcam
#(
parameter CMP_WIDTH = 32,
parameter DEPTH = 32,
parameter DEPTH_BITS = 5,
parameter ENCODE = 0,
parameter CURRENT_TABLE_ID = 0
)(
input clk,
input reset,
input [CMP_WIDTH - 1 : 0] cmp_din,
output busy,
output match,
output reg [DEPTH_BITS - 1 : 0] match_addr,
input cmp_req,
// output reg[DEPTH - 1 : 0] match_addr,
input we,
input [`PRIO_WIDTH -1:0] tcam_addr,
output reg [CMP_WIDTH-1:0]tcam_data_out,
output reg [CMP_WIDTH-33:0] tcam_data_mask_out,
input [CMP_WIDTH-1:0]tcam_data_in,
input [CMP_WIDTH-33:0]tcam_data_mask_in
/*input [CMP_WIDTH-1:0]tcam_data_in,
input [CMP_WIDTH-33:0]tcam_data_mask_in*/
);
wire [DEPTH - 1 : 0] match_addr_unencoded;
reg [DEPTH - 1 : 0] match_addr_unencoded_reg;
wire [CMP_WIDTH - 1 : 0] stage1[DEPTH - 1 : 0];
wire [CMP_WIDTH - 1 : 0] stage2[DEPTH - 1 : 0];
reg [CMP_WIDTH - 1 : 0] cam_data[DEPTH - 1 : 0];
reg [CMP_WIDTH - 33 : 0] cam_data_mask[DEPTH - 1 : 0];
reg [DEPTH_BITS-1:0] prio;
wire [DEPTH - 1 : 0] match_addr_tmp;
reg [7:0] reg_addr_actions_d;
reg [7:0] clear_count;
always@(*)
if(tcam_addr < DEPTH)
begin
tcam_data_mask_out=cam_data_mask[tcam_addr] ;
tcam_data_out=cam_data[tcam_addr] ;
end
else begin
tcam_data_mask_out=0;
tcam_data_out=0;
end
always@(posedge clk)
if(reset)
clear_count<=0;
else if(clear_count==DEPTH)
clear_count<=clear_count;
else clear_count<=clear_count+1;
always@(posedge clk)
if(clear_count<DEPTH)
begin
cam_data[clear_count][CMP_WIDTH-1]<=1;
cam_data[clear_count][CMP_WIDTH-2:0]<=0;
cam_data_mask[clear_count]<=0;
end
else if(we)
begin
/*if(CMP_WIDTH<=32)
case(tcam_addr[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS] )
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:cam_data_mask[tcam_addr[7+DEPTH_BITS:8]][CMP_WIDTH-1:0] <=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:cam_data[tcam_addr[7+DEPTH_BITS:8]][CMP_WIDTH-1:0] <=tcam_data_in;
endcase
else if(CMP_WIDTH<=64)
case(tcam_addr[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS] )
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:cam_data_mask[tcam_addr[7+DEPTH_BITS:8]][31:0] <=tcam_data_in;
//`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG:cam_data_mask[tcam_addr[7+DEPTH_BITS:8]][CMP_WIDTH-1:32]<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:cam_data[tcam_addr[7+DEPTH_BITS:8]][31:0] <=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG:cam_data[tcam_addr[7+DEPTH_BITS:8]][CMP_WIDTH-1:32]<=tcam_data_in;
endcase
else if(CMP_WIDTH<=96)*/
/*case(tcam_addr[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS] )
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:cam_data_mask[tcam_addr[7+DEPTH_BITS:8]][31:0] <=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG:cam_data_mask[tcam_addr[7+DEPTH_BITS:8]][63:32]<=tcam_data_in;
//`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_2_REG:cam_data_mask[tcam_addr[7+DEPTH_BITS:8]][CMP_WIDTH-1:64]<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:cam_data[tcam_addr[7+DEPTH_BITS:8]][31:0] <=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG:cam_data[tcam_addr[7+DEPTH_BITS:8]][63:32]<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_2_REG:cam_data[tcam_addr[7+DEPTH_BITS:8]][CMP_WIDTH-1:64]<=tcam_data_in; */
cam_data_mask[tcam_addr] <= tcam_data_mask_in;
cam_data[tcam_addr] <= tcam_data_in;
//endcase
end
//////////////////////////////////// CMP_DATA /////////////////////////////////////////
/* always@(*)
if(reset) cam_data_tmp[31:0]=0;
else if(cur_st==WRITE_PRE) cam_data_tmp[31:0]=cam_data[prio][31:0];
else if(cur_st==WRITE && reg_addr_actions==8'h30) cam_data_tmp[31:0]=reg_data;
else cam_data_tmp[31:0]=cam_data_tmp[31:0];
always@(*)
if(reset) cam_data_tmp[63:32]=0;
else if(cur_st==WRITE_PRE) cam_data_tmp[63:32]=cam_data[prio][63:32];
else if(cur_st==WRITE && reg_addr_actions==8'h34) cam_data_tmp[63:32]=reg_data;
else cam_data_tmp[63:32]=cam_data_tmp[63:32];
always@(*)
if(reset) cam_data_tmp[95:64]=0;
else if(cur_st==WRITE_PRE) cam_data_tmp[95:64]=cam_data[prio][95:64];
else if(cur_st==WRITE && reg_addr_actions==8'h38) cam_data_tmp[95:64]=reg_data;
else cam_data_tmp[95:64]=cam_data_tmp[95:64];
always@(*)
if(reset) cam_data_mask_tmp[31:0]=0;
else if(cur_st==WRITE_PRE) cam_data_mask_tmp[31:0]=cam_data_mask[prio][31:0];
else if(cur_st==WRITE && reg_addr_actions==8'h40) cam_data_mask_tmp[31:0]=reg_data;
else cam_data_mask_tmp[31:0]=cam_data_mask_tmp[31:0];
always@(*)
if(reset) cam_data_mask_tmp[63:32]=0;
else if(cur_st==WRITE_PRE) cam_data_mask_tmp[63:32]=cam_data_mask[prio][63:32];
else if(cur_st==WRITE && reg_addr_actions==8'h44) cam_data_mask_tmp[31:0]=reg_data;
else cam_data_mask_tmp[63:32]=cam_data_mask_tmp[63:32];
always@(*)
if(reset) cam_data_mask_tmp[95:64]=0;
else if(cur_st==WRITE_PRE) cam_data_mask_tmp[95:64]=cam_data_mask[prio][95:64];
else if(cur_st==WRITE && reg_addr_actions==8'h48) cam_data_mask_tmp[95:64]=reg_data;
else cam_data_mask_tmp[95:64]=cam_data_mask_tmp[95:64];*/
////////////////////////////////////////////////////////////////////////////////////////////////
reg [CMP_WIDTH - 1 : 0] cmp_din_reg;
always@(posedge clk)
if(reset)
cmp_din_reg<=0;
else if(cmp_req)
cmp_din_reg<=cmp_din;
genvar n;
generate
for(n = DEPTH-1; n >= 0; n = n - 1) begin : gen_cmp
assign stage1[n] = cmp_din_reg ^ ~cam_data[n];
assign stage2[n] = stage1[n] | cam_data_mask[n];
assign match_addr_tmp[n]=&stage2[n];
end
endgenerate
integer i;
always @(*)
begin match_addr=0;
if(|match_addr_tmp)
begin
for (i = 0; i <= DEPTH-1; i = i+1) begin
if (match_addr_tmp[i])
match_addr = i[DEPTH_BITS-1:0];
/*case(1)
match_addr_tmp[i]:match_addr = i[DEPTH_BITS-1:0];
//default:match_addr = 0;
endcase*/
end
end
end
reg cmp_req_d1;
reg cmp_req_d2;
reg cmp_req_d3;
always@(posedge clk)
if(reset)
begin
cmp_req_d1<=0;
cmp_req_d2<=0;
cmp_req_d3<=0;
end
else
begin
cmp_req_d1<=cmp_req;
cmp_req_d2<=cmp_req_d1;
cmp_req_d3<=cmp_req_d2;
end
assign busy = 0;
assign match = (| match_addr_tmp) && cmp_req_d3;
endmodule
|
//-----------------------------------------------------------------------------
//-- Secuenciador de 4 estados usando un multiplexor de 4 a 1
//-- (C) BQ. August 2015. Written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- License GPL
//-----------------------------------------------------------------------------
//-- Entrada: reloj
//-- Salida: datos a conectar en los leds
module mux4(input wire clk, output reg [3:0] data);
//-- Parametros del secuenciador:
parameter NP = 23; //-- Bits del prescaler
parameter VAL0 = 4'b0000; //-- Valor secuencia 0
parameter VAL1 = 4'b1010; //-- Valor secuencia 1
parameter VAL2 = 4'b1111; //-- Valor secuencia 2
parameter VAL3 = 4'b0101; //-- Valor secuencia 3
//-- Cables para las 5 entradas del multiplexor
wire [3:0] val0;
wire [3:0] val1;
wire [3:0] val2;
wire [3:0] val3;
wire [1:0] sel; //-- Dos bits de selección
//-- Contador de 2 bits
reg [1:0] count = 0;
wire clk_pres; //-- Reloj una vez pasado por prescaler
//-- Por las entradas del mux cableamos los datos de entrada
assign val0 = VAL0;
assign val1 = VAL1;
assign val2 = VAL2;
assign val3 = VAL3;
//-- Implementación del multiplexor de 4 a 1
always@*
case (sel)
0 : data <= val0;
1 : data <= val1;
2 : data <= val2;
3 : data <= val3;
default : data <= 0;
endcase
//-- Contador de 2 bits para realizar la seleccion de la fuente de datos
always @(posedge(clk_pres))
count <= count + 1;
//-- El contador esta conectado a la entrada sel del mux
assign sel = count;
//-- Presaler que controla el incremento del contador para la selección
prescaler #(.N(NP))
PRES (
.clk_in(clk),
.clk_out(clk_pres)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; pair<int, int> a[200002 + 1]; int min(int a, int b) { return a > b ? b : a; } int abs(int a) { return a < 0 ? -a : a; } int main() { cin >> N; N *= 2; int b; for (int i = 0; i < N; i++) { cin >> b; a[i] = {b, i}; } sort(a, a + N); long long ans = a[0].second + a[1].second; for (int i = 2; i < N; i += 2) { ans += min(abs(a[i - 2].second - a[i].second) + abs(a[i - 1].second - a[i + 1].second), abs(a[i - 1].second - a[i].second) + abs(a[i - 2].second - a[i + 1].second)); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxsize = 100; int n, m; bool visited[maxsize][maxsize]; string v, h; int go[][2] = {1, 0, -1, 0, 0, -1, 0, 1}; map<char, int> dir; int cnt; void dfs(int row, int col) { if (visited[row][col]) return; visited[row][col] = true; cnt++; int n_row = -1, n_col = -1; n_row = row + go[dir[h[row]]][0]; n_col = col + go[dir[h[row]]][1]; if (n_col >= 0 && n_col < m) { dfs(n_row, n_col); } n_row = row + go[dir[v[col]]][0]; n_col = col + go[dir[v[col]]][1]; if (n_row >= 0 && n_row < n) { dfs(n_row, n_col); } } int main(int argc, char* argv[]) { dir[ > ] = 3; dir[ < ] = 2; dir[ ^ ] = 1; dir[ v ] = 0; while (scanf( %d%d , &n, &m) != EOF) { cin >> h >> v; bool flag = true; for (int ii = 0; ii < n && flag; ii++) { for (int jj = 0; jj < m && flag; jj++) { memset(visited, false, sizeof(visited)); cnt = 0; dfs(ii, jj); if (cnt != n * m) flag = false; } } if (cnt == n * m) printf( YES n ); else printf( NO n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_TB_V
`define SKY130_FD_SC_LP__SREGSBP_TB_V
/**
* sregsbp: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sregsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg ASYNC;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
ASYNC = 1'bX;
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 ASYNC = 1'b0;
#40 D = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 ASYNC = 1'b1;
#200 D = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 ASYNC = 1'b0;
#360 D = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 D = 1'b1;
#640 ASYNC = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 D = 1'bx;
#800 ASYNC = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sregsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .ASYNC(ASYNC), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_TB_V
|
#include <bits/stdc++.h> using namespace std; int a[4] = {1, 2, 3, 5}; int main(void) { int n, k; scanf( %d%d , &n, &k); printf( %d n , (5 + 6 * (n - 1)) * k); for (int i = 0; i < n; i++) { printf( %d %d %d %d n , (a[0] + 6 * i) * k, (a[1] + 6 * i) * k, (a[2] + 6 * i) * k, (a[3] + 6 * i) * k); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
|
`include "../network_params.h"
module rect_linear_tb;
reg clock;
reg reset;
reg [`NN_BITWIDTH:0] rect_in;
wire [`NN_BITWIDTH:0] rect_out;
rect_linear dut(
.clock(clock),
.reset(reset),
.rect_in(rect_in),
.rect_out(rect_out)
);
initial begin
clock = 1'b0;
reset = 1'b0;
rect_in = 1'b0;
end
always
#5 clock = !clock;
initial begin
#20 reset = 1'b1;
#20 reset = 1'b0;
#20
reset = 1'b1;
rect_in = $random;
# 10
if(rect_in[`NN_BITWIDTH] == 1'b1 && rect_out == `NN_WIDTH'd0) begin
$display ("Pass");
end else if(rect_in[`NN_BITWIDTH] == 1'b0 && rect_out == rect_in) begin
$display ("Pass");
end else begin
$display ("Fail!!!");
$display ("rect_in: %d", rect_in);
$display ("rect_out: %d", rect_out);
end
#20
rect_in = $random;
# 10
if(rect_in[`NN_BITWIDTH] == 1'b1 && rect_out == `NN_WIDTH'd0) begin
$display ("Pass");
end else if(rect_in[`NN_BITWIDTH] == 1'b0 && rect_out == rect_in) begin
$display ("Pass");
end else begin
$display ("Fail!!!");
$display ("rect_in: %d", rect_in);
$display ("rect_out: %d", rect_out);
end
#20
rect_in = $random;
# 10
if(rect_in[`NN_BITWIDTH] == 1'b1 && rect_out == `NN_WIDTH'd0) begin
$display ("Pass");
end else if(rect_in[`NN_BITWIDTH] == 1'b0 && rect_out == rect_in) begin
$display ("Pass");
end else begin
$display ("Fail!!!");
$display ("rect_in: %d", rect_in);
$display ("rect_out: %d", rect_out);
end
# 100
$finish;
end
endmodule
|
/*
SD card interface
$0 RW - RDY|XXX|XXX|XXX|XXX|XXX|XXX|SS0
$1 RW - DATA
$2 RW - PRESCALER
RDY - R- IO ready
SS0 - select SPI device 0
*/
module sdcardio (
input wire clk,
input wire rst,
input wire [2:0] AD,
input wire [7:0] DI,
output reg [7:0] DO,
input wire rw,
input wire cs,
// output wire irq,
input wire clk_in,
output wire mosi,
output reg msck,
input wire miso
);
reg [7:0] spics_reg;
reg [7:0] config_reg;
reg [7:0] rx_data;
reg [7:0] tx_data;
reg [7:0] prescaler;
reg start;
reg [7:0] shifted_tx_data;
reg [3:0] bit_counter;
reg [7:0] scale_counter;
wire data_ready = ((bit_counter == 0) && (!msck))?1'b1:1'b0;
always @ (posedge clk) begin
if (rst) begin
config_reg <= 8'b00000001;
tx_data <= 8'b11111111;
prescaler <= 0;
start <= 0;
end else begin
if (cs) begin
if (rw) begin
case (AD[2:0])
3'b000: DO <= {data_ready, 3'b0, config_reg[3:0]};
3'b001: begin
DO <= rx_data;
end
3'b010: DO <= prescaler;
3'b011: DO <= spics_reg;
endcase
end else begin
case (AD[2:0])
3'b000: config_reg <= DI;
3'b001: begin
tx_data <= DI;
start <= 1'b1;
end
3'b010: prescaler <= DI;
3'b011: spics_reg <= DI;
endcase
end
end else begin
if (!data_ready) start <= 1'b0;
end
end
end
assign mosi = ((bit_counter == 0) && (!msck))?1'b1:shifted_tx_data[7];
always @ (posedge clk_in) begin
if (rst) begin
msck <= 0;
rx_data <= 8'b11111111;
scale_counter <= 0;
end else if (start) begin
shifted_tx_data <= tx_data;
bit_counter <= 8;
end else begin
if (bit_counter != 0) begin
if (scale_counter == prescaler) begin
scale_counter <= 0;
msck <= ~msck;
if (msck) begin
shifted_tx_data <= {shifted_tx_data[6:0], 1'b1};
rx_data <= {rx_data[6:0], miso};
bit_counter <= bit_counter - 1'b1;
end
end else scale_counter <= scale_counter + 1'b1;
end else msck <= 0;
end
end
endmodule
|
`timescale 1ns / 1ns
/* verilator lint_off INITIALDLY */
///////////////////////////////////
// MulA
///////////////////////////////////
module MulA(
input wire sysclock,
input wire [31:0] inputMulA,
output reg [63:0] product
);
initial begin
product <= 64'd0;
end
always @ (posedge sysclock) begin
product <= (inputMulA * inputMulA);
end
endmodule
///////////////////////////////////
// MulB
///////////////////////////////////
module MulB(
input wire sysclock,
input wire [31:0] inputMulB,
output reg [63:0] product
);
initial begin
product <= 64'd0;
end
always @ (posedge sysclock) begin
product <= (inputMulB * inputMulB);
end
endmodule
///////////////////////////////////
// BRAM
///////////////////////////////////
module BRAM(
input wire sysclock,
input wire [4:0] address,
input wire [7:0] datain,
output reg [7:0] dataout,
input wire write_enable
);
reg [7:0] mem [0:31];
initial begin
dataout <= 8'd0;
end
always @ (posedge sysclock) begin
if (write_enable) begin
mem[address] <= datain;
end
else begin
dataout <= mem[address];
end
end
endmodule
///////////////////////////////////
// IOB
///////////////////////////////////
module IOB(
input wire sysclock,
input wire [31:0] a,
input wire b,
output reg e
);
reg [3:0] fsmstate;
initial begin
e <= 1'd0;
fsmstate <= 4'd0;
end
always @ (posedge sysclock) begin
case (fsmstate)
4'h0: begin
fsmstate <= 4'h1;
e <= 1'h0;
end
4'h1: begin
fsmstate <= 4'h2;
e <= 1'h1;
end
4'h2: begin
fsmstate <= 4'h3;
e <= 1'h1;
end
4'h3: begin
fsmstate <= 4'h1;
e <= 1'h0;
end
endcase
end
endmodule
///////////////////////////////////
// Module1
///////////////////////////////////
module Module1(
input wire sysclock,
output reg [31:0] x,
output reg [31:0] y
);
reg [31:0] a;
reg [31:0] b;
wire e;
IOB __IOB (sysclock, x, y[0], e);
initial begin
a <= 32'd0;
b <= 32'd0;
x <= 32'd0;
y <= 32'd0;
end
always @ (posedge sysclock) begin
if (y > x) begin
x <= (x + 32'h1);
y <= (y + 32'h2);
a <= {16'd0,((((x - y))>>0)&16'hffff)};
b <= (y - x);
end
else begin
x <= (x + 32'h1);
y <= (y + 32'h4);
a <= (y - x);
b <= (x - y);
end
end
endmodule
///////////////////////////////////
// Top
///////////////////////////////////
module Top(
input wire sysclock,
output reg lineout
);
wire [31:0] gcdX;
wire [31:0] gcdY;
reg [31:0] o;
reg [31:0] o2;
wire [63:0] resA;
wire [63:0] resB;
reg [4:0] romaddr;
wire [7:0] romdatain;
reg [7:0] romdataout;
reg romwe;
MulA __MulA (sysclock, o, resA);
MulB __MulB (sysclock, o2, resB);
BRAM __BRAM (sysclock, romaddr, romdataout, romdatain, romwe);
Module1 __Module1 (sysclock, gcdX, gcdY);
initial begin
lineout <= 1'd0;
o <= 32'd0;
o2 <= 32'd0;
romaddr <= 5'd0;
romdataout <= 8'd0;
romwe <= 1'd0;
end
always @ (posedge sysclock) begin
o <= ((((o + 32'h1))>>0)&32'hffffffff);
romaddr <= ((((o + 32'h1))>>0)&5'h1f);
end
always @ (posedge sysclock) begin
lineout <= romdatain[0];
o2 <= (o + 32'h3);
end
endmodule
///////////////////////////////////
// TestBench
///////////////////////////////////
module TestBench(
);
wire lineout;
reg sysclock;
Top __Top (sysclock, lineout);
initial begin
sysclock <= 1'd0;
end
// begin testbench node
/* verilator lint_off STMTDLY */
initial begin
#0 $dumpfile("test.vcd");
#0 $dumpvars;
#1000 $finish;
end
always begin
#5 sysclock = !sysclock;
end
/* verilator lint_on STMTDLY */
// end testbench node
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
|
//ÊýÂë¹Ü¼Æ·ÖÄ£¿é
module Seg_Display
(
input clk,
input rst,
input add_cube,
inout [1:0]game_status,
output reg[15:0]point,
output reg[7:0]seg_out,
output reg[3:0]sel
);
localparam RESTART = 2'b00;
reg[31:0]clk_cnt;
always@(posedge clk or posedge rst)
begin
if(!rst)
begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else if (game_status == RESTART) begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else
begin
if(clk_cnt <= 20_0000)
begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 5_0000)
begin
sel <= 4'b0111;
case(point[3:0])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 10_0000)
begin
sel <= 4'b1011;
case(point[7:4])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 15_0000)
begin
sel <= 4'b1101;
case(point[11:8])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 20_0000)
begin
sel <= 4'b1110;
case(point[15:12])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
end
else
clk_cnt <= 0;
end
end
reg addcube_state;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
point <= 0;
addcube_state <= 0;
end
else if (game_status == RESTART) begin
point <= 0;
addcube_state <= 0;
end
else begin
case(addcube_state)
0: begin
if(add_cube) begin
if(point[3:0] < 9)
point[3:0] <= point[3:0] + 1;
else begin
point[3:0] <= 0;
if(point[7:4] < 9)
point[7:4] <= point[7:4] + 1;
else begin
point[7:4] <= 0;
if(point[11:8] < 9)
point[11:8] <= point[11:8] + 1;
else begin
point[11:8] <= 0;
point[15:12] <= point[15:12] + 1;
end
end
end
addcube_state <= 1;
end
end
1: begin
if(!add_cube)
addcube_state <= 0;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFRBP_PP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRBP_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output [ 7:0 ] z
);
wire [7:0] z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output [ 7:0 ] z
);
wire [7:0] zi;
reg [7:0] z;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
#include <bits/stdc++.h> using namespace std; long long dp[2]; void solve() { long long n; cin >> n; for (int i = 0; i < n; i++) { dp[i % 2] = dp[i % 2] + dp[!(i % 2)] + 1; if (dp[i % 2] > 1000000007) dp[i % 2] %= 1000000007; } cout << (dp[0] + dp[1] + 1000000007) % (1000000007); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; solve(); }
|
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