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platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/AKL3ILG7S7RH6P54PDHJK7ZCG4HRKZQ4HFSVHSDT4K4LCS26KR3A/triton_poi_fused_view_5.llir

@@ -0,0 +1,49 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+define ptx_kernel void @triton_poi_fused_view_5(ptr addrspace(1) %0, i32 %1, ptr addrspace(1) readnone captures(none) %2) local_unnamed_addr !dbg !6 {
+  %4 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %5 = shl i32 %4, 9, !dbg !10
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %7 = shl i32 %6, 1, !dbg !11
+  %8 = and i32 %7, 510, !dbg !11
+  %9 = or disjoint i32 %8, %5, !dbg !12
+  %10 = icmp slt i32 %9, %1, !dbg !13
+  %11 = sext i32 %9 to i64, !dbg !14
+  %12 = getelementptr bfloat, ptr addrspace(1) %0, i64 %11, !dbg !14
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 0, ptr addrspace(1) %12, i1 %10) #1, !dbg !15
+  ret void, !dbg !16
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py", directory: "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws")
+!4 = !{ptr @triton_poi_fused_view_5, !"reqntidx", i32 256}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_poi_fused_view_5", linkageName: "triton_poi_fused_view_5", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 19, column: 28, scope: !6)
+!10 = !DILocation(line: 19, column: 33, scope: !6)
+!11 = !DILocation(line: 20, column: 36, scope: !6)
+!12 = !DILocation(line: 20, column: 23, scope: !6)
+!13 = !DILocation(line: 21, column: 21, scope: !6)
+!14 = !DILocation(line: 24, column: 25, scope: !6)
+!15 = !DILocation(line: 24, column: 36, scope: !6)
+!16 = !DILocation(line: 24, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/AKL3ILG7S7RH6P54PDHJK7ZCG4HRKZQ4HFSVHSDT4K4LCS26KR3A/triton_poi_fused_view_5.ttgir

@@ -0,0 +1,28 @@
+#blocked = #ttg.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [8], order = [0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":18:0)
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 8 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_view_5(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":18:0), %arg1: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<512xbf16, #blocked> loc(#loc1)
+    %c512_i32 = arith.constant 512 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c512_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<512xi32, #blocked> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<512xi32, #blocked> loc(#loc5)
+    %5 = tt.splat %arg1 : i32 -> tensor<512xi32, #blocked> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<512xi32, #blocked> loc(#loc6)
+    %7 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc7)
+    %8 = tt.addptr %7, %4 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc7)
+    tt.store %8, %cst, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc8)
+    tt.return loc(#loc9)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":24:25)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":24:36)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":24:4)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/AKL3ILG7S7RH6P54PDHJK7ZCG4HRKZQ4HFSVHSDT4K4LCS26KR3A/triton_poi_fused_view_5.ttir

@@ -0,0 +1,27 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":18:0)
+module {
+  tt.func public @triton_poi_fused_view_5(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":18:0), %arg1: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<512xbf16> loc(#loc1)
+    %c512_i32 = arith.constant 512 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c512_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<512xi32> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<512xi32> loc(#loc5)
+    %5 = tt.splat %arg1 : i32 -> tensor<512xi32> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<512xi32> loc(#loc6)
+    %7 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>> loc(#loc7)
+    %8 = tt.addptr %7, %4 : tensor<512x!tt.ptr<bf16>>, tensor<512xi32> loc(#loc7)
+    tt.store %8, %cst, %6 : tensor<512x!tt.ptr<bf16>> loc(#loc8)
+    tt.return loc(#loc9)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":24:25)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":24:36)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ws/cwshqobvu77zaab5g5spahb6m75awzcikihngr3d5z5rkxeufy4k.py":24:4)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/__grp__triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_3.ttir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.ttir", "triton_red_fused__to_copy_mean_pow_3.ttgir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.ttgir", "triton_red_fused__to_copy_mean_pow_3.llir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.llir", "triton_red_fused__to_copy_mean_pow_3.ptx": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.ptx", "triton_red_fused__to_copy_mean_pow_3.cubin": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.cubin", "triton_red_fused__to_copy_mean_pow_3.json": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.json"}}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"hash": "1340b11cd7f9c2dfa685eb782190021d0520f9e13dbec4359d70e7e2ea9cbecd", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 256, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_mean_pow_3"}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/CNALCHGX7HBN7JUF5N4CDEACDUCSB6PBHW7MINM5ODT6F2U4X3GQ/triton_red_fused__to_copy_mean_pow_3.ptx

@@ -0,0 +1,553 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_mean_pow_3 // -- Begin function triton_red_fused__to_copy_mean_pow_3
+.extern .shared .align 16 .b8 global_smem[];
+                                        // @triton_red_fused__to_copy_mean_pow_3
+.visible .entry triton_red_fused__to_copy_mean_pow_3(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_1,
+	.param .u32 triton_red_fused__to_copy_mean_pow_3_param_2,
+	.param .u32 triton_red_fused__to_copy_mean_pow_3_param_3,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_4
+)
+.reqntid 128, 1, 1
+{
+	.reg .pred 	%p<24>;
+	.reg .b16 	%rs<5>;
+	.reg .b32 	%r<106>;
+	.reg .f32 	%f<26>;
+	.reg .b64 	%rd<30>;
+	.loc	1 18 0                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:18:0
+
+// %bb.0:
+	ld.param.u32 	%r8, [triton_red_fused__to_copy_mean_pow_3_param_2];
+	ld.param.u64 	%rd5, [triton_red_fused__to_copy_mean_pow_3_param_1];
+	ld.param.u64 	%rd4, [triton_red_fused__to_copy_mean_pow_3_param_0];
+$L__tmp0:
+	.loc	1 22 28                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:22:28
+	mov.u32 	%r1, %ctaid.x;
+	.loc	1 22 33                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:22:33
+	shl.b32 	%r2, %r1, 6;
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	mov.u32 	%r3, %tid.x;
+	bfe.u32 	%r4, %r3, 1, 6;
+	.loc	1 23 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:23
+	or.b32  	%r9, %r4, %r2;
+	.loc	1 25 37                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:25:37
+	shl.b32 	%r10, %r3, 2;
+	and.b32  	%r5, %r10, 4;
+	.loc	1 28 19                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:28:19
+	mul.hi.s32 	%r11, %r9, 1717986919;
+	shr.u32 	%r12, %r11, 31;
+	shr.s32 	%r13, %r11, 4;
+	add.s32 	%r6, %r13, %r12;
+	setp.ge.s32 	%p1, %r9, %r8;
+	@%p1 bra 	$L__BB0_5;
+// %bb.1:                               // %.split.us.preheader
+	.loc	1 31 40                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:31:40
+	shl.b32 	%r82, %r1, 13;
+	shl.b32 	%r83, %r6, 11;
+	add.s32 	%r84, %r82, %r83;
+	shl.b32 	%r85, %r4, 7;
+	add.s32 	%r86, %r84, %r85;
+	or.b32  	%r87, %r86, %r5;
+	cvt.u64.u32 	%rd1, %r87;
+	mov.f32 	%f21, 0f00000000;
+	mov.b64 	%rd29, -8;
+	mov.f32 	%f22, %f21;
+	mov.f32 	%f23, %f21;
+	mov.f32 	%f24, %f21;
+$L__BB0_2:                              // %.split.us
+                                        // =>This Inner Loop Header: Depth=1
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd25, %rd1, %rd29;
+	cvt.u32.u64 	%r92, %rd25;
+	add.s32 	%r93, %r92, 8;
+	mul.wide.s32 	%rd26, %r93, 2;
+	add.s64 	%rd24, %rd4, %rd26;
+	mov.b32 	%r90, 0;
+	mov.pred 	%p18, -1;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r88, %r90;
+	mov.u32 %r89, %r90;
+	@%p18 ld.global.L1::evict_first.v2.b32 { %r88, %r89 }, [ %rd24 + 0 ];
+	// end inline asm
+	mov.b32 	{%rs1, %rs2}, %r88;
+	mov.b32 	{%rs3, %rs4}, %r89;
+	.loc	1 37 122                        // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:122
+	cvt.f32.bf16 	%f13, %rs1;
+	cvt.f32.bf16 	%f14, %rs2;
+	cvt.f32.bf16 	%f15, %rs3;
+	cvt.f32.bf16 	%f16, %rs4;
+	.loc	1 41 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:41:23
+	fma.rn.f32 	%f21, %f13, %f13, %f21;
+	fma.rn.f32 	%f22, %f14, %f14, %f22;
+	fma.rn.f32 	%f23, %f15, %f15, %f23;
+	fma.rn.f32 	%f24, %f16, %f16, %f24;
+	.loc	1 31 40                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:31:40
+	add.s64 	%rd29, %rd29, 8;
+	setp.lt.u64 	%p19, %rd29, 120;
+	@%p19 bra 	$L__BB0_2;
+// %bb.3:                               // %.split4.us.loopexit
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	add.f32 	%f17, %f21, %f22;
+	add.f32 	%f18, %f23, %f17;
+	add.f32 	%f25, %f24, %f18;
+	bra.uni 	$L__BB0_4;
+$L__BB0_5:                              // %.split.preheader
+	.loc	1 0 44                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:0:44
+	mul.lo.s32 	%r14, %r6, 40;
+	sub.s32 	%r15, %r9, %r14;
+	shl.b32 	%r16, %r15, 7;
+	or.b32  	%r17, %r16, %r5;
+	mad.lo.s32 	%r7, %r6, 7168, %r17;
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	mul.wide.s32 	%rd22, %r7, 2;
+	add.s64 	%rd6, %rd4, %rd22;
+	mov.b32 	%r20, 0;
+	mov.pred 	%p2, 0;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r18, %r20;
+	mov.u32 %r19, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r18, %r19 }, [ %rd6 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd7, %rd6, 16;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r22, %r20;
+	mov.u32 %r23, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r22, %r23 }, [ %rd7 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd8, %rd6, 32;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r26, %r20;
+	mov.u32 %r27, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r26, %r27 }, [ %rd8 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd9, %rd6, 48;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r30, %r20;
+	mov.u32 %r31, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r30, %r31 }, [ %rd9 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd10, %rd6, 64;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r34, %r20;
+	mov.u32 %r35, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r34, %r35 }, [ %rd10 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd11, %rd6, 80;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r38, %r20;
+	mov.u32 %r39, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r38, %r39 }, [ %rd11 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd12, %rd6, 96;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r42, %r20;
+	mov.u32 %r43, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r42, %r43 }, [ %rd12 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd13, %rd6, 112;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r46, %r20;
+	mov.u32 %r47, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r46, %r47 }, [ %rd13 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd14, %rd6, 128;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r50, %r20;
+	mov.u32 %r51, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r50, %r51 }, [ %rd14 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd15, %rd6, 144;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r54, %r20;
+	mov.u32 %r55, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r54, %r55 }, [ %rd15 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd16, %rd6, 160;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r58, %r20;
+	mov.u32 %r59, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r58, %r59 }, [ %rd16 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd17, %rd6, 176;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r62, %r20;
+	mov.u32 %r63, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r62, %r63 }, [ %rd17 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd18, %rd6, 192;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r66, %r20;
+	mov.u32 %r67, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r66, %r67 }, [ %rd18 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd19, %rd6, 208;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r70, %r20;
+	mov.u32 %r71, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r70, %r71 }, [ %rd19 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd20, %rd6, 224;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r74, %r20;
+	mov.u32 %r75, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r74, %r75 }, [ %rd20 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd21, %rd6, 240;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r78, %r20;
+	mov.u32 %r79, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r78, %r79 }, [ %rd21 + 0 ];
+	// end inline asm
+	mov.f32 	%f25, 0f00000000;
+$L__BB0_4:                              // %.split4.us
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	and.b32  	%r97, %r3, 63;
+	.loc	1 23 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:23
+	or.b32  	%r98, %r2, %r97;
+	.loc	1 24 21                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:24:21
+	setp.lt.s32 	%p22, %r98, %r8;
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	and.b32  	%r99, %r3, 64;
+	setp.eq.s32 	%p23, %r99, 0;
+$L__tmp1:
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r100, %f25;
+	shfl.sync.bfly.b32	%r101, %r100, 1, 31, -1;
+	mov.b32 	%f19, %r101;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f20, %f25, %f19;
+$L__tmp2:
+	.loc	1 43 28                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:43:28
+	shl.b32 	%r102, %r4, 2;
+	mov.u32 	%r103, global_smem;
+	add.s32 	%r94, %r103, %r102;
+	mov.b32 	%r95, %f20;
+	mov.pred 	%p20, -1;
+	// begin inline asm
+	@%p20 st.shared.b32 [ %r94 + 0 ], %r95;
+	// end inline asm
+	bar.sync 	0;
+	shl.b32 	%r104, %r97, 2;
+	add.s32 	%r105, %r103, %r104;
+	ld.shared.u32 	%r96, [%r105];
+	.loc	1 44 25                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:25
+	mul.wide.s32 	%rd28, %r98, 4;
+	add.s64 	%rd27, %rd5, %rd28;
+	.loc	1 44 36                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:36
+	and.pred  	%p21, %p23, %p22;
+	// begin inline asm
+	@%p21 st.global.b32 [ %rd27 + 0 ], { %r96 };
+	// end inline asm
+	.loc	1 44 4                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:4
+	ret;
+$L__tmp3:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py"
+	.file	2 "/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 241                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xea DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 108
+.b8 107
+.b8 98
+.b8 102
+.b8 110
+.b8 51
+.b8 118
+.b8 110
+.b8 116
+.b8 114
+.b8 106
+.b8 114
+.b8 111
+.b8 104
+.b8 55
+.b8 114
+.b8 118
+.b8 54
+.b8 112
+.b8 97
+.b8 112
+.b8 109
+.b8 102
+.b8 55
+.b8 51
+.b8 118
+.b8 119
+.b8 122
+.b8 102
+.b8 120
+.b8 109
+.b8 109
+.b8 105
+.b8 115
+.b8 113
+.b8 112
+.b8 50
+.b8 105
+.b8 53
+.b8 55
+.b8 113
+.b8 51
+.b8 100
+.b8 105
+.b8 113
+.b8 53
+.b8 121
+.b8 112
+.b8 51
+.b8 103
+.b8 120
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 57
+.b8 48
+.b8 98
+.b8 52
+.b8 53
+.b8 98
+.b8 99
+.b8 101
+.b8 48
+.b8 50
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 108
+.b8 107
+.b8 0
+.b8 2                                   // Abbrev [2] 0x9f:0x27 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 109
+.b8 101
+.b8 97
+.b8 110
+.b8 95
+.b8 112
+.b8 111
+.b8 119
+.b8 95
+.b8 51
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xc6:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 159                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xdb:0x18 DW_TAG_inlined_subroutine
+.b32 159                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp2                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 43                                  // DW_AT_call_line
+.b8 25                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/__grp__triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ttir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ttir", "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ttgir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ttgir", "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.llir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.llir", "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ptx": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ptx", "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.cubin": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.cubin", "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.json": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.json"}}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/FZK7UU4YVWHKHDXSBPGZIUGDDPPEKFR225GY24V5O66L2RAPDY4Q/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ttgir

@@ -0,0 +1,153 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 4], threadsPerWarp = [1, 32], warpsPerCTA = [1, 16], order = [1, 0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0)
+#loc1 = loc(unknown)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":47:27)
+#loc62 = loc(callsite(#loc1 at #loc27))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 16 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg5: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg6: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg7: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1x2048xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<5.120000e+03> : tensor<1x1xf32, #blocked> loc(#loc1)
+    %cst_1 = arith.constant dense<9.99999997E-7> : tensor<1x1xf32, #blocked> loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %c5120_i32 = arith.constant 5120 : i32 loc(#loc1)
+    %c2048_i32 = arith.constant 2048 : i32 loc(#loc1)
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<1x2048xbf16, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<5120> : tensor<1x2048xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.cmpi slt, %0, %arg6 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 2048 : i32, start = 0 : i32} : tensor<2048xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 0 : i32} : tensor<2048xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x2048xi32, #blocked> loc(#loc4)
+    %4 = arith.muli %0, %c5120_i32 : i32 loc(#loc5)
+    %5 = tt.splat %4 : i32 -> tensor<1x2048xi32, #blocked> loc(#loc59)
+    %6 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc7)
+    %7 = tt.splat %1 : i1 -> tensor<1x2048xi1, #blocked> loc(#loc60)
+    %8 = tt.splat %arg1 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc9)
+    %9 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc10)
+    %10 = scf.for %arg8 = %c0_i32 to %c5120_i32 step %c2048_i32 iter_args(%arg9 = %cst) -> (tensor<1x2048xf32, #blocked>)  : i32 {
+      %20 = tt.splat %arg8 : i32 -> tensor<1x2048xi32, #blocked> loc(#loc12)
+      %21 = arith.addi %20, %3 : tensor<1x2048xi32, #blocked> loc(#loc12)
+      %22 = arith.cmpi slt, %21, %cst_3 : tensor<1x2048xi32, #blocked> loc(#loc13)
+      %23 = arith.addi %21, %5 : tensor<1x2048xi32, #blocked> loc(#loc6)
+      %24 = tt.addptr %6, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc7)
+      %25 = arith.andi %22, %7 : tensor<1x2048xi1, #blocked> loc(#loc8)
+      %26 = tt.load %24, %25, %cst_2 evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc14)
+      %27 = arith.extf %26 : tensor<1x2048xbf16, #blocked> to tensor<1x2048xf32, #blocked> loc(#loc15)
+      %28 = tt.addptr %8, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc9)
+      %29 = tt.load %28, %25, %cst_2 evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc16)
+      %30 = arith.extf %29 : tensor<1x2048xbf16, #blocked> to tensor<1x2048xf32, #blocked> loc(#loc17)
+      %31 = tt.addptr %9, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc10)
+      %32 = tt.load %31, %25, %cst_2 evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc18)
+      %33 = arith.extf %32 : tensor<1x2048xbf16, #blocked> to tensor<1x2048xf32, #blocked> loc(#loc19)
+      %34 = arith.addf %30, %33 : tensor<1x2048xf32, #blocked> loc(#loc20)
+      %35 = arith.addf %27, %34 : tensor<1x2048xf32, #blocked> loc(#loc21)
+      %36 = arith.mulf %35, %35 : tensor<1x2048xf32, #blocked> loc(#loc22)
+      %37 = arith.addf %arg9, %36 : tensor<1x2048xf32, #blocked> loc(#loc23)
+      %38 = arith.select %25, %37, %arg9 : tensor<1x2048xi1, #blocked>, tensor<1x2048xf32, #blocked> loc(#loc24)
+      scf.yield %38 : tensor<1x2048xf32, #blocked> loc(#loc25)
+    } loc(#loc11)
+    %11 = "tt.reduce"(%10) <{axis = 1 : i32}> ({
+    ^bb0(%arg8: f32 loc(callsite(#loc1 at #loc27)), %arg9: f32 loc(callsite(#loc1 at #loc27))):
+      %20 = arith.addf %arg8, %arg9 : f32 loc(#loc64)
+      tt.reduce.return %20 : f32 loc(#loc61)
+    }) : (tensor<1x2048xf32, #blocked>) -> tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc61)
+    %12 = tt.expand_dims %11 {axis = 1 : i32} : tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<1x1xf32, #blocked> loc(#loc29)
+    %13 = tt.splat %arg3 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc30)
+    %14 = arith.divf %12, %cst_0 : tensor<1x1xf32, #blocked> loc(#loc31)
+    %15 = arith.addf %14, %cst_1 : tensor<1x1xf32, #blocked> loc(#loc32)
+    %16 = tt.extern_elementwise %15 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1x1xf32, #blocked>) -> tensor<1x1xf32, #blocked> loc(#loc33)
+    %17 = tt.broadcast %16 : tensor<1x1xf32, #blocked> -> tensor<1x2048xf32, #blocked> loc(#loc34)
+    %18 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc35)
+    %19 = tt.splat %arg5 : !tt.ptr<bf16> -> tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc36)
+    scf.for %arg8 = %c0_i32 to %c5120_i32 step %c2048_i32  : i32 {
+      %20 = tt.splat %arg8 : i32 -> tensor<1x2048xi32, #blocked> loc(#loc38)
+      %21 = arith.addi %20, %3 : tensor<1x2048xi32, #blocked> loc(#loc38)
+      %22 = arith.cmpi slt, %21, %cst_3 : tensor<1x2048xi32, #blocked> loc(#loc39)
+      %23 = arith.addi %21, %5 : tensor<1x2048xi32, #blocked> loc(#loc40)
+      %24 = tt.addptr %6, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc41)
+      %25 = arith.andi %22, %7 : tensor<1x2048xi1, #blocked> loc(#loc42)
+      %26 = tt.load %24, %25, %cst_2 evictionPolicy = evict_first : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc43)
+      %27 = arith.extf %26 : tensor<1x2048xbf16, #blocked> to tensor<1x2048xf32, #blocked> loc(#loc44)
+      %28 = tt.addptr %8, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc45)
+      %29 = tt.load %28, %25, %cst_2 evictionPolicy = evict_first : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc46)
+      %30 = arith.extf %29 : tensor<1x2048xbf16, #blocked> to tensor<1x2048xf32, #blocked> loc(#loc47)
+      %31 = tt.addptr %9, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc48)
+      %32 = tt.load %31, %25, %cst_2 evictionPolicy = evict_first : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc49)
+      %33 = arith.extf %32 : tensor<1x2048xbf16, #blocked> to tensor<1x2048xf32, #blocked> loc(#loc50)
+      %34 = tt.addptr %13, %21 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc30)
+      %35 = tt.load %34, %22, %cst_2 evictionPolicy = evict_last : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc51)
+      %36 = arith.extf %35 : tensor<1x2048xbf16, #blocked> to tensor<1x2048xf32, #blocked> loc(#loc52)
+      %37 = arith.addf %30, %33 : tensor<1x2048xf32, #blocked> loc(#loc53)
+      %38 = arith.addf %27, %37 : tensor<1x2048xf32, #blocked> loc(#loc54)
+      %39 = arith.mulf %38, %17 : tensor<1x2048xf32, #blocked> loc(#loc34)
+      %40 = arith.mulf %39, %36 : tensor<1x2048xf32, #blocked> loc(#loc55)
+      %41 = tt.addptr %18, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc35)
+      %42 = arith.truncf %40 : tensor<1x2048xf32, #blocked> to tensor<1x2048xbf16, #blocked> loc(#loc56)
+      tt.store %41, %42, %25 : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc56)
+      %43 = tt.addptr %19, %23 : tensor<1x2048x!tt.ptr<bf16>, #blocked>, tensor<1x2048xi32, #blocked> loc(#loc36)
+      %44 = arith.truncf %38 : tensor<1x2048xf32, #blocked> to tensor<1x2048xbf16, #blocked> loc(#loc57)
+      tt.store %43, %44, %25 : tensor<1x2048x!tt.ptr<bf16>, #blocked> loc(#loc57)
+    } loc(#loc37)
+    tt.return loc(#loc58)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":24:21)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":25:37)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:46)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:41)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:34)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:61)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":36:34)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":37:34)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":29:40)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":30:31)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":31:29)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:51)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:112)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":36:51)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":36:112)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":37:51)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":37:112)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":41:22)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":42:22)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":43:22)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":45:25)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":46:50)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":46:8)
+#loc26 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc28 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":47:30)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":57:35)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":64:25)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":66:24)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":67:32)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":68:24)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":72:29)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":73:29)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":48:40)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":49:31)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":50:29)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:42)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:35)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:62)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:52)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:114)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":55:35)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":55:52)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":55:114)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":56:35)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":56:52)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":56:114)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":57:42)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":57:95)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":61:24)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":62:24)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":70:24)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":72:53)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":73:53)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":48:4)
+#loc59 = loc(fused[#loc6, #loc5])
+#loc60 = loc(fused[#loc8, #loc3])
+#loc61 = loc(callsite(#loc26 at #loc27))
+#loc63 = loc(callsite(#loc28 at #loc26))
+#loc64 = loc(callsite(#loc63 at #loc27))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/H3MF4QUJUGW4DC7WBAEFFGLJQIWZPDWN6EHI4E32BY4WWLDO3GJA/triton_red_fused__to_copy_mean_pow_4.json

@@ -0,0 +1 @@
+{"hash": "3ed85e4289a1adc18bf60808529969822d978ecdf10e8e137a0e396b2c6ed992", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 4, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 16, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_mean_pow_4"}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/H3MF4QUJUGW4DC7WBAEFFGLJQIWZPDWN6EHI4E32BY4WWLDO3GJA/triton_red_fused__to_copy_mean_pow_4.llir

@@ -0,0 +1,143 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+define ptx_kernel void @triton_red_fused__to_copy_mean_pow_4(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2, i32 %3, ptr addrspace(1) readnone captures(none) %4) local_unnamed_addr !dbg !6 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %7 = shl i32 %6, 2, !dbg !10
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %9 = lshr i32 %8, 5, !dbg !11
+  %10 = and i32 %9, 3, !dbg !11
+  %11 = and i32 %8, 3, !dbg !11
+  %12 = or disjoint i32 %10, %7, !dbg !12
+  %13 = or disjoint i32 %7, %11, !dbg !12
+  %14 = icmp slt i32 %12, %2, !dbg !13
+  %15 = icmp slt i32 %13, %2, !dbg !13
+  %16 = shl i32 %8, 2, !dbg !14
+  %17 = and i32 %16, 124, !dbg !14
+  %18 = sdiv i32 %12, 8, !dbg !15
+  %19 = mul i32 %18, 8, !dbg !16
+  %.decomposed = sub i32 %12, %19, !dbg !16
+  %20 = or disjoint i32 %17, 5120, !dbg !17
+  %21 = shl nsw i32 %.decomposed, 7, !dbg !18
+  %22 = add nsw i32 %20, %21, !dbg !19
+  %23 = mul i32 %18, 7168, !dbg !20
+  %24 = add i32 %22, %23, !dbg !21
+  %25 = sext i32 %24 to i64, !dbg !22
+  %26 = getelementptr bfloat, ptr addrspace(1) %0, i64 %25, !dbg !22
+  %27 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %26, i1 %14) #3, !dbg !23
+  %28 = extractvalue { i32, i32 } %27, 0, !dbg !23
+  %29 = bitcast i32 %28 to <2 x bfloat>, !dbg !23
+  %30 = extractvalue { i32, i32 } %27, 1, !dbg !23
+  %31 = bitcast i32 %30 to <2 x bfloat>, !dbg !23
+  %32 = extractelement <2 x bfloat> %29, i64 0, !dbg !23
+  %33 = extractelement <2 x bfloat> %29, i64 1, !dbg !23
+  %34 = extractelement <2 x bfloat> %31, i64 0, !dbg !23
+  %35 = extractelement <2 x bfloat> %31, i64 1, !dbg !23
+  %36 = fpext bfloat %32 to float, !dbg !24
+  %37 = fpext bfloat %33 to float, !dbg !24
+  %38 = fpext bfloat %34 to float, !dbg !24
+  %39 = fpext bfloat %35 to float, !dbg !24
+  %40 = fmul float %36, %36, !dbg !25
+  %41 = fmul float %37, %37, !dbg !25
+  %42 = fmul float %38, %38, !dbg !25
+  %43 = fmul float %39, %39, !dbg !25
+  %44 = fadd float %40, %41, !dbg !26
+  %45 = fadd float %42, %44, !dbg !26
+  %46 = fadd float %43, %45, !dbg !26
+  %47 = select i1 %14, float %46, float 0.000000e+00, !dbg !26
+  %48 = bitcast float %47 to i32, !dbg !31
+  %49 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %48, i32 16, i32 31), !dbg !31
+  %50 = bitcast i32 %49 to float, !dbg !31
+  %51 = fadd float %47, %50, !dbg !26
+  %52 = bitcast float %51 to i32, !dbg !31
+  %53 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %52, i32 8, i32 31), !dbg !31
+  %54 = bitcast i32 %53 to float, !dbg !31
+  %55 = fadd float %51, %54, !dbg !26
+  %56 = bitcast float %55 to i32, !dbg !31
+  %57 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %56, i32 4, i32 31), !dbg !31
+  %58 = bitcast i32 %57 to float, !dbg !31
+  %59 = fadd float %55, %58, !dbg !26
+  %60 = bitcast float %59 to i32, !dbg !31
+  %61 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %60, i32 2, i32 31), !dbg !31
+  %62 = bitcast i32 %61 to float, !dbg !31
+  %63 = fadd float %59, %62, !dbg !26
+  %64 = bitcast float %63 to i32, !dbg !31
+  %65 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %64, i32 1, i32 31), !dbg !31
+  %66 = bitcast i32 %65 to float, !dbg !31
+  %67 = fadd float %63, %66, !dbg !26
+  %68 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %10, !dbg !32
+  %69 = bitcast float %67 to <1 x i32>, !dbg !32
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %68, <1 x i32> %69, i1 true) #3, !dbg !32
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %70 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %11, !dbg !32
+  %71 = load i32, ptr addrspace(3) %70, align 4, !dbg !32
+  %72 = sext i32 %13 to i64, !dbg !33
+  %73 = getelementptr float, ptr addrspace(1) %1, i64 %72, !dbg !33
+  %74 = and i32 %8, 124, !dbg !34
+  %75 = icmp eq i32 %74, 0, !dbg !34
+  %76 = and i1 %75, %15, !dbg !34
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %71, ptr addrspace(1) %73, i1 %76) #3, !dbg !34
+  ret void, !dbg !35
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py", directory: "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty")
+!4 = !{ptr @triton_red_fused__to_copy_mean_pow_4, !"reqntidx", i32 128}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mean_pow_4", linkageName: "triton_red_fused__to_copy_mean_pow_4", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 22, column: 28, scope: !6)
+!10 = !DILocation(line: 22, column: 33, scope: !6)
+!11 = !DILocation(line: 23, column: 44, scope: !6)
+!12 = !DILocation(line: 23, column: 23, scope: !6)
+!13 = !DILocation(line: 24, column: 21, scope: !6)
+!14 = !DILocation(line: 25, column: 37, scope: !6)
+!15 = !DILocation(line: 28, column: 19, scope: !6)
+!16 = !DILocation(line: 27, column: 19, scope: !6)
+!17 = !DILocation(line: 37, column: 41, scope: !6)
+!18 = !DILocation(line: 37, column: 52, scope: !6)
+!19 = !DILocation(line: 37, column: 48, scope: !6)
+!20 = !DILocation(line: 37, column: 62, scope: !6)
+!21 = !DILocation(line: 37, column: 57, scope: !6)
+!22 = !DILocation(line: 37, column: 34, scope: !6)
+!23 = !DILocation(line: 37, column: 67, scope: !6)
+!24 = !DILocation(line: 37, column: 129, scope: !6)
+!25 = !DILocation(line: 39, column: 22, scope: !6)
+!26 = !DILocation(line: 256, column: 15, scope: !27, inlinedAt: !30)
+!27 = distinct !DILexicalBlockFile(scope: !29, file: !28, discriminator: 0)
+!28 = !DIFile(filename: "standard.py", directory: "/home/x/hfenv/lib/python3.12/site-packages/triton/language")
+!29 = distinct !DILexicalBlockFile(scope: !6, file: !28, discriminator: 0)
+!30 = !DILocation(line: 43, column: 25, scope: !6)
+!31 = !DILocation(line: 286, column: 36, scope: !29, inlinedAt: !30)
+!32 = !DILocation(line: 43, column: 28, scope: !6)
+!33 = !DILocation(line: 44, column: 25, scope: !6)
+!34 = !DILocation(line: 44, column: 36, scope: !6)
+!35 = !DILocation(line: 44, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/H3MF4QUJUGW4DC7WBAEFFGLJQIWZPDWN6EHI4E32BY4WWLDO3GJA/triton_red_fused__to_copy_mean_pow_4.ttgir

@@ -0,0 +1,96 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 4], threadsPerWarp = [1, 32], warpsPerCTA = [4, 1], order = [1, 0]}>
+#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [4, 8], warpsPerCTA = [1, 4], order = [0, 1]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)
+#loc1 = loc(unknown)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:25)
+#loc31 = loc(callsite(#loc1 at #loc24))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mean_pow_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<4x128xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<4x128xbf16, #blocked> loc(#loc1)
+    %c4_i32 = arith.constant 4 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<8> : tensor<4x1xi32, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<7168> : tensor<4x1xi32, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<128> : tensor<4x1xi32, #blocked> loc(#loc1)
+    %cst_4 = arith.constant dense<5120> : tensor<1x128xi32, #blocked> loc(#loc1)
+    %cst_5 = arith.constant dense<128> : tensor<1x128xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c4_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 4 : i32, start = 0 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc4)
+    %3 = tt.make_range {end = 4 : i32, start = 0 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc4)
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<4x1xi32, #blocked> loc(#loc4)
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<4x1xi32, #blocked1> loc(#loc4)
+    %6 = tt.splat %1 : i32 -> tensor<4x1xi32, #blocked> loc(#loc5)
+    %7 = tt.splat %1 : i32 -> tensor<4x1xi32, #blocked1> loc(#loc5)
+    %8 = arith.addi %6, %4 : tensor<4x1xi32, #blocked> loc(#loc5)
+    %9 = arith.addi %7, %5 : tensor<4x1xi32, #blocked1> loc(#loc5)
+    %10 = tt.splat %arg2 : i32 -> tensor<4x1xi32, #blocked> loc(#loc6)
+    %11 = tt.splat %arg2 : i32 -> tensor<4x1xi32, #blocked1> loc(#loc6)
+    %12 = arith.cmpi slt, %8, %10 : tensor<4x1xi32, #blocked> loc(#loc6)
+    %13 = arith.cmpi slt, %9, %11 : tensor<4x1xi32, #blocked1> loc(#loc6)
+    %14 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc7)
+    %15 = tt.expand_dims %14 {axis = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x128xi32, #blocked> loc(#loc7)
+    %16 = arith.remsi %8, %cst_1 : tensor<4x1xi32, #blocked> loc(#loc8)
+    %17 = arith.divsi %8, %cst_1 : tensor<4x1xi32, #blocked> loc(#loc9)
+    %18 = arith.cmpi slt, %15, %cst_5 : tensor<1x128xi32, #blocked> loc(#loc10)
+    %19 = arith.addi %15, %cst_4 : tensor<1x128xi32, #blocked> loc(#loc11)
+    %20 = arith.muli %16, %cst_3 : tensor<4x1xi32, #blocked> loc(#loc12)
+    %21 = tt.broadcast %19 : tensor<1x128xi32, #blocked> -> tensor<4x128xi32, #blocked> loc(#loc13)
+    %22 = tt.broadcast %20 : tensor<4x1xi32, #blocked> -> tensor<4x128xi32, #blocked> loc(#loc13)
+    %23 = arith.addi %21, %22 : tensor<4x128xi32, #blocked> loc(#loc13)
+    %24 = arith.muli %17, %cst_2 : tensor<4x1xi32, #blocked> loc(#loc14)
+    %25 = tt.broadcast %24 : tensor<4x1xi32, #blocked> -> tensor<4x128xi32, #blocked> loc(#loc15)
+    %26 = arith.addi %23, %25 : tensor<4x128xi32, #blocked> loc(#loc15)
+    %27 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<4x128x!tt.ptr<bf16>, #blocked> loc(#loc16)
+    %28 = tt.addptr %27, %26 : tensor<4x128x!tt.ptr<bf16>, #blocked>, tensor<4x128xi32, #blocked> loc(#loc16)
+    %29 = tt.broadcast %18 : tensor<1x128xi1, #blocked> -> tensor<4x128xi1, #blocked> loc(#loc17)
+    %30 = tt.broadcast %12 : tensor<4x1xi1, #blocked> -> tensor<4x128xi1, #blocked> loc(#loc17)
+    %31 = arith.andi %29, %30 : tensor<4x128xi1, #blocked> loc(#loc17)
+    %32 = tt.load %28, %31, %cst_0 evictionPolicy = evict_first : tensor<4x128x!tt.ptr<bf16>, #blocked> loc(#loc18)
+    %33 = arith.extf %32 : tensor<4x128xbf16, #blocked> to tensor<4x128xf32, #blocked> loc(#loc19)
+    %34 = arith.mulf %33, %33 : tensor<4x128xf32, #blocked> loc(#loc20)
+    %35 = arith.addf %34, %cst : tensor<4x128xf32, #blocked> loc(#loc21)
+    %36 = arith.select %31, %35, %cst : tensor<4x128xi1, #blocked>, tensor<4x128xf32, #blocked> loc(#loc22)
+    %37 = "tt.reduce"(%36) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc24)), %arg5: f32 loc(callsite(#loc1 at #loc24))):
+      %42 = arith.addf %arg4, %arg5 : f32 loc(#loc33)
+      tt.reduce.return %42 : f32 loc(#loc30)
+    }) : (tensor<4x128xf32, #blocked>) -> tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc30)
+    %38 = ttg.convert_layout %37 : tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc26)
+    %39 = tt.expand_dims %38 {axis = 1 : i32} : tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<4x1xf32, #blocked1> loc(#loc26)
+    %40 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<4x1x!tt.ptr<f32>, #blocked1> loc(#loc27)
+    %41 = tt.addptr %40, %9 : tensor<4x1x!tt.ptr<f32>, #blocked1>, tensor<4x1xi32, #blocked1> loc(#loc27)
+    tt.store %41, %39, %13 : tensor<4x1x!tt.ptr<f32>, #blocked1> loc(#loc28)
+    tt.return loc(#loc29)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:44)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":24:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:37)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":27:19)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":28:19)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":33:29)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:41)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:52)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:48)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:62)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:57)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:34)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:77)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:67)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:129)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":39:22)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":41:23)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:48)
+#loc23 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc25 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:28)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:25)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:36)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:4)
+#loc30 = loc(callsite(#loc23 at #loc24))
+#loc32 = loc(callsite(#loc25 at #loc23))
+#loc33 = loc(callsite(#loc32 at #loc24))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/H3MF4QUJUGW4DC7WBAEFFGLJQIWZPDWN6EHI4E32BY4WWLDO3GJA/triton_red_fused__to_copy_mean_pow_4.ttir

@@ -0,0 +1,89 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)
+#loc1 = loc(unknown)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:25)
+#loc33 = loc(callsite(#loc1 at #loc26))
+module {
+  tt.func public @triton_red_fused__to_copy_mean_pow_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<4x128xbf16> loc(#loc1)
+    %cst_0 = arith.constant dense<7168> : tensor<4x1xi32> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<4x1xi32> loc(#loc1)
+    %cst_2 = arith.constant dense<5120> : tensor<1x128xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<128> : tensor<1x128xi32> loc(#loc1)
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<4x128xf32> loc(#loc1)
+    %cst_5 = arith.constant dense<8> : tensor<4x1xi32> loc(#loc1)
+    %c4_i32 = arith.constant 4 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c4_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 4 : i32, start = 0 : i32} : tensor<4xi32> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : tensor<4xi32> -> tensor<4x1xi32> loc(#loc5)
+    %4 = tt.splat %1 : i32 -> tensor<4x1xi32> loc(#loc6)
+    %5 = arith.addi %4, %3 : tensor<4x1xi32> loc(#loc6)
+    %6 = tt.splat %arg2 : i32 -> tensor<4x1xi32> loc(#loc7)
+    %7 = arith.cmpi slt, %5, %6 : tensor<4x1xi32> loc(#loc7)
+    %8 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32> loc(#loc8)
+    %9 = tt.expand_dims %8 {axis = 0 : i32} : tensor<128xi32> -> tensor<1x128xi32> loc(#loc9)
+    %10 = arith.remsi %5, %cst_5 : tensor<4x1xi32> loc(#loc10)
+    %11 = arith.divsi %5, %cst_5 : tensor<4x1xi32> loc(#loc11)
+    %12 = arith.cmpi slt, %9, %cst_3 : tensor<1x128xi32> loc(#loc12)
+    %13 = arith.addi %9, %cst_2 : tensor<1x128xi32> loc(#loc13)
+    %14 = arith.muli %10, %cst_1 : tensor<4x1xi32> loc(#loc14)
+    %15 = tt.broadcast %13 : tensor<1x128xi32> -> tensor<4x128xi32> loc(#loc15)
+    %16 = tt.broadcast %14 : tensor<4x1xi32> -> tensor<4x128xi32> loc(#loc15)
+    %17 = arith.addi %15, %16 : tensor<4x128xi32> loc(#loc15)
+    %18 = arith.muli %11, %cst_0 : tensor<4x1xi32> loc(#loc16)
+    %19 = tt.broadcast %18 : tensor<4x1xi32> -> tensor<4x128xi32> loc(#loc17)
+    %20 = arith.addi %17, %19 : tensor<4x128xi32> loc(#loc17)
+    %21 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<4x128x!tt.ptr<bf16>> loc(#loc18)
+    %22 = tt.addptr %21, %20 : tensor<4x128x!tt.ptr<bf16>>, tensor<4x128xi32> loc(#loc18)
+    %23 = tt.broadcast %12 : tensor<1x128xi1> -> tensor<4x128xi1> loc(#loc19)
+    %24 = tt.broadcast %7 : tensor<4x1xi1> -> tensor<4x128xi1> loc(#loc19)
+    %25 = arith.andi %23, %24 : tensor<4x128xi1> loc(#loc19)
+    %26 = tt.load %22, %25, %cst evictionPolicy = evict_first : tensor<4x128x!tt.ptr<bf16>> loc(#loc20)
+    %27 = arith.extf %26 : tensor<4x128xbf16> to tensor<4x128xf32> loc(#loc21)
+    %28 = arith.mulf %27, %27 : tensor<4x128xf32> loc(#loc22)
+    %29 = arith.addf %28, %cst_4 : tensor<4x128xf32> loc(#loc23)
+    %30 = arith.select %25, %29, %cst_4 : tensor<4x128xi1>, tensor<4x128xf32> loc(#loc24)
+    %31 = "tt.reduce"(%30) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc26)), %arg5: f32 loc(callsite(#loc1 at #loc26))):
+      %35 = arith.addf %arg4, %arg5 : f32 loc(#loc35)
+      tt.reduce.return %35 : f32 loc(#loc32)
+    }) : (tensor<4x128xf32>) -> tensor<4xf32> loc(#loc32)
+    %32 = tt.expand_dims %31 {axis = 1 : i32} : tensor<4xf32> -> tensor<4x1xf32> loc(#loc28)
+    %33 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<4x1x!tt.ptr<f32>> loc(#loc29)
+    %34 = tt.addptr %33, %5 : tensor<4x1x!tt.ptr<f32>>, tensor<4x1xi32> loc(#loc29)
+    tt.store %34, %32, %7 : tensor<4x1x!tt.ptr<f32>> loc(#loc30)
+    tt.return loc(#loc31)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:44)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:23)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":24:21)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:27)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:37)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":27:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":28:19)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":33:29)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:41)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:52)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:48)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:62)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:57)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:34)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:77)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:67)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:129)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":39:22)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":41:23)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:48)
+#loc25 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc27 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:28)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:25)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:36)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:4)
+#loc32 = loc(callsite(#loc25 at #loc26))
+#loc34 = loc(callsite(#loc27 at #loc25))
+#loc35 = loc(callsite(#loc34 at #loc26))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/IU5ZJI3Y5WXTTEPQ3FCFJROVHMQ3URH7WEEKYQL3V6EM23IIYN6A/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.json

@@ -0,0 +1 @@
+{"hash": "453b94a378edaf3991f0d94454c5d53b21ba44ffb108ac417baf88cd6d08c37c", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 16, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 64, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2"}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/IU5ZJI3Y5WXTTEPQ3FCFJROVHMQ3URH7WEEKYQL3V6EM23IIYN6A/triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2.ttgir

@@ -0,0 +1,153 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 2], threadsPerWarp = [1, 32], warpsPerCTA = [1, 16], order = [1, 0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0)
+#loc1 = loc(unknown)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":47:27)
+#loc62 = loc(callsite(#loc1 at #loc27))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 16 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_add_mean_mul_pow_rsqrt_2(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg3: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg5: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg6: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0), %arg7: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1x1024xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<5.120000e+03> : tensor<1x1xf32, #blocked> loc(#loc1)
+    %cst_1 = arith.constant dense<9.99999997E-7> : tensor<1x1xf32, #blocked> loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %c5120_i32 = arith.constant 5120 : i32 loc(#loc1)
+    %c1024_i32 = arith.constant 1024 : i32 loc(#loc1)
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<1x1024xbf16, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<5120> : tensor<1x1024xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.cmpi slt, %0, %arg6 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 0 : i32} : tensor<1024xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x1024xi32, #blocked> loc(#loc4)
+    %4 = arith.muli %0, %c5120_i32 : i32 loc(#loc5)
+    %5 = tt.splat %4 : i32 -> tensor<1x1024xi32, #blocked> loc(#loc59)
+    %6 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc7)
+    %7 = tt.splat %1 : i1 -> tensor<1x1024xi1, #blocked> loc(#loc60)
+    %8 = tt.splat %arg1 : !tt.ptr<bf16> -> tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc9)
+    %9 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc10)
+    %10 = scf.for %arg8 = %c0_i32 to %c5120_i32 step %c1024_i32 iter_args(%arg9 = %cst) -> (tensor<1x1024xf32, #blocked>)  : i32 {
+      %20 = tt.splat %arg8 : i32 -> tensor<1x1024xi32, #blocked> loc(#loc12)
+      %21 = arith.addi %20, %3 : tensor<1x1024xi32, #blocked> loc(#loc12)
+      %22 = arith.cmpi slt, %21, %cst_3 : tensor<1x1024xi32, #blocked> loc(#loc13)
+      %23 = arith.addi %21, %5 : tensor<1x1024xi32, #blocked> loc(#loc6)
+      %24 = tt.addptr %6, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc7)
+      %25 = arith.andi %22, %7 : tensor<1x1024xi1, #blocked> loc(#loc8)
+      %26 = tt.load %24, %25, %cst_2 evictionPolicy = evict_last : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc14)
+      %27 = arith.extf %26 : tensor<1x1024xbf16, #blocked> to tensor<1x1024xf32, #blocked> loc(#loc15)
+      %28 = tt.addptr %8, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc9)
+      %29 = tt.load %28, %25, %cst_2 evictionPolicy = evict_last : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc16)
+      %30 = arith.extf %29 : tensor<1x1024xbf16, #blocked> to tensor<1x1024xf32, #blocked> loc(#loc17)
+      %31 = tt.addptr %9, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc10)
+      %32 = tt.load %31, %25, %cst_2 evictionPolicy = evict_last : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc18)
+      %33 = arith.extf %32 : tensor<1x1024xbf16, #blocked> to tensor<1x1024xf32, #blocked> loc(#loc19)
+      %34 = arith.addf %30, %33 : tensor<1x1024xf32, #blocked> loc(#loc20)
+      %35 = arith.addf %27, %34 : tensor<1x1024xf32, #blocked> loc(#loc21)
+      %36 = arith.mulf %35, %35 : tensor<1x1024xf32, #blocked> loc(#loc22)
+      %37 = arith.addf %arg9, %36 : tensor<1x1024xf32, #blocked> loc(#loc23)
+      %38 = arith.select %25, %37, %arg9 : tensor<1x1024xi1, #blocked>, tensor<1x1024xf32, #blocked> loc(#loc24)
+      scf.yield %38 : tensor<1x1024xf32, #blocked> loc(#loc25)
+    } loc(#loc11)
+    %11 = "tt.reduce"(%10) <{axis = 1 : i32}> ({
+    ^bb0(%arg8: f32 loc(callsite(#loc1 at #loc27)), %arg9: f32 loc(callsite(#loc1 at #loc27))):
+      %20 = arith.addf %arg8, %arg9 : f32 loc(#loc64)
+      tt.reduce.return %20 : f32 loc(#loc61)
+    }) : (tensor<1x1024xf32, #blocked>) -> tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc61)
+    %12 = tt.expand_dims %11 {axis = 1 : i32} : tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<1x1xf32, #blocked> loc(#loc29)
+    %13 = tt.splat %arg3 : !tt.ptr<bf16> -> tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc30)
+    %14 = arith.divf %12, %cst_0 : tensor<1x1xf32, #blocked> loc(#loc31)
+    %15 = arith.addf %14, %cst_1 : tensor<1x1xf32, #blocked> loc(#loc32)
+    %16 = tt.extern_elementwise %15 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1x1xf32, #blocked>) -> tensor<1x1xf32, #blocked> loc(#loc33)
+    %17 = tt.broadcast %16 : tensor<1x1xf32, #blocked> -> tensor<1x1024xf32, #blocked> loc(#loc34)
+    %18 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc35)
+    %19 = tt.splat %arg5 : !tt.ptr<bf16> -> tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc36)
+    scf.for %arg8 = %c0_i32 to %c5120_i32 step %c1024_i32  : i32 {
+      %20 = tt.splat %arg8 : i32 -> tensor<1x1024xi32, #blocked> loc(#loc38)
+      %21 = arith.addi %20, %3 : tensor<1x1024xi32, #blocked> loc(#loc38)
+      %22 = arith.cmpi slt, %21, %cst_3 : tensor<1x1024xi32, #blocked> loc(#loc39)
+      %23 = arith.addi %21, %5 : tensor<1x1024xi32, #blocked> loc(#loc40)
+      %24 = tt.addptr %6, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc41)
+      %25 = arith.andi %22, %7 : tensor<1x1024xi1, #blocked> loc(#loc42)
+      %26 = tt.load %24, %25, %cst_2 evictionPolicy = evict_first : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc43)
+      %27 = arith.extf %26 : tensor<1x1024xbf16, #blocked> to tensor<1x1024xf32, #blocked> loc(#loc44)
+      %28 = tt.addptr %8, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc45)
+      %29 = tt.load %28, %25, %cst_2 evictionPolicy = evict_first : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc46)
+      %30 = arith.extf %29 : tensor<1x1024xbf16, #blocked> to tensor<1x1024xf32, #blocked> loc(#loc47)
+      %31 = tt.addptr %9, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc48)
+      %32 = tt.load %31, %25, %cst_2 evictionPolicy = evict_first : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc49)
+      %33 = arith.extf %32 : tensor<1x1024xbf16, #blocked> to tensor<1x1024xf32, #blocked> loc(#loc50)
+      %34 = tt.addptr %13, %21 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc30)
+      %35 = tt.load %34, %22, %cst_2 evictionPolicy = evict_last : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc51)
+      %36 = arith.extf %35 : tensor<1x1024xbf16, #blocked> to tensor<1x1024xf32, #blocked> loc(#loc52)
+      %37 = arith.addf %30, %33 : tensor<1x1024xf32, #blocked> loc(#loc53)
+      %38 = arith.addf %27, %37 : tensor<1x1024xf32, #blocked> loc(#loc54)
+      %39 = arith.mulf %38, %17 : tensor<1x1024xf32, #blocked> loc(#loc34)
+      %40 = arith.mulf %39, %36 : tensor<1x1024xf32, #blocked> loc(#loc55)
+      %41 = tt.addptr %18, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc35)
+      %42 = arith.truncf %40 : tensor<1x1024xf32, #blocked> to tensor<1x1024xbf16, #blocked> loc(#loc56)
+      tt.store %41, %42, %25 : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc56)
+      %43 = tt.addptr %19, %23 : tensor<1x1024x!tt.ptr<bf16>, #blocked>, tensor<1x1024xi32, #blocked> loc(#loc36)
+      %44 = arith.truncf %38 : tensor<1x1024xf32, #blocked> to tensor<1x1024xbf16, #blocked> loc(#loc57)
+      tt.store %43, %44, %25 : tensor<1x1024x!tt.ptr<bf16>, #blocked> loc(#loc57)
+    } loc(#loc37)
+    tt.return loc(#loc58)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":24:21)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":25:37)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:46)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:41)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:34)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:61)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":36:34)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":37:34)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":29:40)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":30:31)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":31:29)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:51)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":35:112)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":36:51)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":36:112)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":37:51)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":37:112)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":41:22)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":42:22)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":43:22)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":45:25)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":46:50)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":46:8)
+#loc26 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc28 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":47:30)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":57:35)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":64:25)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":66:24)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":67:32)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":68:24)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":72:29)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":73:29)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":48:40)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":49:31)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":50:29)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:42)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:35)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:62)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:52)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":54:114)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":55:35)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":55:52)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":55:114)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":56:35)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":56:52)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":56:114)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":57:42)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":57:95)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":61:24)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":62:24)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":70:24)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":72:53)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":73:53)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ba/cbae5wmn654pnu4ksnsd2uolvtcfej6hyfr36na3zlgeqvrpvj33.py":48:4)
+#loc59 = loc(fused[#loc6, #loc5])
+#loc60 = loc(fused[#loc8, #loc3])
+#loc61 = loc(callsite(#loc26 at #loc27))
+#loc63 = loc(callsite(#loc28 at #loc26))
+#loc64 = loc(callsite(#loc63 at #loc27))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KDOBAX2VQKBWDZWBYGTVPVFPVPDMVJR77GO463F57U2EDEXXPF5Q/triton_poi_fused_mul_silu_1.ttgir

@@ -0,0 +1,74 @@
+#blocked = #ttg.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [8], order = [0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":18:0)
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 8 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_mul_silu_1(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":18:0), %arg1: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":18:0), %arg2: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<1.000000e+00> : tensor<512xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<512xf32, #blocked> loc(#loc1)
+    %c512_i32 = arith.constant 512 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<17408> : tensor<512xi32, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<34816> : tensor<512xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c512_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<512xi32, #blocked> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<512xi32, #blocked> loc(#loc5)
+    %5 = tt.splat %arg2 : i32 -> tensor<512xi32, #blocked> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<512xi32, #blocked> loc(#loc6)
+    %7 = arith.remsi %4, %cst_1 : tensor<512xi32, #blocked> loc(#loc7)
+    %8 = arith.divsi %4, %cst_1 : tensor<512xi32, #blocked> loc(#loc8)
+    %9 = arith.muli %8, %cst_2 : tensor<512xi32, #blocked> loc(#loc9)
+    %10 = arith.addi %7, %9 : tensor<512xi32, #blocked> loc(#loc10)
+    %11 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc11)
+    %12 = tt.addptr %11, %10 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc11)
+    %13 = tt.load %12, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc12)
+    %14 = arith.extf %13 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc13)
+    %15 = arith.addi %7, %cst_1 : tensor<512xi32, #blocked> loc(#loc14)
+    %16 = arith.addi %15, %9 : tensor<512xi32, #blocked> loc(#loc15)
+    %17 = tt.addptr %11, %16 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc16)
+    %18 = tt.load %17, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc17)
+    %19 = arith.extf %18 : tensor<512xbf16, #blocked> to tensor<512xf32, #blocked> loc(#loc18)
+    %20 = arith.subf %cst_0, %14 : tensor<512xf32, #blocked> loc(#loc29)
+    %21 = math.exp %20 : tensor<512xf32, #blocked> loc(#loc30)
+    %22 = arith.addf %21, %cst : tensor<512xf32, #blocked> loc(#loc31)
+    %23 = arith.divf %cst, %22 : tensor<512xf32, #blocked> loc(#loc32)
+    %24 = arith.mulf %14, %23 : tensor<512xf32, #blocked> loc(#loc24)
+    %25 = arith.mulf %24, %19 : tensor<512xf32, #blocked> loc(#loc25)
+    %26 = tt.splat %arg1 : !tt.ptr<bf16> -> tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc26)
+    %27 = tt.addptr %26, %4 : tensor<512x!tt.ptr<bf16>, #blocked>, tensor<512xi32, #blocked> loc(#loc26)
+    %28 = arith.truncf %25 : tensor<512xf32, #blocked> to tensor<512xbf16, #blocked> loc(#loc27)
+    tt.store %27, %28, %6 : tensor<512x!tt.ptr<bf16>, #blocked> loc(#loc27)
+    tt.return loc(#loc28)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":23:19)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":25:41)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":25:35)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":25:30)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":25:46)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":25:56)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":26:38)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":26:43)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":26:30)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":26:54)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":26:64)
+#loc19 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":47:30)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":28:22)
+#loc21 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":47:29)
+#loc22 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":47:20)
+#loc23 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":47:16)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":29:18)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":31:18)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":32:25)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":32:36)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/z4/cz4n3q3gd5hna4phstgqlbohw3umfmkyoaz3ypzjru4tbveijfcv.py":32:4)
+#loc29 = loc(callsite(#loc19 at #loc20))
+#loc30 = loc(callsite(#loc21 at #loc20))
+#loc31 = loc(callsite(#loc22 at #loc20))
+#loc32 = loc(callsite(#loc23 at #loc20))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/__grp__triton_red_fused__to_copy_mean_pow_4.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_4.ttir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.ttir", "triton_red_fused__to_copy_mean_pow_4.ttgir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.ttgir", "triton_red_fused__to_copy_mean_pow_4.llir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.llir", "triton_red_fused__to_copy_mean_pow_4.ptx": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.ptx", "triton_red_fused__to_copy_mean_pow_4.cubin": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.cubin", "triton_red_fused__to_copy_mean_pow_4.json": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.json"}}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.json

@@ -0,0 +1 @@
+{"hash": "514fcc53f10b2e6159ae7928a47992359cd799ce0e5507dac6a8f51afbce6e1e", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 2, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 8, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_mean_pow_4"}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.llir

@@ -0,0 +1,137 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+define ptx_kernel void @triton_red_fused__to_copy_mean_pow_4(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2, i32 %3, ptr addrspace(1) readnone captures(none) %4) local_unnamed_addr !dbg !6 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %7 = icmp slt i32 %6, %2, !dbg !10
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %9 = and i32 %8, 31, !dbg !11
+  %10 = lshr i32 %8, 5, !dbg !11
+  %11 = shl i32 %8, 1, !dbg !11
+  %12 = and i32 %11, 126, !dbg !11
+  %13 = sdiv i32 %6, 8, !dbg !12
+  %14 = mul i32 %13, 8, !dbg !13
+  %.decomposed = sub i32 %6, %14, !dbg !13
+  %15 = or disjoint i32 %12, 5120, !dbg !14
+  %16 = shl nsw i32 %.decomposed, 7, !dbg !15
+  %17 = add nsw i32 %15, %16, !dbg !16
+  %18 = mul i32 %13, 7168, !dbg !17
+  %19 = add i32 %17, %18, !dbg !18
+  %20 = sext i32 %19 to i64, !dbg !19
+  %21 = getelementptr bfloat, ptr addrspace(1) %0, i64 %20, !dbg !19
+  %22 = tail call i32 asm sideeffect "mov.u32 $0, $1;\0A\09@$3 ld.global.L1::evict_first.b32 { $0 }, [ $2 + 0 ];", "=r,r,l,b"(i32 0, ptr addrspace(1) %21, i1 %7) #3, !dbg !20
+  %23 = bitcast i32 %22 to <2 x bfloat>, !dbg !20
+  %24 = extractelement <2 x bfloat> %23, i64 0, !dbg !20
+  %25 = extractelement <2 x bfloat> %23, i64 1, !dbg !20
+  %26 = fpext bfloat %24 to float, !dbg !21
+  %27 = fpext bfloat %25 to float, !dbg !21
+  %28 = fmul float %26, %26, !dbg !22
+  %29 = fmul float %27, %27, !dbg !22
+  %30 = fadd float %28, %29, !dbg !23
+  %31 = select i1 %7, float %30, float 0.000000e+00, !dbg !23
+  %32 = bitcast float %31 to i32, !dbg !28
+  %33 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %32, i32 16, i32 31), !dbg !28
+  %34 = bitcast i32 %33 to float, !dbg !28
+  %35 = fadd float %31, %34, !dbg !23
+  %36 = bitcast float %35 to i32, !dbg !28
+  %37 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %36, i32 8, i32 31), !dbg !28
+  %38 = bitcast i32 %37 to float, !dbg !28
+  %39 = fadd float %35, %38, !dbg !23
+  %40 = bitcast float %39 to i32, !dbg !28
+  %41 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %40, i32 4, i32 31), !dbg !28
+  %42 = bitcast i32 %41 to float, !dbg !28
+  %43 = fadd float %39, %42, !dbg !23
+  %44 = bitcast float %43 to i32, !dbg !28
+  %45 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %44, i32 2, i32 31), !dbg !28
+  %46 = bitcast i32 %45 to float, !dbg !28
+  %47 = fadd float %43, %46, !dbg !23
+  %48 = bitcast float %47 to i32, !dbg !28
+  %49 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %48, i32 1, i32 31), !dbg !28
+  %50 = bitcast i32 %49 to float, !dbg !28
+  %51 = fadd float %47, %50, !dbg !23
+  %52 = and i32 %10, 1, !dbg !28
+  %53 = icmp eq i32 %9, 0, !dbg !28
+  %54 = getelementptr float, ptr addrspace(3) @global_smem, i32 %52, !dbg !28
+  %55 = bitcast float %51 to <1 x i32>, !dbg !28
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %54, <1 x i32> %55, i1 %53) #3, !dbg !28
+  tail call void @llvm.nvvm.barrier0(), !dbg !28
+  %56 = icmp slt i32 %8, 2, !dbg !28
+  %57 = getelementptr float, ptr addrspace(3) @global_smem, i32 %8, !dbg !28
+  %58 = tail call i32 asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %57, i1 %56) #3, !dbg !28
+  %59 = bitcast i32 %58 to float, !dbg !28
+  %60 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %58, i32 1, i32 31), !dbg !28
+  %61 = bitcast i32 %60 to float, !dbg !28
+  %62 = fadd float %59, %61, !dbg !23
+  %63 = and i32 %8, 1, !dbg !28
+  %64 = icmp eq i32 %63, 0, !dbg !28
+  %65 = and i1 %56, %64, !dbg !28
+  %66 = bitcast float %62 to <1 x i32>, !dbg !28
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %57, <1 x i32> %66, i1 %65) #3, !dbg !28
+  tail call void @llvm.nvvm.barrier0(), !dbg !28
+  %67 = load i32, ptr addrspace(3) @global_smem, align 16, !dbg !28
+  %68 = sext i32 %6 to i64, !dbg !29
+  %69 = getelementptr float, ptr addrspace(1) %1, i64 %68, !dbg !29
+  %70 = and i32 %8, 63, !dbg !30
+  %71 = icmp eq i32 %70, 0, !dbg !30
+  %72 = and i1 %71, %7, !dbg !30
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %67, ptr addrspace(1) %69, i1 %72) #3, !dbg !30
+  ret void, !dbg !31
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py", directory: "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty")
+!4 = !{ptr @triton_red_fused__to_copy_mean_pow_4, !"reqntidx", i32 64}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mean_pow_4", linkageName: "triton_red_fused__to_copy_mean_pow_4", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 22, column: 28, scope: !6)
+!10 = !DILocation(line: 24, column: 21, scope: !6)
+!11 = !DILocation(line: 25, column: 37, scope: !6)
+!12 = !DILocation(line: 28, column: 19, scope: !6)
+!13 = !DILocation(line: 27, column: 19, scope: !6)
+!14 = !DILocation(line: 37, column: 41, scope: !6)
+!15 = !DILocation(line: 37, column: 52, scope: !6)
+!16 = !DILocation(line: 37, column: 48, scope: !6)
+!17 = !DILocation(line: 37, column: 62, scope: !6)
+!18 = !DILocation(line: 37, column: 57, scope: !6)
+!19 = !DILocation(line: 37, column: 34, scope: !6)
+!20 = !DILocation(line: 37, column: 67, scope: !6)
+!21 = !DILocation(line: 37, column: 129, scope: !6)
+!22 = !DILocation(line: 39, column: 22, scope: !6)
+!23 = !DILocation(line: 256, column: 15, scope: !24, inlinedAt: !27)
+!24 = distinct !DILexicalBlockFile(scope: !26, file: !25, discriminator: 0)
+!25 = !DIFile(filename: "standard.py", directory: "/home/x/hfenv/lib/python3.12/site-packages/triton/language")
+!26 = distinct !DILexicalBlockFile(scope: !6, file: !25, discriminator: 0)
+!27 = !DILocation(line: 43, column: 25, scope: !6)
+!28 = !DILocation(line: 286, column: 36, scope: !26, inlinedAt: !27)
+!29 = !DILocation(line: 44, column: 25, scope: !6)
+!30 = !DILocation(line: 44, column: 36, scope: !6)
+!31 = !DILocation(line: 44, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.ptx

@@ -0,0 +1,421 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_mean_pow_4 // -- Begin function triton_red_fused__to_copy_mean_pow_4
+.extern .shared .align 16 .b8 global_smem[];
+                                        // @triton_red_fused__to_copy_mean_pow_4
+.visible .entry triton_red_fused__to_copy_mean_pow_4(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_1,
+	.param .u32 triton_red_fused__to_copy_mean_pow_4_param_2,
+	.param .u32 triton_red_fused__to_copy_mean_pow_4_param_3,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_4
+)
+.reqntid 64, 1, 1
+{
+	.reg .pred 	%p<9>;
+	.reg .b16 	%rs<3>;
+	.reg .b32 	%r<43>;
+	.reg .f32 	%f<19>;
+	.reg .b64 	%rd<7>;
+	.loc	1 18 0                          // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:18:0
+
+// %bb.0:
+	ld.param.u64 	%rd3, [triton_red_fused__to_copy_mean_pow_4_param_0];
+	ld.param.u64 	%rd4, [triton_red_fused__to_copy_mean_pow_4_param_1];
+$L__tmp0:
+	.loc	1 22 28                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:22:28
+	mov.u32 	%r10, %ctaid.x;
+	ld.param.u32 	%r11, [triton_red_fused__to_copy_mean_pow_4_param_2];
+	.loc	1 24 21                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:24:21
+	setp.lt.s32 	%p1, %r10, %r11;
+	.loc	1 25 37                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:25:37
+	mov.u32 	%r12, %tid.x;
+	and.b32  	%r13, %r12, 31;
+	shl.b32 	%r14, %r12, 1;
+	and.b32  	%r15, %r14, 126;
+	.loc	1 28 19                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:28:19
+	shr.s32 	%r16, %r10, 31;
+	shr.u32 	%r17, %r16, 29;
+	add.s32 	%r18, %r10, %r17;
+	shr.u32 	%r19, %r18, 3;
+	.loc	1 27 19                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:27:19
+	and.b32  	%r20, %r18, 33554424;
+	sub.s32 	%r21, %r10, %r20;
+	.loc	1 37 52                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:52
+	shl.b32 	%r22, %r21, 7;
+	.loc	1 37 48                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:48
+	or.b32  	%r23, %r22, %r15;
+	mad.lo.s32 	%r24, %r19, 7168, %r23;
+	.loc	1 37 57                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:57
+	add.s32 	%r25, %r24, 5120;
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	mul.wide.s32 	%rd5, %r25, 2;
+	add.s64 	%rd1, %rd3, %rd5;
+	mov.b32 	%r2, 0;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r1, %r2;
+	@%p1 ld.global.L1::evict_first.b32 { %r1 }, [ %rd1 + 0 ];
+	// end inline asm
+	mov.b32 	{%rs1, %rs2}, %r1;
+	.loc	1 37 129                        // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:129
+	cvt.f32.bf16 	%f1, %rs1;
+	cvt.f32.bf16 	%f2, %rs2;
+	.loc	1 39 22                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:39:22
+	mul.f32 	%f3, %f2, %f2;
+$L__tmp1:
+	.loc	2 256 15                        // standard.py:256:15
+	fma.rn.f32 	%f4, %f1, %f1, %f3;
+	selp.f32 	%f5, %f4, 0f00000000, %p1;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r26, %f5;
+	shfl.sync.bfly.b32	%r27, %r26, 16, 31, -1;
+	mov.b32 	%f6, %r27;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f7, %f5, %f6;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r28, %f7;
+	shfl.sync.bfly.b32	%r29, %r28, 8, 31, -1;
+	mov.b32 	%f8, %r29;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f9, %f7, %f8;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r30, %f9;
+	shfl.sync.bfly.b32	%r31, %r30, 4, 31, -1;
+	mov.b32 	%f10, %r31;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f11, %f9, %f10;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r32, %f11;
+	shfl.sync.bfly.b32	%r33, %r32, 2, 31, -1;
+	mov.b32 	%f12, %r33;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f13, %f11, %f12;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r34, %f13;
+	shfl.sync.bfly.b32	%r35, %r34, 1, 31, -1;
+	mov.b32 	%f14, %r35;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f15, %f13, %f14;
+	.loc	2 286 36                        // standard.py:286:36
+	setp.eq.s32 	%p2, %r13, 0;
+	shr.u32 	%r36, %r12, 3;
+	and.b32  	%r37, %r36, 4;
+	mov.u32 	%r38, global_smem;
+	add.s32 	%r3, %r38, %r37;
+	mov.b32 	%r4, %f15;
+	// begin inline asm
+	@%p2 st.shared.b32 [ %r3 + 0 ], %r4;
+	// end inline asm
+	bar.sync 	0;
+	setp.lt.s32 	%p3, %r12, 2;
+	shl.b32 	%r39, %r12, 2;
+	add.s32 	%r6, %r38, %r39;
+	// begin inline asm
+	@%p3 ld.shared.b32 %r5, [ %r6 + 0 ];
+	// end inline asm
+	mov.b32 	%f16, %r5;
+	shfl.sync.bfly.b32	%r40, %r5, 1, 31, -1;
+	mov.b32 	%f17, %r40;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f18, %f16, %f17;
+	.loc	2 286 36                        // standard.py:286:36
+	and.b32  	%r41, %r12, 1;
+	setp.eq.b32 	%p6, %r41, 1;
+	not.pred 	%p7, %p6;
+	and.pred  	%p4, %p3, %p7;
+	mov.b32 	%r8, %f18;
+	// begin inline asm
+	@%p4 st.shared.b32 [ %r6 + 0 ], %r8;
+	// end inline asm
+	bar.sync 	0;
+	ld.shared.u32 	%r9, [global_smem];
+$L__tmp2:
+	.loc	1 44 25                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:44:25
+	mul.wide.s32 	%rd6, %r10, 4;
+	add.s64 	%rd2, %rd4, %rd6;
+	.loc	1 44 36                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:44:36
+	and.b32  	%r42, %r12, 63;
+	setp.eq.s32 	%p8, %r42, 0;
+	and.pred  	%p5, %p8, %p1;
+	// begin inline asm
+	@%p5 st.global.b32 [ %rd2 + 0 ], { %r9 };
+	// end inline asm
+	.loc	1 44 4                          // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:44:4
+	ret;
+$L__tmp3:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py"
+	.file	2 "/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 241                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xea DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 116
+.b8 121
+.b8 100
+.b8 106
+.b8 97
+.b8 55
+.b8 107
+.b8 116
+.b8 114
+.b8 101
+.b8 119
+.b8 120
+.b8 113
+.b8 101
+.b8 104
+.b8 107
+.b8 105
+.b8 122
+.b8 106
+.b8 105
+.b8 55
+.b8 113
+.b8 122
+.b8 105
+.b8 52
+.b8 119
+.b8 122
+.b8 113
+.b8 107
+.b8 106
+.b8 99
+.b8 115
+.b8 119
+.b8 106
+.b8 107
+.b8 113
+.b8 110
+.b8 120
+.b8 97
+.b8 108
+.b8 102
+.b8 101
+.b8 121
+.b8 51
+.b8 109
+.b8 111
+.b8 104
+.b8 103
+.b8 103
+.b8 111
+.b8 116
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 57
+.b8 48
+.b8 98
+.b8 52
+.b8 53
+.b8 98
+.b8 99
+.b8 101
+.b8 48
+.b8 50
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 116
+.b8 121
+.b8 0
+.b8 2                                   // Abbrev [2] 0x9f:0x27 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 109
+.b8 101
+.b8 97
+.b8 110
+.b8 95
+.b8 112
+.b8 111
+.b8 119
+.b8 95
+.b8 52
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xc6:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 159                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xdb:0x18 DW_TAG_inlined_subroutine
+.b32 159                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp2                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 43                                  // DW_AT_call_line
+.b8 25                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.ttgir

@@ -0,0 +1,82 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 2], threadsPerWarp = [1, 32], warpsPerCTA = [1, 2], order = [1, 0]}>
+#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 2], order = [0, 1]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)
+#loc1 = loc(unknown)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:25)
+#loc31 = loc(callsite(#loc1 at #loc21))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 2 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mean_pow_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1x128xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<1x128xbf16, #blocked> loc(#loc1)
+    %c7168_i32 = arith.constant 7168 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<5120> : tensor<1x128xi32, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<128> : tensor<1x128xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.cmpi slt, %0, %arg2 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x128xi32, #blocked> loc(#loc4)
+    %4 = arith.remsi %0, %c8_i32 : i32 loc(#loc5)
+    %5 = arith.divsi %0, %c8_i32 : i32 loc(#loc6)
+    %6 = arith.cmpi slt, %3, %cst_2 : tensor<1x128xi32, #blocked> loc(#loc7)
+    %7 = arith.addi %3, %cst_1 : tensor<1x128xi32, #blocked> loc(#loc8)
+    %8 = arith.muli %4, %c128_i32 : i32 loc(#loc9)
+    %9 = tt.splat %8 : i32 -> tensor<1x128xi32, #blocked> loc(#loc27)
+    %10 = arith.addi %7, %9 : tensor<1x128xi32, #blocked> loc(#loc10)
+    %11 = arith.muli %5, %c7168_i32 : i32 loc(#loc11)
+    %12 = tt.splat %11 : i32 -> tensor<1x128xi32, #blocked> loc(#loc28)
+    %13 = arith.addi %10, %12 : tensor<1x128xi32, #blocked> loc(#loc12)
+    %14 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1x128x!tt.ptr<bf16>, #blocked> loc(#loc13)
+    %15 = tt.addptr %14, %13 : tensor<1x128x!tt.ptr<bf16>, #blocked>, tensor<1x128xi32, #blocked> loc(#loc13)
+    %16 = tt.splat %1 : i1 -> tensor<1x128xi1, #blocked> loc(#loc29)
+    %17 = arith.andi %6, %16 : tensor<1x128xi1, #blocked> loc(#loc14)
+    %18 = tt.load %15, %17, %cst_0 evictionPolicy = evict_first : tensor<1x128x!tt.ptr<bf16>, #blocked> loc(#loc15)
+    %19 = arith.extf %18 : tensor<1x128xbf16, #blocked> to tensor<1x128xf32, #blocked> loc(#loc16)
+    %20 = arith.mulf %19, %19 : tensor<1x128xf32, #blocked> loc(#loc17)
+    %21 = arith.addf %20, %cst : tensor<1x128xf32, #blocked> loc(#loc18)
+    %22 = arith.select %17, %21, %cst : tensor<1x128xi1, #blocked>, tensor<1x128xf32, #blocked> loc(#loc19)
+    %23 = "tt.reduce"(%22) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc21)), %arg5: f32 loc(callsite(#loc1 at #loc21))):
+      %29 = arith.addf %arg4, %arg5 : f32 loc(#loc33)
+      tt.reduce.return %29 : f32 loc(#loc30)
+    }) : (tensor<1x128xf32, #blocked>) -> tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc30)
+    %24 = ttg.convert_layout %23 : tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc23)
+    %25 = tt.expand_dims %24 {axis = 1 : i32} : tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<1x1xf32, #blocked1> loc(#loc23)
+    %26 = tt.addptr %arg1, %0 : !tt.ptr<f32>, i32 loc(#loc24)
+    %27 = tt.splat %26 : !tt.ptr<f32> -> tensor<1x1x!tt.ptr<f32>, #blocked1> loc(#loc25)
+    %28 = tt.splat %1 : i1 -> tensor<1x1xi1, #blocked1> loc(#loc25)
+    tt.store %27, %25, %28 : tensor<1x1x!tt.ptr<f32>, #blocked1> loc(#loc25)
+    tt.return loc(#loc26)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":24:21)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:37)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":27:19)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":28:19)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":33:29)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:41)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:52)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:48)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:62)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:57)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:34)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:77)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:67)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:129)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":39:22)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":41:23)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:48)
+#loc20 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc22 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:28)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:25)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:36)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:4)
+#loc27 = loc(fused[#loc10, #loc9])
+#loc28 = loc(fused[#loc12, #loc11])
+#loc29 = loc(fused[#loc14, #loc3])
+#loc30 = loc(callsite(#loc20 at #loc21))
+#loc32 = loc(callsite(#loc22 at #loc20))
+#loc33 = loc(callsite(#loc32 at #loc21))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KFH4YU7RBMXGCWNOPEUKI6MSGWONPGOOBZKQPWWGVD2RV66ONYPA/triton_red_fused__to_copy_mean_pow_4.ttir

@@ -0,0 +1,80 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)
+#loc1 = loc(unknown)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:25)
+#loc32 = loc(callsite(#loc1 at #loc22))
+module {
+  tt.func public @triton_red_fused__to_copy_mean_pow_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)) attributes {noinline = false} {
+    %c7168_i32 = arith.constant 7168 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc1)
+    %cst = arith.constant dense<0.000000e+00> : tensor<1x128xbf16> loc(#loc1)
+    %cst_0 = arith.constant dense<5120> : tensor<1x128xi32> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<1x128xi32> loc(#loc1)
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<1x128xf32> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.cmpi slt, %0, %arg2 : i32 loc(#loc3)
+    %2 = tt.splat %1 : i1 -> tensor<1x1xi1> loc(#loc3)
+    %3 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32> loc(#loc4)
+    %4 = tt.expand_dims %3 {axis = 0 : i32} : tensor<128xi32> -> tensor<1x128xi32> loc(#loc5)
+    %5 = arith.remsi %0, %c8_i32 : i32 loc(#loc6)
+    %6 = arith.divsi %0, %c8_i32 : i32 loc(#loc7)
+    %7 = arith.cmpi slt, %4, %cst_1 : tensor<1x128xi32> loc(#loc8)
+    %8 = arith.addi %4, %cst_0 : tensor<1x128xi32> loc(#loc9)
+    %9 = arith.muli %5, %c128_i32 : i32 loc(#loc10)
+    %10 = tt.splat %9 : i32 -> tensor<1x128xi32> loc(#loc28)
+    %11 = arith.addi %8, %10 : tensor<1x128xi32> loc(#loc11)
+    %12 = arith.muli %6, %c7168_i32 : i32 loc(#loc12)
+    %13 = tt.splat %12 : i32 -> tensor<1x128xi32> loc(#loc29)
+    %14 = arith.addi %11, %13 : tensor<1x128xi32> loc(#loc13)
+    %15 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1x128x!tt.ptr<bf16>> loc(#loc14)
+    %16 = tt.addptr %15, %14 : tensor<1x128x!tt.ptr<bf16>>, tensor<1x128xi32> loc(#loc14)
+    %17 = tt.splat %1 : i1 -> tensor<1x128xi1> loc(#loc30)
+    %18 = arith.andi %7, %17 : tensor<1x128xi1> loc(#loc15)
+    %19 = tt.load %16, %18, %cst evictionPolicy = evict_first : tensor<1x128x!tt.ptr<bf16>> loc(#loc16)
+    %20 = arith.extf %19 : tensor<1x128xbf16> to tensor<1x128xf32> loc(#loc17)
+    %21 = arith.mulf %20, %20 : tensor<1x128xf32> loc(#loc18)
+    %22 = arith.addf %21, %cst_2 : tensor<1x128xf32> loc(#loc19)
+    %23 = arith.select %18, %22, %cst_2 : tensor<1x128xi1>, tensor<1x128xf32> loc(#loc20)
+    %24 = "tt.reduce"(%23) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc22)), %arg5: f32 loc(callsite(#loc1 at #loc22))):
+      %28 = arith.addf %arg4, %arg5 : f32 loc(#loc34)
+      tt.reduce.return %28 : f32 loc(#loc31)
+    }) : (tensor<1x128xf32>) -> tensor<1xf32> loc(#loc31)
+    %25 = tt.expand_dims %24 {axis = 1 : i32} : tensor<1xf32> -> tensor<1x1xf32> loc(#loc24)
+    %26 = tt.addptr %arg1, %0 : !tt.ptr<f32>, i32 loc(#loc25)
+    %27 = tt.splat %26 : !tt.ptr<f32> -> tensor<1x1x!tt.ptr<f32>> loc(#loc25)
+    tt.store %27, %25, %2 : tensor<1x1x!tt.ptr<f32>> loc(#loc26)
+    tt.return loc(#loc27)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":24:21)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:27)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:37)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":27:19)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":28:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":33:29)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:41)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:52)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:48)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:62)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:57)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:34)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:77)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:67)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:129)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":39:22)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":41:23)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:48)
+#loc21 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc23 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:28)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:25)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:36)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:4)
+#loc28 = loc(fused[#loc11, #loc10])
+#loc29 = loc(fused[#loc13, #loc12])
+#loc30 = loc(fused[#loc15, #loc3])
+#loc31 = loc(callsite(#loc21 at #loc22))
+#loc33 = loc(callsite(#loc23 at #loc21))
+#loc34 = loc(callsite(#loc33 at #loc22))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/__grp__triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_3.ttir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.ttir", "triton_red_fused__to_copy_mean_pow_3.ttgir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.ttgir", "triton_red_fused__to_copy_mean_pow_3.llir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.llir", "triton_red_fused__to_copy_mean_pow_3.ptx": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.ptx", "triton_red_fused__to_copy_mean_pow_3.cubin": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.cubin", "triton_red_fused__to_copy_mean_pow_3.json": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.json"}}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"hash": "5676a20ad1cc83f777665d23ccefbb265b26eb8f3c0f84ae82823670c3cd02b9", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 16, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 256, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_mean_pow_3"}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.ptx

@@ -0,0 +1,462 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_mean_pow_3 // -- Begin function triton_red_fused__to_copy_mean_pow_3
+.extern .shared .align 16 .b8 global_smem[];
+                                        // @triton_red_fused__to_copy_mean_pow_3
+.visible .entry triton_red_fused__to_copy_mean_pow_3(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_1,
+	.param .u32 triton_red_fused__to_copy_mean_pow_3_param_2,
+	.param .u32 triton_red_fused__to_copy_mean_pow_3_param_3,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_4
+)
+.reqntid 512, 1, 1
+{
+	.reg .pred 	%p<7>;
+	.reg .b16 	%rs<17>;
+	.reg .b32 	%r<50>;
+	.reg .f32 	%f<47>;
+	.reg .b64 	%rd<8>;
+	.loc	1 18 0                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:18:0
+
+// %bb.0:
+	ld.param.u64 	%rd4, [triton_red_fused__to_copy_mean_pow_3_param_0];
+	ld.param.u64 	%rd5, [triton_red_fused__to_copy_mean_pow_3_param_1];
+$L__tmp0:
+	.loc	1 22 28                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:22:28
+	mov.u32 	%r20, %ctaid.x;
+	.loc	1 22 33                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:22:33
+	shl.b32 	%r21, %r20, 6;
+	ld.param.u32 	%r22, [triton_red_fused__to_copy_mean_pow_3_param_2];
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	mov.u32 	%r23, %tid.x;
+	bfe.u32 	%r24, %r23, 3, 6;
+	.loc	1 23 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:23
+	or.b32  	%r25, %r24, %r21;
+	.loc	1 24 21                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:24:21
+	setp.lt.s32 	%p1, %r25, %r22;
+	.loc	1 25 37                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:25:37
+	shl.b32 	%r26, %r23, 3;
+	and.b32  	%r27, %r26, 56;
+	.loc	1 28 19                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:28:19
+	mul.hi.s32 	%r28, %r25, 1717986919;
+	shr.u32 	%r29, %r28, 31;
+	shr.s32 	%r30, %r28, 4;
+	add.s32 	%r31, %r30, %r29;
+	.loc	1 27 19                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:27:19
+	mul.lo.s32 	%r32, %r31, 40;
+	sub.s32 	%r33, %r25, %r32;
+	.loc	1 37 45                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:45
+	shl.b32 	%r34, %r33, 7;
+	or.b32  	%r35, %r34, %r27;
+	mad.lo.s32 	%r36, %r31, 7168, %r35;
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	mul.wide.s32 	%rd6, %r36, 2;
+	add.s64 	%rd1, %rd4, %rd6;
+	mov.b32 	%r5, 0;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r1, %r5;
+	mov.u32 %r2, %r5;
+	mov.u32 %r3, %r5;
+	mov.u32 %r4, %r5;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r1, %r2, %r3, %r4 }, [ %rd1 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd2, %rd1, 128;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u32 %r9, %r5;
+	mov.u32 %r10, %r5;
+	mov.u32 %r11, %r5;
+	mov.u32 %r12, %r5;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r9, %r10, %r11, %r12 }, [ %rd2 + 0 ];
+	// end inline asm
+	.loc	1 37 122                        // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:122
+	mov.b32 	{%rs1, %rs2}, %r1;
+	cvt.f32.bf16 	%f1, %rs1;
+	cvt.f32.bf16 	%f2, %rs2;
+	mov.b32 	{%rs3, %rs4}, %r9;
+	cvt.f32.bf16 	%f3, %rs4;
+	cvt.f32.bf16 	%f4, %rs3;
+	.loc	1 39 22                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:39:22
+	mul.f32 	%f5, %f4, %f4;
+	mul.f32 	%f6, %f3, %f3;
+	.loc	1 41 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:41:23
+	fma.rn.f32 	%f7, %f2, %f2, %f6;
+	fma.rn.f32 	%f8, %f1, %f1, %f5;
+	.loc	1 37 122                        // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:122
+	mov.b32 	{%rs5, %rs6}, %r2;
+	cvt.f32.bf16 	%f9, %rs5;
+	cvt.f32.bf16 	%f10, %rs6;
+	mov.b32 	{%rs7, %rs8}, %r10;
+	cvt.f32.bf16 	%f11, %rs8;
+	cvt.f32.bf16 	%f12, %rs7;
+	.loc	1 39 22                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:39:22
+	mul.f32 	%f13, %f12, %f12;
+	mul.f32 	%f14, %f11, %f11;
+	.loc	1 41 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:41:23
+	fma.rn.f32 	%f15, %f10, %f10, %f14;
+	fma.rn.f32 	%f16, %f9, %f9, %f13;
+	.loc	1 37 122                        // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:122
+	mov.b32 	{%rs9, %rs10}, %r3;
+	cvt.f32.bf16 	%f17, %rs9;
+	cvt.f32.bf16 	%f18, %rs10;
+	mov.b32 	{%rs11, %rs12}, %r11;
+	cvt.f32.bf16 	%f19, %rs12;
+	cvt.f32.bf16 	%f20, %rs11;
+	.loc	1 39 22                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:39:22
+	mul.f32 	%f21, %f20, %f20;
+	mul.f32 	%f22, %f19, %f19;
+	.loc	1 41 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:41:23
+	fma.rn.f32 	%f23, %f18, %f18, %f22;
+	fma.rn.f32 	%f24, %f17, %f17, %f21;
+	.loc	1 37 122                        // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:122
+	mov.b32 	{%rs13, %rs14}, %r4;
+	cvt.f32.bf16 	%f25, %rs13;
+	cvt.f32.bf16 	%f26, %rs14;
+	mov.b32 	{%rs15, %rs16}, %r12;
+	cvt.f32.bf16 	%f27, %rs16;
+	cvt.f32.bf16 	%f28, %rs15;
+	.loc	1 39 22                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:39:22
+	mul.f32 	%f29, %f28, %f28;
+	mul.f32 	%f30, %f27, %f27;
+	.loc	1 41 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:41:23
+	fma.rn.f32 	%f31, %f26, %f26, %f30;
+	fma.rn.f32 	%f32, %f25, %f25, %f29;
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	and.b32  	%r37, %r23, 63;
+	.loc	1 23 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:23
+	or.b32  	%r38, %r21, %r37;
+	.loc	1 24 21                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:24:21
+	setp.lt.s32 	%p5, %r38, %r22;
+$L__tmp1:
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f33, %f8, %f7;
+	add.f32 	%f34, %f16, %f33;
+	add.f32 	%f35, %f15, %f34;
+	add.f32 	%f36, %f24, %f35;
+	add.f32 	%f37, %f23, %f36;
+	add.f32 	%f38, %f32, %f37;
+	add.f32 	%f39, %f31, %f38;
+	selp.f32 	%f40, %f39, 0f00000000, %p1;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r39, %f40;
+	shfl.sync.bfly.b32	%r40, %r39, 4, 31, -1;
+	mov.b32 	%f41, %r40;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f42, %f40, %f41;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r41, %f42;
+	shfl.sync.bfly.b32	%r42, %r41, 2, 31, -1;
+	mov.b32 	%f43, %r42;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f44, %f42, %f43;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r43, %f44;
+	shfl.sync.bfly.b32	%r44, %r43, 1, 31, -1;
+	mov.b32 	%f45, %r44;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f46, %f44, %f45;
+$L__tmp2:
+	.loc	1 43 28                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:43:28
+	shl.b32 	%r45, %r24, 2;
+	mov.u32 	%r46, global_smem;
+	add.s32 	%r17, %r46, %r45;
+	mov.b32 	%r18, %f46;
+	mov.pred 	%p3, -1;
+	// begin inline asm
+	@%p3 st.shared.b32 [ %r17 + 0 ], %r18;
+	// end inline asm
+	bar.sync 	0;
+	shl.b32 	%r47, %r37, 2;
+	add.s32 	%r48, %r46, %r47;
+	ld.shared.u32 	%r19, [%r48];
+	.loc	1 44 25                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:25
+	mul.wide.s32 	%rd7, %r38, 4;
+	add.s64 	%rd3, %rd5, %rd7;
+	.loc	1 44 36                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:36
+	and.b32  	%r49, %r23, 448;
+	setp.eq.s32 	%p6, %r49, 0;
+	and.pred  	%p4, %p6, %p5;
+	// begin inline asm
+	@%p4 st.global.b32 [ %rd3 + 0 ], { %r19 };
+	// end inline asm
+	.loc	1 44 4                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:4
+	ret;
+$L__tmp3:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py"
+	.file	2 "/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 241                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xea DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 108
+.b8 107
+.b8 98
+.b8 102
+.b8 110
+.b8 51
+.b8 118
+.b8 110
+.b8 116
+.b8 114
+.b8 106
+.b8 114
+.b8 111
+.b8 104
+.b8 55
+.b8 114
+.b8 118
+.b8 54
+.b8 112
+.b8 97
+.b8 112
+.b8 109
+.b8 102
+.b8 55
+.b8 51
+.b8 118
+.b8 119
+.b8 122
+.b8 102
+.b8 120
+.b8 109
+.b8 109
+.b8 105
+.b8 115
+.b8 113
+.b8 112
+.b8 50
+.b8 105
+.b8 53
+.b8 55
+.b8 113
+.b8 51
+.b8 100
+.b8 105
+.b8 113
+.b8 53
+.b8 121
+.b8 112
+.b8 51
+.b8 103
+.b8 120
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 57
+.b8 48
+.b8 98
+.b8 52
+.b8 53
+.b8 98
+.b8 99
+.b8 101
+.b8 48
+.b8 50
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 108
+.b8 107
+.b8 0
+.b8 2                                   // Abbrev [2] 0x9f:0x27 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 109
+.b8 101
+.b8 97
+.b8 110
+.b8 95
+.b8 112
+.b8 111
+.b8 119
+.b8 95
+.b8 51
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xc6:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 159                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xdb:0x18 DW_TAG_inlined_subroutine
+.b32 159                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp2                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 43                                  // DW_AT_call_line
+.b8 25                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.ttgir

@@ -0,0 +1,103 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 8], threadsPerWarp = [4, 8], warpsPerCTA = [16, 1], order = [1, 0]}>
+#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 8], order = [0, 1]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)
+#loc1 = loc(unknown)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:25)
+#loc33 = loc(callsite(#loc1 at #loc26))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 16 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mean_pow_3(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x64xf32, #blocked> loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<64x64xbf16, #blocked> loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<40> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<7168> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<128> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_4 = arith.constant dense<128> : tensor<1x64xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c64_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc4)
+    %3 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc4)
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64x1xi32, #blocked> loc(#loc4)
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<64x1xi32, #blocked1> loc(#loc4)
+    %6 = tt.splat %1 : i32 -> tensor<64x1xi32, #blocked> loc(#loc5)
+    %7 = tt.splat %1 : i32 -> tensor<64x1xi32, #blocked1> loc(#loc5)
+    %8 = arith.addi %6, %4 : tensor<64x1xi32, #blocked> loc(#loc5)
+    %9 = arith.addi %7, %5 : tensor<64x1xi32, #blocked1> loc(#loc5)
+    %10 = tt.splat %arg2 : i32 -> tensor<64x1xi32, #blocked> loc(#loc6)
+    %11 = tt.splat %arg2 : i32 -> tensor<64x1xi32, #blocked1> loc(#loc6)
+    %12 = arith.cmpi slt, %8, %10 : tensor<64x1xi32, #blocked> loc(#loc6)
+    %13 = arith.cmpi slt, %9, %11 : tensor<64x1xi32, #blocked1> loc(#loc6)
+    %14 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc7)
+    %15 = tt.expand_dims %14 {axis = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x64xi32, #blocked> loc(#loc7)
+    %16 = arith.remsi %8, %cst_1 : tensor<64x1xi32, #blocked> loc(#loc8)
+    %17 = arith.divsi %8, %cst_1 : tensor<64x1xi32, #blocked> loc(#loc9)
+    %18 = arith.muli %16, %cst_3 : tensor<64x1xi32, #blocked> loc(#loc10)
+    %19 = tt.broadcast %18 : tensor<64x1xi32, #blocked> -> tensor<64x64xi32, #blocked> loc(#loc11)
+    %20 = arith.muli %17, %cst_2 : tensor<64x1xi32, #blocked> loc(#loc12)
+    %21 = tt.broadcast %20 : tensor<64x1xi32, #blocked> -> tensor<64x64xi32, #blocked> loc(#loc13)
+    %22 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<64x64x!tt.ptr<bf16>, #blocked> loc(#loc14)
+    %23 = tt.broadcast %12 : tensor<64x1xi1, #blocked> -> tensor<64x64xi1, #blocked> loc(#loc15)
+    %24 = scf.for %arg4 = %c0_i32 to %c128_i32 step %c64_i32 iter_args(%arg5 = %cst) -> (tensor<64x64xf32, #blocked>)  : i32 {
+      %30 = tt.splat %arg4 : i32 -> tensor<1x64xi32, #blocked> loc(#loc17)
+      %31 = arith.addi %30, %15 : tensor<1x64xi32, #blocked> loc(#loc17)
+      %32 = arith.cmpi slt, %31, %cst_4 : tensor<1x64xi32, #blocked> loc(#loc18)
+      %33 = tt.broadcast %31 : tensor<1x64xi32, #blocked> -> tensor<64x64xi32, #blocked> loc(#loc11)
+      %34 = arith.addi %33, %19 : tensor<64x64xi32, #blocked> loc(#loc11)
+      %35 = arith.addi %34, %21 : tensor<64x64xi32, #blocked> loc(#loc13)
+      %36 = tt.addptr %22, %35 : tensor<64x64x!tt.ptr<bf16>, #blocked>, tensor<64x64xi32, #blocked> loc(#loc14)
+      %37 = tt.broadcast %32 : tensor<1x64xi1, #blocked> -> tensor<64x64xi1, #blocked> loc(#loc15)
+      %38 = arith.andi %37, %23 : tensor<64x64xi1, #blocked> loc(#loc15)
+      %39 = tt.load %36, %38, %cst_0 evictionPolicy = evict_first : tensor<64x64x!tt.ptr<bf16>, #blocked> loc(#loc19)
+      %40 = arith.extf %39 : tensor<64x64xbf16, #blocked> to tensor<64x64xf32, #blocked> loc(#loc20)
+      %41 = arith.mulf %40, %40 : tensor<64x64xf32, #blocked> loc(#loc21)
+      %42 = arith.addf %arg5, %41 : tensor<64x64xf32, #blocked> loc(#loc22)
+      %43 = arith.select %38, %42, %arg5 : tensor<64x64xi1, #blocked>, tensor<64x64xf32, #blocked> loc(#loc23)
+      scf.yield %43 : tensor<64x64xf32, #blocked> loc(#loc24)
+    } loc(#loc16)
+    %25 = "tt.reduce"(%24) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc26)), %arg5: f32 loc(callsite(#loc1 at #loc26))):
+      %30 = arith.addf %arg4, %arg5 : f32 loc(#loc35)
+      tt.reduce.return %30 : f32 loc(#loc32)
+    }) : (tensor<64x64xf32, #blocked>) -> tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc32)
+    %26 = ttg.convert_layout %25 : tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc28)
+    %27 = tt.expand_dims %26 {axis = 1 : i32} : tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<64x1xf32, #blocked1> loc(#loc28)
+    %28 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>, #blocked1> loc(#loc29)
+    %29 = tt.addptr %28, %9 : tensor<64x1x!tt.ptr<f32>, #blocked1>, tensor<64x1xi32, #blocked1> loc(#loc29)
+    tt.store %29, %27, %13 : tensor<64x1x!tt.ptr<f32>, #blocked1> loc(#loc30)
+    tt.return loc(#loc31)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:44)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":24:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:37)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":27:19)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":28:19)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:45)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:41)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:55)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:50)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:34)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:70)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":31:40)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":32:31)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":33:29)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:60)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:122)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":39:22)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":41:23)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:48)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:8)
+#loc25 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc27 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:28)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:25)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:36)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:4)
+#loc32 = loc(callsite(#loc25 at #loc26))
+#loc34 = loc(callsite(#loc27 at #loc25))
+#loc35 = loc(callsite(#loc34 at #loc26))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/KZ3KECWRZSB7O53GLUR4Z353EZNSN24PHQHYJLUCQI3HBQ6NAK4Q/triton_red_fused__to_copy_mean_pow_3.ttir

@@ -0,0 +1,94 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)
+#loc1 = loc(unknown)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:25)
+#loc34 = loc(callsite(#loc1 at #loc27))
+module {
+  tt.func public @triton_red_fused__to_copy_mean_pow_3(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x64xbf16> loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<7168> : tensor<64x1xi32> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<64x1xi32> loc(#loc1)
+    %cst_2 = arith.constant dense<128> : tensor<1x64xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<64x64xf32> loc(#loc1)
+    %cst_4 = arith.constant dense<40> : tensor<64x1xi32> loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c64_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : tensor<64xi32> -> tensor<64x1xi32> loc(#loc5)
+    %4 = tt.splat %1 : i32 -> tensor<64x1xi32> loc(#loc6)
+    %5 = arith.addi %4, %3 : tensor<64x1xi32> loc(#loc6)
+    %6 = tt.splat %arg2 : i32 -> tensor<64x1xi32> loc(#loc7)
+    %7 = arith.cmpi slt, %5, %6 : tensor<64x1xi32> loc(#loc7)
+    %8 = tt.expand_dims %2 {axis = 0 : i32} : tensor<64xi32> -> tensor<1x64xi32> loc(#loc8)
+    %9 = arith.remsi %5, %cst_4 : tensor<64x1xi32> loc(#loc9)
+    %10 = arith.divsi %5, %cst_4 : tensor<64x1xi32> loc(#loc10)
+    %11 = scf.for %arg4 = %c0_i32 to %c128_i32 step %c64_i32 iter_args(%arg5 = %cst_3) -> (tensor<64x64xf32>)  : i32 {
+      %16 = tt.splat %arg4 : i32 -> tensor<1x64xi32> loc(#loc12)
+      %17 = arith.addi %16, %8 : tensor<1x64xi32> loc(#loc12)
+      %18 = arith.cmpi slt, %17, %cst_2 : tensor<1x64xi32> loc(#loc13)
+      %19 = arith.muli %9, %cst_1 : tensor<64x1xi32> loc(#loc14)
+      %20 = tt.broadcast %17 : tensor<1x64xi32> -> tensor<64x64xi32> loc(#loc15)
+      %21 = tt.broadcast %19 : tensor<64x1xi32> -> tensor<64x64xi32> loc(#loc15)
+      %22 = arith.addi %20, %21 : tensor<64x64xi32> loc(#loc15)
+      %23 = arith.muli %10, %cst_0 : tensor<64x1xi32> loc(#loc16)
+      %24 = tt.broadcast %23 : tensor<64x1xi32> -> tensor<64x64xi32> loc(#loc17)
+      %25 = arith.addi %22, %24 : tensor<64x64xi32> loc(#loc17)
+      %26 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<64x64x!tt.ptr<bf16>> loc(#loc18)
+      %27 = tt.addptr %26, %25 : tensor<64x64x!tt.ptr<bf16>>, tensor<64x64xi32> loc(#loc18)
+      %28 = tt.broadcast %18 : tensor<1x64xi1> -> tensor<64x64xi1> loc(#loc19)
+      %29 = tt.broadcast %7 : tensor<64x1xi1> -> tensor<64x64xi1> loc(#loc19)
+      %30 = arith.andi %28, %29 : tensor<64x64xi1> loc(#loc19)
+      %31 = tt.load %27, %30, %cst evictionPolicy = evict_first : tensor<64x64x!tt.ptr<bf16>> loc(#loc20)
+      %32 = arith.extf %31 : tensor<64x64xbf16> to tensor<64x64xf32> loc(#loc21)
+      %33 = arith.mulf %32, %32 : tensor<64x64xf32> loc(#loc22)
+      %34 = arith.addf %arg5, %33 : tensor<64x64xf32> loc(#loc23)
+      %35 = arith.select %30, %34, %arg5 : tensor<64x64xi1>, tensor<64x64xf32> loc(#loc24)
+      scf.yield %35 : tensor<64x64xf32> loc(#loc25)
+    } loc(#loc11)
+    %12 = "tt.reduce"(%11) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc27)), %arg5: f32 loc(callsite(#loc1 at #loc27))):
+      %16 = arith.addf %arg4, %arg5 : f32 loc(#loc36)
+      tt.reduce.return %16 : f32 loc(#loc33)
+    }) : (tensor<64x64xf32>) -> tensor<64xf32> loc(#loc33)
+    %13 = tt.expand_dims %12 {axis = 1 : i32} : tensor<64xf32> -> tensor<64x1xf32> loc(#loc29)
+    %14 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>> loc(#loc30)
+    %15 = tt.addptr %14, %5 : tensor<64x1x!tt.ptr<f32>>, tensor<64x1xi32> loc(#loc30)
+    tt.store %15, %13, %7 : tensor<64x1x!tt.ptr<f32>> loc(#loc31)
+    tt.return loc(#loc32)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:44)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:23)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":24:21)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:37)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":27:19)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":28:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":31:40)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":32:31)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":33:29)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:45)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:41)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:55)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:50)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:34)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:70)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:60)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:122)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":39:22)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":41:23)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:48)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:8)
+#loc26 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc28 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:28)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:25)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:36)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:4)
+#loc33 = loc(callsite(#loc26 at #loc27))
+#loc35 = loc(callsite(#loc28 at #loc26))
+#loc36 = loc(callsite(#loc35 at #loc27))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/MK3FJPCFNSMUI3HT5RCMHKKN2VYBEGXR6NAGCJWY3YJGZLEJQX3Q/triton_poi_fused_add_mul_sub_4.ttgir

@@ -0,0 +1,196 @@
+#blocked = #ttg.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0)
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_poi_fused_add_mul_sub_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0), %arg2: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0), %arg3: !tt.ptr<i64> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0), %arg4: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0), %arg5: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0), %arg6: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0), %arg7: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<1.280000e+02> : tensor<1024xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<9.99999997E-7> : tensor<1024xf32, #blocked> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<40960> : tensor<1024xi64, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<0> : tensor<1024xi64, #blocked> loc(#loc1)
+    %c1024_i32 = arith.constant 1024 : i32 loc(#loc1)
+    %cst_4 = arith.constant dense<64> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_5 = arith.constant dense<8> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_6 = arith.constant dense<512> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_7 = arith.constant dense<5120> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_8 = arith.constant dense<128> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_9 = arith.constant dense<7168> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_10 = arith.constant dense<5184> : tensor<1024xi32, #blocked> loc(#loc1)
+    %cst_11 = arith.constant dense<true> : tensor<1024xi1, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c1024_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked> loc(#loc4)
+    %3 = tt.splat %1 : i32 -> tensor<1024xi32, #blocked> loc(#loc5)
+    %4 = arith.addi %3, %2 : tensor<1024xi32, #blocked> loc(#loc5)
+    %5 = tt.splat %arg7 : i32 -> tensor<1024xi32, #blocked> loc(#loc6)
+    %6 = arith.cmpi slt, %4, %5 : tensor<1024xi32, #blocked> loc(#loc6)
+    %7 = arith.remsi %4, %cst_4 : tensor<1024xi32, #blocked> loc(#loc7)
+    %8 = arith.divsi %4, %cst_4 : tensor<1024xi32, #blocked> loc(#loc8)
+    %9 = arith.remsi %8, %cst_5 : tensor<1024xi32, #blocked> loc(#loc9)
+    %10 = arith.divsi %4, %cst_6 : tensor<1024xi32, #blocked> loc(#loc10)
+    %11 = arith.addi %7, %cst_7 : tensor<1024xi32, #blocked> loc(#loc11)
+    %12 = arith.muli %9, %cst_8 : tensor<1024xi32, #blocked> loc(#loc12)
+    %13 = arith.addi %11, %12 : tensor<1024xi32, #blocked> loc(#loc13)
+    %14 = arith.muli %10, %cst_9 : tensor<1024xi32, #blocked> loc(#loc14)
+    %15 = arith.addi %13, %14 : tensor<1024xi32, #blocked> loc(#loc15)
+    %16 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc16)
+    %17 = tt.addptr %16, %15 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc16)
+    %18 = tt.load %17, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc17)
+    %19 = arith.extf %18 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc18)
+    %20 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<1024x!tt.ptr<f32>, #blocked> loc(#loc19)
+    %21 = tt.addptr %20, %8 : tensor<1024x!tt.ptr<f32>, #blocked>, tensor<1024xi32, #blocked> loc(#loc19)
+    %22 = tt.load %21, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<f32>, #blocked> loc(#loc20)
+    %23 = tt.splat %arg2 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc21)
+    %24 = tt.addptr %23, %7 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc21)
+    %25 = tt.load %24, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc22)
+    %26 = arith.extf %25 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc23)
+    %27 = tt.splat %arg3 : !tt.ptr<i64> -> tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc24)
+    %28 = tt.addptr %27, %10 : tensor<1024x!tt.ptr<i64>, #blocked>, tensor<1024xi32, #blocked> loc(#loc24)
+    %29 = tt.load %28, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<i64>, #blocked> loc(#loc25)
+    %30 = arith.addi %7, %cst_10 : tensor<1024xi32, #blocked> loc(#loc26)
+    %31 = arith.addi %30, %12 : tensor<1024xi32, #blocked> loc(#loc27)
+    %32 = arith.addi %7, %cst_4 : tensor<1024xi32, #blocked> loc(#loc28)
+    %33 = arith.divsi %32, %cst_8 : tensor<1024xi32, #blocked> loc(#loc29)
+    %34 = arith.muli %33, %cst_8 : tensor<1024xi32, #blocked> loc(#loc30)
+    %35 = arith.addi %31, %34 : tensor<1024xi32, #blocked> loc(#loc31)
+    %36 = arith.addi %35, %14 : tensor<1024xi32, #blocked> loc(#loc32)
+    %37 = tt.addptr %16, %36 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc33)
+    %38 = tt.load %37, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc34)
+    %39 = arith.extf %38 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc35)
+    %40 = arith.addi %8, %33 : tensor<1024xi32, #blocked> loc(#loc36)
+    %41 = tt.addptr %20, %40 : tensor<1024x!tt.ptr<f32>, #blocked>, tensor<1024xi32, #blocked> loc(#loc37)
+    %42 = tt.load %41, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<f32>, #blocked> loc(#loc38)
+    %43 = tt.addptr %23, %32 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc39)
+    %44 = tt.load %43, %6 evictionPolicy = evict_last : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc40)
+    %45 = arith.extf %44 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc41)
+    %46 = arith.divf %22, %cst : tensor<1024xf32, #blocked> loc(#loc42)
+    %47 = arith.addf %46, %cst_0 : tensor<1024xf32, #blocked> loc(#loc43)
+    %48 = tt.extern_elementwise %47 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1024xf32, #blocked>) -> tensor<1024xf32, #blocked> loc(#loc44)
+    %49 = arith.mulf %19, %48 : tensor<1024xf32, #blocked> loc(#loc45)
+    %50 = arith.mulf %49, %26 : tensor<1024xf32, #blocked> loc(#loc46)
+    %51 = arith.addi %29, %cst_2 : tensor<1024xi64, #blocked> loc(#loc47)
+    %52 = arith.cmpi slt, %29, %cst_3 : tensor<1024xi64, #blocked> loc(#loc48)
+    %53 = arith.select %52, %51, %29 : tensor<1024xi1, #blocked>, tensor<1024xi64, #blocked> loc(#loc49)
+    %54 = arith.cmpi sge, %53, %cst_3 : tensor<1024xi64, #blocked> loc(#loc50)
+    %55 = arith.cmpi slt, %53, %cst_2 : tensor<1024xi64, #blocked> loc(#loc51)
+    %56 = arith.andi %54, %55 : tensor<1024xi1, #blocked> loc(#loc52)
+    %57 = arith.xori %6, %cst_11 : tensor<1024xi1, #blocked> loc(#loc53)
+    %58 = arith.ori %56, %57 : tensor<1024xi1, #blocked> loc(#loc54)
+    tt.assert %58, "index out of bounds: 0 <= tmp16 < 40960" : tensor<1024xi1, #blocked> loc(#loc55)
+    %59 = arith.muli %53, %cst_1 : tensor<1024xi64, #blocked> loc(#loc56)
+    %60 = arith.extsi %7 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked> loc(#loc57)
+    %61 = arith.addi %60, %59 : tensor<1024xi64, #blocked> loc(#loc57)
+    %62 = tt.splat %arg4 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc58)
+    %63 = tt.addptr %62, %61 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc58)
+    %64 = tt.load %63, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc59)
+    %65 = arith.extf %64 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc60)
+    %66 = arith.mulf %50, %65 : tensor<1024xf32, #blocked> loc(#loc61)
+    %67 = arith.divf %42, %cst : tensor<1024xf32, #blocked> loc(#loc62)
+    %68 = arith.addf %67, %cst_0 : tensor<1024xf32, #blocked> loc(#loc63)
+    %69 = tt.extern_elementwise %68 {libname = "", libpath = "", pure = true, symbol = "__nv_rsqrtf"} : (tensor<1024xf32, #blocked>) -> tensor<1024xf32, #blocked> loc(#loc64)
+    %70 = arith.mulf %39, %69 : tensor<1024xf32, #blocked> loc(#loc65)
+    %71 = arith.mulf %70, %45 : tensor<1024xf32, #blocked> loc(#loc66)
+    %72 = arith.extsi %32 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked> loc(#loc67)
+    %73 = arith.addi %72, %59 : tensor<1024xi64, #blocked> loc(#loc67)
+    %74 = tt.addptr %62, %73 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi64, #blocked> loc(#loc68)
+    %75 = tt.load %74, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc69)
+    %76 = arith.extf %75 : tensor<1024xbf16, #blocked> to tensor<1024xf32, #blocked> loc(#loc70)
+    %77 = arith.mulf %71, %76 : tensor<1024xf32, #blocked> loc(#loc71)
+    %78 = arith.subf %66, %77 : tensor<1024xf32, #blocked> loc(#loc72)
+    %79 = arith.mulf %71, %65 : tensor<1024xf32, #blocked> loc(#loc73)
+    %80 = arith.mulf %50, %76 : tensor<1024xf32, #blocked> loc(#loc74)
+    %81 = arith.addf %79, %80 : tensor<1024xf32, #blocked> loc(#loc75)
+    %82 = arith.muli %8, %cst_8 : tensor<1024xi32, #blocked> loc(#loc76)
+    %83 = arith.addi %7, %82 : tensor<1024xi32, #blocked> loc(#loc77)
+    %84 = tt.splat %arg5 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc78)
+    %85 = tt.addptr %84, %83 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc78)
+    %86 = arith.truncf %78 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked> loc(#loc79)
+    tt.store %85, %86, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc79)
+    %87 = tt.splat %arg6 : !tt.ptr<bf16> -> tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc80)
+    %88 = tt.addptr %87, %83 : tensor<1024x!tt.ptr<bf16>, #blocked>, tensor<1024xi32, #blocked> loc(#loc80)
+    %89 = arith.truncf %81 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked> loc(#loc81)
+    tt.store %88, %89, %6 : tensor<1024x!tt.ptr<bf16>, #blocked> loc(#loc81)
+    tt.return loc(#loc82)
+  } loc(#loc)
+} loc(#loc)
+#loc1 = loc(unknown)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":19:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":19:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":20:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":20:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":21:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":22:19)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":23:21)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":23:27)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":24:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:37)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:46)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:42)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:56)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:51)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:30)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:61)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":26:71)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":27:30)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":27:35)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":28:31)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":28:36)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":28:76)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":29:31)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":29:36)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:38)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:43)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:63)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:70)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:57)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:52)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:77)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:31)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:87)
+#loc35 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":30:97)
+#loc36 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":31:37)
+#loc37 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":31:31)
+#loc38 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":31:57)
+#loc39 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":32:31)
+#loc40 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":32:41)
+#loc41 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":32:81)
+#loc42 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":35:19)
+#loc43 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":37:18)
+#loc44 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":38:27)
+#loc45 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":39:18)
+#loc46 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":41:19)
+#loc47 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":43:20)
+#loc48 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":44:20)
+#loc49 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":45:35)
+#loc50 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":46:28)
+#loc51 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":46:46)
+#loc52 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":46:38)
+#loc53 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":46:58)
+#loc54 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":46:56)
+#loc55 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":46:66)
+#loc56 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":47:40)
+#loc57 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":47:36)
+#loc58 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":47:31)
+#loc59 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":47:48)
+#loc60 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":47:58)
+#loc61 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":48:20)
+#loc62 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":50:21)
+#loc63 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":51:20)
+#loc64 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":52:28)
+#loc65 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":53:20)
+#loc66 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":55:20)
+#loc67 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":56:41)
+#loc68 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":56:31)
+#loc69 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":56:53)
+#loc70 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":56:63)
+#loc71 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":57:20)
+#loc72 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":58:20)
+#loc73 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":59:20)
+#loc74 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":60:20)
+#loc75 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":61:20)
+#loc76 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":62:34)
+#loc77 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":62:30)
+#loc78 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":62:25)
+#loc79 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":62:46)
+#loc80 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":63:25)
+#loc81 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":63:46)
+#loc82 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/vb/cvbkhi7d6h5jvzml6jzvxticrzr7mw4wdcluimbdrv3xqyih3cga.py":63:4)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/__grp__triton_red_fused__to_copy_mean_pow_4.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_4.ttir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.ttir", "triton_red_fused__to_copy_mean_pow_4.ttgir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.ttgir", "triton_red_fused__to_copy_mean_pow_4.llir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.llir", "triton_red_fused__to_copy_mean_pow_4.ptx": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.ptx", "triton_red_fused__to_copy_mean_pow_4.cubin": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.cubin", "triton_red_fused__to_copy_mean_pow_4.json": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.json"}}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.llir

@@ -0,0 +1,233 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+define ptx_kernel void @triton_red_fused__to_copy_mean_pow_4(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2, i32 %3, ptr addrspace(1) readnone captures(none) %4) local_unnamed_addr !dbg !6 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %7 = shl i32 %6, 6, !dbg !10
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %9 = lshr i32 %8, 1, !dbg !11
+  %10 = and i32 %9, 63, !dbg !11
+  %11 = or disjoint i32 %10, %7, !dbg !12
+  %12 = icmp slt i32 %11, %2, !dbg !13
+  %13 = shl i32 %8, 2, !dbg !14
+  %14 = and i32 %13, 4, !dbg !14
+  %15 = sdiv i32 %11, 8, !dbg !15
+  %16 = mul i32 %15, 8, !dbg !16
+  %.decomposed = sub i32 %11, %16, !dbg !16
+  %17 = shl nsw i32 %.decomposed, 7, !dbg !17
+  %18 = mul i32 %15, 7168, !dbg !18
+  %19 = add nsw i32 %17, 5120
+  %20 = add i32 %19, %18
+  %.fr = freeze i1 %12
+  br i1 %.fr, label %.split.us, label %.split.preheader
+
+.split.preheader:                                 ; preds = %5
+  %21 = or disjoint i32 %20, %14, !dbg !19
+  %22 = sext i32 %21 to i64, !dbg !20
+  %23 = getelementptr bfloat, ptr addrspace(1) %0, i64 %22, !dbg !20
+  %24 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %23, i1 false) #3, !dbg !21
+  %25 = or disjoint i32 %14, 8, !dbg !22
+  %26 = or disjoint i32 %20, %25, !dbg !19
+  %27 = sext i32 %26 to i64, !dbg !20
+  %28 = getelementptr bfloat, ptr addrspace(1) %0, i64 %27, !dbg !20
+  %29 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %28, i1 false) #3, !dbg !21
+  %30 = or disjoint i32 %14, 16, !dbg !22
+  %31 = or disjoint i32 %20, %30, !dbg !19
+  %32 = sext i32 %31 to i64, !dbg !20
+  %33 = getelementptr bfloat, ptr addrspace(1) %0, i64 %32, !dbg !20
+  %34 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %33, i1 false) #3, !dbg !21
+  %35 = or disjoint i32 %14, 24, !dbg !22
+  %36 = or disjoint i32 %20, %35, !dbg !19
+  %37 = sext i32 %36 to i64, !dbg !20
+  %38 = getelementptr bfloat, ptr addrspace(1) %0, i64 %37, !dbg !20
+  %39 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %38, i1 false) #3, !dbg !21
+  %40 = or disjoint i32 %14, 32, !dbg !22
+  %41 = or disjoint i32 %20, %40, !dbg !19
+  %42 = sext i32 %41 to i64, !dbg !20
+  %43 = getelementptr bfloat, ptr addrspace(1) %0, i64 %42, !dbg !20
+  %44 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %43, i1 false) #3, !dbg !21
+  %45 = or disjoint i32 %14, 40, !dbg !22
+  %46 = or disjoint i32 %20, %45, !dbg !19
+  %47 = sext i32 %46 to i64, !dbg !20
+  %48 = getelementptr bfloat, ptr addrspace(1) %0, i64 %47, !dbg !20
+  %49 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %48, i1 false) #3, !dbg !21
+  %50 = or disjoint i32 %14, 48, !dbg !22
+  %51 = or disjoint i32 %20, %50, !dbg !19
+  %52 = sext i32 %51 to i64, !dbg !20
+  %53 = getelementptr bfloat, ptr addrspace(1) %0, i64 %52, !dbg !20
+  %54 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %53, i1 false) #3, !dbg !21
+  %55 = or disjoint i32 %14, 56, !dbg !22
+  %56 = or disjoint i32 %20, %55, !dbg !19
+  %57 = sext i32 %56 to i64, !dbg !20
+  %58 = getelementptr bfloat, ptr addrspace(1) %0, i64 %57, !dbg !20
+  %59 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %58, i1 false) #3, !dbg !21
+  %60 = or disjoint i32 %14, 64, !dbg !22
+  %61 = or disjoint i32 %20, %60, !dbg !19
+  %62 = sext i32 %61 to i64, !dbg !20
+  %63 = getelementptr bfloat, ptr addrspace(1) %0, i64 %62, !dbg !20
+  %64 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %63, i1 false) #3, !dbg !21
+  %65 = or disjoint i32 %14, 72, !dbg !22
+  %66 = or disjoint i32 %20, %65, !dbg !19
+  %67 = sext i32 %66 to i64, !dbg !20
+  %68 = getelementptr bfloat, ptr addrspace(1) %0, i64 %67, !dbg !20
+  %69 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %68, i1 false) #3, !dbg !21
+  %70 = or disjoint i32 %14, 80, !dbg !22
+  %71 = or disjoint i32 %20, %70, !dbg !19
+  %72 = sext i32 %71 to i64, !dbg !20
+  %73 = getelementptr bfloat, ptr addrspace(1) %0, i64 %72, !dbg !20
+  %74 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %73, i1 false) #3, !dbg !21
+  %75 = or disjoint i32 %14, 88, !dbg !22
+  %76 = or disjoint i32 %20, %75, !dbg !19
+  %77 = sext i32 %76 to i64, !dbg !20
+  %78 = getelementptr bfloat, ptr addrspace(1) %0, i64 %77, !dbg !20
+  %79 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %78, i1 false) #3, !dbg !21
+  %80 = or disjoint i32 %14, 96, !dbg !22
+  %81 = or disjoint i32 %20, %80, !dbg !19
+  %82 = sext i32 %81 to i64, !dbg !20
+  %83 = getelementptr bfloat, ptr addrspace(1) %0, i64 %82, !dbg !20
+  %84 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %83, i1 false) #3, !dbg !21
+  %85 = or disjoint i32 %14, 104, !dbg !22
+  %86 = or disjoint i32 %20, %85, !dbg !19
+  %87 = sext i32 %86 to i64, !dbg !20
+  %88 = getelementptr bfloat, ptr addrspace(1) %0, i64 %87, !dbg !20
+  %89 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %88, i1 false) #3, !dbg !21
+  %90 = or disjoint i32 %14, 112, !dbg !22
+  %91 = or disjoint i32 %20, %90, !dbg !19
+  %92 = sext i32 %91 to i64, !dbg !20
+  %93 = getelementptr bfloat, ptr addrspace(1) %0, i64 %92, !dbg !20
+  %94 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %93, i1 false) #3, !dbg !21
+  %95 = or disjoint i32 %14, 120, !dbg !22
+  %96 = or disjoint i32 %20, %95, !dbg !19
+  %97 = sext i32 %96 to i64, !dbg !20
+  %98 = getelementptr bfloat, ptr addrspace(1) %0, i64 %97, !dbg !20
+  %99 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %98, i1 false) #3, !dbg !21
+  br label %.split4.us, !dbg !11
+
+.split.us:                                        ; preds = %5, %.split.us
+  %indvars.iv = phi i64 [ %indvars.iv.next, %.split.us ], [ 0, %5 ]
+  %100 = phi float [ %126, %.split.us ], [ 0.000000e+00, %5 ]
+  %101 = phi float [ %127, %.split.us ], [ 0.000000e+00, %5 ]
+  %102 = phi float [ %128, %.split.us ], [ 0.000000e+00, %5 ]
+  %103 = phi float [ %129, %.split.us ], [ 0.000000e+00, %5 ]
+  %104 = trunc i64 %indvars.iv to i32, !dbg !19
+  %105 = or disjoint i32 %14, %104, !dbg !19
+  %106 = add i32 %20, %105, !dbg !19
+  %107 = sext i32 %106 to i64, !dbg !20
+  %108 = getelementptr bfloat, ptr addrspace(1) %0, i64 %107, !dbg !20
+  %109 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %108, i1 true) #3, !dbg !21
+  %110 = extractvalue { i32, i32 } %109, 0, !dbg !21
+  %111 = bitcast i32 %110 to <2 x bfloat>, !dbg !21
+  %112 = extractvalue { i32, i32 } %109, 1, !dbg !21
+  %113 = bitcast i32 %112 to <2 x bfloat>, !dbg !21
+  %114 = extractelement <2 x bfloat> %111, i64 0, !dbg !21
+  %115 = extractelement <2 x bfloat> %111, i64 1, !dbg !21
+  %116 = extractelement <2 x bfloat> %113, i64 0, !dbg !21
+  %117 = extractelement <2 x bfloat> %113, i64 1, !dbg !21
+  %118 = fpext bfloat %114 to float, !dbg !23
+  %119 = fpext bfloat %115 to float, !dbg !23
+  %120 = fpext bfloat %116 to float, !dbg !23
+  %121 = fpext bfloat %117 to float, !dbg !23
+  %122 = fmul float %118, %118, !dbg !24
+  %123 = fmul float %119, %119, !dbg !24
+  %124 = fmul float %120, %120, !dbg !24
+  %125 = fmul float %121, %121, !dbg !24
+  %126 = fadd float %100, %122, !dbg !25
+  %127 = fadd float %101, %123, !dbg !25
+  %128 = fadd float %102, %124, !dbg !25
+  %129 = fadd float %103, %125, !dbg !25
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 8, !dbg !26
+  %130 = icmp samesign ult i64 %indvars.iv, 120, !dbg !26
+  br i1 %130, label %.split.us, label %.split4.us.loopexit, !dbg !26
+
+.split4.us.loopexit:                              ; preds = %.split.us
+  %131 = fadd float %126, %127, !dbg !11
+  %132 = fadd float %128, %131, !dbg !11
+  %133 = fadd float %129, %132, !dbg !11
+  br label %.split4.us, !dbg !11
+
+.split4.us:                                       ; preds = %.split4.us.loopexit, %.split.preheader
+  %134 = phi float [ 0.000000e+00, %.split.preheader ], [ %133, %.split4.us.loopexit ], !dbg !27
+  %135 = and i32 %8, 63, !dbg !11
+  %136 = or disjoint i32 %7, %135, !dbg !12
+  %137 = icmp slt i32 %136, %2, !dbg !13
+  %138 = and i32 %8, 64, !dbg !11
+  %139 = icmp eq i32 %138, 0, !dbg !11
+  %140 = bitcast float %134 to i32, !dbg !32
+  %141 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %140, i32 1, i32 31), !dbg !32
+  %142 = bitcast i32 %141 to float, !dbg !32
+  %143 = fadd float %134, %142, !dbg !27
+  %144 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %10, !dbg !33
+  %145 = bitcast float %143 to <1 x i32>, !dbg !33
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %144, <1 x i32> %145, i1 true) #3, !dbg !33
+  tail call void @llvm.nvvm.barrier0(), !dbg !33
+  %146 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %135, !dbg !33
+  %147 = load i32, ptr addrspace(3) %146, align 4, !dbg !33
+  %148 = sext i32 %136 to i64, !dbg !34
+  %149 = getelementptr float, ptr addrspace(1) %1, i64 %148, !dbg !34
+  %150 = and i1 %139, %137, !dbg !35
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %147, ptr addrspace(1) %149, i1 %150) #3, !dbg !35
+  ret void, !dbg !36
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py", directory: "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty")
+!4 = !{ptr @triton_red_fused__to_copy_mean_pow_4, !"reqntidx", i32 128}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mean_pow_4", linkageName: "triton_red_fused__to_copy_mean_pow_4", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 22, column: 28, scope: !6)
+!10 = !DILocation(line: 22, column: 33, scope: !6)
+!11 = !DILocation(line: 23, column: 44, scope: !6)
+!12 = !DILocation(line: 23, column: 23, scope: !6)
+!13 = !DILocation(line: 24, column: 21, scope: !6)
+!14 = !DILocation(line: 25, column: 37, scope: !6)
+!15 = !DILocation(line: 28, column: 19, scope: !6)
+!16 = !DILocation(line: 27, column: 19, scope: !6)
+!17 = !DILocation(line: 37, column: 52, scope: !6)
+!18 = !DILocation(line: 37, column: 62, scope: !6)
+!19 = !DILocation(line: 37, column: 57, scope: !6)
+!20 = !DILocation(line: 37, column: 34, scope: !6)
+!21 = !DILocation(line: 37, column: 67, scope: !6)
+!22 = !DILocation(line: 32, column: 31, scope: !6)
+!23 = !DILocation(line: 37, column: 129, scope: !6)
+!24 = !DILocation(line: 39, column: 22, scope: !6)
+!25 = !DILocation(line: 41, column: 23, scope: !6)
+!26 = !DILocation(line: 31, column: 40, scope: !6)
+!27 = !DILocation(line: 256, column: 15, scope: !28, inlinedAt: !31)
+!28 = distinct !DILexicalBlockFile(scope: !30, file: !29, discriminator: 0)
+!29 = !DIFile(filename: "standard.py", directory: "/home/x/hfenv/lib/python3.12/site-packages/triton/language")
+!30 = distinct !DILexicalBlockFile(scope: !6, file: !29, discriminator: 0)
+!31 = !DILocation(line: 43, column: 25, scope: !6)
+!32 = !DILocation(line: 286, column: 36, scope: !30, inlinedAt: !31)
+!33 = !DILocation(line: 43, column: 28, scope: !6)
+!34 = !DILocation(line: 44, column: 25, scope: !6)
+!35 = !DILocation(line: 44, column: 36, scope: !6)
+!36 = !DILocation(line: 44, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.ptx

@@ -0,0 +1,559 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_mean_pow_4 // -- Begin function triton_red_fused__to_copy_mean_pow_4
+.extern .shared .align 16 .b8 global_smem[];
+                                        // @triton_red_fused__to_copy_mean_pow_4
+.visible .entry triton_red_fused__to_copy_mean_pow_4(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_1,
+	.param .u32 triton_red_fused__to_copy_mean_pow_4_param_2,
+	.param .u32 triton_red_fused__to_copy_mean_pow_4_param_3,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_4_param_4
+)
+.reqntid 128, 1, 1
+{
+	.reg .pred 	%p<24>;
+	.reg .b16 	%rs<5>;
+	.reg .b32 	%r<106>;
+	.reg .f32 	%f<26>;
+	.reg .b64 	%rd<35>;
+	.loc	1 18 0                          // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:18:0
+
+// %bb.0:
+	ld.param.u32 	%r8, [triton_red_fused__to_copy_mean_pow_4_param_2];
+	ld.param.u64 	%rd5, [triton_red_fused__to_copy_mean_pow_4_param_1];
+	ld.param.u64 	%rd4, [triton_red_fused__to_copy_mean_pow_4_param_0];
+$L__tmp0:
+	.loc	1 22 28                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:22:28
+	mov.u32 	%r1, %ctaid.x;
+	.loc	1 22 33                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:22:33
+	shl.b32 	%r2, %r1, 6;
+	.loc	1 23 44                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:23:44
+	mov.u32 	%r3, %tid.x;
+	bfe.u32 	%r4, %r3, 1, 6;
+	.loc	1 23 23                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:23:23
+	or.b32  	%r9, %r4, %r2;
+	.loc	1 25 37                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:25:37
+	shl.b32 	%r10, %r3, 2;
+	and.b32  	%r5, %r10, 4;
+	.loc	1 28 19                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:28:19
+	bfe.s32 	%r11, %r1, 25, 1;
+	shr.u32 	%r12, %r11, 29;
+	add.s32 	%r13, %r9, %r12;
+	shr.s32 	%r6, %r13, 3;
+	setp.ge.s32 	%p1, %r9, %r8;
+	@%p1 bra 	$L__BB0_5;
+// %bb.1:                               // %.split.us.preheader
+	.loc	1 31 40                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:31:40
+	shl.b32 	%r83, %r1, 13;
+	mad.lo.s32 	%r84, %r6, 6144, %r83;
+	shl.b32 	%r85, %r4, 7;
+	add.s32 	%r86, %r84, %r85;
+	or.b32  	%r87, %r86, %r5;
+	cvt.u64.u32 	%rd1, %r87;
+	mov.f32 	%f21, 0f00000000;
+	mov.b64 	%rd34, -8;
+	mov.f32 	%f22, %f21;
+	mov.f32 	%f23, %f21;
+	mov.f32 	%f24, %f21;
+$L__BB0_2:                              // %.split.us
+                                        // =>This Inner Loop Header: Depth=1
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd30, %rd1, %rd34;
+	cvt.u32.u64 	%r92, %rd30;
+	add.s32 	%r93, %r92, 5128;
+	mul.wide.s32 	%rd31, %r93, 2;
+	add.s64 	%rd29, %rd4, %rd31;
+	mov.b32 	%r90, 0;
+	mov.pred 	%p18, -1;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r88, %r90;
+	mov.u32 %r89, %r90;
+	@%p18 ld.global.L1::evict_first.v2.b32 { %r88, %r89 }, [ %rd29 + 0 ];
+	// end inline asm
+	mov.b32 	{%rs1, %rs2}, %r88;
+	mov.b32 	{%rs3, %rs4}, %r89;
+	.loc	1 37 129                        // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:129
+	cvt.f32.bf16 	%f13, %rs1;
+	cvt.f32.bf16 	%f14, %rs2;
+	cvt.f32.bf16 	%f15, %rs3;
+	cvt.f32.bf16 	%f16, %rs4;
+	.loc	1 41 23                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:41:23
+	fma.rn.f32 	%f21, %f13, %f13, %f21;
+	fma.rn.f32 	%f22, %f14, %f14, %f22;
+	fma.rn.f32 	%f23, %f15, %f15, %f23;
+	fma.rn.f32 	%f24, %f16, %f16, %f24;
+	.loc	1 31 40                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:31:40
+	add.s64 	%rd34, %rd34, 8;
+	setp.lt.u64 	%p19, %rd34, 120;
+	@%p19 bra 	$L__BB0_2;
+// %bb.3:                               // %.split4.us.loopexit
+	.loc	1 23 44                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:23:44
+	add.f32 	%f17, %f21, %f22;
+	add.f32 	%f18, %f23, %f17;
+	add.f32 	%f25, %f24, %f18;
+	bra.uni 	$L__BB0_4;
+$L__BB0_5:                              // %.split.preheader
+	.loc	1 0 44                          // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:0:44
+	and.b32  	%r14, %r13, 33554424;
+	sub.s32 	%r15, %r9, %r14;
+	shl.b32 	%r16, %r15, 7;
+	mad.lo.s32 	%r17, %r6, 7168, %r16;
+	add.s32 	%r7, %r17, 5120;
+	.loc	1 37 57                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:57
+	or.b32  	%r82, %r7, %r5;
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	mul.wide.s32 	%rd22, %r82, 2;
+	add.s64 	%rd6, %rd4, %rd22;
+	mov.b32 	%r20, 0;
+	mov.pred 	%p2, 0;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r18, %r20;
+	mov.u32 %r19, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r18, %r19 }, [ %rd6 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	cvt.s64.s32 	%rd23, %r7;
+	cvt.u64.u32 	%rd24, %r5;
+	add.s64 	%rd25, %rd23, %rd24;
+	shl.b64 	%rd26, %rd25, 1;
+	add.s64 	%rd27, %rd4, %rd26;
+	add.s64 	%rd7, %rd27, 16;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r22, %r20;
+	mov.u32 %r23, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r22, %r23 }, [ %rd7 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd8, %rd27, 32;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r26, %r20;
+	mov.u32 %r27, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r26, %r27 }, [ %rd8 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd9, %rd27, 48;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r30, %r20;
+	mov.u32 %r31, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r30, %r31 }, [ %rd9 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd10, %rd27, 64;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r34, %r20;
+	mov.u32 %r35, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r34, %r35 }, [ %rd10 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd11, %rd27, 80;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r38, %r20;
+	mov.u32 %r39, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r38, %r39 }, [ %rd11 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd12, %rd27, 96;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r42, %r20;
+	mov.u32 %r43, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r42, %r43 }, [ %rd12 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd13, %rd27, 112;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r46, %r20;
+	mov.u32 %r47, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r46, %r47 }, [ %rd13 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd14, %rd27, 128;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r50, %r20;
+	mov.u32 %r51, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r50, %r51 }, [ %rd14 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd15, %rd27, 144;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r54, %r20;
+	mov.u32 %r55, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r54, %r55 }, [ %rd15 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd16, %rd27, 160;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r58, %r20;
+	mov.u32 %r59, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r58, %r59 }, [ %rd16 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd17, %rd27, 176;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r62, %r20;
+	mov.u32 %r63, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r62, %r63 }, [ %rd17 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd18, %rd27, 192;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r66, %r20;
+	mov.u32 %r67, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r66, %r67 }, [ %rd18 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd19, %rd27, 208;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r70, %r20;
+	mov.u32 %r71, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r70, %r71 }, [ %rd19 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd20, %rd27, 224;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r74, %r20;
+	mov.u32 %r75, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r74, %r75 }, [ %rd20 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:34
+	add.s64 	%rd21, %rd27, 240;
+	.loc	1 37 67                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:37:67
+	// begin inline asm
+	mov.u32 %r78, %r20;
+	mov.u32 %r79, %r20;
+	@%p2 ld.global.L1::evict_first.v2.b32 { %r78, %r79 }, [ %rd21 + 0 ];
+	// end inline asm
+	mov.f32 	%f25, 0f00000000;
+$L__BB0_4:                              // %.split4.us
+	.loc	1 23 44                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:23:44
+	and.b32  	%r97, %r3, 63;
+	.loc	1 23 23                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:23:23
+	or.b32  	%r98, %r2, %r97;
+	.loc	1 24 21                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:24:21
+	setp.lt.s32 	%p22, %r98, %r8;
+	.loc	1 23 44                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:23:44
+	and.b32  	%r99, %r3, 64;
+	setp.eq.s32 	%p23, %r99, 0;
+$L__tmp1:
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r100, %f25;
+	shfl.sync.bfly.b32	%r101, %r100, 1, 31, -1;
+	mov.b32 	%f19, %r101;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f20, %f25, %f19;
+$L__tmp2:
+	.loc	1 43 28                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:43:28
+	shl.b32 	%r102, %r4, 2;
+	mov.u32 	%r103, global_smem;
+	add.s32 	%r94, %r103, %r102;
+	mov.b32 	%r95, %f20;
+	mov.pred 	%p20, -1;
+	// begin inline asm
+	@%p20 st.shared.b32 [ %r94 + 0 ], %r95;
+	// end inline asm
+	bar.sync 	0;
+	shl.b32 	%r104, %r97, 2;
+	add.s32 	%r105, %r103, %r104;
+	ld.shared.u32 	%r96, [%r105];
+	.loc	1 44 25                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:44:25
+	mul.wide.s32 	%rd33, %r98, 4;
+	add.s64 	%rd32, %rd5, %rd33;
+	.loc	1 44 36                         // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:44:36
+	and.pred  	%p21, %p23, %p22;
+	// begin inline asm
+	@%p21 st.global.b32 [ %rd32 + 0 ], { %r96 };
+	// end inline asm
+	.loc	1 44 4                          // ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py:44:4
+	ret;
+$L__tmp3:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py"
+	.file	2 "/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 241                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xea DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 116
+.b8 121
+.b8 100
+.b8 106
+.b8 97
+.b8 55
+.b8 107
+.b8 116
+.b8 114
+.b8 101
+.b8 119
+.b8 120
+.b8 113
+.b8 101
+.b8 104
+.b8 107
+.b8 105
+.b8 122
+.b8 106
+.b8 105
+.b8 55
+.b8 113
+.b8 122
+.b8 105
+.b8 52
+.b8 119
+.b8 122
+.b8 113
+.b8 107
+.b8 106
+.b8 99
+.b8 115
+.b8 119
+.b8 106
+.b8 107
+.b8 113
+.b8 110
+.b8 120
+.b8 97
+.b8 108
+.b8 102
+.b8 101
+.b8 121
+.b8 51
+.b8 109
+.b8 111
+.b8 104
+.b8 103
+.b8 103
+.b8 111
+.b8 116
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 57
+.b8 48
+.b8 98
+.b8 52
+.b8 53
+.b8 98
+.b8 99
+.b8 101
+.b8 48
+.b8 50
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 116
+.b8 121
+.b8 0
+.b8 2                                   // Abbrev [2] 0x9f:0x27 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 109
+.b8 101
+.b8 97
+.b8 110
+.b8 95
+.b8 112
+.b8 111
+.b8 119
+.b8 95
+.b8 52
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xc6:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 159                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xdb:0x18 DW_TAG_inlined_subroutine
+.b32 159                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp2                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 43                                  // DW_AT_call_line
+.b8 25                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.ttgir

@@ -0,0 +1,107 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 4], threadsPerWarp = [16, 2], warpsPerCTA = [4, 1], order = [1, 0]}>
+#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 2], order = [0, 1]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)
+#loc1 = loc(unknown)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:25)
+#loc34 = loc(callsite(#loc1 at #loc27))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mean_pow_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x8xf32, #blocked> loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<64x8xbf16, #blocked> loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<8> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<7168> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<128> : tensor<64x1xi32, #blocked> loc(#loc1)
+    %cst_4 = arith.constant dense<5120> : tensor<1x8xi32, #blocked> loc(#loc1)
+    %cst_5 = arith.constant dense<128> : tensor<1x8xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c64_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc4)
+    %3 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc4)
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64x1xi32, #blocked> loc(#loc4)
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : tensor<64xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<64x1xi32, #blocked1> loc(#loc4)
+    %6 = tt.splat %1 : i32 -> tensor<64x1xi32, #blocked> loc(#loc5)
+    %7 = tt.splat %1 : i32 -> tensor<64x1xi32, #blocked1> loc(#loc5)
+    %8 = arith.addi %6, %4 : tensor<64x1xi32, #blocked> loc(#loc5)
+    %9 = arith.addi %7, %5 : tensor<64x1xi32, #blocked1> loc(#loc5)
+    %10 = tt.splat %arg2 : i32 -> tensor<64x1xi32, #blocked> loc(#loc6)
+    %11 = tt.splat %arg2 : i32 -> tensor<64x1xi32, #blocked1> loc(#loc6)
+    %12 = arith.cmpi slt, %8, %10 : tensor<64x1xi32, #blocked> loc(#loc6)
+    %13 = arith.cmpi slt, %9, %11 : tensor<64x1xi32, #blocked1> loc(#loc6)
+    %14 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc7)
+    %15 = tt.expand_dims %14 {axis = 0 : i32} : tensor<8xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x8xi32, #blocked> loc(#loc7)
+    %16 = arith.remsi %8, %cst_1 : tensor<64x1xi32, #blocked> loc(#loc8)
+    %17 = arith.divsi %8, %cst_1 : tensor<64x1xi32, #blocked> loc(#loc9)
+    %18 = arith.muli %16, %cst_3 : tensor<64x1xi32, #blocked> loc(#loc10)
+    %19 = tt.broadcast %18 : tensor<64x1xi32, #blocked> -> tensor<64x8xi32, #blocked> loc(#loc11)
+    %20 = arith.muli %17, %cst_2 : tensor<64x1xi32, #blocked> loc(#loc12)
+    %21 = tt.broadcast %20 : tensor<64x1xi32, #blocked> -> tensor<64x8xi32, #blocked> loc(#loc13)
+    %22 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>, #blocked> loc(#loc14)
+    %23 = tt.broadcast %12 : tensor<64x1xi1, #blocked> -> tensor<64x8xi1, #blocked> loc(#loc15)
+    %24 = scf.for %arg4 = %c0_i32 to %c128_i32 step %c8_i32 iter_args(%arg5 = %cst) -> (tensor<64x8xf32, #blocked>)  : i32 {
+      %30 = tt.splat %arg4 : i32 -> tensor<1x8xi32, #blocked> loc(#loc17)
+      %31 = arith.addi %30, %15 : tensor<1x8xi32, #blocked> loc(#loc17)
+      %32 = arith.cmpi slt, %31, %cst_5 : tensor<1x8xi32, #blocked> loc(#loc18)
+      %33 = arith.addi %31, %cst_4 : tensor<1x8xi32, #blocked> loc(#loc19)
+      %34 = tt.broadcast %33 : tensor<1x8xi32, #blocked> -> tensor<64x8xi32, #blocked> loc(#loc11)
+      %35 = arith.addi %34, %19 : tensor<64x8xi32, #blocked> loc(#loc11)
+      %36 = arith.addi %35, %21 : tensor<64x8xi32, #blocked> loc(#loc13)
+      %37 = tt.addptr %22, %36 : tensor<64x8x!tt.ptr<bf16>, #blocked>, tensor<64x8xi32, #blocked> loc(#loc14)
+      %38 = tt.broadcast %32 : tensor<1x8xi1, #blocked> -> tensor<64x8xi1, #blocked> loc(#loc15)
+      %39 = arith.andi %38, %23 : tensor<64x8xi1, #blocked> loc(#loc15)
+      %40 = tt.load %37, %39, %cst_0 evictionPolicy = evict_first : tensor<64x8x!tt.ptr<bf16>, #blocked> loc(#loc20)
+      %41 = arith.extf %40 : tensor<64x8xbf16, #blocked> to tensor<64x8xf32, #blocked> loc(#loc21)
+      %42 = arith.mulf %41, %41 : tensor<64x8xf32, #blocked> loc(#loc22)
+      %43 = arith.addf %arg5, %42 : tensor<64x8xf32, #blocked> loc(#loc23)
+      %44 = arith.select %39, %43, %arg5 : tensor<64x8xi1, #blocked>, tensor<64x8xf32, #blocked> loc(#loc24)
+      scf.yield %44 : tensor<64x8xf32, #blocked> loc(#loc25)
+    } loc(#loc16)
+    %25 = "tt.reduce"(%24) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc27)), %arg5: f32 loc(callsite(#loc1 at #loc27))):
+      %30 = arith.addf %arg4, %arg5 : f32 loc(#loc36)
+      tt.reduce.return %30 : f32 loc(#loc33)
+    }) : (tensor<64x8xf32, #blocked>) -> tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc33)
+    %26 = ttg.convert_layout %25 : tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc29)
+    %27 = tt.expand_dims %26 {axis = 1 : i32} : tensor<64xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<64x1xf32, #blocked1> loc(#loc29)
+    %28 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>, #blocked1> loc(#loc30)
+    %29 = tt.addptr %28, %9 : tensor<64x1x!tt.ptr<f32>, #blocked1>, tensor<64x1xi32, #blocked1> loc(#loc30)
+    tt.store %29, %27, %13 : tensor<64x1x!tt.ptr<f32>, #blocked1> loc(#loc31)
+    tt.return loc(#loc32)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:44)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":24:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:37)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":27:19)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":28:19)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:52)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:48)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:62)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:57)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:34)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:77)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":31:40)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":32:31)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":33:29)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:41)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:67)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:129)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":39:22)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":41:23)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:48)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:8)
+#loc26 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc28 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:28)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:25)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:36)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:4)
+#loc33 = loc(callsite(#loc26 at #loc27))
+#loc35 = loc(callsite(#loc28 at #loc26))
+#loc36 = loc(callsite(#loc35 at #loc27))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/T3JM25SHJKIT26DJIVKB2COTPIWFRN46F6AA2QKQTZOBG5I6OBQQ/triton_red_fused__to_copy_mean_pow_4.ttir

@@ -0,0 +1,100 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)
+#loc1 = loc(unknown)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:25)
+#loc36 = loc(callsite(#loc1 at #loc29))
+module {
+  tt.func public @triton_red_fused__to_copy_mean_pow_4(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x8xbf16> loc(#loc1)
+    %c8_i32 = arith.constant 8 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<7168> : tensor<64x1xi32> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<64x1xi32> loc(#loc1)
+    %cst_2 = arith.constant dense<5120> : tensor<1x8xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<128> : tensor<1x8xi32> loc(#loc1)
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<64x8xf32> loc(#loc1)
+    %cst_5 = arith.constant dense<8> : tensor<64x1xi32> loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c64_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : tensor<64xi32> -> tensor<64x1xi32> loc(#loc5)
+    %4 = tt.splat %1 : i32 -> tensor<64x1xi32> loc(#loc6)
+    %5 = arith.addi %4, %3 : tensor<64x1xi32> loc(#loc6)
+    %6 = tt.splat %arg2 : i32 -> tensor<64x1xi32> loc(#loc7)
+    %7 = arith.cmpi slt, %5, %6 : tensor<64x1xi32> loc(#loc7)
+    %8 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32> loc(#loc8)
+    %9 = tt.expand_dims %8 {axis = 0 : i32} : tensor<8xi32> -> tensor<1x8xi32> loc(#loc9)
+    %10 = arith.remsi %5, %cst_5 : tensor<64x1xi32> loc(#loc10)
+    %11 = arith.divsi %5, %cst_5 : tensor<64x1xi32> loc(#loc11)
+    %12 = scf.for %arg4 = %c0_i32 to %c128_i32 step %c8_i32 iter_args(%arg5 = %cst_4) -> (tensor<64x8xf32>)  : i32 {
+      %17 = tt.splat %arg4 : i32 -> tensor<1x8xi32> loc(#loc13)
+      %18 = arith.addi %17, %9 : tensor<1x8xi32> loc(#loc13)
+      %19 = arith.cmpi slt, %18, %cst_3 : tensor<1x8xi32> loc(#loc14)
+      %20 = arith.addi %18, %cst_2 : tensor<1x8xi32> loc(#loc15)
+      %21 = arith.muli %10, %cst_1 : tensor<64x1xi32> loc(#loc16)
+      %22 = tt.broadcast %20 : tensor<1x8xi32> -> tensor<64x8xi32> loc(#loc17)
+      %23 = tt.broadcast %21 : tensor<64x1xi32> -> tensor<64x8xi32> loc(#loc17)
+      %24 = arith.addi %22, %23 : tensor<64x8xi32> loc(#loc17)
+      %25 = arith.muli %11, %cst_0 : tensor<64x1xi32> loc(#loc18)
+      %26 = tt.broadcast %25 : tensor<64x1xi32> -> tensor<64x8xi32> loc(#loc19)
+      %27 = arith.addi %24, %26 : tensor<64x8xi32> loc(#loc19)
+      %28 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<64x8x!tt.ptr<bf16>> loc(#loc20)
+      %29 = tt.addptr %28, %27 : tensor<64x8x!tt.ptr<bf16>>, tensor<64x8xi32> loc(#loc20)
+      %30 = tt.broadcast %19 : tensor<1x8xi1> -> tensor<64x8xi1> loc(#loc21)
+      %31 = tt.broadcast %7 : tensor<64x1xi1> -> tensor<64x8xi1> loc(#loc21)
+      %32 = arith.andi %30, %31 : tensor<64x8xi1> loc(#loc21)
+      %33 = tt.load %29, %32, %cst evictionPolicy = evict_first : tensor<64x8x!tt.ptr<bf16>> loc(#loc22)
+      %34 = arith.extf %33 : tensor<64x8xbf16> to tensor<64x8xf32> loc(#loc23)
+      %35 = arith.mulf %34, %34 : tensor<64x8xf32> loc(#loc24)
+      %36 = arith.addf %arg5, %35 : tensor<64x8xf32> loc(#loc25)
+      %37 = arith.select %32, %36, %arg5 : tensor<64x8xi1>, tensor<64x8xf32> loc(#loc26)
+      scf.yield %37 : tensor<64x8xf32> loc(#loc27)
+    } loc(#loc12)
+    %13 = "tt.reduce"(%12) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc29)), %arg5: f32 loc(callsite(#loc1 at #loc29))):
+      %17 = arith.addf %arg4, %arg5 : f32 loc(#loc38)
+      tt.reduce.return %17 : f32 loc(#loc35)
+    }) : (tensor<64x8xf32>) -> tensor<64xf32> loc(#loc35)
+    %14 = tt.expand_dims %13 {axis = 1 : i32} : tensor<64xf32> -> tensor<64x1xf32> loc(#loc31)
+    %15 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>> loc(#loc32)
+    %16 = tt.addptr %15, %5 : tensor<64x1x!tt.ptr<f32>>, tensor<64x1xi32> loc(#loc32)
+    tt.store %16, %14, %7 : tensor<64x1x!tt.ptr<f32>> loc(#loc33)
+    tt.return loc(#loc34)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:44)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":23:23)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":24:21)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:27)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":25:37)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":27:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":28:19)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":31:40)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":32:31)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":33:29)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:41)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:52)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:48)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:62)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:57)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:34)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:77)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:67)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":37:129)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":39:22)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":41:23)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:48)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":42:8)
+#loc28 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc30 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":43:28)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:25)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:36)
+#loc34 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/ty/ctydja7ktrewxqehkizji7qzi4wzqkjcswjkqnxalfey3mohggot.py":44:4)
+#loc35 = loc(callsite(#loc28 at #loc29))
+#loc37 = loc(callsite(#loc30 at #loc28))
+#loc38 = loc(callsite(#loc37 at #loc29))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/WWVE4L3JNPA466VTEASWQD5XMPD3BLL73RENYAYQTAKJGCYZT3JA/triton_red_fused__to_copy_mean_pow_3.llir

@@ -0,0 +1,141 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+define ptx_kernel void @triton_red_fused__to_copy_mean_pow_3(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2, i32 %3, ptr addrspace(1) readnone captures(none) %4) local_unnamed_addr !dbg !6 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %7 = shl i32 %6, 2, !dbg !10
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %9 = lshr i32 %8, 5, !dbg !11
+  %10 = and i32 %9, 3, !dbg !11
+  %11 = and i32 %8, 3, !dbg !11
+  %12 = or disjoint i32 %10, %7, !dbg !12
+  %13 = or disjoint i32 %7, %11, !dbg !12
+  %14 = icmp slt i32 %12, %2, !dbg !13
+  %15 = icmp slt i32 %13, %2, !dbg !13
+  %16 = shl i32 %8, 2, !dbg !14
+  %17 = and i32 %16, 124, !dbg !14
+  %18 = sdiv i32 %12, 40, !dbg !15
+  %19 = mul i32 %18, 40, !dbg !16
+  %.decomposed = sub i32 %12, %19, !dbg !16
+  %20 = shl nsw i32 %.decomposed, 7, !dbg !17
+  %21 = or disjoint i32 %20, %17, !dbg !18
+  %22 = mul i32 %18, 7168, !dbg !19
+  %23 = add i32 %21, %22, !dbg !20
+  %24 = sext i32 %23 to i64, !dbg !21
+  %25 = getelementptr bfloat, ptr addrspace(1) %0, i64 %24, !dbg !21
+  %26 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, $2;\0A\09mov.u32 $1, $3;\0A\09@$5 ld.global.L1::evict_first.v2.b32 { $0, $1 }, [ $4 + 0 ];", "=r,=r,r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %25, i1 %14) #3, !dbg !22
+  %27 = extractvalue { i32, i32 } %26, 0, !dbg !22
+  %28 = bitcast i32 %27 to <2 x bfloat>, !dbg !22
+  %29 = extractvalue { i32, i32 } %26, 1, !dbg !22
+  %30 = bitcast i32 %29 to <2 x bfloat>, !dbg !22
+  %31 = extractelement <2 x bfloat> %28, i64 0, !dbg !22
+  %32 = extractelement <2 x bfloat> %28, i64 1, !dbg !22
+  %33 = extractelement <2 x bfloat> %30, i64 0, !dbg !22
+  %34 = extractelement <2 x bfloat> %30, i64 1, !dbg !22
+  %35 = fpext bfloat %31 to float, !dbg !23
+  %36 = fpext bfloat %32 to float, !dbg !23
+  %37 = fpext bfloat %33 to float, !dbg !23
+  %38 = fpext bfloat %34 to float, !dbg !23
+  %39 = fmul float %35, %35, !dbg !24
+  %40 = fmul float %36, %36, !dbg !24
+  %41 = fmul float %37, %37, !dbg !24
+  %42 = fmul float %38, %38, !dbg !24
+  %43 = fadd float %39, %40, !dbg !25
+  %44 = fadd float %41, %43, !dbg !25
+  %45 = fadd float %42, %44, !dbg !25
+  %46 = select i1 %14, float %45, float 0.000000e+00, !dbg !25
+  %47 = bitcast float %46 to i32, !dbg !30
+  %48 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %47, i32 16, i32 31), !dbg !30
+  %49 = bitcast i32 %48 to float, !dbg !30
+  %50 = fadd float %46, %49, !dbg !25
+  %51 = bitcast float %50 to i32, !dbg !30
+  %52 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %51, i32 8, i32 31), !dbg !30
+  %53 = bitcast i32 %52 to float, !dbg !30
+  %54 = fadd float %50, %53, !dbg !25
+  %55 = bitcast float %54 to i32, !dbg !30
+  %56 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %55, i32 4, i32 31), !dbg !30
+  %57 = bitcast i32 %56 to float, !dbg !30
+  %58 = fadd float %54, %57, !dbg !25
+  %59 = bitcast float %58 to i32, !dbg !30
+  %60 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %59, i32 2, i32 31), !dbg !30
+  %61 = bitcast i32 %60 to float, !dbg !30
+  %62 = fadd float %58, %61, !dbg !25
+  %63 = bitcast float %62 to i32, !dbg !30
+  %64 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %63, i32 1, i32 31), !dbg !30
+  %65 = bitcast i32 %64 to float, !dbg !30
+  %66 = fadd float %62, %65, !dbg !25
+  %67 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %10, !dbg !31
+  %68 = bitcast float %66 to <1 x i32>, !dbg !31
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %67, <1 x i32> %68, i1 true) #3, !dbg !31
+  tail call void @llvm.nvvm.barrier0(), !dbg !31
+  %69 = getelementptr inbounds nuw float, ptr addrspace(3) @global_smem, i32 %11, !dbg !31
+  %70 = load i32, ptr addrspace(3) %69, align 4, !dbg !31
+  %71 = sext i32 %13 to i64, !dbg !32
+  %72 = getelementptr float, ptr addrspace(1) %1, i64 %71, !dbg !32
+  %73 = and i32 %8, 124, !dbg !33
+  %74 = icmp eq i32 %73, 0, !dbg !33
+  %75 = and i1 %74, %15, !dbg !33
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %70, ptr addrspace(1) %72, i1 %75) #3, !dbg !33
+  ret void, !dbg !34
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py", directory: "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk")
+!4 = !{ptr @triton_red_fused__to_copy_mean_pow_3, !"reqntidx", i32 128}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mean_pow_3", linkageName: "triton_red_fused__to_copy_mean_pow_3", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 22, column: 28, scope: !6)
+!10 = !DILocation(line: 22, column: 33, scope: !6)
+!11 = !DILocation(line: 23, column: 44, scope: !6)
+!12 = !DILocation(line: 23, column: 23, scope: !6)
+!13 = !DILocation(line: 24, column: 21, scope: !6)
+!14 = !DILocation(line: 25, column: 37, scope: !6)
+!15 = !DILocation(line: 28, column: 19, scope: !6)
+!16 = !DILocation(line: 27, column: 19, scope: !6)
+!17 = !DILocation(line: 37, column: 45, scope: !6)
+!18 = !DILocation(line: 37, column: 41, scope: !6)
+!19 = !DILocation(line: 37, column: 55, scope: !6)
+!20 = !DILocation(line: 37, column: 50, scope: !6)
+!21 = !DILocation(line: 37, column: 34, scope: !6)
+!22 = !DILocation(line: 37, column: 60, scope: !6)
+!23 = !DILocation(line: 37, column: 122, scope: !6)
+!24 = !DILocation(line: 39, column: 22, scope: !6)
+!25 = !DILocation(line: 256, column: 15, scope: !26, inlinedAt: !29)
+!26 = distinct !DILexicalBlockFile(scope: !28, file: !27, discriminator: 0)
+!27 = !DIFile(filename: "standard.py", directory: "/home/x/hfenv/lib/python3.12/site-packages/triton/language")
+!28 = distinct !DILexicalBlockFile(scope: !6, file: !27, discriminator: 0)
+!29 = !DILocation(line: 43, column: 25, scope: !6)
+!30 = !DILocation(line: 286, column: 36, scope: !28, inlinedAt: !29)
+!31 = !DILocation(line: 43, column: 28, scope: !6)
+!32 = !DILocation(line: 44, column: 25, scope: !6)
+!33 = !DILocation(line: 44, column: 36, scope: !6)
+!34 = !DILocation(line: 44, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/WWVE4L3JNPA466VTEASWQD5XMPD3BLL73RENYAYQTAKJGCYZT3JA/triton_red_fused__to_copy_mean_pow_3.ttgir

@@ -0,0 +1,93 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 4], threadsPerWarp = [1, 32], warpsPerCTA = [4, 1], order = [1, 0]}>
+#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [4, 8], warpsPerCTA = [1, 4], order = [0, 1]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)
+#loc1 = loc(unknown)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:25)
+#loc30 = loc(callsite(#loc1 at #loc23))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mean_pow_3(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<4x128xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<4x128xbf16, #blocked> loc(#loc1)
+    %c4_i32 = arith.constant 4 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<40> : tensor<4x1xi32, #blocked> loc(#loc1)
+    %cst_2 = arith.constant dense<7168> : tensor<4x1xi32, #blocked> loc(#loc1)
+    %cst_3 = arith.constant dense<128> : tensor<4x1xi32, #blocked> loc(#loc1)
+    %cst_4 = arith.constant dense<128> : tensor<1x128xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c4_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 4 : i32, start = 0 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc4)
+    %3 = tt.make_range {end = 4 : i32, start = 0 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc4)
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<4x1xi32, #blocked> loc(#loc4)
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : tensor<4xi32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<4x1xi32, #blocked1> loc(#loc4)
+    %6 = tt.splat %1 : i32 -> tensor<4x1xi32, #blocked> loc(#loc5)
+    %7 = tt.splat %1 : i32 -> tensor<4x1xi32, #blocked1> loc(#loc5)
+    %8 = arith.addi %6, %4 : tensor<4x1xi32, #blocked> loc(#loc5)
+    %9 = arith.addi %7, %5 : tensor<4x1xi32, #blocked1> loc(#loc5)
+    %10 = tt.splat %arg2 : i32 -> tensor<4x1xi32, #blocked> loc(#loc6)
+    %11 = tt.splat %arg2 : i32 -> tensor<4x1xi32, #blocked1> loc(#loc6)
+    %12 = arith.cmpi slt, %8, %10 : tensor<4x1xi32, #blocked> loc(#loc6)
+    %13 = arith.cmpi slt, %9, %11 : tensor<4x1xi32, #blocked1> loc(#loc6)
+    %14 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc7)
+    %15 = tt.expand_dims %14 {axis = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x128xi32, #blocked> loc(#loc7)
+    %16 = arith.remsi %8, %cst_1 : tensor<4x1xi32, #blocked> loc(#loc8)
+    %17 = arith.divsi %8, %cst_1 : tensor<4x1xi32, #blocked> loc(#loc9)
+    %18 = arith.cmpi slt, %15, %cst_4 : tensor<1x128xi32, #blocked> loc(#loc10)
+    %19 = arith.muli %16, %cst_3 : tensor<4x1xi32, #blocked> loc(#loc11)
+    %20 = tt.broadcast %15 : tensor<1x128xi32, #blocked> -> tensor<4x128xi32, #blocked> loc(#loc12)
+    %21 = tt.broadcast %19 : tensor<4x1xi32, #blocked> -> tensor<4x128xi32, #blocked> loc(#loc12)
+    %22 = arith.addi %20, %21 : tensor<4x128xi32, #blocked> loc(#loc12)
+    %23 = arith.muli %17, %cst_2 : tensor<4x1xi32, #blocked> loc(#loc13)
+    %24 = tt.broadcast %23 : tensor<4x1xi32, #blocked> -> tensor<4x128xi32, #blocked> loc(#loc14)
+    %25 = arith.addi %22, %24 : tensor<4x128xi32, #blocked> loc(#loc14)
+    %26 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<4x128x!tt.ptr<bf16>, #blocked> loc(#loc15)
+    %27 = tt.addptr %26, %25 : tensor<4x128x!tt.ptr<bf16>, #blocked>, tensor<4x128xi32, #blocked> loc(#loc15)
+    %28 = tt.broadcast %18 : tensor<1x128xi1, #blocked> -> tensor<4x128xi1, #blocked> loc(#loc16)
+    %29 = tt.broadcast %12 : tensor<4x1xi1, #blocked> -> tensor<4x128xi1, #blocked> loc(#loc16)
+    %30 = arith.andi %28, %29 : tensor<4x128xi1, #blocked> loc(#loc16)
+    %31 = tt.load %27, %30, %cst_0 evictionPolicy = evict_first : tensor<4x128x!tt.ptr<bf16>, #blocked> loc(#loc17)
+    %32 = arith.extf %31 : tensor<4x128xbf16, #blocked> to tensor<4x128xf32, #blocked> loc(#loc18)
+    %33 = arith.mulf %32, %32 : tensor<4x128xf32, #blocked> loc(#loc19)
+    %34 = arith.addf %33, %cst : tensor<4x128xf32, #blocked> loc(#loc20)
+    %35 = arith.select %30, %34, %cst : tensor<4x128xi1, #blocked>, tensor<4x128xf32, #blocked> loc(#loc21)
+    %36 = "tt.reduce"(%35) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc23)), %arg5: f32 loc(callsite(#loc1 at #loc23))):
+      %41 = arith.addf %arg4, %arg5 : f32 loc(#loc32)
+      tt.reduce.return %41 : f32 loc(#loc29)
+    }) : (tensor<4x128xf32, #blocked>) -> tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc29)
+    %37 = ttg.convert_layout %36 : tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc25)
+    %38 = tt.expand_dims %37 {axis = 1 : i32} : tensor<4xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<4x1xf32, #blocked1> loc(#loc25)
+    %39 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<4x1x!tt.ptr<f32>, #blocked1> loc(#loc26)
+    %40 = tt.addptr %39, %9 : tensor<4x1x!tt.ptr<f32>, #blocked1>, tensor<4x1xi32, #blocked1> loc(#loc26)
+    tt.store %40, %38, %13 : tensor<4x1x!tt.ptr<f32>, #blocked1> loc(#loc27)
+    tt.return loc(#loc28)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:44)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:23)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":24:21)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:37)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":27:19)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":28:19)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":33:29)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:45)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:41)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:55)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:50)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:34)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:70)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:60)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:122)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":39:22)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":41:23)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:48)
+#loc22 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc24 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:28)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:25)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:36)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:4)
+#loc29 = loc(callsite(#loc22 at #loc23))
+#loc31 = loc(callsite(#loc24 at #loc22))
+#loc32 = loc(callsite(#loc31 at #loc23))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/WWVE4L3JNPA466VTEASWQD5XMPD3BLL73RENYAYQTAKJGCYZT3JA/triton_red_fused__to_copy_mean_pow_3.ttir

@@ -0,0 +1,86 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)
+#loc1 = loc(unknown)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:25)
+#loc32 = loc(callsite(#loc1 at #loc25))
+module {
+  tt.func public @triton_red_fused__to_copy_mean_pow_3(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<4x128xbf16> loc(#loc1)
+    %cst_0 = arith.constant dense<7168> : tensor<4x1xi32> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<4x1xi32> loc(#loc1)
+    %cst_2 = arith.constant dense<128> : tensor<1x128xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<4x128xf32> loc(#loc1)
+    %cst_4 = arith.constant dense<40> : tensor<4x1xi32> loc(#loc1)
+    %c4_i32 = arith.constant 4 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c4_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 4 : i32, start = 0 : i32} : tensor<4xi32> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : tensor<4xi32> -> tensor<4x1xi32> loc(#loc5)
+    %4 = tt.splat %1 : i32 -> tensor<4x1xi32> loc(#loc6)
+    %5 = arith.addi %4, %3 : tensor<4x1xi32> loc(#loc6)
+    %6 = tt.splat %arg2 : i32 -> tensor<4x1xi32> loc(#loc7)
+    %7 = arith.cmpi slt, %5, %6 : tensor<4x1xi32> loc(#loc7)
+    %8 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32> loc(#loc8)
+    %9 = tt.expand_dims %8 {axis = 0 : i32} : tensor<128xi32> -> tensor<1x128xi32> loc(#loc9)
+    %10 = arith.remsi %5, %cst_4 : tensor<4x1xi32> loc(#loc10)
+    %11 = arith.divsi %5, %cst_4 : tensor<4x1xi32> loc(#loc11)
+    %12 = arith.cmpi slt, %9, %cst_2 : tensor<1x128xi32> loc(#loc12)
+    %13 = arith.muli %10, %cst_1 : tensor<4x1xi32> loc(#loc13)
+    %14 = tt.broadcast %9 : tensor<1x128xi32> -> tensor<4x128xi32> loc(#loc14)
+    %15 = tt.broadcast %13 : tensor<4x1xi32> -> tensor<4x128xi32> loc(#loc14)
+    %16 = arith.addi %14, %15 : tensor<4x128xi32> loc(#loc14)
+    %17 = arith.muli %11, %cst_0 : tensor<4x1xi32> loc(#loc15)
+    %18 = tt.broadcast %17 : tensor<4x1xi32> -> tensor<4x128xi32> loc(#loc16)
+    %19 = arith.addi %16, %18 : tensor<4x128xi32> loc(#loc16)
+    %20 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<4x128x!tt.ptr<bf16>> loc(#loc17)
+    %21 = tt.addptr %20, %19 : tensor<4x128x!tt.ptr<bf16>>, tensor<4x128xi32> loc(#loc17)
+    %22 = tt.broadcast %12 : tensor<1x128xi1> -> tensor<4x128xi1> loc(#loc18)
+    %23 = tt.broadcast %7 : tensor<4x1xi1> -> tensor<4x128xi1> loc(#loc18)
+    %24 = arith.andi %22, %23 : tensor<4x128xi1> loc(#loc18)
+    %25 = tt.load %21, %24, %cst evictionPolicy = evict_first : tensor<4x128x!tt.ptr<bf16>> loc(#loc19)
+    %26 = arith.extf %25 : tensor<4x128xbf16> to tensor<4x128xf32> loc(#loc20)
+    %27 = arith.mulf %26, %26 : tensor<4x128xf32> loc(#loc21)
+    %28 = arith.addf %27, %cst_3 : tensor<4x128xf32> loc(#loc22)
+    %29 = arith.select %24, %28, %cst_3 : tensor<4x128xi1>, tensor<4x128xf32> loc(#loc23)
+    %30 = "tt.reduce"(%29) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc25)), %arg5: f32 loc(callsite(#loc1 at #loc25))):
+      %34 = arith.addf %arg4, %arg5 : f32 loc(#loc34)
+      tt.reduce.return %34 : f32 loc(#loc31)
+    }) : (tensor<4x128xf32>) -> tensor<4xf32> loc(#loc31)
+    %31 = tt.expand_dims %30 {axis = 1 : i32} : tensor<4xf32> -> tensor<4x1xf32> loc(#loc27)
+    %32 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<4x1x!tt.ptr<f32>> loc(#loc28)
+    %33 = tt.addptr %32, %5 : tensor<4x1x!tt.ptr<f32>>, tensor<4x1xi32> loc(#loc28)
+    tt.store %33, %31, %7 : tensor<4x1x!tt.ptr<f32>> loc(#loc29)
+    tt.return loc(#loc30)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:44)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:23)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":24:21)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:27)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:37)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":27:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":28:19)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":33:29)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:45)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:41)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:55)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:50)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:34)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:70)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:60)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:122)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":39:22)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":41:23)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:48)
+#loc24 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc26 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc27 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:28)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:25)
+#loc29 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:36)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:4)
+#loc31 = loc(callsite(#loc24 at #loc25))
+#loc33 = loc(callsite(#loc26 at #loc24))
+#loc34 = loc(callsite(#loc33 at #loc25))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/__grp__triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"child_paths": {"triton_red_fused__to_copy_mean_pow_3.ttir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.ttir", "triton_red_fused__to_copy_mean_pow_3.ttgir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.ttgir", "triton_red_fused__to_copy_mean_pow_3.llir": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.llir", "triton_red_fused__to_copy_mean_pow_3.ptx": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.ptx", "triton_red_fused__to_copy_mean_pow_3.cubin": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.cubin", "triton_red_fused__to_copy_mean_pow_3.json": "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.json"}}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.json

@@ -0,0 +1 @@
+{"hash": "bc31c8323f1b2a8da3d3e7c56533445c5ca2f65ffd332b3a499eb967432ea122", "target": {"backend": "cuda", "arch": 90, "warp_size": 32}, "num_warps": 8, "num_ctas": 1, "num_stages": 1, "num_buffers_warp_spec": 0, "num_consumer_groups": 0, "reg_dec_producer": 0, "reg_inc_consumer": 0, "maxnreg": null, "cluster_dims": [1, 1, 1], "ptx_version": null, "enable_fp_fusion": true, "launch_cooperative_grid": false, "supported_fp8_dtypes": ["fp8e4b15", "fp8e4nv", "fp8e5"], "deprecated_fp8_dtypes": ["fp8e4b15"], "default_dot_input_precision": "tf32", "allowed_dot_input_precisions": ["tf32", "tf32x3", "ieee"], "max_num_imprecise_acc_default": 1073741824, "extern_libs": [["libdevice", "/home/x/hfenv/lib/python3.12/site-packages/triton/backends/nvidia/lib/libdevice.10.bc"]], "debug": true, "backend_name": "cuda", "sanitize_overflow": false, "arch": "sm90", "triton_version": "3.3.1", "shared": 256, "tmem_size": 0, "global_scratch_size": 0, "global_scratch_align": 1, "name": "triton_red_fused__to_copy_mean_pow_3"}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.ptx

@@ -0,0 +1,635 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.4
+.target sm_90a
+.address_size 64
+
+	// .globl	triton_red_fused__to_copy_mean_pow_3 // -- Begin function triton_red_fused__to_copy_mean_pow_3
+.extern .shared .align 16 .b8 global_smem[];
+                                        // @triton_red_fused__to_copy_mean_pow_3
+.visible .entry triton_red_fused__to_copy_mean_pow_3(
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_0,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_1,
+	.param .u32 triton_red_fused__to_copy_mean_pow_3_param_2,
+	.param .u32 triton_red_fused__to_copy_mean_pow_3_param_3,
+	.param .u64 .ptr .global .align 1 triton_red_fused__to_copy_mean_pow_3_param_4
+)
+.reqntid 256, 1, 1
+{
+	.reg .pred 	%p<40>;
+	.reg .b16 	%rs<67>;
+	.reg .b32 	%r<39>;
+	.reg .f32 	%f<13>;
+	.reg .b64 	%rd<46>;
+	.loc	1 18 0                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:18:0
+$L__func_begin0:
+	.loc	1 18 0                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:18:0
+
+// %bb.0:
+	ld.param.u32 	%r8, [triton_red_fused__to_copy_mean_pow_3_param_2];
+	ld.param.u64 	%rd5, [triton_red_fused__to_copy_mean_pow_3_param_1];
+	ld.param.u64 	%rd4, [triton_red_fused__to_copy_mean_pow_3_param_0];
+$L__tmp0:
+	.loc	1 22 28                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:22:28
+	mov.u32 	%r1, %ctaid.x;
+	.loc	1 22 33                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:22:33
+	shl.b32 	%r2, %r1, 6;
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	mov.u32 	%r3, %tid.x;
+	bfe.u32 	%r4, %r3, 2, 6;
+	and.b32  	%r5, %r3, 3;
+	.loc	1 23 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:23
+	or.b32  	%r9, %r4, %r2;
+	.loc	1 28 19                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:28:19
+	mul.hi.s32 	%r10, %r9, 1717986919;
+	shr.u32 	%r11, %r10, 31;
+	shr.s32 	%r12, %r10, 4;
+	add.s32 	%r6, %r12, %r11;
+	setp.ge.s32 	%p1, %r9, %r8;
+	@%p1 bra 	$L__BB0_4;
+// %bb.1:                               // %.split.us.preheader
+	.loc	1 31 40                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:31:40
+	shl.b32 	%r17, %r1, 13;
+	shl.b32 	%r18, %r6, 11;
+	add.s32 	%r19, %r17, %r18;
+	shl.b32 	%r20, %r4, 7;
+	add.s32 	%r21, %r19, %r20;
+	or.b32  	%r22, %r21, %r5;
+	cvt.u64.u32 	%rd1, %r22;
+	mov.f32 	%f12, 0f00000000;
+	mov.b64 	%rd45, -4;
+$L__BB0_2:                              // %.split.us
+                                        // =>This Inner Loop Header: Depth=1
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd41, %rd1, %rd45;
+	cvt.u32.u64 	%r23, %rd41;
+	add.s32 	%r24, %r23, 4;
+	mul.wide.s32 	%rd42, %r24, 2;
+	add.s64 	%rd40, %rd4, %rd42;
+	mov.b16 	%rs66, 0;
+	mov.pred 	%p34, -1;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs65, %rs66;
+	@%p34 ld.global.L1::evict_first.b16 { %rs65 }, [ %rd40 + 0 ];
+	// end inline asm
+	.loc	1 37 122                        // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:122
+	cvt.f32.bf16 	%f6, %rs65;
+	.loc	1 41 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:41:23
+	fma.rn.f32 	%f12, %f6, %f6, %f12;
+	.loc	1 31 40                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:31:40
+	add.s64 	%rd45, %rd45, 4;
+	setp.lt.u64 	%p35, %rd45, 124;
+	@%p35 bra 	$L__BB0_2;
+	bra.uni 	$L__BB0_3;
+$L__BB0_4:                              // %.split.preheader
+	.loc	1 0 40                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:0:40
+	mul.lo.s32 	%r13, %r6, 40;
+	sub.s32 	%r14, %r9, %r13;
+	shl.b32 	%r15, %r14, 7;
+	or.b32  	%r16, %r15, %r5;
+	mad.lo.s32 	%r7, %r6, 7168, %r16;
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	mul.wide.s32 	%rd38, %r7, 2;
+	add.s64 	%rd6, %rd4, %rd38;
+	mov.b16 	%rs2, 0;
+	mov.pred 	%p2, 0;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs1, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs1 }, [ %rd6 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd7, %rd6, 8;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs3, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs3 }, [ %rd7 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd8, %rd6, 16;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs5, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs5 }, [ %rd8 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd9, %rd6, 24;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs7, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs7 }, [ %rd9 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd10, %rd6, 32;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs9, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs9 }, [ %rd10 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd11, %rd6, 40;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs11, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs11 }, [ %rd11 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd12, %rd6, 48;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs13, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs13 }, [ %rd12 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd13, %rd6, 56;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs15, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs15 }, [ %rd13 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd14, %rd6, 64;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs17, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs17 }, [ %rd14 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd15, %rd6, 72;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs19, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs19 }, [ %rd15 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd16, %rd6, 80;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs21, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs21 }, [ %rd16 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd17, %rd6, 88;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs23, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs23 }, [ %rd17 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd18, %rd6, 96;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs25, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs25 }, [ %rd18 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd19, %rd6, 104;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs27, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs27 }, [ %rd19 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd20, %rd6, 112;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs29, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs29 }, [ %rd20 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd21, %rd6, 120;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs31, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs31 }, [ %rd21 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd22, %rd6, 128;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs33, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs33 }, [ %rd22 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd23, %rd6, 136;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs35, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs35 }, [ %rd23 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd24, %rd6, 144;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs37, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs37 }, [ %rd24 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd25, %rd6, 152;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs39, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs39 }, [ %rd25 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd26, %rd6, 160;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs41, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs41 }, [ %rd26 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd27, %rd6, 168;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs43, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs43 }, [ %rd27 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd28, %rd6, 176;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs45, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs45 }, [ %rd28 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd29, %rd6, 184;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs47, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs47 }, [ %rd29 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd30, %rd6, 192;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs49, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs49 }, [ %rd30 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd31, %rd6, 200;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs51, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs51 }, [ %rd31 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd32, %rd6, 208;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs53, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs53 }, [ %rd32 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd33, %rd6, 216;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs55, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs55 }, [ %rd33 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd34, %rd6, 224;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs57, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs57 }, [ %rd34 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd35, %rd6, 232;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs59, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs59 }, [ %rd35 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd36, %rd6, 240;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs61, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs61 }, [ %rd36 + 0 ];
+	// end inline asm
+	.loc	1 37 34                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:34
+	add.s64 	%rd37, %rd6, 248;
+	.loc	1 37 60                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:37:60
+	// begin inline asm
+	mov.u16 %rs63, %rs2;
+	@%p2 ld.global.L1::evict_first.b16 { %rs63 }, [ %rd37 + 0 ];
+	// end inline asm
+	mov.f32 	%f12, 0f00000000;
+$L__BB0_3:                              // %.split3.us
+	.loc	1 23 44                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:44
+	and.b32  	%r28, %r3, 63;
+	.loc	1 23 23                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:23:23
+	or.b32  	%r29, %r2, %r28;
+	.loc	1 24 21                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:24:21
+	setp.lt.s32 	%p38, %r29, %r8;
+$L__tmp1:
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r30, %f12;
+	shfl.sync.bfly.b32	%r31, %r30, 2, 31, -1;
+	mov.b32 	%f7, %r31;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f8, %f12, %f7;
+	.loc	2 286 36                        // standard.py:286:36
+	mov.b32 	%r32, %f8;
+	shfl.sync.bfly.b32	%r33, %r32, 1, 31, -1;
+	mov.b32 	%f9, %r33;
+	.loc	2 256 15                        // standard.py:256:15
+	add.f32 	%f10, %f8, %f9;
+$L__tmp2:
+	.loc	1 43 28                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:43:28
+	shl.b32 	%r34, %r4, 2;
+	mov.u32 	%r35, global_smem;
+	add.s32 	%r25, %r35, %r34;
+	mov.b32 	%r26, %f10;
+	mov.pred 	%p36, -1;
+	// begin inline asm
+	@%p36 st.shared.b32 [ %r25 + 0 ], %r26;
+	// end inline asm
+	bar.sync 	0;
+	shl.b32 	%r36, %r28, 2;
+	add.s32 	%r37, %r35, %r36;
+	ld.shared.u32 	%r27, [%r37];
+	.loc	1 44 25                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:25
+	mul.wide.s32 	%rd44, %r29, 4;
+	add.s64 	%rd43, %rd5, %rd44;
+	.loc	1 44 36                         // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:36
+	and.b32  	%r38, %r3, 192;
+	setp.eq.s32 	%p39, %r38, 0;
+	and.pred  	%p37, %p39, %p38;
+	// begin inline asm
+	@%p37 st.global.b32 [ %rd43 + 0 ], { %r27 };
+	// end inline asm
+	.loc	1 44 4                          // clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py:44:4
+	ret;
+$L__tmp3:
+$L__func_end0:
+                                        // -- End function
+}
+	.file	1 "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py"
+	.file	2 "/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1                                   // Abbreviation Code
+.b8 17                                  // DW_TAG_compile_unit
+.b8 1                                   // DW_CHILDREN_yes
+.b8 37                                  // DW_AT_producer
+.b8 8                                   // DW_FORM_string
+.b8 19                                  // DW_AT_language
+.b8 5                                   // DW_FORM_data2
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 16                                  // DW_AT_stmt_list
+.b8 6                                   // DW_FORM_data4
+.b8 27                                  // DW_AT_comp_dir
+.b8 8                                   // DW_FORM_string
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 2                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 0                                   // DW_CHILDREN_no
+.b8 3                                   // DW_AT_name
+.b8 8                                   // DW_FORM_string
+.b8 32                                  // DW_AT_inline
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 3                                   // Abbreviation Code
+.b8 46                                  // DW_TAG_subprogram
+.b8 1                                   // DW_CHILDREN_yes
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 4                                   // Abbreviation Code
+.b8 29                                  // DW_TAG_inlined_subroutine
+.b8 0                                   // DW_CHILDREN_no
+.b8 49                                  // DW_AT_abstract_origin
+.b8 19                                  // DW_FORM_ref4
+.b8 17                                  // DW_AT_low_pc
+.b8 1                                   // DW_FORM_addr
+.b8 18                                  // DW_AT_high_pc
+.b8 1                                   // DW_FORM_addr
+.b8 88                                  // DW_AT_call_file
+.b8 11                                  // DW_FORM_data1
+.b8 89                                  // DW_AT_call_line
+.b8 11                                  // DW_FORM_data1
+.b8 87                                  // DW_AT_call_column
+.b8 11                                  // DW_FORM_data1
+.b8 0                                   // EOM(1)
+.b8 0                                   // EOM(2)
+.b8 0                                   // EOM(3)
+	}
+	.section	.debug_info
+	{
+.b32 241                                // Length of Unit
+.b8 2                                   // DWARF version number
+.b8 0
+.b32 .debug_abbrev                      // Offset Into Abbrev. Section
+.b8 8                                   // Address Size (in bytes)
+.b8 1                                   // Abbrev [1] 0xb:0xea DW_TAG_compile_unit
+.b8 116                                 // DW_AT_producer
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2                                   // DW_AT_language
+.b8 0
+.b8 99                                  // DW_AT_name
+.b8 108
+.b8 107
+.b8 98
+.b8 102
+.b8 110
+.b8 51
+.b8 118
+.b8 110
+.b8 116
+.b8 114
+.b8 106
+.b8 114
+.b8 111
+.b8 104
+.b8 55
+.b8 114
+.b8 118
+.b8 54
+.b8 112
+.b8 97
+.b8 112
+.b8 109
+.b8 102
+.b8 55
+.b8 51
+.b8 118
+.b8 119
+.b8 122
+.b8 102
+.b8 120
+.b8 109
+.b8 109
+.b8 105
+.b8 115
+.b8 113
+.b8 112
+.b8 50
+.b8 105
+.b8 53
+.b8 55
+.b8 113
+.b8 51
+.b8 100
+.b8 105
+.b8 113
+.b8 53
+.b8 121
+.b8 112
+.b8 51
+.b8 103
+.b8 120
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line                        // DW_AT_stmt_list
+.b8 47                                  // DW_AT_comp_dir
+.b8 104
+.b8 111
+.b8 109
+.b8 101
+.b8 47
+.b8 120
+.b8 47
+.b8 46
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 118
+.b8 108
+.b8 108
+.b8 109
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 95
+.b8 99
+.b8 111
+.b8 109
+.b8 112
+.b8 105
+.b8 108
+.b8 101
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 57
+.b8 48
+.b8 98
+.b8 52
+.b8 53
+.b8 98
+.b8 99
+.b8 101
+.b8 48
+.b8 50
+.b8 47
+.b8 114
+.b8 97
+.b8 110
+.b8 107
+.b8 95
+.b8 48
+.b8 95
+.b8 48
+.b8 47
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 99
+.b8 97
+.b8 99
+.b8 104
+.b8 101
+.b8 47
+.b8 108
+.b8 107
+.b8 0
+.b8 2                                   // Abbrev [2] 0x9f:0x27 DW_TAG_subprogram
+.b8 116                                 // DW_AT_name
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 114
+.b8 101
+.b8 100
+.b8 95
+.b8 102
+.b8 117
+.b8 115
+.b8 101
+.b8 100
+.b8 95
+.b8 95
+.b8 116
+.b8 111
+.b8 95
+.b8 99
+.b8 111
+.b8 112
+.b8 121
+.b8 95
+.b8 109
+.b8 101
+.b8 97
+.b8 110
+.b8 95
+.b8 112
+.b8 111
+.b8 119
+.b8 95
+.b8 51
+.b8 0
+.b8 1                                   // DW_AT_inline
+.b8 3                                   // Abbrev [3] 0xc6:0x2e DW_TAG_subprogram
+.b64 $L__func_begin0                    // DW_AT_low_pc
+.b64 $L__func_end0                      // DW_AT_high_pc
+.b32 159                                // DW_AT_abstract_origin
+.b8 4                                   // Abbrev [4] 0xdb:0x18 DW_TAG_inlined_subroutine
+.b32 159                                // DW_AT_abstract_origin
+.b64 $L__tmp1                           // DW_AT_low_pc
+.b64 $L__tmp2                           // DW_AT_high_pc
+.b8 1                                   // DW_AT_call_file
+.b8 43                                  // DW_AT_call_line
+.b8 25                                  // DW_AT_call_column
+.b8 0                                   // End Of Children Mark
+.b8 0                                   // End Of Children Mark
+	}
+	.section	.debug_macinfo	{	}

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/XQY4QMR7DMVI3I6T47CWKM2ELROKF5S77UZSWOSJT24WOQZOUERA/triton_red_fused__to_copy_mean_pow_3.ttir

@@ -0,0 +1,97 @@
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)
+#loc1 = loc(unknown)
+#loc28 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:25)
+#loc35 = loc(callsite(#loc1 at #loc28))
+module {
+  tt.func public @triton_red_fused__to_copy_mean_pow_3(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x4xbf16> loc(#loc1)
+    %c4_i32 = arith.constant 4 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %c0_i32 = arith.constant 0 : i32 loc(#loc1)
+    %cst_0 = arith.constant dense<7168> : tensor<64x1xi32> loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<64x1xi32> loc(#loc1)
+    %cst_2 = arith.constant dense<128> : tensor<1x4xi32> loc(#loc1)
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<64x4xf32> loc(#loc1)
+    %cst_4 = arith.constant dense<40> : tensor<64x1xi32> loc(#loc1)
+    %c64_i32 = arith.constant 64 : i32 loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.muli %0, %c64_i32 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : tensor<64xi32> -> tensor<64x1xi32> loc(#loc5)
+    %4 = tt.splat %1 : i32 -> tensor<64x1xi32> loc(#loc6)
+    %5 = arith.addi %4, %3 : tensor<64x1xi32> loc(#loc6)
+    %6 = tt.splat %arg2 : i32 -> tensor<64x1xi32> loc(#loc7)
+    %7 = arith.cmpi slt, %5, %6 : tensor<64x1xi32> loc(#loc7)
+    %8 = tt.make_range {end = 4 : i32, start = 0 : i32} : tensor<4xi32> loc(#loc8)
+    %9 = tt.expand_dims %8 {axis = 0 : i32} : tensor<4xi32> -> tensor<1x4xi32> loc(#loc9)
+    %10 = arith.remsi %5, %cst_4 : tensor<64x1xi32> loc(#loc10)
+    %11 = arith.divsi %5, %cst_4 : tensor<64x1xi32> loc(#loc11)
+    %12 = scf.for %arg4 = %c0_i32 to %c128_i32 step %c4_i32 iter_args(%arg5 = %cst_3) -> (tensor<64x4xf32>)  : i32 {
+      %17 = tt.splat %arg4 : i32 -> tensor<1x4xi32> loc(#loc13)
+      %18 = arith.addi %17, %9 : tensor<1x4xi32> loc(#loc13)
+      %19 = arith.cmpi slt, %18, %cst_2 : tensor<1x4xi32> loc(#loc14)
+      %20 = arith.muli %10, %cst_1 : tensor<64x1xi32> loc(#loc15)
+      %21 = tt.broadcast %18 : tensor<1x4xi32> -> tensor<64x4xi32> loc(#loc16)
+      %22 = tt.broadcast %20 : tensor<64x1xi32> -> tensor<64x4xi32> loc(#loc16)
+      %23 = arith.addi %21, %22 : tensor<64x4xi32> loc(#loc16)
+      %24 = arith.muli %11, %cst_0 : tensor<64x1xi32> loc(#loc17)
+      %25 = tt.broadcast %24 : tensor<64x1xi32> -> tensor<64x4xi32> loc(#loc18)
+      %26 = arith.addi %23, %25 : tensor<64x4xi32> loc(#loc18)
+      %27 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<64x4x!tt.ptr<bf16>> loc(#loc19)
+      %28 = tt.addptr %27, %26 : tensor<64x4x!tt.ptr<bf16>>, tensor<64x4xi32> loc(#loc19)
+      %29 = tt.broadcast %19 : tensor<1x4xi1> -> tensor<64x4xi1> loc(#loc20)
+      %30 = tt.broadcast %7 : tensor<64x1xi1> -> tensor<64x4xi1> loc(#loc20)
+      %31 = arith.andi %29, %30 : tensor<64x4xi1> loc(#loc20)
+      %32 = tt.load %28, %31, %cst evictionPolicy = evict_first : tensor<64x4x!tt.ptr<bf16>> loc(#loc21)
+      %33 = arith.extf %32 : tensor<64x4xbf16> to tensor<64x4xf32> loc(#loc22)
+      %34 = arith.mulf %33, %33 : tensor<64x4xf32> loc(#loc23)
+      %35 = arith.addf %arg5, %34 : tensor<64x4xf32> loc(#loc24)
+      %36 = arith.select %31, %35, %arg5 : tensor<64x4xi1>, tensor<64x4xf32> loc(#loc25)
+      scf.yield %36 : tensor<64x4xf32> loc(#loc26)
+    } loc(#loc12)
+    %13 = "tt.reduce"(%12) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc28)), %arg5: f32 loc(callsite(#loc1 at #loc28))):
+      %17 = arith.addf %arg4, %arg5 : f32 loc(#loc37)
+      tt.reduce.return %17 : f32 loc(#loc34)
+    }) : (tensor<64x4xf32>) -> tensor<64xf32> loc(#loc34)
+    %14 = tt.expand_dims %13 {axis = 1 : i32} : tensor<64xf32> -> tensor<64x1xf32> loc(#loc30)
+    %15 = tt.splat %arg1 : !tt.ptr<f32> -> tensor<64x1x!tt.ptr<f32>> loc(#loc31)
+    %16 = tt.addptr %15, %5 : tensor<64x1x!tt.ptr<f32>>, tensor<64x1xi32> loc(#loc31)
+    tt.store %16, %14, %7 : tensor<64x1x!tt.ptr<f32>> loc(#loc32)
+    tt.return loc(#loc33)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:33)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:36)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:44)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":23:23)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":24:21)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:27)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:37)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":27:19)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":28:19)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":31:40)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":32:31)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":33:29)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:45)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:41)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:55)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:50)
+#loc19 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:34)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:70)
+#loc21 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:60)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:122)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":39:22)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":41:23)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:48)
+#loc26 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:8)
+#loc27 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc29 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc30 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:28)
+#loc31 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:25)
+#loc32 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:36)
+#loc33 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:4)
+#loc34 = loc(callsite(#loc27 at #loc28))
+#loc36 = loc(callsite(#loc29 at #loc27))
+#loc37 = loc(callsite(#loc36 at #loc28))

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/ZJDU4EODRWXUWRHXXXMJN25SB6P3QV3CZYCSOPU6H44DZVCRHICA/triton_red_fused__to_copy_mean_pow_3.llir

@@ -0,0 +1,135 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+
+@global_smem = external addrspace(3) global [0 x i8], align 16
+
+define ptx_kernel void @triton_red_fused__to_copy_mean_pow_3(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2, i32 %3, ptr addrspace(1) readnone captures(none) %4) local_unnamed_addr !dbg !6 {
+  %6 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !dbg !9
+  %7 = icmp slt i32 %6, %2, !dbg !10
+  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !11
+  %9 = and i32 %8, 31, !dbg !11
+  %10 = lshr i32 %8, 5, !dbg !11
+  %11 = shl i32 %8, 1, !dbg !11
+  %12 = and i32 %11, 126, !dbg !11
+  %13 = sdiv i32 %6, 40, !dbg !12
+  %14 = mul i32 %13, 40, !dbg !13
+  %.decomposed = sub i32 %6, %14, !dbg !13
+  %15 = shl nsw i32 %.decomposed, 7, !dbg !14
+  %16 = or disjoint i32 %12, %15, !dbg !15
+  %17 = mul i32 %13, 7168, !dbg !16
+  %18 = add i32 %16, %17, !dbg !17
+  %19 = sext i32 %18 to i64, !dbg !18
+  %20 = getelementptr bfloat, ptr addrspace(1) %0, i64 %19, !dbg !18
+  %21 = tail call i32 asm sideeffect "mov.u32 $0, $1;\0A\09@$3 ld.global.L1::evict_first.b32 { $0 }, [ $2 + 0 ];", "=r,r,l,b"(i32 0, ptr addrspace(1) %20, i1 %7) #3, !dbg !19
+  %22 = bitcast i32 %21 to <2 x bfloat>, !dbg !19
+  %23 = extractelement <2 x bfloat> %22, i64 0, !dbg !19
+  %24 = extractelement <2 x bfloat> %22, i64 1, !dbg !19
+  %25 = fpext bfloat %23 to float, !dbg !20
+  %26 = fpext bfloat %24 to float, !dbg !20
+  %27 = fmul float %25, %25, !dbg !21
+  %28 = fmul float %26, %26, !dbg !21
+  %29 = fadd float %27, %28, !dbg !22
+  %30 = select i1 %7, float %29, float 0.000000e+00, !dbg !22
+  %31 = bitcast float %30 to i32, !dbg !27
+  %32 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %31, i32 16, i32 31), !dbg !27
+  %33 = bitcast i32 %32 to float, !dbg !27
+  %34 = fadd float %30, %33, !dbg !22
+  %35 = bitcast float %34 to i32, !dbg !27
+  %36 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %35, i32 8, i32 31), !dbg !27
+  %37 = bitcast i32 %36 to float, !dbg !27
+  %38 = fadd float %34, %37, !dbg !22
+  %39 = bitcast float %38 to i32, !dbg !27
+  %40 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %39, i32 4, i32 31), !dbg !27
+  %41 = bitcast i32 %40 to float, !dbg !27
+  %42 = fadd float %38, %41, !dbg !22
+  %43 = bitcast float %42 to i32, !dbg !27
+  %44 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %43, i32 2, i32 31), !dbg !27
+  %45 = bitcast i32 %44 to float, !dbg !27
+  %46 = fadd float %42, %45, !dbg !22
+  %47 = bitcast float %46 to i32, !dbg !27
+  %48 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %47, i32 1, i32 31), !dbg !27
+  %49 = bitcast i32 %48 to float, !dbg !27
+  %50 = fadd float %46, %49, !dbg !22
+  %51 = and i32 %10, 1, !dbg !27
+  %52 = icmp eq i32 %9, 0, !dbg !27
+  %53 = getelementptr float, ptr addrspace(3) @global_smem, i32 %51, !dbg !27
+  %54 = bitcast float %50 to <1 x i32>, !dbg !27
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %53, <1 x i32> %54, i1 %52) #3, !dbg !27
+  tail call void @llvm.nvvm.barrier0(), !dbg !27
+  %55 = icmp slt i32 %8, 2, !dbg !27
+  %56 = getelementptr float, ptr addrspace(3) @global_smem, i32 %8, !dbg !27
+  %57 = tail call i32 asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %56, i1 %55) #3, !dbg !27
+  %58 = bitcast i32 %57 to float, !dbg !27
+  %59 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %57, i32 1, i32 31), !dbg !27
+  %60 = bitcast i32 %59 to float, !dbg !27
+  %61 = fadd float %58, %60, !dbg !22
+  %62 = and i32 %8, 1, !dbg !27
+  %63 = icmp eq i32 %62, 0, !dbg !27
+  %64 = and i1 %55, %63, !dbg !27
+  %65 = bitcast float %61 to <1 x i32>, !dbg !27
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %56, <1 x i32> %65, i1 %64) #3, !dbg !27
+  tail call void @llvm.nvvm.barrier0(), !dbg !27
+  %66 = load i32, ptr addrspace(3) @global_smem, align 16, !dbg !27
+  %67 = sext i32 %6 to i64, !dbg !28
+  %68 = getelementptr float, ptr addrspace(1) %1, i64 %67, !dbg !28
+  %69 = and i32 %8, 63, !dbg !29
+  %70 = icmp eq i32 %69, 0, !dbg !29
+  %71 = and i1 %70, %7, !dbg !29
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %66, ptr addrspace(1) %68, i1 %71) #3, !dbg !29
+  ret void, !dbg !30
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4}
+!llvm.ident = !{!5}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
+!3 = !DIFile(filename: "clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py", directory: "/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk")
+!4 = !{ptr @triton_red_fused__to_copy_mean_pow_3, !"reqntidx", i32 64}
+!5 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!6 = distinct !DISubprogram(name: "triton_red_fused__to_copy_mean_pow_3", linkageName: "triton_red_fused__to_copy_mean_pow_3", scope: !3, file: !3, line: 18, type: !7, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!7 = !DISubroutineType(cc: DW_CC_normal, types: !8)
+!8 = !{}
+!9 = !DILocation(line: 22, column: 28, scope: !6)
+!10 = !DILocation(line: 24, column: 21, scope: !6)
+!11 = !DILocation(line: 25, column: 37, scope: !6)
+!12 = !DILocation(line: 28, column: 19, scope: !6)
+!13 = !DILocation(line: 27, column: 19, scope: !6)
+!14 = !DILocation(line: 37, column: 45, scope: !6)
+!15 = !DILocation(line: 37, column: 41, scope: !6)
+!16 = !DILocation(line: 37, column: 55, scope: !6)
+!17 = !DILocation(line: 37, column: 50, scope: !6)
+!18 = !DILocation(line: 37, column: 34, scope: !6)
+!19 = !DILocation(line: 37, column: 60, scope: !6)
+!20 = !DILocation(line: 37, column: 122, scope: !6)
+!21 = !DILocation(line: 39, column: 22, scope: !6)
+!22 = !DILocation(line: 256, column: 15, scope: !23, inlinedAt: !26)
+!23 = distinct !DILexicalBlockFile(scope: !25, file: !24, discriminator: 0)
+!24 = !DIFile(filename: "standard.py", directory: "/home/x/hfenv/lib/python3.12/site-packages/triton/language")
+!25 = distinct !DILexicalBlockFile(scope: !6, file: !24, discriminator: 0)
+!26 = !DILocation(line: 43, column: 25, scope: !6)
+!27 = !DILocation(line: 286, column: 36, scope: !25, inlinedAt: !26)
+!28 = !DILocation(line: 44, column: 25, scope: !6)
+!29 = !DILocation(line: 44, column: 36, scope: !6)
+!30 = !DILocation(line: 44, column: 4, scope: !6)

platform/aiml/models/vllm/torch_compile_cache/90b45bce02/rank_0_0/triton_cache/ZJDU4EODRWXUWRHXXXMJN25SB6P3QV3CZYCSOPU6H44DZVCRHICA/triton_red_fused__to_copy_mean_pow_3.ttgir

@@ -0,0 +1,79 @@
+#blocked = #ttg.blocked<{sizePerThread = [1, 2], threadsPerWarp = [1, 32], warpsPerCTA = [1, 2], order = [1, 0]}>
+#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 2], order = [0, 1]}>
+#loc = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)
+#loc1 = loc(unknown)
+#loc20 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:25)
+#loc30 = loc(callsite(#loc1 at #loc20))
+module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 2 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
+  tt.func public @triton_red_fused__to_copy_mean_pow_3(%arg0: !tt.ptr<bf16> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg2: i32 loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0), %arg3: i32 {tt.divisibility = 16 : i32} loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":18:0)) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1x128xf32, #blocked> loc(#loc1)
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<1x128xbf16, #blocked> loc(#loc1)
+    %c7168_i32 = arith.constant 7168 : i32 loc(#loc1)
+    %c128_i32 = arith.constant 128 : i32 loc(#loc1)
+    %c40_i32 = arith.constant 40 : i32 loc(#loc1)
+    %cst_1 = arith.constant dense<128> : tensor<1x128xi32, #blocked> loc(#loc1)
+    %0 = tt.get_program_id x : i32 loc(#loc2)
+    %1 = arith.cmpi slt, %0, %arg2 : i32 loc(#loc3)
+    %2 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> loc(#loc4)
+    %3 = tt.expand_dims %2 {axis = 0 : i32} : tensor<128xi32, #ttg.slice<{dim = 0, parent = #blocked}>> -> tensor<1x128xi32, #blocked> loc(#loc4)
+    %4 = arith.remsi %0, %c40_i32 : i32 loc(#loc5)
+    %5 = arith.divsi %0, %c40_i32 : i32 loc(#loc6)
+    %6 = arith.cmpi slt, %3, %cst_1 : tensor<1x128xi32, #blocked> loc(#loc7)
+    %7 = arith.muli %4, %c128_i32 : i32 loc(#loc8)
+    %8 = tt.splat %7 : i32 -> tensor<1x128xi32, #blocked> loc(#loc26)
+    %9 = arith.addi %3, %8 : tensor<1x128xi32, #blocked> loc(#loc9)
+    %10 = arith.muli %5, %c7168_i32 : i32 loc(#loc10)
+    %11 = tt.splat %10 : i32 -> tensor<1x128xi32, #blocked> loc(#loc27)
+    %12 = arith.addi %9, %11 : tensor<1x128xi32, #blocked> loc(#loc11)
+    %13 = tt.splat %arg0 : !tt.ptr<bf16> -> tensor<1x128x!tt.ptr<bf16>, #blocked> loc(#loc12)
+    %14 = tt.addptr %13, %12 : tensor<1x128x!tt.ptr<bf16>, #blocked>, tensor<1x128xi32, #blocked> loc(#loc12)
+    %15 = tt.splat %1 : i1 -> tensor<1x128xi1, #blocked> loc(#loc28)
+    %16 = arith.andi %6, %15 : tensor<1x128xi1, #blocked> loc(#loc13)
+    %17 = tt.load %14, %16, %cst_0 evictionPolicy = evict_first : tensor<1x128x!tt.ptr<bf16>, #blocked> loc(#loc14)
+    %18 = arith.extf %17 : tensor<1x128xbf16, #blocked> to tensor<1x128xf32, #blocked> loc(#loc15)
+    %19 = arith.mulf %18, %18 : tensor<1x128xf32, #blocked> loc(#loc16)
+    %20 = arith.addf %19, %cst : tensor<1x128xf32, #blocked> loc(#loc17)
+    %21 = arith.select %16, %20, %cst : tensor<1x128xi1, #blocked>, tensor<1x128xf32, #blocked> loc(#loc18)
+    %22 = "tt.reduce"(%21) <{axis = 1 : i32}> ({
+    ^bb0(%arg4: f32 loc(callsite(#loc1 at #loc20)), %arg5: f32 loc(callsite(#loc1 at #loc20))):
+      %28 = arith.addf %arg4, %arg5 : f32 loc(#loc32)
+      tt.reduce.return %28 : f32 loc(#loc29)
+    }) : (tensor<1x128xf32, #blocked>) -> tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> loc(#loc29)
+    %23 = ttg.convert_layout %22 : tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked}>> -> tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> loc(#loc22)
+    %24 = tt.expand_dims %23 {axis = 1 : i32} : tensor<1xf32, #ttg.slice<{dim = 1, parent = #blocked1}>> -> tensor<1x1xf32, #blocked1> loc(#loc22)
+    %25 = tt.addptr %arg1, %0 : !tt.ptr<f32>, i32 loc(#loc23)
+    %26 = tt.splat %25 : !tt.ptr<f32> -> tensor<1x1x!tt.ptr<f32>, #blocked1> loc(#loc24)
+    %27 = tt.splat %1 : i1 -> tensor<1x1xi1, #blocked1> loc(#loc24)
+    tt.store %26, %24, %27 : tensor<1x1x!tt.ptr<f32>, #blocked1> loc(#loc24)
+    tt.return loc(#loc25)
+  } loc(#loc)
+} loc(#loc)
+#loc2 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":22:28)
+#loc3 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":24:21)
+#loc4 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":25:37)
+#loc5 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":27:19)
+#loc6 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":28:19)
+#loc7 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":33:29)
+#loc8 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:45)
+#loc9 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:41)
+#loc10 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:55)
+#loc11 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:50)
+#loc12 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:34)
+#loc13 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:70)
+#loc14 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:60)
+#loc15 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":37:122)
+#loc16 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":39:22)
+#loc17 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":41:23)
+#loc18 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":42:48)
+#loc19 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":286:36)
+#loc21 = loc("/home/x/hfenv/lib/python3.12/site-packages/triton/language/standard.py":256:15)
+#loc22 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":43:28)
+#loc23 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:25)
+#loc24 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:36)
+#loc25 = loc("/home/x/.cache/vllm/torch_compile_cache/90b45bce02/rank_0_0/inductor_cache/lk/clkbfn3vntrjroh7rv6papmf73vwzfxmmisqp2i57q3diq5yp3gx.py":44:4)
+#loc26 = loc(fused[#loc9, #loc8])
+#loc27 = loc(fused[#loc11, #loc10])
+#loc28 = loc(fused[#loc13, #loc3])
+#loc29 = loc(callsite(#loc19 at #loc20))
+#loc31 = loc(callsite(#loc21 at #loc19))
+#loc32 = loc(callsite(#loc31 at #loc20))