| # Six-Transistor SRAM Bitcell Layout Task |
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| ## Objective |
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| Implement the supplied six-transistor SRAM bitcell, retaining cross-coupled storage, complementary bitlines and the shared wordline. Preserve authoritative netlist models, W/L, interface and connections; top cell is `cell_6t`. |
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| ### Optimization objective |
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| Maximize the declared quality score within the solve budget while satisfying all physical and necessary functional requirements. The first passing DRC, LVS and required electrical checks establish a feasible baseline. Continue improving the scored metrics from that baseline; a passing check or `task_success = true` does not mean that the quality objectives have been achieved. |
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| ## Inputs and Interface |
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| Ordered SPICE ports: `bl br wl vdd gnd`. Names are case-insensitive, but different names are not interchangeable. Inputs are this description, `materials/circuit.spice` and `materials/testbench.spice`. The reviewed resource package supplies models and extraction resources; reference geometry and qualification evidence are not solver inputs. |
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| ## Operating Conditions |
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| Use nominal FreePDK45 BSIM4 models at **1.0 V and 27 C**, with ground at 0 V. Every transistor has channel length 50 nm; widths and model types follow the netlist. |
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| Each bitline has a 10 fF load; ideal external switches have on resistance 10 ohm and off resistance 1e12 ohm. Write BL=0/BR=1 over 0–500 ps; after precharge, read at 1 ns and 2 ns. Write the opposite value over 4–4.5 ns, then read again at 5 ns and 6 ns. Sample differential bitline voltage 110 ps after each read starts; wordline edges are 10 ps and read pulses 300 ps. The second read checks nondestructive reading and retention after idle; see the deck for exact switching times. Power over 0–7 ns includes DUT and precharge supplies. |
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| The deck precisely defines stimuli and observation times, testing only through external ports. Validation covers these nominal conditions, excluding PVT, mismatch, array integration, substrate noise and manufacturing signoff. |
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| ## Physical Requirements |
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| Submit a nonempty GDSII no larger than 10 MiB. Enable every check in the supplied KLayout DRC deck, including grid and antenna checks, without waivers. Strict LVS checks named ports, models, W/L and physical well/contact connectivity, with library-specific implicit or global power connections disabled. The upstream deck does not implement its documented spacing rule for wells at different potentials and does not provide complete foundry signoff. |
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| The hard functional-outline limit is 100 um × 100 um. Its bounding box includes all functional geometry on drawing layers 1/0–29/0: active regions, wells, implants, threshold markers, poly, contacts, ten metal layers and nine via layers. Area is scored in um2. Keep functional geometry on these layers, excluding pin-purpose and annotation geometry. Electrical labels use poly or metal drawing layers (9/0, 11/0, 13/0, …, 29/0); nonelectrical annotation text is not extracted. |
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| Translation, equivalent hierarchy and internal instance renaming are allowed. LVS permits source/drain exchange and equivalent parallel devices; the candidate must still pass the same RC electrical evaluation. Preserve top-level port identities and explicit body connections. |
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| ## Electrical Requirements and Scoring |
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| Artifact, geometry, DRC, LVS and declared functional requirements must pass. Parasitic extraction is also mandatory: it must produce a complete, electrically consistent netlist usable by the required post-layout simulations. A completed candidate rejection scores zero; infrastructure errors do not establish candidate failure. |
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| For `layout` scoring, cap every positively weighted raw quality at 1 before aggregation; the score ranges from 0 to 100. Reaching every weighted target scores 100, and no minimum score is required for validity. |
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| Extract the candidate GDS only after file, DRC, LVS and geometry checks pass. Simulate its Magic RC netlist directly, with independent source simulation supplying the scoring baseline. Independent LVS first checks VTG/VTL device types, then uses the matching extraction configuration. Extraction includes poly/metal sheet resistance, contacts/vias, geometry-dependent coupling and ground capacitance, and device junction areas/perimeters. Wells use lumped connectivity; BSIM4 describes device and junction behavior. Interconnect RC uses estimated coefficients and native capacitance placement from the fixed community FreePDK45 Magic technology. The adapter binds VTG/VTL models, preserves annotation layers and corrects dimension-unit conversion. This is a predictive approximation without field-solver signoff accuracy. |
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| Physical checks and the declared functional bounds must pass. Each `source_*` job and its corresponding candidate extracted circuit use exactly the same testbench, model resources, parameters, loads and measurement windows. Electrical quality uses the paired pre-layout observations to score preservation of the fixed circuit's performance. Reports retain every source/candidate pair. |
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| Let x be the post-layout measurement and b its same-condition pre-layout measurement: |
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| - Ratio normalization: maximize with q = x/b and minimize with q = b/x. When a numerical scale s is declared, use (x+s)/(b+s) and its reciprocal, respectively. The scale handles zero values as a normalization floor; it is neither an allowed degradation nor an acceptance bound. |
| - Amplitude in dB: maximize with q = 10^((x-b)/20) and minimize with its reciprocal. |
| - Target normalization: q = 1/(1+abs(x-b)/s), where s is the declared physical scale. Signed or zero-valued operating points are not divided directly. |
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| Use `layout` scoring. First compute each metric's raw quality q from the worst paired condition, with raw area quality q_area = area_target / candidate_functional_area. Credit c_i = min(1, q_i) for every positively weighted metric, then compute S = 100 * product(c_i ** w_i). The weights sum to 1 and the score is bounded by 100. An improvement beyond one target cannot compensate for missing another target. Physical, extraction, or functional rejection scores zero; other missing or invalid measurements leave the score unknown, and zero-weight observations must also be valid. Reaching every positively weighted target scores 100; a feasible reference may score far below 100. Weights express quality tradeoffs, not acceptance bounds. |
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| | Metric | Definition / observation | Unit | Quality normalization | Functional range | Scale | |
| | --- | --- | --- | --- | --- | --- | |
| | `read0` | `find par('v(br)-v(bl)') at=1110p` | V | functional check | 0.3 … +∞ | — | |
| | `repeat0` | `find par('v(br)-v(bl)') at=2110p` | V | functional check | 0.3 … +∞ | — | |
| | `read1` | `find par('v(bl)-v(br)') at=5110p` | V | functional check | 0.3 … +∞ | — | |
| | `repeat1` | `find par('v(bl)-v(br)') at=6110p` | V | functional check | 0.3 … +∞ | — | |
| | `supply` | `avg par('-v(vdd)*i(Vdd)') from=0 to=7n` | W | minimize / ratio | 0 … +∞ | 1e-12 | |
| | `read_delay` | WL rising through 0.5 V to signed bitline difference reaching 0.1 V, for read edges at 1, 2, 5 and 6 ns (distinct from the 0.3 V sampled-level requirement). | s | minimize / ratio | 0 … +∞ | — | |
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| The area scoring target is **0.55 um2**. It is a continuous quality goal, not a hard limit, process minimum or a percentage of the current feasibility witness. |
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| The 0.55 um2 area target is an expert engineering estimate for a compact standalone bitcell under the declared rules and complete functional-bbox measurement. A four-NMOS shared-diffusion chain uses 50 nm gates, 65 nm contacts and 35 nm gate-to-contact clearances: 4*50 + 3*(65+2*35) + 2*(35+65+5) = 815 nm of active width. Two 55 nm well enclosures give 925 nm. The 205 nm pull-down and 90 nm pull-up widths, inter-row gate/contact access, body ties and cross-coupled routing motivate an approximately 590-600 nm total height, giving a 0.546-0.555 um2 compact envelope. This is a demanding layout budget, not a demonstrated optimum or a mandatory topology; other aspect ratios and equivalent layouts remain allowed. Array sharing of wells or body contacts is not assumed for the standalone cell. Area carries 60%, read delay 35% and supply power 5%. Electrical quality uses same-condition pre-layout anchors; nondestructive reads and both stored states remain functional checks. |
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| The area objective and electrical normalization introduce no additional functional cutoffs. Each read observation is normalized against the pre-layout observation for the same read event before taking the worst quality. |
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| The capability coefficient is **6**, independent of this task's reference-normalized score. |
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| ### Score weights |
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| | Metric | Weight | |
| | --- | ---: | |
| | `functional_area` | 0.6 | |
| | `read_delay` | 0.35 | |
| | `supply` | 0.05 | |
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| ## Tools and Submission |
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| Soft solve budget: **1 hour**. |
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| Read `/protocol/task.json` for input/output paths, constraints and the `resources` object; `/protocol/harness.json` describes the active check and submission interface. |
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| Use the reviewed FreePDK45 KLayout, Magic and ngspice resources in the `resources` field of `/protocol/task.json`. Magic RC extraction uses `/resources/support/magic-vtg/freepdk45.tech`, including model and unit adaptation. `/protocol/task.json` supplies consistent constraints, measurements and scoring; `/task` contains only declared inputs. Write `/workspace/output/final.gds`, then run `python -I /protocol/submit.py` to submit explicitly. If `process-feedback` is provided, intermediate checks use the frozen plan and backend identities; their snapshots are not final submissions. |
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| ### Solve workflow |
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| 1. Read the declared circuit and materials, `/protocol/task.json` for paths, constraints and reviewed resources, and `/protocol/harness.json` for capabilities and helper commands. Task inputs under `/task` and resources under `/resources` are read-only; construct the layout in `/workspace` with the declared tools. With layout MCP, paths and commands refer to the remote EDA workspace. Create your own implementation with real devices, interconnect and pins, using your own tool loop without delegating to other agents; reference layouts and author code are not solver inputs. |
| 2. Inspect `resources.external` before using external tools. Each command starts a fresh shell: when tool modules are declared, source `/usr/share/Modules/init/bash` and load the selected tool's modules; export its declared `tool_environment` settings in that same command. Repeat as needed and use batch or headless operation. Local manuals, command references, and release notes may be available within the declared EDA installation and PDK resource directories. Locate these resources through `/protocol/task.json` and consult the documentation for the installed tool version when diagnosing unfamiliar syntax or tool failures. |
| 3. Generate an initial candidate and submit a snapshot early. When `process-feedback` is available, check the current GDS with layout MCP `check` or `python -I /protocol/process_check.py` before the final submission. This runs the final evaluator's complete plan and returns engineering diagnostics and candidate measurements, without scores or normalized quality factors. Checks have no count limit and consume the same wall-clock budget. Inspect the physical and functional results and all scored metrics; successful tool execution alone does not establish requirement satisfaction. Read paginated diagnostics with `report` when using MCP. Local exploratory checks do not replace this complete check. |
| 4. Use the remaining time for measured improvements to the declared quality objectives. Identify the limiting scored metrics, make targeted layout changes, regenerate and check the candidate, and compare measurements with the previous candidate and the stated scoring targets and trade-offs. Preserve the best valid candidate and revert changes that worsen the overall objective. Repeat while time and useful improvements remain; passing validity checks alone is not a stopping condition. |
| 5. Stop optimization when the budget expires, all declared quality objectives are achieved, or measured trials support convergence. If stopping early, explain the changes tried, the metric comparisons and the remaining limitations. Track remaining time through session status. At soft-budget expiry, finish or cancel already-started work and submit immediately; do not start another command, check or optimization round. If an MCP execution is running, use `poll` with its `execution_id` and the returned `next_offset` as `offset` until completion, or cancel it and wait for it to stop. |
| 6. Finish or cancel outstanding work, restore your best candidate to the declared output path, and explicitly submit it before ending the session. With layout MCP `submit`, remove the `/workspace/` prefix from `output.path`; with the container interface, run `python -I /protocol/submit.py`. Wait for the receipt: only the last accepted snapshot is judged, and writing a file alone is not submission. Acceptance confirms delivery; the framework independently evaluates validity and quality after the session. |
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