Symposium on Cluster Computing and the Grid, 2007; 541–548, doi:10.1109/CCGRID.2007.85.
Yang L, Man L. On-Line and Off-Line DVS for Fixed Priority with Preemption Threshold Scheduling. Proceedings of ICESS'09, the International Conference on Embedded Software and Systems, 2009; 273–280, doi:10.1109/ICESS.2009.50.
AMD processors. http://www.amd.com.
Intel XScale technology. http://www.intel.com/design/intelxscale.
Langen P, Juurlink B. Leakage-aware multiprocessor scheduling. J. Signal Process. Syst. 2009; 57(1):73–88, doi:http://dx.doi.org/10.1007/s11265-008-0176-8.
Chen G, Malkowski K, Kandemir M, Raghavan P. Reducing power with performance constraints for parallel sparse applications. Proceedings of IPDPS 2005, the 19th IEEE International Parallel and Distributed Processing Symposium, 2005; 8 pp., doi:10.1109/IPDPS.2005.378.
Xu R, Mossé D, Melhem R. Minimizing expected energy consumption in real-time systems through dynamic voltage scaling. ACM Trans. Comput. Syst. 2007; 25(4):9, doi:http://doi.acm.org/10.1145/1314299.1314300.
Gonzalez R, Horowitz M. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits Sep 1996; 31(9):1277–1284, doi:10.1109/4.535411.
Yao F, Demers A, Shenker S. A scheduling model for reduced CPU energy. Proceedings of FOCS '95, the 36th Annual Symposium on Foundations of Computer Science, IEEE Computer Society: Washington, DC, USA, 1995; 374.
Zhang Y, Hu XS, Chen DZ. Task scheduling and voltage selection for energy minimization. Proceedings of DAC'02, the 39th annual Design Automation Conference, ACM: New York, NY, USA, 2002; 183–188, doi:http://doi.acm.org/10.1145/513918.513966.
Beigne E, Clermidy F, Durupt J, Lhermet H, Miermont S, Thonnart Y, Xuan T, Valentian A, Varreau D, Vivet P. An asynchronous power aware and adaptive NoC based circuit. Proceedings of the 2008 IEEE Symposium on VLSI Circuits, 2008; 190–191, doi:10.1109/VLSIC.2008.4586002.
Beigne E, Clermidy F, Miermont S, Thonnart Y, Valentian A, Vivet P. A Localized Power Control mixing hopping and Super Cut-Off techniques within a GALS NoC. Proceedings of ICICDT 2008, the IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008; 37–42, doi: 10.1109/ICICDT.2008.4567241.
Kawaguchi H, Zhang G, Lee S, Sakurai T. An LSI for VDD-Hopping and MPEG4 System Based on the Chip. Proceedings of ISCAS'2001, the International Symposium on Circuits and Systems, 2001.
Nocedal J, Wright SJ. Numerical Optimization. Springer, 2006.
Schrijver A. Combinatorial Optimization: Polyhedra and Efficiency, Algorithms and Combinatorics, vol. 24. Springer-Verlag, 2003.
Garey MR, Johnson DS. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman & Co.: New York, NY, USA, 1990.