Vdd-Hopping model. This model is similar to the DISCRETE one, except that switching modes during the execution of a given task is allowed: any rational speed can be simulated, by simply switching, at the appropriate time during the execution of a task, between two consecutive modes [15]. Note that $V_{DD}$ usually represents the supply voltage, hence the name VDD-HOPPING.
Incremental model. In this variant of the DISCRETE model, we introduce a value $\delta$ that corresponds the minimum permissible speed increment, induced by the minimum voltage increment that can be achieved when controlling the processor CPU. This new model aims at capturing a realistic version of the DISCRETE model, where the different modes are spread regularly instead of arbitrarily chosen.
Our main contributions are the following. For the CONTINUOUS model, we give a closed-form formula for trees and series-parallel graphs, and we cast the problem into a geometric programming problem [16] for general DAGs. For the VDD-HOPPING model, we show that the optimal solution for general DAGs can be computed in polynomial time, using a (rational) linear program. Finally, for the DISCRETE and INCREMENTAL models, we show that the problem is NP-complete. Furthermore, we provide approximation algorithms that rely on the polynomial algorithm for the VDD-HOPPING model, and we compare their solution with the optimal CONTINUOUS solution.
The paper is organized as follows. We start with a survey of related literature in Section 2. We then provide the formal description of the framework and of the energy models in Section 3, together with a simple example to illustrate the different models. The next two sections constitute the heart of the paper: in Section 4, we provide analytical formulas for continuous speeds, and the formulation into the convex optimization problem. In Section 5, we assess the complexity of the problem with all the discrete models: DISCRETE, VDD-HOPPING and INCREMENTAL, and we discuss approximation algorithms. Finally we conclude in Section 6.
2. Related work
Reducing the energy consumption of computational platforms is an important research topic, and many techniques at the process, circuit design, and micro-architectural levels have been proposed [17, 18, 19]. The dynamic voltage and frequency scaling (DVFS) technique has been extensively studied, since it may lead to efficient energy/performance trade-offs [20, 2, 13, 21, 22, 23, 11]. Current microprocessors (for instance, from AMD [24] and Intel [25]) allow the speed to be set dynamically. Indeed, by lowering supply voltage, hence processor clock frequency, it is possible to achieve important reductions in power consumption, without necessarily increasing the execution time. We first discuss different optimization problems that arise in this context. Then we review energy models.