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To simplify the notation, we write [MATH] instead of [MATH] and [MATH] instead of [MATH] Suppose [MATH] is accepted by [MATH] Write [MATH] , where [MATH] is the shortest prefix of [MATH] such that [MATH] Since [MATH] is minimal in length, for every proper prefix [MATH] of [MATH] , we have [MATH] for some [MATH] It foll... |
Conversely, suppose [MATH] . Write [MATH] with [MATH] minimal. Since [MATH] , we have [MATH] Furthermore, [MATH] is the shortest prefix of [MATH] such that [MATH] , since if there was a shorter prefix then [MATH] would not be minimal. This means that [MATH] by the definition of [MATH] So [MATH] and hence [MATH] is acce... |
Fix [MATH] with state complexity [MATH] , and let [MATH] and [MATH] be the DFAs for [MATH] and [MATH] , respectively, as described in the proof of Proposition 22 . Fix [MATH] with state complexity at most |
[MATH] , and let [MATH] be an [MATH] -state DFA for [MATH] with state set [MATH] and final state set [MATH] . The direct product DFA [MATH] with final state set [MATH] recognizes [MATH] . Since [MATH] has [MATH] states, this gives an upper bound of [MATH] on the state complexity of [MATH] . We claim that this upper bou... |
Theorem 23 Suppose [MATH] and [MATH] There exists a non-empty word [MATH] and a language [MATH] , with [MATH] and [MATH] , such that [MATH] |
Proof 20 Let [MATH] and let [MATH] Let [MATH] be the DFA for [MATH] Let [MATH] be the language accepted by the DFA [MATH] with state set [MATH] , alphabet [MATH] , initial state [MATH] , final state set [MATH] , and transformations [MATH] and [MATH] |
We show that [MATH] has [MATH] reachable and pairwise distinguishable states. For reachability, for [MATH] and [MATH] , we can reach [MATH] from the initial state [MATH] by the word [MATH] For distinguishability, suppose we have states [MATH] and [MATH] in the same column [MATH] , with [MATH] By [MATH] we reach [MATH] ... |
7.4 Matching a Single Subsequence Proposition 24 If the state complexity of [MATH] is [MATH] , then the state complexity of [MATH] is [MATH] |
Proof 21 Define a DFA [MATH] where [MATH] , and [MATH] for [MATH] . Note that [MATH] is minimal: state [MATH] is reached by word [MATH] and states [MATH] with [MATH] are distinguished by [MATH] . We claim that [MATH] recognizes [MATH] |
Write [MATH] rather than [MATH] to simplify the notation. Suppose [MATH] . Then we can write [MATH] , where [MATH] . We claim that [MATH] for some [MATH] . We proceed by induction on [MATH] . The base case [MATH] is trivial. |
Now, suppose that [MATH] and [MATH] for some [MATH] Then [MATH] We consider two cases: 1. If [MATH] , we have [MATH] for some [MATH] with [MATH] , as required. |
2. If [MATH] , we have [MATH] for some [MATH] with [MATH] , as required. This completes the inductive proof. It follows then that |
[MATH] , and so [MATH] is accepted by [MATH] Conversely, if [MATH] is accepted by [MATH] , then it is clear from the definition of the transition function that the letters [MATH] must occur within [MATH] in order, and so [MATH] \qed |
Fix [MATH] with state complexity [MATH] , and let [MATH] be the DFA for [MATH] described in the proof of Proposition 24 . Fix [MATH] with state complexity at most |
Theorem 25 Suppose [MATH] and [MATH] There exists a non-empty word [MATH] and a language [MATH] , with [MATH] and [MATH] , such that [MATH] |
Proof 22 Let [MATH] and let [MATH] Let [MATH] be the DFA for [MATH] Let [MATH] be the language accepted by the DFA [MATH] with state set [MATH] , alphabet [MATH] , initial state [MATH] , final state set [MATH] , and transformations [MATH] and [MATH] |
We show that [MATH] has [MATH] reachable and pairwise distinguishable states. For reachability, for [MATH] and [MATH] , we can reach [MATH] from the initial state [MATH] by the word [MATH] For distinguishability, suppose we have states [MATH] and [MATH] in the same column [MATH] , with [MATH] By [MATH] we reach [MATH] ... |
Conclusions We investigated the state complexity of four new combined operations on regular languages, inspired by pattern matching problems, in both the general case and the case where the pattern set is a single word. The operations we considered were of the form “the intersection of [MATH] with the right (left, two-... |
# Source: arxiv 1806.04671 # Title: Real-time data compression for data acquisition systems applied to the ITER Radial Neutron Camera # Sections: all # Downloaded: 2026-03-03T05:16:07.161463+00:00 |
Real-time data compression for data acquisition systems applied to the ITER Radial Neutron Camera Abstract To achieve the aim of the ITER Radial Neutron Camera Diagnostic, the data acquisition prototype must be compliant with a sustained 2 MHz peak event for each channel with 128 samples of 16 bits per event. The data ... |
The acquired data in the event-based data-path is streamed to the host through the PCIe x8 Direct Memory Access (DMA) with a maximum data throughput per channel [MATH] 0.5 GB/s of raw data (event base), [MATH] 1 GB/s per digitizer and up to 1.6 GB/s in continuous mode. |
The prototype architecture comprises an host PC with two KC705 modules and four channels, producing up to 2 GB/s in event mode and up to 3.2 GB/s in continuous mode. To reduce the produced data throughput from host to ITER archiving system, the real-time data compression was evaluated using the LZ4 lossless compression... |
This paper presents the architecture, implementation and test of the parallel real-time data compression system running in multiple isolated cores. The average space-saving and the performance results for long term acquisitions up to 30 minutes, using different data block size and different number of CPUs, is also pres... |
Index Terms: Compression, Data Acquisition, Diagnostic, ITER, Real-time. Introduction This Radial Neutron Camera (RNC) is a key ITER diagnostic aiming at the real-time measurement of the neutron emissivity to characterize the neutron emission that will be produced by the ITER tokamak |
. To achieve the aim of the RNC diagnostic, the data acquisition prototype must be compliant with a sustained 2 MHz peak event for each channel with 128 samples of 16 bits. The data is acquired and processed using IPFN FPGA Mezzanine Cards (FMC-AD2-1600) with 2 digitizer channels of 12-bit resolution sampling up to 1.6... |
The prototype architecture comprises one host PC with two installed KC705 modules and four channels, producing up to 2 GB/s in event mode and up to 3.2 GB/s in continuous mode |
The LZ4 is a lossless compression algorithm, providing compression speed at 400 MB/s per core, scalable with multi-core CPUs. This algorithm appears as the fastest compression algorithm with a relevant compression ratio comparing to other dictionary encoding and entropy encoding algorithms |
During the RNC diagnostic prototype phase, the LZ4 was chosen to evaluate the feasibility of the real-time data compression implementation in the host PC to reduce the produced data throughput to ITER archiving system |
LZ4 is also suitable for implementation in FPGAs or in the Graphics Processor Units (GPUs) such as other lossless algorithms , which can be a valuable feature for future developments. |
This paper presents the implemented solution and the achieved results, which contribute to the RNC diagnostic specification. A brief overview of the system and software architecture is provided in Section II . The preliminary results that contributes to the design of the implemented architecture are presented in Sectio... |
II System Architecture Fig. depicts the overall system architecture , highlighting the context compression software path. The system was designed to support two IPFN FPGA Mezzanine Cards installed in the PCIe evaluation boards from Xilinx (KC705) and connected to the host through the PCIe x8 slots. The data production ... |
, providing higher data throughput to stress tests. The host computer hardware specification includes: Motherboard: ASUS Rampage V Extreme with 4xPCIe 3.0/2.0 x16 slots |
CPU: Intel Core TM i7-5930K@3.50 GHz supporting Intel Hyper-Threading Technology (6 cores, 12 threads) 64 GB of RAM and 256 GB SSD. |
The Scientific Linux 7 is running as Operating System with kernel 3.10-rt and LZ4 version 1.7.5. Interfacing between the hardware and high-level applications is installed the Linux device driver, supporting data transfers up to 1.6 GB/s per board. The Control and Data Acquisition (CDAQ) software includes a shared memor... |
At the application level, software modules were developed for: Real-time data compression to reduce the data size. Data pulse processing for energy and particle discrimination. |
Real-time raw archiving for test purposes with low data rate acquisitions. In the presented tests, the compression application was directly connected to the device driver for evaluating its performance limit. |
The introduction of the shared memory layer should not affect performance since the approach to read the data from the shared memory must be, in the worst case, as fast as the direct reads from the device drive. |
II-A Software Architecture Fig. presents the compression application software architecture and its interface to the device driver. The compression application is based on the task farm algorithm approach with a master thread that launches a poll of threads with a configured number of worker threads. |
The device driver implements a kernel thread with an internal circular buffer to store in real-time the data transferred from the hardware, until it is read from the consumer applications. There are two implemented pointers for the circular buffer (read pointer and write pointer) to control the read operations from the... |
The master thread reads the available data from device driver in real-time, packs it into data blocks with configurable data size and distributes it across the configured number of worker threads. Each data block is tagged with an id to be used by the worker threads to store the compressed data in the correct position ... |
The worker threads implement the compression algorithm and are responsible for the parallel compression in real-time. In the present tests, the worker threads store the compressed data in a memory buffer but can deliver it through the network directly to the data archiver. |
The device driver, master thread and worker threads run in isolated cores (detached from the kernel scheduling, preventing its usage by the operating system), taking advantage of the CPU affinity feature, which is the ability to direct a specific task, or process, to use a specified core. |
III Preliminary Tests To identify the achieved compression speed, compression ratio and space-saving with different configurations of the LZ4 algorithm several tests are done using the LZ4 default and LZ4 HC. In the LZ4 default an acceleration option can be configured to get a better compression speed compromising the ... |
The input data for these tests was collected with real radation sources in Frascatti Neutron Generator (FNG) during the tests in January 2018 and from a waveform generator simulating a gamma ray type signal as input to compare different signal types. The acquisition was configured with a pulse width of 128 samples, pro... |
Table presents the LZ4 default compression tests comparing the different sources and acceleration factors. The results suggest that the accelerations with even number (2, 4, 6, 8, 10 and 12) have a better relation between compress speed and compress ratio. However, the acceleration with factor 1 has the better compress... |
Table II presents the LZ4 High Compression (HC) tests comparing the different sources and compression levels. Using the 256 MB/s of data throughput with up to 8 CPU cores running in parallel, only the first 3 compression levels can be used without missing data. The results present a better space saving than in the LZ4 ... |
Table III presents the theoretically number of needed cores to compress 1 GB/s of data throughput in real-time with different LZ4 default acceleration factors and different LZ4 HC compression levels. |
Using the LZ4 default algorithm there is no difference in the needed cores between the acceleration levels 2 and 5, but the space saving reduces [MATH] 5%. Using the compression level 1, the space saving is increased [MATH] 2% but one more core is need. |
The LZ4 high compression variant usage is not possible because it needs at minimum 13 available cores (10 more than LZ4 default) to improve the space saving in [MATH] 6%. |
The tests also confirm compressing speed and ratio similarities between the acquired signals in the real environment and signals from the waveform generator. |
IV Tests and Results The tests were based in a pulse type signal from a waveform generator simulating a gamma-ray distribution. The acquisition tests have different pulse width configurations to produce distinct acquisition data rates up to 1.5 GB/s. Each acquisition test has 60 minutes, in agreement with the ITER long... |
To compress data with maximum compression ratio available, the LZ4 default algorithm with acceleration factor 1 was selected. IV-A |
Number of Cores Table IV presents the relation between the data loss and number of cores for different data acquisition rates. Based on the results, the minimum number of needed cores per data acquisition rate with no data loss are: |
1 core to compress until 256 MB/s 2 cores for 512 MB/s 3 cores for 768 MB/s 4 cores for 1 GB/s 6 cores for 1.5 GB/s. These results are inside the range of the preliminary results for acceleration level 1, which have a compression speed [MATH] 300 MB/s per core. |
IV-B CPU Usage The used CPU supports Intel Hyper-Threading Technology, providing 12 logical cores for the operating system, based on their 6 physical cores. This architecture can result in slightly differences to tests with 12 dedicated cores that can produce small improvements. |
Table presents average core usage of the dedicated cores to the master and worker threads for each acquisition data rate. IV-C Compression Statistics |
Table VI summarizes the compression results of the tests with different pulse widths. IV-D Block Sizes Table VII presents the test of different data block sizes with same input signal and configurations (1 channel with pulse width 128 and acquisition data rate of 512 MB/s). |
The results suggest that data block size did not improve the space saving, however the standard deviation of the compression speed during the pulse is reduced. |
IV-E CPU and Memory Usage Fig. presents the CPU and memory usage during 3 acquisitions from one board during 10 seconds with 1024 MB/s of acquisition data rate. There are two dedicated cores for the operating system, one isolated core for the device driver thread, one isolated core for the compression master thread and... |
Fig. present the CPU and memory usage during 3 acquisitions from two boards simultaneously during 10 seconds with 512 MB/s of data acquisition rate per board. There are two dedicated cores for the operating system and each board uses five isolated cores (one for the device driver thread, one for the compression master ... |
IV-F Relation Between Space Saving and Pulse Width Fig. depicts the relation between space saving and pulse width for signals using one and two ADCs. |
Independently of the ADCs number, a relation between space saving and pulse width can be identified. Using a greater pulse width, the relative space saving increases which can be related with the type of acquired data. |
Conclusions and Future Work This contribution evaluates the feasibility of data compression implementation in the host PC and contributes to the RNC diagnostic specification. |
The presented architecture is scalable and adjustable. The number of worker threads can be configured to comply with different algorithms and data throughput. |
The stress tests show a stable solution during 60-minute acquisitions with data acquisition rates up to 1.5 GB/s, using a maximum of 6 worker threads in parallel. |
The system was also tested in Fedora Linux 27, kernel 4.16, the community version of Red Hat Linux that supports ITER CODAC system. The results were similar, which validates the developed architecture for future kernel version of Red Hat Linux. |
Based on the presented tests, to compress 1 GB/s from one board in real-time, a minimum of 5 cores are needed (1 master and 4 worker threads). Using two boards simultaneously to acquire 1GB/s in each, the system will need 14 cores (2 cores for operating system, 2 cores for the device driver, 2 cores for master thread a... |
The preliminary tests with two boards simultaneously showed a possible performance decreasing. Acquiring 512 MB/s the system needs 3 cores, instead of 2 with a single board. This can be related with the usage of Intel Hyper-Threading Technology instead of dedicated cores but intensive tests with two hardware modules ac... |
With the tested signals, the maximum achieved space saving with the LZ4 algorithm was between 25% and 40%. Changes on signal configuration can influence the compress ratio. |
In the future, the data compression can be implemented in the GPU or FPGA to compare the results with the host PC. There are some possible advantages to be tested but for the FPGA implementation, a new data path to the host is needed, once the processing algorithms need decompressed data in real-time. This increases th... |
# Source: arxiv 1806.04703 # Title: Electronic schematic for bio-plausible dopamine neuromodulation of eSTDP and iSTDP # Sections: all # Downloaded: 2026-03-03T02:32:36.849608+00:00 |
Electronic schematic for bio-plausible dopamine neuromodulation of eSTDP and iSTDP Abstract In this technical report we present novel results of the dopamine bio-plausible neuromodulation excitatory (eSTDP) and inhibitory (iSTDP) learning. We present the principal schematic for the neuromodulation of D1 and D2 receptor... |
keywords: neuromodulation, dopamine, neuromorphic computing, affective computing, simulation The experimental set-up In our previous technical report we presented the electronic schematic to generate complex learning impulses for memristive devices to implement iSTDP and eSTDP learning functions (Talanov et al.,, 2017 ... |
1.1 Block diagram We have decided to use mixture of two functions that represents extreme positions in the dopamine modulation STDP “Sombrero” and Hebbian indicated as [MATH] and [MATH] triangles in Fig. . Input signals of “Sombrero” and Hebbian learning functions are balanced via dopamine level represented as [MATH] g... |
1.2 Wiring schematic The wiring schematic of the dopamine modulation via receptor D1 is depicted in Fig. . The op-amp [MATH] plays the role of inverter for the “Sombrero” input signals to implement the extreme state of the learning function for D1 receptor the inverted “Sombrero” (see Fig. ). Two op-amps [MATH] and [MA... |
[EQUATION] The value of the [MATH] is set via digital potentiometer opposed to [MATH] [EQUATION] When [MATH] , according to eq. [MATH] , which makes gain almost equal zero. At the same time, from eq. |
[MATH] , combined with [MATH] makes gain equals to one. If [MATH] gains are opposite. The outbound signal of both amplifiers [MATH] and [MATH] is processed by the weighted adder implemented via [MATH] . The “Sombrero” amplitude is twice lower than Hebbian, to match global amplitude change in process of dopamine modulat... |
The modulation schematic for D2 receptor is done in similar way except for the inverter of the “Sombrero” input signals that in case of D2 receptor is not used. The neuromodulatory schematic is represented in Fig. |
1.3 Results For the simulatory validation we have used LTSpice software framework. Inbound signals are presented in Fig. where green graph is the “Sombrero” signals and blue is the Hebbian signals for both the D1 and D2 dopamine receptors. |
The results of D1 modulation are indicated in Fig. where the proportion of the influence of the inbound learning function over outbound signal is defined by the level of the dopamine or set up of resistors [MATH] and [MATH] . The level of the dopamine is represented as the red graph. Learning impulses that indicate the... |
The initial state of both graphs is low level of the dopamine and the learning function is inverted “Sombrero” for D1 and “Sombrero” for D2 respectively. The learning function for high level of the dopamine is Hebbian or [MATH] The gradual mixture of initial learning functions with final Hebbian is represented during s... |
# Source: arxiv 1806.04712 # Title: Boundedness of the number of nodal domains for eigenfunctions of generic Kaluza-Klein $3$-folds # Sections: all # Downloaded: 2026-03-03T02:26:32.466203+00:00 |
\alttitle Limite du nombre de domaines nodales des fonctions propres de variétées Kaluza-Klein generiques en dimension 3 \altkeywords |
fonction propre du Laplacien, fibré principale, metrique de Kaluza-Klein, domaine nodale Boundedness of the number of nodal domains for eigenfunctions of generic Kaluza-Klein 3-folds |
Abstract. This article concerns the number of nodal domains of eigenfunctions of the Laplacian on special Riemannian [MATH] -manifolds, namely nontrivial principal [MATH] bundles |
[MATH] over Riemann surfaces equipped with certain [MATH] invariant metrics, the Kaluza-Klein metrics. We prove for generic Kaluza-Klein metrics that any Laplacian eigenfunction has exactly two nodal domains unless it is invariant under the [MATH] action. |
We also construct an explicit orthonormal eigenbasis on the flat [MATH] -torus [MATH] for which every non-constant eigenfunction has two nodal domains. |
Key words and phrases: Eigenfunction of the Laplacian, Principal bundle, Kaluza-Klein metric, Nodal domain 1991 Mathematics Subject Classification: 58J50 |
Research partially supported by NSF grant DMS-1541126. The first author is partially supported by Sloan Research Fellowship and by NSF grant DMS-1900993. The first author thanks Eviatar Procaccia for an enlightening discussion. |
{altabstract} Cet article concerne le nombre de domaines nodales des fonctions propres du Laplacien sur des variétées Riemanniennes Kaluza-Klein en dimension trois, à savoir des variétées qui sont fibrés [MATH] -principales [MATH] sur des surfaces de Riemann équipées avec une métrique [MATH] -invariante de type Kaluza-... |
On construit aussi une base orthonormale de fonctions propres explicite du tore plat [MATH] pour que chaque fonction propre non-constant possède exactement deux domaines nodales. |
1. Introduction This article is concerned with the number of nodal domains of eigenfunctions of the Laplacian on certain [MATH] -dimensional compact smooth Riemannian manifolds [MATH] The manifolds are [MATH] bundles [MATH] over a Riemannian surface [MATH] , and [MATH] is assumed to be a Kaluza-Klein metric adapted to ... |
is a special kind of Riemannian submersion with totally geodesic fibers in the sense of (see Definition 1.1 and Definition 6.1 ). The [MATH] action commutes with the the Laplacian [MATH] of the Kaluza-Klein metric [MATH] and one may separate variables to obtain an orthonormal basis of joint eigenfunctions [MATH] |
[EQUATION] Our focus is on the nodal sets of the real or imaginary parts of [EQUATION] and on particularly on the number of their nodal domains. Since [MATH] is a real operator, the real and imaginary parts ( 1.2 ) satisfied the modified eigenvalue system, |
[EQUATION] Our main result (Theorem 1.3 ) is that when [MATH] is a regular value of [MATH] for all [MATH] , then for [MATH] , the nodal sets of [MATH] resp. [MATH] , are connected and there exist exactly [MATH] corresponding nodal domains. The case [MATH] is special because |
[MATH] is then real valued and is pullback from the base [MATH] in this case, the number of connected components of the nodal set (and the number of nodal domains) is the same as for the corresponding eigenfunction on [MATH] Theorem 1.3 shows that it is a generic property of Kaluza-Klein metrics on [MATH] bundles over ... |
1.1. Adapted Kaluza-Klein metrics We now define Kaluza-Klein metrics on a three-dimensional manifold [MATH] which is an [MATH] bundle over a (usually) compact Riemannian surface [MATH] . In our main results, [MATH] is the unit co-circle bundle of an ample complex holomorphic line bundle [MATH] Thus, [MATH] or [MATH] (t... |
A Kaluza-Klein metric is determined by the following data: (i) A surface [MATH] equipped with a Riemannian metric [MATH] and a complex structure [MATH] |
(ii) A nontrivial complex holomorphic line bundle [MATH] over a surface, (iii) A Hermitian metric [MATH] on [MATH] (iv) A complex structure [MATH] on [MATH] |
(v) An [MATH] -compatible connection [MATH] on [MATH] In this article, we fix [MATH] [MATH] and [MATH] and only vary the data [MATH] . The unitary frame bundle for the Hermitian metric [MATH] is defined by |
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