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module GatedLatch (
input wire enable, // Enable signal to control the latch
input wire data_in, // Input data to be stored in the latch
input wire clock, // Clock signal
output reg data_out // Output data from the latch
);
always @(posedge clock) begin
if (enable... | |
module signExt(IMM, sextIMM);
input [5:0] IMM;
output [7:0] sextIMM;
assign sextIMM[5:0] = IMM;
assign sextIMM[7:6] = IMM[5] ? 2'b11 : 2'b00;
endmodule | |
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT... | |
/* =====================================================================
* DoCE Transport Layer Wrapper
*
* Author: Ran Zhao (zhaoran@ict.ac.cn)
* Date: 03/02/2017
* Version: v0.0.1
*=======================================================================
*/
`timescale 1ns / 1ps
module mac_id_table
(
... | |
module seg7 (clk_1k,rst_n,data_in,sel,seg);
input clk_1k; // Clock
input rst_n; // Asynchronous reset active low
input [23:0] data_in;
// reg [23:0] data_in = 24'b0000_0001_0010_0011_0100_0101;
//parameter [23:0] data_in = 24'b0000_0001_0010_0011_0100_0101;
output reg [7:0] seg;
output reg [2:0] sel... | |
`timescale 1ns / 1ps
module Mux2(input wire a,input wire b,input wire sel,output wire out);
wire temp[1:0];
and( temp[1] , a , sel );
and( temp[0] , b , ~sel );
or( out , temp[1] , temp[0] );
endmodule
module Mux4(input wire [3:0] a,input wire [1:0] sel,output wire out);
wire temp[1:0];
Mux2 m1 (a[3]... | |
module sdram_write(
// system signals
input sclk ,
input s_rst_n ,
// Communicate with TOP
input wr_en ,
output wire wr_req ,
... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:46:06 06/12/2019
// Design Name:
// Module Name: Timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependenc... | |
module iiitb_pwm_gen
(
clk, // 100MHz clock input
increase_duty, // input to increase 10% duty cycle
decrease_duty, // input to decrease 10% duty cycle
reset,
PWM_OUT // 10MHz PWM output signal
);
input clk,reset;
input increase_duty;
input decrease_duty;
output PWM_OUT;
wire slow_clk_... | |
// ---------------------
// Guia 05 - Exercicio 02
// Nome: Bruno Csar Lopes Silva
// Matricula: 415985
// ---------------------
//--- Module Meia Diferena---
module meiadiferenca (s, s1, p, q);
output s, s1;
input p, q;
xor XOR1(s, p, q);
not NOT1(s2, p);
and AND1(s1, s2, q);
endmodule // meiadiferen... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/11/2023 06:16:24 PM
// Design Name:
// Module Name: sp_sram
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencie... | |
`define EXPONENT 5
`define MANTISSA 10
`define ACTUAL_MANTISSA 11
`define EXPONENT_LSB 10
`define EXPONENT_MSB 14
`define MANTISSA_LSB 0
`define MANTISSA_MSB 9
`define MANTISSA_MUL_SPLIT_LSB 3
`define MANTISSA_MUL_SPLIT_MSB 9
`define SIGN 1
`define SIGN_LOC 15
`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA)
`def... | |
module control(opCode, RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUsrc, RegWrite);
input [5:0] opCode;
output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, RegWrite, ALUsrc;
assign RegDst = (opCode == 6'h0);
assign Jump = (opCode == 6'h2);
assign Branch = (opCode == 6'h4);
assign Me... | |
module figure2_42(x1, x2, s, f);
input x1, x2, s;
output f;
reg f;
always @(x1 or x2 or s)
if (s==0)
f = x1;
else
f = x2;
endmodule | |
/* ----------------------------------------------------------------------------
Projeto: modulo conversor Float 32 - 16
UFABC - universidade Federal do ABC
Verso: 1.0 Data: 02.10.2017
Prog: Carolina Zambelli
Descrio: converte um fp single precision (32bits) para um half precision
(16... | |
module hardware_counter (
input clk, resetn,
output reg [31:0] counter
);
always @(posedge clk or negedge resetn) begin
if(resetn == 0) begin
counter <= 32'd0;
end else begin
counter <= counter + 1;
end
end
endmodule
| |
module det_seq(clk, rst, d, q, num);
input clk, rst;
input d;
output reg q;
output reg [2:0] num;
reg [2:0] cs, ns;
parameter one = 3'd0, two = 3'd1, three = 3'd2;
parameter four = 3'd3, five = 3'd4, six = 3'd5, correct = 3'd6;
// reset
always @(posedge clk or posedge rst)
begin
if(rst)
cs... | |
//------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------
module dpincbar(CIN,CINBAR,IN0,COUT,COUTBAR,Y);
parameter BIT = 0;
parameter COLINST = "0";
parameter GROUP = "dpath1";
paramete... | |
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter y0=0,y1=1,y2=2,y3=3,y4=4;
reg [2:0] state, next_state;
always @ (posedge clk) begin
if(reset)
state<=y0;
else
state<=next_state;
end
... | |
`timescale 1ns / 1ps
module decoder(ANODES, X, Y, Z, A, B, C, out);
input [7:0] ANODES;
input [3:0] X;
input [3:0] Y;
input [3:0] Z;
input [3:0] A;
input [3:0] B;
input [3:0] C;
output reg [3:0] out;
always@(*)
begin
out = (ANODES == 8'b111111... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// List of Array Registers Logics used in most of other hardware blocks
//////////////////////////////////////////////////////////////////////////////////
module latch_32bit(
input wire clk, active,
i... | |
//Memeory
module mem(
//Output(s)
ReadData,
//Input(s)
Addr,
WriteData,
MemWrite,
MemRead
);
input wire MemWrite, MemRead;
input wire[15:0] Addr, WriteData;
output reg [15:0] ReadData;
endmodule | |
//File12 name : smc_wr_enable_lite12.v
//Title12 :
//Created12 : 1999
//Description12 :
//Notes12 :
//----------------------------------------------------------------------
// Copyright12 1999-2010 Cadence12 Design12 Systems12, Inc12.
// All Rights12 Reserved12 Worldwide12
//
// Lice... | |
// megafunction wizard: %MAX II oscillator%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altufm_osc
// ============================================================
// File Name: internal_osc.v
// Megafunction Name(s):
// altufm_osc
//
// Simulation Library Files(s):
// maxii
// =========... | |
// Copyright 2020 Matt Venn
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed... | |
module if_else_logicalOR (
input condition1,
input condition2,
input condition3,
output reg result
);
always @(*) begin
if (condition1 || condition2 || condition3) begin
// execute behavior if any condition is met
result <= 1'b1;
end
else begin
// execut... | |
module BTB #(parameter W_PC = 8, W_BTA = 32)
(
input clk,
input reset,
input [W_PC-1:0] pc, // LSB 8 bits
input [31:0] aluBranchAddress,
input [31:0] pcOfAluBranchAddress,
input [0:0] branchTakenE,
input [0:0] branchPredictedE,
output reg [W_BTA-1:0] BTA, // MSB 32 bits
output reg hit,
... | |
module shifter_27 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] c
);
always @* begin
case (alufn[0+5-:6])
6'h20: begin
c = a << b[0+2-:3];
end
6'h21: begin
c = a >> b[0+2-:3];
end
6'h23: begin
... | |
module sbentsrc #(
parameter RNG_WIDTH = 4,
parameter RESET = 1
)(
input wire i_clk,
input wire i_reset,
input wire i_en,
output reg [RNG_WIDTH-1:0] o_rnd
) /* synthesis syn_preserve = 1 */ ;
wire ff_reset = RESET & i_reset;
function [3:0] sbox_f_hdminmax;
//design criterias:
//- invertible
... | |
`default_nettype wire
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated ... | |
module thermometer_to_bcd(bcd, thermometer);
output [7:0] bcd;
input [15:0] thermometer;
assign bcd = (thermometer == 16'b0) ? 0 :
(thermometer == 16'b1) ? 1 :
(thermometer == 16'b11) ? 2 :
(thermometer == 16'b111) ? 3 :
(thermometer == 16'b1111) ? 4 :
... | |
module stack
(
input wire CLK,
input wire RST,
input wire PUSH_STB,
input wire [7:0] PUSH_DAT,
output reg PUSH_ACK,
output reg POP_STB,
output wire [7:0] POP_DAT,
input wire PO... | |
module Adder(A, B, out);
input [7:0] A, B;
output [7:0] out;
assign out = A + B;
endmodule
| |
`timescale 1ns / 1ps
module rom_mem #(
parameter CELL00 = 16'b0000_0000_0000_0000,
parameter CELL01 = 16'b0000_0000_0000_0000,
parameter CELL02 = 16'b0000_0000_0000_0000,
parameter CELL03 = 16'b0000_0000_0000_0000,
parameter CELL04 = 16'b0000_0000_0000_0000,
parameter CELL05 = 16'b000... | |
//-----------------------
//TP03 - 45142
//-----------------------
module multiplexador(output s, input p, input q, input r);
wire temp1, temp2, temp3;
not(temp3, r);
and(temp1, p, temp3);
and(temp2, q, r);
or ( s,temp1, temp2);
endmodule
module exemplo0033(output s, output s1, input p, input q, i... | |
module timing_control (
input wire clk,
input wire rst,
// Timing control block inputs and outputs
);
// Timing control block implementation here
endmodule | |
module left_shift(
input [31:0] data_in,
input [31:0] shift_amount,
output [31:0] data_out
);
assign data_out = data_in << shift_amount[4:0]; //max shift amount is 5 bits for 32 bit values
endmodule | |
module rsc(clk, in, x_out, z_out, rst_N, mode, mode_out, valid_out);
input clk, in, rst_N, mode;
output x_out, z_out, mode_out, valid_out;
wire clk, in, rst_N, mode; // 1-bit wide
reg x_out, z_out, valid_out, mode_out; // 1-bit wide
reg IN, d1, d2, d3;
reg n1, n2, n... | |
module etapa2_flops (
input [7:0] data_in0,
input valid_in0,
output reg [7:0] data_out0,
output reg valid_out0,
input clk_2f,
input reset
... | |
`timescale 1ns / 1ps
// fpga4student.com
// FPGA projects, VHDL projects, Verilog projects
// Verilog code for RISC Processor
// Verilog code for Control Unit
module Control_Unit(
input[3:0] opcode,
output reg[1:0] alu_op,
output reg beq,mem_read,mem_write,reg_dst,mem_to_reg,reg_write,load... | |
//Modulo Decodificador do simbolo de adubacao/limpeza
module decode_simb(Limp, M, SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_P);
input Limp, M; // Entradas para o decodificador
output SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_P;
// Entradas negadas
wire notL, notM, wire1, wire2, wire3, w... | |
`timescale 1ns / 1ps
`ifndef LIB_STYCZYNSKI_MIN_MAX_V
`define LIB_STYCZYNSKI_MIN_MAX_V
/*
* Piotr Styczyski @styczynski
* Verilog Components Library
*
* Min-max arithmetic module
*
*
* MIT License
*/
module MinMax
#(
parameter INPUT_BIT_WIDTH = 8
)
(
input Clk,
input [INPUT_BIT_WID... | |
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merg... | |
module spi_master (
input wire clk,
input wire rst,
input wire enable,
input wire data_in,
output reg data_out,
output reg ready
);
// State machine states
parameter IDLE_STATE = 2'b00;
parameter TRANSMIT_STATE = 2'b01;
parameter RECEIVE_STATE = 2'b10;
// Data registers
reg [7:0... | |
module VerilogAdder(
input wire [31:0]a,
input wire [31:0]b,
input wire Cin,
output wire posOverflow,
output wire negOverflow,
output wire [31:0]S,
output wire Cout
);
assign {Cout,S} = a + b + Cin;
assign negOverflow = (a[31] == b[31]) & (a[31] == 1) & (S[31] == 0);
assign posOverflow = (a[31] ... | |
module ADC
(
input wire clk_in,
input wire [7:0]data_in,
output wire read,
output reg [7:0]data_ch1,data_ch2,data_ch3,
output [1:0]in
);
reg [3:0]state;
always @ (posedge clk_in)
begin
state <= state + 1'b1;
end
assign read = (state[1]^state[0]) ? 1'b0 : 1'b1;
assign in[1] = state[3];
assi... | |
/*
Copyright (c) 2019-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish,... | |
module d_ff_sync_reset_set (
input wire clk,
input wire reset,
input wire set,
input wire D,
output reg Q
);
always @(posedge clk) begin
if (reset) begin
Q <= 1'b0;
end else if (set) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule | |
/*######################################################################
//# G0B1T: HDL EXAMPLES. 2018.
//######################################################################
//# Copyright (C) 2018. F.E.Segura-Quijano (FES) fsegura@uniandes.edu.co
//#
//# This program is free software: you can redistribute it a... | |
// Stochastic to Binary converter
module StochToBin (
input clk,
input reset,
input bit_stream,
output [7:0] bin_number,
output done
);
localparam BITSTR_LENGTH = 256; // 8-bits, max length of LFSR loop
reg [7:0] ones_count = 0;
reg [7:0] clk_count = 0;
// Acc... | |
`timescale 1ps / 1ps
/*****************************************************************************
Verilog RTL Description
Configured at: 19:27:26 KST (+0900), Tuesday 19 January 2021
Configured on: design1
Configured by: hanji ()
Created by: Stratus DpOpt 2019.1.01
************... | |
module pid_control(Clk,Rst_n,CurrentAngle,CurrentGyro,ResultOut_l,ResultOut_r);
input Clk,Rst_n;
input signed[12:0]CurrentAngle,CurrentGyro;
output [15:0]ResultOut_l,ResultOut_r;
//reg [8:0]setAngle;
reg signed[12:0]Angle_1,Angle_2,Angle_3,Angle_4,Angle_5;
reg signed[13:0]Angle_Tmp;
reg signed[12:0]Gyro_1,Gyro... | |
module BarrelShifter(
input wire [7:0] input_data,
input wire [1:0] shift_amount,
input wire [3:0] shift_type,
output reg [7:0] output_data
);
always @(*)
begin
case(shift_type)
2'b00: // Logical Shift Left
output_data = input_data << shift_amount;
2'b01: // ... | |
module ConvertBinaryToMantissa (
en,
isFloat,
isExponentOdd,
in,
mantissa,
isDone
);
parameter DOUBLE_PRECISION_ODD = 11'd52,
SINGLE_PRECISION_ODD = 8'd23,
DOUBLE_PRECISION_EVEN = 11'd53,
SINGLE_PRECISION_EV... | |
module HA_Dataflow(a,b,sum,cout);
input a,b;
output sum,cout;
assign #5 sum = a^b;
assign #5 cout = a & b;
endmodule | |
// This program was cloned from: https://github.com/chipsalliance/aib-phy-hardware
// License: Apache License 2.0
// SPDX-License-Identifier: Apache-2.0
// Copyright (C) 2019 Intel Corporation.
module io_min_interp_mux (
input [3:0] phy_clk_phs, // half of 8 phase 1.6GHz clock
input svcc, ... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/06/2023 08:39:44 PM
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
... | |
`timescale 1ps / 1ps
/*****************************************************************************
Verilog RTL Description
Configured at: 16:16:05 CST (+0800), Tuesday 04 May 2021
Configured on: ws32
Configured by: m109061634 (m109061634)
Created by: Stratus DpOpt 2019.1.01
****... | |
module greyscale(
input [7:0] in_R,
input [7:0] in_G,
input [7:0] in_B,
output [7:0] grey
);
// 16 bit due to multiplication overflow
wire [15:0] intermediate;
// luminance formula (NTSC formula): greyscale = 0.299*R + 0.587*G + 0.114*B)
// R: 77/256 = 0.3
// G: 150/256 = 0.5859375
// B... | |
module uart_out (
input clk,
input [7:0]data,
input flag_start,
output reg out,
output reg flag_busy
);
wire [9:0]res = {1'b1, data, 1'b0};
reg [3:0]bit_num = 4'h0;
always @(posedge clk) begin
out <= res[bit_num];
if((flag_start == 1) && (flag_busy == 0)) begin
bit_num <= 0;
flag_busy... | |
// SPDX-License-Identifier: Apache-2.0
// Copyright (C) 2019 Intel Corporation.
// Library - aibnd_lib, Cell - aibnd_rambit_buf, View - schematic
// LAST TIME SAVED: Apr 19 23:56:59 2015
// NETLIST TIME: May 12 17:53:11 2015
// `timescale 1ns / 1ns
module aibnd_rambit_buf ( sig_out, sig_in, vccl_aibnd, vssl_a... | |
module mux2(select,a,b,y);
input select;
input[31:0] a,b;
output reg [31:0] y;
always@(select,a,b) begin
case(select)
1'b0:y=a;
1'b1:y=b;
endcase
end
endmodule
module mux2A(select,a,b,y);
input select;
input[4:0] a,b;
output reg [4:0] y;
always@(select,a,b) begin
case(select)
1'b0:y=a;
1'b1... | |
module wideexpr_00419(ctrl, u0, u1, u2, u3, u4, u5, u6, u7, s0, s1, s2, s3, s4, s5, s6, s7, y);
input [7:0] ctrl;
input [0:0] u0;
input [1:0] u1;
input [2:0] u2;
input [3:0] u3;
input [4:0] u4;
input [5:0] u5;
input [6:0] u6;
input [7:0] u7;
input signed [0:0] s0;
input signed [1:0] s1;... | |
module EHR_6 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5
);
parameter ... | |
// Guia 10 - 01
// Paulo Henrique de Almeida Amorim - 412765
// constant definitions
`define found 1
`define notfound 0
// FSM by Mealy
module exercicio01_seq010_mealy ( y, x, clk, reset );
output y;
input x;
input clk;
input reset;
reg y;
parameter // state identifiers
... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22.02.2022 17:03:16
// Design Name:
// Module Name: SpiControll
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenci... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:33:11 06/01/2013
// Design Name:
// Module Name: mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependenci... | |
module FixedPointAdder (
input signed [15:0] num1, // 16-bit signed fixed-point number 1
input signed [15:0] num2, // 16-bit signed fixed-point number 2
output reg signed [16:0] result // 17-bit signed fixed-point result
);
reg signed [16:0] result_temp;
always @(*) begin
result_temp = num1 +... | |
module unsigned_multiplier (
input [7:0] A,
input [7:0] B,
output reg [15:0] C
);
reg [15:0] temp;
integer i;
always @(*) begin
temp = 16'b0;
for(i = 0; i < 8; i = i + 1) begin
if(B[i] == 1) begin
temp = temp + (A << i);
end
end
C = t... | |
module comparator (
input [7:0] num1,
input [7:0] num2,
output equal_flag,
output greater_flag,
output less_flag
);
wire [7:0] xor_output;
wire [7:0] and_output;
assign xor_output = num1 ^ num2;
assign and_output = num1 & num2;
assign equal_flag = !| xor_output;
assign greater_flag... | |
module shift2(input [63:0] data1 , output [63:0] data2);
wire [1:0] a = 2'b00;
assign data2 = {data1[63:0] , a};
endmodule
| |
module counter
(
input clk,
input aclr_n,
output [1:0]count_out
);
reg [1:0]Q_next,Q_reg;
always@(posedge clk,negedge aclr_n)
begin
Q_reg<=Q_reg;
if(!aclr_n)
Q_reg<=2'b00;
else
Q_reg<=Q_next;
end
always@(Q_reg)
begin
Q_next=Q_reg+(1'b1);
end
assign count_out=Q_reg;
endmodule
| |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17.06.2023 23:30:05
// Design Name:
// Module Name: slowclk100Hz
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenc... | |
// This file contains a pareto-optimal circuit with respect to pdp and the fault-resilince parameter p_fault which is defined as:
// "For all input vectors, the ratio of the no. of faults observable at the POs to the no. of total possible faults in the circuit".
// This code is part of the ReCkt library (https://gith... | |
`timescale 1ns / 1ps
module aircraft_led
(
input sys_clk,
input rst_n,
output reg out
);
reg toggle = 1'b0;
reg [31:0] counter = 0 ;
reg [24:0] count_reg = 0;
reg clk1 = 0;
always @(posedge sys_clk)
begin
if (rst_n == 1'b0) begin
count_reg <= 0;
clk1 <= 0;
end else... | |
module vga_sync_generator(
input clk,
input rst,
output hsync,
output vsync,
output blanking
);
reg [10:0] h_counter = 0;
reg [9:0] v_counter = 0;
always @(posedge clk or posedge rst) begin
if (rst) begin
h_counter <= 0;
v_counter <= 0;
hsync <= 1'b0;
... | |
module fj_latch_e(Q, G, D);
output Q;
input G, D;
reg Q;
always @ (G or D) begin
if (G==1) Q <= #1 D;
end
endmodule | |
//------------------------------
// Module name: add3_ge5
// Function: Add 3 to input if it is 5 or above
// Creator: Peter Cheung
// Version: 1.0
// Date: 21 Jan 2014
//------------------------------
module add3_ge5(iW,oA);
input [3:0] iW;
output reg [3:0] oA;
always @ (iW)
case (iW)
... | |
module sky130_fd_sc_hs__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule | |
module alu (a,b,aluc4,s,z);
input [31:0] a,b;
input [3:0] aluc4;
output [31:0] s;
output z;
wire [3:0] aluc4;
reg [31:0] s;
reg z;
always @ (a or b or aluc4)
begin // event
casex (aluc4)
4'bx000: s = a + b; ... | |
module timing_control_sync(
input wire clk_a,
input wire clk_b,
input wire reset,
// Add other input ports as needed
// Add output ports as needed
);
// Add Verilog code for timing control and synchronization blocks here
endmodule | |
module UART_TFIFO
#(parameter DWIDTH = 8, AWIDTH = 1)
(
input wire clk,
input wire rstn,
input wire rd,
input wire wr,
input wire [DWIDTH-1:0] w_data,
output wire empty,
output wire full,
output wire [DWIDTH-1:0] r_data
);
// Internal Signal declarations
reg [DWIDTH-1:0] array_reg [2**AWIDTH... | |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
... | |
// ==============================================================
// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit)
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// ==============================================================
`timescale 1 ns / 1 ps
module backprop_chang... | |
/*
Universal binary counter with
* synchronous clear
* enable
* load
* direction (up or not(up) which is equal to down)
* min and max tick
*/
module univ_bin_counter
#(parameter N=8)
(
input wire clk, reset,
input wire sync_clear, enable, load, up,
input wire [N-1:0] d,
outp... | |
module j_shifter #(
parameter SRAM_DEPTH = 256*256*4 ,
parameter SRAM_ADDR_W = clog2(SRAM_DEPTH)
) (
input clk ,
input reset_n ,
output reg sram_en ,
output reg [SRAM_ADDR_W-1:0] sram_addr ,
i... | |
module Mealy_State_Machine (
input wire clk,
input wire reset,
input wire in_data,
output reg out_data
);
// Define states
parameter STATE_A = 2'b00;
parameter STATE_B = 2'b01;
parameter STATE_C = 2'b10;
// Define state register
reg [1:0] state_reg, next_state;
// Define output logic
... | |
module allocate(
input wire clk,
input wire rst,
input wire [31:0] CPU_addr,
input wire [31:0] main_mem_dout,
output reg [12:0] main_mem_addr,
output reg [8:0] cache_data_addr,
output wire [31:0] cache_data_din,
output reg cache_data_we,
input wire start,
output ... | |
// -------------------------
// Moore1010
// Nome: Guilherme Andrade Salum Terra
// Matricula: 427407
// -------------------------
// --------------
// --- Moore FSM
// --------------
// constant definition
`define found 1
`define notfound 0
// FSM by Moore
module moore1010 ( y, x, clk, re... | |
module ShiftQueue( // @[:freechips.rocketchip.system.TinyConfig.fir@109889.2]
input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@109890.4]
input reset, // @[:freechips.rocketchip.system.TinyConfig.fir@109891.4]
output io_enq_ready, // @[:freechips.rocketchip.system.TinyConfig.... | |
module sm_register_file
(
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf [31:0];
assign rd0 = (a0 != 0)... | |
module ov7670_config(
input clk_25M,
input rst_n_25M,
input sccb_ready,
input start,
input [7:0] conf_addr,
input [7:0] conf_data,
input[15:0] rom_data,
output reg done,
output reg sccb_start,
output reg [7:0] rom_address,
output reg [7:0] sccb_data,
output reg[7:0] sccb_address
);
// On rese... | |
//todo BCD adder
//bcd 0-9 | 0000 - 1001
// assign
// module adder_bcd (
// input wire [3:0] a,
// input wire [3:0] b,
// input wire cin,
// output wire [3:0] sum,
// output wire cout
// );
// wire [4:0] sum_temp;
// assign sum_temp = a + b + cin;
// assign sum = (sum_temp > 9) ... | |
module programmable_clock_divider (
input wire clk,
input wire reset,
input wire [7:0] divisor,
output reg out_clk
);
reg [7:0] counter;
always @ (posedge clk or posedge reset) begin
if (reset) begin
counter <= 8'h00;
out_clk <= 1'b0;
end else begin
if (co... | |
module aluselct(output h,input a,input b,input c,input d,input e );
or or1(temp1,a,b);
or or2(temp2,c,d);
or or3(temp3,e,temp2);
or or4(h,temp3,temp1);
endmodule | |
module Solidsquare_Y(input wire sysclk,
input wire Enable_SW_3,
output wire Pulse);
reg [5:0] count = 0;
reg [5:0] DC_Index = 0;
reg [5:0] Amp_Index = 0;
reg [6:0] Duty_Cycle = 0;
reg [5:0] Index_Count = 0;
assign Pulse = (count < Duty_Cycle) * Enable_SW_3;
always @(posedge sysclk)begin
count<=count+1'... | |
//
// HPSDR - High Performance Software Defined Radio
//
// Metis code.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your optio... | |
/* Generated by Yosys 0.20 (git sha1 4fcb95ed087, clang 14.0.0-1ubuntu1 -fPIC -Os) */
(* dynports = 1 *)
(* src = "dlatchsr.v:1.1-15.10" *)
module m_0(CLR, CLR_t, D, D_t, EN, EN_t, Q, Q_t, SET, SET_t);
(* src = "dlatchsr.v:7.19-7.20" *)
input [1:0] CLR;
wire [1:0] CLR;
(* src = "dlatchsr.v:7.19-7.20"... | |
//////////////////////////////////////////////////////////////////////////////////
// Module: InstMem.v
// Project: Single Cycled RISC_V Processor
// Author: Kyrollos Soliman - kyrolloszakaria@aucegypt.edu, Michael Reda Michael12@aucegypt.edu
// Description: the memory for instructions
////////////////////////////... | |
module and32(dataA, dataB, dataOut);
input [31:0] dataA, dataB;
output [31:0] dataOut;
genvar c;
generate
for(c=0; c<32; c = c + 1) begin: andLoop
and andAB(dataOut[c], dataA[c], dataB[c]);
end
endgenerate
endmodule |