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module pari_gen_odd
(input a,b,c,
output p);
wire x;
xor r1(x,b,c);
xor r2(p,x,a);
endmodule
| |
module oversampling
(
input [7:0]sclk,
input res,
input enable,
input sdata,
output [7:0]samples,
output reg [7:0]trans
);
reg [7:0]s1; // fixed position in FPGA
always @(posedge sclk[0]) s1[0] <= sdata;
always @(posedge sclk[1]) s1[1] <= sdata;
always @(posedge sclk[2]) s1[2] <= sdata;
alw... | |
module fifomem #(parameter DATA_SIZE = 16, // Memory data word width
parameter ADDR_SIZE = 12) // Number of mem address bits
(output [DATA_SIZE-1:0] rdata,
input [DATA_SIZE-1:0] wdata,
input [ADDR_SIZE-1:0] waddr, raddr,
input wclken, wfull, wclk);
`ifdef VENDORRAM
// Instantiation of a vendor's dual... | |
module ballscan(clk, screenx, screeny, ball_x, ball_y, ball_scan);
parameter BALLSIZE=8;
input clk;
input [9:0] screenx;
input [9:0] screeny;
input [9:0] ball_x;
input [9:0] ball_y;
output ball_scan;
reg [3:0] ballscanX;
reg ballscanY;
always @(posedge clk) begin
if (screenx == ball_x-BALL... | |
// VIS testbench for a sequential floating point multiplier.
// The purpose of this testbench is exclusively to latch the inputs, so
// that CTL properties may refer to them.
//
// Author: Fabio Somenzi <Fabio@Colorado.EDU>
//
module fvFPMult(clock,i,j);
parameter MBITS = 3; // size of significand minus h... | |
module prnf5ccc (
address,
clock,
q);
input [15:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:58:29 06/24/2018
// Design Name:
// Module Name: number_mod
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Depe... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:29:49 03/19/2014
// Design Name:
// Module Name: pbdebounce
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Depe... | |
//ps2_scan
`timescale 1ns/1ps
module ps2_scan(
clk, rst_n, ps2k_clk, ps2k_data,
ps2_byte, ps2_state
);
input clk; //50MHz
input rst_n; //reset signal , active low
input ps2k_clk; //PS2
input ps2k_data; //PS2
output [7:0] ps2_byte; //1byte
output ps2_state; //1 :
//-----------------------... | |
module B_G( input [2:0]B,output [2:0]G );
// gate level modelling
buf (G[2],B[2]);
xor x1(G[1],B[2],B[1]);
xor x2 (G[0],B[1],B[0]);
endmodule | |
module LUT2_D (LO, O, I0, I1);
parameter INIT = 4'h0;
input I0, I1;
output LO, O;
reg O;
wire LO;
wire [1:0] s;
assign s = {I1, I0};
assign LO = O;
always @(s)
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
O = INIT[s];
else if ((INIT[0] =... | |
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Caglayan DOKME
// Create Date: 09.05.2020
// Module Name: DFF (Industry Version)
// Description:
// Revision:
// 09.05.2020 -> Revision 0.01 - Created
////////////////////////////////////////////////////////////////... | |
/* -----------------------------------------------------------------------------
* Part of midgetv
* 2019-2020. Copyright B. Nossum.
* For licence, see LICENCE
* ----------------------------------------------------------------------------ehdr
* This is the fundamental input multiplexer, which is the last part... | |
module logical_OR (input wire [31:0] A, B, output wire [31:0] result);
assign result = A | B;
endmodule
| |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Private
// Engineer: Uttej
//
// Create Date: 07/01/2019 09:28:08 PM
// Design Name:
// Module Name: MAC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dep... | |
module LShifter(shift, lr, in, out);
//lr? 1 == left, 0 == right
//logical shifter
input [3:0] shift;
input lr;
input [15:0] in;
output [15:0] out;
wire [15:0] st1, st2, st3;
assign st1 = shift[0]? (lr? {in[14:0], 1'b0}:{1'b0, in[15:1]}) : in[15:0];
assign st2 = shift[1]? (lr? {st1[13:0], 2'b... | |
module bancoInstrucoes (
input wire clock,
input wire [7:0] endereco,
output wire [7:0] out
);
reg [7:0] memoriaInstrucoes [10:0];
reg[7:0] memoriaPC;
always @(posedge clock)
begin
memoriaPC = memoriaInstrucoes[endereco];
end
assign out = memoriaPC;
/*reg [7:0] memori... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/04/15 15:12:59
// Design Name:
// Module Name: EXEMEM
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
... | |
`timescale 1ns / 1ps
module BusMux3(
input [31:0] IN1,
input [31:0] IN2,
input [31:0] IN3,
input [1:0] SEL,
output reg [31:0] R
);
always @(*)
begin
case (SEL)
0: R = IN1;
1: R = IN2;
2: R = IN3;
default: R = IN1;
endcase
end
endmodule
| |
module ALU(
input [7:0] A,
input [7:0] B,
input [2:0] control,
input add_sub,
output reg [7:0] result,
output reg carry_out
);
reg [8:0] temp_result;
always @(*)
begin
case(control)
3'b000: begin // Addition
if(add_sub == 1)
temp_result =... | |
module ALU_4bit (f, a, b, op);
input [1: 0] op;
input [7: 0] a, b;
output reg [7: 0] f;
parameter ADD = 2'b00, SUB = 2'b01, MUL = 2'b10, DIV = 2'b11;
always @ (*)
begin
case (op)
ADD: f <= a + b;
SUB: f <= a - b;
MUL: f <= a * b;
DIV: f <=... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/02/24 13:17:25
// Design Name:
// Module Name: rcomp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
... | |
module if_else_statement (
input wire condition1,
input wire condition2,
output reg output_signal
);
always @ (*) begin
if (condition1 || condition2) begin
// Block of code to execute when condition1 or condition2 is true
output_signal <= 1;
end
else begin
//... | |
/******************************************************************
* Description
* This is a register of 32-bit that corresponds to the PC counter.
* This register does not have an enable signal.
* Version:
* 1.0
* Author:
* Dr. Jos Luis Pizano Escalante
* email:
* luispizano@iteso.mx
* Date:
* 05/07/2020
... | |
module datapath (
input rst_n, clk,
input [31:0] size,
input latch_size,
input [ 7:0] data,
input upd_data,
input clr_data,
input dec_cnt,
output last_data,
output [31:0] checksum
);
reg [15:0] A, B;
reg [31:0] size_cnt;
wire [15:... | |
module part2 (input [1:0]SW, input [0:0]KEY, output [9:0] LEDR);
reg [3:0] current, next;
parameter A = 4'b0000, B = 4'b0001, C = 4'b0010, D = 4'b0011, E = 4'b0100,
F = 4'b0101, G = 4'b0110, H = 4'b0111, I = 4'b1000;
wire w;
assign w = SW[1];
always @(w, current)
begin: state_table
case (curren... | |
//SW[0] reset when 0
//SW[1] input signal
//KEY[0] clock signal
//LEDR[3:0] displays current state
//LEDR[9] displays output
module part1(Clock, Reset, w, z, CurState);
input Clock;
input Reset;
input w;
output z;
output [3:0] CurState;
reg [3:0] y_Q, Y_D; // y_Q represents cu... | |
module sky130_fd_sc_hs__einvn (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:35:48 11/12/2020
// Design Name:
// Module Name: cla_16bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Depen... | |
module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*RAMDATA enable parameter*/
parameter Port1_en = 1,
/************************/
/*LED enable parameter*/
parameter Port2_en = 1,
/************************/
/... | |
module fifo_buffer (
input clk,
input rst,
input wr_en,
input [DATA_WIDTH-1:0] data_in,
output reg empty,
output reg full,
output reg [DATA_WIDTH-1:0] data_out,
input rd_en
);
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;
reg [DATA_WIDTH-1:0] fifo_mem[FIFO_DEPTH-1:... | |
`ifndef FIXWID
`define FIXWID 16
`endif
`ifndef FIXASH
`define FIXASH 10
`endif
module fix_mul(
output reg overflow,
output reg [`FIXWID-1:0] z,
input [`FIXWID-1:0] a, b
);
reg sign;
reg [`FIXWID-1:0] abs_a, abs_b;
reg [2*`FIXWID-1:0] abs_r_result;
always@(*) begin
sign = a[`FIXWID-1] ^ b[... | |
`timescale 1ns/1ps
module PcAdder (
input [31:0] pc,
output reg [31:0] nextPc
);
always @(pc) begin
nextPc = pc + 32'h00000004;
//waits a cycle so pc isnt constantly being written to
#1;
end
endmodule | |
module expManZeroOne(input [15:0]a, input [15:0]b, output isExpAZero, output isExpBZero, output isExpAOne, output isExpBOne, output isManAZero, output isManBZero, output isManAOne, output isManBOne);
assign isExpAZero = a[14]|a[13]|a[12]|a[11]|a[10];
assign isExpBZero = b[14]|b[13]|b[12]|b[11]|b[10];
assign isExp... | |
module comparator8bit (
input signed [7:0] a,
input signed [7:0] b,
output f_bigger,
output signed [7:0] diff
);
wire [8:0] temp;
wire [7:0] complement_b;
assign complement_b = ~b +1'b1;
assign temp = a +complement_b;
assign f_bigger = temp[8];
assign diff = temp[8] ? temp[7:0... | |
`timescale 1ns / 1ps
module oneHz_gen(
input clk_100MHz,
output clk_1Hz
);
reg r_1Hz = 0;
reg [25:0] r_counter = 0;
always @(posedge clk_100MHz)
if(r_counter == 49_999_999) begin
r_counter <= 0;
r_1Hz <= ~r_1Hz;
end
else
... | |
// Copyright lowRISC contributors.
// Copyright 2017 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
////////////////////////////////////////////////////////////////////////////////
// Engineer: Matthia... | |
module AS(sel, A, B, S, O);
input [3:0] A, B;
input sel;
output [3:0] S;
output O;
wire C1;
wire C2;
wire C3;
wire B0;
wire B1;
wire B2;
wire B3;
xor(B0, B[0], sel);
xor(B1, B[1], sel);
xor(B2, B[2], sel);
xor(B3, B[3], sel);
xor(O, C4, C3);
Full_adder FA0(S[0], C1, A[0], B0,... | |
module lab5(in, out);// lab6()
//
input [2:0]in; // in , 3bit wire
output [3:0]out; // out , 4bit wire
wire nin2, nin1, nin0; //
wire w0, w1, w2, w3, w4, w5, w6;
//
// not in[2] nin2
not n2(nin2, in[2]),
n1(nin1, in[1]),
n0(nin0, in[0]);
// and and gate
and a0(w0, nin2, nin1,... | |
`timescale 1ns/1ns
module EXMEM(
input clk, rst, zeroin, RegWritein, MemWritein, MemReadin, PCsrcin,
input[1:0] MemtoRegin,
input[4:0] win,
input[31:0] pcp4in, pcin, Oin, rdata2in
);
//output reg RegWriteout, MemtoRegout, MemWriteout, MemReadout, ALUsrcout, RegDstout,
//output reg[1:0] ALUopout,
... | |
module data_pipe(
input [7:0] in,
output reg [7:0] out,
input clk
);
always@(posedge clk)
out <= in;
endmodule
| |
module MUX(in0, in1, sel, out);
parameter len = 32;
input [len-1:0] in0, in1;
input sel;
output [len-1:0] out;
assign out = sel ? in1 : in0;
endmodule | |
module if_else_statement(
input wire condition,
output reg result
);
always @(*)
begin
if (~condition) begin
// statements to be executed if condition is false
result <= 0;
end else begin
// statements to be executed if condition is true
result <= 1;
end... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:17:49 05/23/2016
// Design Name:
// Module Name: Decodificador_tecla
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//... | |
module mybram #(parameter LOGSIZE=14, WIDTH=1)
(input wire [LOGSIZE-1:0] addr,
input wire clk,
input wire [WIDTH-1:0] din,
output reg [WIDTH-1:0] dout,
input wire we);
// let the tools infer the right number of BRAMs
(* ram_style = "... | |
//design code for Hamming encoder
module hamenc(clk,d,c );
input clk;
input [3:0] d;
output reg[6:0] c;
always@(posedge clk)
begin
c[6]=d[3];
c[5]=d[2];
c[4]=d[1];
c[3]=d[1]^d[2]^d[3];
c[2]=d[0];
c[1]=d[0]^d[2]^d[3];
c[0]=d[0]^d[1]^d[3];
end
... | |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack );
// count 1000cycle 1 -> 0 1000cycle
parameter A = 0, B = 1, C = 2, D = 3; //1101
parameter shift_S0 = 4, shift_S1 = ... | |
`timescale 1ns / 1ps
module dff_1(
input D,
input clk,
input rst,
output reg q
);
always @(posedge (clk) , posedge (rst))begin
if (rst)begin
q<= 1'b0;
end else begin
q<=D;
end
end
endmodule
| |
module mux_4to1(
input [3:0] input_lines,
input [1:0] select_line,
output output_line
);
assign output_line = select_line[1] ? input_lines[3:2] : input_lines[1:0];
endmodule | |
module SimplePulseGenerator (
input clk,
input rst,
input [31:0] pulse_width,
input [31:0] pulse_freq,
output reg pulse
);
reg [31:0] counter;
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 0;
pulse <= 0;
end else begin
if (counter >= pulse_width) begin
... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:52:45 12/16/2020
// Design Name:
// Module Name: branch_comparator
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
... | |
`timescale 1ps / 1ps
/*****************************************************************************
Verilog RTL Description
Configured at: 21:20:32 CST (+0800), Tuesday 12 April 2022
Configured on: ws37
Configured by: u107061139 (u107061139)
Created by: Stratus DpOpt 2019.1.01
**... | |
// Guia 10
// Karen Alves Pereira
// Matricula: 407451
// ---Exercicio 02
// constant definition
`define found 1
`define notfound 0
// FSM by Moore
module seq0110_moore ( y, x, clk, reset );
output y;
input x;
input clk;
input reset;
reg y;
parameter // state id... | |
//random number generator
//author:WangFW
//date:2020-5-4
module LSFR(clk,rst_n,load,initial_num,dout);
input clk,rst_n;
input load;
input [3:0] initial_num;
output reg [3:0] dout;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
dout<=4'd0;
else if(load)
dout<=initial_num;
... | |
module fulladder(
output Sum,
output Co,
input A,
input B,
input Ci
);
wire S1,S2,S3;
xor(Sum,A,B,Ci);
and(S1,A,B);
xor(S2,A,B);
and(S3,Ci,S2);
or (Co,S1,S3);
endmodule | |
module am_mod_counter
#(
parameter N_BLOCKS = 16383, //[REVISAR] cantidad de bloquen entre am y am
parameter N_LANES = 20
)
(
input wire i_reset,
input wire i_clock,
input wire i_enable,
input wire i_valid, // coontrol de flujo de cgmii, puede estar siempre en 1
output wire o_bloc... | |
module multiplier (
input wire [7:0] a,
input wire [7:0] b,
output reg [15:0] product
);
assign product = a * b;
endmodule | |
module f_adder(
input a, b, cin,
output cout, sum );
assign {cout, sum} = a + b + cin;
endmodule
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
f_adder add1(a[0], b[0], cin, cout[0], sum[0]);
f_adder add2(a[1], b[1], cout[0],... | |
module Quadriture
(
input wire A, // Feedback from motor
input wire B, // Feedback from motor
input wire clk, // 50 MHz clock
output reg signed [7 : 0] speed // The speed calculated from the feedback (signed)
);
// REG/WIRE ... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:03:01 11/23/2017
// Design Name:
// Module Name: sp_ram_rw_instruction
// Project Name:
// Target Devices:
// Tool versions:
// Description:
... | |
`timescale 1ns / 1ps
module IF_ID_Register(Clk, Rst, Instruction, PC, Instruction_out, PC_out, myPC, myPC_out);
input Clk, Rst;
input [31:0] Instruction;
input [31:0] PC;
input [31:0] myPC;
output reg [31:0] Instruction_out;
output reg [31:0] PC_out;
output reg [31:0] myPC_out;
... | |
`timescale 1ns / 1ps
module stalling_unit(
input Ex_O_Mem_Reg_Write,
input Ex_O_Mem_MemRead,
input [4:0] Ex_O_Mem_Rd,
input Id_O_Ex_MemRead,
input Id_O_Ex_Reg_Write,
input [4:0] Id_Out_Ex_Rd,
input [4:0] Id_Out_Ex_Rs2,
input [4:0] If_Id_Rs2,
input [4:0] If_Id_Rs1,
input [6:0] opcocde,
input [6:0] Id_O_E... | |
module CascadeBypassRegister (
input wire clk,
input wire rst,
input wire bypass_1,
input wire bypass_2,
input wire bypass_3,
input wire [31:0] data_in,
output wire [31:0] data_out
);
reg [31:0] reg_1;
reg [31:0] reg_2;
reg [31:0] reg_3;
always @(posedge clk or posedge rst) b... | |
// Name: logic_32_bit.v
// Module:
// Input:
// Output:
//
// Notes: Common definitions
//
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu In... | |
module cpx_buf_p4(/*AUTOARG*/
// Outputs
scache3_cpx_req_bufp4_cq, scache3_cpx_atom_bufp4_cq,
io_cpx_req_bufp4_cq, cpx_scache3_grant_bufp4_ca,
cpx_spc7_data_rdy_bufp4_cx,
// Inputs
scache3_cpx_req_bufpt_cq_l, scache3_cpx_atom_bufpt_cq_l,
io_cpx_req_bufpt_cq_l, cpx_scache3_grant_bufp3_ca_... | |
// Copyright 2023 Dominik Brandstetter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE2.0
//
// Unless required by applicable law or a... | |
module Line_Follower (
input clk ,
input colour_freq,
output red_led,
output blue_led,
output s2,
output s3,
output green_led ,
output TX
) ;
reg Tx = 0 ;
assign TX = Tx ;
reg temp_col_freq;
reg [50:0] act_freq_cnt1 = 0;
reg [50:0] cnt_freq_str1 = 0;
reg [50:0] act_freq_cnt2 = ... | |
module Select_gen (output reg [2:0] s_e, s_w, s_n, s_s, s_eject,
input e_g, w_g, n_g, s_g, inject_g, clk, reset, input [2:0] e_req, w_req, n_req, s_req, inject_req);
always @(posedge clk)
begin
if(reset)
begin
s_e = 3'b111;
s_w = 3'b111;
s_n = 3'b111;
... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.04.2022 01:15:02
// Design Name:
// Module Name: anode_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependen... | |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual pro... | |
module ALUControl(
input [1:0] ALUOp,
input [5:0] OP,
input [5:0] func,
output reg [2:0] s
);
// s == 0 --add; s == 1 --sub; s == 2 --or; s == 3 --xor; s == 4 --nor; s == 5 --slt;
always @ (*)
begin
if (ALUOp == 2'b00)
s = 0;
else if (ALUOp == 2'b01)
... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/05/22 16:15:21
// Design Name:
// Module Name: wen
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//... | |
`timescale 1ps/1ps
module cell_nor3
(
input wire A,
input wire B,
input wire C,
output wire Y
);
assign Y = !(A | B | C);
endmodule
| |
module SevenSegDec (clock,DataIn, AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE, CF, CG, CDP);
input [15:0] DataIn; // = 16'h9ABC;
//USED FOR SEVEN SEG
input clock;
output AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE, CF, CG, CDP;
reg [7:0] cathodedata; //cathode data
reg [3:0] anodedata; //anode data
reg [2:0] digit ... | |
module AddRoundKey(
input [127:0] Data_in,
output [127:0] Data_out,
input [127:0] Key
);
assign Data_out = Key ^ Data_in;
endmodule
| |
module neg_edge_d_flip_flop(
input D,
input clk,
output reg Q
);
always @(negedge clk) begin
Q <= D;
end
endmodule | |
/*
1s
00
01
10
*/
module button_state (
input key, //
input CLOCK_50,
output reg[1:0] state
);
reg en;
reg[27:0] count; //
always @(posedge CLOCK_50) begin
if(key == 0)
en <= 1;
else en <= 0;
end
always @(posedge CLOCK_50) begin
if... | |
module and_gate (
input A,
input B,
output reg Y
);
always @* begin
if (A && B) begin
Y = 1;
end else begin
Y = 0;
end
end
endmodule | |
module ParallelPrefixCircuit(outputflag, inputflag);
input [33:0] inputflag;
output [33:0] outputflag;
wire [33:0] output1;
wire [33:0] output2;
wire [33:0] output3;
wire [33:0] output4;
assign output1[33:32] = (^inputflag[33:32]) ? {inputflag[31],inputflag[30]} : inputflag[33:32];
assign output1[31:30] =... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//`define DCM 1
module u1e
(output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
input debug_pb,
// GPMC
input EM_CLK, input [15:0] EM_D, input [10:1] EM_A,
input EM_WAIT0,... | |
module activation(
input [7:0] in,
input [7:0] treshold,
output reg out
);
always@(*)
begin
if(in>treshold)
begin
out=1'b1;
end
else
begin
out=1'b0;
end
end
endmodule
| |
`timescale 1ns / 1ps
module One_Bit (
input a, b,
output c, d, e, f
);
assign c = ( a == b );
assign d = ( a != b );
assign e = ( a > b );
assign f = ( a < b );
endmodule
| |
module S1L3C(entrada1, entrada2, control, salida);
input entrada1, entrada2, control;
output salida;
wire A;
wire B;
assign salida = (control) ? A : B;
assign A = entrada1 & entrada2;
assign B = entrada1 | entrada2;
endmodule
| |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, dist... | |
module binaryToBCD(
input wire clk, start,
input wire [19:0] bin,
output wire[3:0] bcd3, bcd2, bcd1, bcd0
);
reg [4:0] i;
reg[15:0] bcd;
always @(posedge clk)
begin
bcd = 0;
for(i = 0; i < 20; i = i+1)
begin
bcd = {bcd[14:0], bin[19-i]};
if( i < 19 && bcd[3:0] > 4)
bcd[... | |
module wideexpr_00074(ctrl, u0, u1, u2, u3, u4, u5, u6, u7, s0, s1, s2, s3, s4, s5, s6, s7, y);
input [7:0] ctrl;
input [0:0] u0;
input [1:0] u1;
input [2:0] u2;
input [3:0] u3;
input [4:0] u4;
input [5:0] u5;
input [6:0] u6;
input [7:0] u7;
input signed [0:0] s0;
input signed [1:0] s1;... | |
module control(
instruction,
RegDst,
MemRead,
MemtoReg,
ALUOp,
MemWrite,
ALUSrc,
RegWrite);
input [5:0] instruction;
output reg RegDst, MemRead, MemtoReg,
MemWrite, ALUSrc, RegWrite;
output reg [1:0] ALUOp;
always @ (instruction) begin
case (in... | |
module decoder2_4(register,reg_no);
input [1:0] reg_no;
output [3:0] register;
reg [3:0] register;
always @(reg_no)
begin
case(reg_no)
2'b00:
begin
register[0] = 1'b1;
register[1] = 1'b0;
register[2] = 1'b0;
register[3] = 1'b0;
end
2'b01:
begin
register[0] = 1'b0;
regi... | |
//***************************************
// Vanshika Tanwar
//Verilog file: dvsd_cmp.v
//***************************************
module dvsd_cmp(
//Input A
A_in,
//Input B
B_in, ... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/05/17 09:06:22
// Design Name:
// Module Name: Control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies: ... | |
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:27:56 07/15/2016
// Design Name:
// Module Name: memory
// Project Name:
// Target Devices:
// Tool versions:
// Descr... | |
module d_ff_sync_reset(
input wire D,
input wire CLK,
input wire RESET,
output reg Q
);
always @(posedge CLK or posedge RESET) begin
if (RESET) begin
Q <= 1'b0; // Reset to known state
end else begin
Q <= D; // Load D on rising edge of clock
end
end
endmodule | |
module MUX7(input [31:0] alu,eight,sixteen,
input [1:0] memToReg,
output reg [31:0] Result);
always @(*)
begin
case (memToReg)
//ALU Result
2'b00: Result = alu;
//16 bit sign extended
2'b01: Result = sixteen;
//8 bit zero extended : 10, 11
default: Result = eight;
endcase
end
endmodule... | |
module Hazard_Detection (
ID_EX_MemRead_i,
ID_EX_RDaddr_i,
RS1addr_i,
RS2addr_i,
NoOp_o,
PCWrite_o,
Stall_o
);
input ID_EX_MemRead_i;
input [4:0] ID_EX_RDaddr_i, RS1addr_i, RS2addr_i;
output reg NoOp_o, PCWrite_o, Stall_o;
always @(ID_EX_RDaddr_i, RS1addr_i, RS2addr_i) beg... | |
// This Verilog HDL source file was automatically generated
// by C++ model based on VPP library. Modification of this file
// is possible, but if you want to keep it in sync with the C++
// model, please modify the model and re-generate this file.
// VPP library web-page: http://www.phys.ufl.edu/~madorsky/v... | |
`timescale 1ns / 1ps
module lector(funcion,orden,out1,out2,out3,bus);
input orden, funcion;
input [3:0] out1, out2, out3;
output reg [10:0] bus;
initial
bus<=11'd0;
always @(posedge orden, negedge funcion)
if(~funcion)
bus=11'd0;
else if(orden)
bus=out1*7'd100+out2*4'd10+out3;
endmo... | |
module FIFO(clk,rst,buf_in,buf_out,wr_en,rd_en,buf_empty,buf_full);
parameter N=32;
input rst,clk,wr_en,rd_en;
input[N-1:0] buf_in;
output reg[N-1:0] buf_out;
output reg buf_empty,buf_full;
reg[6:0] fifo_counter;
reg[5:0] rd_ptr,wr_ptr;
reg[N-1:0] buf_mem[63:0];
always @(fifo_counter) begin
buf_empty<=(fi... | |
module P_SYNC
#(
parameter BUS_WIDTH = 3,
parameter NUM_STAGES = 2
)
(
input wire CLK,
input wire rst_n,
input wire [BUS_WIDTH-1:0] Async,
output reg [BUS_WIDTH-1:0] Sync
);
// Number of stages
reg [NUM_STAGES-1:0] NFFS [BUS_WIDTH-1:0];
integer i;
always @(posedge CLK , negedge rs... | |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer:
// Create Date: 2020/11/24 14:04:39
// Module Name: digitron_driver
// Description: This is digitron driver
//
///////////////////////////////////////////////////////////////////////////////... | |
module uart_reciever
(
input clk,
input rx,
output rx_done,
output [7:0] rx_byte
);
// Define uart reciever state items
reg [1:0] state;
localparam [1:0]
IDLE = 2'b00,
START = 2'b01,
DATA = 2'b10,
STOP = 2'b11;
// Counter used to sample in the middle of a uart bit
/... |