code stringlengths 1 2.01M | repo_name stringlengths 3 62 | path stringlengths 1 267 | language stringclasses 231 values | license stringclasses 13 values | size int64 1 2.01M |
|---|---|---|---|---|---|
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package dao;
import java.util.List;
import myClass.Post;
import pojo.User;
/**
*
* @author 4pril
*/
public class PostDAO extends ObjectDAO{
public static List<Post> getListPost(User u_id){
String hql = "from MyObject p where p.onUser = " + u_id + " and p.ObjType.ObjName = 'post'";
return (List<Post>) (List<?>) getList(hql);
}
}
| 11hca1-java-web | trunk/src/java/dao/PostDAO.java | Java | gpl3 | 491 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package system;
/**
*
* @author 4pril
*/
public class System {
private static String login_url = "login";
private static String home_url = "index";
/**
* @return the login_url
*/
public static String getLogin_url() {
return login_url;
}
/**
* @param aLogin_url the login_url to set
*/
public static void setLogin_url(String aLogin_url) {
login_url = aLogin_url;
}
/**
* @return the home_url
*/
public static String getHome_url() {
return home_url;
}
/**
* @param aHome_url the home_url to set
*/
public static void setHome_url(String aHome_url) {
home_url = aHome_url;
}
}
| 11hca1-java-web | trunk/src/java/system/System.java | Java | gpl3 | 851 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package myClass;
import dao.ObjectTypeDAO;
/**
*
* @author 4pril
*/
public class Post extends pojo.Object{
public Post(){
this.setObjType( ObjectTypeDAO.getObjectTypeByName("post"));
}
}
| 11hca1-java-web | trunk/src/java/myClass/Post.java | Java | gpl3 | 337 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import dao.MyQuery;
import dao.UserDAO;
import java.io.IOException;
import java.io.PrintWriter;
import java.net.URLDecoder;
import java.util.List;
import java.util.logging.Level;
import java.util.logging.Logger;
import javax.servlet.ServletException;
import javax.servlet.annotation.WebServlet;
import javax.servlet.http.HttpServlet;
import javax.servlet.http.HttpServletRequest;
import javax.servlet.http.HttpServletResponse;
import org.json.simple.JSONObject;
import org.json.simple.parser.JSONParser;
import org.json.simple.parser.ParseException;
import pojo.User;
/**
*
* @author TrieuKhang
*/
@WebServlet(name = "ajax_register", urlPatterns = {"/ajax_register"})
public class ajax_register extends HttpServlet {
/**
* Processes requests for both HTTP
* <code>GET</code> and
* <code>POST</code> methods.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
protected void processRequest(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
PrintWriter out = response.getWriter();
try {
/*
* TODO output your page here. You may use following sample code.
*/
//init json obj response
JSONObject jObj_response = new JSONObject();
//init json parser
JSONParser jsonPaser = new JSONParser();
JSONObject jsonObj = new JSONObject();
try {
jsonObj = (JSONObject) jsonPaser.parse(request.getParameter("data"));
} catch (ParseException ex) {
Logger.getLogger(ajax_register.class.getName()).log(Level.SEVERE, null, ex);
}
response.setContentType("text/x-json; charset=UTF-8");
request.setCharacterEncoding("UTF-8");
String username = (String) jsonObj.get("username");
String pass = (String) jsonObj.get("password");
User user = new User();
user.setUsername(username);
user.setPassword(pass);
//get list user
boolean result = UserDAO.checkExists(user);
//có nghĩa là chưa có ai sử dụng username đó
if(result == false) {
UserDAO.addUser(user);
}
boolean register_result = !result;
jObj_response.put("result", register_result);
//tra json ra
out.println(jObj_response);
} finally {
out.close();
}
}
// <editor-fold defaultstate="collapsed" desc="HttpServlet methods. Click on the + sign on the left to edit the code.">
/**
* Handles the HTTP
* <code>GET</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doGet(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Handles the HTTP
* <code>POST</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doPost(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Returns a short description of the servlet.
*
* @return a String containing servlet description
*/
@Override
public String getServletInfo() {
return "Short description";
}// </editor-fold>
}
| 11hca1-java-web | trunk/src/java/controller/ajax_register.java | Java | gpl3 | 4,472 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import dao.MyQuery;
import dao.UserDAO;
import java.io.IOException;
import java.io.PrintWriter;
import java.util.List;
import javax.servlet.ServletException;
import javax.servlet.annotation.WebServlet;
import javax.servlet.http.HttpServlet;
import javax.servlet.http.HttpServletRequest;
import javax.servlet.http.HttpServletResponse;
import pojo.User;
/**
*
* @author 4pril
*/
@WebServlet(name = "test", urlPatterns = {"/test"})
public class test extends HttpServlet {
/**
* Processes requests for both HTTP
* <code>GET</code> and
* <code>POST</code> methods.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
protected void processRequest(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
response.setContentType("text/html;charset=UTF-8");
PrintWriter out = response.getWriter();
try {
/*
* TODO output your page here. You may use following sample code.
*/
out.println("fck");
List<User> ds = null;
try {
ds = (List<User>) (List<?>) UserDAO.getListUser("from User");
} catch (Exception e) {
out.println(e.toString());
}
//duyet tim thang trung
for (int i = 0; i < ds.size(); i++) {
// if(ds.get(i).getUsername().equals(user.getUsername()) && ds.get(i).getPassword().equals(user.getPassword())){
// return true;
// }
out.println(ds.get(i).getUsername());
}
User user = new User();
user.setUsername("trieukhang");
user.setPassword("123");
boolean result = UserDAO.login(user);
if(result)
out.println(result);
else
out.println("fck");
} finally {
out.close();
}
}
// <editor-fold defaultstate="collapsed" desc="HttpServlet methods. Click on the + sign on the left to edit the code.">
/**
* Handles the HTTP
* <code>GET</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doGet(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Handles the HTTP
* <code>POST</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doPost(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Returns a short description of the servlet.
*
* @return a String containing servlet description
*/
@Override
public String getServletInfo() {
return "Short description";
}// </editor-fold>
}
| 11hca1-java-web | trunk/src/java/controller/test.java | Java | gpl3 | 3,768 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import dao.MyQuery;
import dao.UserDAO;
import java.io.BufferedReader;
import java.io.IOException;
import java.io.OutputStreamWriter;
import java.io.PrintWriter;
import java.lang.reflect.Array;
import java.net.URLDecoder;
import java.util.ArrayList;
import java.util.List;
import java.util.logging.Level;
import java.util.logging.Logger;
import javax.servlet.ServletException;
import javax.servlet.annotation.WebServlet;
import javax.servlet.http.HttpServlet;
import javax.servlet.http.HttpServletRequest;
import javax.servlet.http.HttpServletResponse;
import javax.servlet.http.HttpSession;
import org.json.simple.JSONArray;
import pojo.User;
import org.json.simple.JSONObject;
import org.json.simple.JSONValue;
import org.json.simple.parser.JSONParser;
import org.json.simple.parser.ParseException;
/**
*
* @author TrieuKhang
*/
@WebServlet(name = "ajax_login", urlPatterns = {"/ajax_login"})
public class ajax_login extends HttpServlet {
/**
* Processes requests for both HTTP
* <code>GET</code> and
* <code>POST</code> methods.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
protected void processRequest(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
PrintWriter out = response.getWriter();
try {
/*
* TODO output your page here. You may use following sample code.
*/
JSONParser jP = new JSONParser();
JSONObject jO = new JSONObject();
try {
jO = (JSONObject) jP.parse(request.getParameter("data"));
//out.println("false");
} catch (ParseException ex) {
//Logger.getLogger(ajax_login.class.getName()).log(Level.SEVERE, null, ex);
out.println(ex.toString());
//return;
}
request.setCharacterEncoding("UTF-8");
response.setCharacterEncoding("UTF-8");
response.setContentType("text/x-json; charset=UTF-8");
String username = (String) jO.get("username");
String pass = (String) jO.get("password");
User user = new User();
user.setUsername(username);
user.setPassword(pass);
boolean result = false;
HttpSession session = request.getSession();
String redirectUrl = "";
result = UserDAO.login(user);
if(result){
session.setAttribute("isLogin", true);
session.setAttribute("currentUser", UserDAO.getLoginUser(user));
//redirect
redirectUrl = "index.jsp";
}
//init JSON
JSONObject new_jo = new JSONObject();
new_jo.put("result", result);
new_jo.put("user", user.getUsername());
new_jo.put("url", redirectUrl);
//new_jo.put("abc", username);
out.println(new_jo);
//neu ko co thi in ra false
//out.println("false");
}catch( Exception e){
out.println("lỗi " + e.toString());
}finally {
out.close();
}
}
// <editor-fold defaultstate="collapsed" desc="HttpServlet methods. Click on the + sign on the left to edit the code.">
/**
* Handles the HTTP
* <code>GET</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doGet(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Handles the HTTP
* <code>POST</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doPost(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Returns a short description of the servlet.
*
* @return a String containing servlet description
*/
@Override
public String getServletInfo() {
return "Short description";
}// </editor-fold>
private void splitat(char c) {
throw new UnsupportedOperationException("Not yet implemented");
}
}
| 11hca1-java-web | trunk/src/java/controller/ajax_login.java | Java | gpl3 | 5,364 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import system.System;
import java.io.IOException;
import java.io.PrintWriter;
import javax.servlet.RequestDispatcher;
import javax.servlet.ServletException;
import javax.servlet.annotation.WebServlet;
import javax.servlet.http.HttpServlet;
import javax.servlet.http.HttpServletRequest;
import javax.servlet.http.HttpServletResponse;
import javax.servlet.http.HttpSession;
import org.hibernate.dialect.RDMSOS2200Dialect;
/**
*
* @author 4pril
*/
@WebServlet(name = "index", urlPatterns = {"/index"})
public class index extends HttpServlet {
/**
* Processes requests for both HTTP
* <code>GET</code> and
* <code>POST</code> methods.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
protected void processRequest(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
response.setContentType("text/html;charset=UTF-8");
PrintWriter out = response.getWriter();
try {
/*
* TODO output your page here. You may use following sample code.
*/
HttpSession session = request.getSession();
out.println(System.getLogin_url());
//out.println(session.getAttribute("isLogin"));
//get isLogin
if(session.getAttribute("isLogin") == null){
RequestDispatcher rd = request.getRequestDispatcher(System.getLogin_url());
rd.forward(request, response);
}
//da login
session.getAttribute("currentUser");
RequestDispatcher toHomePage = request.getRequestDispatcher("index.jsp");
toHomePage.forward(request, response);
} finally {
out.close();
}
}
// <editor-fold defaultstate="collapsed" desc="HttpServlet methods. Click on the + sign on the left to edit the code.">
/**
* Handles the HTTP
* <code>GET</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doGet(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Handles the HTTP
* <code>POST</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doPost(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Returns a short description of the servlet.
*
* @return a String containing servlet description
*/
@Override
public String getServletInfo() {
return "Short description";
}// </editor-fold>
}
| 11hca1-java-web | trunk/src/java/controller/index.java | Java | gpl3 | 3,547 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package controller;
import system.System;
import java.io.IOException;
import java.io.PrintWriter;
import javax.servlet.RequestDispatcher;
import javax.servlet.ServletException;
import javax.servlet.annotation.WebServlet;
import javax.servlet.http.HttpServlet;
import javax.servlet.http.HttpServletRequest;
import javax.servlet.http.HttpServletResponse;
import javax.servlet.http.HttpSession;
/**
*
* @author 4pril
*/
@WebServlet(name = "login", urlPatterns = {"/login"})
public class login extends HttpServlet {
/**
* Processes requests for both HTTP
* <code>GET</code> and
* <code>POST</code> methods.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
protected void processRequest(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
response.setContentType("text/html;charset=UTF-8");
PrintWriter out = response.getWriter();
try {
/*
* TODO output your page here. You may use following sample code.
*/
HttpSession session = request.getSession();
if(session.getAttribute("isLogin") != null){
// RequestDispatcher rd = request.getRequestDispatcher("index.jsp");
// rd.forward(request, response);
response.sendRedirect("index.jsp");
return;
}
RequestDispatcher rd = request.getRequestDispatcher("login_page.jsp");
rd.forward(request, response);
} finally {
out.close();
}
}
// <editor-fold defaultstate="collapsed" desc="HttpServlet methods. Click on the + sign on the left to edit the code.">
/**
* Handles the HTTP
* <code>GET</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doGet(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Handles the HTTP
* <code>POST</code> method.
*
* @param request servlet request
* @param response servlet response
* @throws ServletException if a servlet-specific error occurs
* @throws IOException if an I/O error occurs
*/
@Override
protected void doPost(HttpServletRequest request, HttpServletResponse response)
throws ServletException, IOException {
processRequest(request, response);
}
/**
* Returns a short description of the servlet.
*
* @return a String containing servlet description
*/
@Override
public String getServletInfo() {
return "Short description";
}// </editor-fold>
}
| 11hca1-java-web | trunk/src/java/controller/login.java | Java | gpl3 | 3,375 |
/*
* To change this template, choose Tools | Templates
* and open the template in the editor.
*/
package util;
import org.hibernate.cfg.AnnotationConfiguration;
import org.hibernate.SessionFactory;
/**
* Hibernate Utility class with a convenient method to get Session Factory
* object.
*
* @author 4pril
*/
public class HibernateUtil {
private static final SessionFactory sessionFactory;
static {
try {
// Create the SessionFactory from standard (hibernate.cfg.xml)
// config file.
sessionFactory = new AnnotationConfiguration().configure().buildSessionFactory();
} catch (Throwable ex) {
// Log the exception.
System.err.println("Initial SessionFactory creation failed." + ex);
throw new ExceptionInInitializerError(ex);
}
}
public static SessionFactory getSessionFactory() {
return sessionFactory;
}
}
| 11hca1-java-web | trunk/src/java/util/HibernateUtil.java | Java | gpl3 | 986 |
package controller;
import java.awt.Graphics2D;
import java.awt.image.BufferedImage;
import java.io.BufferedOutputStream;
import java.io.File;
import java.io.FileOutputStream;
import java.io.IOException;
import java.text.SimpleDateFormat;
import java.util.Calendar;
import java.util.HashMap;
import java.util.List;
import java.util.Map;
import javax.imageio.ImageIO;
import model.Food;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.stereotype.Controller;
import org.springframework.web.bind.annotation.ModelAttribute;
import org.springframework.web.bind.annotation.RequestMapping;
import org.springframework.web.bind.annotation.RequestMethod;
import org.springframework.web.bind.annotation.RequestParam;
import org.springframework.web.multipart.MultipartFile;
import org.springframework.web.servlet.ModelAndView;
import dao.FoodDAO;
@Controller
public class FoodController {
private static final int IMG_WIDTH = 100;
private static final int IMG_HEIGHT = 100;
String url = "";
String rootPath = System.getProperty("user.dir");
@Autowired
private FoodDAO dao;
@RequestMapping(value = "/foodlist", method = RequestMethod.GET)
public ModelAndView foodList() {
List<Food> list = dao.getList();
Map<String, Object> model = new HashMap<String, Object>();
url = "foodlist";
model.put("list", list);
model.put("url", url);
return new ModelAndView("../../Homepage", model);
}
@RequestMapping(value = "/addfood", method = RequestMethod.POST)
public ModelAndView addFood(@ModelAttribute Food food) {
Map<String, Object> model = new HashMap<String, Object>();
url = "foodinfo";
if (food.getId()==0) {
String name = food.getName();
File dir = new File(rootPath + File.separator + "workspace"
+ File.separator + "CNPM" + File.separator + "WebContent"
+ File.separator + "resources" + File.separator + "image");
Food.makeQR(name, dir.getAbsolutePath() + File.separator + "qr" + name
+ ".jpg");
String filePath = "/resources/image/qr" + name + ".jpg";
food.setQr(filePath);
}
dao.saveOrUpdate(food);
model.put("url", url);
return new ModelAndView("../../Homepage", model);
}
@RequestMapping(value = "/displayaddfood", method = RequestMethod.GET)
public ModelAndView displayAddFood() {
Map<String, Object> model = new HashMap<String, Object>();
url = "displayaddfood";
model.put("url", url);
model.put("food", new Food());
return new ModelAndView("../../Homepage", model);
}
@RequestMapping(value = "/displayupload", method = RequestMethod.GET)
public String displayUpload() {
return "Upload";
}
@RequestMapping(value = "/upload", method = RequestMethod.POST)
public ModelAndView upload(@RequestParam("file") MultipartFile file) {
Map<String, Object> model = new HashMap<String, Object>();
String message = "";
if (!file.isEmpty()) {
try {
byte[] bytes = file.getBytes();
File dir = new File(rootPath + File.separator + "workspace"
+ File.separator + "CNPM" + File.separator
+ "WebContent" + File.separator + "resources"
+ File.separator + "image");
if (!dir.exists())
dir.mkdirs();
Calendar cal = Calendar.getInstance();
SimpleDateFormat sdf = new SimpleDateFormat("yyyyMMddHHmmss");
String name = sdf.format(cal.getTime());
File serverFile = new File(dir.getAbsolutePath()
+ File.separator + "img" + name + ".jpg");
BufferedOutputStream stream = new BufferedOutputStream(
new FileOutputStream(serverFile));
stream.write(bytes);
stream.close();
resizeIMG(serverFile);
String filePath = "/resources/image/img" + name + ".jpg";
model.put("filepath", filePath);
message = "You successfully uploaded file";
} catch (Exception e) {
message = "You failed to upload => " + e.getMessage();
}
} else {
message = "You failed to upload because the file was empty.";
}
model.put("message", message);
return new ModelAndView("Upload", model);
}
public static void resizeIMG(File file) {
try {
BufferedImage originalImage = ImageIO.read(file);
int type = originalImage.getType() == 0 ? BufferedImage.TYPE_INT_ARGB
: originalImage.getType();
BufferedImage resizeImageJpg = resizeImage(originalImage, type);
ImageIO.write(resizeImageJpg, "jpg",
new File(file.getAbsolutePath()));
} catch (IOException e) {
e.printStackTrace();
}
}
private static BufferedImage resizeImage(BufferedImage originalImage,
int type) {
BufferedImage resizedImage = new BufferedImage(IMG_WIDTH, IMG_HEIGHT,
type);
Graphics2D g = resizedImage.createGraphics();
g.drawImage(originalImage, 0, 0, IMG_WIDTH, IMG_HEIGHT, null);
g.dispose();
return resizedImage;
}
}
| 09130037-cnpm-pproject | DTCNPM/src/controller/FoodController.java | Java | asf20 | 4,876 |
<%@ page language="java" contentType="text/html; charset=ISO-8859-1"
pageEncoding="ISO-8859-1"%>
<%@ taglib uri="http://java.sun.com/jsp/jstl/core" prefix="c"%>
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>Insert title here</title>
<script type="text/javascript">
function done(){
var obj = window.dialogArguments;
obj.returnvalue = "${filepath}";
window.close();
}
</script>
</head>
<body>
<form method="POST" action="upload" enctype="multipart/form-data">
<br/>Image to upload: <input type="file" name="file"><br /> <input
type="submit" value="Upload"> Press here to upload the file!
<br/>
<c:if test="${message!=null}">
<c:out value="${message}"></c:out>
<c:if test="${filepath!=null}">
<img alt="" src="<%=request.getContextPath()%>${filepath}">
<button onclick="done()">Done</button>
</c:if>
</c:if>
</form>
</body>
</html> | 09130037-cnpm-pproject | DTCNPM/WebContent/WEB-INF/view/Upload.jsp | Java Server Pages | asf20 | 1,047 |
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="utf-8">
<title>Sign in · Twitter Bootstrap</title>
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<meta name="description" content="">
<meta name="author" content="">
<!-- Le styles -->
<link href="assets/css/bootstrap.css" rel="stylesheet">
<style type="text/css">
body {
padding-top: 40px;
padding-bottom: 40px;
background-color: #f5f5f5;
}
.form-signin {
max-width: 300px;
padding: 19px 29px 29px;
margin: 0 auto 20px;
background-color: #fff;
border: 1px solid #e5e5e5;
-webkit-border-radius: 5px;
-moz-border-radius: 5px;
border-radius: 5px;
-webkit-box-shadow: 0 1px 2px rgba(0,0,0,.05);
-moz-box-shadow: 0 1px 2px rgba(0,0,0,.05);
box-shadow: 0 1px 2px rgba(0,0,0,.05);
}
.form-signin .form-signin-heading,
.form-signin .checkbox {
margin-bottom: 10px;
}
.form-signin input[type="text"],
.form-signin input[type="password"] {
font-size: 16px;
height: auto;
margin-bottom: 15px;
padding: 7px 9px;
}
</style>
<link href="assets/css/bootstrap-responsive.css" rel="stylesheet">
<!-- HTML5 shim, for IE6-8 support of HTML5 elements -->
<!--[if lt IE 9]>
<script src="http://html5shim.googlecode.com/svn/trunk/html5.js"></script>
<![endif]-->
<!-- Fav and touch icons -->
<link rel="apple-touch-icon-precomposed" sizes="144x144" href="assets/ico/apple-touch-icon-144-precomposed.png">
<link rel="apple-touch-icon-precomposed" sizes="114x114" href="assets/ico/apple-touch-icon-114-precomposed.png">
<link rel="apple-touch-icon-precomposed" sizes="72x72" href="assets/ico/apple-touch-icon-72-precomposed.png">
<link rel="apple-touch-icon-precomposed" href="assets/ico/apple-touch-icon-57-precomposed.png">
<link rel="shortcut icon" href="assets/ico/favicon.png">
</head>
<body>
<div class="container">
<form class="form-signin">
<h2 class="form-signin-heading">Please sign in</h2>
<input type="text" class="input-block-level" placeholder="Email address">
<input type="password" class="input-block-level" placeholder="Password">
<label class="checkbox">
<input type="checkbox" value="remember-me"> Remember me
</label>
<button class="btn btn-block btn-primary" type="submit">Sign in</button>
<button class="btn btn-block btn-primary" type="submit">Sign up</button>
</form>
</div> <!-- /container -->
<!-- Le javascript
================================================== -->
<!-- Placed at the end of the document so the pages load faster -->
<script src="assets/js/jquery.js"></script>
<script src="assets/js/bootstrap-transition.js"></script>
<script src="assets/js/bootstrap-alert.js"></script>
<script src="assets/js/bootstrap-modal.js"></script>
<script src="assets/js/bootstrap-dropdown.js"></script>
<script src="assets/js/bootstrap-scrollspy.js"></script>
<script src="assets/js/bootstrap-tab.js"></script>
<script src="assets/js/bootstrap-tooltip.js"></script>
<script src="assets/js/bootstrap-popover.js"></script>
<script src="assets/js/bootstrap-button.js"></script>
<script src="assets/js/bootstrap-collapse.js"></script>
<script src="assets/js/bootstrap-carousel.js"></script>
<script src="assets/js/bootstrap-typeahead.js"></script>
</body>
</html>
| 069ka4-cms | trunk/signin.html | HTML | mit | 3,674 |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
<head>
<title>Ambition CMS</title>
<meta http-equiv="content-type" content="application/xhtml+xml; charset=UTF-8" />
<meta name="author" content="Erwin Aligam - styleshout.com" />
<meta name="description" content="Site Description Here" />
<meta name="keywords" content="keywords, here" />
<meta name="robots" content="index, follow, noarchive" />
<meta name="googlebot" content="noarchive" />
<link rel="stylesheet" type="text/css" media="screen" href="css/screen.css" />
</head>
<body>
<!-- wrap starts here -->
<div id="wrap">
<!--header -->
<div id="header">
<h1 id="logo-text"><a href="index.html" title="">Ambition CMS</a></h1>
<p id="slogan">Simple Content Management System</p>
<div id="nav">
<ul>
<li class="first" id="current"><a href="index.html">Home</a></li>
<li><a href="style.html">Style</a></li>
<li><a href="blog.html">Blog</a></li>
<li><a href="archives.html">Archives</a></li>
</ul>
</div>
<div id="header-image"></div>
<!--header ends-->
</div>
<!-- featured starts -->
<div id="featured" class="clear">
<a name="TemplateInfo"></a>
<div class="image-block">
<img src="images/img-featured.jpg" alt="featured"/>
</div>
<div class="text-block">
<h2><a href="index.html">Featured Post</a></h2>
<p class="post-info">Posted by <a href="index.html">erwin</a> | Filed under <a href="index.html">templates</a>, <a href="index.html">internet</a></p>
<p><strong>FreshPick</strong> is a free, W3C-compliant, CSS-based website template
by <a href="http://www.styleshout.com/">styleshout.com</a>. This work is
distributed under the <a rel="license" href="http://creativecommons.org/licenses/by/2.5/">
Creative Commons Attribution 2.5 License</a>, which means that you are free to
use and modify it for any purpose. All I ask is that you give me credit by including a <strong>link back</strong> to
<a href="http://www.styleshout.com/">my website</a>.
</p>
<p>
You can find more of my free template designs at <a href="http://www.styleshout.com/">my website</a>.
For premium commercial designs, you can check out
<a href="http://www.dreamtemplate.com" title="Website Templates">DreamTemplate.com</a>.
</p>
<p><a href="index.html" class="more-link">Read More</a></p>
</div>
<!-- featured ends -->
</div>
<!-- content -->
<div id="content-outer" class="clear"><div id="content-wrap">
<div id="content">
<div id="left">
<div class="entry">
<h3><a href="index.html">Aliquam Risus Justo</a></h3>
<p>
Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo. Donec mattis, purus nec placerat bibendum, dui pede condimentum
odio, ac blandit ante orci ut diam. Cras fringilla magna. Phasellus suscipit, leo a pharetra
condimentum, lorem tellus eleifend magna, eget fringilla velit magna id neque. Curabitur vel urna.
In tristique orci porttitor ipsum. Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo.
</p>
<p><a class="more-link" href="index.html">continue reading</a></p>
</div>
<div class="entry">
<h3>Lorem Ipsum Dolor Sit Amet</h3>
<p>
Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo. Donec mattis, purus nec placerat bibendum, dui pede condimentum
odio, ac blandit ante orci ut diam. Cras fringilla magna. Phasellus suscipit, leo a pharetra
condimentum, lorem tellus eleifend magna, eget fringilla velit magna id neque. Curabitur vel urna.
In tristique orci porttitor ipsum. Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo.
</p>
<p><a class="more-link" href="index.html">continue reading</a></p>
</div>
<div class="entry">
<h3>Lorem Ipsum</h3>
<p>
Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo. Donec mattis, purus nec placerat bibendum, dui pede condimentum
odio, ac blandit ante orci ut diam. Cras fringilla magna. Phasellus suscipit, leo a pharetra
condimentum, lorem tellus eleifend magna, eget fringilla velit magna id neque. Curabitur vel urna.
In tristique orci porttitor ipsum. Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo.
</p>
<p><a class="more-link" href="index.html">continue reading</a></p>
</div>
</div>
<div id="right">
<h3>Search</h3>
<form id="quick-search" action="index.html" method="get" >
<p>
<label for="qsearch">Search:</label>
<input class="tbox" id="qsearch" type="text" name="qsearch" value="type and hit enter..." title="Start typing and hit ENTER" />
<input class="btn" alt="Search" type="image" name="searchsubmit" title="Search" src="images/search.gif" />
</p>
</form>
<div class="sidemenu">
<h3>Sidebar Menu</h3>
<ul>
<li><a href="index.html">Home</a></li>
<li><a href="index.html#TemplateInfo">TemplateInfo</a></li>
<li><a href="style.html">Style Demo</a></li>
<li><a href="blog.html">Blog</a></li>
<li><a href="archives.html">Archives</a></li>
<li><a href="http://www.dreamtemplate.com" title="Web Templates">Web Templates</a></li>
</ul>
</div>
<div class="sidemenu">
<h3>Sponsors</h3>
<ul>
<li><a href="http://www.dreamtemplate.com" title="Website Templates">DreamTemplate <br />
<span>Over 6,000+ Premium Web Templates</span></a>
</li>
<li><a href="http://www.themelayouts.com" title="WordPress Themes">ThemeLayouts <br />
<span>Premium WordPress & Joomla Themes</span></a>
</li>
<li><a href="http://www.imhosted.com" title="Website Hosting">ImHosted.com <br />
<span>Affordable Web Hosting Provider</span></a>
</li>
<li><a href="http://www.dreamstock.com" title="Stock Photos">DreamStock <br />
<span>Download Amazing Stock Photos</span></a>
</li>
<li><a href="http://www.evrsoft.com" title="Website Builder">Evrsoft <br />
<span>Website Builder Software & Tools</span></a>
</li>
<li><a href="http://www.webhostingwp.com" title="Web Hosting">Web Hosting <br />
<span>Top 10 Hosting Reviews</span></a>
</li>
</ul>
</div>
</div>
</div>
<!-- content end -->
</div></div>
<!-- footer starts here -->
<div id="footer-outer" class="clear"><div id="footer-wrap">
<div class="col-a">
<h3>Image Gallery </h3>
<p class="thumbs">
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
<a href="index.html"><img src="images/thumb.jpg" width="40" height="40" alt="thumbnail" /></a>
</p>
</div>
<div class="col-a">
<h3>Lorem Ipsum</h3>
<p>
<strong>Lorem ipsum dolor</strong> <br />
Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo. Donec mattis, purus nec placerat bibendum, dui pede condimentum
odio, ac blandit ante orci ut diam.</p>
</div>
<div class="col-b">
<h3>About</h3>
<p>
<a href="index.html"><img src="images/gravatar.jpg" width="40" height="40" alt="firefox" class="float-left" /></a>
Lorem ipsum dolor sit amet, consectetuer adipiscing elit. Donec libero. Suspendisse bibendum.
Cras id urna. Morbi tincidunt, orci ac convallis aliquam, lectus turpis varius lorem, eu
posuere nunc justo tempus leo. Donec mattis, purus nec placerat bibendum, dui pede condimentum
odio, ac blandit ante orci ut diam.</p>
</div>
<!-- footer ends -->
</div></div>
<!-- footer-bottom starts -->
<div id="footer-bottom">
<div class="bottom-left">
<p>
© 2010 <strong>Your Copyright Info Here</strong>
<a href="http://www.bluewebtemplates.com/" title="Website Templates">website templates</a> by <a href="http://www.styleshout.com/">styleshout</a>
</p>
</div>
<div class="bottom-right">
<p>
<a href="http://jigsaw.w3.org/css-validator/check/referer">CSS</a> |
<a href="http://validator.w3.org/check/referer">XHTML</a> |
<a href="index.html">Home</a> |
<a href="index.html">Sitemap</a> |
<a href="index.html">RSS Feed</a>
</p>
</div>
<!-- footer-bottom ends -->
</div>
<!-- wrap ends here -->
</div>
</body>
</html>
| 069ka4-cms | trunk/main.html | HTML | mit | 11,023 |
.com { color: #93a1a1; }
.lit { color: #195f91; }
.pun, .opn, .clo { color: #93a1a1; }
.fun { color: #dc322f; }
.str, .atv { color: #D14; }
.kwd, .prettyprint .tag { color: #1e347b; }
.typ, .atn, .dec, .var { color: teal; }
.pln { color: #48484c; }
.prettyprint {
padding: 8px;
background-color: #f7f7f9;
border: 1px solid #e1e1e8;
}
.prettyprint.linenums {
-webkit-box-shadow: inset 40px 0 0 #fbfbfc, inset 41px 0 0 #ececf0;
-moz-box-shadow: inset 40px 0 0 #fbfbfc, inset 41px 0 0 #ececf0;
box-shadow: inset 40px 0 0 #fbfbfc, inset 41px 0 0 #ececf0;
}
/* Specify class=linenums on a pre to get line numbering */
ol.linenums {
margin: 0 0 0 33px; /* IE indents via margin-left */
}
ol.linenums li {
padding-left: 12px;
color: #bebec5;
line-height: 20px;
text-shadow: 0 1px 0 #fff;
} | 069ka4-cms | trunk/assets/js/google-code-prettify/prettify.css | CSS | mit | 817 |
/*
Holder - 1.6 - client side image placeholders
(c) 2012 Ivan Malopinsky / http://imsky.co
Provided under the Apache 2.0 License: http://www.apache.org/licenses/LICENSE-2.0
Commercial use requires attribution.
*/
var Holder = Holder || {};
(function (app, win) {
var preempted = false,
fallback = false,
canvas = document.createElement('canvas');
//getElementsByClassName polyfill
document.getElementsByClassName||(document.getElementsByClassName=function(e){var t=document,n,r,i,s=[];if(t.querySelectorAll)return t.querySelectorAll("."+e);if(t.evaluate){r=".//*[contains(concat(' ', @class, ' '), ' "+e+" ')]",n=t.evaluate(r,t,null,0,null);while(i=n.iterateNext())s.push(i)}else{n=t.getElementsByTagName("*"),r=new RegExp("(^|\\s)"+e+"(\\s|$)");for(i=0;i<n.length;i++)r.test(n[i].className)&&s.push(n[i])}return s})
//getComputedStyle polyfill
window.getComputedStyle||(window.getComputedStyle=function(e,t){return this.el=e,this.getPropertyValue=function(t){var n=/(\-([a-z]){1})/g;return t=="float"&&(t="styleFloat"),n.test(t)&&(t=t.replace(n,function(){return arguments[2].toUpperCase()})),e.currentStyle[t]?e.currentStyle[t]:null},this})
//http://javascript.nwbox.com/ContentLoaded by Diego Perini with modifications
function contentLoaded(n,t){var l="complete",s="readystatechange",u=!1,h=u,c=!0,i=n.document,a=i.documentElement,e=i.addEventListener?"addEventListener":"attachEvent",v=i.addEventListener?"removeEventListener":"detachEvent",f=i.addEventListener?"":"on",r=function(e){(e.type!=s||i.readyState==l)&&((e.type=="load"?n:i)[v](f+e.type,r,u),!h&&(h=!0)&&t.call(n,null))},o=function(){try{a.doScroll("left")}catch(n){setTimeout(o,50);return}r("poll")};if(i.readyState==l)t.call(n,"lazy");else{if(i.createEventObject&&a.doScroll){try{c=!n.frameElement}catch(y){}c&&o()}i[e](f+"DOMContentLoaded",r,u),i[e](f+s,r,u),n[e](f+"load",r,u)}};
//https://gist.github.com/991057 by Jed Schmidt with modifications
function selector(a){
a=a.match(/^(\W)?(.*)/);var b=document["getElement"+(a[1]?a[1]=="#"?"ById":"sByClassName":"sByTagName")](a[2]);
var ret=[]; b!=null&&(b.length?ret=b:b.length==0?ret=b:ret=[b]); return ret;
}
//shallow object property extend
function extend(a,b){var c={};for(var d in a)c[d]=a[d];for(var e in b)c[e]=b[e];return c}
function text_size(width, height, template) {
var dimension_arr = [height, width].sort();
var maxFactor = Math.round(dimension_arr[1] / 16),
minFactor = Math.round(dimension_arr[0] / 16);
var text_height = Math.max(template.size, maxFactor);
return {
height: text_height
}
}
function draw(ctx, dimensions, template, ratio) {
var ts = text_size(dimensions.width, dimensions.height, template);
var text_height = ts.height;
var width = dimensions.width * ratio, height = dimensions.height * ratio;
canvas.width = width;
canvas.height = height;
ctx.textAlign = "center";
ctx.textBaseline = "middle";
ctx.fillStyle = template.background;
ctx.fillRect(0, 0, width, height);
ctx.fillStyle = template.foreground;
ctx.font = "bold " + text_height + "px sans-serif";
var text = template.text ? template.text : (dimensions.width + "x" + dimensions.height);
if (ctx.measureText(text).width / width > 1) {
text_height = template.size / (ctx.measureText(text).width / width);
}
ctx.font = "bold " + (text_height * ratio) + "px sans-serif";
ctx.fillText(text, (width / 2), (height / 2), width);
return canvas.toDataURL("image/png");
}
function render(mode, el, holder, src) {
var dimensions = holder.dimensions,
theme = holder.theme,
text = holder.text;
var dimensions_caption = dimensions.width + "x" + dimensions.height;
theme = (text ? extend(theme, {
text: text
}) : theme);
var ratio = 1;
if(window.devicePixelRatio && window.devicePixelRatio > 1){
ratio = window.devicePixelRatio;
}
if (mode == "image") {
el.setAttribute("data-src", src);
el.setAttribute("alt", text ? text : theme.text ? theme.text + " [" + dimensions_caption + "]" : dimensions_caption);
el.style.width = dimensions.width + "px";
el.style.height = dimensions.height + "px";
if (fallback) {
el.style.backgroundColor = theme.background;
}
else{
el.setAttribute("src", draw(ctx, dimensions, theme, ratio));
}
} else {
if (!fallback) {
el.style.backgroundImage = "url(" + draw(ctx, dimensions, theme, ratio) + ")";
el.style.backgroundSize = dimensions.width+"px "+dimensions.height+"px";
}
}
};
function fluid(el, holder, src) {
var dimensions = holder.dimensions,
theme = holder.theme,
text = holder.text;
var dimensions_caption = dimensions.width + "x" + dimensions.height;
theme = (text ? extend(theme, {
text: text
}) : theme);
var fluid = document.createElement("table");
fluid.setAttribute("cellspacing",0)
fluid.setAttribute("cellpadding",0)
fluid.setAttribute("border",0)
var row = document.createElement("tr")
.appendChild(document.createElement("td")
.appendChild(document.createTextNode(theme.text)));
fluid.style.backgroundColor = theme.background;
fluid.style.color = theme.foreground;
fluid.className = el.className + " holderjs-fluid";
fluid.style.width = holder.dimensions.width + (holder.dimensions.width.indexOf("%")>0?"":"px");
fluid.style.height = holder.dimensions.height + (holder.dimensions.height.indexOf("%")>0?"":"px");
fluid.id = el.id;
var frag = document.createDocumentFragment(),
tbody = document.createElement("tbody"),
tr = document.createElement("tr"),
td = document.createElement("td");
tr.appendChild(td);
tbody.appendChild(tr);
frag.appendChild(tbody);
if (theme.text) {
td.appendChild(document.createTextNode(theme.text))
fluid.appendChild(frag);
} else {
td.appendChild(document.createTextNode(dimensions_caption))
fluid.appendChild(frag);
fluid_images.push(fluid);
setTimeout(fluid_update, 0);
}
el.parentNode.replaceChild(fluid, el);
}
function fluid_update() {
for (i in fluid_images) {
var el = fluid_images[i];
var label = el.getElementsByTagName("td")[0].firstChild;
label.data = el.offsetWidth + "x" + el.offsetHeight;
}
}
function parse_flags(flags, options) {
var ret = {
theme: settings.themes.gray
}, render = false;
for (sl = flags.length, j = 0; j < sl; j++) {
var flag = flags[j];
if (app.flags.dimensions.match(flag)) {
render = true;
ret.dimensions = app.flags.dimensions.output(flag);
} else if (app.flags.fluid.match(flag)) {
render = true;
ret.dimensions = app.flags.fluid.output(flag);
ret.fluid = true;
} else if (app.flags.colors.match(flag)) {
ret.theme = app.flags.colors.output(flag);
} else if (options.themes[flag]) {
//If a theme is specified, it will override custom colors
ret.theme = options.themes[flag];
} else if (app.flags.text.match(flag)) {
ret.text = app.flags.text.output(flag);
}
}
return render ? ret : false;
};
if (!canvas.getContext) {
fallback = true;
} else {
if (canvas.toDataURL("image/png")
.indexOf("data:image/png") < 0) {
//Android doesn't support data URI
fallback = true;
} else {
var ctx = canvas.getContext("2d");
}
}
var fluid_images = [];
var settings = {
domain: "holder.js",
images: "img",
elements: ".holderjs",
themes: {
"gray": {
background: "#eee",
foreground: "#aaa",
size: 12
},
"social": {
background: "#3a5a97",
foreground: "#fff",
size: 12
},
"industrial": {
background: "#434A52",
foreground: "#C2F200",
size: 12
}
},
stylesheet: ".holderjs-fluid {font-size:16px;font-weight:bold;text-align:center;font-family:sans-serif;border-collapse:collapse;border:0;vertical-align:middle;margin:0}"
};
app.flags = {
dimensions: {
regex: /(\d+)x(\d+)/,
output: function (val) {
var exec = this.regex.exec(val);
return {
width: +exec[1],
height: +exec[2]
}
}
},
fluid: {
regex: /([0-9%]+)x([0-9%]+)/,
output: function (val) {
var exec = this.regex.exec(val);
return {
width: exec[1],
height: exec[2]
}
}
},
colors: {
regex: /#([0-9a-f]{3,})\:#([0-9a-f]{3,})/i,
output: function (val) {
var exec = this.regex.exec(val);
return {
size: settings.themes.gray.size,
foreground: "#" + exec[2],
background: "#" + exec[1]
}
}
},
text: {
regex: /text\:(.*)/,
output: function (val) {
return this.regex.exec(val)[1];
}
}
}
for (var flag in app.flags) {
app.flags[flag].match = function (val) {
return val.match(this.regex)
}
}
app.add_theme = function (name, theme) {
name != null && theme != null && (settings.themes[name] = theme);
return app;
};
app.add_image = function (src, el) {
var node = selector(el);
if (node.length) {
for (var i = 0, l = node.length; i < l; i++) {
var img = document.createElement("img")
img.setAttribute("data-src", src);
node[i].appendChild(img);
}
}
return app;
};
app.run = function (o) {
var options = extend(settings, o),
images_nodes = selector(options.images),
elements = selector(options.elements),
preempted = true,
images = [];
for (i = 0, l = images_nodes.length; i < l; i++) images.push(images_nodes[i]);
var holdercss = document.createElement("style");
holdercss.type = "text/css";
holdercss.styleSheet ? holdercss.styleSheet.cssText = options.stylesheet : holdercss.textContent = options.stylesheet;
document.getElementsByTagName("head")[0].appendChild(holdercss);
var cssregex = new RegExp(options.domain + "\/(.*?)\"?\\)");
for (var l = elements.length, i = 0; i < l; i++) {
var src = window.getComputedStyle(elements[i], null)
.getPropertyValue("background-image");
var flags = src.match(cssregex);
if (flags) {
var holder = parse_flags(flags[1].split("/"), options);
if (holder) {
render("background", elements[i], holder, src);
}
}
}
for (var l = images.length, i = 0; i < l; i++) {
var src = images[i].getAttribute("src") || images[i].getAttribute("data-src");
if (src != null && src.indexOf(options.domain) >= 0) {
var holder = parse_flags(src.substr(src.lastIndexOf(options.domain) + options.domain.length + 1)
.split("/"), options);
if (holder) {
if (holder.fluid) {
fluid(images[i], holder, src);
} else {
render("image", images[i], holder, src);
}
}
}
}
return app;
};
contentLoaded(win, function () {
if (window.addEventListener) {
window.addEventListener("resize", fluid_update, false);
window.addEventListener("orientationchange", fluid_update, false);
} else {
window.attachEvent("onresize", fluid_update)
}
preempted || app.run();
});
})(Holder, window);
| 069ka4-cms | trunk/assets/js/holder/holder.js | JavaScript | mit | 10,517 |
// NOTICE!! DO NOT USE ANY OF THIS JAVASCRIPT
// IT'S ALL JUST JUNK FOR OUR DOCS!
// ++++++++++++++++++++++++++++++++++++++++++
!function ($) {
$(function(){
var $window = $(window)
// Disable certain links in docs
$('section [href^=#]').click(function (e) {
e.preventDefault()
})
// side bar
$('.bs-docs-sidenav').affix({
offset: {
top: function () { return $window.width() <= 980 ? 290 : 210 }
, bottom: 270
}
})
// make code pretty
window.prettyPrint && prettyPrint()
// add-ons
$('.add-on :checkbox').on('click', function () {
var $this = $(this)
, method = $this.attr('checked') ? 'addClass' : 'removeClass'
$(this).parents('.add-on')[method]('active')
})
// add tipsies to grid for scaffolding
if ($('#gridSystem').length) {
$('#gridSystem').tooltip({
selector: '.show-grid > div'
, title: function () { return $(this).width() + 'px' }
})
}
// tooltip demo
$('.tooltip-demo').tooltip({
selector: "a[rel=tooltip]"
})
$('.tooltip-test').tooltip()
$('.popover-test').popover()
// popover demo
$("a[rel=popover]")
.popover()
.click(function(e) {
e.preventDefault()
})
// button state demo
$('#fat-btn')
.click(function () {
var btn = $(this)
btn.button('loading')
setTimeout(function () {
btn.button('reset')
}, 3000)
})
// carousel demo
$('#myCarousel').carousel()
// javascript build logic
var inputsComponent = $("#components.download input")
, inputsPlugin = $("#plugins.download input")
, inputsVariables = $("#variables.download input")
// toggle all plugin checkboxes
$('#components.download .toggle-all').on('click', function (e) {
e.preventDefault()
inputsComponent.attr('checked', !inputsComponent.is(':checked'))
})
$('#plugins.download .toggle-all').on('click', function (e) {
e.preventDefault()
inputsPlugin.attr('checked', !inputsPlugin.is(':checked'))
})
$('#variables.download .toggle-all').on('click', function (e) {
e.preventDefault()
inputsVariables.val('')
})
// request built javascript
$('.download-btn .btn').on('click', function () {
var css = $("#components.download input:checked")
.map(function () { return this.value })
.toArray()
, js = $("#plugins.download input:checked")
.map(function () { return this.value })
.toArray()
, vars = {}
, img = ['glyphicons-halflings.png', 'glyphicons-halflings-white.png']
$("#variables.download input")
.each(function () {
$(this).val() && (vars[ $(this).prev().text() ] = $(this).val())
})
$.ajax({
type: 'POST'
, url: /\?dev/.test(window.location) ? 'http://localhost:3000' : 'http://bootstrap.herokuapp.com'
, dataType: 'jsonpi'
, params: {
js: js
, css: css
, vars: vars
, img: img
}
})
})
})
// Modified from the original jsonpi https://github.com/benvinegar/jquery-jsonpi
$.ajaxTransport('jsonpi', function(opts, originalOptions, jqXHR) {
var url = opts.url;
return {
send: function(_, completeCallback) {
var name = 'jQuery_iframe_' + jQuery.now()
, iframe, form
iframe = $('<iframe>')
.attr('name', name)
.appendTo('head')
form = $('<form>')
.attr('method', opts.type) // GET or POST
.attr('action', url)
.attr('target', name)
$.each(opts.params, function(k, v) {
$('<input>')
.attr('type', 'hidden')
.attr('name', k)
.attr('value', typeof v == 'string' ? v : JSON.stringify(v))
.appendTo(form)
})
form.appendTo('body').submit()
}
}
})
}(window.jQuery) | 069ka4-cms | trunk/assets/js/application.js | JavaScript | mit | 3,954 |
/* Add additional stylesheets below
-------------------------------------------------- */
/*
Bootstrap's documentation styles
Special styles for presenting Bootstrap's documentation and examples
*/
/* Body and structure
-------------------------------------------------- */
body {
position: relative;
padding-top: 40px;
}
/* Code in headings */
h3 code {
font-size: 14px;
font-weight: normal;
}
/* Tweak navbar brand link to be super sleek
-------------------------------------------------- */
body > .navbar {
font-size: 13px;
}
/* Change the docs' brand */
body > .navbar .brand {
padding-right: 0;
padding-left: 0;
margin-left: 20px;
float: right;
font-weight: bold;
color: #000;
text-shadow: 0 1px 0 rgba(255,255,255,.1), 0 0 30px rgba(255,255,255,.125);
-webkit-transition: all .2s linear;
-moz-transition: all .2s linear;
transition: all .2s linear;
}
body > .navbar .brand:hover {
text-decoration: none;
text-shadow: 0 1px 0 rgba(255,255,255,.1), 0 0 30px rgba(255,255,255,.4);
}
/* Sections
-------------------------------------------------- */
/* padding for in-page bookmarks and fixed navbar */
section {
padding-top: 30px;
}
section > .page-header,
section > .lead {
color: #5a5a5a;
}
section > ul li {
margin-bottom: 5px;
}
/* Separators (hr) */
.bs-docs-separator {
margin: 40px 0 39px;
}
/* Faded out hr */
hr.soften {
height: 1px;
margin: 70px 0;
background-image: -webkit-linear-gradient(left, rgba(0,0,0,0), rgba(0,0,0,.1), rgba(0,0,0,0));
background-image: -moz-linear-gradient(left, rgba(0,0,0,0), rgba(0,0,0,.1), rgba(0,0,0,0));
background-image: -ms-linear-gradient(left, rgba(0,0,0,0), rgba(0,0,0,.1), rgba(0,0,0,0));
background-image: -o-linear-gradient(left, rgba(0,0,0,0), rgba(0,0,0,.1), rgba(0,0,0,0));
border: 0;
}
/* Jumbotrons
-------------------------------------------------- */
/* Base class
------------------------- */
.jumbotron {
position: relative;
padding: 40px 0;
color: #fff;
text-align: center;
text-shadow: 0 1px 3px rgba(0,0,0,.4), 0 0 30px rgba(0,0,0,.075);
background: #020031; /* Old browsers */
background: -moz-linear-gradient(45deg, #020031 0%, #6d3353 100%); /* FF3.6+ */
background: -webkit-gradient(linear, left bottom, right top, color-stop(0%,#020031), color-stop(100%,#6d3353)); /* Chrome,Safari4+ */
background: -webkit-linear-gradient(45deg, #020031 0%,#6d3353 100%); /* Chrome10+,Safari5.1+ */
background: -o-linear-gradient(45deg, #020031 0%,#6d3353 100%); /* Opera 11.10+ */
background: -ms-linear-gradient(45deg, #020031 0%,#6d3353 100%); /* IE10+ */
background: linear-gradient(45deg, #020031 0%,#6d3353 100%); /* W3C */
filter: progid:DXImageTransform.Microsoft.gradient( startColorstr='#020031', endColorstr='#6d3353',GradientType=1 ); /* IE6-9 fallback on horizontal gradient */
-webkit-box-shadow: inset 0 3px 7px rgba(0,0,0,.2), inset 0 -3px 7px rgba(0,0,0,.2);
-moz-box-shadow: inset 0 3px 7px rgba(0,0,0,.2), inset 0 -3px 7px rgba(0,0,0,.2);
box-shadow: inset 0 3px 7px rgba(0,0,0,.2), inset 0 -3px 7px rgba(0,0,0,.2);
}
.jumbotron h1 {
font-size: 80px;
font-weight: bold;
letter-spacing: -1px;
line-height: 1;
}
.jumbotron p {
font-size: 24px;
font-weight: 300;
line-height: 1.25;
margin-bottom: 30px;
}
/* Link styles (used on .masthead-links as well) */
.jumbotron a {
color: #fff;
color: rgba(255,255,255,.5);
-webkit-transition: all .2s ease-in-out;
-moz-transition: all .2s ease-in-out;
transition: all .2s ease-in-out;
}
.jumbotron a:hover {
color: #fff;
text-shadow: 0 0 10px rgba(255,255,255,.25);
}
/* Download button */
.masthead .btn {
padding: 19px 24px;
font-size: 24px;
font-weight: 200;
color: #fff; /* redeclare to override the `.jumbotron a` */
border: 0;
-webkit-border-radius: 6px;
-moz-border-radius: 6px;
border-radius: 6px;
-webkit-box-shadow: inset 0 1px 0 rgba(255,255,255,.1), 0 1px 5px rgba(0,0,0,.25);
-moz-box-shadow: inset 0 1px 0 rgba(255,255,255,.1), 0 1px 5px rgba(0,0,0,.25);
box-shadow: inset 0 1px 0 rgba(255,255,255,.1), 0 1px 5px rgba(0,0,0,.25);
-webkit-transition: none;
-moz-transition: none;
transition: none;
}
.masthead .btn:hover {
-webkit-box-shadow: inset 0 1px 0 rgba(255,255,255,.1), 0 1px 5px rgba(0,0,0,.25);
-moz-box-shadow: inset 0 1px 0 rgba(255,255,255,.1), 0 1px 5px rgba(0,0,0,.25);
box-shadow: inset 0 1px 0 rgba(255,255,255,.1), 0 1px 5px rgba(0,0,0,.25);
}
.masthead .btn:active {
-webkit-box-shadow: inset 0 2px 4px rgba(0,0,0,.1), 0 1px 0 rgba(255,255,255,.1);
-moz-box-shadow: inset 0 2px 4px rgba(0,0,0,.1), 0 1px 0 rgba(255,255,255,.1);
box-shadow: inset 0 2px 4px rgba(0,0,0,.1), 0 1px 0 rgba(255,255,255,.1);
}
/* Pattern overlay
------------------------- */
.jumbotron .container {
position: relative;
z-index: 2;
}
.jumbotron:after {
content: '';
display: block;
position: absolute;
top: 0;
right: 0;
bottom: 0;
left: 0;
background: url(../img/bs-docs-masthead-pattern.png) repeat center center;
opacity: .4;
}
@media
only screen and (-webkit-min-device-pixel-ratio: 2),
only screen and ( min--moz-device-pixel-ratio: 2),
only screen and ( -o-min-device-pixel-ratio: 2/1) {
.jumbotron:after {
background-size: 150px 150px;
}
}
/* Masthead (docs home)
------------------------- */
.masthead {
padding: 70px 0 80px;
margin-bottom: 0;
color: #fff;
}
.masthead h1 {
font-size: 120px;
line-height: 1;
letter-spacing: -2px;
}
.masthead p {
font-size: 40px;
font-weight: 200;
line-height: 1.25;
}
/* Textual links in masthead */
.masthead-links {
margin: 0;
list-style: none;
}
.masthead-links li {
display: inline;
padding: 0 10px;
color: rgba(255,255,255,.25);
}
/* Social proof buttons from GitHub & Twitter */
.bs-docs-social {
padding: 15px 0;
text-align: center;
background-color: #f5f5f5;
border-top: 1px solid #fff;
border-bottom: 1px solid #ddd;
}
/* Quick links on Home */
.bs-docs-social-buttons {
margin-left: 0;
margin-bottom: 0;
padding-left: 0;
list-style: none;
}
.bs-docs-social-buttons li {
display: inline-block;
padding: 5px 8px;
line-height: 1;
*display: inline;
*zoom: 1;
}
/* Subhead (other pages)
------------------------- */
.subhead {
text-align: left;
border-bottom: 1px solid #ddd;
}
.subhead h1 {
font-size: 60px;
}
.subhead p {
margin-bottom: 20px;
}
.subhead .navbar {
display: none;
}
/* Marketing section of Overview
-------------------------------------------------- */
.marketing {
text-align: center;
color: #5a5a5a;
}
.marketing h1 {
margin: 60px 0 10px;
font-size: 60px;
font-weight: 200;
line-height: 1;
letter-spacing: -1px;
}
.marketing h2 {
font-weight: 200;
margin-bottom: 5px;
}
.marketing p {
font-size: 16px;
line-height: 1.5;
}
.marketing .marketing-byline {
margin-bottom: 40px;
font-size: 20px;
font-weight: 300;
line-height: 1.25;
color: #999;
}
.marketing-img {
display: block;
margin: 0 auto 30px;
max-height: 145px;
}
/* Footer
-------------------------------------------------- */
.footer {
text-align: center;
padding: 30px 0;
margin-top: 70px;
border-top: 1px solid #e5e5e5;
background-color: #f5f5f5;
}
.footer p {
margin-bottom: 0;
color: #777;
}
.footer-links {
margin: 10px 0;
}
.footer-links li {
display: inline;
padding: 0 2px;
}
.footer-links li:first-child {
padding-left: 0;
}
/* Special grid styles
-------------------------------------------------- */
.show-grid {
margin-top: 10px;
margin-bottom: 20px;
}
.show-grid [class*="span"] {
background-color: #eee;
text-align: center;
-webkit-border-radius: 3px;
-moz-border-radius: 3px;
border-radius: 3px;
min-height: 40px;
line-height: 40px;
}
.show-grid:hover [class*="span"] {
background: #ddd;
}
.show-grid .show-grid {
margin-top: 0;
margin-bottom: 0;
}
.show-grid .show-grid [class*="span"] {
margin-top: 5px;
}
.show-grid [class*="span"] [class*="span"] {
background-color: #ccc;
}
.show-grid [class*="span"] [class*="span"] [class*="span"] {
background-color: #999;
}
/* Mini layout previews
-------------------------------------------------- */
.mini-layout {
border: 1px solid #ddd;
-webkit-border-radius: 6px;
-moz-border-radius: 6px;
border-radius: 6px;
-webkit-box-shadow: 0 1px 2px rgba(0,0,0,.075);
-moz-box-shadow: 0 1px 2px rgba(0,0,0,.075);
box-shadow: 0 1px 2px rgba(0,0,0,.075);
}
.mini-layout,
.mini-layout .mini-layout-body,
.mini-layout.fluid .mini-layout-sidebar {
height: 300px;
}
.mini-layout {
margin-bottom: 20px;
padding: 9px;
}
.mini-layout div {
-webkit-border-radius: 3px;
-moz-border-radius: 3px;
border-radius: 3px;
}
.mini-layout .mini-layout-body {
background-color: #dceaf4;
margin: 0 auto;
width: 70%;
}
.mini-layout.fluid .mini-layout-sidebar,
.mini-layout.fluid .mini-layout-header,
.mini-layout.fluid .mini-layout-body {
float: left;
}
.mini-layout.fluid .mini-layout-sidebar {
background-color: #bbd8e9;
width: 20%;
}
.mini-layout.fluid .mini-layout-body {
width: 77.5%;
margin-left: 2.5%;
}
/* Download page
-------------------------------------------------- */
.download .page-header {
margin-top: 36px;
}
.page-header .toggle-all {
margin-top: 5px;
}
/* Space out h3s when following a section */
.download h3 {
margin-bottom: 5px;
}
.download-builder input + h3,
.download-builder .checkbox + h3 {
margin-top: 9px;
}
/* Fields for variables */
.download-builder input[type=text] {
margin-bottom: 9px;
font-family: Menlo, Monaco, "Courier New", monospace;
font-size: 12px;
color: #d14;
}
.download-builder input[type=text]:focus {
background-color: #fff;
}
/* Custom, larger checkbox labels */
.download .checkbox {
padding: 6px 10px 6px 25px;
font-size: 13px;
line-height: 18px;
color: #555;
background-color: #f9f9f9;
-webkit-border-radius: 3px;
-moz-border-radius: 3px;
border-radius: 3px;
cursor: pointer;
}
.download .checkbox:hover {
color: #333;
background-color: #f5f5f5;
}
.download .checkbox small {
font-size: 12px;
color: #777;
}
/* Variables section */
#variables label {
margin-bottom: 0;
}
/* Giant download button */
.download-btn {
margin: 36px 0 108px;
}
#download p,
#download h4 {
max-width: 50%;
margin: 0 auto;
color: #999;
text-align: center;
}
#download h4 {
margin-bottom: 0;
}
#download p {
margin-bottom: 18px;
}
.download-btn .btn {
display: block;
width: auto;
padding: 19px 24px;
margin-bottom: 27px;
font-size: 30px;
line-height: 1;
text-align: center;
-webkit-border-radius: 6px;
-moz-border-radius: 6px;
border-radius: 6px;
}
/* Misc
-------------------------------------------------- */
/* Make tables spaced out a bit more */
h2 + table,
h3 + table,
h4 + table,
h2 + .row {
margin-top: 5px;
}
/* Example sites showcase */
.example-sites {
xmargin-left: 20px;
}
.example-sites img {
max-width: 100%;
margin: 0 auto;
}
.scrollspy-example {
height: 200px;
overflow: auto;
position: relative;
}
/* Fake the :focus state to demo it */
.focused {
border-color: rgba(82,168,236,.8);
-webkit-box-shadow: inset 0 1px 3px rgba(0,0,0,.1), 0 0 8px rgba(82,168,236,.6);
-moz-box-shadow: inset 0 1px 3px rgba(0,0,0,.1), 0 0 8px rgba(82,168,236,.6);
box-shadow: inset 0 1px 3px rgba(0,0,0,.1), 0 0 8px rgba(82,168,236,.6);
outline: 0;
}
/* For input sizes, make them display block */
.docs-input-sizes select,
.docs-input-sizes input[type=text] {
display: block;
margin-bottom: 9px;
}
/* Icons
------------------------- */
.the-icons {
margin-left: 0;
list-style: none;
}
.the-icons li {
float: left;
width: 25%;
line-height: 25px;
}
.the-icons i:hover {
background-color: rgba(255,0,0,.25);
}
/* Example page
------------------------- */
.bootstrap-examples p {
font-size: 13px;
line-height: 18px;
}
.bootstrap-examples .thumbnail {
margin-bottom: 9px;
background-color: #fff;
}
/* Bootstrap code examples
-------------------------------------------------- */
/* Base class */
.bs-docs-example {
position: relative;
margin: 15px 0;
padding: 39px 19px 14px;
*padding-top: 19px;
background-color: #fff;
border: 1px solid #ddd;
-webkit-border-radius: 4px;
-moz-border-radius: 4px;
border-radius: 4px;
}
/* Echo out a label for the example */
.bs-docs-example:after {
content: "Example";
position: absolute;
top: -1px;
left: -1px;
padding: 3px 7px;
font-size: 12px;
font-weight: bold;
background-color: #f5f5f5;
border: 1px solid #ddd;
color: #9da0a4;
-webkit-border-radius: 4px 0 4px 0;
-moz-border-radius: 4px 0 4px 0;
border-radius: 4px 0 4px 0;
}
/* Remove spacing between an example and it's code */
.bs-docs-example + .prettyprint {
margin-top: -20px;
padding-top: 15px;
}
/* Tweak examples
------------------------- */
.bs-docs-example > p:last-child {
margin-bottom: 0;
}
.bs-docs-example .table,
.bs-docs-example .progress,
.bs-docs-example .well,
.bs-docs-example .alert,
.bs-docs-example .hero-unit,
.bs-docs-example .pagination,
.bs-docs-example .navbar,
.bs-docs-example > .nav,
.bs-docs-example blockquote {
margin-bottom: 5px;
}
.bs-docs-example .pagination {
margin-top: 0;
}
.bs-navbar-top-example,
.bs-navbar-bottom-example {
z-index: 1;
padding: 0;
height: 90px;
overflow: hidden; /* cut the drop shadows off */
}
.bs-navbar-top-example .navbar-fixed-top,
.bs-navbar-bottom-example .navbar-fixed-bottom {
margin-left: 0;
margin-right: 0;
}
.bs-navbar-top-example {
-webkit-border-radius: 0 0 4px 4px;
-moz-border-radius: 0 0 4px 4px;
border-radius: 0 0 4px 4px;
}
.bs-navbar-top-example:after {
top: auto;
bottom: -1px;
-webkit-border-radius: 0 4px 0 4px;
-moz-border-radius: 0 4px 0 4px;
border-radius: 0 4px 0 4px;
}
.bs-navbar-bottom-example {
-webkit-border-radius: 4px 4px 0 0;
-moz-border-radius: 4px 4px 0 0;
border-radius: 4px 4px 0 0;
}
.bs-navbar-bottom-example .navbar {
margin-bottom: 0;
}
form.bs-docs-example {
padding-bottom: 19px;
}
/* Images */
.bs-docs-example-images img {
margin: 10px;
display: inline-block;
}
/* Tooltips */
.bs-docs-tooltip-examples {
text-align: center;
margin: 0 0 10px;
list-style: none;
}
.bs-docs-tooltip-examples li {
display: inline;
padding: 0 10px;
}
/* Popovers */
.bs-docs-example-popover {
padding-bottom: 24px;
background-color: #f9f9f9;
}
.bs-docs-example-popover .popover {
position: relative;
display: block;
float: left;
width: 260px;
margin: 20px;
}
/* Dropdowns */
.bs-docs-example-submenus {
min-height: 180px;
}
.bs-docs-example-submenus > .pull-left + .pull-left {
margin-left: 20px;
}
.bs-docs-example-submenus .dropup > .dropdown-menu,
.bs-docs-example-submenus .dropdown > .dropdown-menu {
display: block;
position: static;
margin-bottom: 5px;
*width: 180px;
}
/* Responsive docs
-------------------------------------------------- */
/* Utility classes table
------------------------- */
.responsive-utilities th small {
display: block;
font-weight: normal;
color: #999;
}
.responsive-utilities tbody th {
font-weight: normal;
}
.responsive-utilities td {
text-align: center;
}
.responsive-utilities td.is-visible {
color: #468847;
background-color: #dff0d8 !important;
}
.responsive-utilities td.is-hidden {
color: #ccc;
background-color: #f9f9f9 !important;
}
/* Responsive tests
------------------------- */
.responsive-utilities-test {
margin-top: 5px;
margin-left: 0;
list-style: none;
overflow: hidden; /* clear floats */
}
.responsive-utilities-test li {
position: relative;
float: left;
width: 25%;
height: 43px;
font-size: 14px;
font-weight: bold;
line-height: 43px;
color: #999;
text-align: center;
border: 1px solid #ddd;
-webkit-border-radius: 4px;
-moz-border-radius: 4px;
border-radius: 4px;
}
.responsive-utilities-test li + li {
margin-left: 10px;
}
.responsive-utilities-test span {
position: absolute;
top: -1px;
left: -1px;
right: -1px;
bottom: -1px;
-webkit-border-radius: 4px;
-moz-border-radius: 4px;
border-radius: 4px;
}
.responsive-utilities-test span {
color: #468847;
background-color: #dff0d8;
border: 1px solid #d6e9c6;
}
/* Sidenav for Docs
-------------------------------------------------- */
.bs-docs-sidenav {
width: 228px;
margin: 30px 0 0;
padding: 0;
background-color: #fff;
-webkit-border-radius: 6px;
-moz-border-radius: 6px;
border-radius: 6px;
-webkit-box-shadow: 0 1px 4px rgba(0,0,0,.065);
-moz-box-shadow: 0 1px 4px rgba(0,0,0,.065);
box-shadow: 0 1px 4px rgba(0,0,0,.065);
}
.bs-docs-sidenav > li > a {
display: block;
width: 190px \9;
margin: 0 0 -1px;
padding: 8px 14px;
border: 1px solid #e5e5e5;
}
.bs-docs-sidenav > li:first-child > a {
-webkit-border-radius: 6px 6px 0 0;
-moz-border-radius: 6px 6px 0 0;
border-radius: 6px 6px 0 0;
}
.bs-docs-sidenav > li:last-child > a {
-webkit-border-radius: 0 0 6px 6px;
-moz-border-radius: 0 0 6px 6px;
border-radius: 0 0 6px 6px;
}
.bs-docs-sidenav > .active > a {
position: relative;
z-index: 2;
padding: 9px 15px;
border: 0;
text-shadow: 0 1px 0 rgba(0,0,0,.15);
-webkit-box-shadow: inset 1px 0 0 rgba(0,0,0,.1), inset -1px 0 0 rgba(0,0,0,.1);
-moz-box-shadow: inset 1px 0 0 rgba(0,0,0,.1), inset -1px 0 0 rgba(0,0,0,.1);
box-shadow: inset 1px 0 0 rgba(0,0,0,.1), inset -1px 0 0 rgba(0,0,0,.1);
}
/* Chevrons */
.bs-docs-sidenav .icon-chevron-right {
float: right;
margin-top: 2px;
margin-right: -6px;
opacity: .25;
}
.bs-docs-sidenav > li > a:hover {
background-color: #f5f5f5;
}
.bs-docs-sidenav a:hover .icon-chevron-right {
opacity: .5;
}
.bs-docs-sidenav .active .icon-chevron-right,
.bs-docs-sidenav .active a:hover .icon-chevron-right {
background-image: url(../img/glyphicons-halflings-white.png);
opacity: 1;
}
.bs-docs-sidenav.affix {
top: 40px;
}
.bs-docs-sidenav.affix-bottom {
position: absolute;
top: auto;
bottom: 270px;
}
/* Responsive
-------------------------------------------------- */
/* Desktop large
------------------------- */
@media (min-width: 1200px) {
.bs-docs-container {
max-width: 970px;
}
.bs-docs-sidenav {
width: 258px;
}
.bs-docs-sidenav > li > a {
width: 230px \9; /* Override the previous IE8-9 hack */
}
}
/* Desktop
------------------------- */
@media (max-width: 980px) {
/* Unfloat brand */
body > .navbar-fixed-top .brand {
float: left;
margin-left: 0;
padding-left: 10px;
padding-right: 10px;
}
/* Inline-block quick links for more spacing */
.quick-links li {
display: inline-block;
margin: 5px;
}
/* When affixed, space properly */
.bs-docs-sidenav {
top: 0;
width: 218px;
margin-top: 30px;
margin-right: 0;
}
}
/* Tablet to desktop
------------------------- */
@media (min-width: 768px) and (max-width: 979px) {
/* Remove any padding from the body */
body {
padding-top: 0;
}
/* Widen masthead and social buttons to fill body padding */
.jumbotron {
margin-top: -20px; /* Offset bottom margin on .navbar */
}
/* Adjust sidenav width */
.bs-docs-sidenav {
width: 166px;
margin-top: 20px;
}
.bs-docs-sidenav.affix {
top: 0;
}
}
/* Tablet
------------------------- */
@media (max-width: 767px) {
/* Remove any padding from the body */
body {
padding-top: 0;
}
/* Widen masthead and social buttons to fill body padding */
.jumbotron {
padding: 40px 20px;
margin-top: -20px; /* Offset bottom margin on .navbar */
margin-right: -20px;
margin-left: -20px;
}
.masthead h1 {
font-size: 90px;
}
.masthead p,
.masthead .btn {
font-size: 24px;
}
.marketing .span4 {
margin-bottom: 40px;
}
.bs-docs-social {
margin: 0 -20px;
}
/* Space out the show-grid examples */
.show-grid [class*="span"] {
margin-bottom: 5px;
}
/* Sidenav */
.bs-docs-sidenav {
width: auto;
margin-bottom: 20px;
}
.bs-docs-sidenav.affix {
position: static;
width: auto;
top: 0;
}
/* Unfloat the back to top link in footer */
.footer {
margin-left: -20px;
margin-right: -20px;
padding-left: 20px;
padding-right: 20px;
}
.footer p {
margin-bottom: 9px;
}
}
/* Landscape phones
------------------------- */
@media (max-width: 480px) {
/* Remove padding above jumbotron */
body {
padding-top: 0;
}
/* Change up some type stuff */
h2 small {
display: block;
}
/* Downsize the jumbotrons */
.jumbotron h1 {
font-size: 45px;
}
.jumbotron p,
.jumbotron .btn {
font-size: 18px;
}
.jumbotron .btn {
display: block;
margin: 0 auto;
}
/* center align subhead text like the masthead */
.subhead h1,
.subhead p {
text-align: center;
}
/* Marketing on home */
.marketing h1 {
font-size: 30px;
}
.marketing-byline {
font-size: 18px;
}
/* center example sites */
.example-sites {
margin-left: 0;
}
.example-sites > li {
float: none;
display: block;
max-width: 280px;
margin: 0 auto 18px;
text-align: center;
}
.example-sites .thumbnail > img {
max-width: 270px;
}
/* Do our best to make tables work in narrow viewports */
table code {
white-space: normal;
word-wrap: break-word;
word-break: break-all;
}
/* Examples: dropdowns */
.bs-docs-example-submenus > .pull-left {
float: none;
clear: both;
}
.bs-docs-example-submenus > .pull-left,
.bs-docs-example-submenus > .pull-left + .pull-left {
margin-left: 0;
}
.bs-docs-example-submenus p {
margin-bottom: 0;
}
.bs-docs-example-submenus .dropup > .dropdown-menu,
.bs-docs-example-submenus .dropdown > .dropdown-menu {
margin-bottom: 10px;
float: none;
max-width: 180px;
}
/* Examples: modal */
.modal-example .modal {
position: relative;
top: auto;
right: auto;
bottom: auto;
left: auto;
}
/* Tighten up footer */
.footer {
padding-top: 20px;
padding-bottom: 20px;
}
}
| 069ka4-cms | trunk/assets/css/docs.css | CSS | mit | 22,431 |
/* theme screen stylesheets */
/* import stylesheets and hide from ie/mac \*/
@import url("reset.css");
@import url("FreshPick.css");
/* end import/hide */ | 069ka4-cms | trunk/css/screen.css | CSS | mit | 161 |
/* ----------------------------------------------
Template Name : FreshPick
Template Code : S-0029
Version : 1.0
Author : Erwin Aligam
Author URI : http://www.styleshout.com/
Last Date Modified : April 24, 2009
------------------------------------------------ */
/* ----------------------------------------------
HTML ELEMENTS
------------------------------------------------- */
body {
font: 12px/170% 'Lucida Grande', 'Lucida Sans Unicode', Geneva, Verdana, Sans-Serif;
color: #666666;
margin: 0;
padding: 0;
background: #FFF url(../images/bg.gif) repeat-x;
text-align: center;
}
/* Links */
a:link, a:visited {
text-decoration: none;
color: #0788C3;
}
a:hover {
border-bottom: 1px dotted #0788C3;
}
a:link.more-link, a:visited.more-link {
padding-bottom: 2px;
font-weight: bold;
color: #0788C3;
border-bottom: 1px dotted #0788C3;
}
a:hover.more-link {
text-decoration: none;
}
/* Headers */
h1, h2, h3, h4 {
font: bold 1em/1.5em Georgia, 'Times New Roman', Times, serif;
color: #555;
margin: 10px 20px 7px 20px;
}
h1 { font-size: 3.7em; font-weight: normal; letter-spacing: -2px; }
h2 { font-size: 2.8em; font-weight: normal; }
h3 { font-size: 2.2em; font-weight: normal; letter-spacing: -0.5px; padding-top: 15px; }
h4 { font-size: 1.4em; }
/* Lists */
ul, ol {
margin: 10px 20px;
padding: 0 20px;
}
ul { list-style: disc; }
ol { list-style: decimal; }
dt {
font-weight: bold;
color: #1980AF;
}
dd {
padding-left: 20px;
}
p, dl { margin: 10px 20px; }
/* Images */
img {
background: #FAFAFA;
border: 1px solid #E4E4E4;
padding: 8px;
}
img.float-right {
margin: 5px 0px 10px 10px;
}
img.float-left {
margin: 5px 10px 10px 0px;
}
code {
margin: 3px 0;
padding: 15px;
text-align: left;
display: block;
overflow: auto;
font: 500 1em/1.5em 'Lucida Console', 'Courier New', Monospace;
/* white-space: pre; */
border: 1px solid #F0F0F0;
background: #F8F8F8;
}
acronym {
cursor: help;
border-bottom: 1px dotted #555;
}
blockquote {
margin: 10px 20px;
padding: 10px 10px 10px 32px;
border: 1px solid #F0F0F0;
background: #f8f8f8 url(../images/quote.gif) no-repeat 12px 12px;
font-weight: normal;
font-size: 17px;
line-height: 1.5em;
font-style: italic;
font-family: Georgia, 'Times New Roman', Times, Serif;
color: #555;
}
strong {
font-weight: bold;
}
/* start - table */
table {
border-collapse: collapse;
margin: 10px 20px;
}
tr { background: #FFF; }
tr.altrow { background: #F9F9F9; }
th, td {
text-align: left;
border-width: 1px;
border-style: solid;
}
th {
color: #555;
background: #F0FBFF;
padding: .8em 1em;
border-color: #D8EBF5 #D8EBF5 #B9DBEE #D8EBF5;
}
td {
border-color: #EFEFEF;
padding: .7em 1em;
}
/* end - table */
/* form elements */
form {
margin: 10px 20px;
padding: 15px 25px 25px 25px;
border: 1px solid #F0F0F0;
background: #F8F8F8;
}
form p {
border-bottom: 1px solid #E6E6E6;
padding: 12px 0 5px 0; margin: 0;
color: #666666;
}
label {
font-weight: bold;
color: #666666;
}
input, select, textarea {
margin: 5px 0;
padding: 5px;
color: #6A6969;
border-width: 1px;
border-style: solid;
border-color: #D4D4D4 #EBEBEB #EBEBEB #D4D4D4;
font: 11px 'Lucida Grande', Verdana, Helvetica, sans-serif;
}
input:focus, select:focus, textarea:focus {
color: #7BA857;
background: #EFFAE6;
}
#name, #email, #message, #website {
width: 380px;
}
input.button {
font: bold 12px Arial, Sans-serif;
height: 30px;
margin: 0;
padding: 2px 3px;
color: #FFF;
background:#B4DB6F;
border-width: 1px;
border-style: solid;
border-color: #B6DE8F #91BD37 #91BD37 #B6DE8F;
}
/* ------------------------------------------
LAYOUT
------------------------------------------- */
#wrap {
width: 920px;
margin: 0 auto;
text-align: left;
}
/* Header */
#header {
position: relative;
margin: 0 auto;
height: 245px;
}
#header h1#logo-text { margin: 0; padding: 0; }
#header h1#logo-text a {
position: absolute;
margin: 0; padding: 0 5px 0 0;
font: bold 62px 'Trebuchet MS', 'Helvetica Neue', Arial, Sans-Serif;
letter-spacing: -5px;
color: #1980AF;
text-decoration: none;
/* change the values of top and left to adjust the position of the logo*/
top: 30px; left: 30px;
}
#header h1#logo-text a:hover { border: none; }
#header p#slogan {
position: absolute;
margin: 0; padding: 0 5px 0 0;
font-family: Georgia, 'Times New Roman', Times, serif;;
font-weight: bold;
font-size: 13px;
line-height: 1.8em;
font-style: italic;
letter-spacing: -.3px;
color: #999;
/* change the values of top and left to adjust the position */
top: 102px; left: 32px;
}
#header #header-image {
position: absolute;
top: 12px; right: 30px;
width: 292px;
height: 234px;
/*background: url(../images/header-bg.png) no-repeat; */
}
/* navigation */
#header #nav {
position: absolute;
left: 0px; bottom: 20px;
margin: 0; padding: 0 0 0 20px;
width: 900px;
border-bottom: 1px solid #F2F2F2;
/* z-index: 99999; */
}
#header #nav ul {
float: left;
list-style: none;
margin: 0;
padding: 0;
}
#header #nav ul li {
float: left;
margin: 0; padding: 0;
}
#header #nav ul li a:link,
#header #nav ul li a:visited {
float: left;
margin: 0;
padding: 5px 15px 10px 15px;
color: #666666;
font: bold 14px 'Trebuchet MS', Arial, Sans-Serif;
text-transform: uppercase;
border-right: 1px solid #EEE;
}
#header #nav ul li a:hover,
#header #nav ul li a:active {
border: none;
color: #000;
border-right: 1px solid #EEE;
}
#header #nav ul li#current a {
background: transparent url(../images/current.gif) repeat-x left bottom;
color: #222;
}
#header #nav ul li.first a:link,
#header #nav ul li.first a:visited {
border-left: 1px solid #F1F1F1;
}
/* Featured Block */
#featured {
clear: both;
background: #F8FAFD;
border: 1px solid #DCF1FB;
margin: 3px 0 15px 10px;
padding-bottom: 20px;
width: 900px;
}
#featured h2 {
font: normal 3.8em Georgia, 'Times New Roman', Times, Serif;
color: #295177;
letter-spacing: -2.0px;
margin-bottom: 0;
padding-bottom: 3px;
border-bottom: 1px solid #EBEBEB;
}
#featured h2 a {
color: #295177;
border: none;
}
#featured .image-block {
float: left;
width: 330px;
margin: 20px 0 0 25px;
padding: 10px 0 0 0;
display: inline;
border-right: 1px solid #DCF1FB;
}
#featured .image-block img {
background: #FFF;
border: 1px solid #DFEAF0;
padding: 12px;
}
#featured .text-block {
float: right;
width: 510px;
margin: 15px 25px 0 0;
display: inline;
}
#featured a.more-link {
background: #B4DB6F;
padding: 5px 10px 5px 10px;
margin-top: 15px;
color: #FFF;
text-decoration: none;
border: 1px solid #BADE7D;
text-transform: uppercase;
font-size: 10px;
font-weight: bold;
line-height: 20px;
display: block;
float: left;
}
#featured a.more-link:hover {
background: #008EFD;
border-color: #007DE2;
}
/* Content */
#content-outer {
clear: both;
float: left;
width: 920px;
margin: 0; padding: 0;
background: transparent url(../images/hor-line.gif) repeat-y center 0;
}
#content-wrap {
float: left;
width: 920px;
background: transparent url(../images/dotted-lines.gif) repeat-x;
}
#content {
float: left;
width: 900px;
margin-left: 10px;
display: inline;
padding-bottom: 40px;
}
/* columns */
#left {
width: 580px;
float: left;
padding-top: 15px;
}
#right {
width: 285px;
float: right;
padding-top: 5px;
}
#right h3 {
margin-left: 10px;
}
#left h2 {
font: normal 3.6em Georgia, 'Times New Roman', Times, Serif;
color: #444;
letter-spacing: -2.2px;
margin-bottom: 0px;
padding-bottom: 3px;
padding-left: 3px;
border-bottom: 1px solid #EBEBEB;
}
#left h2 a {
color: #444;
border: none;
}
#left .entry {
background: url(../images/dotted-lines.gif) repeat-x left bottom;
padding-bottom: 15px;
}
#left .entry h3 a {
color: #444;
border: none;
}
/* sidebar quick search */
#right form#quick-search {
padding: 0; margin: 10px 0 0 10px;
width: 270px; height: 33px;
background: #fff url(../images/header-search.gif) no-repeat;
border: none;
}
#right form#quick-search p {
margin: 0; padding: 0;
border: none;
}
#right form#quick-search input {
border: none;
background: transparent;
color: #BABABA;
margin: 0; padding: 5px;
font-size: .9em;
float: left;
}
#right form#quick-search .tbox {
margin: 6px 0 0 5px;
width: 220px;
display: inline;
}
#right form#quick-search .btn{
width: 24px; height: 24px;
margin: 5px 0 0 0; padding: 0;
}
#right form#quick-search label {
display: none;
}
/* sidemenus */
.sidemenu ul {
text-align: left;
margin: 10px 8px 8px 8px; padding: 0;
border-top: 1px solid #EBEBEB;
}
.sidemenu ul li {
list-style: none;
background: url(../images/dotted-lines.gif) repeat-x left bottom;
padding: 7px 5px;
margin: 0;
}
* html body .sidemenu ul li {
height: 1%;
}
.sidemenu ul li a,
.sidemenu ul li a:visited {
color: #5D95CA;
padding-left: 0;
font-weight: bold;
}
.sidemenu ul li a span {
color: #9F9F9F;
font-family: Georgia, 'Times New Roman', Times, Serif;
font-style: normal;
font-weight: normal;
font-size: .9em;
}
.sidemenu ul li a:hover { color: #000; border: none; }
.sidemenu ul ul { margin: 0 0 0 5px; padding: 0; }
.sidemenu ul ul li { background: none; }
/* footer */
#footer-outer {
clear: both;
float: left;
width: 920px;
background: url(../images/dotted-lines.gif) repeat-x;
font-size: .9em;
color: #777;
}
#footer-wrap {
float: left;
width: 900px;
margin-left: 10px;
display: inline;
}
#footer-wrap h3 {
font-size: 2.4em;
}
#footer-wrap .col-a {
width: 300px;
float: left;
}
#footer-wrap .col-b {
width: 295px;
float: right;
}
/* footer-list */
#footer-outer .footer-list ul {
border-top: 1px solid #E6E6E6;
list-style: none;
padding: 0;
margin-left: 20px;
}
#footer-outer .footer-list ul li {
background: url(../images/dotted-lines.gif) repeat-x left bottom;
}
#footer-outer .footer-list ul li a {
display: block;
width: 98%;
line-height: 2em;
padding: 5px 0;
margin-left: 0;
color: #77A6D3;
border: none;
}
#footer-outer .footer-list ul li a span {
font-style: italic;
font-weight: normal;
font-family: Georgia, 'Times New Roman', Times, Serif;
font-size: .95em;
}
#footer-outer .footer-list ul li a:hover,
#footer-outer .footer-list ul li a:hover span {
color: #333;
}
/* footer-bottom */
#footer-bottom {
float: left;
clear: both;
background: url(../images/dotted-lines.gif) repeat-x;
width: 920px;
margin: 30px auto 0 auto;
font-family: 'Trebuchet MS', 'Helvetica Neue', Arial, sans-serif;
font-size: .9em;
color: #777;
border-bottom: 50px solid #FFF;
}
#footer-bottom a:hover { border: none; }
#footer-bottom .bottom-left {
float: left;
padding-left: 5px;
}
#footer-bottom .bottom-right {
text-align: right;
padding-right: 0;
}
/* post */
.post {
margin-bottom: 15px;
background: url(../images/dotted-lines.gif) repeat-x left bottom;
padding-bottom: 15px;
}
.post .image-section {
clear: both;
display: block;
margin: 25px 0 10px 20px;
padding: 0;
}
.post .image-section img {
background: #FAFAFA;
border: 1px solid #ECECEC;
padding: 12px;
}
.post .postmeta {
padding: 5px 15px; margin: 20px 20px 15px 20px;
background: #f9fbfd;
border: 1px solid #eaf1f5;
}
.post .postmeta a { background: transparent; }
.post .postmeta a:hover { border: none; }
.post .postmeta a.comments { margin: 0 10px 0 5px; }
.post .postmeta a.readmore { margin: 0 10px 0 5px; }
.post .postmeta .date { margin: 0 10px 0 5px; }
.post .post-info,
#featured .post-info { font-size: .95em; margin-top: 0; color: #B0B0B0; }
.post .post-info a, .post .post-info a:visited,
#featured .post-info a, #featured .post-info a:visited { color: #8BB92E; border: none; }
.post .tags {
padding: 5px 15px; margin: 20px 20px 15px 20px;
border-top: 1px solid #eaf1f5;
border-bottom: 1px solid #eaf1f5;
}
/* comments list */
ol.commentlist {
margin: 12px 20px;
padding: 0;
border-style: solid;
border-color: #F0F0F0;
border-width: 1px 1px 0 1px;
}
.commentlist li {
margin: 0;
padding: 10px;
list-style: none;
border-bottom: 1px solid #F0F0F0;
}
.commentlist li cite {
display: block;
font-style: normal;
font-weight: bold;
padding: 7px;
}
.commentlist li cite img {
float: left;
margin-right: 10px;
}
.commentlist li cite .comment-data {
font-size: .8em;
font-weight: normal;
}
.commentlist li .comment-text {
clear: both;
margin: 0; padding: 5px 0 0 0;
}
.commentlist li.alt {
background: #F8F8F8;
}
/* archives */
ul.archive {
background: url(../images/dotted-lines.gif) repeat-x left top;
margin: 15px 20px 20px 20px;
padding: 0;
}
ul.archive li {
list-style: none;
background: url(../images/dotted-lines.gif) repeat-x left bottom;
margin: 0;
padding: 10px 5px;
}
ul.archive li .post-title {
margin: 0;
padding: 0;
font-size: 1.2em;
}
ul.archive li .post-title a {
color: #555;
}
ul.archive li .post-title a:hover {
border: none;
color: #222;
}
ul.archive li .post-details {
font-size: .9em;
margin-left: 0;
margin-top: 0;
}
ul.archive li .post-details a {
border: none;
}
/* pagenavigation */
.page-navigation {
margin: 10px 20px 10px 20px;
padding: 5px 15px;
background: #F9F9F9;
border: 1px solid #F0F0F0;
width: 510px;
}
.page-navigation a:hover {
border: none;
color: #333;
}
/* thumbnails */
p.thumbs {
padding: 10px 0 0 0px;
margin: 0 0 0 15px;
}
.thumbs img {
position: relative;
padding: 8px;
margin: 4px;
background: #FAFAFA;
border: 1px solid #EDEDED;
}
.thumbs img:hover {
border: 1px solid #D2D2D2;
}
.thumbs a:hover { background-color: transparent; border: none }
/* alignment classes & additional classes*/
.float-left { float: left; }
.float-right { float: right; }
.align-left { text-align: left; }
.align-right { text-align: right; }
.no-border { border: none; }
.no-bg { background: none; }
/* clearing */
.clearer { clear: both; }
.clear { display:inline-block; }
.clear:after {
display:block;
visibility:hidden;
clear:both;
height:0;
content: ".";
}
| 069ka4-cms | trunk/css/FreshPick.css | CSS | mit | 14,763 |
/* http://meyerweb.com/eric/thoughts/2007/05/01/reset-reloaded/ */
html, body, div, span, applet, object, iframe, h1, h2, h3, h4, h5, h6, p, blockquote, pre,
a, abbr, acronym, address, big, cite, code, del, dfn, em, font, img, ins, kbd, q, s, samp,
small, strike, strong, sub, sup, tt, var,dl, dt, dd, ol, ul, li, fieldset, form, label, legend,
table, caption, tbody, tfoot, thead, tr, th, td {
margin: 0;
padding: 0;
border: 0;
outline: 0;
font-weight: inherit;
font-style: inherit;
font-size: 100%;
font-family: inherit;
vertical-align: baseline;
}
/* remember to define focus styles! */
:focus {
outline: 0;
}
body {
line-height: 1;
color: black;
background: white;
}
ol, ul {
list-style: none;
}
/* tables still need 'cellspacing="0"' in the markup */
table {
border-collapse: separate;
border-spacing: 0;
}
caption, th, td {
text-align: left;
font-weight: normal;
}
blockquote:before, blockquote:after,
q:before, q:after {
content: "";
}
blockquote, q {
quotes: "" "";
} | 069ka4-cms | trunk/css/reset.css | CSS | mit | 996 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class ContributorActivity extends Activity {
public void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.contributors);
final Button button01 = (Button)
findViewById(R.id.Button01);
button01.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://www.tAIIC.com");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button02 = (Button)
findViewById(R.id.Button02);
button02.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://sites.jsoft.com/rm/home");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button03 = (Button)
findViewById(R.id.Button03);
button03.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://www.suavestudio.com/");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button04 = (Button)
findViewById(R.id.Button04);
button04.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
finish();
}
});
}
}
| 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/ContributorActivity.java | Java | gpl3 | 2,356 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class AndDevActivity extends Activity {
@Override
public void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.anddevtab);
final Button button01 = (Button)
findViewById(R.id.Button01);
button01.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://developer.android.com/sdk/index.html");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button02 = (Button)
findViewById(R.id.Button02);
button02.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("http://developer.android.com/guide/index.html");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
//
final Button button03 = (Button)
findViewById(R.id.Button03);
button03.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("http://developer.android.com/reference/packages.html");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
//
final Button button04 = (Button)
findViewById(R.id.Button04);
button04.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("http://developer.android.com/resources/index.html");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button05 = (Button)
findViewById(R.id.Button05);
button05.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("https://groups.google.com/forum/#!forum/android-developers");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button06 = (Button)
findViewById(R.id.Button06);
button06.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("mailto:android-developers@googlegroups.com?body=\n\n\n\n\nSent from tAIR Companion App");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
}
}
| 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/AndDevActivity.java | Java | gpl3 | 3,433 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class GroupActivity extends Activity {
public void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.grouptab);
final Button button01 = (Button)
findViewById(R.id.Button01);
button01.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://groups.google.com/group/theairepository/about");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button02 = (Button)
findViewById(R.id.Button02);
button02.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("https://groups.google.com/group/theairepository/");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button03 = (Button)
findViewById(R.id.Button03);
button03.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("mailto:theairepository@googlegroups.com?body=\n\n\n\n\nSent from tAIR Companion App");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button04 = (Button)
findViewById(R.id.Button04);
button04.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("https://groups.google.com/forum/?hl=en#!members/theairepository");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
}
}
| 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/GroupActivity.java | Java | gpl3 | 2,468 |
package info.tAIR.tAIRApp;
import android.app.TabActivity;
import android.content.Intent;
import android.content.res.Resources;
import android.os.Bundle;
import android.widget.TabHost;
public class tAIRTabWidget extends TabActivity {
/** Called when the activity is first created. */
@Override
public void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.main);
Resources res = getResources(); // Resource object to get Drawables
TabHost tabHost = getTabHost(); // The activity TabHost
TabHost.TabSpec spec; // Resusable TabSpec for each tab
Intent intent; // Reusable Intent for each tab
// Create an Intent to launch an Activity for the tab (to be reused)
intent = new Intent().setClass(this, tAIRActivity.class);
// Initialize a TabSpec for each tab and add it to the TabHost
spec = tabHost.newTabSpec("tair").setIndicator("tAIR",
res.getDrawable(R.drawable.ic_tab_tair))
.setContent(intent);
tabHost.addTab(spec);
// Do the same for the other tabs
intent = new Intent().setClass(this, GroupActivity.class);
spec = tabHost.newTabSpec("group").setIndicator("Discuss",
res.getDrawable(R.drawable.ic_tab_group))
.setContent(intent);
tabHost.addTab(spec);
intent = new Intent().setClass(this, CodeActivity.class);
spec = tabHost.newTabSpec("code").setIndicator("Code",
res.getDrawable(R.drawable.ic_tab_code))
.setContent(intent);
tabHost.addTab(spec);
intent = new Intent().setClass(this, AIActivity.class);
spec = tabHost.newTabSpec("aiforum").setIndicator("AI Forums",
res.getDrawable(R.drawable.ic_tab_ai))
.setContent(intent);
tabHost.addTab(spec);
intent = new Intent().setClass(this, AndDevActivity.class);
spec = tabHost.newTabSpec("anddev").setIndicator("Android Developer",
res.getDrawable(R.drawable.ic_tab_anddev))
.setContent(intent);
tabHost.addTab(spec);
tabHost.setCurrentTab(0);
}
} | 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/tAIRTabWidget.java | Java | gpl3 | 2,332 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
import android.widget.Toast;
public class CodeActivity extends Activity {
public void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.codetab);
final Button button01 = (Button)
findViewById(R.id.Button01);
button01.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://code.google.com/p/the-ai-repository");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button02 = (Button)
findViewById(R.id.Button02);
button02.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://code.google.com/p/the-ai-repository/downloads/list");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button03 = (Button)
findViewById(R.id.Button03);
button03.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://code.google.com/p/the-ai-repository/source/browse/");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button04 = (Button)
findViewById(R.id.Button04);
button04.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on contributors click
Intent contribIntent = new Intent();
contribIntent.setClassName("info.tAIR.tAIRApp", "info.tAIR.tAIRApp.ContributorActivity");
startActivity(contribIntent);
}
});
final Button button05 = (Button)
findViewById(R.id.Button05);
button05.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Toast.makeText(CodeActivity.this, "tAIR Companion App v2.0\n\n Copyright @ 2010-2011\n\n http://www.tAIR.info", Toast.LENGTH_LONG).show();
}
});
}
}
| 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/CodeActivity.java | Java | gpl3 | 2,767 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class AIActivity extends Activity {
public void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.aitab);
final Button button01 = (Button)
findViewById(R.id.Button01);
button01.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://appinventor.googlelabs.com/forum");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button02 = (Button)
findViewById(R.id.Button02);
button02.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("mailto:getting-started-with-app-inventor@googlegroups.com?body=\n\n\n\n\nSent from tAIR Companion App");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button03 = (Button)
findViewById(R.id.Button03);
button03.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("mailto:app-inventor-instructors@googlegroups.com?body=\n\n\n\n\nSent from tAIR Companion App");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button04 = (Button)
findViewById(R.id.Button04);
button04.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("mailto:programming-with-app-inventor@googlegroups.com?body=\n\n\n\n\nSent from tAIR Companion App");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button05 = (Button)
findViewById(R.id.Button05);
button05.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("mailto:appinventor@googlegroups.com?body=\n\n\n\n\nSent from tAIR Companion App");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
}
}
| 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/AIActivity.java | Java | gpl3 | 3,276 |
package info.tAIR.tAIRApp;
import android.app.Activity;
import android.content.Intent;
import android.net.Uri;
import android.os.Bundle;
import android.view.View;
import android.view.View.OnClickListener;
import android.widget.Button;
public class tAIRActivity extends Activity {
@Override
public void onCreate(Bundle savedInstanceState) {
super.onCreate(savedInstanceState);
setContentView(R.layout.tairtab);
final Button button01 = (Button)
findViewById(R.id.Button01);
button01.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://www.tair.info/messages");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button02 = (Button)
findViewById(R.id.Button02);
button02.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("http://www.tair.info/block-images");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
//
final Button button03 = (Button)
findViewById(R.id.Button03);
button03.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("http://www.tair.info/source-code");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
//
final Button button04 = (Button)
findViewById(R.id.Button04);
button04.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
// //Perform action on click
Uri uri = Uri.parse("http://www.tair.info/tutorials");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button05 = (Button)
findViewById(R.id.Button05);
button05.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://www.tair.info/other-resources");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button06 = (Button)
findViewById(R.id.Button06);
button06.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://www.tair.info/android-sdk-1");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
final Button button07 = (Button)
findViewById(R.id.Button07);
button07.setOnClickListener(new OnClickListener() {
public void onClick(View v) {
//Perform action on click
Uri uri = Uri.parse("http://www.tair.info/contact-us");
Intent intent = new Intent(Intent.ACTION_VIEW, uri);
startActivity(intent);
}
});
}
}
| 0skillz63-test | tAIRCompanionApp/src/info/tAIR/tAIRApp/tAIRActivity.java | Java | gpl3 | 3,762 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity DECODER_TB is -- entity declaration
end DECODER_TB;
architecture TB of DECODER_TB is
signal T_I: std_logic_vector(1 downto 0):="00";
signal T_O: std_logic_vector(3 downto 0);
-- declare the component
component DECODER
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end component;
begin
U_DECODER: DECODER port map (T_I, T_O);
process
-- variable should be declared within process
variable err_cnt : integer := 0;
begin
-- case "00"
wait for 10 ns;
T_I <= "00";
wait for 1 ns;
assert (T_O="0001") report "Error Case 0"
severity error;
if (T_O/="0001") then
err_cnt := err_cnt + 1;
end if;
-- case "01"
wait for 10 ns;
T_I <= "01";
wait for 1 ns;
assert (T_O="0010") report "Error Case 1"
severity error;
if (T_O/="0010") then
err_cnt := err_cnt + 1;
end if;
-- case "10"
wait for 10 ns;
T_I <= "10";
wait for 1 ns;
assert (T_O="0100") report "Error Case 2"
severity error;
if (T_O/="0100") then
err_cnt := err_cnt + 1;
end if;
-- case "11"
wait for 10 ns;
T_I <= "11";
wait for 1 ns;
assert (T_O="1000") report "Error Case 3"
severity error;
if (T_O/="1000") then
err_cnt := err_cnt + 1;
end if;
-- case "11"
wait for 10 ns;
T_I <= "UU";
-- summary of all the tests
if (err_cnt=0) then
assert false
report "Testbench of Adder completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;
wait;
end process;
end TB;
---------------------------------------------------------------
configuration CFG_TB of DECODER_TB is
for TB
end for;
end CFG_TB;
----------------------------------------------------------------
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_demultiplexer.vhd | VHDL | lgpl | 1,782 |
-- some modifications made to the original version, which was provided by Alberto.
-- configuration at the bottom changed.
-- Rajesh
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal RESET : std_logic;
signal en0 : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal en3 : std_logic;
signal QK : std_logic_vector (7 downto 0);
signal Q : std_logic_vector (31 downto 0);
component SHIFTREG_ENABLE
Port ( CLOCK : In std_logic;
RESET : In std_logic;
en0 : In std_logic;
en1 : In std_logic;
en2 : In std_logic;
en3 : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (31 downto 0) );
end component;
begin
UUT : SHIFTREG_ENABLE
Port Map ( CLOCK, RESET, en0, en1, en2, en3, QK, Q );
TB : block
begin
process
CONSTANT NLOOPS : integer := 15;
file cmdfile: TEXT; -- Define the file 'handle'
variable line_in,line_out: Line; -- Line buffers
variable good: boolean; -- Status of the read operations
variable A,B: std_logic_vector(7 downto 0);
variable S: std_logic_vector(55 downto 0);
variable Z: std_logic_vector(31 downto 0);
variable ERR: std_logic_vector(55 downto 0);
variable c : integer;
-- constant TEST_PASSED: string := "Test passed:";
-- constant TEST_FAILED: string := "Test FAILED:";
begin
c := 1;
FILE_OPEN(cmdfile,"testvecs.in",READ_MODE);
reset <= '0';
clock <= '1'; wait for 5 ns;
reset <= '1';
clock <= '0'; wait for 5 ns;
-- -------------------------------------------------------------------------
loop
if endfile(cmdfile) then -- Check EOF
assert false
report "End of file encountered; exiting."
severity NOTE;
exit;
end if;
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
-- - byte 0 ---------------------------------------------------------
hread(line_in,A,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
QK(7 downto 0) <= A(7 downto 0);
EN0 <= '1'; EN1 <= '0'; EN2 <= '0'; EN3 <= '0';
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
write(line_out, string'("byte 0 : "));
hwrite(line_out,A,RIGHT,2);
writeline(OUTPUT,line_out); -- write the message
-- - byte 0 ---------------------------------------------------------
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
hread(line_in,A,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
QK(7 downto 0) <= A(7 downto 0);
EN0 <= '0'; EN1 <= '1'; EN2 <= '0'; EN3 <= '0';
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
write(line_out, string'("byte 1 : "));
hwrite(line_out,A,RIGHT,2);
writeline(OUTPUT,line_out); -- write the message
-- - byte 0 ---------------------------------------------------------
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
hread(line_in,A,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
QK(7 downto 0) <= A(7 downto 0);
EN0 <= '0'; EN1 <= '0'; EN2 <= '1'; EN3 <= '0';
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
write(line_out, string'("byte 2 : "));
hwrite(line_out,A,RIGHT,2);
writeline(OUTPUT,line_out); -- write the message
-- - byte 0 ---------------------------------------------------------
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
hread(line_in,A,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
QK(7 downto 0) <= A(7 downto 0);
EN0 <= '0'; EN1 <= '0'; EN2 <= '0'; EN3 <= '1';
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
Z(31 downto 0) := Q(31 downto 0);
write(line_out, string'("byte 3 : "));
hwrite(line_out,A,RIGHT,2);
write(line_out, string'(" -> "));
hwrite(line_out,Z,RIGHT,8);
writeline(OUTPUT,line_out); -- write the message
end loop;
write(line_out, string'("END ENABLE"));
writeline(OUTPUT,line_out);
-- -------------------------------------------------------------------------
-- ===============================================================
clock <= '1'; wait for 1000 ns;
assert q = "11111111111111111111111111111111"
report "--------- END SIMULATION ------------------ " severity error;
-- ===============================================================
end process;
end block;
end A;
configuration CFG_tb_shiftreg_enable_BEHAVIORAL of E is
for A
for UUT : SHIFTREG_ENABLE
-- use configuration WORK.CFG_q_regs_enable_SCHEMATIC;
use configuration WORK.CFG_SHIFTREG_enable_SCHEMATIC;
end for;
for TB
end for;
end for;
end CFG_tb_shiftreg_enable_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_shiftreg-enable.vhd | VHDL | lgpl | 5,421 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity REG is
port(
D : in std_logic_vector(7 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(7 downto 0));
end entity REG;
architecture BEH_REG of REG is
begin
p0: process (Clock, Reset) is
begin
if (Reset = '0') then
Q <= (others => '0');
elsif rising_edge(clock) then
Q <= D;
end if;
end process p0;
end architecture BEH_REG;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/REG.vhd | VHDL | lgpl | 557 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
clock: in std_logic;
clear: in std_logic;
Qc: out std_logic_vector(1 downto 0)
);
end counter;
architecture beh_counter of counter is
signal Pre_Q: std_logic_vector(1 downto 0);
begin
process(clock, clear)
begin
if (clear = '0') then
Pre_Q <= "11";
elsif (clock='1' and clock'event) then
Pre_Q <= Pre_Q + "01";
end if;
end process;
Qc <= Pre_Q;
end beh_counter; | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/counter.vhd | VHDL | lgpl | 552 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY toplevel_shiftreg IS
PORT (
CLK : IN STD_LOGIC;
RSTx : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END toplevel_shiftreg;
ARCHITECTURE struct OF toplevel_shiftreg IS
-- Signals AKA internal wiring
SIGNAL s_R1_to_R2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_R2_to_R3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_R3_to_R4 : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT REG
PORT (
Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
BEGIN
R1 : REG
PORT MAP (
Clock => CLK,
Reset => RSTx,
D => data_in,
Q => s_R1_to_R2
);
R2 : REG
PORT MAP (
Clock => CLK,
Reset => RSTx,
D => s_R1_to_R2,
Q => s_R2_to_R3
);
R3 : REG
PORT MAP (
Clock => CLK,
Reset => RSTx,
D => s_R2_to_R3,
Q => s_R3_to_R4
);
R4 : REG
PORT MAP (
Clock => CLK,
Reset => RSTx,
D => s_R3_to_R4,
Q => data_out(31 DOWNTO 24)
);
data_out(23 DOWNTO 16) <= s_R3_R4;
END struct;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/toplevel_shiftreg.vhd | VHDL | lgpl | 1,194 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG_ENABLE is
Port (
CLOCK : In std_logic;
RESET : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (31 downto 0);
en0: In std_logic;
en1: In std_logic;
en2: In std_logic;
en3: In std_logic
);
end SHIFTREG_ENABLE;
architecture BEH_SHIFTREG_ENABLE of SHIFTREG_ENABLE is
component REG is
port(
D : in std_logic_vector(7 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component REG;
component MUX is
port (
Q0 : in std_logic_vector(7 downto 0);
Q1 : in std_logic_vector(7 downto 0);
enable: in std_logic;
Qmux : out std_logic_vector(7 downto 0)
);
end component MUX;
signal Qout0, Qout1, Qout2, Qout3 : std_logic_vector(7 downto 0);
begin
m1: MUX port map (Q(31 downto 24), QK, en0, Qout0);
m2: MUX port map (Q(23 downto 16), QK, en1, Qout1);
m3: MUX port map (Q(15 downto 8), QK, en2, Qout2);
m4: MUX port map (Q(7 downto 0), QK, en3, Qout3);
r1: REG port map (Qout0, Clock, Reset, Q(31 downto 24));
r2: REG port map (Qout1, Clock, Reset, Q(23 downto 16));
r3: REG port map (Qout2, Clock, Reset, Q(15 downto 8));
r4: REG port map (Qout3, Clock, Reset, Q(7 downto 0));
end BEH_SHIFTREG_ENABLE;
configuration CFG_SHIFTREG_enable_SCHEMATIC of SHIFTREG_ENABLE is
for BEH_SHIFTREG_ENABLE
end for;
end CFG_SHIFTREG_enable_SCHEMATIC; | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/SHIFTREG_enable.vhd | VHDL | lgpl | 1,531 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity MUX is
port (
Q0 : in std_logic_vector(7 downto 0);
Q1 : in std_logic_vector(7 downto 0);
enable: in std_logic;
Qmux : out std_logic_vector(7 downto 0)
);
end entity MUX;
architecture BEH_MUX of MUX is
begin
process (Q0,Q1,enable) is
begin
if (enable = '0') then
Qmux <= Q0;
elsif (enable = '1') then
Qmux <= Q1;
else
Qmux <= (others => '0');
end if;
end process;
end architecture BEH_MUX;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/MUX.vhd | VHDL | lgpl | 611 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal RESET : std_logic;
signal QK : std_logic_vector (7 downto 0);
signal Q : std_logic_vector (31 downto 0);
component SHIFTREG_GATED
Port ( CLK : In std_logic;
RESET : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : Out std_logic_vector (31 downto 0) );
end component;
begin
UUT : SHIFTREG_GATED
Port Map ( CLOCK, RESET, QK, Q );
TB : block
begin
process
CONSTANT NLOOPS : integer := 15;
file cmdfile: TEXT; -- Define the file 'handle'
variable line_in,line_out: Line; -- Line buffers
variable good: boolean; -- Status of the read operations
variable A,B: std_logic_vector(7 downto 0);
variable S: std_logic_vector(55 downto 0);
variable Z: std_logic_vector(31 downto 0);
variable ERR: std_logic_vector(55 downto 0);
variable c : integer;
-- constant TEST_PASSED: string := "Test passed:";
-- constant TEST_FAILED: string := "Test FAILED:";
begin
c := 1;
FILE_OPEN(cmdfile,"testvecs.in",READ_MODE);
reset <= '0';
clock <= '1'; wait for 5 ns;
reset <= '1';
clock <= '0'; wait for 5 ns;
-- -------------------------------------------------------------------------
loop
if endfile(cmdfile) then -- Check EOF
assert false
report "End of file encountered; exiting."
severity NOTE;
exit;
end if;
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
hread(line_in,A,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
QK(7 downto 0) <= A(7 downto 0);
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
Z(31 downto 0) := Q(31 downto 0);
write(line_out, string'("byte "));
write(line_out,c-1);
write(line_out, string'(" : "));
if (c = 4) then
hwrite(line_out,A,RIGHT,2);
write(line_out, string'(" -> "));
hwrite(line_out,Z,RIGHT,8);
c := 0;
else
hwrite(line_out,A,RIGHT,2);
end if;
writeline(OUTPUT,line_out); -- write the message
--assert (Z = S) report "Z does not match in pattern " severity error;
c := c + 1;
end loop;
-- -------------------------------------------------------------------------
write(line_out, string'("--------- END GATED 2 ------------------"));
writeline(OUTPUT,line_out);
-- ===============================================================
clock <= '1'; wait for 1000 ns;
assert q = "11111111111111111111111111111111"
report "--------- END SIMULATION ------------------ " severity error;
-- ===============================================================
end process;
end block;
end A;
configuration CFG_tb_shiftreg_gated_BEHAVIORAL of E is
for A
for UUT : SHIFTREG_GATED
-- use configuration WORK.CFG_q_regs_enable_SCHEMATIC;
use configuration WORK.CFG_SHIFTREG_GATED_SCHEMATIC;
end for;
for TB
end for;
end for;
end CFG_tb_shiftreg_gated_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_shiftreg-gated2.vhd | VHDL | lgpl | 3,261 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter_TB is -- entity declaration
end counter_TB;
-----------------------------------------------------------------------
architecture TB of counter_TB is
component counter
port( clock: in std_logic;
clear: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
signal T_clock: std_logic;
signal T_clear: std_logic;
--signal T_count: std_logic;
signal T_Q: std_logic_vector(1 downto 0);
begin
U_counter: counter port map (T_clock, T_clear, T_Q);
process
begin
T_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;
process
variable err_cnt: integer :=0;
begin
T_clear <= '1'; -- start counting
-- T_count <= '1';
wait for 20 ns;
T_clear <= '0'; -- clear output
-- test case 1
wait for 10 ns;
assert (T_Q=1) report "Failed case 1" severity error;
if (T_Q/=1) then
err_cnt := err_cnt+1;
end if;
-- test case 2
wait for 10 ns;
assert (T_Q=2) report "Failed case 2" severity error;
if (T_Q/=2) then
err_cnt := err_cnt+1;
end if;
-- test case 3
wait for 10 ns;
assert (T_Q=3) report "Failed case 3" severity error;
if (T_Q/=3) then
err_cnt := err_cnt+1;
end if;
-- test case 4
wait for 10 ns;
assert (T_Q=0) report "Failed case 4" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- test case 5
wait for 20 ns;
T_clear <= '1';
wait for 10 ns;
assert (T_Q=0) report "Failed case 5" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- summary of all the tests
if (err_cnt=0) then
assert false
report "Testbench of Adder completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;
wait;
end process;
end TB;
----------------------------------------------------------------
configuration CFG_TB of counter_TB is
for TB
end for;
end CFG_TB;
----------------------------------------------------------------
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_counter.vhd | VHDL | lgpl | 2,060 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut_enable.saif
run 41000 > run.out
quit | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/cmd_saif_enable.inc | PHP | lgpl | 108 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG_GATED is
Port ( CLK : In std_logic;
RESET : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : Out std_logic_vector (31 downto 0) );
end SHIFTREG_GATED;
architecture BEH_SHIFTREG_GATED of SHIFTREG_GATED is
component Counter is
port(
clock: in std_logic;
clear: in std_logic;
Qc: out std_logic_vector(1 downto 0)
);
end component Counter;
component REG is
port(
D : in std_logic_vector(7 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component REG;
component DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end component DECODER;
signal out_counter : std_logic_vector(1 downto 0);
signal out_decoder : std_logic_vector(3 downto 0);
begin
c1: Counter port map (CLK, Reset, out_counter);
d1: DECODER port map (out_counter, out_decoder);
r1: REG port map (QK, out_decoder(3), Reset, Q(31 downto 24));
r2: REG port map (QK, out_decoder(2), Reset, Q(23 downto 16));
r3: REG port map (QK, out_decoder(1), Reset, Q(15 downto 8));
r4: REG port map (QK, out_decoder(0), Reset, Q(7 downto 0));
end BEH_SHIFTREG_GATED;
configuration CFG_SHIFTREG_GATED_SCHEMATIC of SHIFTREG_GATED is
for BEH_SHIFTREG_GATED
end for;
end CFG_SHIFTREG_GATED_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/SHIFTREG_GATED.vhd | VHDL | lgpl | 1,568 |
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;
architecture BEH_DECODER of DECODER is
begin
process (I)
begin
case I is
when "00" => O <= "1000";
when "01" => O <= "0100";
when "10" => O <= "0010";
when "11" => O <= "0001";
when others => O <= "1000";
end case;
end process;
end BEH_DECODER; | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/Decoder.vhd | VHDL | lgpl | 446 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
ENABLE : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (31 downto 0) );
end SHIFTREG;
architecture BEHAVIORAL of SHIFTREG is
begin
process(RESET,CLOCK)
variable i,j,k,l : integer;
begin
if ( RESET = '0' ) then
for i in 0 to 31 loop
q(i) <= '0';
end loop;
elsif ((CLOCK = '1') AND (CLOCK'EVENT)) then
for i in 31 downto 8 loop
q(i) <= q(i-8);
end loop;
q(7 downto 0) <= qk;
end if;
end process;
end BEHAVIORAL;
configuration CFG_SHIFTREG_BEHAVIORAL of SHIFTREG is
for BEHAVIORAL
end for;
end CFG_SHIFTREG_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/SHIFTREG.vhd | VHDL | lgpl | 962 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut_gated.saif
run 41000 > run.out
quit | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/cmd_saif_gated.inc | PHP | lgpl | 107 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal RESET : std_logic;
signal ENABLE : std_logic;
signal QK : std_logic_vector (7 downto 0);
signal Q : std_logic_vector (31 downto 0);
component SHIFTREG
Port ( CLOCK : In std_logic;
RESET : In std_logic;
ENABLE : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (31 downto 0) );
end component;
begin
UUT : SHIFTREG
Port Map ( CLOCK, RESET, ENABLE, QK, Q );
TB : block
begin
process
CONSTANT NLOOPS : integer := 15;
file cmdfile: TEXT; -- Define the file 'handle'
variable line_in,line_out: Line; -- Line buffers
variable good: boolean; -- Status of the read operations
variable A,B: std_logic_vector(7 downto 0);
variable S: std_logic_vector(55 downto 0);
variable Z: std_logic_vector(31 downto 0);
variable ERR: std_logic_vector(55 downto 0);
variable c : integer;
-- constant TEST_PASSED: string := "Test passed:";
-- constant TEST_FAILED: string := "Test FAILED:";
begin
c := 1;
FILE_OPEN(cmdfile,"testvecs.in",READ_MODE);
reset <= '0';
clock <= '1'; wait for 5 ns;
reset <= '1';
ENABLE <= '1';
clock <= '0'; wait for 5 ns;
-- -------------------------------------------------------------------------
loop
if endfile(cmdfile) then -- Check EOF
assert false
report "End of file encountered; exiting."
severity NOTE;
exit;
end if;
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
hread(line_in,A,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
QK(7 downto 0) <= A(7 downto 0);
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
Z(31 downto 0) := Q(31 downto 0);
write(line_out, string'("byte "));
write(line_out,c-1);
write(line_out, string'(" : "));
if (c = 4) then
hwrite(line_out,A,RIGHT,2);
write(line_out, string'(" -> "));
hwrite(line_out,Z,RIGHT,8);
c := 0;
else
hwrite(line_out,A,RIGHT,2);
end if;
writeline(OUTPUT,line_out); -- write the message
--assert (Z = S) report "Z does not match in pattern " severity error;
c := c + 1;
end loop;
-- -------------------------------------------------------------------------
write(line_out, string'("--------- END SHIFT REG ------------------"));
writeline(OUTPUT,line_out);
-- ===============================================================
clock <= '1'; wait for 1000 ns;
assert q = "11111111111111111111111111111111"
report "--------- END SIMULATION ------------------ " severity error;
-- ===============================================================
end process;
end block;
end A;
configuration CFG_tb_shiftreg_BEHAVIORAL of E is
for A
for UUT : SHIFTREG
-- use configuration WORK.CFG_q_regs_enable_SCHEMATIC;
use configuration WORK.CFG_SHIFTREG_BEHAVIORAL;
end for;
for TB
end for;
end for;
end CFG_tb_shiftreg_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/tb_shiftreg.vhd | VHDL | lgpl | 3,328 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut.saif
run 41000 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/code/cmd_saif.inc | PHP | lgpl | 102 |
\documentclass[11pt,a4paper]{article}
\usepackage{url,,}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{multirow}
\usepackage{listings}
\usepackage{fullpage}
\usepackage{fancyhdr,a4wide}
\usepackage{makeidx}
\usepackage{placeins}
\usepackage[procnames,noindent]{lgrind}
\lstset{ %
language=VHDL, % choose the language of the code
basicstyle=\footnotesize, % the size of the fonts that are used for the code
showstringspaces=false, % underline spaces within strings
%numbers=left, % where to put the line-numbers
%numberstyle=\footnotesize, % the size of the fonts that are used for the line-numbers
%stepnumber=1, % the step between two line-numbers. If it's 1 each line will be numbered
%numbersep=5pt, % how far the line-numbers are from the code
%backgroundcolor=\color{white}, % choose the background color. You must add \usepackage{color}
showspaces=false, % show spaces within strings adding particular underscores
showtabs=false, % show tabs within strings adding particular underscores
escapeinside={\%*}{*)} % if you want to add a comment within your code
}
\begin{document}
\begin{titlepage}
\thispagestyle{fancy}
\lhead{}
\chead{
\large{\textit{
Informatics and Mathematical Modelling\\
Technical University of Denmark}}}
\rhead{}
\rule{0pt}{50pt}
\vspace{3cm}
\begin{center}
\huge{\textbf{02207 : Advanced Digital Design Techniques}}\\
\vspace{1cm}
\huge{Design for Low Power by Reducing Switching Activity}\\
\vspace{1cm}
\huge{\textit{LAB 2}}\\
\vspace{1cm}
\huge{Group \textit{dt07}}\\
\end{center}
\vspace{4cm}
\begin{flushright}
\LARGE{Markku Eerola (s053739)}\\
\vspace{0.3cm}
\LARGE{Rajesh Bachani (s061332)}\\
\vspace{0.3cm}
\LARGE{Josep Renard (s071158)}\\
\end{flushright}
\cfoot{\today}
\end{titlepage}
%\begin{abstract}
%\centering
%Abstract to be created.
%\end{abstract}
%-----------------------------------------------------------
\newpage
\tableofcontents
\newpage
\section{Introduction}
The purpose of this exercise was to estimate the power dissipation in a digital circuit due to the switching activity in the cells. Power is dissipated in a digital circuit, dynamically, in two ways; one, the power that is spent in charging or discharging the capacitance load connected to the output of the cell, and two, the power dissipated inside the cell due to short circuit currents and the internal capacitance charging or discharging. This holds for combinational cells. For sequential cells, there is extra power spent at every clock cycle, even if the output of the cell does not change. This is because there is some reaction to every clock cycle in sequential cells, which would take some power.
Static power in digital circuits is due to the internal leakage currents in CMOS. Though, in this exercise, we are particularly interested in analyzing the dynamic power dissipation.
We estimate the dynamic power in a serial to parallel converter. The converter takes in 8 bits (one byte) in every clock cycle, and gives out 32 bits (4 bytes) after every 4 clock cycles. The input byte at the first clock cycle is the most significant byte in the output, whereas the input byte in the fourth clock cycle is the lowest significant byte. The converter, thus, waits for four clock cycles to produce an output. We refer to the register holding the most significant byte in the output as the most significant register, and that holding the least significant byte as the least significant register.
The report is organized as follows. In section \ref{section:designs}, we discuss three designs for a serial to parallel converter. In section \ref{section:simulation}, we simulate the VHDL code for the designs using Modelsim, and verify that all the designs are working correctly. Section \ref{section:power} contains the power results obtained from the synthesis of the VHDL using Design Vision, and Synopsys VSS for annotating the switching activity in a given time period. In this section, we discuss and justify the results obtained. Later, in section \ref{section:impl}, the VHDL is provided, alongwith the power reports from Design Vision.
\subsection{Authors by Section}
\begin{itemize}
\item \textit{Rajesh Bachani} VHDL code for Design A, Design B and Design C, and simulation of the designs in Modelsim.
\item \textit{Josep Renard} Synthesis of the designs for power reports, using Synopsys VSS and Design Vision.
\item \textit{Markku Eerola} Discussion and Analysis of the power reports.
\end{itemize}
\newpage
\section{Designs for Serial to Parallel Conversion}
\label{section:designs}
In this section, we give an overview of the three designs for serial to parallel conversion, which are evaluated for their power consumption in this exercise.
\subsection{Design A: Shift Register}
\begin{figure}[htp]
\centering
\includegraphics[width = 3.5in]{./images/shiftregister.jpg}
\caption{Converter using a 8-bit Shift Register}
\label{figure:sr}
\end{figure}
As we can see in figure \ref{figure:sr}, the input data flows continuously through the registers. On every rising clock edge each of the 8-bit registers takes on a new state. The least significant register takes its state from the input to the converter block and all the other registers take their states from the outputs of the adjacent less significant register. All components of this block are driven with the same clock signal, which ensures that the 8-bit registers change their state at the same time as the clock signal event.
\subsection{Design B: Register with Enable}
\begin{figure}[htp]
\centering
\includegraphics[width = 3.5in]{./images/shiftregisterenable.jpg}
\caption{Converter using 8-bit Registers with Enable}
\label{figure:sre}
\end{figure}
In figure \ref{figure:sre} we see another design for a serial to parallel converter. In this design we use multiplexers to control when the 8-bit registers should take on a new state. The multiplexers take in two inputs, one from the output of the 8-bit register connected with that multiplexer, and one from the input to the converter block, which is Qk. When the enable signal to a multiplexer is SET, it lets through Qk, whereas, in the other case, it lets through the data from the 8-bit register's output, thus retaining the register's previous state. The enable signal to the four multiplexers is changed in a sequence, with the multiplexer 3 getting the enable first, and the multiplexer 0 getting the enable last. This way, the value of Qk in the first clock cycle is transferred to the most significant register, while Qk in the fourth clock cycle is transferred to the least significant register.
\
\subsection{Design C: Register with Clock-Gating}
\begin{figure}[htp]
\centering
\includegraphics[width = 3.5in]{./images/shiftregistergated.jpg}
\caption{Converter using 8-bit Registers with Clock Gating}
\label{figure:srg}
\end{figure}
In figure \ref{figure:srg} we see the third design for a serial to parallel converter we used in the exercise. In this design we restirct the amount of register state changes by not driving the 8-bit registers with the clock directly but instead using a 2-bit counter and a 2:4 decoder to give a rising clock edge only to one of the four 8-bit register's at a time. In this design the 8-bit registers operate only when they change their state once every fourth clock cycle. This means that they consume much less power. Of course the logic for dividing the clock consumes power as well, but we expect that the power savings which are gained by reducing the operation of the 8-bit registers outweighs this, since we're not only restricting the number of state changes but we're also completely removing the power consumption for 'idle' operations.
\newpage
\section{Simulation of the designs with Modelsim}
\label{section:simulation}
All the three designs are simulated with Modelsim, to verify the functionality.
The following two screenshots demonstrate the working of implementation for Design A. The first screenshot is taken at 33ns while the second is taken at 43ns. It can be seen that in the new clock cycle, the 8 bit registers have rippled their values to the more significant register, and the value of Qk for that clock cycle is fed into the least significant register. The most significant register looses its old value.
\begin{figure}[htp]
\centering
\includegraphics[length = 4in,width = 6.5in]{./images/simsr1.png}
\caption{Simulation screenshot for Design A at 33ns}
\end{figure}
\begin{figure}[htp]
\centering
\includegraphics[length = 4in,width = 6.5in]{./images/simsr2.png}
\caption{Simulation screenshot for Design A at 43ns}
\end{figure}
\newpage
The following screenshots are from the simulation of Design B. In the first instance, at 14ns on the timeline, we have some value at Qk, but it has not been transferred in any way to the output Q. Then, at 24ns, the value of Qk in the previous clock cycle is loaded into the most significant register. Further on, at 33ns, the value of Qk in the previous clock cycle is loaded into the second most significant register. This repeats for four clock cycles, after which the most significant register is again loaded.
\begin{figure}[htp]
\centering
\includegraphics[length = 4in,width = 6.5in]{./images/simsre1.png}
\caption{Simulation screenshot for Design B at 14ns}
\end{figure}
\begin{figure}[htp]
\centering
\includegraphics[length = 4in,width = 6.5in]{./images/simsre2.png}
\caption{Simulation screenshot for Design B at 24ns}
\end{figure}
\begin{figure}[htp]
\centering
\includegraphics[length = 4in,width = 6.5in]{./images/simsre3.png}
\caption{Simulation screenshot for Design B at 33ns}
\end{figure}
\newpage
Then, for Design C, we have the following screenshots. As we can see, the values of Qk are transferred to different registers every clock cycle. This is practically the same functionality as Design B. The only difference though is that in Design C, Qk is transferred in the same clock cycle, while in Design B, it happens one clock cycle later. Ofcourse, the internal working of the two designs are completely different, which has already been discussed in section \ref{section:designs}
\begin{figure}[htp]
\centering
\includegraphics[length = 4in,width = 6.5in]{./images/simsrg1.png}
\caption{Simulation screenshot for Design C at 14ns}
\end{figure}
\begin{figure}[htp]
\centering
\includegraphics[length = 4in,width = 6.5in]{./images/simsrg2.png}
\caption{Simulation screenshot for Design C at 24ns}
\end{figure}
\newpage
\section{Power Reports and Discussion}
\label{section:power}
In this section we discuss the results obtained from the power-aware synthesis of the three designs. The Synopsys VSS Simulator is used to annotate the switching activity, based on a testbench for each design. This switching activity is used by Design Vision to estimate the total dynamic power consumption for the design. We have synthesized the designs for clock time periods of 2ns and 10ns and got the same results for all three designs for both clock periods. The power reports obtained from the synthesis are presented in section \ref{section:impl}. For a short recap the results can be seen in table \ref{table:power}:
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{} & \textbf{Total Dynamic Power} & \textbf{Cell Leakage Power}\\ \hline
Design A & 55.2 uW & 773.7 nW \\ \hline
Design B & 47 uW & 800.5 nW \\ \hline
Design C & 32.6 uW & 835.0 nW \\ \hline
\end{tabular}
\end{center}
\caption{Overview of Results from Power Reports}
\label{table:power}
\end{table}
According to the results design A has the highest dynamic power consumption while design C has the least. We expected as much from design C, but from what we had learned on the lectures we had expected that design B would have consumed more power than design A. The static power consumption which comes from the internal leakage currents, is considerably lower than the dynamic power consumption in all of the designs. This is because static power consumption just depends on the number of cells in the design and does not depend on the switching activity. In the following analysis, we will only consider the dynamic power consumption and from now on when we use the word power we refer to the dynamic power.
In Design A the 8-bit registers change their state on each clock cycle. The input Qk is transferred from one register to the adjacent more significant register, every clock cycle, until it reaches the most significant register. This is the reason why the design is much consuming in terms of power: in every clock cycle, there is a switching activity in all the output bits of the four registers. Since switching accounts for a lot of power, for a given time line of the simulation, we have high levels of power consumption.
Design B is more efficient than Design A from what is seen in the dynamic power consumption. Switching in Design B is controlled by the enable signals, which indicate which register should be loaded with Qk in the next clock event. If the enable signal is SET, the register is loaded with Qk, otherwise the output of the register is reloaded back into the register. Where the former case consumes a lot of dynamic power since the output bits are changed, the latter consumes less dynamic power which is due to internal response to the clock signal. So, since the registers still consume internal power on each clock cycle and since the multiplexers and the logic generating their enabling signals, both add to the overall power consumption, Design B should be less efficient than Design A for the overall power consumption. This is backed up by the lecture notes: the ratio of power dissipated in Design A to that in Design B is 1:1.19, which indicates that Design B should consume more power. We believe that the reason why our results differed from this is that the logic that generated the enabling signals was within the testbench instead of the converter and thus its power dissipation was not considered in the power analysis.
Lets consider Design C now. It is quite clear that this design is most efficient among the three. This design is based on clock-gating, which means that the original clock signal is not sent directly to the registers, but sent only when the register should be loaded with a new value. So, if there is a clock signal, the register funtions normally, and power is dissipated both internally and for charging/discharging the load (if the output changes). So, 75\% of the time the clock would be cut off completely, thus saving at least the internal power dissipation due to clock cycles. In Design B, even if the enable for a register was RESET, which meant that the register output would not change, there was still internal power dissipation in the cell for every clock cycle. This is avoided in Design C since the registers do not get clock signals except when they are supposed to change their state.
We see that the attempt to reduce power disspation has been successful, without affecting the functionality of the circuit. With the reduction in power consumption come some costs, in the form of extra area and time delay. The extra logic in designs B and C use up more area and some delay is also added to the critical path. It should also be noted, that in Design C the rising clock events for the 8-bit registers come a bit later than the event at the actual clock signal, which is referred to as skew. This means that the clock period must not be shorter than the delay or the circuit will not work properly.
\newpage
\section{Implementation and Power Reports}
\label{section:impl}
\lstinputlisting[frame=trbl, caption={SHIFTREG.vhd}]{../code/SHIFTREG.vhd}
\newpage
\lstinputlisting[frame=trbl,caption={SHIFTREG\_ENABLE.vhd}]{../code/SHIFTREG_ENABLE.vhd}
\newpage
\lstinputlisting[frame=trbl,caption={SHIFTREG\_GATED.vhd}]{../code/SHIFTREG_GATED.vhd}
\newpage
\lstinputlisting[frame=trbl,caption={REG.vhd}]{../code/REG.vhd}
\lstinputlisting[frame=trbl,caption={MUX.vhd}]{../code/MUX.vhd}
\newpage
\lstinputlisting[frame=trbl,caption={COUNTER.vhd}]{../code/counter.vhd}
\lstinputlisting[frame=trbl,caption={DECODER.vhd}]{../code/DECODER.vhd}
\newpage
\lstinputlisting[frame=trbl, caption={Power Report Design A}]{../code/power_report1.txt}
\newpage
\lstinputlisting[frame=trbl, caption={Power Report Design B}]{../code/power_report2.txt}
\newpage
\lstinputlisting[frame=trbl, , caption={Power Report Design C}]{../code/power_report3.txt}
\end{document} | 02207-work-groupdt07 | trunk/Lab Work/Exercise 2/report/dt07_lab2.tex | TeX | lgpl | 16,741 |
library IEEE;
use IEEE.std_logic_1164.all, IEEE.numeric_std.all;
entity NBitAdder is
port (A, B: in std_logic_vector(23 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector(23 downto 0);
Cout: out std_logic);
end entity NBitAdder;
architecture unsgned of NBitAdder is
signal result: unsigned(24 downto 0);
signal carry: unsigned(24 downto 0);
constant zeros: unsigned(23 downto 0) := (others => '0');
begin
carry <= (zeros & Cin);
result <= ('0' & unsigned(A)) + ('0' & unsigned(B)) + carry;
Sum <= std_logic_vector(result(23 downto 0));
Cout <= result(24);
end architecture unsgned; | 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/NBitAdder.vhdl | VHDL | lgpl | 665 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AdderNetlist is
port( A1 : in std_logic_vector(23 downto 0);
A2 : in std_logic_vector(23 downto 0);
Clock, Reset: in std_logic;
Z : out std_logic_vector( 23 downto 0));
end entity AdderNetlist;
architecture NetlistBehavior of AdderNetlist is
component NBitAdder is
port (A, B: in std_logic_vector(23 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector(23 downto 0);
Cout: out std_logic);
end component NBitAdder;
component reg is
port (D : in std_logic_vector(23 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(23 downto 0));
end component reg;
signal Co, Ci : std_logic;
signal A1out, A2out, Sum : std_logic_vector(23 downto 0);
begin
g1: reg port map (A1, Clock, Reset, A1out);
g2: reg port map (A2, Clock, Reset, A2out);
g3: nbitadder port map (A1out, A2out, Ci, Sum, Co);
g4: reg port map (Sum, Clock, Reset, Z);
end architecture NetlistBehavior;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/addernetlist.vhdl | VHDL | lgpl | 1,057 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity reg is
port (D : in std_logic_vector(23 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(23 downto 0));
end entity reg;
architecture behavioural of reg is
begin
p0: process (Clock, Reset) is
begin
if (Reset = '0') then
Q <= (others => '0');
elsif rising_edge(Clock) then
Q <= D;
end if;
end process p0;
end architecture behavioural;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/reg.vhdl | VHDL | lgpl | 499 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity TestNBitAdder is
end entity TestNBitAdder;
architecture TestBench_4 of TestNBitAdder is
signal A, B, Sumint : NATURAL;
signal Aslv, Bslv, Sum: std_logic_vector (23 downto 0);
signal Cin, Cout: std_logic;
signal error: BOOLEAN := FALSE;
begin
s0: entity WORK.NBitAdder(unsgned) port map(Aslv, Bslv, Cin, Sum, Cout);
Aslv <= std_logic_vector(to_unsigned(A, 24));
Bslv <= std_logic_vector(to_unsigned(B, 24));
Sumint <= to_integer(unsigned(Cout & Sum));
stim: process is
begin
Cin <= '0';
A <= 44;
B <= 8990;
wait for 5 NS;
A <= 34545;
wait for 5 NS;
Cin <= '1';
wait for 5 NS;
A <= 7840;
wait for 5 NS;
B <= 0;
wait for 5 NS;
Cin <= '0';
wait;
end process;
resp: process (Cout, Sum) is
begin
error <= (A + B + BIT'POS(to_bit(Cin))) /= Sumint;
end process;
end architecture TestBench_4;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/source/tbnadder.vhdl | VHDL | lgpl | 907 |
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\begin{document}
\begin{titlepage}
\thispagestyle{fancy}
\lhead{}
\chead{
\large{\textit{
Informatics and Mathematical Modelling\\
Technical University of Denmark}}}
\rhead{}
\rule{0pt}{50pt}
\vspace{3cm}
\begin{center}
\huge{\textbf{02207 : Advanced Digital Design Techniques}}\\
\vspace{1cm}
\huge{Lab 1: Exercise on Synthesis}\\
\vspace{1cm}
\huge{Group \textit{dt07}}\\
\end{center}
\vspace{4cm}
\begin{flushright}
\LARGE{Markku Eerola (s053739)}\\
\vspace{0.3cm}
\LARGE{Rajesh Bachani (s061332)}\\
\vspace{0.3cm}
\LARGE{Josep Renard (s071158)}\\
\end{flushright}
\cfoot{\today}
\end{titlepage}
%\begin{abstract}
%\centering
%Abstract to be created.
%\end{abstract}
%-----------------------------------------------------------
\newpage
\tableofcontents
\newpage
\section{Introduction}
The goal of the exercise was to get familiar with the process of synthesis of digital circuits, using special tools for synthesis such as Design Vision. A register-level netlist containing a 24-bit adder is synthesized in the exercise, for different values of the clock time period. The reports concerning the timing constraints, area, power consumption etc. which are generated by the tool are documented in the report.
\subsection{Authors by Section}
\begin{itemize}
\item \textit{Markku Eerola} Behavioral description for the 24-bit adder, a testbench for the adder and the top-level netlist.
\item \textit{Josep Renard} Simulation of testbench with Modelsim (for different values of signals in testbench), behavioral description for the 24-bit register.
\item \textit{Rajesh Bachani} Synthesis with Design Vision and analysis of the results from synthesis.
\end{itemize}
\section{Behavioral Description for 24-bit Adder}
\subsection{VHDL code for the 24-bit Adder}
% Describe something about the adder %
The VHDL code for a simple 24-bit adder is provided below.\\
\lstinputlisting[frame=trbl]{../source/NBitAdder.vhdl}
\newpage
\subsection{Simulation with Modelsim}
The behavior of this adder is verified in Modelsim. Following is a testbench for the adder, and also a screenshot for the waveform from the values provided by the testbench.
\lstinputlisting[frame=trbl]{../source/tbnadder.vhdl}
\newpage
\begin{figure}[htp]
\centering
\includegraphics[width = 6in]{../source/wave.jpg}
\caption{Simulation of the 24-bit adder with Modelsim for the testbench shown}
\end{figure}
As we can see, the values of a, b and cin at the point of the yellow line are 34545, 8990 and 1. The resulting sum is shown as 43536, which is correct. Even for the other values in the testbench, we can verify the adder is working fine.
\section{Behavioral Description for 24-bit Register}
The VHDL code for a 24-bit register is provided below.\\
\lstinputlisting[frame=trbl]{../source/reg.vhdl}
\section{Top-Level Netlist from 24-bit Adder and 24-bit Register}
\label{sec:netlist}
The VHDL code for the top-level netlist described in the exercise sheet, is provided below.\\
\lstinputlisting[frame=trbl]{../source/addernetlist.vhdl}
\newpage
\section{Synthesis Results}
The synthesis of the top-level netlist described in section \ref{sec:netlist} is done using Design Vision by Synopsys. We have synthesized the netlist for three different sets of clock time periods, which are 0.5, 1.0 and 2.0 ns. For each of these time periods, we have synthesized the netlist with and without constraints for low power. In the end, we have commented on the results obtained from the data gathered.
The power constraints for low power are 1 uW and 1 pW for maximum dynamic power and maximum leakage power respectively. This is done by using the following two commands (as is also shown in the exercise sheet):\\
\begin{lstlisting}[frame=trbl]{}
set_max_dynamic_power 1
set_max_leakage_power 1
\end{lstlisting}
\vspace{0.5cm}
For the synthesis in which no constraints are put on power, the values are kept at 10 mW and 30 uW for maximum dynamic power and maximum leakage power respectively.\\
\begin{lstlisting}[frame=trbl]{}
set_max_dynamic_power 10 mW
set_max_leakage_power 30 uW
\end{lstlisting}
\vspace{0.5cm}
In the following subsections, we give the results and comments of the synthesis for both the above mentioned power constraints. In the next section, we give comments for the change in area and power with respect to the different clock periods.
\newpage
\subsection{Clock Time Period = 0.5 ns}
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters} & \textbf{Values} & \textbf{Comment}\\ \hline
Dynamic Power & 5.91 mW & MET\\ \hline
Leakage Power & 11.04 uW & MET\\ \hline
Library Setup Time & 0.08 ns & - \\ \hline
Data Arrival Time & 0.43 ns & - \\ \hline
SLACK & -0.01 ns & VIOLATED \\ \hline
Combinational Area & 2700 um^2 & - \\ \hline
Non-Combinational Area & 1343 um^2 & - \\ \hline
SVT cells & 403 & - \\ \hline
HVT cells & 0 & - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 0.5 ns, normal power}
\label{tab:syn0.5.1}
\end{table}
Synthesis for low power:
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters} & \textbf{Values} & \textbf{Comment}\\ \hline
Dynamic Power & 5.29 mW & VIOLATED\\ \hline
Leakage Power & 9.22 uW & VIOLATED\\ \hline
Library Setup Time & 0.08 ns & - \\ \hline
Data Arrival Time & 0.44 ns & - \\ \hline
SLACK & -0.02 ns & VIOLATED \\ \hline
Combinational Area & 2345 um^2 & - \\ \hline
Non-Combinational Area & 1343 um^2 & - \\ \hline
SVT cells & 377 & - \\ \hline
HVT cells & 0 & - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 0.5 ns, low power}
\label{tab:syn0.5.2}
\end{table}
\newpage
\subsection{Clock Time Period = 1.0 ns}
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters} & \textbf{Values} & \textbf{Comment}\\ \hline
Dynamic Power & 2.76 mW & MET\\ \hline
Leakage Power & 11.25 uW & MET\\ \hline
Library Setup Time & 0.08 ns & - \\ \hline
Data Arrival Time & 0.89 ns & - \\ \hline
SLACK & 0.02 ns & MET\\ \hline
Combinational Area & 2335 um^2 & - \\ \hline
Non-Combinational Area & 1343 um^2 & - \\ \hline
SVT cells & 276 & - \\ \hline
HVT cells & 0 & - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 1.0 ns, normal power}
\label{tab:syn1.0.1}
\end{table}
Synthesis for low power:
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters} & \textbf{Values} & \textbf{Comment}\\ \hline
Dynamic Power & 1.71 mW & VIOLATED\\ \hline
Leakage Power & 2.98 uW & VIOLATED\\ \hline
Library Setup Time & 0.09 ns & - \\ \hline
Data Arrival Time & 0.90 ns & - \\ \hline
SLACK & 0.00 ns & MET\\ \hline
Combinational Area & 1089 um^2 & - \\ \hline
Non-Combinational Area & 1343 um^2 & - \\ \hline
SVT cells & 205 & - \\ \hline
HVT cells & 0 & - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 1.0 ns, low power}
\label{tab:syn1.0.2}
\end{table}
\newpage
\subsection{Clock Time Period = 2.0 ns}
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters} & \textbf{Values} & \textbf{Comment}\\ \hline
Dynamic Power & 0.896 mW & MET\\ \hline
Leakage Power & 3.51 uW & MET \\ \hline
Library Setup Time & 0.09 ns & - \\ \hline
Data Arrival Time & 1.87 ns & - \\ \hline
SLACK & 0.05 ns & MET \\ \hline
Combinational Area & 631 um^2 & - \\ \hline
Non-Combinational Area & 1343 um^2 & - \\ \hline
SVT cells & 97 & - \\ \hline
HVT cells & 0 & - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 2.0 ns, normal power}
\label{tab:syn2.0.1}
\end{table}
Synthesis for low power:
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters} & \textbf{Values} & \textbf{Comment}\\ \hline
Dynamic Power & 0.88 mW & MET\\ \hline
Leakage Power & 3.17 uW & VIOLATED\\ \hline
Library Setup Time & 0.09 ns & - \\ \hline
Data Arrival Time & 1.91 ns & - \\ \hline
SLACK & 0.00 ns & MET\\ \hline
Combinational Area & 614 um^2 & - \\ \hline
Non-Combinational Area & 1343 um^2 & - \\ \hline
SVT cells & 97 & - \\ \hline
HVT cells & 0 & - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 2.0 ns, low power}
\label{tab:syn2.0.2}
\end{table}
\newpage
\subsection{Comments}
Comments on synthesis results for low-power:
\begin{itemize}
\item For low power, the tool has tried to reduce the power to some extent. In some cases the constraint for the maximum dynamic power is met, while the constraint for maximum leakage power is never met.
\item The little reduction in the power with the low power constraints, is achieved by reducing the number of SVT cells in the design. This is because the SVT cells take more power as compared to the HVT cells. But since these cells are faster, reducing their number increases the delay in the circuit, as can be seen by an increase in the time of data arrival for all the three cases.
\item The combinational area reduces when synthesizing for low power. This can be explained with the reduction in the number of SVT cells.
\item We would have expected to see an increase in the number of HVT cells when synthesis is performed for low power, but it has not been the case. Of course, there is a reason for that. The number of SVT cells determined, are the ones on the critical path. Hence, no SVT cells from the critical path are replaced with HVT cells. Certain SVT cells are replaced with HVT cells, but outside the critical path.
\item For the clock time period of 2.0 ns, we note that there is no reduction in the number of SVT cells, when synthesized for low power. The reason for this is follows: for 2.0 ns, the circuit synthesized consists of sequential gates to perform the addition. In this case, there is very little scope of reducing the number of cells on the critical path, since the path is quite linear in flow. But the area is reduced very slightly, since some cells which are not on the critical path, are changed for low power.
\end{itemize}
\noindent Comments on variations observed by changing the clock time-period:
\begin{itemize}
\item The design is not synthesized successfully for the clock time period of 0.5 ns. The critical path in this case for the adder is 0.43 ns and adding the register setup and propagation delay time, the total time delay becomes greater than 0.5 ns. However, we see that the circuit is successfully synthesized for timing constraints of 1.0 ns and 2.0 ns.
\item The number of cells decreases with the increasing clock time period. So, as the constraint on the time period is reduced, the circuit is synthesized with lower number of cells. This is because the design is moving from parallel to sequential with an increase in clock time period constraint.
\item The area for the non-combinational circuit remains the same in all the cases. This is expected since the non-combinational circuit consists of three registers, which would have the same internal design on synthesis. The synthesis is mainly done for the internal design of the 24-bit adder, depending on the constraints of clock time period.
\item The area for the combinational circuit decreases with the increasing clock time period. This is because the number of cells decreases in the synthesized circuit.
\item The total power, including the dynamic power and the leakage power, decreases as the clocl time period is increased. Again, the reason for this is the decrease in the number of cells.
\end{itemize}
\end{document} | 02207-work-groupdt07 | trunk/Lab Work/Exercise 1/Report/dt07_lab1.tex | TeX | lgpl | 13,028 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal D : std_logic_vector (52 downto 0);
signal RESET : std_logic;
signal X : std_logic_vector (53 downto 0);
signal Qj : std_logic_vector (3 downto 0);
component divr4_rec
Port ( CLOCK : In std_logic;
D : In std_logic_vector (52 downto 0);
RESET : In std_logic;
X : In std_logic_vector (53 downto 0);
Qj : Out std_logic_vector (3 downto 0) );
end component;
begin
UUT : divr4_rec
Port Map ( CLOCK, D, RESET, X, Qj );
TB : block
begin
process
-- CONSTANT NLOOPS : integer := 15;
CONSTANT NLOOPS : integer := 30;
file cmdfile: TEXT; -- Define the file 'handle'
variable line_in,line_out: Line; -- Line buffers
variable good: boolean; -- Status of the read operations
variable A,B: std_logic_vector(55 downto 0);
variable S: std_logic_vector(55 downto 0);
variable Z: std_logic_vector(55 downto 0);
variable ERR: std_logic_vector(55 downto 0);
variable c : integer;
begin
c := 1;
FILE_OPEN(cmdfile,"testvecs1.in",READ_MODE);
-- -------------------------------------------------------------------------
loop
if endfile(cmdfile) then -- Check EOF
assert false
report "End of file encountered; exiting."
severity NOTE;
exit;
end if;
reset <= '0';
clock <= '1'; wait for 5 ns;
reset <= '1';
clock <= '0'; wait for 5 ns;
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
hread(line_in,A,good); -- Read the X argument as hex value
assert good report "Text I/O read error" severity ERROR;
hread(line_in,B,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
hread(line_in,S,good); -- Read the Q argument as hex value
assert good report "Text I/O read error" severity ERROR;
D(52 downto 0) <= B(52 downto 0);
X(53 downto 1) <= A(52 downto 0); X(0)<= '0';
for i in 0 to NLOOPS loop
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
end loop;
write(line_out, string'("Test "));
write(line_out,c);
write(line_out, string'(": "));
hwrite(line_out,A,RIGHT,14);
write(line_out, string'(" / "));
hwrite(line_out,B,RIGHT,14);
writeline(OUTPUT,line_out); -- write the message
c := c + 1;
end loop;
write(line_out, string'("--------- END SIMULATION ------------------"));
writeline(OUTPUT,line_out);
-- -------------------------------------------------------------------------
-- ===============================================================
clock <= '1'; wait for 1000 ns;
assert qj = "1111"
report "--------- END SIMULATION ------------------ " severity error;
-- ===============================================================
end process;
end block;
end A;
configuration CFG_TB_divr4_rec_BEHAVIORAL of E is
for A
for UUT : divr4_rec
use configuration WORK.CFG_divr4_rec_SCHEMATIC;
end for;
for TB
end for;
end for;
end CFG_TB_divr4_rec_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/tb_divr4_rec.vhd | VHDL | lgpl | 3,368 |
-- VHDL Model Created from SGE Symbol qds_table.sym -- Apr 21 16:34:54 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_TABLE is
Port ( D : In std_logic_vector (2 downto 0);
Y : In std_logic_vector (6 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end QDS_TABLE;
architecture BEHAVIORAL of QDS_TABLE is
begin
process(Y, D)
TYPE table_type IS ARRAY(0 to 3) OF std_logic_vector (6 downto 0);
CONSTANT sel_fun0 : table_type := (
"0001100", "0000100", "1111100", "1110011" );
CONSTANT sel_fun1 : table_type := (
"0001110", "0000100", "1111010", "1110001" );
CONSTANT sel_fun2 : table_type := (
"0001111", "0000100", "1111010", "1110000" );
CONSTANT sel_fun3 : table_type := (
"0010000", "0000100", "1111010", "1101110" );
CONSTANT sel_fun4 : table_type := (
"0010010", "0000110", "1111000", "1101100" );
CONSTANT sel_fun5 : table_type := (
"0010100", "0000110", "1111000", "1101100" );
CONSTANT sel_fun6 : table_type := (
"0010100", "0001000", "1111000", "1101010" );
CONSTANT sel_fun7 : table_type := (
"0011000", "0001000", "1111000", "1101000" );
begin
-- Selection function
if ( D = "000" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun0(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun0(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun0(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun0(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "001" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun1(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun1(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun1(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun1(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "010" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun2(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun2(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun2(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun2(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "011" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun3(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun3(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun3(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun3(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "100" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun4(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun4(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun4(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun4(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "101" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun5(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun5(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun5(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun5(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "110" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun6(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun6(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun6(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun6(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "111" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun7(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun7(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun7(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun7(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
end if;
end process;
end BEHAVIORAL;
configuration CFG_QDS_TABLE_BEHAVIORAL of QDS_TABLE is
for BEHAVIORAL
end for;
end CFG_QDS_TABLE_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/qds_table.vhd | VHDL | lgpl | 6,548 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_dualreg_ld is
GENERIC(n : integer);
Port ( AS : In std_logic_vector (n downto 0);
AC : In std_logic_vector (n downto 0);
RESET : In std_logic;
CLOCK : In std_logic;
LOAD : In std_logic;
ZS : Out std_logic_vector (n downto 0);
ZC : Out std_logic_vector (n downto 0) );
end gl_dualreg_ld;
architecture BEHAVIORAL of gl_dualreg_ld is
begin
process(reset,clock)
begin
if ( reset = '0' ) then
ZS <= (others => '0');
ZC <= (others => '0');
elsif (( clock = '1' ) and (clock'EVENT)) then
if ( load = '1' ) then
ZS <= AS ;
ZC <= AC ;
end if;
end if;
end process;
end BEHAVIORAL;
configuration CFG_gl_dualreg_ld_BEHAVIORAL of gl_dualreg_ld is
for BEHAVIORAL
end for;
end CFG_gl_dualreg_ld_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/gl_dualreg_ld.vhd | VHDL | lgpl | 978 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity divr4_rec is
Port ( CLOCK : In std_logic;
D : In std_logic_vector (52 downto 0);
RESET : In std_logic;
X : In std_logic_vector (53 downto 0);
Qj : Out std_logic_vector (3 downto 0) );
end divr4_rec;
architecture SCHEMATIC of divr4_rec is
signal Y1 : std_logic_vector(6 downto 0);
signal Y2 : std_logic_vector(6 downto 0);
signal D3 : std_logic_vector(2 downto 0);
signal DD : std_logic_vector(54 downto 0);
signal XX : std_logic_vector(56 downto 0);
signal W2 : std_logic_vector(56 downto 0);
signal W1 : std_logic_vector(56 downto 0);
signal SW2 : std_logic_vector(56 downto 0);
signal SW1 : std_logic_vector(56 downto 0);
signal WC : std_logic_vector(56 downto 0);
signal WS : std_logic_vector(56 downto 0);
signal MXLA : std_logic_vector(56 downto 0);
signal MXLB : std_logic_vector(56 downto 0);
signal qjD : std_logic_vector(56 downto 0);
signal M2, M1, P1, P2 : std_logic;
signal DIGIT, ROUND : std_logic;
signal muxW : std_logic;
signal CLR : std_logic;
signal LOAD : std_logic;
signal SIGN : std_logic;
signal qjD_c2 : std_logic;
signal GND : std_logic;
signal carry_ex : std_logic;
component CONTROL
Port ( CLOCK : In std_logic;
RESET : In std_logic;
CL1 : Out std_logic;
DIGIT : Out std_logic;
LD1 : Out std_logic;
MX1 : Out std_logic;
ROUND : Out std_logic );
end component;
component MUX
Port ( A : In std_logic_vector (56 downto 0);
B : In std_logic_vector (56 downto 0);
SEL : In std_logic;
Z : Out std_logic_vector (56 downto 0) );
end component;
component WLATCH
Port ( A1 : In std_logic_vector (56 downto 0);
A2 : In std_logic_vector (56 downto 0);
CLEAR : In std_logic;
CLK : In std_logic;
LOAD : In std_logic;
RWC : Out std_logic_vector (56 downto 0);
RWS : Out std_logic_vector (56 downto 0) );
end component;
component gl_csa32
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end component;
component csa32LSBs
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end component;
component gl_dualreg_ld
GENERIC(n : integer);
Port ( AS : In std_logic_vector (n downto 0);
AC : In std_logic_vector (n downto 0);
RESET : In std_logic;
CLOCK : In std_logic;
LOAD : In std_logic;
ZS : Out std_logic_vector (n downto 0);
ZC : Out std_logic_vector (n downto 0) );
end component;
component QDSEL
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
D : In std_logic_vector (2 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end component;
component MULT
Port ( A : In std_logic_vector (54 downto 0);
M1 : In std_logic;
M2 : In std_logic;
P1 : In std_logic;
P2 : In std_logic;
COUT : Out std_logic;
Z : Out std_logic_vector (56 downto 0) );
end component;
begin
GND <= '0';
-- divisor alignment
DD(54)<='0' ; DD(53 downto 1)<=D(52 downto 0); DD(0)<='0' ;
-- dividend alignment
XX(56)<='0'; XX(55)<='0'; XX(54)<='0'; XX(53 downto 0)<=X(53 downto 0);
-- bits of d and y going into SEL
D3(2 downto 0)<=D(51 downto 49);
Y1(6 downto 0)<=W1(56 downto 50);
Y2(6 downto 0)<=W2(56 downto 50);
I_CTRL : CONTROL
Port Map ( CLOCK=>CLOCK, RESET=>RESET, CL1=>CLR, DIGIT=>DIGIT,
LD1=>LOAD, MX1=>muxW, ROUND=>ROUND );
-- shift 2 left
SW1(56 downto 2)<=W1(54 downto 0) ; SW1(1)<='0'; SW1(0)<='0';
SW2(56 downto 2)<=W2(54 downto 0) ; SW2(1)<='0'; SW2(0)<='0';
-- MUX selecting either X (initialization) or Ws
I_MUX : MUX
Port Map ( A(56 downto 0)=>XX(56 downto 0),
B(56 downto 0)=>SW1(56 downto 0), SEL=>muxW,
Z(56 downto 0)=>MXLA(56 downto 0) );
-- mux 4:1 acting as multiplier q_j*d
I_MULT : MULT
Port Map ( A(54 downto 0)=>DD(54 downto 0),
M1=>M1, M2=>M2, P1=>P1, P2=>P2, COUT=>qjD_c2,
Z(56 downto 0)=>qjD(56 downto 0) );
-- CSA 3:2 is split into two slices
I_CSA1 : gl_csa32 Generic Map(n=>8)
Port Map ( A=>MXLA(56 downto 48),
B=>SW2(56 downto 48), CIN=>carry_ex,
C=>qjD(56 downto 48),
Y=>WC(56 downto 48),
Z=>WS(56 downto 48) );
I_CSA2 : csa32LSBs Generic Map(n=>47)
Port Map ( A=>MXLA(47 downto 0),
B=>SW2(47 downto 0), CIN=>qjD_c2,
C=>qjD(47 downto 0), Cout=>carry_ex,
Y=>WC(47 downto 0),
Z=>WS(47 downto 0) );
-- REG Ws and Wc are split into two slices
I_REG1 : gl_dualreg_ld Generic Map(n=>10)
Port Map ( AS=>WS(56 downto 46), AC=>WC(56 downto 46),
RESET=>CLR, CLOCK=>CLOCK, LOAD=>LOAD,
ZS=>W1(56 downto 46), ZC=>W2(56 downto 46) );
I_REG2 : gl_dualreg_ld Generic Map(n=>45)
Port Map ( AS=>WS(45 downto 0), AC=>WC(45 downto 0),
RESET=>CLR, CLOCK=>CLOCK, LOAD=>LOAD,
ZS=>W1(45 downto 0), ZC=>W2(45 downto 0) );
-- SELECTION FUNCTION
I_SEL : QDSEL
Port Map ( A1(6 downto 0)=>Y1(6 downto 0), A2(6 downto 0)=>Y2(6 downto 0),
D(2 downto 0)=>D3(2 downto 0),
M1=>M1, M2=>M2, P1=>P1, P2=>P2 );
QJ(3)<=M2;
QJ(2)<=M1;
QJ(1)<=P1;
QJ(0)<=P2;
end SCHEMATIC;
configuration CFG_divr4_rec_SCHEMATIC of divr4_rec is
for SCHEMATIC
for I_CTRL: CONTROL
use configuration WORK.CFG_CONTROL_BEHAVIORAL;
end for;
for I_MUX: MUX
use configuration WORK.CFG_MUX_BEHAVIORAL;
end for;
for I_REG1, I_REG2: gl_dualreg_ld
use configuration WORK.CFG_gl_dualreg_ld_BEHAVIORAL;
end for;
for I_CSA1: gl_csa32
use configuration WORK.CFG_GL_CSA32_BEHAVIORAL;
end for;
for I_CSA2: csa32LSBs
use configuration WORK.CFG_csa32LSBs_BEHAVIORAL;
end for;
for I_SEL: QDSEL
use configuration WORK.CFG_QDSEL_SCHEMATIC;
end for;
for I_MULT: MULT
use configuration WORK.CFG_MULT_BEHAVIORAL;
end for;
end for;
end CFG_divr4_rec_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/divr4_rec.vhd | VHDL | lgpl | 7,654 |
-- VHDL Model Created from SGE Symbol control.sym -- May 5 18:26:48 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity CONTROL is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
CL1 : Out std_logic;
DIGIT : Out std_logic;
LD1 : Out std_logic;
MX1 : Out std_logic;
ROUND : Out std_logic );
end CONTROL;
architecture BEHAVIORAL of CONTROL is
begin
process(reset,clock)
variable state : integer range 0 to 29;
begin
if ( reset = '0' ) then
CL1 <= '0';
LD1 <= '0';
DIGIT <= '0' ;
ROUND <= '1' ;
MX1 <= '1' ;
state := 0;
elsif ((clock'EVENT) AND ( clock = '1' )) then
if( 0 = state ) then
ROUND <= '0' ;
CL1 <= '1';
LD1 <= '1';
state := 1 ;
elsif( 1 = state ) then
DIGIT <= '1' ;
MX1 <= '0' ;
state := 2 ;
elsif( 29 = state ) then
DIGIT <= '0' ;
ROUND <= '1' ;
MX1 <= '1' ;
LD1 <= '0';
state := 0 ;
else
state := state + 1 ;
end if;
end if;
end process;
end BEHAVIORAL;
configuration CFG_CONTROL_BEHAVIORAL of CONTROL is
for BEHAVIORAL
end for;
end CFG_CONTROL_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/control.vhd | VHDL | lgpl | 1,523 |
-- VHDL Model Created from SGE Schematic qdsel.sch -- Apr 21 16:58:17 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDSEL is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
D : In std_logic_vector (2 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end QDSEL;
architecture SCHEMATIC of QDSEL is
signal Y : std_logic_vector(6 downto 0);
component QDS_TABLE
Port ( D : In std_logic_vector (2 downto 0);
Y : In std_logic_vector (6 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end component;
component QDS_ADDER
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
Y : Out std_logic_vector (6 downto 0) );
end component;
begin
I_1 : QDS_TABLE
Port Map ( D(2 downto 0)=>D(2 downto 0),
Y(6 downto 0)=>Y(6 downto 0), M1=>M1, M2=>M2, P1=>P1,
P2=>P2 );
I_2 : QDS_ADDER
Port Map ( A1(6 downto 0)=>A1(6 downto 0),
A2(6 downto 0)=>A2(6 downto 0),
Y(6 downto 0)=>Y(6 downto 0) );
end SCHEMATIC;
configuration CFG_QDSEL_SCHEMATIC of QDSEL is
for SCHEMATIC
for I_1: QDS_TABLE
use configuration WORK.CFG_QDS_TABLE_BEHAVIORAL;
end for;
for I_2: QDS_ADDER
use configuration WORK.CFG_QDS_ADDER_BEHAVIORAL;
end for;
end for;
end CFG_QDSEL_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/qdsel.vhd | VHDL | lgpl | 1,846 |
open run.out
logtime -e run.out
monitor -n Smon active *E/X'sig
monitor -n Smon active *E/D'sig
--monitor -n Smon active *E/Qj'sig
-- monitor -n Smon active *E/UUT/WS'sig
-- monitor -n Smon active *E/UUT/WC'sig
list > run.out
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/cmd.inc | C++ | lgpl | 266 |
-- VHDL Model Created from SGE Symbol mult.sym -- May 27 12:32:12 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MULT is
Port ( A : In std_logic_vector (54 downto 0);
M1 : In std_logic;
M2 : In std_logic;
P1 : In std_logic;
P2 : In std_logic;
COUT : Out std_logic;
Z : Out std_logic_vector (56 downto 0) );
end MULT;
architecture BEHAVIORAL of MULT is
begin
process (M1, M2, P1, P2, A)
variable pd : std_logic;
begin
Z(0) <= M1 OR M2;
Z(1) <= M1 OR M2;
pd := '0';
for i in 0 to 53 loop
Z(i+2) <= ( M2 AND NOT(pd) ) OR ( M1 AND NOT(A(i)) ) OR
( P1 AND A(i) ) OR ( P2 AND pd ) ;
pd := A(i);
end loop;
Z(56) <= ( pd AND P2 ) OR ( NOT(pd) AND M2 ) OR M1;
cout <= M1 or M2 ;
end process;
end BEHAVIORAL;
configuration CFG_MULT_BEHAVIORAL of MULT is
for BEHAVIORAL
end for;
end CFG_MULT_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/mult.vhd | VHDL | lgpl | 1,093 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_divr4_rec is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_divr4_rec;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity CONTROL_DW01_inc_0 is
port( A : in std_logic_vector (4 downto 0); SUM : out std_logic_vector (4
downto 0));
end CONTROL_DW01_inc_0;
architecture SYN_rpl of CONTROL_DW01_inc_0 is
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component HA1SVTX8
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_4_port, carry_3_port, carry_2_port : std_logic;
begin
U5 : EOHVTX1 port map( A => carry_4_port, B => A(4), Z => SUM(4));
U6 : IVHVTX0H port map( A => A(0), Z => SUM(0));
U1_1_1 : HA1SVTX8 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1_1_2 : HA1SVTX8 port map( A => A(2), B => carry_2_port, CO => carry_3_port
, S => SUM(2));
U1_1_3 : HA1SVTX8 port map( A => A(3), B => carry_3_port, CO => carry_4_port
, S => SUM(3));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity CONTROL is
port( CLOCK, RESET : in std_logic; CL1, DIGIT, LD1, MX1, ROUND : out
std_logic);
end CONTROL;
architecture SYN_BEHAVIORAL of CONTROL is
component NR2AHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO6HVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND2AHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO17HVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO20NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component ENHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO6NHVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO7AHVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND4HVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component OR2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component AO2NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX2
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component FD4QSVTX1
port( CP, D : in std_logic; Q : out std_logic; SD : in std_logic);
end component;
component FD2QNSVTX1
port( CD, CP, D : in std_logic; QN : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component FD2QNSVTX4
port( CD, CP, D : in std_logic; QN : out std_logic);
end component;
component EOSVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component FD2QNSVTX2
port( CD, CP, D : in std_logic; QN : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component AN2BSVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR3SVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component FD4QSVTX4
port( CP, D : in std_logic; Q : out std_logic; SD : in std_logic);
end component;
component CONTROL_DW01_inc_0
port( A : in std_logic_vector (4 downto 0); SUM : out std_logic_vector
(4 downto 0));
end component;
signal DIGIT_port, MX1_port, ROUND_port, state_4_port, state_2_port,
state_1_port, state_0_port, ROUND135, state162_4_port, state162_3_port,
state162_2_port, state162_1_port, state162_0_port, sum366_4_port,
sum366_3_port, sum366_2_port, sum366_1_port, sum366_0_port, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, n416, CL1_port, n418, LD1_port : std_logic;
begin
CL1 <= CL1_port;
DIGIT <= DIGIT_port;
LD1 <= LD1_port;
MX1 <= MX1_port;
ROUND <= ROUND_port;
U157 : NR2AHVTX1 port map( A => sum366_4_port, B => n398, Z =>
state162_4_port);
U158 : NR2AHVTX1 port map( A => sum366_3_port, B => n398, Z =>
state162_3_port);
U159 : NR2AHVTX1 port map( A => sum366_2_port, B => n398, Z =>
state162_2_port);
U160 : AO6HVTX1 port map( A => n415, B => n399, C => n400, Z => n398);
U161 : ND2AHVTX1 port map( A => n401, B => n402, Z => state162_1_port);
U162 : AO17HVTX1 port map( A => n403, B => n415, C => n400, D =>
sum366_1_port, Z => n402);
U163 : AO20NHVTX1 port map( A => n400, B => n415, C => sum366_0_port, D =>
n404, Z => state162_0_port);
U164 : ND2HVTX1 port map( A => n405, B => n414, Z => n400);
U165 : ENHVTX1 port map( A => n403, B => n399, Z => n405);
U166 : AO6NHVTX1 port map( A => DIGIT_port, B => n406, C => n401, Z => n409)
;
U167 : AO7AHVTX1 port map( A => MX1_port, B => n401, C => n406, Z => n410);
U168 : NR2AHVTX1 port map( A => n407, B => n415, Z => n401);
U169 : AO7AHVTX1 port map( A => ROUND_port, B => n404, C => n406, Z => n411)
;
U170 : AO6NHVTX1 port map( A => LD1_port, B => n406, C => n404, Z => n412);
U171 : ND4HVTX1 port map( A => n399, B => n403, C => n414, D => state_0_port
, Z => n406);
U172 : OR2HVTX1 port map( A => n404, B => CL1_port, Z => n413);
U174 : IVHVTX0H port map( A => n415, Z => state_0_port);
U176 : AO2NHVTX1 port map( A => state_2_port, B => ROUND135, C => n408, D =>
state_4_port, Z => n403);
U177 : IVHVTX0H port map( A => n414, Z => state_1_port);
U178 : EOHVTX1 port map( A => n408, B => state_4_port, Z => n399);
DIGIT_reg : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n409, Q =>
DIGIT_port);
ROUND_reg : FD4QSVTX1 port map( CP => CLOCK, D => n411, Q => ROUND_port, SD
=> RESET);
state_reg_4_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D =>
state162_4_port, Q => state_4_port);
state_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D =>
state162_3_port, Q => ROUND135);
state_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D =>
state162_2_port, Q => state_2_port);
state_reg_1_inst : FD2QNSVTX1 port map( CD => RESET, CP => CLOCK, D =>
state162_1_port, QN => n414);
state_reg_0_inst : FD2QNSVTX1 port map( CD => RESET, CP => CLOCK, D =>
state162_0_port, QN => n415);
U180 : IVSVTX12 port map( A => n418, Z => LD1_port);
LD1_reg : FD2QNSVTX4 port map( CD => RESET, CP => CLOCK, D => n412, QN =>
n418);
U181 : EOSVTX1 port map( A => state_2_port, B => ROUND135, Z => n408);
CL1_reg : FD2QNSVTX2 port map( CD => RESET, CP => CLOCK, D => n413, QN =>
n416);
U182 : IVSVTX8 port map( A => n416, Z => CL1_port);
U183 : AN2BSVTX1 port map( A => n407, B => state_0_port, Z => n404);
U184 : NR3SVTX1 port map( A => n399, B => state_1_port, C => n403, Z => n407
);
MX1_reg : FD4QSVTX4 port map( CP => CLOCK, D => n410, Q => MX1_port, SD =>
RESET);
add_54 : CONTROL_DW01_inc_0 port map( A(4) => state_4_port, A(3) => ROUND135
, A(2) => state_2_port, A(1) => state_1_port, A(0)
=> state_0_port, SUM(4) => sum366_4_port, SUM(3) =>
sum366_3_port, SUM(2) => sum366_2_port, SUM(1) =>
sum366_1_port, SUM(0) => sum366_0_port);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity MUX is
port( A, B : in std_logic_vector (56 downto 0); SEL : in std_logic; Z :
out std_logic_vector (56 downto 0));
end MUX;
architecture SYN_BEHAVIORAL of MUX is
component AO2NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
signal n5 : std_logic;
begin
U10 : AO2NHVTX1 port map( A => B(9), B => n5, C => SEL, D => A(9), Z => Z(9)
);
U11 : AO2NHVTX1 port map( A => B(8), B => n5, C => A(8), D => SEL, Z => Z(8)
);
U12 : AO2NHVTX1 port map( A => B(7), B => n5, C => A(7), D => SEL, Z => Z(7)
);
U13 : AO2NHVTX1 port map( A => B(6), B => n5, C => A(6), D => SEL, Z => Z(6)
);
U14 : AO2NHVTX1 port map( A => B(5), B => n5, C => A(5), D => SEL, Z => Z(5)
);
U15 : AO2NHVTX1 port map( A => B(56), B => n5, C => A(56), D => SEL, Z =>
Z(56));
U16 : AO2NHVTX1 port map( A => B(55), B => n5, C => A(55), D => SEL, Z =>
Z(55));
U17 : AO2NHVTX1 port map( A => B(54), B => n5, C => A(54), D => SEL, Z =>
Z(54));
U18 : AO2NHVTX1 port map( A => B(53), B => n5, C => A(53), D => SEL, Z =>
Z(53));
U19 : AO2NHVTX1 port map( A => B(52), B => n5, C => A(52), D => SEL, Z =>
Z(52));
U20 : AO2NHVTX1 port map( A => B(51), B => n5, C => A(51), D => SEL, Z =>
Z(51));
U21 : AO2NHVTX1 port map( A => B(50), B => n5, C => A(50), D => SEL, Z =>
Z(50));
U22 : AO2NHVTX1 port map( A => B(4), B => n5, C => A(4), D => SEL, Z => Z(4)
);
U23 : AO2NHVTX1 port map( A => B(49), B => n5, C => A(49), D => SEL, Z =>
Z(49));
U24 : AO2NHVTX1 port map( A => B(48), B => n5, C => A(48), D => SEL, Z =>
Z(48));
U25 : AO2NHVTX1 port map( A => B(47), B => n5, C => A(47), D => SEL, Z =>
Z(47));
U26 : AO2NHVTX1 port map( A => B(46), B => n5, C => A(46), D => SEL, Z =>
Z(46));
U27 : AO2NHVTX1 port map( A => B(45), B => n5, C => A(45), D => SEL, Z =>
Z(45));
U28 : AO2NHVTX1 port map( A => B(44), B => n5, C => A(44), D => SEL, Z =>
Z(44));
U29 : AO2NHVTX1 port map( A => B(43), B => n5, C => A(43), D => SEL, Z =>
Z(43));
U30 : AO2NHVTX1 port map( A => B(42), B => n5, C => A(42), D => SEL, Z =>
Z(42));
U31 : AO2NHVTX1 port map( A => B(41), B => n5, C => A(41), D => SEL, Z =>
Z(41));
U32 : AO2NHVTX1 port map( A => B(40), B => n5, C => A(40), D => SEL, Z =>
Z(40));
U33 : AO2NHVTX1 port map( A => B(3), B => n5, C => A(3), D => SEL, Z => Z(3)
);
U34 : AO2NHVTX1 port map( A => B(39), B => n5, C => A(39), D => SEL, Z =>
Z(39));
U35 : AO2NHVTX1 port map( A => B(38), B => n5, C => A(38), D => SEL, Z =>
Z(38));
U36 : AO2NHVTX1 port map( A => B(37), B => n5, C => A(37), D => SEL, Z =>
Z(37));
U37 : AO2NHVTX1 port map( A => B(36), B => n5, C => A(36), D => SEL, Z =>
Z(36));
U38 : AO2NHVTX1 port map( A => B(35), B => n5, C => A(35), D => SEL, Z =>
Z(35));
U39 : AO2NHVTX1 port map( A => B(34), B => n5, C => A(34), D => SEL, Z =>
Z(34));
U40 : AO2NHVTX1 port map( A => B(33), B => n5, C => A(33), D => SEL, Z =>
Z(33));
U41 : AO2NHVTX1 port map( A => B(32), B => n5, C => A(32), D => SEL, Z =>
Z(32));
U42 : AO2NHVTX1 port map( A => B(31), B => n5, C => A(31), D => SEL, Z =>
Z(31));
U43 : AO2NHVTX1 port map( A => B(30), B => n5, C => A(30), D => SEL, Z =>
Z(30));
U44 : AO2NHVTX1 port map( A => B(2), B => n5, C => A(2), D => SEL, Z => Z(2)
);
U45 : AO2NHVTX1 port map( A => B(29), B => n5, C => A(29), D => SEL, Z =>
Z(29));
U46 : AO2NHVTX1 port map( A => B(28), B => n5, C => A(28), D => SEL, Z =>
Z(28));
U47 : AO2NHVTX1 port map( A => B(27), B => n5, C => A(27), D => SEL, Z =>
Z(27));
U48 : AO2NHVTX1 port map( A => B(26), B => n5, C => A(26), D => SEL, Z =>
Z(26));
U49 : AO2NHVTX1 port map( A => B(25), B => n5, C => A(25), D => SEL, Z =>
Z(25));
U50 : AO2NHVTX1 port map( A => B(24), B => n5, C => A(24), D => SEL, Z =>
Z(24));
U51 : AO2NHVTX1 port map( A => B(23), B => n5, C => A(23), D => SEL, Z =>
Z(23));
U52 : AO2NHVTX1 port map( A => B(22), B => n5, C => A(22), D => SEL, Z =>
Z(22));
U53 : AO2NHVTX1 port map( A => B(21), B => n5, C => A(21), D => SEL, Z =>
Z(21));
U54 : AO2NHVTX1 port map( A => B(20), B => n5, C => A(20), D => SEL, Z =>
Z(20));
U55 : AO2NHVTX1 port map( A => B(1), B => n5, C => A(1), D => SEL, Z => Z(1)
);
U56 : AO2NHVTX1 port map( A => B(19), B => n5, C => A(19), D => SEL, Z =>
Z(19));
U57 : AO2NHVTX1 port map( A => B(18), B => n5, C => A(18), D => SEL, Z =>
Z(18));
U58 : AO2NHVTX1 port map( A => B(17), B => n5, C => A(17), D => SEL, Z =>
Z(17));
U59 : AO2NHVTX1 port map( A => B(16), B => n5, C => A(16), D => SEL, Z =>
Z(16));
U60 : AO2NHVTX1 port map( A => B(15), B => n5, C => A(15), D => SEL, Z =>
Z(15));
U61 : AO2NHVTX1 port map( A => B(14), B => n5, C => A(14), D => SEL, Z =>
Z(14));
U62 : AO2NHVTX1 port map( A => B(13), B => n5, C => A(13), D => SEL, Z =>
Z(13));
U63 : AO2NHVTX1 port map( A => B(12), B => n5, C => A(12), D => SEL, Z =>
Z(12));
U64 : AO2NHVTX1 port map( A => B(11), B => n5, C => A(11), D => SEL, Z =>
Z(11));
U65 : AO2NHVTX1 port map( A => B(10), B => n5, C => A(10), D => SEL, Z =>
Z(10));
U66 : AO2NHVTX1 port map( A => B(0), B => n5, C => A(0), D => SEL, Z => Z(0)
);
U68 : IVSVTX12 port map( A => SEL, Z => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity MULT is
port( A : in std_logic_vector (54 downto 0); M1, M2, P1, P2 : in std_logic;
COUT : out std_logic; Z : out std_logic_vector (56 downto 0));
end MULT;
architecture SYN_BEHAVIORAL of MULT is
component AO2HVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component ND2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2HVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO23SVTX6
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO2HVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component AO23SVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component IVSVTX10
port( A : in std_logic; Z : out std_logic);
end component;
component AO2SVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component NR2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2SVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component OR2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND3SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AN2SVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component NR3SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVHVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component ND3SVTX6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AN2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component ND2SVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component AO2SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AN2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2ASVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2SVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component AO23SVTX8
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO2ASVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO10NSVTX8
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO23NSVTX8
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component ND2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND3SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVHVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component OR2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVHVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component BFSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component OR2SVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component OR2SVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO10NSVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component NR2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component BFSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component AO23SVTX2
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
signal Z_56_port, Z_55_port, Z_54_port, Z_53_port, Z_52_port, Z_51_port,
Z_50_port, Z_49_port, Z_48_port, Z_47_port, Z_46_port, Z_45_port,
Z_44_port, Z_43_port, Z_42_port, Z_41_port, Z_40_port, n235, Z_37_port,
Z_36_port, Z_35_port, Z_34_port, Z_33_port, Z_32_port, Z_31_port,
Z_30_port, Z_29_port, Z_28_port, Z_27_port, Z_26_port, Z_25_port,
Z_24_port, Z_23_port, Z_22_port, Z_21_port, Z_20_port, Z_19_port,
Z_18_port, Z_17_port, Z_16_port, Z_15_port, Z_14_port, Z_13_port,
Z_12_port, Z_11_port, Z_10_port, Z_9_port, Z_8_port, Z_7_port, Z_6_port,
Z_5_port, Z_4_port, Z_3_port, Z_2_port, Z_0_port, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45
, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74
, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n89,
n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139,
n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151,
n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163,
n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187,
n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, Z_38_port, n220, Z_39_port,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234 : std_logic;
begin
COUT <= Z_0_port;
Z <= ( Z_56_port, Z_55_port, Z_54_port, Z_53_port, Z_52_port, Z_51_port,
Z_50_port, Z_49_port, Z_48_port, Z_47_port, Z_46_port, Z_45_port,
Z_44_port, Z_43_port, Z_42_port, Z_41_port, Z_40_port, Z_39_port,
Z_38_port, Z_37_port, Z_36_port, Z_35_port, Z_34_port, Z_33_port,
Z_32_port, Z_31_port, Z_30_port, Z_29_port, Z_28_port, Z_27_port,
Z_26_port, Z_25_port, Z_24_port, Z_23_port, Z_22_port, Z_21_port,
Z_20_port, Z_19_port, Z_18_port, Z_17_port, Z_16_port, Z_15_port,
Z_14_port, Z_13_port, Z_12_port, Z_11_port, Z_10_port, Z_9_port, Z_8_port
, Z_7_port, Z_6_port, Z_5_port, Z_4_port, Z_3_port, Z_2_port, Z_0_port,
Z_0_port );
U11 : IVHVTX0H port map( A => A(6), Z => n16);
U20 : IVHVTX0H port map( A => A(3), Z => n24);
U24 : IVHVTX0H port map( A => A(53), Z => n27);
U27 : IVHVTX0H port map( A => A(52), Z => n29);
U30 : IVHVTX0H port map( A => A(51), Z => n31);
U33 : IVHVTX0H port map( A => A(50), Z => n33);
U36 : IVHVTX0H port map( A => A(49), Z => n35);
U39 : IVHVTX0H port map( A => A(48), Z => n37);
U48 : IVHVTX0H port map( A => A(46), Z => n43);
U51 : IVHVTX0H port map( A => A(45), Z => n45);
U54 : IVHVTX0H port map( A => A(44), Z => n47);
U57 : IVHVTX0H port map( A => A(43), Z => n49);
U60 : IVHVTX0H port map( A => A(42), Z => n51);
U63 : IVHVTX0H port map( A => A(41), Z => n53);
U78 : IVHVTX0H port map( A => A(37), Z => n61);
U81 : IVHVTX0H port map( A => A(36), Z => n65);
U84 : IVHVTX0H port map( A => A(35), Z => n67);
U87 : IVHVTX0H port map( A => A(34), Z => n69);
U90 : IVHVTX0H port map( A => A(33), Z => n71);
U93 : IVHVTX0H port map( A => A(32), Z => n73);
U99 : IVHVTX0H port map( A => A(30), Z => n77);
U102 : IVHVTX0H port map( A => A(29), Z => n79);
U105 : IVHVTX0H port map( A => A(28), Z => n81);
U107 : IVHVTX0H port map( A => A(0), Z => n63);
U110 : IVHVTX0H port map( A => A(27), Z => n83);
U113 : IVHVTX0H port map( A => A(26), Z => n85);
U122 : IVHVTX0H port map( A => A(23), Z => n91);
U128 : IVHVTX0H port map( A => A(21), Z => n95);
U131 : IVHVTX0H port map( A => A(20), Z => n97);
U137 : IVHVTX0H port map( A => A(18), Z => n101);
U140 : IVHVTX0H port map( A => A(17), Z => n103);
U143 : IVHVTX0H port map( A => A(16), Z => n105);
U146 : IVHVTX0H port map( A => A(15), Z => n107);
U161 : IVHVTX0H port map( A => A(10), Z => n117);
U165 : IVHVTX0H port map( A => A(9), Z => n118);
U168 : IVHVTX0H port map( A => A(7), Z => n13);
U169 : IVHVTX0H port map( A => A(8), Z => n121);
U174 : AN2HVTX2 port map( A => A(23), B => n234, Z => n206);
U175 : AO23SVTX6 port map( A => A(13), B => n211, C => n176, D => n111, E =>
n112, Z => Z_15_port);
U176 : AO2HVTX4 port map( A => n209, B => n16, C => n223, D => A(6), Z =>
n20);
U177 : IVSVTX8 port map( A => n209, Z => n211);
U178 : AO23SVTX4 port map( A => A(15), B => n212, C => n174, D => n107, E =>
n108, Z => Z_17_port);
U179 : IVSVTX10 port map( A => n12, Z => n209);
U180 : AO23SVTX4 port map( A => A(35), B => n210, C => n150, D => n67, E =>
n68, Z => Z_37_port);
U181 : AO23SVTX4 port map( A => A(9), B => n210, C => n14, D => n118, E =>
n120, Z => Z_11_port);
U182 : AO23SVTX4 port map( A => A(53), B => n210, C => n147, D => n27, E =>
n28, Z => Z_55_port);
U183 : AO23SVTX6 port map( A => A(16), B => n212, C => n14, D => n105, E =>
n106, Z => Z_18_port);
U184 : AO23SVTX4 port map( A => A(45), B => n212, C => n226, D => n45, E =>
n46, Z => Z_47_port);
U185 : AO23SVTX4 port map( A => A(8), B => n212, C => n176, D => n121, E =>
n122, Z => Z_10_port);
U186 : AO23SVTX6 port map( A => A(21), B => n212, C => n176, D => n95, E =>
n96, Z => Z_23_port);
U187 : AO2SVTX4 port map( A => n228, B => n121, C => A(8), D => n232, Z =>
n120);
U188 : NR2SVTX2 port map( A => A(22), B => n211, Z => n137);
U189 : AO4ABSVTX6 port map( A => A(24), B => n232, C => n233, D => A(24), Z
=> n128);
U190 : AO2SVTX6 port map( A => A(20), B => n229, C => n123, D => n231, Z =>
n96);
U191 : IVSVTX12 port map( A => A(20), Z => n123);
U192 : IVSVTX8 port map( A => M2, Z => n233);
U193 : OR2SVTX4 port map( A => A(19), B => n210, Z => n124);
U194 : OR2SVTX4 port map( A => n176, B => n99, Z => n125);
U195 : ND3SVTX8 port map( A => n124, B => n125, C => n100, Z => Z_21_port);
U196 : AN2SVTX1 port map( A => n227, B => n101, Z => n126);
U197 : AN2HVTX1 port map( A => A(18), B => P2, Z => n127);
U198 : NR2SVTX4 port map( A => n126, B => n127, Z => n100);
U199 : IVSVTX2 port map( A => A(19), Z => n99);
U200 : IVSVTX1 port map( A => n223, Z => n143);
U201 : AO23SVTX6 port map( A => A(50), B => n212, C => n176, D => n33, E =>
n216, Z => Z_52_port);
U202 : NR3SVTX4 port map( A => n137, B => n138, C => n139, Z => n170);
U203 : IVSVTX1 port map( A => n94, Z => n139);
U204 : IVHVTX4 port map( A => P1, Z => n175);
U205 : OR2SVTX4 port map( A => A(1), B => n210, Z => n129);
U206 : OR2SVTX4 port map( A => n176, B => n41, Z => n130);
U207 : ND3SVTX6 port map( A => n129, B => n130, C => n62, Z => Z_3_port);
U208 : AN2SVTX2 port map( A => n228, B => n63, Z => n131);
U209 : AN2SVTX2 port map( A => A(0), B => n234, Z => n132);
U210 : NR2SVTX4 port map( A => n131, B => n132, Z => n62);
U211 : IVSVTX0H port map( A => A(1), Z => n41);
U212 : OR2SVTX4 port map( A => A(7), B => n212, Z => n133);
U213 : OR2SVTX4 port map( A => n13, B => n176, Z => n134);
U214 : ND3SVTX8 port map( A => n133, B => n134, C => n15, Z => Z_9_port);
U215 : ND2SVTX1 port map( A => n227, B => n16, Z => n135);
U216 : ND2SVTX2 port map( A => n232, B => A(6), Z => n136);
U217 : AN2SVTX2 port map( A => n135, B => n136, Z => n15);
U218 : NR2SVTX2 port map( A => n176, B => n93, Z => n138);
U219 : IVSVTX0H port map( A => A(22), Z => n93);
U220 : AO2HVTX1 port map( A => n231, B => n95, C => A(21), D => P2, Z => n94
);
U221 : IVSVTX4 port map( A => n170, Z => Z_24_port);
U222 : AO23SVTX6 port map( A => A(5), B => n233, C => n145, D => n19, E =>
n20, Z => Z_8_port);
U223 : AO2SVTX2 port map( A => n231, B => n37, C => A(48), D => P2, Z => n36
);
U224 : ND2SVTX2 port map( A => n227, B => n29, Z => n140);
U225 : ND2HVTX1 port map( A => A(52), B => P2, Z => n141);
U226 : AN2SVTX4 port map( A => n140, B => n141, Z => n28);
U227 : AN2SVTX2 port map( A => A(11), B => n232, Z => n162);
U228 : IVSVTX2 port map( A => n70, Z => n178);
U229 : AO2ASVTX2 port map( A => n148, B => n234, C => n227, D => n109, Z =>
n108);
U230 : AO23SVTX4 port map( A => A(11), B => n212, C => n147, D => n115, E =>
n116, Z => Z_13_port);
U231 : ND3SVTX8 port map( A => n184, B => n185, C => n64, Z => n235);
U232 : OR2SVTX4 port map( A => n222, B => n61, Z => n185);
U233 : AO2SVTX1 port map( A => n227, B => n65, C => A(36), D => P2, Z => n64
);
U234 : IVSVTX1 port map( A => n228, Z => n142);
U235 : IVSVTX6 port map( A => n222, Z => n223);
U236 : AO23SVTX6 port map( A => A(42), B => n212, C => n177, D => n51, E =>
n52, Z => Z_44_port);
U237 : AO23SVTX8 port map( A => A(51), B => n211, C => n150, D => n31, E =>
n32, Z => Z_53_port);
U238 : AO23SVTX4 port map( A => A(43), B => n212, C => n177, D => n49, E =>
n50, Z => Z_45_port);
U239 : AO2ASVTX4 port map( A => A(42), B => n228, C => n234, D => A(42), Z
=> n50);
U240 : NR2SVTX4 port map( A => n190, B => n189, Z => n40);
U241 : ND2HVTX1 port map( A => n231, B => n111, Z => n151);
U242 : AO2ASVTX4 port map( A => n144, B => n229, C => n231, D => n13, Z =>
n122);
U243 : ND2HVTX1 port map( A => n231, B => n22, Z => n193);
U244 : AN2SVTX1 port map( A => n231, B => n41, Z => n189);
U245 : IVSVTX12 port map( A => A(7), Z => n144);
U246 : AO2SVTX2 port map( A => n231, B => n103, C => n232, D => A(17), Z =>
n102);
U247 : AO10NSVTX8 port map( A => n228, B => n27, C => A(53), D => n234, E =>
n188, Z => Z_56_port);
U248 : AO23SVTX6 port map( A => A(44), B => n210, C => n147, D => n47, E =>
n48, Z => Z_46_port);
U249 : IVSVTX6 port map( A => n165, Z => Z_38_port);
U250 : AO23NSVTX8 port map( A => A(36), B => n212, C => n147, D => n65, E =>
n66, Z => n165);
U251 : ND2SVTX4 port map( A => n142, B => n210, Z => Z_0_port);
U252 : ND3SVTX4 port map( A => n217, B => n42, C => n218, Z => Z_49_port);
U253 : IVHVTX1 port map( A => n229, Z => n145);
U254 : IVSVTX10 port map( A => P2, Z => n18);
U255 : IVSVTX4 port map( A => n175, Z => n146);
U256 : IVSVTX6 port map( A => n146, Z => n147);
U257 : IVSVTX12 port map( A => A(14), Z => n148);
U258 : AO23SVTX6 port map( A => A(4), B => n211, C => n177, D => n22, E =>
n23, Z => Z_6_port);
U259 : OR2SVTX6 port map( A => A(24), B => n210, Z => n207);
U260 : IVHVTX2 port map( A => n233, Z => n149);
U261 : AO23SVTX6 port map( A => A(27), B => n210, C => n150, D => n83, E =>
n84, Z => Z_29_port);
U262 : IVSVTX6 port map( A => n223, Z => n150);
U263 : IVSVTX4 port map( A => n155, Z => n32);
U264 : AO4ASVTX2 port map( A => P2, B => n156, C => n17, D => A(50), Z =>
n155);
U265 : ND3SVTX8 port map( A => n163, B => n164, C => n114, Z => Z_14_port);
U266 : IVSVTX10 port map( A => M2, Z => n17);
U267 : IVHVTX2 port map( A => P1, Z => n14);
U268 : IVSVTX12 port map( A => P1, Z => n176);
U269 : ND3SVTX8 port map( A => n224, B => n225, C => n80, Z => Z_31_port);
U270 : AO2SVTX2 port map( A => n227, B => n67, C => A(35), D => P2, Z => n66
);
U271 : BFSVTX4 port map( A => n176, Z => n226);
U272 : AO2SVTX2 port map( A => n149, B => n107, C => A(15), D => n229, Z =>
n106);
U273 : OR2SVTX6 port map( A => n176, B => n26, Z => n187);
U274 : IVSVTX12 port map( A => n233, Z => n228);
U275 : OR2SVTX1 port map( A => A(9), B => n17, Z => n182);
U276 : IVSVTX2 port map( A => P1, Z => n174);
U277 : IVSVTX12 port map( A => n18, Z => n232);
U278 : OR2SVTX8 port map( A => A(29), B => n212, Z => n224);
U279 : OR2SVTX6 port map( A => A(25), B => n210, Z => n180);
U280 : OR2SVTX4 port map( A => n174, B => n39, Z => n218);
U281 : AO2SVTX2 port map( A => n231, B => n24, C => A(3), D => n234, Z =>
n23);
U282 : AO23SVTX8 port map( A => A(32), B => n210, C => n14, D => n73, E =>
n74, Z => Z_34_port);
U283 : AO10NSVTX4 port map( A => n209, B => n63, C => A(0), D => n223, E =>
n228, Z => Z_2_port);
U284 : IVSVTX1 port map( A => n12, Z => n188);
U285 : ND2HVTX1 port map( A => A(13), B => P2, Z => n152);
U286 : AN2SVTX2 port map( A => n151, B => n152, Z => n110);
U287 : OR2SVTX4 port map( A => A(14), B => n210, Z => n153);
U288 : OR2SVTX4 port map( A => n176, B => n109, Z => n154);
U289 : ND3SVTX8 port map( A => n153, B => n154, C => n110, Z => Z_16_port);
U290 : IVSVTX2 port map( A => A(13), Z => n111);
U291 : IVSVTX2 port map( A => A(14), Z => n109);
U292 : AO23SVTX4 port map( A => A(49), B => n211, C => n176, D => n35, E =>
n36, Z => Z_51_port);
U293 : IVSVTX12 port map( A => A(50), Z => n156);
U294 : ND2SVTX2 port map( A => n228, B => n57, Z => n157);
U295 : ND2HVTX1 port map( A => A(39), B => n229, Z => n158);
U296 : AN2SVTX4 port map( A => n157, B => n158, Z => n56);
U297 : OR2SVTX4 port map( A => A(40), B => n212, Z => n159);
U298 : OR2SVTX4 port map( A => n176, B => n55, Z => n160);
U299 : ND3SVTX8 port map( A => n159, B => n160, C => n56, Z => Z_42_port);
U300 : IVSVTX2 port map( A => A(39), Z => n57);
U301 : IVSVTX2 port map( A => A(40), Z => n55);
U302 : AO23SVTX4 port map( A => A(26), B => n212, C => n174, D => n85, E =>
n86, Z => Z_28_port);
U303 : AO2SVTX4 port map( A => n228, B => n87, C => A(25), D => n234, Z =>
n86);
U304 : AN2SVTX1 port map( A => n231, B => n91, Z => n205);
U305 : AO2SVTX1 port map( A => n227, B => n81, C => A(28), D => P2, Z => n80
);
U306 : AN2SVTX4 port map( A => n228, B => n115, Z => n161);
U307 : NR2SVTX2 port map( A => n161, B => n162, Z => n114);
U308 : OR2SVTX4 port map( A => A(12), B => n212, Z => n163);
U309 : OR2SVTX4 port map( A => n177, B => n113, Z => n164);
U310 : IVSVTX2 port map( A => A(11), Z => n115);
U311 : IVSVTX2 port map( A => A(12), Z => n113);
U312 : OR2SVTX6 port map( A => A(41), B => n210, Z => n166);
U313 : AO2SVTX1 port map( A => n227, B => n55, C => A(40), D => P2, Z => n54
);
U314 : ND3SVTX8 port map( A => n199, B => n200, C => n92, Z => Z_25_port);
U315 : AO2SVTX1 port map( A => n231, B => n93, C => A(22), D => P2, Z => n92
);
U316 : AO23SVTX4 port map( A => A(3), B => n212, C => n177, D => n24, E =>
n25, Z => Z_5_port);
U317 : AO23SVTX4 port map( A => A(28), B => n212, C => n174, D => n81, E =>
n82, Z => Z_30_port);
U318 : AO2SVTX4 port map( A => n228, B => n83, C => n229, D => A(27), Z =>
n82);
U319 : AO23SVTX4 port map( A => A(48), B => n210, C => n176, D => n37, E =>
n38, Z => Z_50_port);
U320 : ND3SVTX6 port map( A => n213, B => n214, C => n179, Z => Z_36_port);
U321 : AO2SVTX2 port map( A => n149, B => n71, C => A(33), D => n232, Z =>
n70);
U322 : OR2SVTX4 port map( A => n176, B => n53, Z => n167);
U323 : ND3SVTX8 port map( A => n166, B => n167, C => n169, Z => Z_43_port);
U324 : IVSVTX2 port map( A => n54, Z => n168);
U325 : IVSVTX4 port map( A => n168, Z => n169);
U326 : ND3SVTX8 port map( A => n180, B => n181, C => n171, Z => Z_27_port);
U327 : IVSVTX4 port map( A => n128, Z => n171);
U328 : AO23SVTX6 port map( A => A(18), B => n211, C => n143, D => n101, E =>
n102, Z => Z_20_port);
U329 : AN2SVTX2 port map( A => n231, B => n75, Z => n172);
U330 : AN2SVTX4 port map( A => A(31), B => n229, Z => n173);
U331 : NR2SVTX6 port map( A => n172, B => n173, Z => n74);
U332 : IVSVTX2 port map( A => A(31), Z => n75);
U333 : IVSVTX4 port map( A => n215, Z => n216);
U334 : AO2SVTX1 port map( A => n227, B => n99, C => A(19), D => P2, Z => n98
);
U335 : IVSVTX4 port map( A => P1, Z => n222);
U336 : AO23SVTX4 port map( A => A(39), B => n212, C => n150, D => n57, E =>
n198, Z => Z_41_port);
U337 : IVSVTX2 port map( A => P1, Z => n177);
U338 : OR2SVTX6 port map( A => n176, B => n87, Z => n181);
U339 : AO2SVTX4 port map( A => n228, B => n26, C => n232, D => A(2), Z =>
n25);
U340 : IVSVTX6 port map( A => M1, Z => n12);
U341 : OR2SVTX4 port map( A => n176, B => n89, Z => n208);
U342 : AO2SVTX4 port map( A => n228, B => n77, C => A(30), D => n232, Z =>
n76);
U343 : AO23SVTX4 port map( A => A(46), B => n212, C => n226, D => n43, E =>
n44, Z => Z_48_port);
U344 : ND3SVTX8 port map( A => n207, B => n208, C => n90, Z => Z_26_port);
U345 : AO2SVTX2 port map( A => n228, B => n45, C => A(45), D => n232, Z =>
n44);
U346 : AO2SVTX4 port map( A => n228, B => n53, C => A(41), D => n232, Z =>
n52);
U347 : OR2SVTX1 port map( A => n118, B => n18, Z => n183);
U348 : OR2SVTX4 port map( A => n176, B => n79, Z => n225);
U349 : IVSVTX2 port map( A => n178, Z => n179);
U350 : IVSVTX2 port map( A => A(25), Z => n87);
U351 : ND3SVTX6 port map( A => n182, B => n119, C => n183, Z => Z_12_port);
U352 : AO2SVTX2 port map( A => n188, B => n117, C => A(10), D => n223, Z =>
n119);
U353 : OR2SVTX4 port map( A => A(37), B => n211, Z => n184);
U354 : IVSVTX4 port map( A => n235, Z => n220);
U355 : OR2SVTX4 port map( A => n176, B => n91, Z => n200);
U356 : AO2SVTX1 port map( A => n227, B => n79, C => A(29), D => P2, Z => n78
);
U357 : ND3SVTX8 port map( A => n191, B => n192, C => n60, Z => Z_40_port);
U358 : OR2SVTX4 port map( A => n175, B => n59, Z => n192);
U359 : OR2SVTX4 port map( A => A(2), B => n211, Z => n186);
U360 : ND3SVTX8 port map( A => n186, B => n187, C => n40, Z => Z_4_port);
U361 : IVSVTX2 port map( A => A(2), Z => n26);
U362 : AN2SVTX1 port map( A => A(1), B => P2, Z => n190);
U363 : AO2SVTX2 port map( A => n227, B => n59, C => A(38), D => P2, Z => n58
);
U364 : OR2SVTX4 port map( A => A(38), B => n210, Z => n191);
U365 : IVSVTX0H port map( A => A(38), Z => n59);
U366 : NR2SVTX2 port map( A => n201, B => n202, Z => n60);
U367 : ND2HVTX1 port map( A => A(4), B => P2, Z => n194);
U368 : AN2SVTX6 port map( A => n193, B => n194, Z => n21);
U369 : OR2SVTX4 port map( A => A(5), B => n211, Z => n195);
U370 : OR2SVTX6 port map( A => n176, B => n19, Z => n196);
U371 : ND3SVTX8 port map( A => n195, B => n196, C => n21, Z => Z_7_port);
U372 : IVSVTX2 port map( A => A(4), Z => n22);
U373 : IVSVTX2 port map( A => A(5), Z => n19);
U374 : BFSVTX12 port map( A => P2, Z => n229);
U375 : IVSVTX1 port map( A => n58, Z => n197);
U376 : IVSVTX2 port map( A => n197, Z => n198);
U377 : OR2SVTX8 port map( A => A(23), B => n211, Z => n199);
U378 : AO23SVTX6 port map( A => A(31), B => n210, C => n176, D => n75, E =>
n76, Z => Z_33_port);
U379 : IVSVTX4 port map( A => n220, Z => Z_39_port);
U380 : AN2SVTX4 port map( A => n227, B => n61, Z => n201);
U381 : AN2SVTX1 port map( A => A(37), B => P2, Z => n202);
U382 : OR2SVTX4 port map( A => A(33), B => n212, Z => n203);
U383 : OR2SVTX4 port map( A => n176, B => n71, Z => n204);
U384 : AO2SVTX2 port map( A => n227, B => n69, C => A(34), D => n229, Z =>
n68);
U385 : AO23SVTX2 port map( A => A(30), B => n211, C => n176, D => n77, E =>
n78, Z => Z_32_port);
U386 : AO2SVTX2 port map( A => n231, B => n35, C => P2, D => A(49), Z => n34
);
U387 : IVSVTX2 port map( A => n34, Z => n215);
U388 : ND3SVTX8 port map( A => n72, B => n204, C => n203, Z => Z_35_port);
U389 : NR2SVTX4 port map( A => n205, B => n206, Z => n90);
U390 : IVSVTX2 port map( A => A(24), Z => n89);
U391 : IVSVTX12 port map( A => n18, Z => n234);
U392 : IVSVTX12 port map( A => n209, Z => n210);
U393 : IVSVTX12 port map( A => n209, Z => n212);
U394 : AO23SVTX2 port map( A => A(17), B => n212, C => n176, D => n103, E =>
n104, Z => Z_19_port);
U395 : OR2SVTX6 port map( A => A(34), B => n210, Z => n213);
U396 : OR2SVTX4 port map( A => n176, B => n69, Z => n214);
U397 : AO2SVTX2 port map( A => n228, B => n85, C => n234, D => A(26), Z =>
n84);
U398 : AO2SVTX1 port map( A => n227, B => n105, C => A(16), D => P2, Z =>
n104);
U399 : AO2SVTX2 port map( A => n228, B => n49, C => n234, D => A(43), Z =>
n48);
U400 : AO2SVTX2 port map( A => n228, B => n39, C => n234, D => A(47), Z =>
n38);
U401 : AO23SVTX2 port map( A => A(20), B => n212, C => n176, D => n97, E =>
n98, Z => Z_22_port);
U402 : AO23SVTX2 port map( A => A(52), B => n212, C => n174, D => n29, E =>
n30, Z => Z_54_port);
U403 : OR2SVTX4 port map( A => A(47), B => n210, Z => n217);
U404 : IVSVTX0H port map( A => A(47), Z => n39);
U405 : AO2SVTX1 port map( A => n231, B => n117, C => A(10), D => P2, Z =>
n116);
U406 : AO2SVTX1 port map( A => n231, B => n113, C => A(12), D => P2, Z =>
n112);
U407 : AO2SVTX1 port map( A => n227, B => n31, C => A(51), D => P2, Z => n30
);
U408 : AO2SVTX1 port map( A => n231, B => n73, C => A(32), D => P2, Z => n72
);
U409 : AO2SVTX1 port map( A => n228, B => n43, C => A(46), D => n234, Z =>
n42);
U410 : IVSVTX12 port map( A => n17, Z => n227);
U411 : AO2SVTX2 port map( A => n228, B => n47, C => A(44), D => n232, Z =>
n46);
U412 : IVSVTX8 port map( A => M2, Z => n230);
U413 : IVSVTX12 port map( A => n230, Z => n231);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity gl_csa32_n8 is
port( A, B, C : in std_logic_vector (8 downto 0); Cin : in std_logic; Z, Y
: out std_logic_vector (8 downto 0));
end gl_csa32_n8;
architecture SYN_BEHAVIORAL of gl_csa32_n8 is
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOSVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EO3SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EOHVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
signal Y_8_port, Y_7_port, Y_6_port, Y_5_port, Y_4_port, Y_3_port, Y_2_port,
Y_1_port, n16, n17, n18, n19, n20, n21, n22, n23 : std_logic;
begin
Y <= ( Y_8_port, Y_7_port, Y_6_port, Y_5_port, Y_4_port, Y_3_port, Y_2_port,
Y_1_port, Cin );
U17 : EOHVTX1 port map( A => B(7), B => A(7), Z => n16);
U19 : EOHVTX1 port map( A => B(6), B => A(6), Z => n17);
U27 : EOHVTX1 port map( A => B(2), B => A(2), Z => n21);
U29 : EOHVTX1 port map( A => B(1), B => A(1), Z => n22);
U31 : EOHVTX1 port map( A => B(0), B => A(0), Z => n23);
U32 : EOSVTX6 port map( A => n18, B => C(5), Z => Z(5));
U33 : EOSVTX4 port map( A => C(3), B => n20, Z => Z(3));
U34 : AO2NSVTX2 port map( A => B(3), B => A(3), C => n20, D => C(3), Z =>
Y_4_port);
U35 : EOSVTX1 port map( A => B(3), B => A(3), Z => n20);
U36 : EOSVTX8 port map( A => C(4), B => n19, Z => Z(4));
U37 : AO2NSVTX4 port map( A => B(6), B => A(6), C => n17, D => C(6), Z =>
Y_7_port);
U38 : AO2NSVTX6 port map( A => B(1), B => A(1), C => C(1), D => n22, Z =>
Y_2_port);
U39 : EOSVTX4 port map( A => n21, B => C(2), Z => Z(2));
U40 : AO2NSVTX4 port map( A => B(2), B => A(2), C => n21, D => C(2), Z =>
Y_3_port);
U41 : AO2NSVTX4 port map( A => B(5), B => A(5), C => n18, D => C(5), Z =>
Y_6_port);
U42 : EOSVTX4 port map( A => n22, B => C(1), Z => Z(1));
U43 : EOSVTX4 port map( A => C(7), B => n16, Z => Z(7));
U44 : EOSVTX4 port map( A => C(6), B => n17, Z => Z(6));
U45 : AO2NSVTX4 port map( A => B(0), B => A(0), C => n23, D => C(0), Z =>
Y_1_port);
U46 : EO3SVTX8 port map( A => C(8), B => B(8), C => A(8), Z => Z(8));
U47 : AO2NSVTX4 port map( A => B(4), B => A(4), C => n19, D => C(4), Z =>
Y_5_port);
U48 : AO2NSVTX4 port map( A => B(7), B => A(7), C => n16, D => C(7), Z =>
Y_8_port);
U49 : EOSVTX4 port map( A => C(0), B => n23, Z => Z(0));
U50 : EOHVTX2 port map( A => B(4), B => A(4), Z => n19);
U51 : EOHVTX2 port map( A => B(5), B => A(5), Z => n18);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity csa32LSBs_n47 is
port( A, B, C : in std_logic_vector (47 downto 0); Cin : in std_logic;
Cout : out std_logic; Z, Y : out std_logic_vector (47 downto 0));
end csa32LSBs_n47;
architecture SYN_BEHAVIORAL of csa32LSBs_n47 is
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOSVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component EOSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component OR2ABSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component ENSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
signal Y_47_port, Y_46_port, Y_45_port, Y_44_port, Y_43_port, Y_42_port,
Y_41_port, Y_40_port, Y_39_port, Y_38_port, Y_37_port, Y_36_port,
Y_35_port, Y_34_port, Y_33_port, Y_32_port, Y_31_port, Y_30_port,
Y_29_port, Y_28_port, Y_27_port, Y_26_port, Y_25_port, Y_24_port,
Y_23_port, Y_22_port, Y_21_port, Y_20_port, Y_19_port, Y_18_port,
Y_17_port, Y_16_port, Y_15_port, Y_14_port, Y_13_port, Y_12_port,
Y_11_port, Y_10_port, Y_9_port, Y_8_port, Y_7_port, Y_6_port, Y_5_port,
Y_4_port, Y_3_port, Y_2_port, Y_1_port, n17, n18, n19, n20, n21, n22, n23
, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52
, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66,
n67, n68, n69, n70, n71 : std_logic;
begin
Y <= ( Y_47_port, Y_46_port, Y_45_port, Y_44_port, Y_43_port, Y_42_port,
Y_41_port, Y_40_port, Y_39_port, Y_38_port, Y_37_port, Y_36_port,
Y_35_port, Y_34_port, Y_33_port, Y_32_port, Y_31_port, Y_30_port,
Y_29_port, Y_28_port, Y_27_port, Y_26_port, Y_25_port, Y_24_port,
Y_23_port, Y_22_port, Y_21_port, Y_20_port, Y_19_port, Y_18_port,
Y_17_port, Y_16_port, Y_15_port, Y_14_port, Y_13_port, Y_12_port,
Y_11_port, Y_10_port, Y_9_port, Y_8_port, Y_7_port, Y_6_port, Y_5_port,
Y_4_port, Y_3_port, Y_2_port, Y_1_port, Cin );
U56 : EOHVTX1 port map( A => B(8), B => A(8), Z => n18);
U62 : EOHVTX1 port map( A => B(5), B => A(5), Z => n21);
U66 : EOHVTX1 port map( A => B(3), B => A(3), Z => n31);
U68 : EOHVTX1 port map( A => B(46), B => A(46), Z => n24);
U70 : EOHVTX1 port map( A => B(45), B => A(45), Z => n25);
U72 : EOHVTX1 port map( A => B(44), B => A(44), Z => n26);
U76 : EOHVTX1 port map( A => B(42), B => A(42), Z => n28);
U78 : EOHVTX1 port map( A => B(41), B => A(41), Z => n29);
U80 : EOHVTX1 port map( A => B(40), B => A(40), Z => n30);
U84 : EOHVTX1 port map( A => B(2), B => A(2), Z => n42);
U86 : EOHVTX1 port map( A => B(38), B => A(38), Z => n33);
U88 : EOHVTX1 port map( A => B(37), B => A(37), Z => n34);
U90 : EOHVTX1 port map( A => B(36), B => A(36), Z => n35);
U94 : EOHVTX1 port map( A => B(34), B => A(34), Z => n37);
U98 : EOHVTX1 port map( A => B(32), B => A(32), Z => n39);
U100 : EOHVTX1 port map( A => B(31), B => A(31), Z => n40);
U106 : EOHVTX1 port map( A => B(1), B => A(1), Z => n53);
U110 : EOHVTX1 port map( A => B(27), B => A(27), Z => n45);
U114 : EOHVTX1 port map( A => B(25), B => A(25), Z => n47);
U120 : EOHVTX1 port map( A => B(22), B => A(22), Z => n50);
U122 : EOHVTX1 port map( A => B(21), B => A(21), Z => n51);
U124 : EOHVTX1 port map( A => B(20), B => A(20), Z => n52);
U126 : EOHVTX1 port map( A => B(19), B => A(19), Z => n54);
U128 : EOHVTX1 port map( A => B(0), B => A(0), Z => n64);
U132 : EOHVTX1 port map( A => B(17), B => A(17), Z => n56);
U136 : EOHVTX1 port map( A => B(15), B => A(15), Z => n58);
U146 : EOHVTX1 port map( A => B(10), B => A(10), Z => n63);
U150 : EOHVTX1 port map( A => B(47), B => A(47), Z => n23);
U151 : EOSVTX6 port map( A => C(19), B => n54, Z => Z(19));
U152 : EOSVTX2 port map( A => n26, B => C(44), Z => Z(44));
U153 : EOSVTX6 port map( A => C(14), B => n59, Z => Z(14));
U154 : AO2NSVTX2 port map( A => B(17), B => A(17), C => n56, D => C(17), Z
=> Y_18_port);
U155 : AO2NSVTX4 port map( A => B(14), B => A(14), C => n59, D => C(14), Z
=> Y_15_port);
U156 : EOSVTX1 port map( A => B(14), B => A(14), Z => n59);
U157 : EOSVTX1 port map( A => B(12), B => A(12), Z => n61);
U158 : EOSVTX1 port map( A => B(9), B => A(9), Z => n17);
U159 : AO2NSVTX6 port map( A => B(18), B => A(18), C => C(18), D => n55, Z
=> Y_19_port);
U160 : EOSVTX1 port map( A => B(6), B => A(6), Z => n20);
U161 : EOSVTX1 port map( A => B(35), B => A(35), Z => n36);
U162 : EOSVTX1 port map( A => B(28), B => A(28), Z => n44);
U163 : EOSVTX1 port map( A => B(18), B => A(18), Z => n55);
U164 : ND2SVTX2 port map( A => B(47), B => A(47), Z => n65);
U165 : ND2SVTX2 port map( A => C(47), B => n23, Z => n66);
U166 : ND2SVTX2 port map( A => n65, B => n66, Z => Cout);
U167 : EOSVTX6 port map( A => C(47), B => n23, Z => Z(47));
U168 : EOSVTX4 port map( A => C(7), B => n19, Z => Z(7));
U169 : AO2NSVTX6 port map( A => B(7), B => A(7), C => n19, D => C(7), Z =>
Y_8_port);
U170 : EOSVTX1 port map( A => B(7), B => A(7), Z => n19);
U171 : AO2NSVTX4 port map( A => B(13), B => A(13), C => n60, D => C(13), Z
=> Y_14_port);
U172 : EOSVTX1 port map( A => B(13), B => A(13), Z => n60);
U173 : EOSVTX1 port map( A => B(4), B => A(4), Z => n22);
U174 : EOSVTX1 port map( A => B(29), B => A(29), Z => n43);
U175 : AO2NSVTX4 port map( A => B(28), B => A(28), C => n44, D => C(28), Z
=> Y_29_port);
U176 : EOSVTX4 port map( A => n32, B => C(39), Z => Z(39));
U177 : EOSVTX1 port map( A => B(39), B => A(39), Z => n32);
U178 : AO2NSVTX4 port map( A => B(16), B => A(16), C => n57, D => C(16), Z
=> Y_17_port);
U179 : EOSVTX1 port map( A => B(16), B => A(16), Z => n57);
U180 : AO2NSVTX8 port map( A => B(45), B => A(45), C => n25, D => n71, Z =>
Y_46_port);
U181 : IVSVTX4 port map( A => n70, Z => n71);
U182 : EOSVTX1 port map( A => B(43), B => A(43), Z => n27);
U183 : AO2NSVTX6 port map( A => B(42), B => A(42), C => n28, D => C(42), Z
=> Y_43_port);
U184 : AO2NSVTX6 port map( A => B(40), B => A(40), C => n30, D => C(40), Z
=> Y_41_port);
U185 : AO2NSVTX6 port map( A => B(25), B => A(25), C => n47, D => C(25), Z
=> Y_26_port);
U186 : EOSVTX4 port map( A => n38, B => C(33), Z => Z(33));
U187 : EOSVTX1 port map( A => B(33), B => A(33), Z => n38);
U188 : EOSVTX4 port map( A => n51, B => C(21), Z => Z(21));
U189 : AO2NSVTX6 port map( A => B(21), B => A(21), C => C(21), D => n51, Z
=> Y_22_port);
U190 : AO2NSVTX8 port map( A => B(33), B => A(33), C => n38, D => C(33), Z
=> Y_34_port);
U191 : EOSVTX1 port map( A => B(26), B => A(26), Z => n46);
U192 : AO2NSVTX4 port map( A => B(3), B => A(3), C => n31, D => C(3), Z =>
Y_4_port);
U193 : EOSVTX8 port map( A => n43, B => C(29), Z => Z(29));
U194 : OR2ABSVTX8 port map( A => B(24), B => A(24), Z => n67);
U195 : ND2SVTX2 port map( A => n48, B => C(24), Z => n68);
U196 : ND2SVTX4 port map( A => n67, B => n68, Z => Y_25_port);
U197 : EOSVTX8 port map( A => B(24), B => A(24), Z => n48);
U198 : ENSVTX8 port map( A => n69, B => C(24), Z => Z(24));
U199 : IVSVTX12 port map( A => n48, Z => n69);
U200 : AO2NSVTX4 port map( A => B(31), B => A(31), C => n40, D => C(31), Z
=> Y_32_port);
U201 : EOSVTX8 port map( A => C(37), B => n34, Z => Z(37));
U202 : AO2NSVTX6 port map( A => B(20), B => A(20), C => n52, D => C(20), Z
=> Y_21_port);
U203 : EOSVTX4 port map( A => n60, B => C(13), Z => Z(13));
U204 : EOSVTX4 port map( A => n58, B => C(15), Z => Z(15));
U205 : EOSVTX4 port map( A => C(30), B => n41, Z => Z(30));
U206 : AO2NSVTX4 port map( A => B(30), B => A(30), C => n41, D => C(30), Z
=> Y_31_port);
U207 : EOSVTX1 port map( A => B(30), B => A(30), Z => n41);
U208 : EOSVTX8 port map( A => C(28), B => n44, Z => Z(28));
U209 : EOSVTX4 port map( A => n30, B => C(40), Z => Z(40));
U210 : EOSVTX8 port map( A => C(1), B => n53, Z => Z(1));
U211 : AO2NSVTX6 port map( A => B(9), B => A(9), C => C(9), D => n17, Z =>
Y_10_port);
U212 : AO2NSVTX6 port map( A => B(12), B => A(12), C => n61, D => C(12), Z
=> Y_13_port);
U213 : AO2NSVTX8 port map( A => B(23), B => A(23), C => C(23), D => n49, Z
=> Y_24_port);
U214 : EOSVTX4 port map( A => n45, B => C(27), Z => Z(27));
U215 : EOSVTX4 port map( A => n37, B => C(34), Z => Z(34));
U216 : EOSVTX4 port map( A => n63, B => C(10), Z => Z(10));
U217 : EOSVTX2 port map( A => n49, B => C(23), Z => Z(23));
U218 : AO2NSVTX4 port map( A => B(34), B => A(34), C => n37, D => C(34), Z
=> Y_35_port);
U219 : EOSVTX4 port map( A => n36, B => C(35), Z => Z(35));
U220 : AO2NSVTX6 port map( A => B(35), B => A(35), C => C(35), D => n36, Z
=> Y_36_port);
U221 : AO2NSVTX6 port map( A => B(6), B => A(6), C => C(6), D => n20, Z =>
Y_7_port);
U222 : EOSVTX4 port map( A => n57, B => C(16), Z => Z(16));
U223 : AO2NSVTX4 port map( A => B(8), B => A(8), C => n18, D => C(8), Z =>
Y_9_port);
U224 : EOSVTX4 port map( A => n28, B => C(42), Z => Z(42));
U225 : AO2NSVTX4 port map( A => B(44), B => A(44), C => C(44), D => n26, Z
=> Y_45_port);
U226 : AO2NSVTX6 port map( A => B(29), B => A(29), C => C(29), D => n43, Z
=> Y_30_port);
U227 : AO2NSVTX4 port map( A => B(46), B => A(46), C => C(46), D => n24, Z
=> Y_47_port);
U228 : EOSVTX4 port map( A => n21, B => C(5), Z => Z(5));
U229 : EOSVTX4 port map( A => n71, B => n25, Z => Z(45));
U230 : EOSVTX4 port map( A => n27, B => C(43), Z => Z(43));
U231 : AO2NSVTX8 port map( A => B(43), B => A(43), C => n27, D => C(43), Z
=> Y_44_port);
U232 : AO2NSVTX2 port map( A => B(1), B => A(1), C => n53, D => C(1), Z =>
Y_2_port);
U233 : AO2NSVTX2 port map( A => B(0), B => A(0), C => n64, D => C(0), Z =>
Y_1_port);
U234 : EOSVTX4 port map( A => n20, B => C(6), Z => Z(6));
U235 : EOSVTX4 port map( A => n56, B => C(17), Z => Z(17));
U236 : EOSVTX4 port map( A => n52, B => C(20), Z => Z(20));
U237 : AO2NSVTX4 port map( A => B(4), B => A(4), C => n22, D => C(4), Z =>
Y_5_port);
U238 : AO2NSVTX8 port map( A => B(39), B => A(39), C => n32, D => C(39), Z
=> Y_40_port);
U239 : EOSVTX1 port map( A => B(11), B => A(11), Z => n62);
U240 : EOSVTX4 port map( A => C(12), B => n61, Z => Z(12));
U241 : AO2NSVTX4 port map( A => B(15), B => A(15), C => n58, D => C(15), Z
=> Y_16_port);
U242 : EOSVTX4 port map( A => n29, B => C(41), Z => Z(41));
U243 : EOSVTX4 port map( A => C(22), B => n50, Z => Z(22));
U244 : EOSVTX8 port map( A => n22, B => C(4), Z => Z(4));
U245 : EOSVTX4 port map( A => n17, B => C(9), Z => Z(9));
U246 : AO2NSVTX4 port map( A => B(22), B => A(22), C => n50, D => C(22), Z
=> Y_23_port);
U247 : AO2NSVTX8 port map( A => B(26), B => A(26), C => C(26), D => n46, Z
=> Y_27_port);
U248 : EOSVTX1 port map( A => B(23), B => A(23), Z => n49);
U249 : EOSVTX4 port map( A => C(38), B => n33, Z => Z(38));
U250 : AO2NSVTX4 port map( A => B(38), B => A(38), C => n33, D => C(38), Z
=> Y_39_port);
U251 : EOSVTX4 port map( A => n24, B => C(46), Z => Z(46));
U252 : AO2NSVTX6 port map( A => B(11), B => A(11), C => C(11), D => n62, Z
=> Y_12_port);
U253 : EOSVTX4 port map( A => n62, B => C(11), Z => Z(11));
U254 : AO2NSVTX4 port map( A => B(41), B => A(41), C => n29, D => C(41), Z
=> Y_42_port);
U255 : EOSVTX4 port map( A => n47, B => C(25), Z => Z(25));
U256 : AO2NSVTX4 port map( A => B(27), B => A(27), C => n45, D => C(27), Z
=> Y_28_port);
U257 : AO2NSVTX4 port map( A => B(32), B => A(32), C => n39, D => C(32), Z
=> Y_33_port);
U258 : EOSVTX2 port map( A => n31, B => C(3), Z => Z(3));
U259 : AO2NSVTX4 port map( A => B(10), B => A(10), C => n63, D => C(10), Z
=> Y_11_port);
U260 : EOSVTX4 port map( A => n46, B => C(26), Z => Z(26));
U261 : EOSVTX2 port map( A => n64, B => C(0), Z => Z(0));
U262 : AO2NSVTX4 port map( A => B(36), B => A(36), C => n35, D => C(36), Z
=> Y_37_port);
U263 : EOSVTX4 port map( A => n35, B => C(36), Z => Z(36));
U264 : EOSVTX4 port map( A => n18, B => C(8), Z => Z(8));
U265 : EOSVTX4 port map( A => n55, B => C(18), Z => Z(18));
U266 : AO2NSVTX4 port map( A => B(37), B => A(37), C => n34, D => C(37), Z
=> Y_38_port);
U267 : AO2NSVTX4 port map( A => B(19), B => A(19), C => n54, D => C(19), Z
=> Y_20_port);
U268 : EOSVTX4 port map( A => n40, B => C(31), Z => Z(31));
U269 : AO2NSVTX4 port map( A => B(5), B => A(5), C => n21, D => C(5), Z =>
Y_6_port);
U270 : EOSVTX4 port map( A => C(2), B => n42, Z => Z(2));
U271 : EOSVTX4 port map( A => C(32), B => n39, Z => Z(32));
U272 : IVSVTX2 port map( A => C(45), Z => n70);
U273 : AO2NSVTX4 port map( A => B(2), B => A(2), C => n42, D => C(2), Z =>
Y_3_port);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity gl_dualreg_ld_n10 is
port( AS, AC : in std_logic_vector (10 downto 0); RESET, CLOCK, LOAD : in
std_logic; ZS, ZC : out std_logic_vector (10 downto 0));
end gl_dualreg_ld_n10;
architecture SYN_BEHAVIORAL of gl_dualreg_ld_n10 is
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX2
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX4
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component AO4ABSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AN2SVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component OR2SVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component OR2ABHVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX1
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
signal ZS_10_port, ZS_9_port, ZS_8_port, ZS_7_port, ZS_6_port, n181,
ZS_4_port, ZS_3_port, ZS_2_port, ZS_1_port, ZS_0_port, ZC_10_port,
ZC_9_port, ZC_8_port, ZC_7_port, ZC_6_port, ZC_5_port, n182, ZC_3_port,
ZC_2_port, ZC_1_port, ZC_0_port, n127, n128, n129, n130, n131, n132, n133
, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, ZS_5_port, n173, n174, n175, n176, n177, ZC_4_port, n179,
n180 : std_logic;
begin
ZS <= ( ZS_10_port, ZS_9_port, ZS_8_port, ZS_7_port, ZS_6_port, ZS_5_port,
ZS_4_port, ZS_3_port, ZS_2_port, ZS_1_port, ZS_0_port );
ZC <= ( ZC_10_port, ZC_9_port, ZC_8_port, ZC_7_port, ZC_6_port, ZC_5_port,
ZC_4_port, ZC_3_port, ZC_2_port, ZC_1_port, ZC_0_port );
ZS_reg_10_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n128, Q
=> ZS_10_port);
ZS_reg_9_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n129, Q
=> ZS_9_port);
ZS_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n130, Q
=> ZS_8_port);
ZS_reg_4_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n134, Q
=> ZS_4_port);
ZS_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n135, Q
=> ZS_3_port);
ZS_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n136, Q
=> ZS_2_port);
ZS_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n137, Q
=> ZS_1_port);
ZS_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n138, Q
=> ZS_0_port);
ZC_reg_10_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n139, Q
=> ZC_10_port);
ZC_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n141, Q
=> ZC_8_port);
ZC_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n146, Q
=> ZC_3_port);
ZC_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n147, Q
=> ZC_2_port);
ZC_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n148, Q
=> ZC_1_port);
U92 : IVSVTX2 port map( A => AS(8), Z => n150);
U93 : AO2NSVTX4 port map( A => ZS_0_port, B => n127, C => AS(0), D => LOAD,
Z => n138);
U94 : AO2NSVTX6 port map( A => ZC_2_port, B => n127, C => AC(2), D => LOAD,
Z => n147);
U95 : ND2SVTX6 port map( A => AC(5), B => LOAD, Z => n167);
U96 : AO2NSVTX8 port map( A => ZC_8_port, B => n127, C => AC(8), D => LOAD,
Z => n141);
U97 : AO2NSVTX8 port map( A => ZS_6_port, B => n127, C => AS(6), D => LOAD,
Z => n132);
U98 : AO4ABSVTX6 port map( A => ZS_8_port, B => n127, C => n150, D => n156,
Z => n130);
U99 : IVSVTX8 port map( A => LOAD, Z => n156);
U100 : AO4ABSVTX6 port map( A => ZS_9_port, B => n127, C => n151, D => n165,
Z => n129);
U101 : IVSVTX12 port map( A => AS(9), Z => n151);
U102 : IVSVTX8 port map( A => LOAD, Z => n165);
U103 : AO2NSVTX8 port map( A => ZC_6_port, B => n127, C => AC(6), D => LOAD,
Z => n143);
U104 : AO2NSVTX8 port map( A => ZC_10_port, B => n127, C => AC(10), D =>
LOAD, Z => n139);
U105 : IVSVTX6 port map( A => AS(10), Z => n157);
ZC_reg_9_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n140, Q
=> ZC_9_port);
U106 : AO4ABSVTX6 port map( A => ZC_0_port, B => n153, C => n152, D => n127,
Z => n149);
U107 : IVSVTX12 port map( A => AC(0), Z => n152);
U108 : IVSVTX12 port map( A => n176, Z => n153);
ZC_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n149, Q
=> ZC_0_port);
U109 : AO4ABSVTX8 port map( A => n154, B => n155, C => n156, D => n157, Z =>
n128);
U110 : IVSVTX12 port map( A => n175, Z => n154);
U111 : IVSVTX12 port map( A => n176, Z => n155);
U112 : AO4ASVTX8 port map( A => AC(9), B => n159, C => n158, D => n176, Z =>
n140);
U113 : IVSVTX12 port map( A => ZC_9_port, Z => n158);
U114 : IVSVTX12 port map( A => LOAD, Z => n159);
U115 : AO2NSVTX8 port map( A => ZC_1_port, B => n127, C => AC(1), D => LOAD,
Z => n148);
U116 : AN2SVTX8 port map( A => ZS_7_port, B => n127, Z => n160);
U117 : AN2SVTX6 port map( A => LOAD, B => AS(7), Z => n161);
U118 : OR2SVTX8 port map( A => n160, B => n161, Z => n131);
ZS_reg_7_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n131, Q
=> ZS_7_port);
U119 : AO2NSVTX6 port map( A => ZC_7_port, B => n127, C => AC(7), D => LOAD,
Z => n142);
U120 : AO4ASVTX4 port map( A => ZS_5_port, B => n176, C => n162, D => n163,
Z => n133);
U121 : IVSVTX12 port map( A => AS(5), Z => n162);
U122 : IVSVTX12 port map( A => LOAD, Z => n163);
U123 : AO4ABSVTX6 port map( A => n180, B => n127, C => n164, D => n165, Z =>
n145);
U124 : IVSVTX12 port map( A => AC(4), Z => n164);
ZC_reg_7_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n142, Q
=> ZC_7_port);
U125 : OR2ABHVTX2 port map( A => ZC_5_port, B => n127, Z => n166);
U126 : ND2SVTX4 port map( A => n166, B => n167, Z => n144);
U127 : AO4ABSVTX6 port map( A => ZS_1_port, B => n127, C => n168, D => n127,
Z => n137);
U128 : IVSVTX12 port map( A => AS(1), Z => n168);
U129 : IVSVTX8 port map( A => n127, Z => n176);
U130 : IVSVTX4 port map( A => AS(2), Z => n170);
ZC_reg_6_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n143, Q
=> ZC_6_port);
U131 : AO4ABSVTX6 port map( A => ZC_3_port, B => n127, C => n169, D => n127,
Z => n146);
U132 : IVSVTX12 port map( A => AC(3), Z => n169);
U133 : AO4ABSVTX6 port map( A => ZS_2_port, B => n127, C => n170, D => n127,
Z => n136);
U134 : IVSVTX8 port map( A => LOAD, Z => n127);
U135 : IVSVTX4 port map( A => n181, Z => n171);
U136 : IVSVTX6 port map( A => n171, Z => ZS_5_port);
ZS_reg_5_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n133, Q
=> n181);
ZS_reg_6_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n132, Q
=> ZS_6_port);
U137 : AO2NSVTX6 port map( A => n174, B => n127, C => AS(4), D => LOAD, Z =>
n134);
U138 : IVHVTX0H port map( A => ZS_4_port, Z => n173);
U139 : IVSVTX0H port map( A => n173, Z => n174);
U140 : IVSVTX12 port map( A => ZS_10_port, Z => n175);
U141 : AO2NSVTX6 port map( A => ZS_3_port, B => n127, C => AS(3), D => LOAD,
Z => n135);
U142 : IVSVTX2 port map( A => n182, Z => n177);
U143 : IVSVTX4 port map( A => n177, Z => ZC_4_port);
ZC_reg_4_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n145, Q
=> n182);
U144 : IVHVTX0H port map( A => ZC_4_port, Z => n179);
U145 : IVSVTX0H port map( A => n179, Z => n180);
ZC_reg_5_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n144, Q
=> ZC_5_port);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity gl_dualreg_ld_n45 is
port( AS, AC : in std_logic_vector (45 downto 0); RESET, CLOCK, LOAD : in
std_logic; ZS, ZC : out std_logic_vector (45 downto 0));
end gl_dualreg_ld_n45;
architecture SYN_BEHAVIORAL of gl_dualreg_ld_n45 is
component AO2NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX2
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2SVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component AO2ASVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4NSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX1
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component FD2QSVTX4
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
signal ZS_45_port, ZS_44_port, ZS_43_port, ZS_42_port, ZS_41_port,
ZS_40_port, ZS_39_port, ZS_38_port, ZS_37_port, ZS_36_port, ZS_35_port,
ZS_34_port, ZS_33_port, ZS_32_port, ZS_31_port, ZS_30_port, ZS_29_port,
ZS_28_port, ZS_27_port, ZS_26_port, ZS_25_port, ZS_24_port, ZS_23_port,
ZS_22_port, ZS_21_port, ZS_20_port, ZS_19_port, ZS_18_port, ZS_17_port,
ZS_16_port, ZS_15_port, ZS_14_port, ZS_13_port, ZS_12_port, ZS_11_port,
ZS_10_port, ZS_9_port, ZS_8_port, ZS_7_port, ZS_6_port, ZS_5_port,
ZS_4_port, ZS_3_port, ZS_2_port, ZS_1_port, ZS_0_port, ZC_45_port,
ZC_44_port, ZC_43_port, ZC_42_port, ZC_41_port, ZC_40_port, ZC_39_port,
ZC_38_port, ZC_37_port, ZC_36_port, ZC_35_port, ZC_34_port, ZC_33_port,
ZC_32_port, ZC_31_port, ZC_30_port, ZC_29_port, ZC_28_port, ZC_27_port,
ZC_26_port, ZC_25_port, ZC_24_port, ZC_23_port, ZC_22_port, ZC_21_port,
ZC_20_port, ZC_19_port, ZC_18_port, ZC_17_port, ZC_16_port, ZC_15_port,
ZC_14_port, ZC_13_port, ZC_12_port, ZC_11_port, ZC_10_port, ZC_9_port,
ZC_8_port, ZC_7_port, ZC_6_port, ZC_5_port, ZC_4_port, ZC_3_port,
ZC_2_port, ZC_1_port, ZC_0_port, n337, n338, n339, n340, n341, n342, n343
, n344, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, n380,
n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416,
n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, n428,
n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, n440,
n441, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, n452,
n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476,
n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, n488,
n489, n490, n491, n492 : std_logic;
begin
ZS <= ( ZS_45_port, ZS_44_port, ZS_43_port, ZS_42_port, ZS_41_port,
ZS_40_port, ZS_39_port, ZS_38_port, ZS_37_port, ZS_36_port, ZS_35_port,
ZS_34_port, ZS_33_port, ZS_32_port, ZS_31_port, ZS_30_port, ZS_29_port,
ZS_28_port, ZS_27_port, ZS_26_port, ZS_25_port, ZS_24_port, ZS_23_port,
ZS_22_port, ZS_21_port, ZS_20_port, ZS_19_port, ZS_18_port, ZS_17_port,
ZS_16_port, ZS_15_port, ZS_14_port, ZS_13_port, ZS_12_port, ZS_11_port,
ZS_10_port, ZS_9_port, ZS_8_port, ZS_7_port, ZS_6_port, ZS_5_port,
ZS_4_port, ZS_3_port, ZS_2_port, ZS_1_port, ZS_0_port );
ZC <= ( ZC_45_port, ZC_44_port, ZC_43_port, ZC_42_port, ZC_41_port,
ZC_40_port, ZC_39_port, ZC_38_port, ZC_37_port, ZC_36_port, ZC_35_port,
ZC_34_port, ZC_33_port, ZC_32_port, ZC_31_port, ZC_30_port, ZC_29_port,
ZC_28_port, ZC_27_port, ZC_26_port, ZC_25_port, ZC_24_port, ZC_23_port,
ZC_22_port, ZC_21_port, ZC_20_port, ZC_19_port, ZC_18_port, ZC_17_port,
ZC_16_port, ZC_15_port, ZC_14_port, ZC_13_port, ZC_12_port, ZC_11_port,
ZC_10_port, ZC_9_port, ZC_8_port, ZC_7_port, ZC_6_port, ZC_5_port,
ZC_4_port, ZC_3_port, ZC_2_port, ZC_1_port, ZC_0_port );
U300 : AO2NHVTX1 port map( A => ZC_0_port, B => n337, C => AC(0), D => LOAD,
Z => n429);
ZS_reg_45_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n338, Q
=> ZS_45_port);
ZS_reg_44_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n339, Q
=> ZS_44_port);
ZS_reg_43_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n340, Q
=> ZS_43_port);
ZS_reg_42_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n341, Q
=> ZS_42_port);
ZS_reg_40_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n343, Q
=> ZS_40_port);
ZS_reg_39_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n344, Q
=> ZS_39_port);
ZS_reg_38_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n490, Q
=> ZS_38_port);
ZS_reg_37_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n346, Q
=> ZS_37_port);
ZS_reg_36_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n347, Q
=> ZS_36_port);
ZS_reg_35_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n348, Q
=> ZS_35_port);
ZS_reg_34_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n349, Q
=> ZS_34_port);
ZS_reg_32_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n351, Q
=> ZS_32_port);
ZS_reg_31_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n352, Q
=> ZS_31_port);
ZS_reg_30_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n353, Q
=> ZS_30_port);
ZS_reg_28_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n355, Q
=> ZS_28_port);
ZS_reg_27_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n356, Q
=> ZS_27_port);
ZS_reg_26_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n357, Q
=> ZS_26_port);
ZS_reg_25_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n358, Q
=> ZS_25_port);
ZS_reg_23_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n360, Q
=> ZS_23_port);
ZS_reg_21_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n362, Q
=> ZS_21_port);
ZS_reg_20_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n363, Q
=> ZS_20_port);
ZS_reg_19_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n364, Q
=> ZS_19_port);
ZS_reg_18_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n365, Q
=> ZS_18_port);
ZS_reg_17_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n366, Q
=> ZS_17_port);
ZS_reg_15_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n368, Q
=> ZS_15_port);
ZS_reg_14_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n369, Q
=> ZS_14_port);
ZS_reg_13_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n370, Q
=> ZS_13_port);
ZS_reg_12_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n371, Q
=> ZS_12_port);
ZS_reg_11_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n372, Q
=> ZS_11_port);
ZS_reg_10_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n373, Q
=> ZS_10_port);
ZS_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n375, Q
=> ZS_8_port);
ZS_reg_7_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n376, Q
=> ZS_7_port);
ZS_reg_4_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n379, Q
=> ZS_4_port);
ZS_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n380, Q
=> ZS_3_port);
ZS_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n381, Q
=> ZS_2_port);
ZS_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n382, Q
=> ZS_1_port);
ZS_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n383, Q
=> ZS_0_port);
ZC_reg_45_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n384, Q
=> ZC_45_port);
ZC_reg_43_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n386, Q
=> ZC_43_port);
ZC_reg_42_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n387, Q
=> ZC_42_port);
ZC_reg_40_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n389, Q
=> ZC_40_port);
ZC_reg_38_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n391, Q
=> ZC_38_port);
ZC_reg_37_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n392, Q
=> ZC_37_port);
ZC_reg_35_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n394, Q
=> ZC_35_port);
ZC_reg_34_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n395, Q
=> ZC_34_port);
ZC_reg_31_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n398, Q
=> ZC_31_port);
ZC_reg_29_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n400, Q
=> ZC_29_port);
ZC_reg_23_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n406, Q
=> ZC_23_port);
ZC_reg_22_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n407, Q
=> ZC_22_port);
ZC_reg_17_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n412, Q
=> ZC_17_port);
ZC_reg_15_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n414, Q
=> ZC_15_port);
ZC_reg_14_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n415, Q
=> ZC_14_port);
ZC_reg_12_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n417, Q
=> ZC_12_port);
ZC_reg_9_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n420, Q
=> ZC_9_port);
ZC_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n421, Q
=> ZC_8_port);
ZC_reg_6_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n423, Q
=> ZC_6_port);
ZC_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n426, Q
=> ZC_3_port);
ZC_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n427, Q
=> ZC_2_port);
ZC_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n428, Q
=> ZC_1_port);
ZC_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n429, Q
=> ZC_0_port);
U302 : IVHVTX0H port map( A => n337, Z => n457);
U303 : IVHVTX0H port map( A => n337, Z => n456);
U304 : IVHVTX0H port map( A => n337, Z => n454);
U305 : IVSVTX6 port map( A => n337, Z => n488);
U306 : IVHVTX0H port map( A => n337, Z => n445);
U307 : IVSVTX0H port map( A => n337, Z => n450);
U308 : AO4ABSVTX4 port map( A => ZC_15_port, B => n337, C => n467, D => n337
, Z => n414);
ZC_reg_26_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n403, Q
=> ZC_26_port);
U309 : AO2NSVTX6 port map( A => ZC_26_port, B => n337, C => AC(26), D =>
LOAD, Z => n403);
ZS_reg_33_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n350, Q
=> ZS_33_port);
U310 : AO4SVTX2 port map( A => n473, B => n488, C => n474, D => n337, Z =>
n350);
U311 : AO2SVTX6 port map( A => AC(25), B => n450, C => n435, D => n436, Z =>
n434);
ZC_reg_36_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n393, Q
=> ZC_36_port);
U312 : AO2NSVTX8 port map( A => ZC_36_port, B => n337, C => AC(36), D =>
LOAD, Z => n393);
U313 : AO4ABSVTX6 port map( A => ZC_33_port, B => n337, C => n430, D => n438
, Z => n396);
U314 : IVSVTX12 port map( A => AC(33), Z => n430);
U315 : AO4ABSVTX6 port map( A => ZS_37_port, B => n337, C => n431, D => n438
, Z => n346);
U316 : IVSVTX12 port map( A => AS(37), Z => n431);
U317 : AO4ASVTX8 port map( A => AS(15), B => n337, C => n466, D => n488, Z
=> n368);
U318 : AO2NSVTX6 port map( A => ZC_32_port, B => n337, C => AC(32), D =>
LOAD, Z => n397);
ZC_reg_21_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n408, Q
=> ZC_21_port);
U319 : AO2NSVTX8 port map( A => ZC_21_port, B => n337, C => AC(21), D =>
LOAD, Z => n408);
U320 : AO4ABSVTX6 port map( A => ZC_30_port, B => n438, C => n432, D => n462
, Z => n399);
U321 : IVSVTX12 port map( A => AC(30), Z => n432);
ZC_reg_30_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n399, Q
=> ZC_30_port);
U322 : IVSVTX8 port map( A => LOAD, Z => n438);
U323 : IVSVTX4 port map( A => n441, Z => n338);
U324 : AO2ASVTX6 port map( A => n444, B => AS(45), C => n442, D => n443, Z
=> n441);
U325 : AO4ABSVTX4 port map( A => ZC_20_port, B => n433, C => n433, D => n471
, Z => n409);
U326 : IVSVTX8 port map( A => n488, Z => n433);
ZC_reg_20_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n409, Q
=> ZC_20_port);
U327 : AO2NSVTX4 port map( A => ZS_20_port, B => n337, C => AS(20), D =>
LOAD, Z => n363);
U328 : IVSVTX12 port map( A => n434, Z => n404);
U329 : IVSVTX12 port map( A => n479, Z => n435);
U330 : IVSVTX12 port map( A => n488, Z => n436);
U331 : AO2NSVTX8 port map( A => ZS_24_port, B => n337, C => AS(24), D =>
LOAD, Z => n359);
ZC_reg_7_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n422, Q
=> ZC_7_port);
U332 : AO4ASVTX8 port map( A => AC(7), B => n337, C => n483, D => n488, Z =>
n422);
U333 : AO4ABSVTX6 port map( A => ZC_23_port, B => n337, C => n437, D => n438
, Z => n406);
U334 : IVSVTX12 port map( A => AC(23), Z => n437);
U335 : AO4ABSVTX6 port map( A => ZC_38_port, B => n337, C => n439, D => n444
, Z => n391);
U336 : IVSVTX12 port map( A => AC(38), Z => n439);
U337 : IVSVTX6 port map( A => AC(24), Z => n478);
U338 : AO2NSVTX6 port map( A => ZS_44_port, B => n337, C => AS(44), D =>
LOAD, Z => n339);
U339 : AO4ABSVTX6 port map( A => ZS_32_port, B => n337, C => n440, D => n444
, Z => n351);
U340 : IVSVTX12 port map( A => AS(32), Z => n440);
U341 : IVSVTX8 port map( A => LOAD, Z => n444);
U342 : IVSVTX12 port map( A => n481, Z => n442);
U343 : IVSVTX12 port map( A => n488, Z => n443);
U344 : AO2NSVTX6 port map( A => ZS_27_port, B => n337, C => AS(27), D =>
LOAD, Z => n356);
U345 : AO2NSVTX1 port map( A => ZS_0_port, B => n337, C => AS(0), D => LOAD,
Z => n383);
U346 : IVSVTX6 port map( A => AC(15), Z => n467);
U347 : AO2NSVTX4 port map( A => AS(21), B => n445, C => n446, D => n447, Z
=> n362);
U348 : IVSVTX12 port map( A => n468, Z => n446);
U349 : IVSVTX12 port map( A => n488, Z => n447);
U350 : AO4ABSVTX6 port map( A => ZS_22_port, B => n337, C => n448, D => n452
, Z => n361);
U351 : IVSVTX12 port map( A => AS(22), Z => n448);
U352 : AO2NSVTX2 port map( A => ZS_34_port, B => n337, C => AS(34), D =>
LOAD, Z => n349);
U353 : AO2NSVTX6 port map( A => ZS_8_port, B => n337, C => AS(8), D => LOAD,
Z => n375);
ZC_reg_39_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n390, Q
=> ZC_39_port);
U354 : AO4ABSVTX2 port map( A => ZC_39_port, B => n452, C => n472, D => n337
, Z => n390);
U355 : IVSVTX4 port map( A => AC(20), Z => n471);
U356 : AO2NSVTX2 port map( A => ZC_45_port, B => n337, C => AC(45), D =>
LOAD, Z => n384);
U357 : AO4ASVTX4 port map( A => AS(13), B => n337, C => n469, D => n488, Z
=> n370);
U358 : AO2NSVTX6 port map( A => ZS_18_port, B => n337, C => AS(18), D =>
LOAD, Z => n365);
U359 : AO4ASVTX4 port map( A => AS(11), B => n337, C => n470, D => n488, Z
=> n372);
U360 : AO2NSVTX6 port map( A => ZC_11_port, B => n337, C => AC(11), D =>
LOAD, Z => n418);
U361 : IVSVTX6 port map( A => AS(19), Z => n489);
U362 : IVSVTX6 port map( A => AS(14), Z => n464);
U363 : AO2NSVTX2 port map( A => ZC_2_port, B => n337, C => AC(2), D => LOAD,
Z => n427);
U364 : AO4ASVTX8 port map( A => AS(10), B => n337, C => n486, D => n488, Z
=> n373);
U365 : AO4ASVTX8 port map( A => AS(39), B => n337, C => n482, D => n488, Z
=> n344);
U366 : IVSVTX4 port map( A => n476, Z => n405);
U367 : AO4NSVTX8 port map( A => n477, B => n488, C => n478, D => n337, Z =>
n476);
U368 : IVSVTX6 port map( A => AS(33), Z => n474);
U369 : AO2NSVTX2 port map( A => ZC_1_port, B => n337, C => AC(1), D => LOAD,
Z => n428);
U370 : IVSVTX4 port map( A => n449, Z => n411);
U371 : AO2SVTX6 port map( A => AC(18), B => n450, C => n451, D => n452, Z =>
n449);
ZC_reg_19_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n410, Q
=> ZC_19_port);
U372 : AO2NSVTX8 port map( A => ZC_19_port, B => n337, C => AC(19), D =>
LOAD, Z => n410);
U373 : AO2NSVTX8 port map( A => ZC_17_port, B => n337, C => AC(17), D =>
LOAD, Z => n412);
U374 : AO2NSVTX6 port map( A => ZC_40_port, B => n337, C => AC(40), D =>
LOAD, Z => n389);
U375 : IVSVTX8 port map( A => n488, Z => n452);
U376 : AO2NSVTX6 port map( A => ZS_12_port, B => n337, C => AS(12), D =>
LOAD, Z => n371);
U377 : AO2NSVTX8 port map( A => ZC_16_port, B => n337, C => AC(16), D =>
LOAD, Z => n413);
ZS_reg_9_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n374, Q
=> ZS_9_port);
U378 : AO2NSVTX8 port map( A => ZS_9_port, B => n337, C => AS(9), D => LOAD,
Z => n374);
U379 : AO2NSVTX8 port map( A => ZC_35_port, B => n337, C => AC(35), D =>
LOAD, Z => n394);
U380 : IVSVTX12 port map( A => n475, Z => n451);
U381 : AO4ASVTX8 port map( A => AS(3), B => n459, C => n453, D => n454, Z =>
n380);
U382 : IVSVTX12 port map( A => ZS_3_port, Z => n453);
U383 : AO2NSVTX6 port map( A => ZS_23_port, B => n337, C => AS(23), D =>
LOAD, Z => n360);
ZS_reg_29_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n354, Q
=> ZS_29_port);
U384 : AO2NSVTX8 port map( A => ZS_29_port, B => n337, C => AS(29), D =>
LOAD, Z => n354);
U385 : AO4ASVTX8 port map( A => AC(10), B => n459, C => n455, D => n456, Z
=> n419);
U386 : IVSVTX12 port map( A => ZC_10_port, Z => n455);
U387 : IVSVTX8 port map( A => n488, Z => n459);
U388 : AO2NSVTX2 port map( A => ZS_42_port, B => n337, C => AS(42), D =>
LOAD, Z => n341);
U389 : AO2NSVTX4 port map( A => AS(17), B => n457, C => n458, D => n459, Z
=> n366);
U390 : IVSVTX12 port map( A => n480, Z => n458);
U391 : AO2NSVTX8 port map( A => ZC_43_port, B => n337, C => AC(43), D =>
LOAD, Z => n386);
U392 : AO4ABSVTX4 port map( A => ZS_7_port, B => n337, C => n460, D => n462,
Z => n376);
U393 : IVSVTX12 port map( A => AS(7), Z => n460);
U394 : AO4ABSVTX2 port map( A => ZC_12_port, B => n462, C => n485, D => n337
, Z => n417);
U395 : AO4ABSVTX6 port map( A => n461, B => n462, C => n462, D => n489, Z =>
n364);
U396 : IVSVTX12 port map( A => n487, Z => n461);
U397 : IVSVTX8 port map( A => n488, Z => n462);
U398 : AO4ABSVTX4 port map( A => AC(22), B => LOAD, C => n463, D => n488, Z
=> n407);
U399 : IVSVTX12 port map( A => ZC_22_port, Z => n463);
U400 : AO2NSVTX2 port map( A => ZC_4_port, B => n337, C => AC(4), D => LOAD,
Z => n425);
U401 : AO4ABSVTX6 port map( A => ZS_14_port, B => n337, C => n464, D => n337
, Z => n369);
U402 : AO4ABSVTX4 port map( A => ZC_14_port, B => n337, C => n465, D => n337
, Z => n415);
U403 : IVSVTX12 port map( A => AC(14), Z => n465);
U404 : IVSVTX12 port map( A => ZS_15_port, Z => n466);
U405 : IVSVTX12 port map( A => ZS_21_port, Z => n468);
U406 : IVSVTX12 port map( A => ZS_13_port, Z => n469);
U407 : IVSVTX12 port map( A => ZS_11_port, Z => n470);
U408 : IVSVTX12 port map( A => AC(39), Z => n472);
U409 : IVSVTX12 port map( A => ZS_33_port, Z => n473);
ZC_reg_27_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n402, Q
=> ZC_27_port);
U410 : IVSVTX12 port map( A => ZC_18_port, Z => n475);
U411 : IVSVTX4 port map( A => AC(12), Z => n485);
U412 : IVSVTX12 port map( A => ZC_24_port, Z => n477);
U413 : AO2NSVTX2 port map( A => ZS_40_port, B => n337, C => AS(40), D =>
LOAD, Z => n343);
U414 : AO2NSVTX2 port map( A => ZC_28_port, B => n337, C => AC(28), D =>
LOAD, Z => n401);
ZC_reg_18_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n411, Q
=> ZC_18_port);
U415 : IVSVTX12 port map( A => ZC_25_port, Z => n479);
U416 : IVSVTX12 port map( A => ZS_17_port, Z => n480);
U417 : IVSVTX12 port map( A => ZS_45_port, Z => n481);
U418 : AO2NSVTX2 port map( A => ZS_35_port, B => n337, C => AS(35), D =>
LOAD, Z => n348);
ZC_reg_4_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n425, Q
=> ZC_4_port);
ZC_reg_25_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n404, Q
=> ZC_25_port);
ZS_reg_22_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n361, Q
=> ZS_22_port);
U419 : AO2NSVTX1 port map( A => ZS_1_port, B => n337, C => AS(1), D => LOAD,
Z => n382);
U420 : IVSVTX12 port map( A => ZS_39_port, Z => n482);
U421 : IVSVTX12 port map( A => ZC_7_port, Z => n483);
U422 : AO4ASVTX8 port map( A => AS(30), B => n337, C => n484, D => n488, Z
=> n353);
U423 : IVSVTX12 port map( A => ZS_30_port, Z => n484);
U424 : IVSVTX12 port map( A => ZS_10_port, Z => n486);
U425 : AO2NSVTX2 port map( A => ZS_26_port, B => n337, C => AS(26), D =>
LOAD, Z => n357);
U426 : AO2NSVTX2 port map( A => ZS_36_port, B => n337, C => AS(36), D =>
LOAD, Z => n347);
U427 : AO2NSVTX2 port map( A => ZS_25_port, B => n337, C => AS(25), D =>
LOAD, Z => n358);
U428 : IVSVTX12 port map( A => ZS_19_port, Z => n487);
U429 : AO2NSVTX2 port map( A => ZC_27_port, B => n337, C => AC(27), D =>
LOAD, Z => n402);
U430 : AO4ABSVTX4 port map( A => ZC_9_port, B => n337, C => n492, D => n337,
Z => n420);
U431 : AO2NSVTX6 port map( A => ZS_38_port, B => n337, C => AS(38), D =>
LOAD, Z => n490);
U432 : AO2NSVTX2 port map( A => ZS_43_port, B => n337, C => AS(43), D =>
LOAD, Z => n340);
U433 : AO4ABSVTX6 port map( A => ZC_5_port, B => n337, C => n491, D => n337,
Z => n424);
U434 : IVSVTX12 port map( A => AC(5), Z => n491);
ZC_reg_44_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n385, Q
=> ZC_44_port);
U435 : AO2NSVTX2 port map( A => ZC_44_port, B => n337, C => AC(44), D =>
LOAD, Z => n385);
U436 : AO2NSVTX2 port map( A => ZC_34_port, B => n337, C => AC(34), D =>
LOAD, Z => n395);
ZC_reg_24_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n405, Q
=> ZC_24_port);
U437 : IVSVTX4 port map( A => AC(9), Z => n492);
ZC_reg_28_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n401, Q
=> ZC_28_port);
U438 : AO2NSVTX2 port map( A => ZC_41_port, B => n337, C => AC(41), D =>
LOAD, Z => n388);
U439 : AO2NSVTX4 port map( A => ZS_31_port, B => n337, C => AS(31), D =>
LOAD, Z => n352);
U440 : AO2NSVTX1 port map( A => ZS_4_port, B => n337, C => AS(4), D => LOAD,
Z => n379);
ZS_reg_5_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n378, Q
=> ZS_5_port);
U441 : AO2NSVTX6 port map( A => ZS_5_port, B => n337, C => AS(5), D => LOAD,
Z => n378);
ZC_reg_16_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n413, Q
=> ZC_16_port);
ZC_reg_5_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n424, Q
=> ZC_5_port);
U442 : AO2NSVTX4 port map( A => ZC_8_port, B => n337, C => AC(8), D => LOAD,
Z => n421);
U443 : AO2NSVTX6 port map( A => ZS_28_port, B => n337, C => AS(28), D =>
LOAD, Z => n355);
ZC_reg_11_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n418, Q
=> ZC_11_port);
ZC_reg_41_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n388, Q
=> ZC_41_port);
U444 : AO2NSVTX6 port map( A => ZS_2_port, B => n337, C => AS(2), D => LOAD,
Z => n381);
ZS_reg_24_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n359, Q
=> ZS_24_port);
ZS_reg_41_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n342, Q
=> ZS_41_port);
U445 : AO2NSVTX6 port map( A => ZS_41_port, B => n337, C => AS(41), D =>
LOAD, Z => n342);
ZS_reg_16_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n367, Q
=> ZS_16_port);
U446 : AO2NSVTX6 port map( A => ZS_16_port, B => n337, C => AS(16), D =>
LOAD, Z => n367);
ZS_reg_6_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n377, Q
=> ZS_6_port);
U447 : AO2NSVTX6 port map( A => ZS_6_port, B => n337, C => AS(6), D => LOAD,
Z => n377);
ZC_reg_10_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n419, Q
=> ZC_10_port);
U448 : AO2NSVTX6 port map( A => ZC_42_port, B => n337, C => AC(42), D =>
LOAD, Z => n387);
U449 : AO2NSVTX6 port map( A => ZC_29_port, B => n337, C => AC(29), D =>
LOAD, Z => n400);
U450 : AO2NSVTX6 port map( A => ZC_37_port, B => n337, C => AC(37), D =>
LOAD, Z => n392);
ZC_reg_33_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n396, Q
=> ZC_33_port);
ZC_reg_32_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n397, Q
=> ZC_32_port);
U451 : AO2NSVTX6 port map( A => ZC_31_port, B => n337, C => AC(31), D =>
LOAD, Z => n398);
U452 : AO2NSVTX6 port map( A => ZC_6_port, B => n337, C => AC(6), D => LOAD,
Z => n423);
U453 : AO2NSVTX8 port map( A => ZC_3_port, B => n337, C => AC(3), D => LOAD,
Z => n426);
ZC_reg_13_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n416, Q
=> ZC_13_port);
U454 : AO2NSVTX4 port map( A => ZC_13_port, B => n337, C => AC(13), D =>
LOAD, Z => n416);
U455 : IVSVTX12 port map( A => LOAD, Z => n337);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity QDS_TABLE is
port( D : in std_logic_vector (2 downto 0); Y : in std_logic_vector (6
downto 0); M1, M2, P1, P2 : out std_logic);
end QDS_TABLE;
architecture SYN_BEHAVIORAL of QDS_TABLE is
component AO7HVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component NR2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component NR3SVTX6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND4ABSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component NR2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR3SVTX2
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component AO7SVTX2
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO9SVTX6
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component ND2ASVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component AO7SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO9SVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component BFSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component AO20SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO52SVTX2
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component IVHVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component AO17SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO35SVTX2
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO52SVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component AO6SVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component AO7SVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AN2BSVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO9NSVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO8SVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO17ASVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO8ASVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO1SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ENSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
signal n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3727,
n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737,
n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747,
n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757,
n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767 :
std_logic;
begin
U807 : AO7HVTX1 port map( A => n3732, B => n3749, C => D(2), Z => n3748);
U826 : NR2HVTX1 port map( A => D(0), B => D(1), Z => n3739);
U828 : IVHVTX0H port map( A => D(0), Z => n3744);
U830 : IVSVTX4 port map( A => Y(0), Z => n3742);
U831 : NR3SVTX6 port map( A => n3733, B => n3764, C => n3734, Z => P1);
U832 : ND4ABSVTX6 port map( A => Y(2), B => Y(3), C => n3727, D => n3730, Z
=> n3717);
U833 : NR2SVTX2 port map( A => D(2), B => D(1), Z => n3758);
U834 : NR3SVTX2 port map( A => n3759, B => Y(2), C => n3740, Z => n3737);
U835 : IVSVTX0H port map( A => n3758, Z => n3759);
U836 : AO7SVTX2 port map( A => n3741, B => n3742, C => n3760, Z => n3740);
U837 : AO7SVTX2 port map( A => n3761, B => n3737, C => n3738, Z => n3736);
U838 : AO9SVTX6 port map( A => n3761, B => n3722, C => n3735, D => n3736, E
=> n3765, Z => n3734);
U839 : ND2ASVTX8 port map( A => n3744, B => Y(1), Z => n3760);
U840 : IVSVTX8 port map( A => n3760, Z => n3731);
U841 : AO7SVTX4 port map( A => n3720, B => n3721, C => n3722, Z => n3718);
U842 : AO9SVTX4 port map( A => n3765, B => D(2), C => n3752, D => n3753, E
=> n3722, Z => n3751);
U843 : BFSVTX6 port map( A => Y(3), Z => n3761);
U844 : AO20SVTX2 port map( A => n3725, B => n3744, C => n3757, D => n3761, Z
=> n3752);
U845 : AO52SVTX2 port map( A => n3750, B => n3739, C => Y(3), D => n3727, E
=> Y(2), Z => n3745);
U846 : IVHVTX1 port map( A => Y(5), Z => n3762);
U847 : NR3SVTX6 port map( A => n3766, B => n3751, C => n3763, Z => M1);
U848 : IVSVTX1 port map( A => n3762, Z => n3763);
U849 : AO17SVTX2 port map( A => D(1), B => D(0), C => n3729, D => n3720, Z
=> n3747);
U850 : AO35SVTX2 port map( A => n3727, B => n3725, C => n3741, D => n3743, E
=> n3729, Z => n3735);
U851 : IVSVTX4 port map( A => n3722, Z => n3765);
U852 : AO52SVTX4 port map( A => n3739, B => n3732, C => n3727, D => n3729, E
=> Y(3), Z => n3738);
U853 : IVSVTX8 port map( A => Y(5), Z => n3733);
U854 : AO7SVTX2 port map( A => n3732, B => n3749, C => n3729, Z => n3757);
U855 : IVSVTX2 port map( A => n3739, Z => n3749);
U856 : AO6SVTX1 port map( A => n3731, B => D(1), C => D(2), Z => n3743);
U857 : IVSVTX4 port map( A => n3766, Z => n3764);
U858 : IVSVTX4 port map( A => n3719, Z => n3766);
U859 : IVSVTX12 port map( A => Y(1), Z => n3732);
U860 : AO7SVTX4 port map( A => D(0), B => n3742, C => D(1), Z => n3756);
U861 : AO20SVTX2 port map( A => D(0), B => n3742, C => D(1), D => n3732, Z
=> n3750);
U862 : IVSVTX4 port map( A => n3767, Z => n3723);
U863 : AO7SVTX1 port map( A => n3725, B => n3760, C => n3727, Z => n3724);
U864 : AN2BSVTX4 port map( A => n3732, B => D(0), Z => n3741);
U865 : AO7SVTX2 port map( A => n3747, B => n3748, C => Y(4), Z => n3746);
U866 : AO9NSVTX4 port map( A => n3754, B => n3720, C => Y(2), D => n3755, E
=> Y(3), Z => n3753);
U867 : AO52SVTX2 port map( A => Y(1), B => n3739, C => n3756, D => n3727, E
=> Y(2), Z => n3755);
U868 : IVSVTX4 port map( A => Y(4), Z => n3722);
U869 : AO8SVTX4 port map( A => n3745, B => n3733, C => n3746, D => Y(6), Z
=> M2);
U870 : IVSVTX4 port map( A => Y(2), Z => n3729);
U871 : IVSVTX4 port map( A => Y(3), Z => n3720);
U872 : AO17ASVTX8 port map( A => n3760, B => D(2), C => n3728, D => D(1), Z
=> n3767);
U873 : IVSVTX1 port map( A => D(2), Z => n3727);
U874 : IVSVTX1 port map( A => D(1), Z => n3725);
U875 : AO8ASVTX6 port map( A => n3733, B => n3717, C => n3718, D => n3719, Z
=> P2);
U876 : IVSVTX8 port map( A => Y(6), Z => n3719);
U877 : AO1SVTX2 port map( A => Y(0), B => n3728, C => D(1), D => n3731, Z =>
n3730);
U878 : ENSVTX8 port map( A => n3732, B => D(0), Z => n3728);
U879 : AO7SVTX2 port map( A => Y(2), B => n3723, C => n3724, Z => n3721);
U880 : AO7SVTX2 port map( A => D(1), B => n3732, C => D(2), Z => n3754);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity QDS_ADDER is
port( A1, A2 : in std_logic_vector (6 downto 0); Y : out std_logic_vector
(6 downto 0));
end QDS_ADDER;
architecture SYN_BEHAVIORAL of QDS_ADDER is
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component ND2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO7SVTX6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO5SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component AO7CSVTX6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EOSVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component EO3SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component BFSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component AO7ABSVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EO3SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EO3SVTX2
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EOHVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
signal n228, n229, n230, n231, n232, n233, n234, n236, n237, n238, n239,
n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252 : std_logic;
begin
U51 : IVSVTX8 port map( A => A2(1), Z => n240);
U52 : ND2SVTX6 port map( A => A2(0), B => A1(0), Z => n249);
U53 : AO7SVTX6 port map( A => A1(2), B => n238, C => A2(2), Z => n236);
U54 : AO5SVTX8 port map( A => n239, B => n240, C => n249, Z => n238);
U55 : IVSVTX12 port map( A => A1(1), Z => n239);
U56 : AO7CSVTX6 port map( A => n241, B => n231, C => n242, Z => n232);
U57 : IVSVTX12 port map( A => n246, Z => n241);
U58 : IVSVTX12 port map( A => A2(4), Z => n242);
U59 : AO7CSVTX6 port map( A => n243, B => n233, C => n244, Z => n234);
U60 : IVSVTX12 port map( A => n245, Z => n243);
U61 : IVSVTX12 port map( A => A2(3), Z => n244);
U62 : IVSVTX12 port map( A => A1(3), Z => n245);
U63 : IVSVTX12 port map( A => A1(4), Z => n246);
U64 : EOSVTX2 port map( A => A2(3), B => A1(3), Z => n247);
U65 : EOSVTX4 port map( A => n233, B => n247, Z => Y(3));
U66 : EO3SVTX8 port map( A => A2(1), B => A1(1), C => n248, Z => Y(1));
U67 : BFSVTX4 port map( A => n237, Z => n248);
U68 : IVSVTX4 port map( A => n249, Z => n237);
U69 : AO7CSVTX6 port map( A => n250, B => n229, C => n251, Z => n230);
U70 : IVSVTX12 port map( A => n252, Z => n250);
U71 : IVSVTX12 port map( A => A2(5), Z => n251);
U72 : IVSVTX12 port map( A => A1(5), Z => n252);
U73 : AO7ABSVTX8 port map( A => A1(5), B => n229, C => n230, Z => n228);
U74 : EO3SVTX4 port map( A => A2(5), B => A1(5), C => n229, Z => Y(5));
U75 : AO7ABSVTX8 port map( A => A1(4), B => n231, C => n232, Z => n229);
U76 : AO7ABSVTX8 port map( A => A1(3), B => n233, C => n234, Z => n231);
U77 : EO3SVTX2 port map( A => A2(4), B => A1(4), C => n231, Z => Y(4));
U78 : EO3SVTX8 port map( A => A2(6), B => A1(6), C => n228, Z => Y(6));
U79 : EOHVTX2 port map( A => A2(0), B => A1(0), Z => Y(0));
U80 : AO7ABSVTX8 port map( A => A1(2), B => n238, C => n236, Z => n233);
U81 : EO3SVTX4 port map( A => A2(2), B => A1(2), C => n238, Z => Y(2));
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity QDSEL is
port( A1, A2 : in std_logic_vector (6 downto 0); D : in std_logic_vector (2
downto 0); M1, M2, P1, P2 : out std_logic);
end QDSEL;
architecture SYN_SCHEMATIC of QDSEL is
component QDS_TABLE
port( D : in std_logic_vector (2 downto 0); Y : in std_logic_vector (6
downto 0); M1, M2, P1, P2 : out std_logic);
end component;
component QDS_ADDER
port( A1, A2 : in std_logic_vector (6 downto 0); Y : out
std_logic_vector (6 downto 0));
end component;
signal Y_6_port, Y_5_port, Y_4_port, Y_3_port, Y_2_port, Y_1_port, Y_0_port
: std_logic;
begin
I_1 : QDS_TABLE port map( D(2) => D(2), D(1) => D(1), D(0) => D(0), Y(6) =>
Y_6_port, Y(5) => Y_5_port, Y(4) => Y_4_port, Y(3)
=> Y_3_port, Y(2) => Y_2_port, Y(1) => Y_1_port,
Y(0) => Y_0_port, M1 => M1, M2 => M2, P1 => P1, P2
=> P2);
I_2 : QDS_ADDER port map( A1(6) => A1(6), A1(5) => A1(5), A1(4) => A1(4),
A1(3) => A1(3), A1(2) => A1(2), A1(1) => A1(1),
A1(0) => A1(0), A2(6) => A2(6), A2(5) => A2(5),
A2(4) => A2(4), A2(3) => A2(3), A2(2) => A2(2),
A2(1) => A2(1), A2(0) => A2(0), Y(6) => Y_6_port,
Y(5) => Y_5_port, Y(4) => Y_4_port, Y(3) => Y_3_port
, Y(2) => Y_2_port, Y(1) => Y_1_port, Y(0) =>
Y_0_port);
end SYN_SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity divr4_rec is
port( CLOCK : in std_logic; D : in std_logic_vector (52 downto 0); RESET :
in std_logic; X : in std_logic_vector (53 downto 0); Qj : out
std_logic_vector (3 downto 0));
end divr4_rec;
architecture SYN_SCHEMATIC of divr4_rec is
component CONTROL
port( CLOCK, RESET : in std_logic; CL1, DIGIT, LD1, MX1, ROUND : out
std_logic);
end component;
component MUX
port( A, B : in std_logic_vector (56 downto 0); SEL : in std_logic; Z :
out std_logic_vector (56 downto 0));
end component;
component MULT
port( A : in std_logic_vector (54 downto 0); M1, M2, P1, P2 : in
std_logic; COUT : out std_logic; Z : out std_logic_vector (56
downto 0));
end component;
component gl_csa32_n8
port( A, B, C : in std_logic_vector (8 downto 0); Cin : in std_logic; Z
, Y : out std_logic_vector (8 downto 0));
end component;
component csa32LSBs_n47
port( A, B, C : in std_logic_vector (47 downto 0); Cin : in std_logic;
Cout : out std_logic; Z, Y : out std_logic_vector (47 downto 0));
end component;
component gl_dualreg_ld_n10
port( AS, AC : in std_logic_vector (10 downto 0); RESET, CLOCK, LOAD :
in std_logic; ZS, ZC : out std_logic_vector (10 downto 0));
end component;
component gl_dualreg_ld_n45
port( AS, AC : in std_logic_vector (45 downto 0); RESET, CLOCK, LOAD :
in std_logic; ZS, ZC : out std_logic_vector (45 downto 0));
end component;
component QDSEL
port( A1, A2 : in std_logic_vector (6 downto 0); D : in std_logic_vector
(2 downto 0); M1, M2, P1, P2 : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component BFHVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component BFSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
signal GND, W1_56_port, W1_55_port, W1_54_port, W1_53_port, W1_52_port,
W1_51_port, W1_50_port, W1_49_port, W1_48_port, W1_47_port, W1_46_port,
W1_45_port, W1_44_port, W1_43_port, W1_42_port, W1_41_port, W1_40_port,
W1_39_port, W1_38_port, W1_37_port, W1_36_port, W1_35_port, W1_34_port,
W1_33_port, W1_32_port, W1_31_port, W1_30_port, W1_29_port, W1_28_port,
W1_27_port, W1_26_port, W1_25_port, W1_24_port, W1_23_port, W1_22_port,
W1_21_port, W1_20_port, W1_19_port, W1_18_port, W1_17_port, W1_16_port,
W1_15_port, W1_14_port, W1_13_port, W1_12_port, W1_11_port, W1_10_port,
W1_9_port, W1_8_port, W1_7_port, W1_6_port, W1_5_port, W1_4_port,
W1_3_port, W1_2_port, W1_1_port, W1_0_port, W2_56_port, W2_55_port,
W2_54_port, W2_53_port, W2_52_port, W2_51_port, W2_50_port, W2_49_port,
W2_48_port, W2_47_port, W2_46_port, W2_45_port, W2_44_port, W2_43_port,
W2_42_port, W2_41_port, W2_40_port, W2_39_port, W2_38_port, W2_37_port,
W2_36_port, W2_35_port, W2_34_port, W2_33_port, W2_32_port, W2_31_port,
W2_30_port, W2_29_port, W2_28_port, W2_27_port, W2_26_port, W2_25_port,
W2_24_port, W2_23_port, W2_22_port, W2_21_port, W2_20_port, W2_19_port,
W2_18_port, W2_17_port, W2_16_port, W2_15_port, W2_14_port, W2_13_port,
W2_12_port, W2_11_port, W2_10_port, W2_9_port, W2_8_port, W2_7_port,
W2_6_port, W2_5_port, W2_4_port, W2_3_port, W2_2_port, W2_1_port,
W2_0_port, CLR, LOAD, muxW, n112, Qj_2_port, n113, n114, MXLA_56_port,
MXLA_55_port, MXLA_54_port, MXLA_53_port, MXLA_52_port, MXLA_51_port,
MXLA_50_port, MXLA_49_port, MXLA_48_port, MXLA_47_port, MXLA_46_port,
MXLA_45_port, MXLA_44_port, MXLA_43_port, MXLA_42_port, MXLA_41_port,
MXLA_40_port, MXLA_39_port, MXLA_38_port, MXLA_37_port, MXLA_36_port,
MXLA_35_port, MXLA_34_port, MXLA_33_port, MXLA_32_port, MXLA_31_port,
MXLA_30_port, MXLA_29_port, MXLA_28_port, MXLA_27_port, MXLA_26_port,
MXLA_25_port, MXLA_24_port, MXLA_23_port, MXLA_22_port, MXLA_21_port,
MXLA_20_port, MXLA_19_port, MXLA_18_port, MXLA_17_port, MXLA_16_port,
MXLA_15_port, MXLA_14_port, MXLA_13_port, MXLA_12_port, MXLA_11_port,
MXLA_10_port, MXLA_9_port, MXLA_8_port, MXLA_7_port, MXLA_6_port,
MXLA_5_port, MXLA_4_port, MXLA_3_port, MXLA_2_port, MXLA_1_port,
MXLA_0_port, qjD_c2, qjD_56_port, qjD_55_port, qjD_54_port, qjD_53_port,
qjD_52_port, qjD_51_port, qjD_50_port, qjD_49_port, qjD_48_port,
qjD_47_port, qjD_46_port, qjD_45_port, qjD_44_port, qjD_43_port,
qjD_42_port, qjD_41_port, qjD_40_port, qjD_39_port, qjD_38_port,
qjD_37_port, qjD_36_port, qjD_35_port, qjD_34_port, qjD_33_port,
qjD_32_port, qjD_31_port, qjD_30_port, qjD_29_port, qjD_28_port,
qjD_27_port, qjD_26_port, qjD_25_port, qjD_24_port, qjD_23_port,
qjD_22_port, qjD_21_port, qjD_20_port, qjD_19_port, qjD_18_port,
qjD_17_port, qjD_16_port, qjD_15_port, qjD_14_port, qjD_13_port,
qjD_12_port, qjD_11_port, qjD_10_port, qjD_9_port, qjD_8_port, qjD_7_port
, qjD_6_port, qjD_5_port, qjD_4_port, qjD_3_port, qjD_2_port, qjD_1_port,
qjD_0_port, carry_ex, WC_56_port, WC_55_port, WC_54_port, WC_53_port,
WC_52_port, WC_51_port, WC_50_port, WC_49_port, WC_48_port, WC_47_port,
WC_46_port, WC_45_port, WC_44_port, WC_43_port, WC_42_port, WC_41_port,
WC_40_port, WC_39_port, WC_38_port, WC_37_port, WC_36_port, WC_35_port,
WC_34_port, WC_33_port, WC_32_port, WC_31_port, WC_30_port, WC_29_port,
WC_28_port, WC_27_port, WC_26_port, WC_25_port, WC_24_port, WC_23_port,
WC_22_port, WC_21_port, WC_20_port, WC_19_port, WC_18_port, WC_17_port,
WC_16_port, WC_15_port, WC_14_port, WC_13_port, WC_12_port, WC_11_port,
WC_10_port, WC_9_port, WC_8_port, WC_7_port, WC_6_port, WC_5_port,
WC_4_port, WC_3_port, WC_2_port, WC_1_port, WC_0_port, WS_56_port,
WS_55_port, WS_54_port, WS_53_port, WS_52_port, WS_51_port, WS_50_port,
WS_49_port, WS_48_port, WS_47_port, WS_46_port, WS_45_port, WS_44_port,
WS_43_port, WS_42_port, WS_41_port, WS_40_port, WS_39_port, WS_38_port,
WS_37_port, WS_36_port, WS_35_port, WS_34_port, WS_33_port, WS_32_port,
WS_31_port, WS_30_port, WS_29_port, WS_28_port, WS_27_port, WS_26_port,
WS_25_port, WS_24_port, WS_23_port, WS_22_port, WS_21_port, WS_20_port,
WS_19_port, WS_18_port, WS_17_port, WS_16_port, WS_15_port, WS_14_port,
WS_13_port, WS_12_port, WS_11_port, WS_10_port, WS_9_port, WS_8_port,
WS_7_port, WS_6_port, WS_5_port, WS_4_port, WS_3_port, WS_2_port,
WS_1_port, WS_0_port, n104, n105, n106, Qj_3_port, Qj_0_port, n109,
Qj_1_port, n111, n_1001, n_1002 : std_logic;
begin
Qj <= ( Qj_3_port, Qj_2_port, Qj_1_port, Qj_0_port );
GND <= '0';
I_CTRL : CONTROL port map( CLOCK => CLOCK, RESET => RESET, CL1 => CLR, DIGIT
=> n_1001, LD1 => LOAD, MX1 => muxW, ROUND => n_1002
);
I_MUX : MUX port map( A(56) => GND, A(55) => GND, A(54) => GND, A(53) =>
X(53), A(52) => X(52), A(51) => X(51), A(50) =>
X(50), A(49) => X(49), A(48) => X(48), A(47) =>
X(47), A(46) => X(46), A(45) => X(45), A(44) =>
X(44), A(43) => X(43), A(42) => X(42), A(41) =>
X(41), A(40) => X(40), A(39) => X(39), A(38) =>
X(38), A(37) => X(37), A(36) => X(36), A(35) =>
X(35), A(34) => X(34), A(33) => X(33), A(32) =>
X(32), A(31) => X(31), A(30) => X(30), A(29) =>
X(29), A(28) => X(28), A(27) => X(27), A(26) =>
X(26), A(25) => X(25), A(24) => X(24), A(23) =>
X(23), A(22) => X(22), A(21) => X(21), A(20) =>
X(20), A(19) => X(19), A(18) => X(18), A(17) =>
X(17), A(16) => X(16), A(15) => X(15), A(14) =>
X(14), A(13) => X(13), A(12) => X(12), A(11) =>
X(11), A(10) => X(10), A(9) => X(9), A(8) => X(8),
A(7) => X(7), A(6) => X(6), A(5) => X(5), A(4) =>
X(4), A(3) => X(3), A(2) => X(2), A(1) => X(1), A(0)
=> X(0), B(56) => W1_54_port, B(55) => W1_53_port,
B(54) => W1_52_port, B(53) => W1_51_port, B(52) =>
W1_50_port, B(51) => W1_49_port, B(50) => W1_48_port
, B(49) => W1_47_port, B(48) => W1_46_port, B(47) =>
W1_45_port, B(46) => W1_44_port, B(45) => W1_43_port
, B(44) => W1_42_port, B(43) => W1_41_port, B(42) =>
W1_40_port, B(41) => W1_39_port, B(40) => W1_38_port
, B(39) => W1_37_port, B(38) => W1_36_port, B(37) =>
W1_35_port, B(36) => W1_34_port, B(35) => W1_33_port
, B(34) => W1_32_port, B(33) => W1_31_port, B(32) =>
W1_30_port, B(31) => W1_29_port, B(30) => W1_28_port
, B(29) => W1_27_port, B(28) => W1_26_port, B(27) =>
W1_25_port, B(26) => W1_24_port, B(25) => W1_23_port
, B(24) => W1_22_port, B(23) => W1_21_port, B(22) =>
W1_20_port, B(21) => W1_19_port, B(20) => W1_18_port
, B(19) => W1_17_port, B(18) => W1_16_port, B(17) =>
W1_15_port, B(16) => W1_14_port, B(15) => W1_13_port
, B(14) => W1_12_port, B(13) => W1_11_port, B(12) =>
W1_10_port, B(11) => W1_9_port, B(10) => W1_8_port,
B(9) => W1_7_port, B(8) => W1_6_port, B(7) =>
W1_5_port, B(6) => W1_4_port, B(5) => W1_3_port,
B(4) => W1_2_port, B(3) => W1_1_port, B(2) =>
W1_0_port, B(1) => GND, B(0) => GND, SEL => muxW,
Z(56) => MXLA_56_port, Z(55) => MXLA_55_port, Z(54)
=> MXLA_54_port, Z(53) => MXLA_53_port, Z(52) =>
MXLA_52_port, Z(51) => MXLA_51_port, Z(50) =>
MXLA_50_port, Z(49) => MXLA_49_port, Z(48) =>
MXLA_48_port, Z(47) => MXLA_47_port, Z(46) =>
MXLA_46_port, Z(45) => MXLA_45_port, Z(44) =>
MXLA_44_port, Z(43) => MXLA_43_port, Z(42) =>
MXLA_42_port, Z(41) => MXLA_41_port, Z(40) =>
MXLA_40_port, Z(39) => MXLA_39_port, Z(38) =>
MXLA_38_port, Z(37) => MXLA_37_port, Z(36) =>
MXLA_36_port, Z(35) => MXLA_35_port, Z(34) =>
MXLA_34_port, Z(33) => MXLA_33_port, Z(32) =>
MXLA_32_port, Z(31) => MXLA_31_port, Z(30) =>
MXLA_30_port, Z(29) => MXLA_29_port, Z(28) =>
MXLA_28_port, Z(27) => MXLA_27_port, Z(26) =>
MXLA_26_port, Z(25) => MXLA_25_port, Z(24) =>
MXLA_24_port, Z(23) => MXLA_23_port, Z(22) =>
MXLA_22_port, Z(21) => MXLA_21_port, Z(20) =>
MXLA_20_port, Z(19) => MXLA_19_port, Z(18) =>
MXLA_18_port, Z(17) => MXLA_17_port, Z(16) =>
MXLA_16_port, Z(15) => MXLA_15_port, Z(14) =>
MXLA_14_port, Z(13) => MXLA_13_port, Z(12) =>
MXLA_12_port, Z(11) => MXLA_11_port, Z(10) =>
MXLA_10_port, Z(9) => MXLA_9_port, Z(8) =>
MXLA_8_port, Z(7) => MXLA_7_port, Z(6) =>
MXLA_6_port, Z(5) => MXLA_5_port, Z(4) =>
MXLA_4_port, Z(3) => MXLA_3_port, Z(2) =>
MXLA_2_port, Z(1) => MXLA_1_port, Z(0) =>
MXLA_0_port);
I_MULT : MULT port map( A(54) => GND, A(53) => D(52), A(52) => D(51), A(51)
=> D(50), A(50) => D(49), A(49) => D(48), A(48) =>
D(47), A(47) => D(46), A(46) => D(45), A(45) =>
D(44), A(44) => D(43), A(43) => D(42), A(42) =>
D(41), A(41) => D(40), A(40) => D(39), A(39) =>
D(38), A(38) => D(37), A(37) => D(36), A(36) =>
D(35), A(35) => D(34), A(34) => D(33), A(33) =>
D(32), A(32) => D(31), A(31) => D(30), A(30) =>
D(29), A(29) => D(28), A(28) => D(27), A(27) =>
D(26), A(26) => D(25), A(25) => D(24), A(24) =>
D(23), A(23) => D(22), A(22) => D(21), A(21) =>
D(20), A(20) => D(19), A(19) => D(18), A(18) =>
D(17), A(17) => D(16), A(16) => D(15), A(15) =>
D(14), A(14) => D(13), A(13) => D(12), A(12) =>
D(11), A(11) => D(10), A(10) => D(9), A(9) => D(8),
A(8) => D(7), A(7) => D(6), A(6) => D(5), A(5) =>
D(4), A(4) => D(3), A(3) => D(2), A(2) => D(1), A(1)
=> D(0), A(0) => GND, M1 => Qj_2_port, M2 =>
Qj_3_port, P1 => Qj_1_port, P2 => Qj_0_port, COUT =>
qjD_c2, Z(56) => qjD_56_port, Z(55) => qjD_55_port,
Z(54) => qjD_54_port, Z(53) => qjD_53_port, Z(52) =>
qjD_52_port, Z(51) => qjD_51_port, Z(50) =>
qjD_50_port, Z(49) => qjD_49_port, Z(48) =>
qjD_48_port, Z(47) => qjD_47_port, Z(46) =>
qjD_46_port, Z(45) => qjD_45_port, Z(44) =>
qjD_44_port, Z(43) => qjD_43_port, Z(42) =>
qjD_42_port, Z(41) => qjD_41_port, Z(40) =>
qjD_40_port, Z(39) => qjD_39_port, Z(38) =>
qjD_38_port, Z(37) => qjD_37_port, Z(36) =>
qjD_36_port, Z(35) => qjD_35_port, Z(34) =>
qjD_34_port, Z(33) => qjD_33_port, Z(32) =>
qjD_32_port, Z(31) => qjD_31_port, Z(30) =>
qjD_30_port, Z(29) => qjD_29_port, Z(28) =>
qjD_28_port, Z(27) => qjD_27_port, Z(26) =>
qjD_26_port, Z(25) => qjD_25_port, Z(24) =>
qjD_24_port, Z(23) => qjD_23_port, Z(22) =>
qjD_22_port, Z(21) => qjD_21_port, Z(20) =>
qjD_20_port, Z(19) => qjD_19_port, Z(18) =>
qjD_18_port, Z(17) => qjD_17_port, Z(16) =>
qjD_16_port, Z(15) => qjD_15_port, Z(14) =>
qjD_14_port, Z(13) => qjD_13_port, Z(12) =>
qjD_12_port, Z(11) => qjD_11_port, Z(10) =>
qjD_10_port, Z(9) => qjD_9_port, Z(8) => qjD_8_port,
Z(7) => qjD_7_port, Z(6) => qjD_6_port, Z(5) =>
qjD_5_port, Z(4) => qjD_4_port, Z(3) => qjD_3_port,
Z(2) => qjD_2_port, Z(1) => qjD_1_port, Z(0) =>
qjD_0_port);
I_CSA1 : gl_csa32_n8 port map( A(8) => MXLA_56_port, A(7) => MXLA_55_port,
A(6) => MXLA_54_port, A(5) => MXLA_53_port, A(4) =>
MXLA_52_port, A(3) => MXLA_51_port, A(2) =>
MXLA_50_port, A(1) => MXLA_49_port, A(0) =>
MXLA_48_port, B(8) => W2_54_port, B(7) => W2_53_port
, B(6) => W2_52_port, B(5) => n104, B(4) => n106,
B(3) => W2_49_port, B(2) => W2_48_port, B(1) =>
W2_47_port, B(0) => W2_46_port, C(8) => qjD_56_port,
C(7) => qjD_55_port, C(6) => qjD_54_port, C(5) =>
qjD_53_port, C(4) => qjD_52_port, C(3) =>
qjD_51_port, C(2) => qjD_50_port, C(1) =>
qjD_49_port, C(0) => qjD_48_port, Cin => carry_ex,
Z(8) => WS_56_port, Z(7) => WS_55_port, Z(6) =>
WS_54_port, Z(5) => WS_53_port, Z(4) => WS_52_port,
Z(3) => WS_51_port, Z(2) => WS_50_port, Z(1) =>
WS_49_port, Z(0) => WS_48_port, Y(8) => WC_56_port,
Y(7) => WC_55_port, Y(6) => WC_54_port, Y(5) =>
WC_53_port, Y(4) => WC_52_port, Y(3) => WC_51_port,
Y(2) => WC_50_port, Y(1) => WC_49_port, Y(0) =>
WC_48_port);
I_CSA2 : csa32LSBs_n47 port map( A(47) => MXLA_47_port, A(46) =>
MXLA_46_port, A(45) => MXLA_45_port, A(44) =>
MXLA_44_port, A(43) => MXLA_43_port, A(42) =>
MXLA_42_port, A(41) => MXLA_41_port, A(40) =>
MXLA_40_port, A(39) => MXLA_39_port, A(38) =>
MXLA_38_port, A(37) => MXLA_37_port, A(36) =>
MXLA_36_port, A(35) => MXLA_35_port, A(34) =>
MXLA_34_port, A(33) => MXLA_33_port, A(32) =>
MXLA_32_port, A(31) => MXLA_31_port, A(30) =>
MXLA_30_port, A(29) => MXLA_29_port, A(28) =>
MXLA_28_port, A(27) => MXLA_27_port, A(26) =>
MXLA_26_port, A(25) => MXLA_25_port, A(24) =>
MXLA_24_port, A(23) => MXLA_23_port, A(22) =>
MXLA_22_port, A(21) => MXLA_21_port, A(20) =>
MXLA_20_port, A(19) => MXLA_19_port, A(18) =>
MXLA_18_port, A(17) => MXLA_17_port, A(16) =>
MXLA_16_port, A(15) => MXLA_15_port, A(14) =>
MXLA_14_port, A(13) => MXLA_13_port, A(12) =>
MXLA_12_port, A(11) => MXLA_11_port, A(10) =>
MXLA_10_port, A(9) => MXLA_9_port, A(8) =>
MXLA_8_port, A(7) => MXLA_7_port, A(6) =>
MXLA_6_port, A(5) => MXLA_5_port, A(4) =>
MXLA_4_port, A(3) => MXLA_3_port, A(2) =>
MXLA_2_port, A(1) => MXLA_1_port, A(0) =>
MXLA_0_port, B(47) => W2_45_port, B(46) =>
W2_44_port, B(45) => W2_43_port, B(44) => W2_42_port
, B(43) => W2_41_port, B(42) => W2_40_port, B(41) =>
W2_39_port, B(40) => W2_38_port, B(39) => W2_37_port
, B(38) => W2_36_port, B(37) => W2_35_port, B(36) =>
W2_34_port, B(35) => W2_33_port, B(34) => W2_32_port
, B(33) => W2_31_port, B(32) => W2_30_port, B(31) =>
W2_29_port, B(30) => W2_28_port, B(29) => W2_27_port
, B(28) => W2_26_port, B(27) => W2_25_port, B(26) =>
W2_24_port, B(25) => W2_23_port, B(24) => W2_22_port
, B(23) => W2_21_port, B(22) => W2_20_port, B(21) =>
W2_19_port, B(20) => W2_18_port, B(19) => W2_17_port
, B(18) => W2_16_port, B(17) => W2_15_port, B(16) =>
W2_14_port, B(15) => W2_13_port, B(14) => W2_12_port
, B(13) => W2_11_port, B(12) => W2_10_port, B(11) =>
W2_9_port, B(10) => W2_8_port, B(9) => W2_7_port,
B(8) => W2_6_port, B(7) => W2_5_port, B(6) =>
W2_4_port, B(5) => W2_3_port, B(4) => W2_2_port,
B(3) => W2_1_port, B(2) => W2_0_port, B(1) => GND,
B(0) => GND, C(47) => qjD_47_port, C(46) =>
qjD_46_port, C(45) => qjD_45_port, C(44) =>
qjD_44_port, C(43) => qjD_43_port, C(42) =>
qjD_42_port, C(41) => qjD_41_port, C(40) =>
qjD_40_port, C(39) => qjD_39_port, C(38) =>
qjD_38_port, C(37) => qjD_37_port, C(36) =>
qjD_36_port, C(35) => qjD_35_port, C(34) =>
qjD_34_port, C(33) => qjD_33_port, C(32) =>
qjD_32_port, C(31) => qjD_31_port, C(30) =>
qjD_30_port, C(29) => qjD_29_port, C(28) =>
qjD_28_port, C(27) => qjD_27_port, C(26) =>
qjD_26_port, C(25) => qjD_25_port, C(24) =>
qjD_24_port, C(23) => qjD_23_port, C(22) =>
qjD_22_port, C(21) => qjD_21_port, C(20) =>
qjD_20_port, C(19) => qjD_19_port, C(18) =>
qjD_18_port, C(17) => qjD_17_port, C(16) =>
qjD_16_port, C(15) => qjD_15_port, C(14) =>
qjD_14_port, C(13) => qjD_13_port, C(12) =>
qjD_12_port, C(11) => qjD_11_port, C(10) =>
qjD_10_port, C(9) => qjD_9_port, C(8) => qjD_8_port,
C(7) => qjD_7_port, C(6) => qjD_6_port, C(5) =>
qjD_5_port, C(4) => qjD_4_port, C(3) => qjD_3_port,
C(2) => qjD_2_port, C(1) => qjD_1_port, C(0) =>
qjD_0_port, Cin => qjD_c2, Cout => carry_ex, Z(47)
=> WS_47_port, Z(46) => WS_46_port, Z(45) =>
WS_45_port, Z(44) => WS_44_port, Z(43) => WS_43_port
, Z(42) => WS_42_port, Z(41) => WS_41_port, Z(40) =>
WS_40_port, Z(39) => WS_39_port, Z(38) => WS_38_port
, Z(37) => WS_37_port, Z(36) => WS_36_port, Z(35) =>
WS_35_port, Z(34) => WS_34_port, Z(33) => WS_33_port
, Z(32) => WS_32_port, Z(31) => WS_31_port, Z(30) =>
WS_30_port, Z(29) => WS_29_port, Z(28) => WS_28_port
, Z(27) => WS_27_port, Z(26) => WS_26_port, Z(25) =>
WS_25_port, Z(24) => WS_24_port, Z(23) => WS_23_port
, Z(22) => WS_22_port, Z(21) => WS_21_port, Z(20) =>
WS_20_port, Z(19) => WS_19_port, Z(18) => WS_18_port
, Z(17) => WS_17_port, Z(16) => WS_16_port, Z(15) =>
WS_15_port, Z(14) => WS_14_port, Z(13) => WS_13_port
, Z(12) => WS_12_port, Z(11) => WS_11_port, Z(10) =>
WS_10_port, Z(9) => WS_9_port, Z(8) => WS_8_port,
Z(7) => WS_7_port, Z(6) => WS_6_port, Z(5) =>
WS_5_port, Z(4) => WS_4_port, Z(3) => WS_3_port,
Z(2) => WS_2_port, Z(1) => WS_1_port, Z(0) =>
WS_0_port, Y(47) => WC_47_port, Y(46) => WC_46_port,
Y(45) => WC_45_port, Y(44) => WC_44_port, Y(43) =>
WC_43_port, Y(42) => WC_42_port, Y(41) => WC_41_port
, Y(40) => WC_40_port, Y(39) => WC_39_port, Y(38) =>
WC_38_port, Y(37) => WC_37_port, Y(36) => WC_36_port
, Y(35) => WC_35_port, Y(34) => WC_34_port, Y(33) =>
WC_33_port, Y(32) => WC_32_port, Y(31) => WC_31_port
, Y(30) => WC_30_port, Y(29) => WC_29_port, Y(28) =>
WC_28_port, Y(27) => WC_27_port, Y(26) => WC_26_port
, Y(25) => WC_25_port, Y(24) => WC_24_port, Y(23) =>
WC_23_port, Y(22) => WC_22_port, Y(21) => WC_21_port
, Y(20) => WC_20_port, Y(19) => WC_19_port, Y(18) =>
WC_18_port, Y(17) => WC_17_port, Y(16) => WC_16_port
, Y(15) => WC_15_port, Y(14) => WC_14_port, Y(13) =>
WC_13_port, Y(12) => WC_12_port, Y(11) => WC_11_port
, Y(10) => WC_10_port, Y(9) => WC_9_port, Y(8) =>
WC_8_port, Y(7) => WC_7_port, Y(6) => WC_6_port,
Y(5) => WC_5_port, Y(4) => WC_4_port, Y(3) =>
WC_3_port, Y(2) => WC_2_port, Y(1) => WC_1_port,
Y(0) => WC_0_port);
I_REG1 : gl_dualreg_ld_n10 port map( AS(10) => WS_56_port, AS(9) =>
WS_55_port, AS(8) => WS_54_port, AS(7) => WS_53_port
, AS(6) => WS_52_port, AS(5) => WS_51_port, AS(4) =>
WS_50_port, AS(3) => WS_49_port, AS(2) => WS_48_port
, AS(1) => WS_47_port, AS(0) => WS_46_port, AC(10)
=> WC_56_port, AC(9) => WC_55_port, AC(8) =>
WC_54_port, AC(7) => WC_53_port, AC(6) => WC_52_port
, AC(5) => WC_51_port, AC(4) => WC_50_port, AC(3) =>
WC_49_port, AC(2) => WC_48_port, AC(1) => WC_47_port
, AC(0) => WC_46_port, RESET => CLR, CLOCK => CLOCK,
LOAD => LOAD, ZS(10) => W1_56_port, ZS(9) =>
W1_55_port, ZS(8) => W1_54_port, ZS(7) => W1_53_port
, ZS(6) => W1_52_port, ZS(5) => W1_51_port, ZS(4) =>
W1_50_port, ZS(3) => W1_49_port, ZS(2) => W1_48_port
, ZS(1) => W1_47_port, ZS(0) => W1_46_port, ZC(10)
=> W2_56_port, ZC(9) => W2_55_port, ZC(8) =>
W2_54_port, ZC(7) => W2_53_port, ZC(6) => W2_52_port
, ZC(5) => W2_51_port, ZC(4) => W2_50_port, ZC(3) =>
W2_49_port, ZC(2) => W2_48_port, ZC(1) => W2_47_port
, ZC(0) => W2_46_port);
I_REG2 : gl_dualreg_ld_n45 port map( AS(45) => WS_45_port, AS(44) =>
WS_44_port, AS(43) => WS_43_port, AS(42) =>
WS_42_port, AS(41) => WS_41_port, AS(40) =>
WS_40_port, AS(39) => WS_39_port, AS(38) =>
WS_38_port, AS(37) => WS_37_port, AS(36) =>
WS_36_port, AS(35) => WS_35_port, AS(34) =>
WS_34_port, AS(33) => WS_33_port, AS(32) =>
WS_32_port, AS(31) => WS_31_port, AS(30) =>
WS_30_port, AS(29) => WS_29_port, AS(28) =>
WS_28_port, AS(27) => WS_27_port, AS(26) =>
WS_26_port, AS(25) => WS_25_port, AS(24) =>
WS_24_port, AS(23) => WS_23_port, AS(22) =>
WS_22_port, AS(21) => WS_21_port, AS(20) =>
WS_20_port, AS(19) => WS_19_port, AS(18) =>
WS_18_port, AS(17) => WS_17_port, AS(16) =>
WS_16_port, AS(15) => WS_15_port, AS(14) =>
WS_14_port, AS(13) => WS_13_port, AS(12) =>
WS_12_port, AS(11) => WS_11_port, AS(10) =>
WS_10_port, AS(9) => WS_9_port, AS(8) => WS_8_port,
AS(7) => WS_7_port, AS(6) => WS_6_port, AS(5) =>
WS_5_port, AS(4) => WS_4_port, AS(3) => WS_3_port,
AS(2) => WS_2_port, AS(1) => WS_1_port, AS(0) =>
WS_0_port, AC(45) => WC_45_port, AC(44) =>
WC_44_port, AC(43) => WC_43_port, AC(42) =>
WC_42_port, AC(41) => WC_41_port, AC(40) =>
WC_40_port, AC(39) => WC_39_port, AC(38) =>
WC_38_port, AC(37) => WC_37_port, AC(36) =>
WC_36_port, AC(35) => WC_35_port, AC(34) =>
WC_34_port, AC(33) => WC_33_port, AC(32) =>
WC_32_port, AC(31) => WC_31_port, AC(30) =>
WC_30_port, AC(29) => WC_29_port, AC(28) =>
WC_28_port, AC(27) => WC_27_port, AC(26) =>
WC_26_port, AC(25) => WC_25_port, AC(24) =>
WC_24_port, AC(23) => WC_23_port, AC(22) =>
WC_22_port, AC(21) => WC_21_port, AC(20) =>
WC_20_port, AC(19) => WC_19_port, AC(18) =>
WC_18_port, AC(17) => WC_17_port, AC(16) =>
WC_16_port, AC(15) => WC_15_port, AC(14) =>
WC_14_port, AC(13) => WC_13_port, AC(12) =>
WC_12_port, AC(11) => WC_11_port, AC(10) =>
WC_10_port, AC(9) => WC_9_port, AC(8) => WC_8_port,
AC(7) => WC_7_port, AC(6) => WC_6_port, AC(5) =>
WC_5_port, AC(4) => WC_4_port, AC(3) => WC_3_port,
AC(2) => WC_2_port, AC(1) => WC_1_port, AC(0) =>
WC_0_port, RESET => CLR, CLOCK => CLOCK, LOAD =>
LOAD, ZS(45) => W1_45_port, ZS(44) => W1_44_port,
ZS(43) => W1_43_port, ZS(42) => W1_42_port, ZS(41)
=> W1_41_port, ZS(40) => W1_40_port, ZS(39) =>
W1_39_port, ZS(38) => W1_38_port, ZS(37) =>
W1_37_port, ZS(36) => W1_36_port, ZS(35) =>
W1_35_port, ZS(34) => W1_34_port, ZS(33) =>
W1_33_port, ZS(32) => W1_32_port, ZS(31) =>
W1_31_port, ZS(30) => W1_30_port, ZS(29) =>
W1_29_port, ZS(28) => W1_28_port, ZS(27) =>
W1_27_port, ZS(26) => W1_26_port, ZS(25) =>
W1_25_port, ZS(24) => W1_24_port, ZS(23) =>
W1_23_port, ZS(22) => W1_22_port, ZS(21) =>
W1_21_port, ZS(20) => W1_20_port, ZS(19) =>
W1_19_port, ZS(18) => W1_18_port, ZS(17) =>
W1_17_port, ZS(16) => W1_16_port, ZS(15) =>
W1_15_port, ZS(14) => W1_14_port, ZS(13) =>
W1_13_port, ZS(12) => W1_12_port, ZS(11) =>
W1_11_port, ZS(10) => W1_10_port, ZS(9) => W1_9_port
, ZS(8) => W1_8_port, ZS(7) => W1_7_port, ZS(6) =>
W1_6_port, ZS(5) => W1_5_port, ZS(4) => W1_4_port,
ZS(3) => W1_3_port, ZS(2) => W1_2_port, ZS(1) =>
W1_1_port, ZS(0) => W1_0_port, ZC(45) => W2_45_port,
ZC(44) => W2_44_port, ZC(43) => W2_43_port, ZC(42)
=> W2_42_port, ZC(41) => W2_41_port, ZC(40) =>
W2_40_port, ZC(39) => W2_39_port, ZC(38) =>
W2_38_port, ZC(37) => W2_37_port, ZC(36) =>
W2_36_port, ZC(35) => W2_35_port, ZC(34) =>
W2_34_port, ZC(33) => W2_33_port, ZC(32) =>
W2_32_port, ZC(31) => W2_31_port, ZC(30) =>
W2_30_port, ZC(29) => W2_29_port, ZC(28) =>
W2_28_port, ZC(27) => W2_27_port, ZC(26) =>
W2_26_port, ZC(25) => W2_25_port, ZC(24) =>
W2_24_port, ZC(23) => W2_23_port, ZC(22) =>
W2_22_port, ZC(21) => W2_21_port, ZC(20) =>
W2_20_port, ZC(19) => W2_19_port, ZC(18) =>
W2_18_port, ZC(17) => W2_17_port, ZC(16) =>
W2_16_port, ZC(15) => W2_15_port, ZC(14) =>
W2_14_port, ZC(13) => W2_13_port, ZC(12) =>
W2_12_port, ZC(11) => W2_11_port, ZC(10) =>
W2_10_port, ZC(9) => W2_9_port, ZC(8) => W2_8_port,
ZC(7) => W2_7_port, ZC(6) => W2_6_port, ZC(5) =>
W2_5_port, ZC(4) => W2_4_port, ZC(3) => W2_3_port,
ZC(2) => W2_2_port, ZC(1) => W2_1_port, ZC(0) =>
W2_0_port);
I_SEL : QDSEL port map( A1(6) => W1_56_port, A1(5) => W1_55_port, A1(4) =>
W1_54_port, A1(3) => W1_53_port, A1(2) => W1_52_port
, A1(1) => W1_51_port, A1(0) => W1_50_port, A2(6) =>
W2_56_port, A2(5) => W2_55_port, A2(4) => W2_54_port
, A2(3) => W2_53_port, A2(2) => W2_52_port, A2(1) =>
W2_51_port, A2(0) => W2_50_port, D(2) => D(51), D(1)
=> D(50), D(0) => D(49), M1 => Qj_2_port, M2 => n112
, P1 => n113, P2 => n114);
U4 : IVSVTX8 port map( A => n111, Z => Qj_3_port);
U5 : IVSVTX4 port map( A => n112, Z => n111);
U6 : IVSVTX12 port map( A => n109, Z => Qj_1_port);
U7 : BFHVTX1 port map( A => W2_51_port, Z => n104);
U8 : IVHVTX0H port map( A => W2_50_port, Z => n105);
U9 : IVSVTX0H port map( A => n105, Z => n106);
U10 : IVSVTX4 port map( A => n113, Z => n109);
U11 : BFSVTX12 port map( A => n114, Z => Qj_0_port);
end SYN_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/divr4_rec_0.9ns.vhd | VHDL | lgpl | 155,432 |
library IEEE;
use IEEE.std_logic_1164.all;
entity csa32LSBs is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end csa32LSBs;
architecture BEHAVIORAL of csa32LSBs is
begin
process(A, B, C, Cin)
variable p : std_logic_vector (n downto 0) ;
variable g : std_logic_vector (n downto 0) ;
variable i : integer;
begin
for i in 0 to n loop
p(i) := A(i) XOR B(i) ;
g(i) := A(i) AND B(i) ;
end loop;
-- CARRY -----------------------------------
Y(0) <= Cin;
for i in 0 to n-1 loop
Y(i+1) <= g(i) OR (c(i) AND p(i));
end loop;
Cout <= g(n) OR (c(n) AND p(n));
-- SUM -------------------------------------
for i in 0 to n loop
Z(i) <= p(i) XOR c(i);
end loop;
end process;
end BEHAVIORAL;
configuration CFG_csa32LSBs_BEHAVIORAL of csa32LSBs is
for BEHAVIORAL
end for;
end CFG_csa32LSBs_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/csa32LSBs.vhd | VHDL | lgpl | 1,041 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_csa32 is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end gl_csa32;
architecture BEHAVIORAL of gl_csa32 is
begin
process(A, B, C, Cin)
variable p : std_logic_vector (n downto 0) ;
variable g : std_logic_vector (n downto 0) ;
variable i : integer;
begin
for i in 0 to n loop
p(i) := A(i) XOR B(i) ;
g(i) := A(i) AND B(i) ;
end loop;
-- CARRY -----------------------------------
Y(0) <= Cin;
for i in 0 to n-1 loop
Y(i+1) <= g(i) OR (c(i) AND p(i));
end loop;
-- SUM -------------------------------------
for i in 0 to n loop
Z(i) <= p(i) XOR c(i);
end loop;
end process;
end BEHAVIORAL;
configuration CFG_gl_csa32_BEHAVIORAL of gl_csa32 is
for BEHAVIORAL
end for;
end CFG_gl_csa32_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/gl_csa32.vhd | VHDL | lgpl | 977 |
-- VHDL Model Created from SGE Symbol qds_adder.sym -- Apr 21 16:44:47 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_ADDER is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
Y : Out std_logic_vector (6 downto 0) );
end QDS_ADDER;
architecture BEHAVIORAL of QDS_ADDER is
begin
process(A1, A2)
variable g0,p0 : std_logic_vector (1 downto 0) ;
variable g1,p1 : std_logic_vector (1 downto 0) ;
variable g2,p2 : std_logic_vector (1 downto 0) ;
variable g3,p3 : std_logic;
variable c : std_logic_vector (4 downto 0) ;
variable cc : std_logic_vector (1 downto 0) ;
variable i,j,k,l : integer;
begin
cc(0) := '0';
----------------------------------- 1st level -----------------------
j := 0 ;
g0(0) := A1(0+j) AND A2(0+j); p0(0) := A1(0+j) OR A2(0+j);
g1(0) := A1(1+j) AND A2(1+j); p1(0) := A1(1+j) OR A2(1+j);
g2(0) := A1(2+j) AND A2(2+j); p2(0) := A1(2+j) OR A2(2+j);
g3 := A1(3+j) AND A2(3+j); p3 := A1(3+j) OR A2(3+j);
j := 4 ;
g0(1) := A1(0+j) AND A2(0+j); p0(1) := A1(0+j) OR A2(0+j);
g1(1) := A1(1+j) AND A2(1+j); p1(1) := A1(1+j) OR A2(1+j);
g2(1) := A1(2+j) AND A2(2+j); p2(1) := A1(2+j) OR A2(2+j);
----------------------------------- 2nd level -----------------------
k := 0;
cc(1) := g3 OR (g2(k) AND p3 ) OR (g1(k) AND p2(k) AND p3 )
OR (g0(k) AND p1(k) AND p2(k) AND p3 ) ;
-- CARRY -------------------------- 1st level -----------------------
k := 0;
c(0) := cc(k);
c(1) := g0(k) OR (c(0) AND p0(k));
c(2) := g1(k) OR (g0(k) AND p1(k)) OR (c(0) AND p0(k) AND p1(k));
c(3) := g2(k) OR (g1(k) AND p2(k)) OR (g0(k) AND p1(k) AND p2(k))
OR (c(0) AND p0(k) AND p1(k) AND p2(k));
j := k*4 ;
for i in 0 to 3 loop
Y(i+j) <= A1(i+j) XOR A2(i+j) XOR c(i) ;
end loop;
k := 1;
c(0) := cc(k);
c(1) := g0(k) OR (c(0) AND p0(k));
c(2) := g1(k) OR (g0(k) AND p1(k)) OR (c(0) AND p0(k) AND p1(k));
j := k*4 ;
for i in 0 to 2 loop
Y(i+j) <= A1(i+j) XOR A2(i+j) XOR c(i) ;
end loop;
end process;
end BEHAVIORAL;
configuration CFG_QDS_ADDER_BEHAVIORAL of QDS_ADDER is
for BEHAVIORAL
end for;
end CFG_QDS_ADDER_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/qds_adder.vhd | VHDL | lgpl | 2,330 |
-- VHDL Model Created from SGE Symbol mux.sym -- May 27 12:33:10 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MUX is
Port ( A : In std_logic_vector (56 downto 0);
B : In std_logic_vector (56 downto 0);
SEL : In std_logic;
Z : Out std_logic_vector (56 downto 0) );
end MUX;
architecture BEHAVIORAL of MUX is
begin
process (A, B, SEL)
begin
if ( SEL = '1' ) then
Z <= A ;
else
Z <= B ;
end if;
end process;
end BEHAVIORAL;
configuration CFG_MUX_BEHAVIORAL of MUX is
for BEHAVIORAL
end for;
end CFG_MUX_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/mux.vhd | VHDL | lgpl | 762 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut.saif
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_noretiming/cmd_saif.inc | PHP | lgpl | 102 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_signed.all;
entity E is
end E;
architecture A of E is
signal CLOCK : std_logic;
signal D : std_logic_vector (52 downto 0);
signal RESET : std_logic;
signal X : std_logic_vector (53 downto 0);
signal Qj : std_logic_vector (3 downto 0);
component divr4_rec
Port ( CLOCK : In std_logic;
D : In std_logic_vector (52 downto 0);
RESET : In std_logic;
X : In std_logic_vector (53 downto 0);
Qj : Out std_logic_vector (3 downto 0) );
end component;
begin
UUT : divr4_rec
Port Map ( CLOCK, D, RESET, X, Qj );
TB : block
begin
process
-- CONSTANT NLOOPS : integer := 15;
CONSTANT NLOOPS : integer := 30;
file cmdfile: TEXT; -- Define the file 'handle'
variable line_in,line_out: Line; -- Line buffers
variable good: boolean; -- Status of the read operations
variable A,B: std_logic_vector(55 downto 0);
variable S: std_logic_vector(55 downto 0);
variable Z: std_logic_vector(55 downto 0);
variable ERR: std_logic_vector(55 downto 0);
variable c : integer;
begin
c := 1;
FILE_OPEN(cmdfile,"testvecs1.in",READ_MODE);
-- -------------------------------------------------------------------------
loop
if endfile(cmdfile) then -- Check EOF
assert false
report "End of file encountered; exiting."
severity NOTE;
exit;
end if;
reset <= '0';
clock <= '1'; wait for 5 ns;
reset <= '1';
clock <= '0'; wait for 5 ns;
readline(cmdfile,line_in); -- Read a line from the file
next when line_in'length = 0; -- Skip empty lines
hread(line_in,A,good); -- Read the X argument as hex value
assert good report "Text I/O read error" severity ERROR;
hread(line_in,B,good); -- Read the D argument as hex value
assert good report "Text I/O read error" severity ERROR;
hread(line_in,S,good); -- Read the Q argument as hex value
assert good report "Text I/O read error" severity ERROR;
D(52 downto 0) <= B(52 downto 0);
X(53 downto 1) <= A(52 downto 0); X(0)<= '0';
for i in 0 to NLOOPS loop
clock <= '1'; wait for 5 ns;
clock <= '0'; wait for 5 ns;
end loop;
write(line_out, string'("Test "));
write(line_out,c);
write(line_out, string'(": "));
hwrite(line_out,A,RIGHT,14);
write(line_out, string'(" / "));
hwrite(line_out,B,RIGHT,14);
writeline(OUTPUT,line_out); -- write the message
c := c + 1;
end loop;
write(line_out, string'("--------- END SIMULATION ------------------"));
writeline(OUTPUT,line_out);
-- -------------------------------------------------------------------------
-- ===============================================================
clock <= '1'; wait for 1000 ns;
assert qj = "1111"
report "--------- END SIMULATION ------------------ " severity error;
-- ===============================================================
end process;
end block;
end A;
configuration CFG_TB_divr4_rec_BEHAVIORAL of E is
for A
for UUT : divr4_rec
use configuration WORK.CFG_divr4_rec_SCHEMATIC;
end for;
for TB
end for;
end for;
end CFG_TB_divr4_rec_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/tb_divr4_rec.vhd | VHDL | lgpl | 3,368 |
-- VHDL Model Created from SGE Symbol qds_table.sym -- Apr 21 16:34:54 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_TABLE is
Port ( D : In std_logic_vector (2 downto 0);
Y : In std_logic_vector (6 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end QDS_TABLE;
architecture BEHAVIORAL of QDS_TABLE is
begin
process(Y, D)
TYPE table_type IS ARRAY(0 to 3) OF std_logic_vector (6 downto 0);
CONSTANT sel_fun0 : table_type := (
"0001100", "0000100", "1111100", "1110011" );
CONSTANT sel_fun1 : table_type := (
"0001110", "0000100", "1111010", "1110001" );
CONSTANT sel_fun2 : table_type := (
"0001111", "0000100", "1111010", "1110000" );
CONSTANT sel_fun3 : table_type := (
"0010000", "0000100", "1111010", "1101110" );
CONSTANT sel_fun4 : table_type := (
"0010010", "0000110", "1111000", "1101100" );
CONSTANT sel_fun5 : table_type := (
"0010100", "0000110", "1111000", "1101100" );
CONSTANT sel_fun6 : table_type := (
"0010100", "0001000", "1111000", "1101010" );
CONSTANT sel_fun7 : table_type := (
"0011000", "0001000", "1111000", "1101000" );
begin
-- Selection function
if ( D = "000" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun0(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun0(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun0(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun0(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "001" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun1(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun1(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun1(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun1(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "010" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun2(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun2(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun2(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun2(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "011" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun3(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun3(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun3(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun3(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "100" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun4(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun4(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun4(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun4(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "101" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun5(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun5(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun5(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun5(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "110" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun6(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun6(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun6(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun6(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
elsif ( D = "111" ) then
if ( y(6) = '0' ) then ------- y is positive
if ( y >= sel_fun7(0) ) then
M2 <= '1'; M1 <= '0'; P1 <= '0'; P2 <= '0';
elsif ( y < sel_fun7(1) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '1'; P1 <= '0'; P2 <= '0';
end if;
else ------- y is negative
if ( y < sel_fun7(3) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '1';
elsif ( y >= sel_fun7(2) ) then
M2 <= '0'; M1 <= '0'; P1 <= '0'; P2 <= '0';
else
M2 <= '0'; M1 <= '0'; P1 <= '1'; P2 <= '0';
end if;
end if;
end if;
end process;
end BEHAVIORAL;
configuration CFG_QDS_TABLE_BEHAVIORAL of QDS_TABLE is
for BEHAVIORAL
end for;
end CFG_QDS_TABLE_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/qds_table.vhd | VHDL | lgpl | 6,548 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_dualreg_ld is
GENERIC(n : integer);
Port ( AS : In std_logic_vector (n downto 0);
RESET : In std_logic;
CLOCK : In std_logic;
LOAD : In std_logic;
ZS : Out std_logic_vector (n downto 0) );
end gl_dualreg_ld;
architecture BEHAVIORAL of gl_dualreg_ld is
begin
process(reset,clock)
begin
if ( reset = '0' ) then
ZS <= (others => '0');
elsif (( clock = '1' ) and (clock'EVENT)) then
if ( load = '1' ) then
ZS <= AS ;
end if;
end if;
end process;
end BEHAVIORAL;
configuration CFG_gl_dualreg_ld_BEHAVIORAL of gl_dualreg_ld is
for BEHAVIORAL
end for;
end CFG_gl_dualreg_ld_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/gl_dualreg_ld.vhd | VHDL | lgpl | 835 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity divr4_rec is
Port ( CLOCK : In std_logic;
D : In std_logic_vector (52 downto 0);
RESET : In std_logic;
X : In std_logic_vector (53 downto 0);
Qj : Out std_logic_vector (3 downto 0) );
end divr4_rec;
architecture SCHEMATIC of divr4_rec is
signal Y1 : std_logic_vector(6 downto 0);
signal Y2 : std_logic_vector(6 downto 0);
signal D3 : std_logic_vector(2 downto 0);
signal DD : std_logic_vector(54 downto 0);
signal XX : std_logic_vector(56 downto 0);
signal W2 : std_logic_vector(56 downto 0);
signal W1 : std_logic_vector(56 downto 0);
signal SW2 : std_logic_vector(56 downto 0);
signal SW1 : std_logic_vector(56 downto 0);
signal WC : std_logic_vector(56 downto 0);
signal WS : std_logic_vector(56 downto 0);
signal MXLA : std_logic_vector(56 downto 0);
signal MXLB : std_logic_vector(56 downto 0);
signal qjD : std_logic_vector(56 downto 0);
signal QLa : std_logic_vector(3 downto 0);
signal QL : std_logic_vector(3 downto 0);
signal M2, M1, P1, P2 : std_logic;
signal DIGIT, ROUND : std_logic;
signal muxW : std_logic;
signal CLR : std_logic;
signal LOAD : std_logic;
signal SIGN : std_logic;
signal qjD_c2 : std_logic;
signal GND : std_logic;
signal carry_ex : std_logic;
component CONTROL
Port ( CLOCK : In std_logic;
RESET : In std_logic;
CL1 : Out std_logic;
DIGIT : Out std_logic;
LD1 : Out std_logic;
MX1 : Out std_logic;
ROUND : Out std_logic );
end component;
component MUX
Port ( A : In std_logic_vector (56 downto 0);
B : In std_logic_vector (56 downto 0);
SEL : In std_logic;
Z : Out std_logic_vector (56 downto 0) );
end component;
component WLATCH
Port ( A1 : In std_logic_vector (56 downto 0);
A2 : In std_logic_vector (56 downto 0);
CLEAR : In std_logic;
CLK : In std_logic;
LOAD : In std_logic;
RWC : Out std_logic_vector (56 downto 0);
RWS : Out std_logic_vector (56 downto 0) );
end component;
component gl_csa32
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end component;
component csa32LSBs
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end component;
component gl_dualreg_ld
GENERIC(n : integer);
Port ( AS : In std_logic_vector (n downto 0);
RESET : In std_logic;
CLOCK : In std_logic;
LOAD : In std_logic;
ZS : Out std_logic_vector (n downto 0)
);
end component;
component QDSEL
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
D : In std_logic_vector (2 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end component;
component MULT
Port ( A : In std_logic_vector (54 downto 0);
M1 : In std_logic;
M2 : In std_logic;
P1 : In std_logic;
P2 : In std_logic;
COUT : Out std_logic;
Z : Out std_logic_vector (56 downto 0) );
end component;
begin
GND <= '0';
-- divisor alignment
DD(54)<='0' ; DD(53 downto 1)<=D(52 downto 0); DD(0)<='0' ;
-- dividend alignment
XX(56)<='0'; XX(55)<='0'; XX(54)<='0'; XX(53 downto 0)<=X(53 downto 0);
-- bits of d and y going into SEL
D3(2 downto 0)<=D(51 downto 49);
Y1(6 downto 0)<=WS(56 downto 50);
Y2(6 downto 0)<=WC(56 downto 50);
I_CTRL : CONTROL
Port Map ( CLOCK=>CLOCK, RESET=>RESET, CL1=>CLR, DIGIT=>DIGIT,
LD1=>LOAD, MX1=>muxW, ROUND=>ROUND );
-- shift 2 left
SW1(56 downto 2)<=W1(54 downto 0) ; SW1(1)<='0'; SW1(0)<='0';
SW2(56 downto 2)<=W2(54 downto 0) ; SW2(1)<='0'; SW2(0)<='0';
-- MUX selecting either X (initialization) or Ws
I_MUX : MUX
Port Map ( A(56 downto 0)=>XX(56 downto 0),
B(56 downto 0)=>SW1(56 downto 0), SEL=>muxW,
Z(56 downto 0)=>MXLA(56 downto 0) );
-- mux 4:1 acting as multiplier q_j*d
I_MULT : MULT
Port Map ( A(54 downto 0)=>DD(54 downto 0),
M1=>QLa(2), M2=>QLa(3), P1=>QLa(1), P2=>QLa(0), COUT=>qjD_c2,
Z(56 downto 0)=>qjD(56 downto 0) );
-- CSA 3:2 is split into two slices
I_CSA1 : gl_csa32 Generic Map(n=>8)
Port Map ( A=>MXLA(56 downto 48),
B=>SW2(56 downto 48), CIN=>carry_ex,
C=>qjD(56 downto 48),
Y=>WC(56 downto 48),
Z=>WS(56 downto 48) );
I_CSA2 : csa32LSBs Generic Map(n=>47)
Port Map ( A=>MXLA(47 downto 0),
B=>SW2(47 downto 0), CIN=>qjD_c2,
C=>qjD(47 downto 0), Cout=>carry_ex,
Y=>WC(47 downto 0),
Z=>WS(47 downto 0) );
-- REG Ws and Wc are split into two slices
I_REG1 : gl_dualreg_ld Generic Map(n=>56)
Port Map ( AS=>WS(56 downto 0),
RESET=>CLR, CLOCK=>CLOCK, LOAD=>LOAD,
ZS=>W1(56 downto 0) );
I_REG2 : gl_dualreg_ld Generic Map(n=>56)
Port Map ( AS=>WC(56 downto 0),
RESET=>CLR, CLOCK=>CLOCK, LOAD=>LOAD,
ZS=>W2(56 downto 0) );
-- SELECTION FUNCTION
I_SEL : QDSEL
Port Map ( A1(6 downto 0)=>Y1(6 downto 0), A2(6 downto 0)=>Y2(6 downto 0),
D(2 downto 0)=>D3(2 downto 0),
M1=>M1, M2=>M2, P1=>P1, P2=>P2 );
QL(3)<=M2;
QL(2)<=M1;
QL(1)<=P1;
QL(0)<=P2;
I_REG3 : gl_dualreg_ld Generic Map(n=>3)
Port Map ( AS=>QL(3 downto 0),
RESET=>CLR, CLOCK=>CLOCK, LOAD=>LOAD,
ZS=>QLa(3 downto 0) );
QJ(3)<=QLa(3);
QJ(2)<=QLa(2);
QJ(1)<=QLa(1);
QJ(0)<=QLa(0);
end SCHEMATIC;
configuration CFG_divr4_rec_SCHEMATIC of divr4_rec is
for SCHEMATIC
for I_CTRL: CONTROL
use configuration WORK.CFG_CONTROL_BEHAVIORAL;
end for;
for I_MUX: MUX
use configuration WORK.CFG_MUX_BEHAVIORAL;
end for;
for I_REG1, I_REG2, I_REG3 : gl_dualreg_ld
use configuration WORK.CFG_gl_dualreg_ld_BEHAVIORAL;
end for;
for I_CSA1: gl_csa32
use configuration WORK.CFG_GL_CSA32_BEHAVIORAL;
end for;
for I_CSA2: csa32LSBs
use configuration WORK.CFG_csa32LSBs_BEHAVIORAL;
end for;
for I_SEL: QDSEL
use configuration WORK.CFG_QDSEL_SCHEMATIC;
end for;
for I_MULT: MULT
use configuration WORK.CFG_MULT_BEHAVIORAL;
end for;
end for;
end CFG_divr4_rec_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/divr4_rec.vhd | VHDL | lgpl | 7,924 |
-- VHDL Model Created from SGE Symbol control.sym -- May 5 18:26:48 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity CONTROL is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
CL1 : Out std_logic;
DIGIT : Out std_logic;
LD1 : Out std_logic;
MX1 : Out std_logic;
ROUND : Out std_logic );
end CONTROL;
architecture BEHAVIORAL of CONTROL is
begin
process(reset,clock)
variable state : integer range 0 to 29;
begin
if ( reset = '0' ) then
CL1 <= '0';
LD1 <= '0';
DIGIT <= '0' ;
ROUND <= '1' ;
MX1 <= '1' ;
state := 0;
elsif ((clock'EVENT) AND ( clock = '1' )) then
if( 0 = state ) then
ROUND <= '0' ;
CL1 <= '1';
LD1 <= '1';
state := 1 ;
elsif( 1 = state ) then
DIGIT <= '1' ;
MX1 <= '0' ;
state := 2 ;
elsif( 29 = state ) then
DIGIT <= '0' ;
ROUND <= '1' ;
MX1 <= '1' ;
LD1 <= '0';
state := 0 ;
else
state := state + 1 ;
end if;
end if;
end process;
end BEHAVIORAL;
configuration CFG_CONTROL_BEHAVIORAL of CONTROL is
for BEHAVIORAL
end for;
end CFG_CONTROL_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/control.vhd | VHDL | lgpl | 1,523 |
-- VHDL Model Created from SGE Schematic qdsel.sch -- Apr 21 16:58:17 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDSEL is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
D : In std_logic_vector (2 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end QDSEL;
architecture SCHEMATIC of QDSEL is
signal Y : std_logic_vector(6 downto 0);
component QDS_TABLE
Port ( D : In std_logic_vector (2 downto 0);
Y : In std_logic_vector (6 downto 0);
M1 : Out std_logic;
M2 : Out std_logic;
P1 : Out std_logic;
P2 : Out std_logic );
end component;
component QDS_ADDER
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
Y : Out std_logic_vector (6 downto 0) );
end component;
begin
I_1 : QDS_TABLE
Port Map ( D(2 downto 0)=>D(2 downto 0),
Y(6 downto 0)=>Y(6 downto 0), M1=>M1, M2=>M2, P1=>P1,
P2=>P2 );
I_2 : QDS_ADDER
Port Map ( A1(6 downto 0)=>A1(6 downto 0),
A2(6 downto 0)=>A2(6 downto 0),
Y(6 downto 0)=>Y(6 downto 0) );
end SCHEMATIC;
configuration CFG_QDSEL_SCHEMATIC of QDSEL is
for SCHEMATIC
for I_1: QDS_TABLE
use configuration WORK.CFG_QDS_TABLE_BEHAVIORAL;
end for;
for I_2: QDS_ADDER
use configuration WORK.CFG_QDS_ADDER_BEHAVIORAL;
end for;
end for;
end CFG_QDSEL_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/qdsel.vhd | VHDL | lgpl | 1,846 |
open run.out
logtime -e run.out
monitor -n Smon active *E/X'sig
monitor -n Smon active *E/D'sig
--monitor -n Smon active *E/Qj'sig
-- monitor -n Smon active *E/UUT/WS'sig
-- monitor -n Smon active *E/UUT/WC'sig
list > run.out
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/cmd.inc | C++ | lgpl | 266 |
-- VHDL Model Created from SGE Symbol mult.sym -- May 27 12:32:12 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MULT is
Port ( A : In std_logic_vector (54 downto 0);
M1 : In std_logic;
M2 : In std_logic;
P1 : In std_logic;
P2 : In std_logic;
COUT : Out std_logic;
Z : Out std_logic_vector (56 downto 0) );
end MULT;
architecture BEHAVIORAL of MULT is
begin
process (M1, M2, P1, P2, A)
variable pd : std_logic;
begin
Z(0) <= M1 OR M2;
Z(1) <= M1 OR M2;
pd := '0';
for i in 0 to 53 loop
Z(i+2) <= ( M2 AND NOT(pd) ) OR ( M1 AND NOT(A(i)) ) OR
( P1 AND A(i) ) OR ( P2 AND pd ) ;
pd := A(i);
end loop;
Z(56) <= ( pd AND P2 ) OR ( NOT(pd) AND M2 ) OR M1;
cout <= M1 or M2 ;
end process;
end BEHAVIORAL;
configuration CFG_MULT_BEHAVIORAL of MULT is
for BEHAVIORAL
end for;
end CFG_MULT_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/mult.vhd | VHDL | lgpl | 1,093 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_divr4_rec is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_divr4_rec;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity CONTROL_DW01_inc_0 is
port( A : in std_logic_vector (4 downto 0); SUM : out std_logic_vector (4
downto 0));
end CONTROL_DW01_inc_0;
architecture SYN_rpl of CONTROL_DW01_inc_0 is
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component HA1SVTX8
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_4_port, carry_3_port, carry_2_port : std_logic;
begin
U5 : EOHVTX1 port map( A => carry_4_port, B => A(4), Z => SUM(4));
U6 : IVHVTX0H port map( A => A(0), Z => SUM(0));
U1_1_1 : HA1SVTX8 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1_1_2 : HA1SVTX8 port map( A => A(2), B => carry_2_port, CO => carry_3_port
, S => SUM(2));
U1_1_3 : HA1SVTX8 port map( A => A(3), B => carry_3_port, CO => carry_4_port
, S => SUM(3));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity CONTROL is
port( CLOCK, RESET : in std_logic; CL1, DIGIT, LD1, MX1, ROUND : out
std_logic);
end CONTROL;
architecture SYN_BEHAVIORAL of CONTROL is
component NR2AHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO6HVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND2AHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO17HVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO20NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component ENHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO6NHVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO7AHVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND4HVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component OR2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component AO2NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX2
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component FD4QSVTX1
port( CP, D : in std_logic; Q : out std_logic; SD : in std_logic);
end component;
component FD2QNSVTX1
port( CD, CP, D : in std_logic; QN : out std_logic);
end component;
component BFSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component CONTROL_DW01_inc_0
port( A : in std_logic_vector (4 downto 0); SUM : out std_logic_vector
(4 downto 0));
end component;
component FD4QNSVTX2
port( CP, D : in std_logic; QN : out std_logic; SD : in std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component EOSVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2BSVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR3SVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
signal n418, DIGIT_port, n419, ROUND_port, state_4_port, state_2_port,
state_1_port, state_0_port, ROUND135, state162_4_port, state162_3_port,
state162_2_port, state162_1_port, state162_0_port, sum366_4_port,
sum366_3_port, sum366_2_port, sum366_1_port, sum366_0_port, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, CL1_port, n420, MX1_port : std_logic;
begin
CL1 <= CL1_port;
DIGIT <= DIGIT_port;
MX1 <= MX1_port;
ROUND <= ROUND_port;
U157 : NR2AHVTX1 port map( A => sum366_4_port, B => n398, Z =>
state162_4_port);
U158 : NR2AHVTX1 port map( A => sum366_3_port, B => n398, Z =>
state162_3_port);
U159 : NR2AHVTX1 port map( A => sum366_2_port, B => n398, Z =>
state162_2_port);
U160 : AO6HVTX1 port map( A => n415, B => n399, C => n400, Z => n398);
U161 : ND2AHVTX1 port map( A => n401, B => n402, Z => state162_1_port);
U162 : AO17HVTX1 port map( A => n403, B => n415, C => n400, D =>
sum366_1_port, Z => n402);
U163 : AO20NHVTX1 port map( A => n400, B => n415, C => sum366_0_port, D =>
n404, Z => state162_0_port);
U164 : ND2HVTX1 port map( A => n405, B => n414, Z => n400);
U165 : ENHVTX1 port map( A => n403, B => n399, Z => n405);
U166 : AO6NHVTX1 port map( A => DIGIT_port, B => n406, C => n401, Z => n409)
;
U167 : AO7AHVTX1 port map( A => MX1_port, B => n401, C => n406, Z => n410);
U168 : NR2AHVTX1 port map( A => n407, B => n415, Z => n401);
U169 : AO7AHVTX1 port map( A => ROUND_port, B => n404, C => n406, Z => n411)
;
U170 : AO6NHVTX1 port map( A => n419, B => n406, C => n404, Z => n412);
U171 : ND4HVTX1 port map( A => n399, B => n403, C => n414, D => state_0_port
, Z => n406);
U172 : OR2HVTX1 port map( A => n404, B => CL1_port, Z => n413);
U174 : IVHVTX0H port map( A => n415, Z => state_0_port);
U176 : AO2NHVTX1 port map( A => state_2_port, B => ROUND135, C => n408, D =>
state_4_port, Z => n403);
U177 : IVHVTX0H port map( A => n414, Z => state_1_port);
U178 : EOHVTX1 port map( A => n408, B => state_4_port, Z => n399);
DIGIT_reg : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n409, Q =>
DIGIT_port);
ROUND_reg : FD4QSVTX1 port map( CP => CLOCK, D => n411, Q => ROUND_port, SD
=> RESET);
LD1_reg : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n412, Q => n419
);
CL1_reg : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n413, Q => n418
);
state_reg_4_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D =>
state162_4_port, Q => state_4_port);
state_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D =>
state162_3_port, Q => ROUND135);
state_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D =>
state162_2_port, Q => state_2_port);
state_reg_1_inst : FD2QNSVTX1 port map( CD => RESET, CP => CLOCK, D =>
state162_1_port, QN => n414);
state_reg_0_inst : FD2QNSVTX1 port map( CD => RESET, CP => CLOCK, D =>
state162_0_port, QN => n415);
U181 : BFSVTX8 port map( A => n418, Z => CL1_port);
add_54 : CONTROL_DW01_inc_0 port map( A(4) => state_4_port, A(3) => ROUND135
, A(2) => state_2_port, A(1) => state_1_port, A(0)
=> state_0_port, SUM(4) => sum366_4_port, SUM(3) =>
sum366_3_port, SUM(2) => sum366_2_port, SUM(1) =>
sum366_1_port, SUM(0) => sum366_0_port);
U182 : BFSVTX8 port map( A => n419, Z => LD1);
MX1_reg : FD4QNSVTX2 port map( CP => CLOCK, D => n410, QN => n420, SD =>
RESET);
U183 : IVSVTX6 port map( A => n420, Z => MX1_port);
U184 : EOSVTX1 port map( A => state_2_port, B => ROUND135, Z => n408);
U185 : AN2BSVTX1 port map( A => n407, B => state_0_port, Z => n404);
U186 : NR3SVTX1 port map( A => n399, B => state_1_port, C => n403, Z => n407
);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity MUX is
port( A, B : in std_logic_vector (56 downto 0); SEL : in std_logic; Z :
out std_logic_vector (56 downto 0));
end MUX;
architecture SYN_BEHAVIORAL of MUX is
component AO2NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
signal n5 : std_logic;
begin
U10 : AO2NHVTX1 port map( A => B(9), B => n5, C => SEL, D => A(9), Z => Z(9)
);
U11 : AO2NHVTX1 port map( A => B(8), B => n5, C => A(8), D => SEL, Z => Z(8)
);
U12 : AO2NHVTX1 port map( A => B(7), B => n5, C => A(7), D => SEL, Z => Z(7)
);
U13 : AO2NHVTX1 port map( A => B(6), B => n5, C => A(6), D => SEL, Z => Z(6)
);
U14 : AO2NHVTX1 port map( A => B(5), B => n5, C => A(5), D => SEL, Z => Z(5)
);
U15 : AO2NHVTX1 port map( A => B(56), B => n5, C => A(56), D => SEL, Z =>
Z(56));
U16 : AO2NHVTX1 port map( A => B(55), B => n5, C => A(55), D => SEL, Z =>
Z(55));
U17 : AO2NHVTX1 port map( A => B(54), B => n5, C => A(54), D => SEL, Z =>
Z(54));
U18 : AO2NHVTX1 port map( A => B(53), B => n5, C => A(53), D => SEL, Z =>
Z(53));
U19 : AO2NHVTX1 port map( A => B(52), B => n5, C => A(52), D => SEL, Z =>
Z(52));
U20 : AO2NHVTX1 port map( A => B(51), B => n5, C => A(51), D => SEL, Z =>
Z(51));
U21 : AO2NHVTX1 port map( A => B(50), B => n5, C => A(50), D => SEL, Z =>
Z(50));
U22 : AO2NHVTX1 port map( A => B(4), B => n5, C => A(4), D => SEL, Z => Z(4)
);
U23 : AO2NHVTX1 port map( A => B(49), B => n5, C => A(49), D => SEL, Z =>
Z(49));
U24 : AO2NHVTX1 port map( A => B(48), B => n5, C => A(48), D => SEL, Z =>
Z(48));
U25 : AO2NHVTX1 port map( A => B(47), B => n5, C => A(47), D => SEL, Z =>
Z(47));
U26 : AO2NHVTX1 port map( A => B(46), B => n5, C => A(46), D => SEL, Z =>
Z(46));
U27 : AO2NHVTX1 port map( A => B(45), B => n5, C => A(45), D => SEL, Z =>
Z(45));
U28 : AO2NHVTX1 port map( A => B(44), B => n5, C => A(44), D => SEL, Z =>
Z(44));
U29 : AO2NHVTX1 port map( A => B(43), B => n5, C => A(43), D => SEL, Z =>
Z(43));
U30 : AO2NHVTX1 port map( A => B(42), B => n5, C => A(42), D => SEL, Z =>
Z(42));
U31 : AO2NHVTX1 port map( A => B(41), B => n5, C => A(41), D => SEL, Z =>
Z(41));
U32 : AO2NHVTX1 port map( A => B(40), B => n5, C => A(40), D => SEL, Z =>
Z(40));
U33 : AO2NHVTX1 port map( A => B(3), B => n5, C => A(3), D => SEL, Z => Z(3)
);
U34 : AO2NHVTX1 port map( A => B(39), B => n5, C => A(39), D => SEL, Z =>
Z(39));
U35 : AO2NHVTX1 port map( A => B(38), B => n5, C => A(38), D => SEL, Z =>
Z(38));
U36 : AO2NHVTX1 port map( A => B(37), B => n5, C => A(37), D => SEL, Z =>
Z(37));
U37 : AO2NHVTX1 port map( A => B(36), B => n5, C => A(36), D => SEL, Z =>
Z(36));
U38 : AO2NHVTX1 port map( A => B(35), B => n5, C => A(35), D => SEL, Z =>
Z(35));
U39 : AO2NHVTX1 port map( A => B(34), B => n5, C => A(34), D => SEL, Z =>
Z(34));
U40 : AO2NHVTX1 port map( A => B(33), B => n5, C => A(33), D => SEL, Z =>
Z(33));
U41 : AO2NHVTX1 port map( A => B(32), B => n5, C => A(32), D => SEL, Z =>
Z(32));
U42 : AO2NHVTX1 port map( A => B(31), B => n5, C => A(31), D => SEL, Z =>
Z(31));
U43 : AO2NHVTX1 port map( A => B(30), B => n5, C => A(30), D => SEL, Z =>
Z(30));
U44 : AO2NHVTX1 port map( A => B(2), B => n5, C => A(2), D => SEL, Z => Z(2)
);
U45 : AO2NHVTX1 port map( A => B(29), B => n5, C => A(29), D => SEL, Z =>
Z(29));
U46 : AO2NHVTX1 port map( A => B(28), B => n5, C => A(28), D => SEL, Z =>
Z(28));
U47 : AO2NHVTX1 port map( A => B(27), B => n5, C => A(27), D => SEL, Z =>
Z(27));
U48 : AO2NHVTX1 port map( A => B(26), B => n5, C => A(26), D => SEL, Z =>
Z(26));
U49 : AO2NHVTX1 port map( A => B(25), B => n5, C => A(25), D => SEL, Z =>
Z(25));
U50 : AO2NHVTX1 port map( A => B(24), B => n5, C => A(24), D => SEL, Z =>
Z(24));
U51 : AO2NHVTX1 port map( A => B(23), B => n5, C => A(23), D => SEL, Z =>
Z(23));
U52 : AO2NHVTX1 port map( A => B(22), B => n5, C => A(22), D => SEL, Z =>
Z(22));
U53 : AO2NHVTX1 port map( A => B(21), B => n5, C => A(21), D => SEL, Z =>
Z(21));
U54 : AO2NHVTX1 port map( A => B(20), B => n5, C => A(20), D => SEL, Z =>
Z(20));
U55 : AO2NHVTX1 port map( A => B(1), B => n5, C => A(1), D => SEL, Z => Z(1)
);
U56 : AO2NHVTX1 port map( A => B(19), B => n5, C => A(19), D => SEL, Z =>
Z(19));
U57 : AO2NHVTX1 port map( A => B(18), B => n5, C => A(18), D => SEL, Z =>
Z(18));
U58 : AO2NHVTX1 port map( A => B(17), B => n5, C => A(17), D => SEL, Z =>
Z(17));
U59 : AO2NHVTX1 port map( A => B(16), B => n5, C => A(16), D => SEL, Z =>
Z(16));
U60 : AO2NHVTX1 port map( A => B(15), B => n5, C => A(15), D => SEL, Z =>
Z(15));
U61 : AO2NHVTX1 port map( A => B(14), B => n5, C => A(14), D => SEL, Z =>
Z(14));
U62 : AO2NHVTX1 port map( A => B(13), B => n5, C => A(13), D => SEL, Z =>
Z(13));
U63 : AO2NHVTX1 port map( A => B(12), B => n5, C => A(12), D => SEL, Z =>
Z(12));
U64 : AO2NHVTX1 port map( A => B(11), B => n5, C => A(11), D => SEL, Z =>
Z(11));
U65 : AO2NHVTX1 port map( A => B(10), B => n5, C => A(10), D => SEL, Z =>
Z(10));
U66 : AO2NHVTX1 port map( A => B(0), B => n5, C => A(0), D => SEL, Z => Z(0)
);
U69 : IVSVTX12 port map( A => SEL, Z => n5);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity MULT is
port( A : in std_logic_vector (54 downto 0); M1, M2, P1, P2 : in std_logic;
COUT : out std_logic; Z : out std_logic_vector (56 downto 0));
end MULT;
architecture SYN_BEHAVIORAL of MULT is
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component ND2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component AO23SVTX6
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component ND3SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO2ASVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component OR2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component OR2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2SVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX10
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component ND2HVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2HVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component AO2ASVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2ASVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2SVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AN2HVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component AO10NSVTX8
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component ND3SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component OR2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO23SVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO23SVTX8
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO2SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component OR2HVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component OR2SVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component BFSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component AN2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2SVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND2SVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO23SVTX2
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component OR2ABSVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
signal Z_56_port, Z_55_port, Z_54_port, Z_53_port, Z_52_port, Z_51_port,
Z_50_port, Z_49_port, Z_48_port, Z_47_port, Z_46_port, Z_45_port,
Z_44_port, Z_43_port, Z_42_port, Z_41_port, Z_40_port, Z_39_port,
Z_37_port, Z_36_port, Z_35_port, Z_34_port, Z_33_port, Z_32_port,
Z_31_port, Z_30_port, Z_29_port, Z_28_port, Z_27_port, Z_26_port,
Z_25_port, Z_24_port, Z_23_port, Z_22_port, Z_21_port, Z_20_port,
Z_19_port, Z_18_port, Z_17_port, Z_16_port, Z_15_port, Z_14_port,
Z_13_port, Z_12_port, Z_11_port, Z_10_port, Z_9_port, Z_8_port, Z_7_port,
Z_6_port, Z_5_port, Z_4_port, Z_3_port, Z_2_port, Z_1_port, n12, n13, n14
, n15, n16, n17, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29,
n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44
, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73
, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, Z_38_port,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161,
n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208 :
std_logic;
begin
COUT <= Z_1_port;
Z <= ( Z_56_port, Z_55_port, Z_54_port, Z_53_port, Z_52_port, Z_51_port,
Z_50_port, Z_49_port, Z_48_port, Z_47_port, Z_46_port, Z_45_port,
Z_44_port, Z_43_port, Z_42_port, Z_41_port, Z_40_port, Z_39_port,
Z_38_port, Z_37_port, Z_36_port, Z_35_port, Z_34_port, Z_33_port,
Z_32_port, Z_31_port, Z_30_port, Z_29_port, Z_28_port, Z_27_port,
Z_26_port, Z_25_port, Z_24_port, Z_23_port, Z_22_port, Z_21_port,
Z_20_port, Z_19_port, Z_18_port, Z_17_port, Z_16_port, Z_15_port,
Z_14_port, Z_13_port, Z_12_port, Z_11_port, Z_10_port, Z_9_port, Z_8_port
, Z_7_port, Z_6_port, Z_5_port, Z_4_port, Z_3_port, Z_2_port, Z_1_port,
Z_1_port );
U11 : IVHVTX0H port map( A => A(6), Z => n16);
U14 : IVHVTX0H port map( A => A(5), Z => n19);
U17 : IVHVTX0H port map( A => A(4), Z => n22);
U20 : IVHVTX0H port map( A => A(3), Z => n24);
U24 : IVHVTX0H port map( A => A(53), Z => n27);
U27 : IVHVTX0H port map( A => A(52), Z => n29);
U30 : IVHVTX0H port map( A => A(51), Z => n31);
U36 : IVHVTX0H port map( A => A(49), Z => n35);
U39 : IVHVTX0H port map( A => A(48), Z => n37);
U42 : IVHVTX0H port map( A => A(2), Z => n26);
U48 : IVHVTX0H port map( A => A(46), Z => n43);
U54 : IVHVTX0H port map( A => A(44), Z => n47);
U57 : IVHVTX0H port map( A => A(43), Z => n49);
U60 : IVHVTX0H port map( A => A(42), Z => n51);
U63 : IVHVTX0H port map( A => A(41), Z => n53);
U66 : IVHVTX0H port map( A => A(40), Z => n55);
U81 : IVHVTX0H port map( A => A(36), Z => n65);
U87 : IVHVTX0H port map( A => A(34), Z => n69);
U90 : IVHVTX0H port map( A => A(33), Z => n71);
U93 : IVHVTX0H port map( A => A(32), Z => n73);
U96 : IVHVTX0H port map( A => A(31), Z => n75);
U99 : IVHVTX0H port map( A => A(30), Z => n77);
U102 : IVHVTX0H port map( A => A(29), Z => n79);
U105 : IVHVTX0H port map( A => A(28), Z => n81);
U107 : IVHVTX0H port map( A => A(0), Z => n63);
U110 : IVHVTX0H port map( A => A(27), Z => n83);
U113 : IVHVTX0H port map( A => A(26), Z => n85);
U116 : IVHVTX0H port map( A => A(25), Z => n87);
U119 : IVHVTX0H port map( A => A(24), Z => n89);
U122 : IVHVTX0H port map( A => A(23), Z => n91);
U125 : IVHVTX0H port map( A => A(22), Z => n93);
U131 : IVHVTX0H port map( A => A(20), Z => n97);
U134 : IVHVTX0H port map( A => A(19), Z => n99);
U143 : IVHVTX0H port map( A => A(16), Z => n105);
U146 : IVHVTX0H port map( A => A(15), Z => n107);
U149 : IVHVTX0H port map( A => A(14), Z => n109);
U155 : IVHVTX0H port map( A => A(12), Z => n113);
U158 : IVHVTX0H port map( A => A(11), Z => n115);
U161 : IVHVTX0H port map( A => A(10), Z => n117);
U165 : IVHVTX0H port map( A => A(9), Z => n118);
U168 : IVHVTX0H port map( A => A(7), Z => n13);
U169 : IVHVTX0H port map( A => A(8), Z => n121);
U176 : AO23SVTX6 port map( A => A(30), B => n187, C => n181, D => n77, E =>
n78, Z => Z_32_port);
U177 : ND3SVTX8 port map( A => n166, B => n167, C => n32, Z => Z_53_port);
U178 : AO2ASVTX4 port map( A => n133, B => n67, C => n171, D => A(35), Z =>
n66);
U179 : IVSVTX6 port map( A => n192, Z => n193);
U180 : OR2SVTX6 port map( A => n137, B => n41, Z => n124);
U181 : AO23SVTX6 port map( A => A(49), B => n185, C => n137, D => n35, E =>
n36, Z => Z_51_port);
U182 : OR2SVTX4 port map( A => A(1), B => n186, Z => n123);
U183 : ND3SVTX8 port map( A => n123, B => n124, C => n62, Z => Z_3_port);
U184 : AN2SVTX1 port map( A => M2, B => n63, Z => n125);
U185 : AN2HVTX1 port map( A => A(0), B => P2, Z => n126);
U186 : NR2SVTX2 port map( A => n125, B => n126, Z => n62);
U187 : IVSVTX10 port map( A => n170, Z => n186);
U188 : IVSVTX2 port map( A => A(1), Z => n41);
U189 : ND2HVTX4 port map( A => M2, B => n39, Z => n145);
U190 : AO23SVTX6 port map( A => A(4), B => n187, C => n181, D => n22, E =>
n23, Z => Z_6_port);
U191 : ND2HVTX4 port map( A => n95, B => n175, Z => n194);
U192 : ND2SVTX2 port map( A => M2, B => n111, Z => n127);
U193 : ND2SVTX1 port map( A => P2, B => A(13), Z => n128);
U194 : AN2SVTX4 port map( A => n127, B => n128, Z => n110);
U195 : IVSVTX2 port map( A => A(13), Z => n111);
U196 : AO23SVTX6 port map( A => A(14), B => n185, C => n181, D => n109, E =>
n110, Z => Z_16_port);
U197 : AO2HVTX2 port map( A => M2, B => n79, C => P2, D => A(29), Z => n78);
U198 : ND3SVTX8 port map( A => n154, B => n155, C => n58, Z => Z_41_port);
U199 : AN2SVTX4 port map( A => n156, B => n157, Z => n58);
U200 : IVSVTX8 port map( A => n203, Z => n17);
U201 : AO2ASVTX6 port map( A => n133, B => n13, C => n208, D => A(7), Z =>
n122);
U202 : AO23SVTX6 port map( A => A(13), B => n186, C => n138, D => n111, E =>
n112, Z => Z_15_port);
U203 : AO2ASVTX2 port map( A => A(20), B => n175, C => n208, D => A(20), Z
=> n96);
U204 : AO2ASVTX2 port map( A => A(23), B => n205, C => A(23), D => n171, Z
=> n90);
U205 : AO2SVTX4 port map( A => n203, B => n87, C => n208, D => A(25), Z =>
n86);
U206 : AN2HVTX2 port map( A => M2, B => n35, Z => n162);
U207 : IVSVTX8 port map( A => M2, Z => n130);
U208 : AO4ASVTX4 port map( A => P2, B => n131, C => n130, D => A(14), Z =>
n129);
U209 : IVSVTX12 port map( A => A(14), Z => n131);
U210 : AO10NSVTX8 port map( A => n132, B => n184, C => n136, D => A(15), E
=> n129, Z => Z_17_port);
U211 : IVSVTX12 port map( A => A(15), Z => n132);
U212 : AO23SVTX6 port map( A => A(5), B => n17, C => n204, D => n19, E =>
n20, Z => Z_8_port);
U213 : IVSVTX4 port map( A => n134, Z => n20);
U214 : AO2ASVTX6 port map( A => A(22), B => n203, C => A(22), D => n193, Z
=> n92);
U215 : IVSVTX10 port map( A => M2, Z => n133);
U216 : IVSVTX8 port map( A => n202, Z => n203);
U217 : AO23SVTX6 port map( A => A(33), B => n187, C => n138, D => n71, E =>
n72, Z => Z_35_port);
U218 : AO23SVTX6 port map( A => A(11), B => n186, C => n181, D => n115, E =>
n116, Z => Z_13_port);
U219 : AO23SVTX6 port map( A => A(36), B => n185, C => n138, D => n65, E =>
n66, Z => Z_38_port);
U220 : ND2HVTX1 port map( A => A(37), B => P2, Z => n140);
U221 : ND3SVTX4 port map( A => n147, B => n148, C => n64, Z => Z_39_port);
U222 : AO23SVTX6 port map( A => A(26), B => n186, C => n138, D => n85, E =>
n86, Z => Z_28_port);
U223 : ND2HVTX1 port map( A => M2, B => n59, Z => n156);
U224 : AO23SVTX6 port map( A => A(38), B => n187, C => n137, D => n59, E =>
n60, Z => Z_40_port);
U225 : AN2SVTX4 port map( A => n168, B => n169, Z => n32);
U226 : OR2SVTX2 port map( A => A(51), B => n187, Z => n166);
U227 : AO23SVTX4 port map( A => n185, B => A(0), C => n174, D => n181, E =>
n17, Z => Z_2_port);
U228 : IVSVTX12 port map( A => P1, Z => n181);
U229 : AN2HVTX1 port map( A => A(49), B => P2, Z => n163);
U230 : AN2HVTX1 port map( A => A(28), B => P2, Z => n144);
U231 : OR2SVTX6 port map( A => n181, B => n61, Z => n148);
U232 : AO23SVTX6 port map( A => A(20), B => n186, C => n138, D => n97, E =>
n98, Z => Z_22_port);
U233 : AO2ASVTX6 port map( A => n202, B => n22, C => n171, D => A(4), Z =>
n21);
U234 : AO23SVTX6 port map( A => A(31), B => n186, C => n138, D => n75, E =>
n76, Z => Z_33_port);
U235 : AO23SVTX6 port map( A => A(2), B => n185, C => n138, D => n26, E =>
n40, Z => Z_4_port);
U236 : AO23SVTX4 port map( A => A(25), B => n186, C => n137, D => n87, E =>
n88, Z => Z_27_port);
U237 : ND2HVTX1 port map( A => A(38), B => n206, Z => n157);
U238 : IVSVTX6 port map( A => M2, Z => n202);
U239 : AO4ASVTX6 port map( A => n170, B => A(6), C => n135, D => n14, Z =>
n134);
U240 : IVSVTX12 port map( A => A(6), Z => n135);
U241 : IVSVTX8 port map( A => P1, Z => n14);
U242 : AO23SVTX8 port map( A => A(23), B => n186, C => n138, D => n91, E =>
n92, Z => Z_25_port);
U243 : IVSVTX12 port map( A => n14, Z => n136);
U244 : IVSVTX12 port map( A => n136, Z => n137);
U245 : IVSVTX12 port map( A => n136, Z => n138);
U246 : AO2ASVTX4 port map( A => A(24), B => n205, C => A(24), D => n171, Z
=> n88);
U247 : AO2SVTX2 port map( A => n205, B => n41, C => n208, D => A(1), Z =>
n40);
U248 : AN2SVTX4 port map( A => n178, B => n179, Z => n28);
U249 : AO23SVTX6 port map( A => A(24), B => n186, C => n138, D => n89, E =>
n90, Z => Z_26_port);
U250 : ND2SVTX1 port map( A => A(21), B => n208, Z => n195);
U251 : AO23SVTX4 port map( A => A(47), B => n185, C => n181, D => n39, E =>
n42, Z => Z_49_port);
U252 : AO23SVTX4 port map( A => A(8), B => n187, C => n138, D => n121, E =>
n122, Z => Z_10_port);
U253 : OR2HVTX4 port map( A => A(35), B => n187, Z => n158);
U254 : OR2SVTX8 port map( A => A(37), B => n187, Z => n147);
U255 : AO2SVTX4 port map( A => n205, B => n24, C => n208, D => A(3), Z =>
n23);
U256 : BFSVTX12 port map( A => M2, Z => n205);
U257 : ND2HVTX4 port map( A => A(17), B => n171, Z => n191);
U258 : ND2SVTX2 port map( A => M2, B => n61, Z => n139);
U259 : AN2SVTX4 port map( A => n139, B => n140, Z => n60);
U260 : IVSVTX0H port map( A => A(37), Z => n61);
U261 : AO23SVTX6 port map( A => A(3), B => n185, C => n181, D => n24, E =>
n25, Z => Z_5_port);
U262 : IVSVTX12 port map( A => n12, Z => n170);
U263 : OR2SVTX6 port map( A => A(29), B => n185, Z => n141);
U264 : OR2SVTX4 port map( A => n181, B => n79, Z => n142);
U265 : ND3SVTX8 port map( A => n141, B => n142, C => n80, Z => Z_31_port);
U266 : AN2SVTX1 port map( A => M2, B => n81, Z => n143);
U267 : NR2SVTX2 port map( A => n143, B => n144, Z => n80);
U268 : IVSVTX12 port map( A => n133, Z => n175);
U269 : ND3SVTX8 port map( A => n196, B => n197, C => n94, Z => Z_24_port);
U270 : AN2SVTX4 port map( A => n194, B => n195, Z => n94);
U271 : ND3SVTX8 port map( A => n172, B => n173, C => n52, Z => Z_44_port);
U272 : AO2SVTX2 port map( A => n175, B => n53, C => A(41), D => n171, Z =>
n52);
U273 : ND3SVTX8 port map( A => n200, B => n201, C => n54, Z => Z_43_port);
U274 : AO23SVTX6 port map( A => A(9), B => n186, C => n181, D => n118, E =>
n120, Z => Z_11_port);
U275 : OR2SVTX8 port map( A => A(41), B => n186, Z => n200);
U276 : ND3SVTX8 port map( A => n176, B => n177, C => n28, Z => Z_55_port);
U277 : IVSVTX12 port map( A => n207, Z => n208);
U278 : ND2SVTX1 port map( A => A(47), B => P2, Z => n146);
U279 : AN2SVTX4 port map( A => n145, B => n146, Z => n38);
U280 : IVSVTX2 port map( A => A(47), Z => n39);
U281 : AO2SVTX4 port map( A => n175, B => n57, C => A(39), D => n171, Z =>
n56);
U282 : AO2SVTX2 port map( A => M2, B => n37, C => P2, D => A(48), Z => n36);
U283 : AO23SVTX6 port map( A => A(5), B => n186, C => n137, D => n19, E =>
n21, Z => Z_7_port);
U284 : AO2SVTX2 port map( A => n203, B => n65, C => n206, D => A(36), Z =>
n64);
U285 : OR2SVTX4 port map( A => n181, B => n93, Z => n197);
U286 : ND3SVTX8 port map( A => n182, B => n183, C => n104, Z => Z_19_port);
U287 : AO2SVTX2 port map( A => M2, B => n105, C => n208, D => A(16), Z =>
n104);
U288 : OR2SVTX6 port map( A => A(39), B => n186, Z => n154);
U289 : IVSVTX6 port map( A => n12, Z => n184);
U290 : AO23SVTX4 port map( A => A(46), B => n187, C => n181, D => n43, E =>
n44, Z => Z_48_port);
U291 : OR2SVTX6 port map( A => A(17), B => n187, Z => n182);
U292 : OR2SVTX4 port map( A => A(18), B => n185, Z => n150);
U293 : OR2SVTX6 port map( A => n137, B => n101, Z => n151);
U294 : ND3SVTX8 port map( A => n150, B => n151, C => n102, Z => Z_20_port);
U295 : IVSVTX2 port map( A => A(18), Z => n101);
U296 : AN2SVTX6 port map( A => n190, B => n191, Z => n102);
U297 : AO2SVTX4 port map( A => n175, B => n121, C => n206, D => A(8), Z =>
n120);
U298 : OR2SVTX6 port map( A => A(7), B => n185, Z => n152);
U299 : OR2SVTX4 port map( A => n13, B => n181, Z => n153);
U300 : ND3SVTX8 port map( A => n152, B => n153, C => n15, Z => Z_9_port);
U301 : OR2SVTX6 port map( A => n137, B => n67, Z => n159);
U302 : AO23SVTX6 port map( A => A(21), B => n185, C => n138, D => n95, E =>
n96, Z => Z_23_port);
U303 : AN2SVTX4 port map( A => n198, B => n199, Z => n54);
U304 : AO23SVTX4 port map( A => A(16), B => n186, C => n138, D => n105, E =>
n106, Z => Z_18_port);
U305 : IVSVTX8 port map( A => M1, Z => n12);
U306 : AO23SVTX4 port map( A => A(12), B => n185, C => n137, D => n113, E =>
n114, Z => Z_14_port);
U307 : AO23SVTX4 port map( A => A(28), B => n187, C => n137, D => n81, E =>
n82, Z => Z_30_port);
U308 : AO2SVTX2 port map( A => n175, B => n99, C => A(19), D => n193, Z =>
n98);
U309 : OR2SVTX4 port map( A => n181, B => n51, Z => n173);
U310 : OR2SVTX4 port map( A => n181, B => n33, Z => n161);
U311 : OR2SVTX4 port map( A => A(50), B => n185, Z => n160);
U312 : AO2SVTX4 port map( A => n205, B => n115, C => n206, D => A(11), Z =>
n114);
U313 : AO23SVTX4 port map( A => A(43), B => n186, C => n138, D => n49, E =>
n50, Z => Z_45_port);
U314 : AO2SVTX2 port map( A => n175, B => n101, C => A(18), D => n206, Z =>
n100);
U315 : IVSVTX10 port map( A => n207, Z => n206);
U316 : OR2SVTX4 port map( A => A(42), B => n187, Z => n172);
U317 : OR2SVTX4 port map( A => A(45), B => n187, Z => n188);
U318 : AO23SVTX4 port map( A => A(48), B => n187, C => n137, D => n37, E =>
n38, Z => Z_50_port);
U319 : AO2SVTX4 port map( A => n175, B => n26, C => n171, D => A(2), Z =>
n25);
U320 : OR2SVTX4 port map( A => n137, B => n57, Z => n155);
U321 : IVSVTX2 port map( A => A(39), Z => n57);
U322 : IVSVTX2 port map( A => A(38), Z => n59);
U323 : ND2SVTX2 port map( A => n175, B => n29, Z => n178);
U324 : AO2SVTX2 port map( A => n170, B => n117, C => P1, D => A(10), Z =>
n119);
U325 : ND3SVTX8 port map( A => n158, B => n68, C => n159, Z => Z_37_port);
U326 : IVSVTX2 port map( A => A(35), Z => n67);
U327 : AO2SVTX2 port map( A => n205, B => n77, C => A(30), D => n206, Z =>
n76);
U328 : AO2SVTX4 port map( A => n175, B => n73, C => n193, D => A(32), Z =>
n72);
U329 : AO23SVTX6 port map( A => A(44), B => n186, C => n138, D => n47, E =>
n48, Z => Z_46_port);
U330 : ND3SVTX8 port map( A => n160, B => n161, C => n34, Z => Z_52_port);
U331 : NR2SVTX2 port map( A => n162, B => n163, Z => n34);
U332 : IVSVTX0H port map( A => A(50), Z => n33);
U333 : IVSVTX12 port map( A => n207, Z => n171);
U334 : ND2SVTX8 port map( A => n17, B => n185, Z => Z_1_port);
U335 : AO23SVTX4 port map( A => A(9), B => n17, C => n204, D => n118, E =>
n119, Z => Z_12_port);
U336 : OR2SVTX4 port map( A => n181, B => n53, Z => n201);
U337 : AO2ASVTX2 port map( A => n133, B => n69, C => A(34), D => n171, Z =>
n68);
U338 : AO2SVTX2 port map( A => n203, B => n113, C => n208, D => A(12), Z =>
n112);
U339 : AO23SVTX4 port map( A => A(52), B => n187, C => n138, D => n29, E =>
n30, Z => Z_54_port);
U340 : IVSVTX4 port map( A => n164, Z => n82);
U341 : AO2SVTX1 port map( A => M2, B => n107, C => A(15), D => P2, Z => n106
);
U342 : AO23SVTX4 port map( A => A(19), B => n185, C => n138, D => n99, E =>
n100, Z => Z_21_port);
U343 : AO2SVTX2 port map( A => n203, B => n51, C => n206, D => A(42), Z =>
n50);
U344 : ND2SVTX2 port map( A => A(40), B => n171, Z => n199);
U345 : OR2SVTX4 port map( A => A(22), B => n185, Z => n196);
U346 : AO23SVTX4 port map( A => A(40), B => n187, C => n137, D => n55, E =>
n56, Z => Z_42_port);
U347 : AO2SVTX1 port map( A => M2, B => n16, C => A(6), D => P2, Z => n15);
U348 : AO2SVTX1 port map( A => M2, B => n117, C => P2, D => A(10), Z => n116
);
U349 : AO4ASVTX4 port map( A => P2, B => n165, C => A(27), D => n133, Z =>
n164);
U350 : IVSVTX12 port map( A => A(27), Z => n165);
U351 : OR2SVTX2 port map( A => n181, B => n31, Z => n167);
U352 : ND2SVTX2 port map( A => n175, B => n33, Z => n168);
U353 : ND2HVTX1 port map( A => A(50), B => n208, Z => n169);
U354 : IVSVTX2 port map( A => n206, Z => n204);
U355 : ND2SVTX4 port map( A => n205, B => n103, Z => n190);
U356 : AO23SVTX2 port map( A => n17, B => A(53), C => n204, D => n180, E =>
n186, Z => Z_56_port);
U357 : IVSVTX12 port map( A => A(0), Z => n174);
U358 : AO2SVTX2 port map( A => M2, B => n45, C => P2, D => A(45), Z => n44);
U359 : AO2SVTX1 port map( A => M2, B => n85, C => A(26), D => P2, Z => n84);
U360 : AO2SVTX2 port map( A => n175, B => n49, C => n193, D => A(43), Z =>
n48);
U361 : AO23SVTX4 port map( A => A(34), B => n187, C => n138, D => n69, E =>
n70, Z => Z_36_port);
U362 : OR2SVTX4 port map( A => A(53), B => n185, Z => n176);
U363 : AO23SVTX4 port map( A => A(32), B => n185, C => n137, D => n73, E =>
n74, Z => Z_34_port);
U364 : AO2SVTX2 port map( A => M2, B => n43, C => P2, D => A(46), Z => n42);
U365 : AO2SVTX2 port map( A => n175, B => n47, C => A(44), D => n171, Z =>
n46);
U366 : IVSVTX12 port map( A => n170, Z => n187);
U367 : OR2SVTX2 port map( A => n181, B => n27, Z => n177);
U368 : OR2ABSVTX2 port map( A => P2, B => A(52), Z => n179);
U369 : IVSVTX12 port map( A => A(53), Z => n180);
U370 : IVSVTX12 port map( A => n184, Z => n185);
U371 : OR2SVTX4 port map( A => n181, B => n103, Z => n183);
U372 : AO23SVTX2 port map( A => A(27), B => n187, C => n137, D => n83, E =>
n84, Z => Z_29_port);
U373 : AO2SVTX1 port map( A => M2, B => n71, C => A(33), D => P2, Z => n70);
U374 : OR2SVTX4 port map( A => n181, B => n45, Z => n189);
U375 : ND3SVTX8 port map( A => n188, B => n189, C => n46, Z => Z_47_port);
U376 : IVSVTX0H port map( A => A(45), Z => n45);
U377 : IVSVTX2 port map( A => A(17), Z => n103);
U378 : IVSVTX2 port map( A => P2, Z => n192);
U379 : IVSVTX2 port map( A => A(21), Z => n95);
U380 : ND2HVTX1 port map( A => M2, B => n55, Z => n198);
U381 : AO2SVTX2 port map( A => n175, B => n31, C => n208, D => A(51), Z =>
n30);
U382 : AO2SVTX1 port map( A => M2, B => n75, C => A(31), D => P2, Z => n74);
U383 : IVSVTX12 port map( A => P2, Z => n207);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity gl_csa32_n8 is
port( A, B, C : in std_logic_vector (8 downto 0); Cin : in std_logic; Z, Y
: out std_logic_vector (8 downto 0));
end gl_csa32_n8;
architecture SYN_BEHAVIORAL of gl_csa32_n8 is
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOSVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOHVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component EO3SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
signal Y_8_port, Y_7_port, Y_6_port, Y_5_port, Y_4_port, Y_3_port, Y_2_port,
Y_1_port, n16, n17, n18, n19, n20, n21, n22, n23 : std_logic;
begin
Y <= ( Y_8_port, Y_7_port, Y_6_port, Y_5_port, Y_4_port, Y_3_port, Y_2_port,
Y_1_port, Cin );
U17 : EOHVTX1 port map( A => B(7), B => A(7), Z => n16);
U25 : EOHVTX1 port map( A => B(3), B => A(3), Z => n20);
U27 : EOHVTX1 port map( A => B(2), B => A(2), Z => n21);
U29 : EOHVTX1 port map( A => B(1), B => A(1), Z => n22);
U31 : EOHVTX1 port map( A => B(0), B => A(0), Z => n23);
U32 : EOSVTX4 port map( A => n18, B => C(5), Z => Z(5));
U33 : AO2NSVTX4 port map( A => B(5), B => A(5), C => n18, D => C(5), Z =>
Y_6_port);
U34 : EOSVTX6 port map( A => C(7), B => n16, Z => Z(7));
U35 : EOHVTX2 port map( A => B(6), B => A(6), Z => n17);
U36 : EOSVTX2 port map( A => n22, B => C(1), Z => Z(1));
U37 : AO2NSVTX2 port map( A => B(1), B => A(1), C => C(1), D => n22, Z =>
Y_2_port);
U38 : AO2NSVTX6 port map( A => B(2), B => A(2), C => C(2), D => n21, Z =>
Y_3_port);
U39 : EOSVTX2 port map( A => n23, B => C(0), Z => Z(0));
U40 : AO2NSVTX2 port map( A => B(0), B => A(0), C => n23, D => C(0), Z =>
Y_1_port);
U41 : AO2NSVTX6 port map( A => B(4), B => A(4), C => C(4), D => n19, Z =>
Y_5_port);
U42 : EOSVTX4 port map( A => n21, B => C(2), Z => Z(2));
U43 : EOSVTX4 port map( A => n17, B => C(6), Z => Z(6));
U44 : EOSVTX8 port map( A => n19, B => C(4), Z => Z(4));
U45 : EOSVTX2 port map( A => n20, B => C(3), Z => Z(3));
U46 : AO2NSVTX2 port map( A => B(3), B => A(3), C => C(3), D => n20, Z =>
Y_4_port);
U47 : EOHVTX2 port map( A => B(4), B => A(4), Z => n19);
U48 : AO2NSVTX4 port map( A => B(6), B => A(6), C => n17, D => C(6), Z =>
Y_7_port);
U49 : AO2NSVTX4 port map( A => B(7), B => A(7), C => n16, D => C(7), Z =>
Y_8_port);
U50 : EOHVTX2 port map( A => B(5), B => A(5), Z => n18);
U51 : EO3SVTX4 port map( A => A(8), B => B(8), C => C(8), Z => Z(8));
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity csa32LSBs_n47 is
port( A, B, C : in std_logic_vector (47 downto 0); Cin : in std_logic;
Cout : out std_logic; Z, Y : out std_logic_vector (47 downto 0));
end csa32LSBs_n47;
architecture SYN_BEHAVIORAL of csa32LSBs_n47 is
component EOHVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EOSVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component ND2HVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component ENSVTX4
port( A, B : in std_logic; Z : out std_logic);
end component;
component EOSVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND2SVTX6
port( A, B : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
signal Y_47_port, Y_46_port, Y_45_port, Y_44_port, Y_43_port, Y_42_port,
Y_41_port, Y_40_port, Y_39_port, Y_38_port, Y_37_port, Y_36_port,
Y_35_port, Y_34_port, Y_33_port, Y_32_port, Y_31_port, Y_30_port,
Y_29_port, Y_28_port, Y_27_port, Y_26_port, Y_25_port, Y_24_port,
Y_23_port, Y_22_port, Y_21_port, Y_20_port, Y_19_port, Y_18_port,
Y_17_port, Y_16_port, Y_15_port, Y_14_port, Y_13_port, Y_12_port,
Y_11_port, Y_10_port, Y_9_port, Y_8_port, Y_7_port, Y_6_port, Y_5_port,
Y_4_port, Y_3_port, Y_2_port, Y_1_port, n17, n18, n19, n20, n21, n22, n23
, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52
, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66,
n67, n68, n69, n70, n71, n72, n73, n74, n75, n76 : std_logic;
begin
Y <= ( Y_47_port, Y_46_port, Y_45_port, Y_44_port, Y_43_port, Y_42_port,
Y_41_port, Y_40_port, Y_39_port, Y_38_port, Y_37_port, Y_36_port,
Y_35_port, Y_34_port, Y_33_port, Y_32_port, Y_31_port, Y_30_port,
Y_29_port, Y_28_port, Y_27_port, Y_26_port, Y_25_port, Y_24_port,
Y_23_port, Y_22_port, Y_21_port, Y_20_port, Y_19_port, Y_18_port,
Y_17_port, Y_16_port, Y_15_port, Y_14_port, Y_13_port, Y_12_port,
Y_11_port, Y_10_port, Y_9_port, Y_8_port, Y_7_port, Y_6_port, Y_5_port,
Y_4_port, Y_3_port, Y_2_port, Y_1_port, Cin );
U56 : EOHVTX1 port map( A => B(8), B => A(8), Z => n18);
U58 : EOHVTX1 port map( A => B(7), B => A(7), Z => n19);
U60 : EOHVTX1 port map( A => B(6), B => A(6), Z => n20);
U62 : EOHVTX1 port map( A => B(5), B => A(5), Z => n21);
U64 : EOHVTX1 port map( A => B(4), B => A(4), Z => n22);
U66 : EOHVTX1 port map( A => B(3), B => A(3), Z => n31);
U68 : EOHVTX1 port map( A => B(46), B => A(46), Z => n24);
U70 : EOHVTX1 port map( A => B(45), B => A(45), Z => n25);
U72 : EOHVTX1 port map( A => B(44), B => A(44), Z => n26);
U74 : EOHVTX1 port map( A => B(43), B => A(43), Z => n27);
U76 : EOHVTX1 port map( A => B(42), B => A(42), Z => n28);
U80 : EOHVTX1 port map( A => B(40), B => A(40), Z => n30);
U82 : EOHVTX1 port map( A => B(39), B => A(39), Z => n32);
U84 : EOHVTX1 port map( A => B(2), B => A(2), Z => n42);
U86 : EOHVTX1 port map( A => B(38), B => A(38), Z => n33);
U88 : EOHVTX1 port map( A => B(37), B => A(37), Z => n34);
U90 : EOHVTX1 port map( A => B(36), B => A(36), Z => n35);
U92 : EOHVTX1 port map( A => B(35), B => A(35), Z => n36);
U94 : EOHVTX1 port map( A => B(34), B => A(34), Z => n37);
U96 : EOHVTX1 port map( A => B(33), B => A(33), Z => n38);
U98 : EOHVTX1 port map( A => B(32), B => A(32), Z => n39);
U100 : EOHVTX1 port map( A => B(31), B => A(31), Z => n40);
U102 : EOHVTX1 port map( A => B(30), B => A(30), Z => n41);
U106 : EOHVTX1 port map( A => B(1), B => A(1), Z => n53);
U108 : EOHVTX1 port map( A => B(28), B => A(28), Z => n44);
U110 : EOHVTX1 port map( A => B(27), B => A(27), Z => n45);
U112 : EOHVTX1 port map( A => B(26), B => A(26), Z => n46);
U114 : EOHVTX1 port map( A => B(25), B => A(25), Z => n47);
U116 : EOHVTX1 port map( A => B(24), B => A(24), Z => n48);
U118 : EOHVTX1 port map( A => B(23), B => A(23), Z => n49);
U120 : EOHVTX1 port map( A => B(22), B => A(22), Z => n50);
U122 : EOHVTX1 port map( A => B(21), B => A(21), Z => n51);
U124 : EOHVTX1 port map( A => B(20), B => A(20), Z => n52);
U126 : EOHVTX1 port map( A => B(19), B => A(19), Z => n54);
U128 : EOHVTX1 port map( A => B(0), B => A(0), Z => n64);
U130 : EOHVTX1 port map( A => B(18), B => A(18), Z => n55);
U132 : EOHVTX1 port map( A => B(17), B => A(17), Z => n56);
U134 : EOHVTX1 port map( A => B(16), B => A(16), Z => n57);
U136 : EOHVTX1 port map( A => B(15), B => A(15), Z => n58);
U138 : EOHVTX1 port map( A => B(14), B => A(14), Z => n59);
U140 : EOHVTX1 port map( A => B(13), B => A(13), Z => n60);
U142 : EOHVTX1 port map( A => B(12), B => A(12), Z => n61);
U144 : EOHVTX1 port map( A => B(11), B => A(11), Z => n62);
U146 : EOHVTX1 port map( A => B(10), B => A(10), Z => n63);
U148 : EOHVTX1 port map( A => B(9), B => A(9), Z => n17);
U150 : EOHVTX1 port map( A => B(47), B => A(47), Z => n23);
U151 : EOSVTX6 port map( A => C(28), B => n44, Z => Z(28));
U152 : AO2NSVTX8 port map( A => B(34), B => A(34), C => C(34), D => n37, Z
=> Y_35_port);
U153 : EOSVTX8 port map( A => C(3), B => n31, Z => Z(3));
U154 : AO4ABSVTX6 port map( A => n31, B => C(3), C => n75, D => n76, Z =>
Y_4_port);
U155 : EOSVTX6 port map( A => n25, B => C(45), Z => Z(45));
U156 : EOSVTX8 port map( A => n22, B => C(4), Z => Z(4));
U157 : AO2NSVTX6 port map( A => B(4), B => A(4), C => n22, D => C(4), Z =>
Y_5_port);
U158 : ND2SVTX2 port map( A => B(7), B => A(7), Z => n65);
U159 : ND2SVTX1 port map( A => n19, B => C(7), Z => n66);
U160 : ND2SVTX2 port map( A => n65, B => n66, Z => Y_8_port);
U161 : AO2NSVTX6 port map( A => B(22), B => A(22), C => C(22), D => n50, Z
=> Y_23_port);
U162 : AO2NSVTX4 port map( A => B(32), B => A(32), C => C(32), D => n39, Z
=> Y_33_port);
U163 : AO2NSVTX6 port map( A => B(5), B => A(5), C => C(5), D => n21, Z =>
Y_6_port);
U164 : EOSVTX8 port map( A => C(7), B => n19, Z => Z(7));
U165 : EOSVTX8 port map( A => C(26), B => n46, Z => Z(26));
U166 : AO2NSVTX4 port map( A => B(38), B => A(38), C => n33, D => C(38), Z
=> Y_39_port);
U167 : EOSVTX4 port map( A => C(38), B => n33, Z => Z(38));
U168 : AO2NSVTX4 port map( A => B(24), B => A(24), C => n48, D => C(24), Z
=> Y_25_port);
U169 : EOSVTX4 port map( A => n24, B => C(46), Z => Z(46));
U170 : EOSVTX4 port map( A => C(21), B => n51, Z => Z(21));
U171 : AO2NSVTX6 port map( A => B(40), B => A(40), C => C(40), D => n30, Z
=> Y_41_port);
U172 : IVSVTX4 port map( A => C(41), Z => n72);
U173 : ND2SVTX2 port map( A => n43, B => C(29), Z => n68);
U174 : AO2NSVTX6 port map( A => B(8), B => A(8), C => n18, D => C(8), Z =>
Y_9_port);
U175 : EOSVTX4 port map( A => n55, B => C(18), Z => Z(18));
U176 : EOSVTX4 port map( A => C(24), B => n48, Z => Z(24));
U177 : ND2HVTX4 port map( A => n71, B => C(41), Z => n74);
U178 : EOSVTX4 port map( A => n43, B => C(29), Z => Z(29));
U179 : AO2NSVTX4 port map( A => B(17), B => A(17), C => n56, D => C(17), Z
=> Y_18_port);
U180 : EOSVTX6 port map( A => C(10), B => n63, Z => Z(10));
U181 : EOSVTX4 port map( A => n35, B => C(36), Z => Z(36));
U182 : AO2NSVTX8 port map( A => B(13), B => A(13), C => C(13), D => n60, Z
=> Y_14_port);
U183 : AO2NSVTX8 port map( A => B(25), B => A(25), C => C(25), D => n47, Z
=> Y_26_port);
U184 : AO2NSVTX8 port map( A => B(41), B => A(41), C => C(41), D => n29, Z
=> Y_42_port);
U185 : ND2SVTX2 port map( A => B(29), B => A(29), Z => n67);
U186 : ND2SVTX2 port map( A => n67, B => n68, Z => Y_30_port);
U187 : EOSVTX1 port map( A => B(29), B => A(29), Z => n43);
U188 : EOSVTX4 port map( A => n47, B => C(25), Z => Z(25));
U189 : AO2NSVTX6 port map( A => B(45), B => A(45), C => C(45), D => n25, Z
=> Y_46_port);
U190 : ENSVTX4 port map( A => n59, B => n69, Z => Z(14));
U191 : AO2NSVTX6 port map( A => B(31), B => A(31), C => n40, D => C(31), Z
=> Y_32_port);
U192 : AO2NSVTX4 port map( A => B(43), B => A(43), C => n27, D => C(43), Z
=> Y_44_port);
U193 : EOSVTX4 port map( A => C(43), B => n27, Z => Z(43));
U194 : AO2NSVTX6 port map( A => B(46), B => A(46), C => C(46), D => n24, Z
=> Y_47_port);
U195 : AO2NSVTX4 port map( A => B(15), B => A(15), C => n58, D => C(15), Z
=> Y_16_port);
U196 : EOSVTX4 port map( A => n52, B => C(20), Z => Z(20));
U197 : AO2NSVTX8 port map( A => B(20), B => A(20), C => C(20), D => n52, Z
=> Y_21_port);
U198 : AO2NSVTX8 port map( A => B(9), B => A(9), C => C(9), D => n17, Z =>
Y_10_port);
U199 : EOSVTX4 port map( A => n17, B => C(9), Z => Z(9));
U200 : EOSVTX4 port map( A => n34, B => C(37), Z => Z(37));
U201 : IVSVTX4 port map( A => C(14), Z => n69);
U202 : AO2NSVTX6 port map( A => B(35), B => A(35), C => C(35), D => n36, Z
=> Y_36_port);
U203 : EOSVTX2 port map( A => n54, B => C(19), Z => Z(19));
U204 : IVSVTX4 port map( A => n69, Z => n70);
U205 : AO2NSVTX4 port map( A => B(10), B => A(10), C => n63, D => C(10), Z
=> Y_11_port);
U206 : AO2NSVTX6 port map( A => B(6), B => A(6), C => C(6), D => n20, Z =>
Y_7_port);
U207 : EOSVTX4 port map( A => C(11), B => n62, Z => Z(11));
U208 : EOSVTX4 port map( A => n40, B => C(31), Z => Z(31));
U209 : AO2NSVTX4 port map( A => B(16), B => A(16), C => C(16), D => n57, Z
=> Y_17_port);
U210 : EOSVTX4 port map( A => C(16), B => n57, Z => Z(16));
U211 : EOSVTX4 port map( A => n37, B => C(34), Z => Z(34));
U212 : AO2NSVTX4 port map( A => B(11), B => A(11), C => n62, D => C(11), Z
=> Y_12_port);
U213 : EOSVTX8 port map( A => C(39), B => n32, Z => Z(39));
U214 : EOSVTX4 port map( A => n21, B => C(5), Z => Z(5));
U215 : ND2SVTX6 port map( A => n29, B => n72, Z => n73);
U216 : ND2SVTX6 port map( A => n73, B => n74, Z => Z(41));
U217 : IVHVTX0H port map( A => n29, Z => n71);
U218 : EOSVTX6 port map( A => B(41), B => A(41), Z => n29);
U219 : AO2NSVTX4 port map( A => B(36), B => A(36), C => C(36), D => n35, Z
=> Y_37_port);
U220 : AO2NSVTX4 port map( A => B(21), B => A(21), C => n51, D => C(21), Z
=> Y_22_port);
U221 : EOSVTX4 port map( A => C(6), B => n20, Z => Z(6));
U222 : AO2NSVTX4 port map( A => B(27), B => A(27), C => n45, D => C(27), Z
=> Y_28_port);
U223 : EOSVTX4 port map( A => C(27), B => n45, Z => Z(27));
U224 : AO2NSVTX2 port map( A => B(39), B => A(39), C => C(39), D => n32, Z
=> Y_40_port);
U225 : AO2NSVTX6 port map( A => B(33), B => A(33), C => C(33), D => n38, Z
=> Y_34_port);
U226 : EOSVTX4 port map( A => C(23), B => n49, Z => Z(23));
U227 : AO2NSVTX6 port map( A => B(23), B => A(23), C => C(23), D => n49, Z
=> Y_24_port);
U228 : AO2NSVTX6 port map( A => B(37), B => A(37), C => C(37), D => n34, Z
=> Y_38_port);
U229 : IVSVTX0H port map( A => A(3), Z => n76);
U230 : EOSVTX4 port map( A => n28, B => C(42), Z => Z(42));
U231 : AO2NSVTX4 port map( A => B(42), B => A(42), C => n28, D => C(42), Z
=> Y_43_port);
U232 : AO2NSVTX6 port map( A => B(14), B => A(14), C => n70, D => n59, Z =>
Y_15_port);
U233 : EOSVTX4 port map( A => n18, B => C(8), Z => Z(8));
U234 : EOSVTX2 port map( A => n30, B => C(40), Z => Z(40));
U235 : EOSVTX4 port map( A => C(17), B => n56, Z => Z(17));
U236 : EOSVTX4 port map( A => n38, B => C(33), Z => Z(33));
U237 : AO2NSVTX4 port map( A => B(18), B => A(18), C => n55, D => C(18), Z
=> Y_19_port);
U238 : EOSVTX4 port map( A => C(15), B => n58, Z => Z(15));
U239 : EOSVTX4 port map( A => n50, B => C(22), Z => Z(22));
U240 : AO2NSVTX4 port map( A => B(28), B => A(28), C => n44, D => C(28), Z
=> Y_29_port);
U241 : EOSVTX4 port map( A => n60, B => C(13), Z => Z(13));
U242 : EOSVTX4 port map( A => C(2), B => n42, Z => Z(2));
U243 : AO2NSVTX2 port map( A => B(2), B => A(2), C => n42, D => C(2), Z =>
Y_3_port);
U244 : IVSVTX12 port map( A => B(3), Z => n75);
U245 : AO2NSVTX4 port map( A => B(12), B => A(12), C => n61, D => C(12), Z
=> Y_13_port);
U246 : AO2NSVTX4 port map( A => B(30), B => A(30), C => n41, D => C(30), Z
=> Y_31_port);
U247 : AO2NSVTX2 port map( A => B(47), B => A(47), C => C(47), D => n23, Z
=> Cout);
U248 : EOSVTX4 port map( A => C(35), B => n36, Z => Z(35));
U249 : AO2NSVTX4 port map( A => B(44), B => A(44), C => n26, D => C(44), Z
=> Y_45_port);
U250 : EOSVTX4 port map( A => C(44), B => n26, Z => Z(44));
U251 : EOSVTX4 port map( A => C(12), B => n61, Z => Z(12));
U252 : AO2NSVTX4 port map( A => B(26), B => A(26), C => n46, D => C(26), Z
=> Y_27_port);
U253 : AO2NSVTX4 port map( A => B(19), B => A(19), C => n54, D => C(19), Z
=> Y_20_port);
U254 : EOSVTX4 port map( A => n23, B => C(47), Z => Z(47));
U255 : AO2NSVTX4 port map( A => B(1), B => A(1), C => n53, D => C(1), Z =>
Y_2_port);
U256 : AO2NSVTX4 port map( A => B(0), B => A(0), C => n64, D => C(0), Z =>
Y_1_port);
U257 : EOSVTX2 port map( A => n39, B => C(32), Z => Z(32));
U258 : EOSVTX2 port map( A => n41, B => C(30), Z => Z(30));
U259 : EOSVTX2 port map( A => C(0), B => n64, Z => Z(0));
U260 : EOSVTX2 port map( A => C(1), B => n53, Z => Z(1));
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity gl_dualreg_ld_n10 is
port( AS, AC : in std_logic_vector (10 downto 0); RESET, CLOCK, LOAD : in
std_logic; ZS, ZC : out std_logic_vector (10 downto 0));
end gl_dualreg_ld_n10;
architecture SYN_BEHAVIORAL of gl_dualreg_ld_n10 is
component FD2QSVTX2
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component IVHVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component BFSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX1
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component BFHVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX4
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component AO4ASVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
signal ZS_10_port, ZS_9_port, ZS_8_port, ZS_7_port, ZS_6_port, ZS_5_port,
n175, ZS_3_port, ZS_2_port, ZS_1_port, ZS_0_port, ZC_10_port, ZC_9_port,
ZC_8_port, ZC_7_port, ZC_6_port, ZC_5_port, ZC_4_port, ZC_3_port,
ZC_2_port, ZC_1_port, ZC_0_port, n127, n128, n129, n130, n131, n132, n133
, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, ZS_4_port, n160, n161, n162, n163, n164, n165, n166, n167, n168,
n169, n170, n171, n172, n173, n174 : std_logic;
begin
ZS <= ( ZS_10_port, ZS_9_port, ZS_8_port, ZS_7_port, ZS_6_port, ZS_5_port,
ZS_4_port, ZS_3_port, ZS_2_port, ZS_1_port, ZS_0_port );
ZC <= ( ZC_10_port, ZC_9_port, ZC_8_port, ZC_7_port, ZC_6_port, ZC_5_port,
ZC_4_port, ZC_3_port, ZC_2_port, ZC_1_port, ZC_0_port );
ZS_reg_10_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n128, Q
=> ZS_10_port);
ZS_reg_9_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n129, Q
=> ZS_9_port);
ZS_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n130, Q
=> ZS_8_port);
ZS_reg_7_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n131, Q
=> ZS_7_port);
ZS_reg_6_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n132, Q
=> ZS_6_port);
ZS_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n135, Q
=> ZS_3_port);
ZS_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n136, Q
=> ZS_2_port);
ZS_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n137, Q
=> ZS_1_port);
ZS_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n138, Q
=> ZS_0_port);
ZC_reg_10_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n139, Q
=> ZC_10_port);
ZC_reg_9_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n140, Q
=> ZC_9_port);
ZC_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n141, Q
=> ZC_8_port);
ZC_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n146, Q
=> ZC_3_port);
ZC_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n147, Q
=> ZC_2_port);
ZC_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n148, Q
=> ZC_1_port);
ZC_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n149, Q
=> ZC_0_port);
U93 : AO4ABSVTX2 port map( A => ZC_8_port, B => n127, C => n163, D => n164,
Z => n141);
U94 : IVSVTX2 port map( A => AC(8), Z => n163);
U95 : AO4ABSVTX4 port map( A => ZC_10_port, B => n127, C => n167, D => n172,
Z => n139);
U96 : IVSVTX4 port map( A => AC(10), Z => n167);
U97 : IVSVTX2 port map( A => AC(9), Z => n165);
U98 : IVSVTX4 port map( A => AS(9), Z => n162);
U99 : IVHVTX4 port map( A => LOAD, Z => n127);
U100 : BFSVTX4 port map( A => LOAD, Z => n150);
U101 : AO4ABSVTX4 port map( A => ZC_1_port, B => n127, C => n155, D => n156,
Z => n148);
U102 : IVSVTX4 port map( A => AC(1), Z => n155);
U103 : AO2NSVTX4 port map( A => ZC_6_port, B => n127, C => AC(6), D => LOAD,
Z => n143);
U104 : IVSVTX4 port map( A => n158, Z => ZS_4_port);
U105 : AO2NSVTX2 port map( A => ZS_6_port, B => n127, C => AS(6), D => n150,
Z => n132);
U106 : AO2NSVTX6 port map( A => ZS_10_port, B => n127, C => AS(10), D =>
n150, Z => n128);
U107 : AO4ASVTX8 port map( A => AS(5), B => n153, C => n151, D => n152, Z =>
n133);
U108 : IVSVTX12 port map( A => n161, Z => n151);
U109 : IVSVTX12 port map( A => n127, Z => n152);
U110 : IVSVTX12 port map( A => n150, Z => n153);
U111 : AO4ABSVTX6 port map( A => ZC_0_port, B => n127, C => n154, D => n156,
Z => n149);
U112 : IVSVTX12 port map( A => AC(0), Z => n154);
U113 : IVSVTX8 port map( A => n150, Z => n156);
U114 : AO2NSVTX6 port map( A => ZS_8_port, B => n127, C => AS(8), D => n150,
Z => n130);
U115 : IVSVTX2 port map( A => n175, Z => n158);
ZC_reg_4_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n145, Q
=> ZC_4_port);
U116 : AO2NSVTX8 port map( A => n157, B => n127, C => AS(4), D => n150, Z =>
n134);
ZS_reg_4_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n134, Q
=> n175);
U117 : BFHVTX1 port map( A => ZS_4_port, Z => n157);
ZC_reg_5_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n144, Q
=> ZC_5_port);
U118 : IVHVTX0H port map( A => ZS_5_port, Z => n160);
U119 : IVSVTX0H port map( A => n160, Z => n161);
ZS_reg_5_inst : FD2QSVTX1 port map( CD => RESET, CP => CLOCK, D => n133, Q
=> ZS_5_port);
U120 : AO4ABSVTX6 port map( A => ZS_9_port, B => n127, C => n162, D => n164,
Z => n129);
U121 : IVSVTX8 port map( A => n150, Z => n164);
U122 : AO4ABSVTX6 port map( A => ZC_9_port, B => n127, C => n165, D => n166,
Z => n140);
U123 : IVSVTX12 port map( A => n150, Z => n166);
ZC_reg_6_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n143, Q
=> ZC_6_port);
U124 : AO4ABSVTX6 port map( A => ZS_0_port, B => n127, C => n168, D => n172,
Z => n138);
U125 : IVSVTX12 port map( A => AS(0), Z => n168);
U126 : IVSVTX8 port map( A => n150, Z => n172);
U127 : AO2NSVTX6 port map( A => ZS_2_port, B => n127, C => AS(2), D => n150,
Z => n136);
U128 : AO2NSVTX6 port map( A => ZS_3_port, B => n127, C => AS(3), D => n150,
Z => n135);
U129 : AO2NSVTX2 port map( A => n169, B => n127, C => AC(4), D => n150, Z =>
n145);
U130 : BFHVTX1 port map( A => ZC_4_port, Z => n169);
U131 : AO2NSVTX6 port map( A => ZS_1_port, B => n127, C => AS(1), D => n150,
Z => n137);
U132 : AO2NSVTX6 port map( A => ZS_7_port, B => n127, C => AS(7), D => n150,
Z => n131);
U133 : AO4ASVTX6 port map( A => AC(7), B => n172, C => n170, D => n171, Z =>
n142);
U134 : IVSVTX12 port map( A => ZC_7_port, Z => n170);
U135 : IVSVTX12 port map( A => n127, Z => n171);
U136 : AO2NSVTX8 port map( A => n174, B => n127, C => AC(5), D => n150, Z =>
n144);
ZC_reg_7_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n142, Q
=> ZC_7_port);
U137 : AO2NSVTX6 port map( A => ZC_2_port, B => n127, C => AC(2), D => n150,
Z => n147);
U138 : IVHVTX0H port map( A => ZC_5_port, Z => n173);
U139 : IVSVTX0H port map( A => n173, Z => n174);
U140 : AO2NSVTX2 port map( A => ZC_3_port, B => n127, C => AC(3), D => n150,
Z => n146);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity gl_dualreg_ld_n45 is
port( AS, AC : in std_logic_vector (45 downto 0); RESET, CLOCK, LOAD : in
std_logic; ZS, ZC : out std_logic_vector (45 downto 0));
end gl_dualreg_ld_n45;
architecture SYN_BEHAVIORAL of gl_dualreg_ld_n45 is
component AO2NHVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX2
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ABSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component IVHVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component AO2SVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component FD2QNSVTX1
port( CD, CP, D : in std_logic; QN : out std_logic);
end component;
component FD2QNSVTX2
port( CD, CP, D : in std_logic; QN : out std_logic);
end component;
component AO2NSVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO4ASVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component FD2QSVTX4
port( CD, CP, D : in std_logic; Q : out std_logic);
end component;
component AO2NSVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2ASVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2NSVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
signal ZS_45_port, ZS_44_port, ZS_43_port, ZS_42_port, ZS_41_port,
ZS_40_port, ZS_39_port, ZS_37_port, ZS_36_port, ZS_35_port, ZS_34_port,
ZS_33_port, ZS_32_port, ZS_31_port, ZS_30_port, ZS_29_port, ZS_28_port,
ZS_27_port, ZS_25_port, ZS_24_port, ZS_23_port, ZS_21_port, ZS_20_port,
ZS_19_port, ZS_18_port, ZS_17_port, ZS_16_port, ZS_15_port, ZS_14_port,
ZS_13_port, ZS_12_port, ZS_11_port, ZS_10_port, ZS_9_port, ZS_8_port,
ZS_7_port, ZS_6_port, ZS_5_port, ZS_4_port, ZS_3_port, ZS_2_port,
ZS_1_port, ZS_0_port, ZC_45_port, ZC_44_port, ZC_43_port, ZC_42_port,
ZC_41_port, ZC_40_port, ZC_39_port, ZC_38_port, ZC_37_port, ZC_36_port,
ZC_35_port, ZC_34_port, ZC_33_port, ZC_32_port, ZC_31_port, ZC_30_port,
ZC_29_port, ZC_28_port, ZC_27_port, ZC_26_port, ZC_25_port, ZC_24_port,
ZC_23_port, ZC_22_port, ZC_21_port, ZC_20_port, ZC_19_port, ZC_18_port,
ZC_17_port, ZC_16_port, ZC_15_port, ZC_14_port, ZC_13_port, ZC_12_port,
ZC_11_port, ZC_10_port, ZC_9_port, ZC_8_port, ZC_7_port, ZC_6_port,
ZC_5_port, ZC_4_port, ZC_3_port, ZC_2_port, ZC_1_port, ZC_0_port, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421,
n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433,
n434, ZS_26_port, n436, ZS_38_port, n438, n439, n440, n441, n442, n443,
n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455,
n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, ZS_22_port, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526,
n527, n528, n529, n530, n531, n532 : std_logic;
begin
ZS <= ( ZS_45_port, ZS_44_port, ZS_43_port, ZS_42_port, ZS_41_port,
ZS_40_port, ZS_39_port, ZS_38_port, ZS_37_port, ZS_36_port, ZS_35_port,
ZS_34_port, ZS_33_port, ZS_32_port, ZS_31_port, ZS_30_port, ZS_29_port,
ZS_28_port, ZS_27_port, ZS_26_port, ZS_25_port, ZS_24_port, ZS_23_port,
ZS_22_port, ZS_21_port, ZS_20_port, ZS_19_port, ZS_18_port, ZS_17_port,
ZS_16_port, ZS_15_port, ZS_14_port, ZS_13_port, ZS_12_port, ZS_11_port,
ZS_10_port, ZS_9_port, ZS_8_port, ZS_7_port, ZS_6_port, ZS_5_port,
ZS_4_port, ZS_3_port, ZS_2_port, ZS_1_port, ZS_0_port );
ZC <= ( ZC_45_port, ZC_44_port, ZC_43_port, ZC_42_port, ZC_41_port,
ZC_40_port, ZC_39_port, ZC_38_port, ZC_37_port, ZC_36_port, ZC_35_port,
ZC_34_port, ZC_33_port, ZC_32_port, ZC_31_port, ZC_30_port, ZC_29_port,
ZC_28_port, ZC_27_port, ZC_26_port, ZC_25_port, ZC_24_port, ZC_23_port,
ZC_22_port, ZC_21_port, ZC_20_port, ZC_19_port, ZC_18_port, ZC_17_port,
ZC_16_port, ZC_15_port, ZC_14_port, ZC_13_port, ZC_12_port, ZC_11_port,
ZC_10_port, ZC_9_port, ZC_8_port, ZC_7_port, ZC_6_port, ZC_5_port,
ZC_4_port, ZC_3_port, ZC_2_port, ZC_1_port, ZC_0_port );
U300 : AO2NHVTX1 port map( A => ZC_0_port, B => n337, C => AC(0), D => LOAD,
Z => n429);
ZS_reg_45_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n338, Q
=> ZS_45_port);
ZS_reg_44_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n339, Q
=> ZS_44_port);
ZS_reg_43_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n340, Q
=> ZS_43_port);
ZS_reg_42_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n341, Q
=> ZS_42_port);
ZS_reg_41_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n342, Q
=> ZS_41_port);
ZS_reg_40_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n343, Q
=> ZS_40_port);
ZS_reg_39_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n344, Q
=> ZS_39_port);
ZS_reg_37_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n346, Q
=> ZS_37_port);
ZS_reg_36_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n347, Q
=> ZS_36_port);
ZS_reg_35_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n348, Q
=> ZS_35_port);
ZS_reg_34_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n349, Q
=> ZS_34_port);
ZS_reg_33_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n350, Q
=> ZS_33_port);
ZS_reg_32_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n351, Q
=> ZS_32_port);
ZS_reg_31_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n352, Q
=> ZS_31_port);
ZS_reg_30_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n353, Q
=> ZS_30_port);
ZS_reg_29_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n354, Q
=> ZS_29_port);
ZS_reg_28_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n355, Q
=> ZS_28_port);
ZS_reg_27_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n356, Q
=> ZS_27_port);
ZS_reg_25_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n358, Q
=> ZS_25_port);
ZS_reg_23_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n360, Q
=> ZS_23_port);
ZS_reg_21_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n362, Q
=> ZS_21_port);
ZS_reg_20_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n363, Q
=> ZS_20_port);
ZS_reg_19_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n364, Q
=> ZS_19_port);
ZS_reg_18_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n365, Q
=> ZS_18_port);
ZS_reg_17_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n366, Q
=> ZS_17_port);
ZS_reg_16_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n367, Q
=> ZS_16_port);
ZS_reg_15_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n368, Q
=> ZS_15_port);
ZS_reg_14_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n369, Q
=> ZS_14_port);
ZS_reg_13_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n370, Q
=> ZS_13_port);
ZS_reg_12_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n371, Q
=> ZS_12_port);
ZS_reg_11_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n372, Q
=> ZS_11_port);
ZS_reg_10_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n373, Q
=> ZS_10_port);
ZS_reg_9_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n374, Q
=> ZS_9_port);
ZS_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n375, Q
=> ZS_8_port);
ZS_reg_7_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n376, Q
=> ZS_7_port);
ZS_reg_6_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n377, Q
=> ZS_6_port);
ZS_reg_5_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n378, Q
=> ZS_5_port);
ZS_reg_4_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n379, Q
=> ZS_4_port);
ZS_reg_3_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n380, Q
=> ZS_3_port);
ZS_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n381, Q
=> ZS_2_port);
ZS_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n382, Q
=> ZS_1_port);
ZS_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n383, Q
=> ZS_0_port);
ZC_reg_45_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n384, Q
=> ZC_45_port);
ZC_reg_41_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n388, Q
=> ZC_41_port);
ZC_reg_39_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n390, Q
=> ZC_39_port);
ZC_reg_37_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n392, Q
=> ZC_37_port);
ZC_reg_36_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n393, Q
=> ZC_36_port);
ZC_reg_34_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n395, Q
=> ZC_34_port);
ZC_reg_32_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n397, Q
=> ZC_32_port);
ZC_reg_29_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n400, Q
=> ZC_29_port);
ZC_reg_27_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n402, Q
=> ZC_27_port);
ZC_reg_26_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n403, Q
=> ZC_26_port);
ZC_reg_21_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n408, Q
=> ZC_21_port);
ZC_reg_20_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n409, Q
=> ZC_20_port);
ZC_reg_19_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n410, Q
=> ZC_19_port);
ZC_reg_18_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n411, Q
=> ZC_18_port);
ZC_reg_17_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n412, Q
=> ZC_17_port);
ZC_reg_15_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n414, Q
=> ZC_15_port);
ZC_reg_14_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n415, Q
=> ZC_14_port);
ZC_reg_13_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n416, Q
=> ZC_13_port);
ZC_reg_11_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n418, Q
=> ZC_11_port);
ZC_reg_10_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n419, Q
=> ZC_10_port);
ZC_reg_8_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n421, Q
=> ZC_8_port);
ZC_reg_2_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n427, Q
=> ZC_2_port);
ZC_reg_1_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n428, Q
=> ZC_1_port);
ZC_reg_0_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n429, Q
=> ZC_0_port);
U303 : AO4ABSVTX2 port map( A => ZC_37_port, B => n337, C => n463, D => n464
, Z => n392);
U304 : IVSVTX2 port map( A => AC(37), Z => n463);
U305 : AO4ABSVTX2 port map( A => ZC_13_port, B => n337, C => n430, D => n460
, Z => n416);
U306 : IVSVTX12 port map( A => AC(13), Z => n430);
U307 : IVSVTX8 port map( A => n511, Z => n460);
U308 : AO4ASVTX4 port map( A => AS(40), B => n467, C => n465, D => n480, Z
=> n343);
U309 : AO4ABSVTX2 port map( A => ZS_11_port, B => n337, C => n431, D => n433
, Z => n372);
U310 : IVSVTX12 port map( A => AS(11), Z => n431);
U311 : AO4ABSVTX2 port map( A => ZS_22_port, B => n337, C => n503, D => n504
, Z => n361);
U312 : AO4ABSVTX6 port map( A => ZC_15_port, B => n522, C => n438, D => n525
, Z => n414);
U313 : AO4ABSVTX4 port map( A => ZC_38_port, B => n337, C => n492, D => n520
, Z => n391);
U314 : IVSVTX4 port map( A => AC(38), Z => n492);
U315 : AO4ABSVTX2 port map( A => ZS_34_port, B => n337, C => n440, D => n508
, Z => n349);
U316 : IVSVTX2 port map( A => AS(34), Z => n440);
U317 : AO2NSVTX6 port map( A => ZC_12_port, B => n337, C => AC(12), D =>
LOAD, Z => n417);
U318 : AO4ABSVTX2 port map( A => ZC_16_port, B => n464, C => n452, D => n532
, Z => n413);
U319 : IVSVTX2 port map( A => AC(16), Z => n452);
U320 : AO4ABSVTX2 port map( A => ZC_42_port, B => n337, C => n521, D => n522
, Z => n387);
U321 : IVSVTX4 port map( A => AC(42), Z => n521);
U322 : AO4ABSVTX2 port map( A => ZC_19_port, B => n337, C => n462, D => n464
, Z => n410);
U323 : IVSVTX2 port map( A => AC(19), Z => n462);
U324 : AO2NSVTX6 port map( A => AS(23), B => LOAD, C => ZS_23_port, D =>
n337, Z => n360);
U325 : IVSVTX6 port map( A => AS(10), Z => n449);
U326 : AO4ABSVTX4 port map( A => ZC_11_port, B => n337, C => n450, D => n451
, Z => n418);
U327 : IVSVTX4 port map( A => AC(11), Z => n450);
U328 : AO4ASVTX6 port map( A => AC(9), B => n476, C => n472, D => n480, Z =>
n420);
U329 : IVSVTX0H port map( A => LOAD, Z => n433);
U330 : IVSVTX0H port map( A => LOAD, Z => n446);
U331 : IVSVTX0H port map( A => LOAD, Z => n469);
U332 : IVSVTX0H port map( A => LOAD, Z => n518);
U333 : IVSVTX0H port map( A => LOAD, Z => n500);
U334 : IVSVTX0H port map( A => LOAD, Z => n510);
U335 : IVSVTX0H port map( A => LOAD, Z => n502);
U336 : IVSVTX0H port map( A => LOAD, Z => n467);
U337 : IVSVTX0H port map( A => LOAD, Z => n504);
U338 : IVSVTX0H port map( A => LOAD, Z => n451);
U339 : IVSVTX0H port map( A => LOAD, Z => n508);
U340 : IVSVTX0H port map( A => LOAD, Z => n520);
U341 : IVSVTX0H port map( A => LOAD, Z => n448);
U342 : IVSVTX0H port map( A => LOAD, Z => n464);
U343 : IVSVTX0H port map( A => LOAD, Z => n474);
U344 : IVSVTX0H port map( A => LOAD, Z => n476);
U345 : IVSVTX0H port map( A => LOAD, Z => n506);
U346 : IVSVTX0H port map( A => LOAD, Z => n484);
U347 : IVSVTX0H port map( A => LOAD, Z => n522);
U348 : IVSVTX0H port map( A => LOAD, Z => n532);
U349 : IVSVTX0H port map( A => LOAD, Z => n516);
U350 : IVSVTX2 port map( A => LOAD, Z => n525);
U351 : AO4ABSVTX4 port map( A => ZC_6_port, B => n337, C => n432, D => n433,
Z => n423);
U352 : IVSVTX12 port map( A => AC(6), Z => n432);
U353 : IVSVTX2 port map( A => n337, Z => n531);
U354 : IVSVTX2 port map( A => n337, Z => n529);
U355 : IVSVTX2 port map( A => n337, Z => n527);
U356 : IVSVTX2 port map( A => n337, Z => n515);
U357 : IVHVTX8 port map( A => LOAD, Z => n337);
U358 : AO4ABSVTX2 port map( A => ZS_15_port, B => n337, C => n456, D => n504
, Z => n368);
U359 : IVSVTX4 port map( A => AS(15), Z => n456);
U360 : IVSVTX2 port map( A => n479, Z => n402);
U361 : AO2SVTX4 port map( A => AC(27), B => n480, C => n481, D => n482, Z =>
n479);
ZS_reg_26_inst : FD2QNSVTX1 port map( CD => RESET, CP => CLOCK, D => n357,
QN => n434);
U362 : IVSVTX0H port map( A => n434, Z => ZS_26_port);
ZS_reg_38_inst : FD2QNSVTX2 port map( CD => RESET, CP => CLOCK, D => n345,
QN => n436);
U363 : IVSVTX0H port map( A => n436, Z => ZS_38_port);
U364 : IVSVTX12 port map( A => AC(15), Z => n438);
U365 : AO4ABSVTX4 port map( A => ZS_45_port, B => n337, C => n439, D => n451
, Z => n338);
U366 : IVSVTX12 port map( A => AS(45), Z => n439);
U367 : AO4ABSVTX2 port map( A => ZS_3_port, B => n337, C => n441, D => n448,
Z => n380);
U368 : IVSVTX12 port map( A => AS(3), Z => n441);
ZC_reg_12_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n417, Q
=> ZC_12_port);
U369 : AO4ABSVTX2 port map( A => ZC_36_port, B => n337, C => n442, D => n469
, Z => n393);
U370 : IVSVTX12 port map( A => AC(36), Z => n442);
U371 : AO2NSVTX4 port map( A => ZS_42_port, B => n337, C => AS(42), D =>
LOAD, Z => n341);
U372 : AO2NSVTX6 port map( A => ZC_8_port, B => n337, C => AC(8), D => LOAD,
Z => n421);
ZC_reg_24_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n405, Q
=> ZC_24_port);
ZC_reg_42_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n387, Q
=> ZC_42_port);
U373 : AO2NSVTX4 port map( A => AS(32), B => n458, C => n443, D => n444, Z
=> n351);
U374 : IVSVTX12 port map( A => n468, Z => n443);
U375 : IVSVTX12 port map( A => n480, Z => n444);
U376 : AO2NSVTX6 port map( A => ZS_4_port, B => n337, C => AS(4), D => LOAD,
Z => n379);
U377 : IVSVTX4 port map( A => AS(35), Z => n466);
U378 : IVSVTX4 port map( A => AS(41), Z => n501);
U379 : AO4ABSVTX6 port map( A => ZC_5_port, B => n337, C => n445, D => n446,
Z => n424);
U380 : IVSVTX12 port map( A => AC(5), Z => n445);
ZC_reg_44_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n385, Q
=> ZC_44_port);
U381 : AO2NSVTX4 port map( A => ZC_44_port, B => n337, C => AC(44), D =>
LOAD, Z => n385);
U382 : AO2NSVTX6 port map( A => ZS_43_port, B => n337, C => AS(43), D =>
LOAD, Z => n340);
U383 : AO4ASVTX8 port map( A => AC(4), B => n448, C => n447, D => n458, Z =>
n425);
U384 : IVSVTX12 port map( A => ZC_4_port, Z => n447);
U385 : IVSVTX8 port map( A => n516, Z => n458);
U386 : AO4ABSVTX6 port map( A => ZS_10_port, B => n337, C => n449, D => n451
, Z => n373);
ZC_reg_16_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n413, Q
=> ZC_16_port);
U387 : AO2NSVTX6 port map( A => ZS_16_port, B => n337, C => AS(16), D =>
LOAD, Z => n367);
ZC_reg_33_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n396, Q
=> ZC_33_port);
U388 : AO4ASVTX4 port map( A => AC(30), B => n506, C => n490, D => n511, Z
=> n399);
U389 : IVSVTX4 port map( A => AS(6), Z => n495);
U390 : AO4ABSVTX6 port map( A => n454, B => n455, C => n453, D => n522, Z =>
n401);
U391 : IVSVTX12 port map( A => AC(28), Z => n453);
U392 : IVSVTX12 port map( A => n470, Z => n454);
U393 : IVSVTX12 port map( A => n480, Z => n455);
ZC_reg_28_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n401, Q
=> ZC_28_port);
U394 : AO2NSVTX6 port map( A => ZS_7_port, B => n337, C => AS(7), D => LOAD,
Z => n376);
U395 : AO4ABSVTX6 port map( A => ZC_43_port, B => n337, C => n457, D => n469
, Z => n386);
U396 : IVSVTX12 port map( A => AC(43), Z => n457);
U397 : AO2NSVTX4 port map( A => AS(29), B => n458, C => n459, D => n460, Z
=> n354);
U398 : IVSVTX12 port map( A => n485, Z => n459);
U399 : AO2NSVTX6 port map( A => ZS_37_port, B => n337, C => AS(37), D =>
LOAD, Z => n346);
U400 : AO2NSVTX2 port map( A => ZS_1_port, B => n337, C => AS(1), D => LOAD,
Z => n382);
U401 : IVSVTX4 port map( A => AS(27), Z => n488);
U402 : AO4ABSVTX6 port map( A => ZC_35_port, B => n337, C => n461, D => n474
, Z => n394);
U403 : IVSVTX12 port map( A => AC(35), Z => n461);
ZC_reg_6_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n423, Q
=> ZC_6_port);
U404 : IVSVTX6 port map( A => AS(38), Z => n505);
ZC_reg_40_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n389, Q
=> ZC_40_port);
U405 : AO2NSVTX6 port map( A => ZC_40_port, B => n337, C => AC(40), D =>
LOAD, Z => n389);
U406 : IVSVTX12 port map( A => ZS_40_port, Z => n465);
U407 : AO4ABSVTX6 port map( A => ZS_35_port, B => n337, C => n466, D => n467
, Z => n348);
U408 : IVSVTX12 port map( A => ZS_32_port, Z => n468);
U409 : IVSVTX12 port map( A => ZC_28_port, Z => n470);
U410 : AO4ABSVTX6 port map( A => ZS_17_port, B => n337, C => n471, D => n484
, Z => n366);
U411 : IVSVTX12 port map( A => AS(17), Z => n471);
U412 : IVSVTX12 port map( A => ZC_9_port, Z => n472);
U413 : AO4ASVTX8 port map( A => AC(18), B => n474, C => n473, D => n480, Z
=> n411);
U414 : IVSVTX12 port map( A => ZC_18_port, Z => n473);
U415 : AO4ABSVTX6 port map( A => ZS_8_port, B => n337, C => n475, D => n476,
Z => n375);
U416 : IVSVTX12 port map( A => AS(8), Z => n475);
U417 : AO2NSVTX4 port map( A => AS(18), B => n480, C => n477, D => n478, Z
=> n365);
U418 : IVSVTX12 port map( A => n528, Z => n477);
U419 : IVSVTX12 port map( A => n529, Z => n478);
U420 : IVSVTX8 port map( A => n516, Z => n480);
U421 : IVSVTX12 port map( A => n514, Z => n481);
U422 : IVSVTX12 port map( A => n515, Z => n482);
U423 : AO4ASVTX8 port map( A => AC(33), B => n484, C => n483, D => n511, Z
=> n396);
U424 : IVSVTX12 port map( A => ZC_33_port, Z => n483);
U425 : IVSVTX12 port map( A => ZS_29_port, Z => n485);
ZS_reg_22_inst : FD2QNSVTX1 port map( CD => RESET, CP => CLOCK, D => n361,
QN => n486);
U426 : IVSVTX0H port map( A => n486, Z => ZS_22_port);
U427 : AO4ABSVTX6 port map( A => ZS_27_port, B => n337, C => n488, D => n510
, Z => n356);
U428 : AO4ABSVTX6 port map( A => ZS_13_port, B => n337, C => n489, D => n508
, Z => n370);
U429 : IVSVTX12 port map( A => AS(13), Z => n489);
U430 : AO2NSVTX6 port map( A => ZC_26_port, B => n337, C => AC(26), D =>
LOAD, Z => n403);
U431 : IVSVTX12 port map( A => ZC_30_port, Z => n490);
ZC_reg_5_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n424, Q
=> ZC_5_port);
U432 : AO4ASVTX8 port map( A => AS(36), B => n500, C => n491, D => n511, Z
=> n347);
U433 : IVSVTX12 port map( A => ZS_36_port, Z => n491);
U434 : IVSVTX4 port map( A => AS(26), Z => n519);
U435 : AO4ASVTX8 port map( A => AS(25), B => n502, C => n493, D => n511, Z
=> n358);
U436 : IVSVTX12 port map( A => ZS_25_port, Z => n493);
U437 : AO2ASVTX6 port map( A => n532, B => AC(22), C => n497, D => n498, Z
=> n496);
ZS_reg_24_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n359, Q
=> ZS_24_port);
U438 : AO2NSVTX6 port map( A => ZC_21_port, B => n337, C => AC(21), D =>
LOAD, Z => n408);
U439 : AO4ABSVTX6 port map( A => ZC_23_port, B => n518, C => n494, D => n525
, Z => n406);
U440 : IVSVTX12 port map( A => AC(23), Z => n494);
U441 : IVSVTX4 port map( A => AS(22), Z => n503);
U442 : AO2NSVTX6 port map( A => ZC_31_port, B => n337, C => AC(31), D =>
LOAD, Z => n398);
U443 : AO4ABSVTX6 port map( A => ZS_6_port, B => n337, C => n495, D => n504,
Z => n377);
U444 : IVSVTX6 port map( A => AS(21), Z => n517);
U445 : IVSVTX4 port map( A => n496, Z => n407);
ZC_reg_23_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n406, Q
=> ZC_23_port);
U446 : IVSVTX12 port map( A => n530, Z => n497);
U447 : IVSVTX12 port map( A => n531, Z => n498);
U448 : AO2NSVTX6 port map( A => ZS_39_port, B => n337, C => AS(39), D =>
LOAD, Z => n344);
U449 : AO4ABSVTX6 port map( A => ZC_39_port, B => n337, C => n499, D => n500
, Z => n390);
U450 : IVSVTX12 port map( A => AC(39), Z => n499);
ZC_reg_43_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n386, Q
=> ZC_43_port);
U451 : AO4ABSVTX6 port map( A => ZS_41_port, B => n337, C => n501, D => n502
, Z => n342);
U452 : AO2NSVTX6 port map( A => ZS_12_port, B => n337, C => AS(12), D =>
LOAD, Z => n371);
ZC_reg_7_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n422, Q
=> ZC_7_port);
U453 : AO2NSVTX8 port map( A => ZC_7_port, B => n337, C => AC(7), D => LOAD,
Z => n422);
U454 : AO2NSVTX8 port map( A => ZC_32_port, B => n337, C => AC(32), D =>
LOAD, Z => n397);
U455 : AO4ABSVTX6 port map( A => ZS_38_port, B => n337, C => n505, D => n506
, Z => n345);
U456 : AO4ABSVTX6 port map( A => ZC_29_port, B => n337, C => n507, D => n508
, Z => n400);
U457 : IVSVTX12 port map( A => AC(29), Z => n507);
U458 : AO4ASVTX8 port map( A => AS(28), B => n510, C => n509, D => n511, Z
=> n355);
U459 : IVSVTX12 port map( A => ZS_28_port, Z => n509);
U460 : IVSVTX8 port map( A => n525, Z => n511);
U461 : AO2NSVTX4 port map( A => AS(20), B => n511, C => n512, D => n513, Z
=> n363);
U462 : IVSVTX12 port map( A => n523, Z => n512);
U463 : IVSVTX12 port map( A => n527, Z => n513);
U464 : AO2NSVTX6 port map( A => ZS_0_port, B => n337, C => AS(0), D => LOAD,
Z => n383);
U465 : IVSVTX12 port map( A => ZC_27_port, Z => n514);
U466 : AO4ABSVTX6 port map( A => ZS_21_port, B => n337, C => n517, D => n518
, Z => n362);
U467 : AO4ABSVTX6 port map( A => ZS_26_port, B => n337, C => n519, D => n520
, Z => n357);
U468 : IVSVTX12 port map( A => ZS_20_port, Z => n523);
ZC_reg_22_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n407, Q
=> ZC_22_port);
U469 : AO2NSVTX8 port map( A => ZC_14_port, B => n337, C => AC(14), D =>
LOAD, Z => n415);
U470 : AO2NSVTX2 port map( A => ZS_31_port, B => n337, C => AS(31), D =>
LOAD, Z => n352);
U471 : AO2NSVTX4 port map( A => ZC_45_port, B => n337, C => AC(45), D =>
LOAD, Z => n384);
U472 : AO2NSVTX6 port map( A => ZS_14_port, B => n337, C => AS(14), D =>
LOAD, Z => n369);
U473 : AO2NSVTX4 port map( A => ZS_44_port, B => n337, C => AS(44), D =>
LOAD, Z => n339);
U474 : AO2NSVTX2 port map( A => ZS_19_port, B => n337, C => AS(19), D =>
LOAD, Z => n364);
U475 : AO2NSVTX6 port map( A => ZS_24_port, B => n337, C => AS(24), D =>
LOAD, Z => n359);
U476 : AO2NSVTX6 port map( A => ZC_24_port, B => n337, C => AC(24), D =>
LOAD, Z => n405);
U477 : AO2NSVTX6 port map( A => ZS_33_port, B => n337, C => AS(33), D =>
LOAD, Z => n350);
U478 : AO4ASVTX8 port map( A => AC(34), B => n525, C => n524, D => n529, Z
=> n395);
U479 : IVSVTX12 port map( A => ZC_34_port, Z => n524);
ZC_reg_25_inst : FD2QSVTX2 port map( CD => RESET, CP => CLOCK, D => n404, Q
=> ZC_25_port);
U480 : AO2NSVTX6 port map( A => ZC_25_port, B => n337, C => AC(25), D =>
LOAD, Z => n404);
ZC_reg_4_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n425, Q
=> ZC_4_port);
U481 : AO4ASVTX8 port map( A => AS(30), B => n532, C => n526, D => n527, Z
=> n353);
U482 : IVSVTX12 port map( A => ZS_30_port, Z => n526);
ZC_reg_38_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n391, Q
=> ZC_38_port);
U483 : AO2NSVTX6 port map( A => ZS_9_port, B => n337, C => AS(9), D => LOAD,
Z => n374);
U484 : AO2NSVTX2 port map( A => ZS_2_port, B => n337, C => AS(2), D => LOAD,
Z => n381);
U485 : AO2NSVTX2 port map( A => ZC_2_port, B => n337, C => AC(2), D => LOAD,
Z => n427);
U486 : AO2NSVTX2 port map( A => ZC_10_port, B => n337, C => AC(10), D =>
LOAD, Z => n419);
U487 : AO2NSVTX6 port map( A => ZS_5_port, B => n337, C => AS(5), D => LOAD,
Z => n378);
ZC_reg_3_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n426, Q
=> ZC_3_port);
U488 : AO2NSVTX6 port map( A => ZC_3_port, B => n337, C => AC(3), D => LOAD,
Z => n426);
U489 : AO2NSVTX8 port map( A => ZC_1_port, B => n337, C => AC(1), D => LOAD,
Z => n428);
U490 : IVSVTX12 port map( A => ZS_18_port, Z => n528);
U491 : IVSVTX12 port map( A => ZC_22_port, Z => n530);
U492 : AO2NSVTX2 port map( A => ZC_41_port, B => n337, C => AC(41), D =>
LOAD, Z => n388);
ZC_reg_35_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n394, Q
=> ZC_35_port);
ZC_reg_31_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n398, Q
=> ZC_31_port);
ZC_reg_30_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n399, Q
=> ZC_30_port);
U493 : AO2NSVTX2 port map( A => ZC_20_port, B => n337, C => AC(20), D =>
LOAD, Z => n409);
U494 : AO2NSVTX2 port map( A => ZC_17_port, B => n337, C => AC(17), D =>
LOAD, Z => n412);
ZC_reg_9_inst : FD2QSVTX4 port map( CD => RESET, CP => CLOCK, D => n420, Q
=> ZC_9_port);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity QDS_TABLE is
port( D : in std_logic_vector (2 downto 0); Y : in std_logic_vector (6
downto 0); M1, M2, P1, P2 : out std_logic);
end QDS_TABLE;
architecture SYN_BEHAVIORAL of QDS_TABLE is
component AO7HVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component NR2HVTX1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO8SVTX4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVHVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component NR3ASVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO7SVTX1
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component AO7SVTX2
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO6SVTX2
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO7SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO20SVTX1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO17SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO35SVTX2
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component NR2ASVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR4SVTX8
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO9SVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO52SVTX2
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component AO17ASVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO7SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO52SVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component NR2SVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN3ABCSVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO20SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IVSVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component AO1SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO9NSVTX4
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
component ENSVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND4SVTX2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO8SVTX6
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO9SVTX2
port( A, B, C, D, E : in std_logic; Z : out std_logic);
end component;
signal n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726,
n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736,
n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746,
n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756,
n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764 : std_logic;
begin
U807 : AO7HVTX1 port map( A => n3760, B => n3749, C => D(2), Z => n3748);
U825 : IVHVTX0H port map( A => n3739, Z => n3749);
U826 : NR2HVTX1 port map( A => D(0), B => D(1), Z => n3739);
U828 : IVHVTX0H port map( A => D(0), Z => n3744);
U829 : IVHVTX0H port map( A => D(1), Z => n3725);
U832 : IVHVTX2 port map( A => n3719, Z => n3762);
U833 : IVSVTX4 port map( A => n3732, Z => n3761);
U834 : IVSVTX2 port map( A => Y(4), Z => n3758);
U835 : IVSVTX2 port map( A => Y(4), Z => n3722);
U836 : NR3ASVTX8 port map( A => n3733, B => n3751, C => n3762, Z => M1);
U837 : AO7SVTX1 port map( A => D(1), B => n3759, C => D(2), Z => n3754);
U838 : IVSVTX4 port map( A => Y(1), Z => n3759);
U839 : AO7SVTX1 port map( A => n3725, B => n3726, C => n3727, Z => n3724);
U840 : IVSVTX6 port map( A => n3731, Z => n3726);
U841 : AO7SVTX2 port map( A => D(0), B => n3742, C => D(1), Z => n3756);
U842 : IVSVTX2 port map( A => n3761, Z => n3760);
U843 : AO6SVTX2 port map( A => n3731, B => D(1), C => D(2), Z => n3743);
U844 : AO7SVTX4 port map( A => Y(2), B => n3723, C => n3724, Z => n3721);
U845 : AO20SVTX1 port map( A => D(0), B => n3742, C => D(1), D => n3759, Z
=> n3750);
U846 : AO17SVTX2 port map( A => D(1), B => D(0), C => n3729, D => n3720, Z
=> n3747);
U847 : IVSVTX4 port map( A => Y(3), Z => n3720);
U848 : AO7SVTX2 port map( A => n3760, B => n3749, C => n3729, Z => n3757);
U849 : IVSVTX4 port map( A => Y(2), Z => n3729);
U850 : AO35SVTX2 port map( A => n3727, B => n3725, C => n3741, D => n3743, E
=> n3729, Z => n3735);
U851 : IVSVTX8 port map( A => Y(1), Z => n3732);
U852 : NR2ASVTX8 port map( A => n3759, B => D(0), Z => n3741);
U853 : NR4SVTX8 port map( A => D(2), B => D(1), C => Y(2), D => n3740, Z =>
n3737);
U854 : IVSVTX2 port map( A => n3722, Z => n3764);
U855 : AO9SVTX4 port map( A => n3752, B => D(2), C => n3764, D => n3758, E
=> n3753, Z => n3751);
U856 : AO52SVTX2 port map( A => n3761, B => n3739, C => n3756, D => n3727, E
=> Y(2), Z => n3755);
U857 : AO17ASVTX2 port map( A => n3726, B => D(2), C => n3728, D => D(1), Z
=> n3763);
U858 : IVSVTX2 port map( A => n3763, Z => n3723);
U859 : AO7SVTX8 port map( A => n3741, B => n3742, C => n3726, Z => n3740);
U860 : AO7SVTX4 port map( A => Y(3), B => n3737, C => n3738, Z => n3736);
U861 : AO52SVTX4 port map( A => n3739, B => n3760, C => n3727, D => n3729, E
=> Y(3), Z => n3738);
U862 : AO52SVTX2 port map( A => n3750, B => n3739, C => Y(3), D => n3727, E
=> Y(2), Z => n3745);
U863 : NR2SVTX8 port map( A => n3744, B => n3732, Z => n3731);
U864 : AN3ABCSVTX8 port map( A => n3733, B => n3719, C => n3734, Z => P1);
U865 : AO20SVTX2 port map( A => n3725, B => n3744, C => n3757, D => Y(3), Z
=> n3752);
U866 : IVSVTX1 port map( A => D(2), Z => n3727);
U867 : AO1SVTX2 port map( A => Y(0), B => n3728, C => D(1), D => n3731, Z =>
n3730);
U868 : IVSVTX8 port map( A => Y(6), Z => n3719);
U869 : AO9NSVTX4 port map( A => n3754, B => n3720, C => Y(2), D => n3755, E
=> Y(3), Z => n3753);
U870 : ENSVTX8 port map( A => n3759, B => D(0), Z => n3728);
U871 : AO8SVTX4 port map( A => n3745, B => n3733, C => n3746, D => Y(6), Z
=> M2);
U872 : ND4SVTX2 port map( A => n3729, B => n3720, C => n3727, D => n3730, Z
=> n3717);
U873 : IVSVTX4 port map( A => Y(5), Z => n3733);
U874 : AO8SVTX6 port map( A => Y(5), B => n3717, C => n3718, D => n3719, Z
=> P2);
U875 : AO7SVTX4 port map( A => n3720, B => n3721, C => n3758, Z => n3718);
U876 : IVSVTX4 port map( A => Y(0), Z => n3742);
U877 : AO7SVTX2 port map( A => n3747, B => n3748, C => Y(4), Z => n3746);
U878 : AO9SVTX2 port map( A => n3722, B => Y(3), C => n3735, D => Y(4), E =>
n3736, Z => n3734);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity QDS_ADDER is
port( A1, A2 : in std_logic_vector (6 downto 0); Y : out std_logic_vector
(6 downto 0));
end QDS_ADDER;
architecture SYN_BEHAVIORAL of QDS_ADDER is
component IVSVTX2
port( A : in std_logic; Z : out std_logic);
end component;
component NR2SVTX8
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR2SVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO7CSVTX6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
component EO3SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EO3SVTX2
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component AO5SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EO3SVTX4
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EO3SVTX6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO7ABSVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO7SVTX8
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EOSVTX2
port( A, B : in std_logic; Z : out std_logic);
end component;
signal n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238,
n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250,
n251, n252, n253 : std_logic;
begin
U51 : IVSVTX2 port map( A => n246, Z => n244);
U52 : NR2SVTX8 port map( A => n245, B => n246, Z => n238);
U53 : NR2SVTX2 port map( A => n246, B => n245, Z => n237);
U54 : AO7CSVTX6 port map( A => n239, B => n231, C => n240, Z => n232);
U55 : IVSVTX12 port map( A => n241, Z => n239);
U56 : IVSVTX12 port map( A => A2(4), Z => n240);
U57 : IVSVTX12 port map( A => A1(4), Z => n241);
U58 : EO3SVTX8 port map( A => n242, B => n243, C => n228, Z => Y(6));
U59 : IVSVTX12 port map( A => A2(6), Z => n242);
U60 : IVSVTX12 port map( A => A1(6), Z => n243);
U61 : EO3SVTX2 port map( A => A2(4), B => A1(4), C => n231, Z => Y(4));
U62 : IVSVTX8 port map( A => A1(0), Z => n245);
U63 : IVSVTX4 port map( A => A2(0), Z => n246);
U64 : AO5SVTX8 port map( A => A1(1), B => A2(1), C => n238, Z => n247);
U65 : IVSVTX8 port map( A => n247, Z => n235);
U66 : EO3SVTX8 port map( A => A2(1), B => A1(1), C => n237, Z => Y(1));
U67 : EO3SVTX4 port map( A => A2(2), B => A1(2), C => n235, Z => Y(2));
U68 : AO7CSVTX6 port map( A => n248, B => n233, C => n249, Z => n234);
U69 : IVSVTX12 port map( A => n250, Z => n248);
U70 : IVSVTX12 port map( A => A2(3), Z => n249);
U71 : IVSVTX12 port map( A => A1(3), Z => n250);
U72 : EO3SVTX6 port map( A => A2(3), B => A1(3), C => n233, Z => Y(3));
U73 : AO7ABSVTX8 port map( A => A1(2), B => n235, C => n236, Z => n233);
U74 : AO7SVTX8 port map( A => A1(2), B => n235, C => A2(2), Z => n236);
U75 : AO7CSVTX6 port map( A => n251, B => n229, C => n252, Z => n230);
U76 : IVSVTX12 port map( A => n253, Z => n251);
U77 : IVSVTX12 port map( A => A2(5), Z => n252);
U78 : IVSVTX12 port map( A => A1(5), Z => n253);
U79 : AO7ABSVTX8 port map( A => A1(5), B => n229, C => n230, Z => n228);
U80 : AO7ABSVTX8 port map( A => A1(4), B => n231, C => n232, Z => n229);
U81 : EO3SVTX4 port map( A => A2(5), B => A1(5), C => n229, Z => Y(5));
U82 : AO7ABSVTX8 port map( A => A1(3), B => n233, C => n234, Z => n231);
U83 : EOSVTX2 port map( A => n244, B => A1(0), Z => Y(0));
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity QDSEL is
port( A1, A2 : in std_logic_vector (6 downto 0); D : in std_logic_vector (2
downto 0); M1, M2, P1, P2 : out std_logic);
end QDSEL;
architecture SYN_SCHEMATIC of QDSEL is
component QDS_TABLE
port( D : in std_logic_vector (2 downto 0); Y : in std_logic_vector (6
downto 0); M1, M2, P1, P2 : out std_logic);
end component;
component QDS_ADDER
port( A1, A2 : in std_logic_vector (6 downto 0); Y : out
std_logic_vector (6 downto 0));
end component;
signal Y_6_port, Y_5_port, Y_4_port, Y_3_port, Y_2_port, Y_1_port, Y_0_port
: std_logic;
begin
I_1 : QDS_TABLE port map( D(2) => D(2), D(1) => D(1), D(0) => D(0), Y(6) =>
Y_6_port, Y(5) => Y_5_port, Y(4) => Y_4_port, Y(3)
=> Y_3_port, Y(2) => Y_2_port, Y(1) => Y_1_port,
Y(0) => Y_0_port, M1 => M1, M2 => M2, P1 => P1, P2
=> P2);
I_2 : QDS_ADDER port map( A1(6) => A1(6), A1(5) => A1(5), A1(4) => A1(4),
A1(3) => A1(3), A1(2) => A1(2), A1(1) => A1(1),
A1(0) => A1(0), A2(6) => A2(6), A2(5) => A2(5),
A2(4) => A2(4), A2(3) => A2(3), A2(2) => A2(2),
A2(1) => A2(1), A2(0) => A2(0), Y(6) => Y_6_port,
Y(5) => Y_5_port, Y(4) => Y_4_port, Y(3) => Y_3_port
, Y(2) => Y_2_port, Y(1) => Y_1_port, Y(0) =>
Y_0_port);
end SYN_SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_divr4_rec.all;
entity divr4_rec is
port( CLOCK : in std_logic; D : in std_logic_vector (52 downto 0); RESET :
in std_logic; X : in std_logic_vector (53 downto 0); Qj : out
std_logic_vector (3 downto 0));
end divr4_rec;
architecture SYN_SCHEMATIC of divr4_rec is
component CONTROL
port( CLOCK, RESET : in std_logic; CL1, DIGIT, LD1, MX1, ROUND : out
std_logic);
end component;
component MUX
port( A, B : in std_logic_vector (56 downto 0); SEL : in std_logic; Z :
out std_logic_vector (56 downto 0));
end component;
component MULT
port( A : in std_logic_vector (54 downto 0); M1, M2, P1, P2 : in
std_logic; COUT : out std_logic; Z : out std_logic_vector (56
downto 0));
end component;
component gl_csa32_n8
port( A, B, C : in std_logic_vector (8 downto 0); Cin : in std_logic; Z
, Y : out std_logic_vector (8 downto 0));
end component;
component csa32LSBs_n47
port( A, B, C : in std_logic_vector (47 downto 0); Cin : in std_logic;
Cout : out std_logic; Z, Y : out std_logic_vector (47 downto 0));
end component;
component gl_dualreg_ld_n10
port( AS, AC : in std_logic_vector (10 downto 0); RESET, CLOCK, LOAD :
in std_logic; ZS, ZC : out std_logic_vector (10 downto 0));
end component;
component gl_dualreg_ld_n45
port( AS, AC : in std_logic_vector (45 downto 0); RESET, CLOCK, LOAD :
in std_logic; ZS, ZC : out std_logic_vector (45 downto 0));
end component;
component QDSEL
port( A1, A2 : in std_logic_vector (6 downto 0); D : in std_logic_vector
(2 downto 0); M1, M2, P1, P2 : out std_logic);
end component;
component IVHVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX0H
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX8
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX4
port( A : in std_logic; Z : out std_logic);
end component;
component BFHVTX1
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX6
port( A : in std_logic; Z : out std_logic);
end component;
component IVSVTX12
port( A : in std_logic; Z : out std_logic);
end component;
signal GND, W1_56_port, W1_55_port, W1_54_port, W1_53_port, W1_52_port,
W1_51_port, W1_50_port, W1_49_port, W1_48_port, W1_47_port, W1_46_port,
W1_45_port, W1_44_port, W1_43_port, W1_42_port, W1_41_port, W1_40_port,
W1_39_port, W1_38_port, W1_37_port, W1_36_port, W1_35_port, W1_34_port,
W1_33_port, W1_32_port, W1_31_port, W1_30_port, W1_29_port, W1_28_port,
W1_27_port, W1_26_port, W1_25_port, W1_24_port, W1_23_port, W1_22_port,
W1_21_port, W1_20_port, W1_19_port, W1_18_port, W1_17_port, W1_16_port,
W1_15_port, W1_14_port, W1_13_port, W1_12_port, W1_11_port, W1_10_port,
W1_9_port, W1_8_port, W1_7_port, W1_6_port, W1_5_port, W1_4_port,
W1_3_port, W1_2_port, W1_1_port, W1_0_port, W2_56_port, W2_55_port,
W2_54_port, W2_53_port, W2_52_port, W2_51_port, W2_50_port, W2_49_port,
W2_48_port, W2_47_port, W2_46_port, W2_45_port, W2_44_port, W2_43_port,
W2_42_port, W2_41_port, W2_40_port, W2_39_port, W2_38_port, W2_37_port,
W2_36_port, W2_35_port, W2_34_port, W2_33_port, W2_32_port, W2_31_port,
W2_30_port, W2_29_port, W2_28_port, W2_27_port, W2_26_port, W2_25_port,
W2_24_port, W2_23_port, W2_22_port, W2_21_port, W2_20_port, W2_19_port,
W2_18_port, W2_17_port, W2_16_port, W2_15_port, W2_14_port, W2_13_port,
W2_12_port, W2_11_port, W2_10_port, W2_9_port, W2_8_port, W2_7_port,
W2_6_port, W2_5_port, W2_4_port, W2_3_port, W2_2_port, W2_1_port,
W2_0_port, CLR, LOAD, muxW, n119, Qj_2_port, Qj_1_port, n120,
MXLA_56_port, MXLA_55_port, MXLA_54_port, MXLA_53_port, MXLA_52_port,
MXLA_51_port, MXLA_50_port, MXLA_49_port, MXLA_48_port, MXLA_47_port,
MXLA_46_port, MXLA_45_port, MXLA_44_port, MXLA_43_port, MXLA_42_port,
MXLA_41_port, MXLA_40_port, MXLA_39_port, MXLA_38_port, MXLA_37_port,
MXLA_36_port, MXLA_35_port, MXLA_34_port, MXLA_33_port, MXLA_32_port,
MXLA_31_port, MXLA_30_port, MXLA_29_port, MXLA_28_port, MXLA_27_port,
MXLA_26_port, MXLA_25_port, MXLA_24_port, MXLA_23_port, MXLA_22_port,
MXLA_21_port, MXLA_20_port, MXLA_19_port, MXLA_18_port, MXLA_17_port,
MXLA_16_port, MXLA_15_port, MXLA_14_port, MXLA_13_port, MXLA_12_port,
MXLA_11_port, MXLA_10_port, MXLA_9_port, MXLA_8_port, MXLA_7_port,
MXLA_6_port, MXLA_5_port, MXLA_4_port, MXLA_3_port, MXLA_2_port,
MXLA_1_port, MXLA_0_port, qjD_c2, qjD_56_port, qjD_55_port, qjD_54_port,
qjD_53_port, qjD_52_port, qjD_51_port, qjD_50_port, qjD_49_port,
qjD_48_port, qjD_47_port, qjD_46_port, qjD_45_port, qjD_44_port,
qjD_43_port, qjD_42_port, qjD_41_port, qjD_40_port, qjD_39_port,
qjD_38_port, qjD_37_port, qjD_36_port, qjD_35_port, qjD_34_port,
qjD_33_port, qjD_32_port, qjD_31_port, qjD_30_port, qjD_29_port,
qjD_28_port, qjD_27_port, qjD_26_port, qjD_25_port, qjD_24_port,
qjD_23_port, qjD_22_port, qjD_21_port, qjD_20_port, qjD_19_port,
qjD_18_port, qjD_17_port, qjD_16_port, qjD_15_port, qjD_14_port,
qjD_13_port, qjD_12_port, qjD_11_port, qjD_10_port, qjD_9_port,
qjD_8_port, qjD_7_port, qjD_6_port, qjD_5_port, qjD_4_port, qjD_3_port,
qjD_2_port, qjD_1_port, qjD_0_port, carry_ex, WC_56_port, WC_55_port,
WC_54_port, WC_53_port, WC_52_port, WC_51_port, WC_50_port, WC_49_port,
WC_48_port, WC_47_port, WC_46_port, WC_45_port, WC_44_port, WC_43_port,
WC_42_port, WC_41_port, WC_40_port, WC_39_port, WC_38_port, WC_37_port,
WC_36_port, WC_35_port, WC_34_port, WC_33_port, WC_32_port, WC_31_port,
WC_30_port, WC_29_port, WC_28_port, WC_27_port, WC_26_port, WC_25_port,
WC_24_port, WC_23_port, WC_22_port, WC_21_port, WC_20_port, WC_19_port,
WC_18_port, WC_17_port, WC_16_port, WC_15_port, WC_14_port, WC_13_port,
WC_12_port, WC_11_port, WC_10_port, WC_9_port, WC_8_port, WC_7_port,
WC_6_port, WC_5_port, WC_4_port, WC_3_port, WC_2_port, WC_1_port,
WC_0_port, WS_56_port, WS_55_port, WS_54_port, WS_53_port, WS_52_port,
WS_51_port, WS_50_port, WS_49_port, WS_48_port, WS_47_port, WS_46_port,
WS_45_port, WS_44_port, WS_43_port, WS_42_port, WS_41_port, WS_40_port,
WS_39_port, WS_38_port, WS_37_port, WS_36_port, WS_35_port, WS_34_port,
WS_33_port, WS_32_port, WS_31_port, WS_30_port, WS_29_port, WS_28_port,
WS_27_port, WS_26_port, WS_25_port, WS_24_port, WS_23_port, WS_22_port,
WS_21_port, WS_20_port, WS_19_port, WS_18_port, WS_17_port, WS_16_port,
WS_15_port, WS_14_port, WS_13_port, WS_12_port, WS_11_port, WS_10_port,
WS_9_port, WS_8_port, WS_7_port, WS_6_port, WS_5_port, WS_4_port,
WS_3_port, WS_2_port, WS_1_port, WS_0_port, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, Qj_3_port, n117, Qj_0_port,
n_1001, n_1002 : std_logic;
begin
Qj <= ( Qj_3_port, Qj_2_port, Qj_1_port, Qj_0_port );
GND <= '0';
I_CTRL : CONTROL port map( CLOCK => CLOCK, RESET => RESET, CL1 => CLR, DIGIT
=> n_1001, LD1 => LOAD, MX1 => muxW, ROUND => n_1002
);
I_MUX : MUX port map( A(56) => GND, A(55) => GND, A(54) => GND, A(53) =>
X(53), A(52) => X(52), A(51) => X(51), A(50) =>
X(50), A(49) => X(49), A(48) => X(48), A(47) =>
X(47), A(46) => X(46), A(45) => X(45), A(44) =>
X(44), A(43) => X(43), A(42) => X(42), A(41) =>
X(41), A(40) => X(40), A(39) => X(39), A(38) =>
X(38), A(37) => X(37), A(36) => X(36), A(35) =>
X(35), A(34) => X(34), A(33) => X(33), A(32) =>
X(32), A(31) => X(31), A(30) => X(30), A(29) =>
X(29), A(28) => X(28), A(27) => X(27), A(26) =>
X(26), A(25) => X(25), A(24) => X(24), A(23) =>
X(23), A(22) => X(22), A(21) => X(21), A(20) =>
X(20), A(19) => X(19), A(18) => X(18), A(17) =>
X(17), A(16) => X(16), A(15) => X(15), A(14) =>
X(14), A(13) => X(13), A(12) => X(12), A(11) =>
X(11), A(10) => X(10), A(9) => X(9), A(8) => X(8),
A(7) => X(7), A(6) => X(6), A(5) => X(5), A(4) =>
X(4), A(3) => X(3), A(2) => X(2), A(1) => X(1), A(0)
=> X(0), B(56) => W1_54_port, B(55) => W1_53_port,
B(54) => W1_52_port, B(53) => n114, B(52) => n109,
B(51) => W1_49_port, B(50) => W1_48_port, B(49) =>
W1_47_port, B(48) => W1_46_port, B(47) => W1_45_port
, B(46) => W1_44_port, B(45) => W1_43_port, B(44) =>
W1_42_port, B(43) => W1_41_port, B(42) => W1_40_port
, B(41) => W1_39_port, B(40) => W1_38_port, B(39) =>
W1_37_port, B(38) => W1_36_port, B(37) => W1_35_port
, B(36) => W1_34_port, B(35) => W1_33_port, B(34) =>
W1_32_port, B(33) => W1_31_port, B(32) => W1_30_port
, B(31) => W1_29_port, B(30) => W1_28_port, B(29) =>
W1_27_port, B(28) => W1_26_port, B(27) => W1_25_port
, B(26) => W1_24_port, B(25) => W1_23_port, B(24) =>
W1_22_port, B(23) => W1_21_port, B(22) => W1_20_port
, B(21) => W1_19_port, B(20) => W1_18_port, B(19) =>
W1_17_port, B(18) => W1_16_port, B(17) => W1_15_port
, B(16) => W1_14_port, B(15) => W1_13_port, B(14) =>
W1_12_port, B(13) => W1_11_port, B(12) => W1_10_port
, B(11) => W1_9_port, B(10) => W1_8_port, B(9) =>
W1_7_port, B(8) => W1_6_port, B(7) => W1_5_port,
B(6) => W1_4_port, B(5) => W1_3_port, B(4) =>
W1_2_port, B(3) => W1_1_port, B(2) => W1_0_port,
B(1) => GND, B(0) => GND, SEL => muxW, Z(56) =>
MXLA_56_port, Z(55) => MXLA_55_port, Z(54) =>
MXLA_54_port, Z(53) => MXLA_53_port, Z(52) =>
MXLA_52_port, Z(51) => MXLA_51_port, Z(50) =>
MXLA_50_port, Z(49) => MXLA_49_port, Z(48) =>
MXLA_48_port, Z(47) => MXLA_47_port, Z(46) =>
MXLA_46_port, Z(45) => MXLA_45_port, Z(44) =>
MXLA_44_port, Z(43) => MXLA_43_port, Z(42) =>
MXLA_42_port, Z(41) => MXLA_41_port, Z(40) =>
MXLA_40_port, Z(39) => MXLA_39_port, Z(38) =>
MXLA_38_port, Z(37) => MXLA_37_port, Z(36) =>
MXLA_36_port, Z(35) => MXLA_35_port, Z(34) =>
MXLA_34_port, Z(33) => MXLA_33_port, Z(32) =>
MXLA_32_port, Z(31) => MXLA_31_port, Z(30) =>
MXLA_30_port, Z(29) => MXLA_29_port, Z(28) =>
MXLA_28_port, Z(27) => MXLA_27_port, Z(26) =>
MXLA_26_port, Z(25) => MXLA_25_port, Z(24) =>
MXLA_24_port, Z(23) => MXLA_23_port, Z(22) =>
MXLA_22_port, Z(21) => MXLA_21_port, Z(20) =>
MXLA_20_port, Z(19) => MXLA_19_port, Z(18) =>
MXLA_18_port, Z(17) => MXLA_17_port, Z(16) =>
MXLA_16_port, Z(15) => MXLA_15_port, Z(14) =>
MXLA_14_port, Z(13) => MXLA_13_port, Z(12) =>
MXLA_12_port, Z(11) => MXLA_11_port, Z(10) =>
MXLA_10_port, Z(9) => MXLA_9_port, Z(8) =>
MXLA_8_port, Z(7) => MXLA_7_port, Z(6) =>
MXLA_6_port, Z(5) => MXLA_5_port, Z(4) =>
MXLA_4_port, Z(3) => MXLA_3_port, Z(2) =>
MXLA_2_port, Z(1) => MXLA_1_port, Z(0) =>
MXLA_0_port);
I_MULT : MULT port map( A(54) => GND, A(53) => D(52), A(52) => D(51), A(51)
=> D(50), A(50) => D(49), A(49) => D(48), A(48) =>
D(47), A(47) => D(46), A(46) => D(45), A(45) =>
D(44), A(44) => D(43), A(43) => D(42), A(42) =>
D(41), A(41) => D(40), A(40) => D(39), A(39) =>
D(38), A(38) => D(37), A(37) => D(36), A(36) =>
D(35), A(35) => D(34), A(34) => D(33), A(33) =>
D(32), A(32) => D(31), A(31) => D(30), A(30) =>
D(29), A(29) => D(28), A(28) => D(27), A(27) =>
D(26), A(26) => D(25), A(25) => D(24), A(24) =>
D(23), A(23) => D(22), A(22) => D(21), A(21) =>
D(20), A(20) => D(19), A(19) => D(18), A(18) =>
D(17), A(17) => D(16), A(16) => D(15), A(15) =>
D(14), A(14) => D(13), A(13) => D(12), A(12) =>
D(11), A(11) => D(10), A(10) => D(9), A(9) => D(8),
A(8) => D(7), A(7) => D(6), A(6) => D(5), A(5) =>
D(4), A(4) => D(3), A(3) => D(2), A(2) => D(1), A(1)
=> D(0), A(0) => GND, M1 => Qj_2_port, M2 =>
Qj_3_port, P1 => Qj_1_port, P2 => Qj_0_port, COUT =>
qjD_c2, Z(56) => qjD_56_port, Z(55) => qjD_55_port,
Z(54) => qjD_54_port, Z(53) => qjD_53_port, Z(52) =>
qjD_52_port, Z(51) => qjD_51_port, Z(50) =>
qjD_50_port, Z(49) => qjD_49_port, Z(48) =>
qjD_48_port, Z(47) => qjD_47_port, Z(46) =>
qjD_46_port, Z(45) => qjD_45_port, Z(44) =>
qjD_44_port, Z(43) => qjD_43_port, Z(42) =>
qjD_42_port, Z(41) => qjD_41_port, Z(40) =>
qjD_40_port, Z(39) => qjD_39_port, Z(38) =>
qjD_38_port, Z(37) => qjD_37_port, Z(36) =>
qjD_36_port, Z(35) => qjD_35_port, Z(34) =>
qjD_34_port, Z(33) => qjD_33_port, Z(32) =>
qjD_32_port, Z(31) => qjD_31_port, Z(30) =>
qjD_30_port, Z(29) => qjD_29_port, Z(28) =>
qjD_28_port, Z(27) => qjD_27_port, Z(26) =>
qjD_26_port, Z(25) => qjD_25_port, Z(24) =>
qjD_24_port, Z(23) => qjD_23_port, Z(22) =>
qjD_22_port, Z(21) => qjD_21_port, Z(20) =>
qjD_20_port, Z(19) => qjD_19_port, Z(18) =>
qjD_18_port, Z(17) => qjD_17_port, Z(16) =>
qjD_16_port, Z(15) => qjD_15_port, Z(14) =>
qjD_14_port, Z(13) => qjD_13_port, Z(12) =>
qjD_12_port, Z(11) => qjD_11_port, Z(10) =>
qjD_10_port, Z(9) => qjD_9_port, Z(8) => qjD_8_port,
Z(7) => qjD_7_port, Z(6) => qjD_6_port, Z(5) =>
qjD_5_port, Z(4) => qjD_4_port, Z(3) => qjD_3_port,
Z(2) => qjD_2_port, Z(1) => qjD_1_port, Z(0) =>
qjD_0_port);
I_CSA1 : gl_csa32_n8 port map( A(8) => MXLA_56_port, A(7) => MXLA_55_port,
A(6) => MXLA_54_port, A(5) => MXLA_53_port, A(4) =>
MXLA_52_port, A(3) => MXLA_51_port, A(2) =>
MXLA_50_port, A(1) => MXLA_49_port, A(0) =>
MXLA_48_port, B(8) => W2_54_port, B(7) => W2_53_port
, B(6) => W2_52_port, B(5) => n112, B(4) => n110,
B(3) => W2_49_port, B(2) => W2_48_port, B(1) =>
W2_47_port, B(0) => W2_46_port, C(8) => qjD_56_port,
C(7) => qjD_55_port, C(6) => qjD_54_port, C(5) =>
qjD_53_port, C(4) => qjD_52_port, C(3) =>
qjD_51_port, C(2) => qjD_50_port, C(1) =>
qjD_49_port, C(0) => qjD_48_port, Cin => carry_ex,
Z(8) => WS_56_port, Z(7) => WS_55_port, Z(6) =>
WS_54_port, Z(5) => WS_53_port, Z(4) => WS_52_port,
Z(3) => WS_51_port, Z(2) => WS_50_port, Z(1) =>
WS_49_port, Z(0) => WS_48_port, Y(8) => WC_56_port,
Y(7) => WC_55_port, Y(6) => WC_54_port, Y(5) =>
WC_53_port, Y(4) => WC_52_port, Y(3) => WC_51_port,
Y(2) => WC_50_port, Y(1) => WC_49_port, Y(0) =>
WC_48_port);
I_CSA2 : csa32LSBs_n47 port map( A(47) => MXLA_47_port, A(46) =>
MXLA_46_port, A(45) => MXLA_45_port, A(44) =>
MXLA_44_port, A(43) => MXLA_43_port, A(42) =>
MXLA_42_port, A(41) => MXLA_41_port, A(40) =>
MXLA_40_port, A(39) => MXLA_39_port, A(38) =>
MXLA_38_port, A(37) => MXLA_37_port, A(36) =>
MXLA_36_port, A(35) => MXLA_35_port, A(34) =>
MXLA_34_port, A(33) => MXLA_33_port, A(32) =>
MXLA_32_port, A(31) => MXLA_31_port, A(30) =>
MXLA_30_port, A(29) => MXLA_29_port, A(28) =>
MXLA_28_port, A(27) => MXLA_27_port, A(26) =>
MXLA_26_port, A(25) => MXLA_25_port, A(24) =>
MXLA_24_port, A(23) => MXLA_23_port, A(22) =>
MXLA_22_port, A(21) => MXLA_21_port, A(20) =>
MXLA_20_port, A(19) => MXLA_19_port, A(18) =>
MXLA_18_port, A(17) => MXLA_17_port, A(16) =>
MXLA_16_port, A(15) => MXLA_15_port, A(14) =>
MXLA_14_port, A(13) => MXLA_13_port, A(12) =>
MXLA_12_port, A(11) => MXLA_11_port, A(10) =>
MXLA_10_port, A(9) => MXLA_9_port, A(8) =>
MXLA_8_port, A(7) => MXLA_7_port, A(6) =>
MXLA_6_port, A(5) => MXLA_5_port, A(4) =>
MXLA_4_port, A(3) => MXLA_3_port, A(2) =>
MXLA_2_port, A(1) => MXLA_1_port, A(0) =>
MXLA_0_port, B(47) => W2_45_port, B(46) =>
W2_44_port, B(45) => W2_43_port, B(44) => W2_42_port
, B(43) => W2_41_port, B(42) => W2_40_port, B(41) =>
W2_39_port, B(40) => W2_38_port, B(39) => W2_37_port
, B(38) => W2_36_port, B(37) => W2_35_port, B(36) =>
W2_34_port, B(35) => W2_33_port, B(34) => W2_32_port
, B(33) => W2_31_port, B(32) => W2_30_port, B(31) =>
W2_29_port, B(30) => W2_28_port, B(29) => W2_27_port
, B(28) => W2_26_port, B(27) => W2_25_port, B(26) =>
W2_24_port, B(25) => W2_23_port, B(24) => W2_22_port
, B(23) => W2_21_port, B(22) => W2_20_port, B(21) =>
W2_19_port, B(20) => W2_18_port, B(19) => W2_17_port
, B(18) => W2_16_port, B(17) => W2_15_port, B(16) =>
W2_14_port, B(15) => W2_13_port, B(14) => W2_12_port
, B(13) => W2_11_port, B(12) => W2_10_port, B(11) =>
W2_9_port, B(10) => W2_8_port, B(9) => W2_7_port,
B(8) => W2_6_port, B(7) => W2_5_port, B(6) =>
W2_4_port, B(5) => W2_3_port, B(4) => W2_2_port,
B(3) => W2_1_port, B(2) => W2_0_port, B(1) => GND,
B(0) => GND, C(47) => qjD_47_port, C(46) =>
qjD_46_port, C(45) => qjD_45_port, C(44) =>
qjD_44_port, C(43) => qjD_43_port, C(42) =>
qjD_42_port, C(41) => qjD_41_port, C(40) =>
qjD_40_port, C(39) => qjD_39_port, C(38) =>
qjD_38_port, C(37) => qjD_37_port, C(36) =>
qjD_36_port, C(35) => qjD_35_port, C(34) =>
qjD_34_port, C(33) => qjD_33_port, C(32) =>
qjD_32_port, C(31) => qjD_31_port, C(30) =>
qjD_30_port, C(29) => qjD_29_port, C(28) =>
qjD_28_port, C(27) => qjD_27_port, C(26) =>
qjD_26_port, C(25) => qjD_25_port, C(24) =>
qjD_24_port, C(23) => qjD_23_port, C(22) =>
qjD_22_port, C(21) => qjD_21_port, C(20) =>
qjD_20_port, C(19) => qjD_19_port, C(18) =>
qjD_18_port, C(17) => qjD_17_port, C(16) =>
qjD_16_port, C(15) => qjD_15_port, C(14) =>
qjD_14_port, C(13) => qjD_13_port, C(12) =>
qjD_12_port, C(11) => qjD_11_port, C(10) =>
qjD_10_port, C(9) => qjD_9_port, C(8) => qjD_8_port,
C(7) => qjD_7_port, C(6) => qjD_6_port, C(5) =>
qjD_5_port, C(4) => qjD_4_port, C(3) => qjD_3_port,
C(2) => qjD_2_port, C(1) => qjD_1_port, C(0) =>
qjD_0_port, Cin => qjD_c2, Cout => carry_ex, Z(47)
=> WS_47_port, Z(46) => WS_46_port, Z(45) =>
WS_45_port, Z(44) => WS_44_port, Z(43) => WS_43_port
, Z(42) => WS_42_port, Z(41) => WS_41_port, Z(40) =>
WS_40_port, Z(39) => WS_39_port, Z(38) => WS_38_port
, Z(37) => WS_37_port, Z(36) => WS_36_port, Z(35) =>
WS_35_port, Z(34) => WS_34_port, Z(33) => WS_33_port
, Z(32) => WS_32_port, Z(31) => WS_31_port, Z(30) =>
WS_30_port, Z(29) => WS_29_port, Z(28) => WS_28_port
, Z(27) => WS_27_port, Z(26) => WS_26_port, Z(25) =>
WS_25_port, Z(24) => WS_24_port, Z(23) => WS_23_port
, Z(22) => WS_22_port, Z(21) => WS_21_port, Z(20) =>
WS_20_port, Z(19) => WS_19_port, Z(18) => WS_18_port
, Z(17) => WS_17_port, Z(16) => WS_16_port, Z(15) =>
WS_15_port, Z(14) => WS_14_port, Z(13) => WS_13_port
, Z(12) => WS_12_port, Z(11) => WS_11_port, Z(10) =>
WS_10_port, Z(9) => WS_9_port, Z(8) => WS_8_port,
Z(7) => WS_7_port, Z(6) => WS_6_port, Z(5) =>
WS_5_port, Z(4) => WS_4_port, Z(3) => WS_3_port,
Z(2) => WS_2_port, Z(1) => WS_1_port, Z(0) =>
WS_0_port, Y(47) => WC_47_port, Y(46) => WC_46_port,
Y(45) => WC_45_port, Y(44) => WC_44_port, Y(43) =>
WC_43_port, Y(42) => WC_42_port, Y(41) => WC_41_port
, Y(40) => WC_40_port, Y(39) => WC_39_port, Y(38) =>
WC_38_port, Y(37) => WC_37_port, Y(36) => WC_36_port
, Y(35) => WC_35_port, Y(34) => WC_34_port, Y(33) =>
WC_33_port, Y(32) => WC_32_port, Y(31) => WC_31_port
, Y(30) => WC_30_port, Y(29) => WC_29_port, Y(28) =>
WC_28_port, Y(27) => WC_27_port, Y(26) => WC_26_port
, Y(25) => WC_25_port, Y(24) => WC_24_port, Y(23) =>
WC_23_port, Y(22) => WC_22_port, Y(21) => WC_21_port
, Y(20) => WC_20_port, Y(19) => WC_19_port, Y(18) =>
WC_18_port, Y(17) => WC_17_port, Y(16) => WC_16_port
, Y(15) => WC_15_port, Y(14) => WC_14_port, Y(13) =>
WC_13_port, Y(12) => WC_12_port, Y(11) => WC_11_port
, Y(10) => WC_10_port, Y(9) => WC_9_port, Y(8) =>
WC_8_port, Y(7) => WC_7_port, Y(6) => WC_6_port,
Y(5) => WC_5_port, Y(4) => WC_4_port, Y(3) =>
WC_3_port, Y(2) => WC_2_port, Y(1) => WC_1_port,
Y(0) => WC_0_port);
I_REG1 : gl_dualreg_ld_n10 port map( AS(10) => WS_56_port, AS(9) =>
WS_55_port, AS(8) => WS_54_port, AS(7) => WS_53_port
, AS(6) => WS_52_port, AS(5) => WS_51_port, AS(4) =>
WS_50_port, AS(3) => WS_49_port, AS(2) => WS_48_port
, AS(1) => WS_47_port, AS(0) => WS_46_port, AC(10)
=> WC_56_port, AC(9) => WC_55_port, AC(8) =>
WC_54_port, AC(7) => WC_53_port, AC(6) => WC_52_port
, AC(5) => WC_51_port, AC(4) => WC_50_port, AC(3) =>
WC_49_port, AC(2) => WC_48_port, AC(1) => WC_47_port
, AC(0) => WC_46_port, RESET => CLR, CLOCK => CLOCK,
LOAD => LOAD, ZS(10) => W1_56_port, ZS(9) =>
W1_55_port, ZS(8) => W1_54_port, ZS(7) => W1_53_port
, ZS(6) => W1_52_port, ZS(5) => W1_51_port, ZS(4) =>
W1_50_port, ZS(3) => W1_49_port, ZS(2) => W1_48_port
, ZS(1) => W1_47_port, ZS(0) => W1_46_port, ZC(10)
=> W2_56_port, ZC(9) => W2_55_port, ZC(8) =>
W2_54_port, ZC(7) => W2_53_port, ZC(6) => W2_52_port
, ZC(5) => W2_51_port, ZC(4) => W2_50_port, ZC(3) =>
W2_49_port, ZC(2) => W2_48_port, ZC(1) => W2_47_port
, ZC(0) => W2_46_port);
I_REG2 : gl_dualreg_ld_n45 port map( AS(45) => WS_45_port, AS(44) =>
WS_44_port, AS(43) => WS_43_port, AS(42) =>
WS_42_port, AS(41) => WS_41_port, AS(40) =>
WS_40_port, AS(39) => WS_39_port, AS(38) =>
WS_38_port, AS(37) => WS_37_port, AS(36) =>
WS_36_port, AS(35) => WS_35_port, AS(34) =>
WS_34_port, AS(33) => WS_33_port, AS(32) =>
WS_32_port, AS(31) => WS_31_port, AS(30) =>
WS_30_port, AS(29) => WS_29_port, AS(28) =>
WS_28_port, AS(27) => WS_27_port, AS(26) =>
WS_26_port, AS(25) => WS_25_port, AS(24) =>
WS_24_port, AS(23) => WS_23_port, AS(22) =>
WS_22_port, AS(21) => WS_21_port, AS(20) =>
WS_20_port, AS(19) => WS_19_port, AS(18) =>
WS_18_port, AS(17) => WS_17_port, AS(16) =>
WS_16_port, AS(15) => WS_15_port, AS(14) =>
WS_14_port, AS(13) => WS_13_port, AS(12) =>
WS_12_port, AS(11) => WS_11_port, AS(10) =>
WS_10_port, AS(9) => WS_9_port, AS(8) => WS_8_port,
AS(7) => WS_7_port, AS(6) => WS_6_port, AS(5) =>
WS_5_port, AS(4) => WS_4_port, AS(3) => WS_3_port,
AS(2) => WS_2_port, AS(1) => WS_1_port, AS(0) =>
WS_0_port, AC(45) => WC_45_port, AC(44) =>
WC_44_port, AC(43) => WC_43_port, AC(42) =>
WC_42_port, AC(41) => WC_41_port, AC(40) =>
WC_40_port, AC(39) => WC_39_port, AC(38) =>
WC_38_port, AC(37) => WC_37_port, AC(36) =>
WC_36_port, AC(35) => WC_35_port, AC(34) =>
WC_34_port, AC(33) => WC_33_port, AC(32) =>
WC_32_port, AC(31) => WC_31_port, AC(30) =>
WC_30_port, AC(29) => WC_29_port, AC(28) =>
WC_28_port, AC(27) => WC_27_port, AC(26) =>
WC_26_port, AC(25) => WC_25_port, AC(24) =>
WC_24_port, AC(23) => WC_23_port, AC(22) =>
WC_22_port, AC(21) => WC_21_port, AC(20) =>
WC_20_port, AC(19) => WC_19_port, AC(18) =>
WC_18_port, AC(17) => WC_17_port, AC(16) =>
WC_16_port, AC(15) => WC_15_port, AC(14) =>
WC_14_port, AC(13) => WC_13_port, AC(12) =>
WC_12_port, AC(11) => WC_11_port, AC(10) =>
WC_10_port, AC(9) => WC_9_port, AC(8) => WC_8_port,
AC(7) => WC_7_port, AC(6) => WC_6_port, AC(5) =>
WC_5_port, AC(4) => WC_4_port, AC(3) => WC_3_port,
AC(2) => WC_2_port, AC(1) => WC_1_port, AC(0) =>
WC_0_port, RESET => CLR, CLOCK => CLOCK, LOAD =>
LOAD, ZS(45) => W1_45_port, ZS(44) => W1_44_port,
ZS(43) => W1_43_port, ZS(42) => W1_42_port, ZS(41)
=> W1_41_port, ZS(40) => W1_40_port, ZS(39) =>
W1_39_port, ZS(38) => W1_38_port, ZS(37) =>
W1_37_port, ZS(36) => W1_36_port, ZS(35) =>
W1_35_port, ZS(34) => W1_34_port, ZS(33) =>
W1_33_port, ZS(32) => W1_32_port, ZS(31) =>
W1_31_port, ZS(30) => W1_30_port, ZS(29) =>
W1_29_port, ZS(28) => W1_28_port, ZS(27) =>
W1_27_port, ZS(26) => W1_26_port, ZS(25) =>
W1_25_port, ZS(24) => W1_24_port, ZS(23) =>
W1_23_port, ZS(22) => W1_22_port, ZS(21) =>
W1_21_port, ZS(20) => W1_20_port, ZS(19) =>
W1_19_port, ZS(18) => W1_18_port, ZS(17) =>
W1_17_port, ZS(16) => W1_16_port, ZS(15) =>
W1_15_port, ZS(14) => W1_14_port, ZS(13) =>
W1_13_port, ZS(12) => W1_12_port, ZS(11) =>
W1_11_port, ZS(10) => W1_10_port, ZS(9) => W1_9_port
, ZS(8) => W1_8_port, ZS(7) => W1_7_port, ZS(6) =>
W1_6_port, ZS(5) => W1_5_port, ZS(4) => W1_4_port,
ZS(3) => W1_3_port, ZS(2) => W1_2_port, ZS(1) =>
W1_1_port, ZS(0) => W1_0_port, ZC(45) => W2_45_port,
ZC(44) => W2_44_port, ZC(43) => W2_43_port, ZC(42)
=> W2_42_port, ZC(41) => W2_41_port, ZC(40) =>
W2_40_port, ZC(39) => W2_39_port, ZC(38) =>
W2_38_port, ZC(37) => W2_37_port, ZC(36) =>
W2_36_port, ZC(35) => W2_35_port, ZC(34) =>
W2_34_port, ZC(33) => W2_33_port, ZC(32) =>
W2_32_port, ZC(31) => W2_31_port, ZC(30) =>
W2_30_port, ZC(29) => W2_29_port, ZC(28) =>
W2_28_port, ZC(27) => W2_27_port, ZC(26) =>
W2_26_port, ZC(25) => W2_25_port, ZC(24) =>
W2_24_port, ZC(23) => W2_23_port, ZC(22) =>
W2_22_port, ZC(21) => W2_21_port, ZC(20) =>
W2_20_port, ZC(19) => W2_19_port, ZC(18) =>
W2_18_port, ZC(17) => W2_17_port, ZC(16) =>
W2_16_port, ZC(15) => W2_15_port, ZC(14) =>
W2_14_port, ZC(13) => W2_13_port, ZC(12) =>
W2_12_port, ZC(11) => W2_11_port, ZC(10) =>
W2_10_port, ZC(9) => W2_9_port, ZC(8) => W2_8_port,
ZC(7) => W2_7_port, ZC(6) => W2_6_port, ZC(5) =>
W2_5_port, ZC(4) => W2_4_port, ZC(3) => W2_3_port,
ZC(2) => W2_2_port, ZC(1) => W2_1_port, ZC(0) =>
W2_0_port);
I_SEL : QDSEL port map( A1(6) => W1_56_port, A1(5) => W1_55_port, A1(4) =>
W1_54_port, A1(3) => W1_53_port, A1(2) => W1_52_port
, A1(1) => n114, A1(0) => W1_50_port, A2(6) =>
W2_56_port, A2(5) => W2_55_port, A2(4) => W2_54_port
, A2(3) => W2_53_port, A2(2) => W2_52_port, A2(1) =>
n107, A2(0) => W2_50_port, D(2) => D(51), D(1) =>
D(50), D(0) => D(49), M1 => Qj_2_port, M2 => n119,
P1 => Qj_1_port, P2 => n120);
U4 : IVHVTX0H port map( A => W2_50_port, Z => n104);
U5 : IVSVTX0H port map( A => n104, Z => n105);
U6 : IVSVTX8 port map( A => n106, Z => n107);
U7 : IVSVTX4 port map( A => W2_51_port, Z => n106);
U8 : IVHVTX0H port map( A => W1_50_port, Z => n108);
U9 : IVSVTX0H port map( A => n108, Z => n109);
U10 : IVSVTX8 port map( A => n113, Z => n114);
U11 : BFHVTX1 port map( A => n105, Z => n110);
U12 : IVSVTX6 port map( A => n119, Z => n115);
U13 : IVHVTX0H port map( A => n107, Z => n111);
U14 : IVSVTX0H port map( A => n111, Z => n112);
U15 : IVSVTX4 port map( A => W1_51_port, Z => n113);
U16 : IVSVTX8 port map( A => n120, Z => n117);
U17 : IVSVTX12 port map( A => n115, Z => Qj_3_port);
U18 : IVSVTX12 port map( A => n117, Z => Qj_0_port);
end SYN_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/divr4_rec_0.9ns.vhd | VHDL | lgpl | 155,462 |
library IEEE;
use IEEE.std_logic_1164.all;
entity csa32LSBs is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end csa32LSBs;
architecture BEHAVIORAL of csa32LSBs is
begin
process(A, B, C, Cin)
variable p : std_logic_vector (n downto 0) ;
variable g : std_logic_vector (n downto 0) ;
variable i : integer;
begin
for i in 0 to n loop
p(i) := A(i) XOR B(i) ;
g(i) := A(i) AND B(i) ;
end loop;
-- CARRY -----------------------------------
Y(0) <= Cin;
for i in 0 to n-1 loop
Y(i+1) <= g(i) OR (c(i) AND p(i));
end loop;
Cout <= g(n) OR (c(n) AND p(n));
-- SUM -------------------------------------
for i in 0 to n loop
Z(i) <= p(i) XOR c(i);
end loop;
end process;
end BEHAVIORAL;
configuration CFG_csa32LSBs_BEHAVIORAL of csa32LSBs is
for BEHAVIORAL
end for;
end CFG_csa32LSBs_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/csa32LSBs.vhd | VHDL | lgpl | 1,041 |
library IEEE;
use IEEE.std_logic_1164.all;
entity gl_csa32 is
GENERIC(n : integer);
Port ( A : In std_logic_vector (n downto 0);
B : In std_logic_vector (n downto 0);
C : In std_logic_vector (n downto 0);
Cin : In std_logic;
Z : Out std_logic_vector (n downto 0);
Y : Out std_logic_vector (n downto 0) );
end gl_csa32;
architecture BEHAVIORAL of gl_csa32 is
begin
process(A, B, C, Cin)
variable p : std_logic_vector (n downto 0) ;
variable g : std_logic_vector (n downto 0) ;
variable i : integer;
begin
for i in 0 to n loop
p(i) := A(i) XOR B(i) ;
g(i) := A(i) AND B(i) ;
end loop;
-- CARRY -----------------------------------
Y(0) <= Cin;
for i in 0 to n-1 loop
Y(i+1) <= g(i) OR (c(i) AND p(i));
end loop;
-- SUM -------------------------------------
for i in 0 to n loop
Z(i) <= p(i) XOR c(i);
end loop;
end process;
end BEHAVIORAL;
configuration CFG_gl_csa32_BEHAVIORAL of gl_csa32 is
for BEHAVIORAL
end for;
end CFG_gl_csa32_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/gl_csa32.vhd | VHDL | lgpl | 977 |
-- VHDL Model Created from SGE Symbol qds_adder.sym -- Apr 21 16:44:47 1995
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity QDS_ADDER is
Port ( A1 : In std_logic_vector (6 downto 0);
A2 : In std_logic_vector (6 downto 0);
Y : Out std_logic_vector (6 downto 0) );
end QDS_ADDER;
architecture BEHAVIORAL of QDS_ADDER is
begin
process(A1, A2)
variable g0,p0 : std_logic_vector (1 downto 0) ;
variable g1,p1 : std_logic_vector (1 downto 0) ;
variable g2,p2 : std_logic_vector (1 downto 0) ;
variable g3,p3 : std_logic;
variable c : std_logic_vector (4 downto 0) ;
variable cc : std_logic_vector (1 downto 0) ;
variable i,j,k,l : integer;
begin
cc(0) := '0';
----------------------------------- 1st level -----------------------
j := 0 ;
g0(0) := A1(0+j) AND A2(0+j); p0(0) := A1(0+j) OR A2(0+j);
g1(0) := A1(1+j) AND A2(1+j); p1(0) := A1(1+j) OR A2(1+j);
g2(0) := A1(2+j) AND A2(2+j); p2(0) := A1(2+j) OR A2(2+j);
g3 := A1(3+j) AND A2(3+j); p3 := A1(3+j) OR A2(3+j);
j := 4 ;
g0(1) := A1(0+j) AND A2(0+j); p0(1) := A1(0+j) OR A2(0+j);
g1(1) := A1(1+j) AND A2(1+j); p1(1) := A1(1+j) OR A2(1+j);
g2(1) := A1(2+j) AND A2(2+j); p2(1) := A1(2+j) OR A2(2+j);
----------------------------------- 2nd level -----------------------
k := 0;
cc(1) := g3 OR (g2(k) AND p3 ) OR (g1(k) AND p2(k) AND p3 )
OR (g0(k) AND p1(k) AND p2(k) AND p3 ) ;
-- CARRY -------------------------- 1st level -----------------------
k := 0;
c(0) := cc(k);
c(1) := g0(k) OR (c(0) AND p0(k));
c(2) := g1(k) OR (g0(k) AND p1(k)) OR (c(0) AND p0(k) AND p1(k));
c(3) := g2(k) OR (g1(k) AND p2(k)) OR (g0(k) AND p1(k) AND p2(k))
OR (c(0) AND p0(k) AND p1(k) AND p2(k));
j := k*4 ;
for i in 0 to 3 loop
Y(i+j) <= A1(i+j) XOR A2(i+j) XOR c(i) ;
end loop;
k := 1;
c(0) := cc(k);
c(1) := g0(k) OR (c(0) AND p0(k));
c(2) := g1(k) OR (g0(k) AND p1(k)) OR (c(0) AND p0(k) AND p1(k));
j := k*4 ;
for i in 0 to 2 loop
Y(i+j) <= A1(i+j) XOR A2(i+j) XOR c(i) ;
end loop;
end process;
end BEHAVIORAL;
configuration CFG_QDS_ADDER_BEHAVIORAL of QDS_ADDER is
for BEHAVIORAL
end for;
end CFG_QDS_ADDER_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/qds_adder.vhd | VHDL | lgpl | 2,330 |
-- VHDL Model Created from SGE Symbol mux.sym -- May 27 12:33:10 1998
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MUX is
Port ( A : In std_logic_vector (56 downto 0);
B : In std_logic_vector (56 downto 0);
SEL : In std_logic;
Z : Out std_logic_vector (56 downto 0) );
end MUX;
architecture BEHAVIORAL of MUX is
begin
process (A, B, SEL)
begin
if ( SEL = '1' ) then
Z <= A ;
else
Z <= B ;
end if;
end process;
end BEHAVIORAL;
configuration CFG_MUX_BEHAVIORAL of MUX is
for BEHAVIORAL
end for;
end CFG_MUX_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/mux.vhd | VHDL | lgpl | 762 |
monitor -SAIF -name mntr -hier E/UUT -input power_rtl.saif -output uut.saif
run 33960 > run.out
quit
| 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/code/divr4_rec_retiming/cmd_saif.inc | PHP | lgpl | 102 |
\documentclass[11pt,a4paper]{article}
\usepackage{url,,}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{amsmath}
\usepackage{multirow}
\usepackage{listings}
\usepackage{fullpage}
\usepackage{fancyhdr,a4wide}
\usepackage{makeidx}
\usepackage{placeins}
%\usepackage[procnames,noindent]{lgrind}
\lstset{ %
language=VHDL, % choose the language of the code
basicstyle=\footnotesize, % the size of the fonts that are used for the code
showstringspaces=false, % underline spaces within strings
%numbers=left, % where to put the line-numbers
%numberstyle=\footnotesize, % the size of the fonts that are used for the line-numbers
%stepnumber=1, % the step between two line-numbers. If it's 1 each line will be numbered
%numbersep=5pt, % how far the line-numbers are from the code
%backgroundcolor=\color{white}, % choose the background color. You must add \usepackage{color}
showspaces=false, % show spaces within strings adding particular underscores
showtabs=false, % show tabs within strings adding particular underscores
escapeinside={\%*}{*)} % if you want to add a comment within your code
}
\begin{document}
\begin{titlepage}
\thispagestyle{fancy}
\lhead{}
\chead{
\large{\textit{
Informatics and Mathematical Modelling\\
Technical University of Denmark}}}
\rhead{}
\rule{0pt}{50pt}
\vspace{3cm}
\begin{center}
\huge{\textbf{02207 : Advanced Digital Design Techniques}}\\
\vspace{1cm}
\huge{Exercise of Retiming}\\
\vspace{1cm}
\huge{\textit{LAB 3}}\\
\vspace{1cm}
\huge{Group \textit{dt07}}\\
\end{center}
\vspace{4cm}
\begin{flushright}
\LARGE{Markku Eerola (s053739)}\\
\vspace{0.3cm}
\LARGE{Rajesh Bachani (s061332)}\\
\vspace{0.3cm}
\LARGE{Josep Renard (s071158)}\\
\end{flushright}
\cfoot{\today}
\end{titlepage}
%\begin{abstract}
%\centering
%Abstract to be created.
%\end{abstract}
%-----------------------------------------------------------
\newpage
\tableofcontents
\newpage
% --- I thought about a different document structure which I feel would be more natural. I removed the subsections from the introduction and added the cell counts and dissipated power into the sections about the designs. Read it through and think which you prefer.
\section{Introduction}
This document is report of the third exercise on DTU course Advanced Digital Design. In this exercise we studied the concept of retiming using a digit recurrence division implementation with radix-4 and carry-save adder.
In course of the exercise we examined two designs, the original design for digit recurrence division and the retimed design. We first compiled, simulated and synthesized the original design to get the power report and cell counts for it. We then modified the VHDL code for the original design to retime the recurrence. This retimed design was then also compiled, simulated and synthesized to get the power report and cell counts.
In the following sections we will briefly explain the concept of retiming, present the original circuit and the retimed circuit and the power dissipated and cells used in both. In the last section we will discuss the results.
\subsection{Authors by Section}
\begin{itemize}
\item \textit{Rajesh Bachani - Simulating the retimed design, cell counts for original, Report: introduction, retimed design}
\item \textit{Josep Renard - Editing the top level, cell counts for retimed, Report: retiming, discussion}
\item \textit{Markku Eerola - Synthesis and power reports, Report: original design, appendices}
\end{itemize}
\section{Retiming}
Retiming is an optimizing technique where structural location of registers is manually moved without affecting the functionality of the circuit in order to improve its performance. This is done either by removing a register from each input to a block and adding a register to each output, or by adding registers to the inputs and removing registers from the outputs.
In our case the motivation for retiming was to create slack on a non-critical path, and to have the synthesizer substitute HS cells with LL cells on this path thus lowering the overall power dissipation in the whole circuit. According to the lecture slides the circuit we were studying should gain approximately 30\% power savings from this kind of retiming.
\section{Original Design}
The original design upon which we aimed to improve with the retiming is presented in figure 1.
\begin{figure}[h]
\centering
\includegraphics[width=4in]{./noretiming.PNG}
\caption{Digit recurrence division} \label{fig:noretiming}
\end{figure}
The Sel. function -block implements the quotient digit selection function. The selection function determines a 4-bit quotient digit using 3 most significant bits of the divisor d and 7 most significant bits from the results stored in registers Ws and Wc.
The MUX block selects the input for the divisor multiplication between the dividend, which is used only in the initialization phase of the division algorithm, and the result of the substraction of the quotient digit/divisor multiplication result from the dividend. The substraction result is stored in register Ws.
The Multiple gen. -block implements the divisor multiplication ie. it multiplies the divisor d with the 4-bit quotient digit. This block is basically a multiplexer.
The Carry Save Adder -block implements the substraction of the result of the divisor multiplication from the dividend. The substraction is done with a carry-save adder as the name of the block suggests.
The registers Ws and Wc store the carry and the sum from the carry-save adder respectively.
The critical path of this circuit is marked with red arrows in the figure 1.
\FloatBarrier
\subsection{Power dissipation and cell count}
The Synopsys VSS Simulator was used to annotate the switching activity based on a testbench and test vectors. This switching activity was used by Design Vision to estimate the power dissipation within the circuit. The results can be seen in table~1 for each composing block. The actual report is in appendix~A. The table also shows the number of HVT and SVT cells in each composing block.
\begin{table}[h]
\caption{Power dissipation in original circuit (uW) and cell count}
\begin{center}
\begin{tabular}{|l|l|l|l|l|l|}
\hline
\textbf{Block} & \textbf{P static} & \textbf{P dynamic} & \textbf{P total} & \textbf{SVT cells} & \textbf{HVT cells}\\ \hline
Control & 0.8 & 35.7 & 36.5 & 21 & 24 \\ \hline
Mux & 0.12 & 28.3 & 28.4 & 1 & 57 \\ \hline
Mult. gen. & 6.8 & 124.0 & 130.8 & 226 & 51 \\ \hline
CSA & 7.4 & 196.4 & 203.8 & 141 & 35 \\ \hline
SEL & 3.3 & 68.1 & 71.4 & 80 & 5 \\ \hline
Reg W & 13.3 & 336.7 & 350.0 & 315 & 8 \\ \hline \hline
Total & 31.7 & 789.2 & 820.9 & 784 & 180 \\ \hline
\end{tabular}
\end{center}
\label{table:powerOriginal}
\end{table}
\FloatBarrier
\section{Retimed Design}
The retimed design is presented in figure 2.
\begin{figure}[h]
\centering
\includegraphics[width=4in]{./retiming.PNG}
\caption{Digit recurrence division retimed}
\label{fig:retiming}
\end{figure}
Since only the most significant bits of sum and carry are used in the quotient digit selection it makes sense to separate the most significant bits from the least significant bits to separate structural slices. This is done in the VHDL code by disconnecting the quotient digit selection block from the W registers thus \textit{removing registers from the inputs} and adding new registers to the output of the block. This frees the W registers from the most significant slice. By also separating the implementation of the most significant bits of the adder and the multiplie generation from the implementation for the less significant bits more of the design is freed from the critical path.
We achieved these changes by editing the top-level VHDL file for the original design. We disconnected the higher bits of register W from the selection function and introduced the register q as a new component. We connected the high bits of CSA directly to the selection function and connected the new register between the selection and the multiple generation.
These changes do not affect the functionality of the circuit, but by dividing the implementation to most significant and least significant slices we get two paths. The critical path is marked with red arrows in the figure~2. The delay on the critical path is T(SEL)+T(reg q)+T(mux)+T(CSA). The delay on the non-critical path is at maximum T(reg W)+T(mux)+T(CSA). From this it can be seen that the non critical path has some slack which the synthesizer should be able to use to optimize the least significant slice for power, namely by replacing HS cells with LL cells.
\FloatBarrier
\subsection{Power dissipation and cell count}
Just as with the original design the Synopsys VSS Simulator was used to annotate the switching activity based on a testbench and test vectors. This switching activity was again used by Design Vision to estimate the power dissipation within the circuit. The results can be seen in table~2 for each composing block. The actual report is in appendix~B. The table also shows the number of HVT and SVT cells in each composing block.
\begin{table}[h]
\caption{Power dissipation in retimed circuit (uW) and cell count}
\begin{center}
\begin{tabular}{|l|l|l|l|l|l|} % I don't know if this is the correct way, I was just guessing from what I saw in the lab2 tex file
\hline
\textbf{Block} & \textbf{P static} & \textbf{P dynamic} & \textbf{P total} & \textbf{SVT cells} & \textbf{HVT cells}\\ \hline
Control & 0.9 & 34.9 & 35.8 & 21 & 22 \\ \hline
Mux & 0.3 & 24.9 & 25.2 & 9 & 53 \\ \hline
Mult. gen. & 0.7 & 48.1 & 48.8 & 20 & 154 \\ \hline
CSA & 1.6 & 116.3 & 117.9 & 26 & 150 \\ \hline
SEL & 3.0 & 64.2 & 67.2 & 71 & 7 \\ \hline
Reg W & 3.0 & 258.4 & 261.4 & 118 & 116 \\ \hline
Reg q & 0.7 & 16.3 & 17.0 & 20 & 3 \\ \hline \hline
Total & 10.2 & 563.1 & 573.3 & 285 & 505 \\ \hline
\end{tabular}
\end{center}
\label{table:powerRetimed}
\end{table}
\FloatBarrier
\section{Discussion}
% Discussion on the results
Looking at the results from tables 1 and 2 we can see, that separating the design in two slices has reduced power dissipation. This split makes it possible for the synthesizing tool, Synopsys Design Vision, to optimize the slice with the critical path for speed and the non-critical part for low power. The composing blocks that have been separated from the critical path have been optimized for power by the synthesizer and this shows in SVT cells being replaced by HVT cells. Since these separated blocks contain the large register W and most of the CSA and multiple generator from the original design, the power savings are notable. Namely, we save approximately 30\% - which was expected.
\newpage
\section{Appendix A: Power reports from the original design}
% Add the files
\lstinputlisting[frame=trbl, caption={Power Report - Original}] {../code/divr4_rec_noretiming/power_report_breakdown.txt}
\newpage
\section{Appendix B: Power reports from the retimed design}
% Add the files
\lstinputlisting[frame=trbl, caption={Power Report - Retimed}] {../code/divr4_rec_retiming/power_report_breakdown.txt}
%----------------------------------------------------------- the old structure is below
%\section{Introduction}
%This document is report of the third exercise on DTU course Advanced Digital Design. In this exercise we studied the concept of retiming using digit recurrence division implementation with radix-4 and carry-save adder.
%In the introductory section we will briefly explain the concept of retiming, the original circuit and the retimed circuit. In the next section we will explain how the retimed circuit was implemented ie. what changes we made to the original circuit. In the last two sections we will present the power reports and cell counts of the two designs and discuss the results.
%\subsection{Retiming}
% to just explain what retiming is - the concept and its purpose. that we need to retime circuits manually - so that the synthesizer could identify two different paths easily and perform low power synthesis for the non critical path.
%Retiming is an optimizing technique where structural location of registers is manually moved without affecting the functionality of the circuit in order to improve its performance. This is done either by removing a register from each input to a block and adding a register to each output, or by adding registers to the inputs and removing registers from the outputs.
%In our case the motivation for retiming was to create slack on a non-critical path, and to have the synthesizer substitute HS cells with LL cells on this path thus lowering the overall power dissipation in the whole circuit. According to the lecture slides the circuit we were studying should gain approximately 30\% power savings from this kind of retiming.
%\subsection{Simple Design for Division}
%explain briefly the circuit for division. mention about the critical path in the circuit.
%The original design upon which we aimed to improve with the retiming is presented in figure 1.
%\begin{figure}
% \centering
% \includegraphics{./noretiming.PNG}
% \caption{Figure 1: Digit recurrence division}
% \label{fig:noretiming}
%\end{figure}
%The Sel. function -block implements the quotient digit selection function. The selection function determines a 4-bit quotient digit using 3 most significant bits of the divisor d and 7 most significant bits from the results stored in registers Ws and Wc.
%The MUX block selects the input for the divisor multiplication between the dividend, which is used only in the initialization phase of the division algorithm, and the result of the substraction of the quotient digit/divisor multiplication result from the dividend. The substraction result is stored in register Ws.
%The Multiple gen. -block implements the divisor multiplication ie. it multiplies the divisor d with the 4-bit quotient digit. This block is basically a multiplexer.
%The Carry Save Adder -block implements the substraction of the result of the divisor multiplication from the dividend. The substraction is done with a carry-save adder as the name of the block suggests.
%The registers Ws and Wc store the carry and the sum from the carry-save adder respectively.
%The critical path of this circuit is marked with red arrows in the figure 1.
%\subsection{Design for Division using Retiming}
%explain in detail the circuit for division using retiming. we should argue what is expected from this, and how we should be able to save power in this.
%The retimed design is presented in figure 2.
%\begin{figure}
% \centering
% \includegraphics{./noretiming.PNG}
% \caption{Figure 1: Digit recurrence division retimed}
% \label{fig:retiming}
%\end{figure}
%Since only the most significant bits of sum and carry are used in the quotient digit selection it makes sense to separate the most significant bits from the least significant bits to separate structural slices. This is done in the VHDL code by disconnecting the quotient digit selection block from the W registers thus \textit{removing registers from the inputs} and adding new registers to the output of the block. This frees the W registers from the most significant slice. By also separating the implementation of the most significant bits of the adder and the multiplie generation from the implementation for the less significant bits more of the design is freed from the critical path.
%These changes do not affect the functionality of the circuit, but by dividing the implementation to most significant and least significant slices we get two paths. The critical path is marked with red arrows in the figure 2. The delay on the critical path is T(SEL)+T(reg q)+T(mux)+T(CSA). The delay on the non-critical path is at maximum T(reg W)+T(mux)+T(CSA). From this it can be seen that the non critical path has some slack which the synthesizer should be able to use to optimize the least significant slice for power, namely by replacing HS cells with LL cells.
%\subsection{Authors by Section}
%\begin{itemize}
%\item \textit{Rajesh Bachani}
%\item \textit{Josep Renard}
%\item \textit{Markku Eerola}
%\end{itemize}
%\section{Implementation of Division using Retiming}
%\label{section:impl}
%explain specifically the changes that were implemented for using the retimed circuit for division. this could also include parts of the VHDL, but mostly it should concentrate on highlighting the changes in terms of the connections between the components.
%we would not have any section for implementation, giving the code, since there is a lot of code in the whole thing. so we should try and just explain all the changes in the code here only.
%\section{Power Report and Cell Count}
%\label{section:power}
% put the reports from the power analysis of both the designs here. also, give a short recap kind of a table here. also, write about the cells here.
%\section{Discussion}
%\label{section:discussion}
%discuss the report at length here. we should clearly justify the results, by explaining why the SVT cells count has reduced and HVT has increased, and why the cell internal power has reduced. ofcourse this was expected, but nice explanation is needed here.
%\section{Appendix A: The power reports}
%\label{section:reports}
\end{document} | 02207-work-groupdt07 | trunk/Lab Work/Exercise 3/report/dt07_lab3.tex | TeX | lgpl | 17,427 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity MUX_4 is
port (
SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C: in STD_LOGIC_VECTOR(7 downto 0);
SIG: out STD_LOGIC_VECTOR(7 downto 0));
end MUX_4;
architecture BEH_MUX of MUX_4 is
begin
SEL_PROCESS: process (SEL,A,B,C)
begin
case SEL is
when "00" => SIG <= A;
when "01" => SIG <= B;
when "10" => SIG <= C;
when others => SIG <= (others => '0');
end case;
end process SEL_PROCESS;
end BEH_MUX; | 02207-work-groupdt07 | trunk/Project/code/MUX_4.vhd | VHDL | lgpl | 581 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity TB_multiplier is
end TB_multiplier;
architecture TB of TB_multiplier is
component multiplier is
port( num1, num2: in std_logic_vector(7 downto 0);
product: out std_logic_vector(7 downto 0)
);
end component;
signal T_num1, T_num2: std_logic_vector(7 downto 0);
signal T_product: std_logic_vector(7 downto 0);
begin
U_UT: multiplier port map (T_num1, T_num2, T_product);
process
begin
T_num1 <= "11111111";
T_num2 <= "11111111";
wait for 20 ns;
--assert(T_product="1001") report "Error detected!"
--severity warning;
T_num1 <= "00001100";
T_num2 <= "00000010";
wait for 20 ns;
--assert(T_product="0000") report "Error detected!"
--severity warning;
T_num1 <= "00000010";
T_num2 <= "00000011";
wait for 20 ns;
--assert(T_product="0100") report "Error detected!"
--severity warning;
T_num1 <= "11111100";
T_num2 <= "00000010";
wait for 20 ns;
--assert(T_product="0110") report "Error detected!"
--severity warning;
wait;
end process;
end TB;
-----------------------------------------------------------
configuration CFG_TB of TB_multiplier is
for TB
end for;
end CFG_TB;
-----------------------------------------------------------
| 02207-work-groupdt07 | trunk/Project/code/tb_multiplier.vhd | VHDL | lgpl | 1,370 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- two 4-bit inputs and one 8-bit outputs
entity multiplier is
port( num1, num2: in std_logic_vector(7 downto 0);
product: out std_logic_vector(7 downto 0)
);
end multiplier;
architecture SCHEMATIC of multiplier is
signal P0: std_logic_vector(15 downto 0);
signal P1: std_logic_vector(15 downto 0);
signal P2: std_logic_vector(15 downto 0);
signal P3: std_logic_vector(15 downto 0);
signal P4: std_logic_vector(15 downto 0);
signal P5: std_logic_vector(15 downto 0);
signal P6: std_logic_vector(15 downto 0);
signal P7: std_logic_vector(15 downto 0);
signal A1: std_logic_vector(15 downto 0);
signal A2: std_logic_vector(15 downto 0);
signal A3: std_logic_vector(15 downto 0);
signal A4: std_logic_vector(15 downto 0);
signal A5: std_logic_vector(15 downto 0);
signal A6: std_logic_vector(15 downto 0);
signal A7: std_logic_vector(15 downto 0);
signal A8: std_logic_vector(15 downto 0);
signal A9: std_logic_vector(15 downto 0);
signal A0: std_logic_vector(15 downto 0);
signal B1: std_logic_vector(15 downto 0);
signal B2: std_logic_vector(15 downto 0);
signal B3: std_logic_vector(15 downto 0);
signal B4: std_logic_vector(15 downto 0);
signal B5: std_logic_vector(15 downto 0);
signal carry_ex1,carry_ex2,carry_ex3,carry_ex4,
carry_ex5,carry_ex6,carry_ex7: std_logic;
signal ca: std_logic;
component csa15bit
port ( A : In std_logic_vector (15 downto 0);
B : In std_logic_vector (15 downto 0);
C : In std_logic_vector (15 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (15 downto 0);
Y : Out std_logic_vector (15 downto 0) );
end component;
component ADDER_M
port ( A : In std_logic_vector (15 downto 0);
B : In std_logic_vector (15 downto 0);
C: In std_logic_vector(15 downto 0);
Z: In std_logic_vector(15 downto 0));
end component;
component parcial
port ( M1: in std_logic_vector(7 downto 0);
M2: in std_logic_vector(7 downto 0);
O1: out std_logic_vector(15 downto 0);
O2: out std_logic_vector(15 downto 0);
O3: out std_logic_vector(15 downto 0);
O4: out std_logic_vector(15 downto 0);
O5: out std_logic_vector(15 downto 0);
O6: out std_logic_vector(15 downto 0);
O7: out std_logic_vector(15 downto 0);
O8: out std_logic_vector(15 downto 0) );
end component;
component CRA_15 is
port( A : In std_logic_vector (15 downto 0);
B : In std_logic_vector (15 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Y : Out std_logic_vector (15 downto 0) );
end component;
begin
ca<='0';
I_PAR : parcial
Port Map(
M1=>num1,
M2=>num2 ,
O1(15 downto 0)=>P0(15 downto 0),
O2(15 downto 0)=>P1(15 downto 0),
O3(15 downto 0)=>P2(15 downto 0),
O4(15 downto 0)=>P3(15 downto 0),
O5(15 downto 0)=>P4(15 downto 0),
O6(15 downto 0)=>P5(15 downto 0),
O7(15 downto 0)=>P6(15 downto 0),
O8(15 downto 0)=>P7(15 downto 0)
);
I_CSA1 : csa15bit
Port Map (
A(15 downto 0)=>P0(15 downto 0),
B(15 downto 0)=>P1(15 downto 0),
C(15 downto 0)=>P2(15 downto 0),
Cin=>ca,
Cout=>carry_ex1,
Z(15 downto 0)=>A0(15 downto 0),
Y(15 downto 0)=>A1(15 downto 0)
);
I_CSA2 : csa15bit
Port Map (
A(15 downto 0)=>P3(15 downto 0),
B(15 downto 0)=>P4(15 downto 0),
C(15 downto 0)=>P5(15 downto 0),
Cin=>ca,
Cout=>carry_ex2,
Z(15 downto 0)=>A2(15 downto 0),
Y(15 downto 0)=>A3(15 downto 0)
);
I_CSA3 : csa15bit
Port Map (
A(15 downto 0)=>A0(15 downto 0),
B(15 downto 0)=>A1(15 downto 0),
C(15 downto 0)=>A2(15 downto 0),
Cin=>carry_ex1,
Cout=>carry_ex3,
Z(15 downto 0)=>A4(15 downto 0),
Y(15 downto 0)=>A5(15 downto 0)
);
I_CSA4 : csa15bit
Port Map (
A(15 downto 0)=>A3(15 downto 0),
B(15 downto 0)=>P6(15 downto 0),
C(15 downto 0)=>P7(15 downto 0),
Cin=>carry_ex2,
Cout=>carry_ex4,
Z(15 downto 0)=>A6(15 downto 0),
Y(15 downto 0)=>A7(15 downto 0)
);
I_CSA5 : csa15bit
Port Map (
A(15 downto 0)=>A4(15 downto 0),
B(15 downto 0)=>A5(15 downto 0),
C(15 downto 0)=>A6(15 downto 0),
Cin=>carry_ex3,
Cout=>carry_ex5,
Z(15 downto 0)=>A8(15 downto 0),
Y(15 downto 0)=>A9(15 downto 0)
);
I_CSA6 : csa15bit
Port Map (
A(15 downto 0)=>A7(15 downto 0),
B(15 downto 0)=>A8(15 downto 0),
C(15 downto 0)=>A9(15 downto 0),
Cin=>carry_ex4,
Cout=>carry_ex6,
Z(15 downto 0)=>B1(15 downto 0),
Y(15 downto 0)=>B2(15 downto 0)
);
I_CRA : CRA_15
Port Map (
A(15 downto 0)=>B1(15 downto 0),
B(15 downto 0)=>B2(15 downto 0),
Cin=>carry_ex5,
Cout=>carry_ex7,
Y(15 downto 0)=>B3(15 downto 0)
);
product(7 downto 0)<= B3(7 downto 0);
end SCHEMATIC;
| 02207-work-groupdt07 | trunk/Project/code/Multiplier.vhd | VHDL | lgpl | 6,087 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity REG is
port(
D : in std_logic_vector(7 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(7 downto 0));
end entity REG;
architecture BEH_REG of REG is
begin
p0: process (Clock, Reset) is
begin
if (Reset = '0') then
Q <= (others => '0');
elsif ((CLOCK = '1') AND (CLOCK'EVENT)) then
Q <= D;
end if;
end process p0;
end BEH_REG; | 02207-work-groupdt07 | trunk/Project/code/REG.vhd | VHDL | lgpl | 558 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity FSM_out_3 is
port (
clock: in std_logic;
reset: in std_logic;
read_address: out std_logic_vector(15 downto 0);
write_address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
sel: out std_logic_vector(1 downto 0)
);
end FSM_out_3;
architecture BEH_FSM_out_3 of FSM_out_3 is
type state_type is (init, init_out_memory_1, init_out_memory_2, h_init_1, h_init_2,
h_read_1, h_read_write, h_read_write_2, h_write_1, h_wait_1, h_wait_2,
v_init_1, v_init_2, v_read_1, v_read_write, v_write_1, v_wait_1, v_wait_2, exit_in);
signal next_state, current_state: state_type;
begin
state_reg: process(clock, reset)
begin
if (reset='0') then
current_state <= init;
elsif (clock'event and clock='1') then
current_state <= next_state;
end if;
end process;
comb_logic: process(current_state)
variable addr_h: INTEGER;
variable addr_v: INTEGER;
variable x: INTEGER;
variable y: INTEGER;
variable temp_address: INTEGER;
variable counter: INTEGER;
variable rwcount: INTEGER;
variable sel_num: INTEGER;
begin
case current_state is
when init =>
x := 257;
counter := 1;
rwcount := 1;
sel_num := 0;
next_state <= init_out_memory_1;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when init_out_memory_1 =>
can_write <= '1';
sel_num := 3;
sel <= conv_std_logic_vector(sel_num,2);
write_address <= conv_std_logic_vector(counter,16);
next_state <= init_out_memory_2;
counter := counter + 1;
when init_out_memory_2 =>
can_write <= '1';
write_address <= conv_std_logic_vector(counter,16);
if(counter = 65536) then
next_state <= h_init_1;
counter := 1;
can_write <= '0';
write_address <= (others => '0');
sel_num := 0;
sel <= conv_std_logic_vector(sel_num,2);
else
next_state <= init_out_memory_1;
counter := counter + 1;
sel_num := 3;
sel <= conv_std_logic_vector(sel_num,2);
end if;
when h_init_1 =>
if(counter = 27) then
counter := 1;
next_state <= h_read_1;
addr_h := x;
else
next_state <= h_init_2;
end if;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
counter := counter + 1;
when h_init_2 =>
counter := counter + 1;
next_state <= h_init_1;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when h_read_1 =>
next_state <= h_read_write;
can_read <= '1';
can_write <= '0';
read_address <= conv_std_logic_vector(addr_h,16);
write_address <= (others => '0');
sel <= conv_std_logic_vector(sel_num,2);
sel_num := sel_num + 1;
when h_read_write =>
next_state <= h_write_1;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when h_write_1 =>
rwcount := rwcount + 1;
if(rwcount > 3) then
if(x > 65277) then
x := 2;
next_state <= v_init_1;
counter := 1;
rwcount := 1;
sel_num := 0;
elsif((addr_h mod 256) = 0) then
x := addr_h + 1;
next_state <= h_init_1;
else
next_state <= h_wait_1;
end if;
rwcount := 1;
sel_num := 0;
else
next_state <= h_read_1;
end if;
can_read <= '0';
can_write <= '1';
read_address <= (others => '0');
write_address <= conv_std_logic_vector(addr_h,16);
addr_h := addr_h + 1 ;
-- wait for 3 clock cycles - till FSM1 reads the next 3 pixels
when h_wait_1 =>
counter := counter + 1;
if(counter > 3) then
counter := 1;
x := x + 1;
addr_h := x;
next_state <= h_read_1;
else
next_state <= h_wait_2;
end if;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when h_wait_2 =>
counter := counter + 1;
next_state <= h_wait_1;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
---------------------------------------------
--- States defining the Vertical Movement ---
---------------------------------------------
when v_init_1 =>
counter := counter + 1;
if(counter > 27) then
counter := 1;
next_state <= v_read_1;
addr_v := x;
else
next_state <= v_init_2;
end if;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when v_init_2 =>
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
counter := counter + 1;
next_state <= v_init_1;
when v_read_1 =>
next_state <= v_read_write;
can_read <= '1';
can_write <= '0';
read_address <= conv_std_logic_vector(addr_v,16);
write_address <= (others => '0');
sel <= conv_std_logic_vector(sel_num,2);
sel_num := sel_num + 1;
when v_read_write =>
next_state <= v_write_1;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when v_write_1 =>
rwcount := rwcount + 1;
if(rwcount > 3) then
rwcount := 1;
sel_num := 0;
if(addr_v > 65280) then
x := x + 1;
if(x = 256) then
next_state <= exit_in;
else
addr_v := x;
next_state <= v_init_1;
end if;
else
next_state <= v_wait_1;
end if;
else
next_state <= v_read_1;
end if;
can_read <= '0';
can_write <= '1';
read_address <= (others => '0');
write_address <= conv_std_logic_vector(addr_v,16);
addr_v := addr_v + 256;
-- wait for 3 clock cycles - till FSM1 reads the next 3 pixels
when v_wait_1 =>
counter := counter + 1;
if(counter > 3) then
counter := 1;
next_state <= v_read_1;
else
next_state <= v_wait_2;
end if;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when v_wait_2 =>
counter := counter + 1;
next_state <= v_wait_1;
addr_v := addr_v - 512;
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
when exit_in =>
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
next_state <= exit_in;
when others =>
can_read <= '0';
can_write <= '0';
read_address <= (others => '0');
write_address <= (others => '0');
next_state <= init;
end case;
end process;
end architecture BEH_FSM_out_3; | 02207-work-groupdt07 | trunk/Project/code/FSM_out.vhd | VHDL | lgpl | 9,373 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ADDER_2 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
Z : Out std_logic_vector (7 downto 0));
end ADDER_2;
architecture BEH_ADDER_2 of ADDER_2 is
signal sum_out : std_logic_vector(8 downto 0);
begin
sum_out <= ('0' & A) + ('0' & B);
Z(0) <= sum_out(8) OR sum_out(0);
Z(1) <= sum_out(8) OR sum_out(1);
Z(2) <= sum_out(8) OR sum_out(2);
Z(3) <= sum_out(8) OR sum_out(3);
Z(4) <= sum_out(8) OR sum_out(4);
Z(5) <= sum_out(8) OR sum_out(5);
Z(6) <= sum_out(8) OR sum_out(6);
Z(7) <= sum_out(8) OR sum_out(7);
end BEH_ADDER_2;
--architecture BEH_ADDER_2 of ADDER_2 is
-- signal sum_out : unsigned(9 downto 0);
-- begin
--
-- process(A, B)
--
-- constant zeros: unsigned(1 downto 0) := (others => '0');
-- variable sum_int: INTEGER;
--
-- begin
-- sum_out <= (zeros & unsigned(A)) + (zeros & unsigned(B));
-- sum_int := conv_integer(sum_out);
--
-- if(sum_int < 255) then
-- Z <= std_logic_vector(sum_out(7 downto 0));
-- else
-- Z <= "11111111";
-- end if;
--
-- end process;
--end BEH_ADDER_2;
--
| 02207-work-groupdt07 | trunk/Project/code/Adder_2.vhd | VHDL | lgpl | 1,258 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity fsm_out_tb is
end fsm_out_tb;
architecture FSM_TB of fsm_out_tb is
signal T_clock: std_logic;
signal T_reset: std_logic;
signal T_can_read: std_logic;
signal T_can_write: std_logic;
signal T_read_address: std_logic_vector(15 downto 0);
signal T_write_address: std_logic_vector(15 downto 0);
signal T_sel: std_logic_vector(1 downto 0);
signal t_read_addr: NATURAL;
signal t_write_addr: NATURAL;
signal t_sel_num: NATURAL;
component FSM_out_3 is
port (
clock: in std_logic;
reset: in std_logic;
read_address: out std_logic_vector(15 downto 0);
write_address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
sel: out std_logic_vector(1 downto 0)
);
end component FSM_out_3;
begin
U_fsm: fsm_out_3 port map(T_clock, T_reset, T_read_address, T_write_address, T_can_read, T_can_write, T_sel);
process
begin
T_clock <= '1';
wait for 1 ns;
T_clock <= '0';
wait for 1 ns;
end process;
process
variable counter: integer;
begin
T_reset <= '0';
wait for 2 ns;
-- can put assert statements to assure something holds
T_reset <= '1';
loop
T_read_addr <= conv_integer(T_read_address);
T_write_addr <= conv_integer(T_write_address);
T_sel_num <= conv_integer(T_sel);
wait for 2 ns;
end loop;
end process;
end FSM_TB;
----------------------------------------------------------------------
configuration CFG_TB_FSM_out_3 of FSM_out_TB is
for FSM_TB
end for;
end CFG_TB_FSM_out_3;
-----------------------------------------------------------------------
| 02207-work-groupdt07 | trunk/Project/code/TB_FSM_out.vhd | VHDL | lgpl | 1,809 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity MUX_2 is
port (
SEL: in STD_LOGIC;
A,B: in STD_LOGIC_VECTOR(15 downto 0);
SIG: out STD_LOGIC_VECTOR(15 downto 0));
end MUX_2;
architecture BEH_MUX_2 of MUX_2 is
begin
SEL_PROCESS: process (SEL,A,B)
begin
case SEL is
when '0' => SIG <= A;
when '1' => SIG <= B;
when others => SIG <= (others => '0');
end case;
end process SEL_PROCESS;
end BEH_MUX_2;
| 02207-work-groupdt07 | trunk/Project/code/MUX_2.vhd | VHDL | lgpl | 527 |
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_filter/uutp/clock
add wave -noupdate -format Logic /tb_filter/uutp/reset
add wave -noupdate -format Logic /tb_filter/uutp/read_in_mem
add wave -noupdate -format Logic /tb_filter/uutp/write_in_mem
add wave -noupdate -format Logic /tb_filter/uutp/read_out_mem
add wave -noupdate -format Logic /tb_filter/uutp/write_out_mem
add wave -noupdate -format Literal /tb_filter/uutp/read_addr_in_mem
add wave -noupdate -format Literal /tb_filter/uutp/read_addr_out_mem
add wave -noupdate -format Literal /tb_filter/uutp/write_addr_out_mem
add wave -noupdate -format Literal /tb_filter/uutp/data_in_1
add wave -noupdate -format Literal /tb_filter/uutp/data_in_2
add wave -noupdate -format Literal /tb_filter/uutp/data_out
add wave -noupdate -format Literal /tb_filter/uutp/filter
add wave -noupdate -format Logic /tb_filter/uutp/disable_filter
add wave -noupdate -format Logic /tb_filter/uutp/disable_to_cache
add wave -noupdate -format Literal /tb_filter/uutp/cache_bits
add wave -noupdate -format Literal /tb_filter/uutp/filter_bits
add wave -noupdate -format Literal /tb_filter/uutp/mult1_out
add wave -noupdate -format Literal /tb_filter/uutp/mult2_out
add wave -noupdate -format Literal /tb_filter/uutp/mult3_out
add wave -noupdate -format Literal /tb_filter/uutp/mult4_out
add wave -noupdate -format Literal /tb_filter/uutp/mult5_out
add wave -noupdate -format Literal /tb_filter/uutp/mult6_out
add wave -noupdate -format Literal /tb_filter/uutp/mult7_out
add wave -noupdate -format Literal /tb_filter/uutp/mult8_out
add wave -noupdate -format Literal /tb_filter/uutp/mult9_out
add wave -noupdate -format Literal /tb_filter/uutp/add1_out
add wave -noupdate -format Literal /tb_filter/uutp/add2_out
add wave -noupdate -format Literal /tb_filter/uutp/add3_out
add wave -noupdate -format Literal /tb_filter/uutp/select_adder
add wave -noupdate -format Literal /tb_filter/uutp/mux_out
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {131205 ns} 0}
configure wave -namecolwidth 62
configure wave -valuecolwidth 40
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {131193 ns} {131225 ns}
| 02207-work-groupdt07 | trunk/Project/code/wave_read&write_by_processor.do | Stata | lgpl | 2,505 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity Processor_3a is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
Read_In_Mem: Out std_logic;
Write_In_Mem : Out std_logic;
Read_Out_Mem: Out std_logic;
Write_Out_Mem: Out std_logic;
Read_Addr_In_Mem: Out std_logic_vector(15 downto 0);
Read_Addr_Out_Mem: Out std_logic_vector(15 downto 0);
Write_Addr_Out_Mem: Out std_logic_vector(15 downto 0);
Data_in_1: In std_logic_vector(7 downto 0);
Data_in_2: In std_logic_vector(7 downto 0);
Data_out: Out std_logic_vector(7 downto 0);
Filter: In std_logic_vector(7 downto 0);
disable_filter: In std_logic
);
end Processor_3a;
architecture SCHEMATIC_PROC_3a of Processor_3a is
component csa8bit is
Port ( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
C : In std_logic_vector (7 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (7 downto 0);
Y : Out std_logic_vector (7 downto 0) );
end component;
component CRA_8 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Y : Out std_logic_vector (7 downto 0) );
end component;
component REG is
port(
D : in std_logic_vector(7 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(7 downto 0));
end component REG;
component SHIFTREG is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
disable : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (71 downto 0) );
end component SHIFTREG;
component Multiplier
Port (
num1 : In std_logic_vector (7 downto 0);
num2 : In std_logic_vector (7 downto 0);
product : Out std_logic_vector (7 downto 0) );
end component Multiplier;
component MUX_4 is
port (
SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C: in STD_LOGIC_VECTOR(7 downto 0);
SIG: out STD_LOGIC_VECTOR(7 downto 0));
end component MUX_4;
component MUX_2 is
port (
SEL: in STD_LOGIC;
A,B: in STD_LOGIC_VECTOR(15 downto 0);
SIG: out STD_LOGIC_VECTOR(15 downto 0));
end component MUX_2;
component MUX_2_1 is
port (
SEL: in STD_LOGIC;
A,B: in STD_LOGIC;
SIG: out STD_LOGIC);
end component MUX_2_1;
component FSM_in_3
port (
clock: in std_logic;
reset: in std_logic;
address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
disable_cache: out std_logic
);
end component FSM_in_3;
component FSM_out_3
port (
clock: in std_logic;
reset: in std_logic;
read_address: out std_logic_vector(15 downto 0);
write_address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
sel: out std_logic_vector(1 downto 0)
);
end component FSM_out_3;
signal disable_to_cache: std_logic;
signal cache_bits: std_logic_vector(71 downto 0);
signal filter_bits: std_logic_vector(71 downto 0);
signal mult1_out: std_logic_vector(7 downto 0);
signal mult2_out: std_logic_vector(7 downto 0);
signal mult3_out: std_logic_vector(7 downto 0);
signal mult4_out: std_logic_vector(7 downto 0);
signal mult5_out: std_logic_vector(7 downto 0);
signal mult6_out: std_logic_vector(7 downto 0);
signal mult7_out: std_logic_vector(7 downto 0);
signal mult8_out: std_logic_vector(7 downto 0);
signal mult9_out: std_logic_vector(7 downto 0);
signal add1_out: std_logic_vector(7 downto 0);
signal add1_out1: std_logic_vector(7 downto 0);
signal add1_out2: std_logic_vector(7 downto 0);
signal add2_out: std_logic_vector(7 downto 0);
signal add2_out1: std_logic_vector(7 downto 0);
signal add2_out2: std_logic_vector(7 downto 0);
signal add3_out: std_logic_vector(7 downto 0);
signal add3_out1: std_logic_vector(7 downto 0);
signal add3_out2: std_logic_vector(7 downto 0);
constant zeros: unsigned(7 downto 0) := (others => '0');
signal select_adder: std_logic_vector(1 downto 0);
signal mux_out: std_logic_vector(7 downto 0);
signal co1,co2,co3,cou1,cou2,cou3,cfi: std_logic;
begin
fsm_input:
FSM_in_3 port map(CLOCK, RESET, Read_Addr_In_Mem, Read_In_Mem, Write_In_Mem, disable_to_cache);
fsm_output:
FSM_out_3 port map(CLOCK, RESET, Read_Addr_Out_Mem, Write_Addr_Out_Mem, Read_Out_Mem, Write_Out_Mem, select_adder);
cache:
SHIFTREG port map(CLOCK, RESET, disable_to_cache, Data_in_1, cache_bits);
filtermask:
SHIFTREG port map(CLOCK, RESET, disable_filter, Filter, filter_bits);
Mult1:
Multiplier port map(cache_bits(7 downto 0), filter_bits(7 downto 0),mult1_out);
Mult2:
Multiplier port map(cache_bits(15 downto 8), filter_bits(15 downto 8),mult2_out);
Mult3:
Multiplier port map(cache_bits(23 downto 16), filter_bits(23 downto 16),mult3_out);
Mult4:
Multiplier port map(cache_bits(31 downto 24), filter_bits(31 downto 24),mult4_out);
Mult5:
Multiplier port map(cache_bits(39 downto 32), filter_bits(39 downto 32),mult5_out);
Mult6:
Multiplier port map(cache_bits(47 downto 40), filter_bits(47 downto 40),mult6_out);
Mult7:
Multiplier port map(cache_bits(55 downto 48), filter_bits(55 downto 48),mult7_out);
Mult8:
Multiplier port map(cache_bits(63 downto 56), filter_bits(63 downto 56),mult8_out);
Mult9:
Multiplier port map(cache_bits(71 downto 64), filter_bits(71 downto 64),mult9_out);
Add1:
csa8bit port map(mult1_out, mult2_out, mult3_out,'0',co1, add1_out1,add1_out2);
Add1_2:
CRA_8 port map(add1_out1,add1_out2,co1,cou1,add1_out);
Add2:
csa8bit port map(mult4_out, mult5_out, mult6_out, '0',co2, add2_out1,add2_out2);
Add2_2:
CRA_8 port map(add2_out1,add2_out2,co2,cou2,add2_out);
Add3:
csa8bit port map(mult7_out, mult8_out, mult9_out, '0',co3, add3_out1,add3_out2);
Add3_2:
CRA_8 port map(add3_out1,add3_out2,co3,cou3,add3_out);
Multiplexer:
Mux_4 port map(select_adder, add3_out, add2_out, add1_out, data_out);
Add_new_value:
CRA_8 port map(Data_in_2, mux_out,'0',cfi, Data_out);
end SCHEMATIC_PROC_3a;
| 02207-work-groupdt07 | trunk/Project/code/Processor_3_.vhd | VHDL | lgpl | 7,097 |
-----------------------------------------------------------------
-- test bench for FSM (ESD book figure 2.7)
-- by Weijun Zhang, 04/2001
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity fsm_tb is -- entity declaration
end fsm_tb;
-----------------------------------------------------------------
architecture TB of fsm_tb is
signal T_a: std_logic;
signal T_clock: std_logic;
signal T_reset: std_logic;
signal T_x: std_logic;
component seq_design
port( a: in std_logic;
clock: in std_logic;
reset: in std_logic;
x: out std_logic
);
end component;
begin
U_fsm: seq_design port map(T_a, T_clock, T_reset, T_x);
process
begin
T_clock <= '1'; -- clock cycle 10 ns
wait for 5 ns;
T_clock <= '0';
wait for 5 ns;
end process;
process
variable err_cnt: integer :=0;
begin
-- case 1
T_reset <= '1';
wait for 20 ns;
assert (T_x='0') report "Failed Case 1" severity error;
if (T_x/='0') then
err_cnt:=err_cnt+1;
end if;
-- case 2
T_reset <= '0';
T_a <= '0';
wait for 20 ns;
assert (T_x='0') report "Failed Case 2" severity error;
if (T_x/='0') then
err_cnt:=err_cnt+1;
end if;
-- case 3
wait for 30 ns;
T_a <= '1';
wait for 35 ns;
assert (T_x='1') report "Failed Case 3" severity error;
if (T_x/='1') then
err_cnt:=err_cnt+1;
end if;
-- case 4
wait for 70 ns;
T_reset <= '1';
wait for 10 ns;
assert (T_x='0') report "Failed Case 4" severity error;
if (T_x/='0') then
err_cnt:=err_cnt+1;
end if;
-- summary of all the tests
if (err_cnt=0) then
assert false
report "Testbench of FSM completely successfully!"
severity note;
else
assert true
report "Something wrong, Check again pls!"
severity error;
end if;
wait;
end process;
end TB;
----------------------------------------------------------------------
configuration CFG_TB of fsm_TB is
for TB
end for;
end CFG_TB;
-----------------------------------------------------------------------
| 02207-work-groupdt07 | trunk/Project/code/TB_Sample_FSM.vhd | VHDL | lgpl | 2,174 |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity FSM_in_3 is
port (
clock: in std_logic;
reset: in std_logic;
address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
disable_cache: out std_logic
);
end FSM_in_3;
architecture BEH_FSM_in_3 of FSM_in_3 is
type state_type is (init, init_in_memory_1, init_in_memory_2, h_read_1, h_read_2,
h_read_3, h_cache, v_cache, h_wait, h_temp,
v_read_1, v_read_2, v_read_3, v_wait, v_temp, exit_in);
signal next_state, current_state: state_type;
begin
state_reg: process(clock, reset)
begin
if (reset='0') then
current_state <= init;
elsif (clock'event and clock='1') then
current_state <= next_state;
end if;
end process;
comb_logic: process(current_state)
variable addr_h: INTEGER;
variable addr_v: INTEGER;
variable x: INTEGER;
variable y: INTEGER;
variable temp_address: INTEGER;
variable counter: INTEGER;
begin
case current_state is
when init =>
x := 1;
y := 1;
counter := 1;
disable_cache <= '1';
next_state <= init_in_memory_1;
can_read <= '0';
can_write <= '0';
address <= (others => '0');
when init_in_memory_1 =>
next_state <= init_in_memory_2;
can_write <= '1';
address <= conv_std_logic_vector(counter,16);
counter := counter + 1;
when init_in_memory_2 =>
can_write <= '1';
address <= conv_std_logic_vector(counter,16);
if(counter = 65536) then
next_state <= h_read_1;
counter := 1;
can_write <= '0';
address <= (others => '0');
else
next_state <= init_in_memory_1;
counter := counter + 1;
end if;
when h_read_1 =>
next_state <= h_read_2;
can_read <= '1';
addr_h := x;
address <= conv_std_logic_vector(addr_h,16);
disable_cache <= '1';
when h_read_2 =>
next_state <= h_read_3;
can_read <= '1';
addr_h := addr_h + 256;
address <= conv_std_logic_vector(addr_h,16);
disable_cache <= '0';
when h_read_3 =>
next_state <= h_cache;
can_read <= '1';
addr_h := addr_h + 256;
x := x + 1;
address <= conv_std_logic_vector(addr_h,16);
disable_cache <= '0';
when h_cache =>
disable_cache <= '0';
can_read <= '0';
next_state <= h_wait;
when h_wait =>
counter := counter + 1;
can_read <= '0';
address <= (others => '0');
next_state <= h_temp;
disable_cache <= '1';
when h_temp =>
counter := counter + 1;
can_read <= '0';
address <= (others => '0');
disable_cache <= '1';
if(counter > 8) then
counter := 1;
if(x > 65024) then
x := 1;
next_state <= v_read_1;
else
next_state <= h_read_1;
end if;
else
next_state <= h_wait;
end if;
when v_read_1 =>
disable_cache <= '1';
next_state <= v_read_2;
can_read <= '1';
addr_v := x;
address <= conv_std_logic_vector(addr_v,16);
when v_read_2 =>
next_state <= v_read_3;
can_read <= '1';
addr_v := addr_v + 1;
address <= conv_std_logic_vector(addr_v,16);
disable_cache <= '0';
when v_read_3 =>
next_state <= v_cache;
can_read <= '1';
addr_v := addr_v + 1;
x := x + 256;
address <= conv_std_logic_vector(addr_v,16);
disable_cache <= '0';
when v_cache =>
disable_cache <= '0';
can_read <= '0';
next_state <= v_wait;
when v_wait =>
counter := counter + 1;
next_state <= v_temp;
can_read <= '0';
address <= (others => '0');
disable_cache <= '1';
when v_temp =>
counter := counter + 1;
if(counter > 8) then
counter := 1;
if(x > 65536) then
y := y + 1;
x := y;
end if;
if(y = 255) then
next_state <= exit_in;
else
next_state <= v_read_1;
end if;
else
next_state <= v_wait;
end if;
can_read <= '0';
address <= (others => '0');
when exit_in =>
can_read <= '0';
address <= (others => '0');
next_state <= exit_in;
disable_cache <= '1';
when others =>
disable_cache <= '1';
next_state <= init;
can_read <= '0';
address <= (others => '0');
end case;
end process;
end BEH_FSM_in_3;
configuration CFG_FSM_in_3_BEHAVIORAL of FSM_in_3 is
for BEH_FSM_in_3
end for;
end CFG_FSM_in_3_BEHAVIORAL; | 02207-work-groupdt07 | trunk/Project/code/FSM_in.vhd | VHDL | lgpl | 5,782 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ADDER_3 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
C : In std_logic_vector (7 downto 0);
Z : Out std_logic_vector (7 downto 0));
end ADDER_3;
architecture BEH_ADDER_3 of ADDER_3 is
signal sum_out : std_logic_vector(9 downto 0);
begin
sum_out <= ("00" & A) + ("00" & B) + ("00" & C);
Z(0) <= sum_out(9) OR sum_out(8) OR sum_out(0);
Z(1) <= sum_out(9) OR sum_out(8) OR sum_out(1);
Z(2) <= sum_out(9) OR sum_out(8) OR sum_out(2);
Z(3) <= sum_out(9) OR sum_out(8) OR sum_out(3);
Z(4) <= sum_out(9) OR sum_out(8) OR sum_out(4);
Z(5) <= sum_out(9) OR sum_out(8) OR sum_out(5);
Z(6) <= sum_out(9) OR sum_out(8) OR sum_out(6);
Z(7) <= sum_out(9) OR sum_out(8) OR sum_out(7);
end BEH_ADDER_3;
--architecture BEH_ADDER_3 of ADDER_3 is
-- signal sum_out : unsigned(9 downto 0);
-- signal temp : std_logic_vector(7 downto 0);
-- signal c2, c1: std_logic;
-- begin
--
--
-- process(A, B, C)
--
-- constant zeros: unsigned(1 downto 0) := (others => '0');
-- variable sum_int: INTEGER;
--
-- begin
-- sum_out <= (zeros & unsigned(A)) + (zeros & unsigned(B)) + (zeros & unsigned(C));
-- sum_int := conv_integer(sum_out);
-- if(sum_int < 255) then
-- Z <= std_logic_vector(sum_out(7 downto 0));
-- else
-- Z <= "11111111";
-- end if;
-- end process;
--end BEH_ADDER_3; | 02207-work-groupdt07 | trunk/Project/code/Adder_3.vhd | VHDL | lgpl | 1,549 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CRA_8 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Y : Out std_logic_vector (7 downto 0) );
end CRA_8;
architecture RTL of CRA_8 is
begin
process(A,B,Cin)
variable tempC : std_logic_vector (8 downto 0);
variable P : std_logic_vector (7 downto 0);
variable G : std_logic_vector (7 downto 0);
variable Yaux : std_logic_vector (7 downto 0);
begin
tempC(0):= Cin;
for i in 0 to 7 loop
P(i):= A(i) XOR B(i);
G(i):= A(i) AND B(i);
Yaux(i):= P(i) xor tempC(i);
tempC(i+1):=G(i) OR (tempC(i) AND P(i));
end loop;
if (tempC(8)='1') then
Yaux(7 downto 0):= "11111111";
end if;
Y(7 downto 0)<= Yaux(7 downto 0);
Cout<=tempC(8);
end process;
end RTL;
configuration CFG_CRA_8_BEHAVIORAL of CRA_8 is
for RTL
end for;
end CFG_CRA_8_BEHAVIORAL; | 02207-work-groupdt07 | trunk/Project/code/CRA_8.vhd | VHDL | lgpl | 1,406 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity SHIFTREG is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
disable : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (71 downto 0) );
end SHIFTREG;
architecture BEH_SHIFTREG of SHIFTREG is
begin
process(RESET,CLOCK)
variable i,j,k,l : integer;
begin
if ( RESET = '0' ) then
for i in 0 to 71 loop
q(i) <= '0';
end loop;
elsif ((CLOCK = '1') AND (CLOCK'EVENT)) then
if(disable='0') then
for i in 71 downto 8 loop
q(i-8) <= q(i);
end loop;
q(71 downto 64) <= qk;
else
for i in 71 downto 0 loop
q(i) <= q(i);
end loop;
end if;
end if;
end process;
end BEH_SHIFTREG; | 02207-work-groupdt07 | trunk/Project/code/SHIFTREG.vhd | VHDL | lgpl | 1,059 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity Processor is
Port ( CLOCK : In std_logic;
D : In std_logic_vector (2047 downto 0);
RESET : In std_logic;
Qj : Out std_logic_vector (2047 downto 0) );
end Processor;
architecture SCHEMATIC of Processor is
signal Y1 : std_logic_vector(2047 downto 0);
signal Y2 : std_logic_vector(2047 downto 0);
signal Y3 : std_logic_vector(2047 downto 0);
signal D3 : std_logic_vector(2047 downto 0);
signal F : std_logic_vector(71 downto 0);
signal M1 : std_logic_vector(7 downto 0);
signal M2 : std_logic_vector(7 downto 0);
signal M3 : std_logic_vector(7 downto 0);
signal M4 : std_logic_vector(7 downto 0);
signal M5 : std_logic_vector(7 downto 0);
signal M6 : std_logic_vector(7 downto 0);
signal M7 : std_logic_vector(7 downto 0);
signal M8 : std_logic_vector(7 downto 0);
signal M9 : std_logic_vector(7 downto 0);
signal A1 : std_logic_vector(7 downto 0);
signal A2 : std_logic_vector(7 downto 0);
signal A3 : std_logic_vector(7 downto 0);
signal E1 : std_logic_vector(7 downto 0);
signal E2 : std_logic_vector(7 downto 0);
signal E3 : std_logic_vector(7 downto 0);
signal CLR : std_logic;
signal LOAD : std_logic;
signal SIGN : std_logic;
signal GND : std_logic;
variable n : integer;-- it has to be iniciate to 0.
component ADDER
Port ( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
C : In std_logic_vector (7 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (7 downto 0)
);
end component;
component reg_ld
GENERIC(n : integer);
Port ( AS : In std_logic_vector (n downto 0);
RESET : In std_logic;
CLOCK : In std_logic;
LOAD : In std_logic;
ZS : Out std_logic_vector (n downto 0)
);
end component;
component Multiplier
Port ( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
Z : Out std_logic_vector (7 downto 0) );
end component;
begin
GND <= '0';
--The three rows of the image are stored on the registers
Reg_IN1: reg_ld Generic Map (n=>2047)
Port Map(in(here the row from the memory but l don't know how), RESET=>RESET,CLOCK=>CLOCK,LOAD=>LOAD, ZS=>Y1);
--Y1 the first row
Reg_IN2: reg_ld Generic Map (n=>2047)
Port Map(in(the same), RESET=>RESET,CLOCK=>CLOCK,LOAD=>LOAD, ZS=>Y2);
--Y2 the second row
Reg_IN3: reg_ld Generic Map (n=>2047)
Port Map(in(the same), RESET=>RESET,CLOCK=>CLOCK,LOAD=>LOAD, ZS=>Y3);
--Y3 the third row
Reg_MASK: reg_ld Generic Map (n=>71)
Port Map (in(the filter imput can be a vector with the values), RESET=>RESET,CLOCK=>CLOCK,LOAD=>LOAD, ZS=>F);
--A is the pixel value of the image and B is the filter value.
Mult1: Multiplier
Port Map (A=>Y1(n+7 downto n), B=>M(7 downto 0),Z=>M1 );
Mult2: Multiplier
Port Map (A=>Y2(n+7 downto n), B=>M(31 downto 24),Z=>M2 );
Mult3: Multiplier
Port Map (A=>Y3(n+7 downto n), B=>M(55 downto 48),Z=>M3 );
n=>n+8;
Mult4: Multiplier
Port Map (A=>Y1(n+7 downto n), B=>M(15 downto 8),Z=>M4 );
Mult5: Multiplier
Port Map (A=>Y2(n+7 downto n), B=>M(39 downto 32),Z=>M5 );
Mult6: Multiplier
Port Map (A=>Y3(n+7 downto n), B=>M(63 downto 56),Z=>M6 );
n=>n+8;
Mult7: Multiplier
Port Map (A=>Y1(n+7 downto n), B=>M(23 downto 16),Z=>M7 );
Mult8: Multiplier
Port Map (A=>Y2(n+7 downto n), B=>M(47 downto 40),Z=>M8 );
Mult9: Multiplier
Port Map (A=>Y3(n+7 downto n), B=>M(71 downto 64),Z=>M9 );
n=>n+8;
--The adders, adding the previous values multiplieds
Add1: ADDER
Port Map (A=>M1,B=>M2,C=>M3,Z=>A1);
Add2: ADDER
Port Map (A=>M4,B=>M5,C=>M6,Z=>A2);
Add3: ADDER
Port Map (A=>M7,B=>M8,C=>M9,Z=>A3);
--Update the old image value, only on the vertical pass.
--maybe we have to add a signal to enable it on vertical.
Add_update1: ADDER
Port Map (A=>A1,B=>image_pos_out,C=>0,Z=>E1);
Add_update2: ADDER
Port Map (A=>A2,B=>image_pos_out,C=>0,Z=>E2);
Add_update3: ADDER
Port Map (A=>A3,B=>image_pos_out,C=>0,Z=>E3);
-- On the first pass, initialized 0, on the second we take the values
-- from de memory and store the updates from Add_update1,2,3
-- A1,A2,A3 if horizontal or E1,E2,E3 if vertical
Reg_OUT: reg_ld Generic Map (n=>2047)
Port Map(in, RESET=>RESET,CLOCK=>CLOCK,LOAD=>LOAD, out);
end SCHEMATIC;
configuration CFG_proc_SCHEMATIC of divr4_rec is
for SCHEMATIC
for Reg_IN1, Reg_IN2, Reg_IN3, Reg_MASK, Reg_OUT : reg_ld
use configuration WORK.CFG_reg_ld_BEHAVIORAL;
end for;
for Add1, Add2, Add3, Add_update1, Add_update2, Add_Update3: csa32LSBs
use configuration WORK.CFG_ADDER_BEHAVIORAL;
end for;
for Mult1, Mult2, Mult3, Mult4, Mult5, Mult6, Mult7,Mult8, Mult9, : MULT
use configuration WORK.CFG_Multiplier_BEHAVIORAL;
end for;
end for;
end CFG_proc_SCHEMATIC;
| 02207-work-groupdt07 | trunk/Project/code/archive/proc.vhd | VHDL | lgpl | 5,589 |
------------------------------------------------------------------------
-- Project : 8404129 Hardware Description Languages
-- Group number : 32
-- Group : Markku Eerola 177065
-- markku.eerola@tut.fi
-- Vesa Salander 168075
-- vesa.salander@tut.fi
-- Date : 22.10.2004
-- File : ctrl_fsm.vhdl
-- Design : a state machine, v 1.11
------------------------------------------------------------------------
-- Description : Implementation of the state machine specified in the
-- exercise specification. Fixed it to have two processes
-- instead of one. Removed the unnecessary IF - THEN.
------------------------------------------------------------------------
-- $Log$
------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CTRL_FSM IS
GENERIC (
busw_g : INTEGER := 4 -- bus width
);
PORT (
clk : IN STD_LOGIC; -- clock signal
rst_n : IN STD_LOGIC; -- reset, active low
data_in : IN STD_LOGIC_VECTOR(busw_g-1 DOWNTO 0); -- data in
alu_ctrl_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- alu control
pc_ctrl_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) -- pc control
);
END CTRL_FSM;
ARCHITECTURE RTL OF CTRL_FSM IS
-- !! Important !! --
-- enumerated data type states describes the states of the state
-- machine
TYPE states IS (init, fetch, add, sub, jmp, wait_s);
-- attribute enum_encoding can be used to specify the state machine
-- encoding
ATTRIBUTE ENUM_ENCODING : STRING;
-- specify one hot state encoding
ATTRIBUTE ENUM_ENCODING OF states :
-- INIT FETCH ADD SUB JMP WAIT_S
TYPE IS "000001 000010 000100 001000 010000 100000";
-- intermediate signal current_state holds the current state of the
-- state machine
SIGNAL current_state : states;
-- interm. signal next_state represents the calculated next state of
-- the state machine
SIGNAL next_state : states;
-- !! End of Important !! --
BEGIN -- RTL
-- the clocked process
clocked : PROCESS(clk, rst_n)
BEGIN -- the clocked process
IF (rst_n = '0') THEN
current_state <= init;
ELSIF rising_edge(clk) THEN
current_state <= next_state;
END IF;
END PROCESS clocked;
combinatorial : PROCESS(current_state, data_in)
BEGIN -- the combinatorial process
-- the case-structure for the state machine
CASE current_state IS
-- initial state
WHEN init =>
pc_ctrl_out <= "01";
alu_ctrl_out <= "00";
next_state <= fetch;
-- fetching data from data_in and acting to it
WHEN fetch =>
pc_ctrl_out <= "00";
alu_ctrl_out <= "00";
IF (data_in = "0000") THEN
next_state <= init;
ELSIF (data_in = "0001") THEN
next_state <= add;
ELSIF (data_in = "0010") THEN
next_state <= sub;
ELSIF (data_in = "0011") THEN
next_state <= jmp;
ELSE
next_state <= init;
END IF;
-- adding
WHEN add =>
pc_ctrl_out <= "01";
alu_ctrl_out <= "01";
next_state <= init;
-- substracting
WHEN sub =>
pc_ctrl_out <= "01";
alu_ctrl_out <= "10";
next_state <= init;
-- jumping
WHEN jmp =>
pc_ctrl_out <= "10";
alu_ctrl_out <= "00";
next_state <= wait_s;
-- waiting
WHEN wait_s =>
pc_ctrl_out <= "10";
alu_ctrl_out <= "00";
next_state <= init;
-- any other
WHEN OTHERS =>
pc_ctrl_out <= "00";
alu_ctrl_out <= "00";
next_state <= init;
-- case closed
END CASE;
END PROCESS combinatorial;
END RTL;
| 02207-work-groupdt07 | trunk/Project/code/archive/ctrl_fsm.vhdl | VHDL | lgpl | 4,159 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity Processor_3 is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
Read_In_Mem: Out std_logic;
Read_Out_Mem: Out std_logic;
Write_Out_Mem: Out std_logic;
Read_Addr_In_Mem: Out std_logic_vector(15 downto 0);
Read_Addr_Out_Mem: Out std_logic_vector(15 downto 0);
Write_Addr_Out_Mem: Out std_logic_vector(15 downto 0);
Data_in: In std_logic_vector(7 downto 0);
Data_out: Out std_logic_vector(7 downto 0);
Filter: In std_logic_vector(7 downto 0);
disable_filter: In std_logic
);
end Processor_3;
architecture SCHEMATIC_PROC_3 of Processor_3 is
component csa8bit is
Port ( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
C : In std_logic_vector (7 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (7 downto 0);
Y : Out std_logic_vector (7 downto 0) );
end component;
component CRA_8 is
port( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Y : Out std_logic_vector (7 downto 0) );
end component;
component SHIFTREG is
Port ( CLOCK : In std_logic;
RESET : In std_logic;
disable : In std_logic;
QK : In std_logic_vector (7 downto 0);
Q : InOut std_logic_vector (71 downto 0) );
end component SHIFTREG;
component Multiplier
Port (
num1 : In std_logic_vector (7 downto 0);
num2 : In std_logic_vector (7 downto 0);
product : Out std_logic_vector (7 downto 0) );
end component Multiplier;
component MUX_4 is
port (
SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C: in STD_LOGIC_VECTOR(7 downto 0);
SIG: out STD_LOGIC_VECTOR(7 downto 0));
end component MUX_4;
component MUX_2 is
port (
SEL: in STD_LOGIC;
A,B: in STD_LOGIC_VECTOR(15 downto 0);
SIG: out STD_LOGIC_VECTOR(15 downto 0));
end component MUX_2;
component MUX_2_1 is
port (
SEL: in STD_LOGIC;
A,B: in STD_LOGIC;
SIG: out STD_LOGIC);
end component MUX_2_1;
component FSM_in_3
port (
clock: in std_logic;
reset: in std_logic;
address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
disable_cache: out std_logic
);
end component FSM_in_3;
component FSM_out_3
port (
clock: in std_logic;
reset: in std_logic;
read_address: out std_logic_vector(15 downto 0);
write_address: out std_logic_vector(15 downto 0);
can_read: out std_logic;
can_write: out std_logic;
sel: out std_logic_vector(1 downto 0)
);
end component FSM_out_3;
signal disable_to_cache: std_logic;
signal Read_fsm_in: std_logic;
signal Read_fsm_out: std_logic;
signal Read_Addr_in: std_logic_vector(15 downto 0);
signal Read_Addr_fsm_out: std_logic_vector(15 downto 0);
signal cache_bits: std_logic_vector(71 downto 0);
signal filter_bits: std_logic_vector(71 downto 0);
signal mult1_out: std_logic_vector(7 downto 0);
signal mult2_out: std_logic_vector(7 downto 0);
signal mult3_out: std_logic_vector(7 downto 0);
signal mult4_out: std_logic_vector(7 downto 0);
signal mult5_out: std_logic_vector(7 downto 0);
signal mult6_out: std_logic_vector(7 downto 0);
signal mult7_out: std_logic_vector(7 downto 0);
signal mult8_out: std_logic_vector(7 downto 0);
signal mult9_out: std_logic_vector(7 downto 0);
signal add1_out: std_logic_vector(7 downto 0);
signal add1_out1: std_logic_vector(7 downto 0);
signal add1_out2: std_logic_vector(7 downto 0);
signal add2_out: std_logic_vector(7 downto 0);
signal add2_out1: std_logic_vector(7 downto 0);
signal add2_out2: std_logic_vector(7 downto 0);
signal add3_out: std_logic_vector(7 downto 0);
signal add3_out1: std_logic_vector(7 downto 0);
signal add3_out2: std_logic_vector(7 downto 0);
constant zeros: unsigned(7 downto 0) := (others => '0');
signal select_adder: std_logic_vector(1 downto 0);
signal mux_out: std_logic_vector(7 downto 0);
signal co1,co2,co3,cou1,cou2,cou3,cfi: std_logic;
begin
fsm_input:
FSM_in_3 port map(CLOCK, RESET, Read_Addr_In_Mem, Read_In_Mem, disable_to_cache);
fsm_output:
FSM_out_3 port map(CLOCK, RESET, Read_Addr_Out_Mem, Write_Addr_Out_Mem, Read_Out_Mem, Write_Out_Mem, select_adder);
cache:
SHIFTREG port map(CLOCK, RESET, disable_to_cache, Data_in, cache_bits);
filtermask:
SHIFTREG port map(CLOCK, RESET, disable_filter, Filter, filter_bits);
Mult1:
Multiplier port map(cache_bits(7 downto 0), filter_bits(7 downto 0),mult1_out);
Mult2:
Multiplier port map(cache_bits(15 downto 8), filter_bits(15 downto 8),mult2_out);
Mult3:
Multiplier port map(cache_bits(23 downto 16), filter_bits(23 downto 16),mult3_out);
Mult4:
Multiplier port map(cache_bits(31 downto 24), filter_bits(31 downto 24),mult4_out);
Mult5:
Multiplier port map(cache_bits(39 downto 32), filter_bits(39 downto 32),mult5_out);
Mult6:
Multiplier port map(cache_bits(47 downto 40), filter_bits(47 downto 40),mult6_out);
Mult7:
Multiplier port map(cache_bits(55 downto 48), filter_bits(55 downto 48),mult7_out);
Mult8:
Multiplier port map(cache_bits(63 downto 56), filter_bits(63 downto 56),mult8_out);
Mult9:
Multiplier port map(cache_bits(71 downto 64), filter_bits(71 downto 64),mult9_out);
Add1:
csa8bit port map(mult1_out, mult2_out, mult3_out,'0',co1, add1_out1,add1_out2);
Add1_2:
CRA_8 port map(add1_out1,add1_out2,co1,cou1,add1_out);
Add2:
csa8bit port map(mult4_out, mult5_out, mult6_out, '0',co2, add2_out1,add2_out2);
Add2_2:
CRA_8 port map(add2_out1,add2_out2,co2,cou2,add2_out);
Add3:
csa8bit port map(mult7_out, mult8_out, mult9_out, '0',co3, add3_out1,add3_out2);
Add3_2:
CRA_8 port map(add3_out1,add3_out2,co3,cou3,add3_out);
Multiplexer:
Mux_4 port map(select_adder, add3_out, add2_out, add1_out, mux_out);
Add_new_value:
CRA_8 port map(Data_in, mux_out,'0',cfi, Data_out);
end SCHEMATIC_PROC_3;
| 02207-work-groupdt07 | trunk/Project/code/archive/Processor_3_.vhd | VHDL | lgpl | 6,985 |
-- -----------------------------------------------------------------
-- Model for SRAM
-- use at your own risk
-- do not complain if it does not work properly
-- AN
--
-- ----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
--
-- cache direct-mapped 1 word block (1 Kbyte): index 8, byte offset 2
-- see Patterson&Hennessy for cache specifications
-- work is 32 bits
--
-- This model uses two data busses: D_BUS is from Main Memory to the Cache
-- DB is from Cache to CPU
entity SRAM_1W1K is
Port ( ENABLE : In std_logic;
INDEX : In std_logic_vector (9 downto 2); -- 1 and 0: byte offset
RW : In std_logic;
D_BUS : In std_logic_vector (0 to 31); -- bit 0 is msb
DB : Out std_logic_vector (0 to 31); -- bit 0 is msb
READY : Out std_logic );
end SRAM_1W1K;
architecture BEHAVIORAL of SRAM_1W1K is
begin
memory : process(index,enable)
-- delays for simulation
constant c_tpd : time := 3 ns;
constant c_tac : time := 7 ns;
constant low_adr : integer := 0;
constant high_adr : integer := 256 - 1; -- 2^8
type memory_array is array (low_adr to high_adr) of std_logic_vector(0 to 31);
variable mem : memory_array;
variable address : integer;
begin
--
-- initialize outputs
--
db <= (others => 'Z') after c_tpd;
ready <= '0' after c_tpd;
--
-- wait until ram is enabled
--
if (enable = '1') then
ready <= '0' after c_tpd;
--
-- decode address and perform command if selected
--
address := CONV_INTEGER(index);
if address >= low_adr and address <= high_adr then
if (rw = '0') then -- write cycle
mem(address) := d_bus(0 to 31);
-- wait for c_tac; -- write access time
ready <= '1' after 10 ns; -- c_tpd + c_tac;
elsif (rw = '1') then -- read cycle
-- wait for c_tac; -- read access time
db <= mem(address) after c_tac;
ready <= '1' after (c_tpd + c_tac);
else
assert FALSE
report "cache SRAM: RW line undefined"
severity warning;
end if;
else
assert FALSE
report "cache SRAM: memory access to undefined memory region"
severity warning;
end if;
end if;
end process;
end BEHAVIORAL;
configuration CFG_SRAM_1W1K_BEHAVIORAL of SRAM_1W1K is
for BEHAVIORAL
end for;
end CFG_SRAM_1W1K_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Project/code/archive/sram_1w1k.vhd | VHDL | lgpl | 2,684 |
library IEEE;
use IEEE.std_logic_1164.all;
entity csa32LSBs is
Port ( A : In std_logic_vector (7 downto 0);
B : In std_logic_vector (7 downto 0);
C : In std_logic_vector (7 downto 0);
Z : Out std_logic_vector (7 downto 0) );
end csa32LSBs;
architecture BEHAVIORAL of csa32LSBs is
begin
process(A, B, C)
variable p : std_logic_vector (7 downto 0) ;
variable g : std_logic_vector (7 downto 0) ;
variable Y : std_logic_vector (7 downto 0) ;
variable Cout : std_logic;
variable i : integer;
begin
for i in 0 to 7 loop
p(i) := A(i) XOR B(i) ;
g(i) := A(i) AND B(i) ;
end loop;
-- CARRY -----------------------------------
Y(0) <= 0;
for i in 0 to 6 loop
Y(i+1) <= g(i) OR (c(i) AND p(i));
end loop;
Cout <= g(n) OR (c(n) AND p(n));
-- SUM -------------------------------------
for i in 0 to 7 loop
Z(i) <= p(i) XOR c(i);
end loop;
if (Cout='1') then
Z(7 downto 0)<='11111111';
end if;
end process;
end BEHAVIORAL;
configuration CFG_csa32LSBs_BEHAVIORAL of csa32LSBs is
for BEHAVIORAL
end for;
end CFG_csa32LSBs_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Project/code/archive/csa32LSBs.vhd | VHDL | lgpl | 1,111 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADDER_TB is -- entity declaration
end ADDER_TB;
architecture TB of ADDER_TB is
component CRA is
port( A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
Cin: in std_logic;
Cout: out std_logic;
Y: out std_logic_vector(7 downto 0)
);
end component;
signal A, B: std_logic_vector(7 downto 0);
signal Cin,Cout: std_logic;
signal Y: std_logic_vector(7 downto 0);
begin
U_CRA: CRA port map (A, B, Cin, Cout, Y);
process
variable err_cnt: integer :=0;
begin
-- case 1
A <= "00000000";
B <= "00000011";
Cin<='0';
wait for 10 ns;
--assert (sum="00") report "Sum Error!" severity error;
--assert (carry='0') report "Carry Error!" severity error;
--if (sum/="00" or carry/='0') then
-- err_cnt:=err_cnt+1;
--end if;
-- case 2
A <= "11001111";
B <= "00110000";
Cin<='0';
wait for 10 ns;
--assert (sum="10") report "Sum Error!" severity error;
--assert (carry='1') report "Carry Error!" severity error;
--if (sum/="10" or carry/='1') then
-- err_cnt:=err_cnt+1;
--end if;
-- case 3
A <= "01000000";
B <= "10000000";
Cin<='0';
wait for 10 ns;
--assert (sum="11") report "Sum Error!" severity error;
--assert (carry='0') report "Carry Error!" severity error;
--if (sum/="11" or carry/='0') then
-- err_cnt:=err_cnt+1;
--end if;
-- case 4
A <= "10111111";
B <= "01000000";
Cin<='1';
wait for 10 ns;
--assert (sum="11") report "Sum Error!" severity error;
--assert (carry='0') report "Carry Error!" severity error;
--if (sum/="11" or carry/='0') then
-- err_cnt:=err_cnt+1;
--end if;
-- case 5
A <= "11111111";
B <= "00000001";
Cin<='0';
wait for 10 ns;
--assert (sum="10") report "Sum Error!" severity error;
--assert (carry='0') report "Carry Error!" severity error;
--if (sum/="10" or carry/='0') then
-- err_cnt:=err_cnt+1;
--end if;
end process;
end TB;
--------------------------------------------------------------------
configuration CFG_TB of ADDER_TB is
for TB
end for;
end CFG_TB;
-------------------------------------------------------------------- | 02207-work-groupdt07 | trunk/Project/code/archive/tb_CRA.vhd | VHDL | lgpl | 2,234 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity csa8bit is
Port ( A : In std_logic_vector (15 downto 0);
B : In std_logic_vector (15 downto 0);
C : In std_logic_vector (15 downto 0);
Cin : In std_logic;
Cout : Out std_logic;
Z : Out std_logic_vector (15 downto 0);
Y : Out std_logic_vector (15 downto 0) );
end csa8bit;
architecture BEHAVIORAL of csa8bit is
begin
process(A, B, C, Cin)
variable p : std_logic_vector (15 downto 0) ;
variable g : std_logic_vector (15 downto 0) ;
variable i : integer;
begin
for i in 0 to 15 loop
p(i) := A(i) XOR B(i) ;
g(i) := A(i) AND B(i) ;
end loop;
-- CARRY -----------------------------------
Y(0) <= Cin;
for i in 0 to 15-1 loop
Y(i+1) <= g(i) OR (c(i) AND p(i));
end loop;
Cout <= g(15) OR (c(15) AND p(15));
-- SUM -------------------------------------
for i in 0 to 15 loop
Z(i) <= p(i) XOR c(i);
end loop;
end process;
end BEHAVIORAL;
configuration CFG_csa8bit_BEHAVIORAL of csa8bit is
for BEHAVIORAL
end for;
end CFG_csa8bit_BEHAVIORAL;
| 02207-work-groupdt07 | trunk/Project/code/archive/CSA_8bit.vhd | VHDL | lgpl | 1,080 |