google-code-archive

Dataset card Data Studio Files Files and versions

Split (1)

train · 65.8M rows

code stringlengths 1 2.01M	repo_name stringlengths 3 62	path stringlengths 1 267	language stringclasses 231 values	license stringclasses 13 values	size int64 1 2.01M
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Changes from V3.2.3 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. Changes from V3.2.4 + Removed the use of the %0 parameter within the assembler macros and replaced them with hard coded registers. This will ensure the assembler does not select the link register as the temp register as was occasionally happening previously. + The assembler statements are now included in a single asm block rather than each line having its own asm block. Changes from V4.5.0 + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros and replaced them with portYIELD_FROM_ISR() macro. Application code should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() macros as per the V4.5.1 demo code. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE portLONG #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Architecture specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 8 #define portNOP() asm volatile ( "NOP" ); /-----------------------------------------------------------/ / Scheduler utilities. / / * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but * are included here for efficiency. An attempt to call one from * THUMB mode code will result in a compile time error. / #define portRESTORE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Set the LR to the task stack. / \ asm volatile ( \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "LDR LR, [R0] \n\t" \ \ / The critical nesting depth is the first item on the stack. / \ / Load it into the ulCriticalNesting variable. / \ "LDR R0, =ulCriticalNesting \n\t" \ "LDMFD LR!, {R1} \n\t" \ "STR R1, [R0] \n\t" \ \ / Get the SPSR from the stack. / \ "LDMFD LR!, {R0} \n\t" \ "MSR SPSR, R0 \n\t" \ \ / Restore all system mode registers for the task. / \ "LDMFD LR, {R0-R14}^ \n\t" \ "NOP \n\t" \ \ / Restore the return address. / \ "LDR LR, [LR, #+60] \n\t" \ \ / And return - correcting the offset in the LR to obtain the / \ / correct address. / \ "SUBS PC, LR, #4 \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } /-----------------------------------------------------------/ #define portSAVE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Push R0 as we are going to use the register. / \ asm volatile ( \ "STMDB SP!, {R0} \n\t" \ \ / Set R0 to point to the task stack pointer. / \ "STMDB SP,{SP}^ \n\t" \ "NOP \n\t" \ "SUB SP, SP, #4 \n\t" \ "LDMIA SP!,{R0} \n\t" \ \ / Push the return address onto the stack. / \ "STMDB R0!, {LR} \n\t" \ \ / Now we have saved LR we can use it instead of R0. / \ "MOV LR, R0 \n\t" \ \ / Pop R0 so we can save it onto the system mode stack. / \ "LDMIA SP!, {R0} \n\t" \ \ / Push all the system mode registers onto the task stack. / \ "STMDB LR,{R0-LR}^ \n\t" \ "NOP \n\t" \ "SUB LR, LR, #60 \n\t" \ \ / Push the SPSR onto the task stack. / \ "MRS R0, SPSR \n\t" \ "STMDB LR!, {R0} \n\t" \ \ "LDR R0, =ulCriticalNesting \n\t" \ "LDR R0, [R0] \n\t" \ "STMDB LR!, {R0} \n\t" \ \ / Store the new top of stack for the task. / \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "STR LR, [R0] \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } #define portYIELD_FROM_ISR() vTaskSwitchContext() #define portYIELD() asm volatile ( "SWI 0" ) /-----------------------------------------------------------/ / Critical section management. / / * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions in * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not * defined then the utilities are defined as macros here - as per other ports. / #ifdef THUMB_INTERWORK extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else #define portDISABLE_INTERRUPTS() \ asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #define portENABLE_INTERRUPTS() \ asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #endif / THUMB_INTERWORK / extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical(); #define portEXIT_CRITICAL() vPortExitCritical(); /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h	C	oos	10,512
// ---------------------------------------------------------------------------- // ATMEL Microcontroller Software Support - ROUSSET - // ---------------------------------------------------------------------------- // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // ---------------------------------------------------------------------------- // File Name : AT91SAM7X256.h // Object : AT91SAM7X256 definitions // Generated : AT91 SW Application Group 05/20/2005 (16:22:29) // // CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// // CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// // CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// // CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// // CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// // CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// // CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// // CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// // CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// // CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// // CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// // CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// // CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// // CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// // CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// // CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// // CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// // CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// // CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// // CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// // CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// // CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// // CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// // ---------------------------------------------------------------------------- #ifndef AT91SAM7X256_H #define AT91SAM7X256_H typedef volatile unsigned int AT91_REG;// Hardware register definition // *************************************************************************** // SOFTWARE API DEFINITION FOR System Peripherals // *************************************************************************** typedef struct _AT91S_SYS { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register AT91_REG Reserved2[45]; // AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved3[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved4[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register AT91_REG Reserved5[54]; // AT91_REG PIOA_PER; // PIO Enable Register AT91_REG PIOA_PDR; // PIO Disable Register AT91_REG PIOA_PSR; // PIO Status Register AT91_REG Reserved6[1]; // AT91_REG PIOA_OER; // Output Enable Register AT91_REG PIOA_ODR; // Output Disable Registerr AT91_REG PIOA_OSR; // Output Status Register AT91_REG Reserved7[1]; // AT91_REG PIOA_IFER; // Input Filter Enable Register AT91_REG PIOA_IFDR; // Input Filter Disable Register AT91_REG PIOA_IFSR; // Input Filter Status Register AT91_REG Reserved8[1]; // AT91_REG PIOA_SODR; // Set Output Data Register AT91_REG PIOA_CODR; // Clear Output Data Register AT91_REG PIOA_ODSR; // Output Data Status Register AT91_REG PIOA_PDSR; // Pin Data Status Register AT91_REG PIOA_IER; // Interrupt Enable Register AT91_REG PIOA_IDR; // Interrupt Disable Register AT91_REG PIOA_IMR; // Interrupt Mask Register AT91_REG PIOA_ISR; // Interrupt Status Register AT91_REG PIOA_MDER; // Multi-driver Enable Register AT91_REG PIOA_MDDR; // Multi-driver Disable Register AT91_REG PIOA_MDSR; // Multi-driver Status Register AT91_REG Reserved9[1]; // AT91_REG PIOA_PPUDR; // Pull-up Disable Register AT91_REG PIOA_PPUER; // Pull-up Enable Register AT91_REG PIOA_PPUSR; // Pull-up Status Register AT91_REG Reserved10[1]; // AT91_REG PIOA_ASR; // Select A Register AT91_REG PIOA_BSR; // Select B Register AT91_REG PIOA_ABSR; // AB Select Status Register AT91_REG Reserved11[9]; // AT91_REG PIOA_OWER; // Output Write Enable Register AT91_REG PIOA_OWDR; // Output Write Disable Register AT91_REG PIOA_OWSR; // Output Write Status Register AT91_REG Reserved12[85]; // AT91_REG PIOB_PER; // PIO Enable Register AT91_REG PIOB_PDR; // PIO Disable Register AT91_REG PIOB_PSR; // PIO Status Register AT91_REG Reserved13[1]; // AT91_REG PIOB_OER; // Output Enable Register AT91_REG PIOB_ODR; // Output Disable Registerr AT91_REG PIOB_OSR; // Output Status Register AT91_REG Reserved14[1]; // AT91_REG PIOB_IFER; // Input Filter Enable Register AT91_REG PIOB_IFDR; // Input Filter Disable Register AT91_REG PIOB_IFSR; // Input Filter Status Register AT91_REG Reserved15[1]; // AT91_REG PIOB_SODR; // Set Output Data Register AT91_REG PIOB_CODR; // Clear Output Data Register AT91_REG PIOB_ODSR; // Output Data Status Register AT91_REG PIOB_PDSR; // Pin Data Status Register AT91_REG PIOB_IER; // Interrupt Enable Register AT91_REG PIOB_IDR; // Interrupt Disable Register AT91_REG PIOB_IMR; // Interrupt Mask Register AT91_REG PIOB_ISR; // Interrupt Status Register AT91_REG PIOB_MDER; // Multi-driver Enable Register AT91_REG PIOB_MDDR; // Multi-driver Disable Register AT91_REG PIOB_MDSR; // Multi-driver Status Register AT91_REG Reserved16[1]; // AT91_REG PIOB_PPUDR; // Pull-up Disable Register AT91_REG PIOB_PPUER; // Pull-up Enable Register AT91_REG PIOB_PPUSR; // Pull-up Status Register AT91_REG Reserved17[1]; // AT91_REG PIOB_ASR; // Select A Register AT91_REG PIOB_BSR; // Select B Register AT91_REG PIOB_ABSR; // AB Select Status Register AT91_REG Reserved18[9]; // AT91_REG PIOB_OWER; // Output Write Enable Register AT91_REG PIOB_OWDR; // Output Write Disable Register AT91_REG PIOB_OWSR; // Output Write Status Register AT91_REG Reserved19[341]; // AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved20[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved21[1]; // AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG Reserved22[1]; // AT91_REG PMC_PLLR; // PLL Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved23[3]; // AT91_REG PMC_PCKR[4]; // Programmable Clock Register AT91_REG Reserved24[4]; // AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register AT91_REG Reserved25[36]; // AT91_REG RSTC_RCR; // Reset Control Register AT91_REG RSTC_RSR; // Reset Status Register AT91_REG RSTC_RMR; // Reset Mode Register AT91_REG Reserved26[5]; // AT91_REG RTTC_RTMR; // Real-time Mode Register AT91_REG RTTC_RTAR; // Real-time Alarm Register AT91_REG RTTC_RTVR; // Real-time Value Register AT91_REG RTTC_RTSR; // Real-time Status Register AT91_REG PITC_PIMR; // Period Interval Mode Register AT91_REG PITC_PISR; // Period Interval Status Register AT91_REG PITC_PIVR; // Period Interval Value Register AT91_REG PITC_PIIR; // Period Interval Image Register AT91_REG WDTC_WDCR; // Watchdog Control Register AT91_REG WDTC_WDMR; // Watchdog Mode Register AT91_REG WDTC_WDSR; // Watchdog Status Register AT91_REG Reserved27[5]; // AT91_REG VREG_MR; // Voltage Regulator Mode Register } AT91S_SYS, AT91PS_SYS; // ************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller // *************************************************************************** typedef struct _AT91S_AIC { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register } AT91S_AIC, AT91PS_AIC; // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask // ************************************************************************** // SOFTWARE API DEFINITION FOR Peripheral DMA Controller // *************************************************************************** typedef struct _AT91S_PDC { AT91_REG PDC_RPR; // Receive Pointer Register AT91_REG PDC_RCR; // Receive Counter Register AT91_REG PDC_TPR; // Transmit Pointer Register AT91_REG PDC_TCR; // Transmit Counter Register AT91_REG PDC_RNPR; // Receive Next Pointer Register AT91_REG PDC_RNCR; // Receive Next Counter Register AT91_REG PDC_TNPR; // Transmit Next Pointer Register AT91_REG PDC_TNCR; // Transmit Next Counter Register AT91_REG PDC_PTCR; // PDC Transfer Control Register AT91_REG PDC_PTSR; // PDC Transfer Status Register } AT91S_PDC, AT91PS_PDC; // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Debug Unit // *************************************************************************** typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved0[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved1[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register } AT91S_DBGU, AT91PS_DBGU; // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG // ************************************************************************** // SOFTWARE API DEFINITION FOR Parallel Input Output Controler // *************************************************************************** typedef struct _AT91S_PIO { AT91_REG PIO_PER; // PIO Enable Register AT91_REG PIO_PDR; // PIO Disable Register AT91_REG PIO_PSR; // PIO Status Register AT91_REG Reserved0[1]; // AT91_REG PIO_OER; // Output Enable Register AT91_REG PIO_ODR; // Output Disable Registerr AT91_REG PIO_OSR; // Output Status Register AT91_REG Reserved1[1]; // AT91_REG PIO_IFER; // Input Filter Enable Register AT91_REG PIO_IFDR; // Input Filter Disable Register AT91_REG PIO_IFSR; // Input Filter Status Register AT91_REG Reserved2[1]; // AT91_REG PIO_SODR; // Set Output Data Register AT91_REG PIO_CODR; // Clear Output Data Register AT91_REG PIO_ODSR; // Output Data Status Register AT91_REG PIO_PDSR; // Pin Data Status Register AT91_REG PIO_IER; // Interrupt Enable Register AT91_REG PIO_IDR; // Interrupt Disable Register AT91_REG PIO_IMR; // Interrupt Mask Register AT91_REG PIO_ISR; // Interrupt Status Register AT91_REG PIO_MDER; // Multi-driver Enable Register AT91_REG PIO_MDDR; // Multi-driver Disable Register AT91_REG PIO_MDSR; // Multi-driver Status Register AT91_REG Reserved3[1]; // AT91_REG PIO_PPUDR; // Pull-up Disable Register AT91_REG PIO_PPUER; // Pull-up Enable Register AT91_REG PIO_PPUSR; // Pull-up Status Register AT91_REG Reserved4[1]; // AT91_REG PIO_ASR; // Select A Register AT91_REG PIO_BSR; // Select B Register AT91_REG PIO_ABSR; // AB Select Status Register AT91_REG Reserved5[9]; // AT91_REG PIO_OWER; // Output Write Enable Register AT91_REG PIO_OWDR; // Output Write Disable Register AT91_REG PIO_OWSR; // Output Write Status Register } AT91S_PIO, AT91PS_PIO; // ************************************************************************** // SOFTWARE API DEFINITION FOR Clock Generator Controler // *************************************************************************** typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; // Main Oscillator Register AT91_REG CKGR_MCFR; // Main Clock Frequency Register AT91_REG Reserved0[1]; // AT91_REG CKGR_PLLR; // PLL Register } AT91S_CKGR, AT91PS_CKGR; // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 #define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed #define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter #define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range #define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 // ************************************************************************** // SOFTWARE API DEFINITION FOR Power Management Controler // *************************************************************************** typedef struct _AT91S_PMC { AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved0[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved1[1]; // AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG Reserved2[1]; // AT91_REG PMC_PLLR; // PLL Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved3[3]; // AT91_REG PMC_PCKR[4]; // Programmable Clock Register AT91_REG Reserved4[4]; // AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register } AT91S_PMC, AT91PS_PMC; // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected #define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask #define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Reset Controller Interface // *************************************************************************** typedef struct _AT91S_RSTC { AT91_REG RSTC_RCR; // Reset Control Register AT91_REG RSTC_RSR; // Reset Status Register AT91_REG RSTC_RMR; // Reset Mode Register } AT91S_RSTC, AT91PS_RSTC; // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status #define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type #define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. #define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable #define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable // ************************************************************************** // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface // *************************************************************************** typedef struct _AT91S_RTTC { AT91_REG RTTC_RTMR; // Real-time Mode Register AT91_REG RTTC_RTAR; // Real-time Alarm Register AT91_REG RTTC_RTVR; // Real-time Value Register AT91_REG RTTC_RTSR; // Real-time Status Register } AT91S_RTTC, AT91PS_RTTC; // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment // ************************************************************************** // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface // *************************************************************************** typedef struct _AT91S_PITC { AT91_REG PITC_PIMR; // Period Interval Mode Register AT91_REG PITC_PISR; // Period Interval Status Register AT91_REG PITC_PIVR; // Period Interval Value Register AT91_REG PITC_PIIR; // Period Interval Image Register } AT91S_PITC, AT91PS_PITC; // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface // *************************************************************************** typedef struct _AT91S_WDTC { AT91_REG WDTC_WDCR; // Watchdog Control Register AT91_REG WDTC_WDMR; // Watchdog Mode Register AT91_REG WDTC_WDSR; // Watchdog Status Register } AT91S_WDTC, AT91PS_WDTC; // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error // ************************************************************************** // SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface // *************************************************************************** typedef struct _AT91S_VREG { AT91_REG VREG_MR; // Voltage Regulator Mode Register } AT91S_VREG, AT91PS_VREG; // -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- #define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode // ************************************************************************** // SOFTWARE API DEFINITION FOR Memory Controller Interface // *************************************************************************** typedef struct _AT91S_MC { AT91_REG MC_RCR; // MC Remap Control Register AT91_REG MC_ASR; // MC Abort Status Register AT91_REG MC_AASR; // MC Abort Address Status Register AT91_REG Reserved0[21]; // AT91_REG MC_FMR; // MC Flash Mode Register AT91_REG MC_FCR; // MC Flash Command Register AT91_REG MC_FSR; // MC Flash Status Register } AT91S_MC, AT91PS_MC; // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status #define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status #define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte #define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word #define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word #define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status #define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read #define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write #define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch #define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- #define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready #define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error #define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error #define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming #define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State #define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations #define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations #define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations #define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations #define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- #define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command #define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. #define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. #define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. #define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. #define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. #define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. #define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. #define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. #define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number #define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- #define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status #define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status #define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status #define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status #define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status #define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status #define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status #define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status #define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status #define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status #define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status #define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status #define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status #define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status #define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status #define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status #define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status #define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status #define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status #define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status #define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status #define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status #define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status #define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status #define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status // ************************************************************************** // SOFTWARE API DEFINITION FOR Serial Parallel Interface // *************************************************************************** typedef struct _AT91S_SPI { AT91_REG SPI_CR; // Control Register AT91_REG SPI_MR; // Mode Register AT91_REG SPI_RDR; // Receive Data Register AT91_REG SPI_TDR; // Transmit Data Register AT91_REG SPI_SR; // Status Register AT91_REG SPI_IER; // Interrupt Enable Register AT91_REG SPI_IDR; // Interrupt Disable Register AT91_REG SPI_IMR; // Interrupt Mask Register AT91_REG Reserved0[4]; // AT91_REG SPI_CSR[4]; // Chip Select Register AT91_REG Reserved1[48]; // AT91_REG SPI_RPR; // Receive Pointer Register AT91_REG SPI_RCR; // Receive Counter Register AT91_REG SPI_TPR; // Transmit Pointer Register AT91_REG SPI_TCR; // Transmit Counter Register AT91_REG SPI_RNPR; // Receive Next Pointer Register AT91_REG SPI_RNCR; // Receive Next Counter Register AT91_REG SPI_TNPR; // Transmit Next Pointer Register AT91_REG SPI_TNCR; // Transmit Next Counter Register AT91_REG SPI_PTCR; // PDC Transfer Control Register AT91_REG SPI_PTSR; // PDC Transfer Status Register } AT91S_SPI, AT91PS_SPI; // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status // -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers // ************************************************************************** // SOFTWARE API DEFINITION FOR Usart // *************************************************************************** typedef struct _AT91S_USART { AT91_REG US_CR; // Control Register AT91_REG US_MR; // Mode Register AT91_REG US_IER; // Interrupt Enable Register AT91_REG US_IDR; // Interrupt Disable Register AT91_REG US_IMR; // Interrupt Mask Register AT91_REG US_CSR; // Channel Status Register AT91_REG US_RHR; // Receiver Holding Register AT91_REG US_THR; // Transmitter Holding Register AT91_REG US_BRGR; // Baud Rate Generator Register AT91_REG US_RTOR; // Receiver Time-out Register AT91_REG US_TTGR; // Transmitter Time-guard Register AT91_REG Reserved0[5]; // AT91_REG US_FIDI; // FI_DI_Ratio Register AT91_REG US_NER; // Nb Errors Register AT91_REG Reserved1[1]; // AT91_REG US_IF; // IRDA_FILTER Register AT91_REG Reserved2[44]; // AT91_REG US_RPR; // Receive Pointer Register AT91_REG US_RCR; // Receive Counter Register AT91_REG US_TPR; // Transmit Pointer Register AT91_REG US_TCR; // Transmit Counter Register AT91_REG US_RNPR; // Receive Next Pointer Register AT91_REG US_RNCR; // Receive Next Counter Register AT91_REG US_TNPR; // Transmit Next Pointer Register AT91_REG US_TNCR; // Transmit Next Counter Register AT91_REG US_PTCR; // PDC Transfer Control Register AT91_REG US_PTSR; // PDC Transfer Status Register } AT91S_USART, AT91PS_USART; // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input // ************************************************************************** // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface // *************************************************************************** typedef struct _AT91S_SSC { AT91_REG SSC_CR; // Control Register AT91_REG SSC_CMR; // Clock Mode Register AT91_REG Reserved0[2]; // AT91_REG SSC_RCMR; // Receive Clock ModeRegister AT91_REG SSC_RFMR; // Receive Frame Mode Register AT91_REG SSC_TCMR; // Transmit Clock Mode Register AT91_REG SSC_TFMR; // Transmit Frame Mode Register AT91_REG SSC_RHR; // Receive Holding Register AT91_REG SSC_THR; // Transmit Holding Register AT91_REG Reserved1[2]; // AT91_REG SSC_RSHR; // Receive Sync Holding Register AT91_REG SSC_TSHR; // Transmit Sync Holding Register AT91_REG Reserved2[2]; // AT91_REG SSC_SR; // Status Register AT91_REG SSC_IER; // Interrupt Enable Register AT91_REG SSC_IDR; // Interrupt Disable Register AT91_REG SSC_IMR; // Interrupt Mask Register AT91_REG Reserved3[44]; // AT91_REG SSC_RPR; // Receive Pointer Register AT91_REG SSC_RCR; // Receive Counter Register AT91_REG SSC_TPR; // Transmit Pointer Register AT91_REG SSC_TCR; // Transmit Counter Register AT91_REG SSC_RNPR; // Receive Next Pointer Register AT91_REG SSC_RNCR; // Receive Next Counter Register AT91_REG SSC_TNPR; // Transmit Next Pointer Register AT91_REG SSC_TNCR; // Transmit Next Counter Register AT91_REG SSC_PTCR; // PDC Transfer Control Register AT91_REG SSC_PTSR; // PDC Transfer Status Register } AT91S_SSC, AT91PS_SSC; // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Two-wire Interface // *************************************************************************** typedef struct _AT91S_TWI { AT91_REG TWI_CR; // Control Register AT91_REG TWI_MMR; // Master Mode Register AT91_REG Reserved0[1]; // AT91_REG TWI_IADR; // Internal Address Register AT91_REG TWI_CWGR; // Clock Waveform Generator Register AT91_REG Reserved1[3]; // AT91_REG TWI_SR; // Status Register AT91_REG TWI_IER; // Interrupt Enable Register AT91_REG TWI_IDR; // Interrupt Disable Register AT91_REG TWI_IMR; // Interrupt Mask Register AT91_REG TWI_RHR; // Receive Holding Register AT91_REG TWI_THR; // Transmit Holding Register } AT91S_TWI, AT91PS_TWI; // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR PWMC Channel Interface // *************************************************************************** typedef struct _AT91S_PWMC_CH { AT91_REG PWMC_CMR; // Channel Mode Register AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register AT91_REG PWMC_CPRDR; // Channel Period Register AT91_REG PWMC_CCNTR; // Channel Counter Register AT91_REG PWMC_CUPDR; // Channel Update Register AT91_REG PWMC_Reserved[3]; // Reserved } AT91S_PWMC_CH, AT91PS_PWMC_CH; // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- #define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx #define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) #define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) #define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) #define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment #define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity #define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- #define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- #define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- #define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- #define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update // ************************************************************************** // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface // *************************************************************************** typedef struct _AT91S_PWMC { AT91_REG PWMC_MR; // PWMC Mode Register AT91_REG PWMC_ENA; // PWMC Enable Register AT91_REG PWMC_DIS; // PWMC Disable Register AT91_REG PWMC_SR; // PWMC Status Register AT91_REG PWMC_IER; // PWMC Interrupt Enable Register AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register AT91_REG PWMC_ISR; // PWMC Interrupt Status Register AT91_REG Reserved0[55]; // AT91_REG PWMC_VR; // PWMC Version Register AT91_REG Reserved1[64]; // AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel } AT91S_PWMC, AT91PS_PWMC; // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- #define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. #define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A #define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) #define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. #define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B #define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- #define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 #define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 #define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 #define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR USB Device Interface // *************************************************************************** typedef struct _AT91S_UDP { AT91_REG UDP_NUM; // Frame Number Register AT91_REG UDP_GLBSTATE; // Global State Register AT91_REG UDP_FADDR; // Function Address Register AT91_REG Reserved0[1]; // AT91_REG UDP_IER; // Interrupt Enable Register AT91_REG UDP_IDR; // Interrupt Disable Register AT91_REG UDP_IMR; // Interrupt Mask Register AT91_REG UDP_ISR; // Interrupt Status Register AT91_REG UDP_ICR; // Interrupt Clear Register AT91_REG Reserved1[1]; // AT91_REG UDP_RSTEP; // Reset Endpoint Register AT91_REG Reserved2[1]; // AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register AT91_REG Reserved3[2]; // AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register AT91_REG Reserved4[3]; // AT91_REG UDP_TXVC; // Transceiver Control Register } AT91S_UDP, AT91PS_UDP; // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt #define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt #define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 #define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) #define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON // ************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface // *************************************************************************** typedef struct _AT91S_TC { AT91_REG TC_CCR; // Channel Control Register AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) AT91_REG Reserved0[2]; // AT91_REG TC_CV; // Counter Value AT91_REG TC_RA; // Register A AT91_REG TC_RB; // Register B AT91_REG TC_RC; // Register C AT91_REG TC_SR; // Status Register AT91_REG TC_IER; // Interrupt Enable Register AT91_REG TC_IDR; // Interrupt Disable Register AT91_REG TC_IMR; // Interrupt Mask Register } AT91S_TC, AT91PS_TC; // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Interface // *************************************************************************** typedef struct _AT91S_TCB { AT91S_TC TCB_TC0; // TC Channel 0 AT91_REG Reserved0[4]; // AT91S_TC TCB_TC1; // TC Channel 1 AT91_REG Reserved1[4]; // AT91S_TC TCB_TC2; // TC Channel 2 AT91_REG Reserved2[4]; // AT91_REG TCB_BCR; // TC Block Control Register AT91_REG TCB_BMR; // TC Block Mode Register } AT91S_TCB, AT91PS_TCB; // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 // ************************************************************************** // SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface // *************************************************************************** typedef struct _AT91S_CAN_MB { AT91_REG CAN_MB_MMR; // MailBox Mode Register AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register AT91_REG CAN_MB_MID; // MailBox ID Register AT91_REG CAN_MB_MFID; // MailBox Family ID Register AT91_REG CAN_MB_MSR; // MailBox Status Register AT91_REG CAN_MB_MDL; // MailBox Data Low Register AT91_REG CAN_MB_MDH; // MailBox Data High Register AT91_REG CAN_MB_MCR; // MailBox Control Register } AT91S_CAN_MB, AT91PS_CAN_MB; // -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- #define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark #define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority #define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type #define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) #define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) #define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) #define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) #define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) #define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) // -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- #define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode #define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode #define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version // -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- // -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- // -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- #define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value #define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code #define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request #define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort #define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready #define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored // -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- // -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- // -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- #define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox #define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command // ************************************************************************** // SOFTWARE API DEFINITION FOR Control Area Network Interface // *************************************************************************** typedef struct _AT91S_CAN { AT91_REG CAN_MR; // Mode Register AT91_REG CAN_IER; // Interrupt Enable Register AT91_REG CAN_IDR; // Interrupt Disable Register AT91_REG CAN_IMR; // Interrupt Mask Register AT91_REG CAN_SR; // Status Register AT91_REG CAN_BR; // Baudrate Register AT91_REG CAN_TIM; // Timer Register AT91_REG CAN_TIMESTP; // Time Stamp Register AT91_REG CAN_ECR; // Error Counter Register AT91_REG CAN_TCR; // Transfer Command Register AT91_REG CAN_ACR; // Abort Command Register AT91_REG Reserved0[52]; // AT91_REG CAN_VR; // Version Register AT91_REG Reserved1[64]; // AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 } AT91S_CAN, AT91PS_CAN; // -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- #define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable #define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode #define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode #define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame #define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame #define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode #define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze #define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat // -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- #define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag #define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag #define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag #define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag #define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag #define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag #define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag #define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag #define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag #define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag #define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag #define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag #define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag #define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag #define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag #define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag #define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag #define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag #define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag #define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag #define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag #define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag #define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag #define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag #define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error #define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error #define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error #define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error #define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error // -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- // -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- // -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- #define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy #define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy #define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy // -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- #define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment #define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment #define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment #define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment #define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler #define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode // -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- #define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field // -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- // -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- #define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter #define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter // -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- #define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field // -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 // *************************************************************************** typedef struct _AT91S_EMAC { AT91_REG EMAC_NCR; // Network Control Register AT91_REG EMAC_NCFGR; // Network Configuration Register AT91_REG EMAC_NSR; // Network Status Register AT91_REG Reserved0[2]; // AT91_REG EMAC_TSR; // Transmit Status Register AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer AT91_REG EMAC_RSR; // Receive Status Register AT91_REG EMAC_ISR; // Interrupt Status Register AT91_REG EMAC_IER; // Interrupt Enable Register AT91_REG EMAC_IDR; // Interrupt Disable Register AT91_REG EMAC_IMR; // Interrupt Mask Register AT91_REG EMAC_MAN; // PHY Maintenance Register AT91_REG EMAC_PTR; // Pause Time Register AT91_REG EMAC_PFR; // Pause Frames received Register AT91_REG EMAC_FTO; // Frames Transmitted OK Register AT91_REG EMAC_SCF; // Single Collision Frame Register AT91_REG EMAC_MCF; // Multiple Collision Frame Register AT91_REG EMAC_FRO; // Frames Received OK Register AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register AT91_REG EMAC_ALE; // Alignment Error Register AT91_REG EMAC_DTF; // Deferred Transmission Frame Register AT91_REG EMAC_LCOL; // Late Collision Register AT91_REG EMAC_ECOL; // Excessive Collision Register AT91_REG EMAC_TUND; // Transmit Underrun Error Register AT91_REG EMAC_CSE; // Carrier Sense Error Register AT91_REG EMAC_RRE; // Receive Ressource Error Register AT91_REG EMAC_ROV; // Receive Overrun Errors Register AT91_REG EMAC_RSE; // Receive Symbol Errors Register AT91_REG EMAC_ELE; // Excessive Length Errors Register AT91_REG EMAC_RJA; // Receive Jabbers Register AT91_REG EMAC_USF; // Undersize Frames Register AT91_REG EMAC_STE; // SQE Test Error Register AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register AT91_REG EMAC_TPF; // Transmitted Pause Frames Register AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] AT91_REG EMAC_HRT; // Hash Address Top[63:32] AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes AT91_REG EMAC_TID; // Type ID Checking Register AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register AT91_REG EMAC_USRIO; // USER Input/Output Register AT91_REG EMAC_WOL; // Wake On LAN Register AT91_REG Reserved1[13]; // AT91_REG EMAC_REV; // Revision Register } AT91S_EMAC, AT91PS_EMAC; // -------- EMAC_NCR : (EMAC Offset: 0x0) -------- #define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. #define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. #define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. #define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. #define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. #define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. #define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. #define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. #define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. #define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. #define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. #define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame #define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- #define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. #define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. #define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. #define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. #define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable #define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. #define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. #define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. #define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) #define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 #define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 #define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 #define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 #define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) #define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) #define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) #define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer #define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer #define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer #define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer #define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable #define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS #define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) #define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- #define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- #define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) #define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go #define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame #define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) #define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- #define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- #define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) #define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) #define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) #define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) #define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) #define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) #define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) #define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) #define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) #define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) #define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) #define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) #define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) #define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- #define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- #define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address #define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable #define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable #define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- #define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) #define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) // ************************************************************************** // SOFTWARE API DEFINITION FOR Analog to Digital Convertor // *************************************************************************** typedef struct _AT91S_ADC { AT91_REG ADC_CR; // ADC Control Register AT91_REG ADC_MR; // ADC Mode Register AT91_REG Reserved0[2]; // AT91_REG ADC_CHER; // ADC Channel Enable Register AT91_REG ADC_CHDR; // ADC Channel Disable Register AT91_REG ADC_CHSR; // ADC Channel Status Register AT91_REG ADC_SR; // ADC Status Register AT91_REG ADC_LCDR; // ADC Last Converted Data Register AT91_REG ADC_IER; // ADC Interrupt Enable Register AT91_REG ADC_IDR; // ADC Interrupt Disable Register AT91_REG ADC_IMR; // ADC Interrupt Mask Register AT91_REG ADC_CDR0; // ADC Channel Data Register 0 AT91_REG ADC_CDR1; // ADC Channel Data Register 1 AT91_REG ADC_CDR2; // ADC Channel Data Register 2 AT91_REG ADC_CDR3; // ADC Channel Data Register 3 AT91_REG ADC_CDR4; // ADC Channel Data Register 4 AT91_REG ADC_CDR5; // ADC Channel Data Register 5 AT91_REG ADC_CDR6; // ADC Channel Data Register 6 AT91_REG ADC_CDR7; // ADC Channel Data Register 7 AT91_REG Reserved1[44]; // AT91_REG ADC_RPR; // Receive Pointer Register AT91_REG ADC_RCR; // Receive Counter Register AT91_REG ADC_TPR; // Transmit Pointer Register AT91_REG ADC_TCR; // Transmit Counter Register AT91_REG ADC_RNPR; // Receive Next Pointer Register AT91_REG ADC_RNCR; // Receive Next Counter Register AT91_REG ADC_TNPR; // Transmit Next Pointer Register AT91_REG ADC_TNCR; // Transmit Next Counter Register AT91_REG ADC_PTCR; // PDC Transfer Control Register AT91_REG ADC_PTSR; // PDC Transfer Status Register } AT91S_ADC, AT91PS_ADC; // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- #define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset #define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- #define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable #define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software #define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. #define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection #define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 #define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 #define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 #define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 #define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 #define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 #define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger #define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. #define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution #define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution #define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode #define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode #define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode #define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection #define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time #define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- #define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 #define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 #define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 #define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 #define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 #define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 #define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 #define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- #define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion #define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion #define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion #define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion #define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion #define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion #define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion #define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion #define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error #define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error #define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error #define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error #define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error #define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error #define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error #define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error #define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready #define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun #define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer #define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- #define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- #define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Encryption Standard // *************************************************************************** typedef struct _AT91S_AES { AT91_REG AES_CR; // Control Register AT91_REG AES_MR; // Mode Register AT91_REG Reserved0[2]; // AT91_REG AES_IER; // Interrupt Enable Register AT91_REG AES_IDR; // Interrupt Disable Register AT91_REG AES_IMR; // Interrupt Mask Register AT91_REG AES_ISR; // Interrupt Status Register AT91_REG AES_KEYWxR[4]; // Key Word x Register AT91_REG Reserved1[4]; // AT91_REG AES_IDATAxR[4]; // Input Data x Register AT91_REG AES_ODATAxR[4]; // Output Data x Register AT91_REG AES_IVxR[4]; // Initialization Vector x Register AT91_REG Reserved2[35]; // AT91_REG AES_VR; // AES Version Register AT91_REG AES_RPR; // Receive Pointer Register AT91_REG AES_RCR; // Receive Counter Register AT91_REG AES_TPR; // Transmit Pointer Register AT91_REG AES_TCR; // Transmit Counter Register AT91_REG AES_RNPR; // Receive Next Pointer Register AT91_REG AES_RNCR; // Receive Next Counter Register AT91_REG AES_TNPR; // Transmit Next Pointer Register AT91_REG AES_TNCR; // Transmit Next Counter Register AT91_REG AES_PTCR; // PDC Transfer Control Register AT91_REG AES_PTSR; // PDC Transfer Status Register } AT91S_AES, AT91PS_AES; // -------- AES_CR : (AES Offset: 0x0) Control Register -------- #define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing #define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset #define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading // -------- AES_MR : (AES Offset: 0x4) Mode Register -------- #define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode #define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay #define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode #define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. #define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). #define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). #define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode #define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. #define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. #define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. #define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. #define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. #define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode #define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size #define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. #define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. #define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. #define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. #define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. #define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key #define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type #define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. #define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. #define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. #define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. #define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. // -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- #define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY #define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End #define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End #define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full #define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty #define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection // -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- // -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- // -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- #define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status #define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. #define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. #define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. #define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. #define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. #define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. // ************************************************************************** // SOFTWARE API DEFINITION FOR Triple Data Encryption Standard // *************************************************************************** typedef struct _AT91S_TDES { AT91_REG TDES_CR; // Control Register AT91_REG TDES_MR; // Mode Register AT91_REG Reserved0[2]; // AT91_REG TDES_IER; // Interrupt Enable Register AT91_REG TDES_IDR; // Interrupt Disable Register AT91_REG TDES_IMR; // Interrupt Mask Register AT91_REG TDES_ISR; // Interrupt Status Register AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register AT91_REG Reserved1[2]; // AT91_REG TDES_IDATAxR[2]; // Input Data x Register AT91_REG Reserved2[2]; // AT91_REG TDES_ODATAxR[2]; // Output Data x Register AT91_REG Reserved3[2]; // AT91_REG TDES_IVxR[2]; // Initialization Vector x Register AT91_REG Reserved4[37]; // AT91_REG TDES_VR; // TDES Version Register AT91_REG TDES_RPR; // Receive Pointer Register AT91_REG TDES_RCR; // Receive Counter Register AT91_REG TDES_TPR; // Transmit Pointer Register AT91_REG TDES_TCR; // Transmit Counter Register AT91_REG TDES_RNPR; // Receive Next Pointer Register AT91_REG TDES_RNCR; // Receive Next Counter Register AT91_REG TDES_TNPR; // Transmit Next Pointer Register AT91_REG TDES_TNCR; // Transmit Next Counter Register AT91_REG TDES_PTCR; // PDC Transfer Control Register AT91_REG TDES_PTSR; // PDC Transfer Status Register } AT91S_TDES, AT91PS_TDES; // -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- #define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing #define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset // -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- #define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode #define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode #define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode #define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode #define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. #define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). #define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). #define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode #define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. #define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. #define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. #define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. #define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode #define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size #define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. #define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. #define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. #define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. // -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- #define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY #define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End #define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End #define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full #define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty #define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection // -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- // -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- // -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- #define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status #define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. #define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. #define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. #define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. // ************************************************************************** // REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 // *************************************************************************** // ========== Register definition for SYS peripheral ========== // ========== Register definition for AIC peripheral ========== #define AT91C_AIC_IVR ((AT91_REG ) 0xFFFFF100) // (AIC) IRQ Vector Register #define AT91C_AIC_SMR ((AT91_REG ) 0xFFFFF000) // (AIC) Source Mode Register #define AT91C_AIC_FVR ((AT91_REG ) 0xFFFFF104) // (AIC) FIQ Vector Register #define AT91C_AIC_DCR ((AT91_REG ) 0xFFFFF138) // (AIC) Debug Control Register (Protect) #define AT91C_AIC_EOICR ((AT91_REG ) 0xFFFFF130) // (AIC) End of Interrupt Command Register #define AT91C_AIC_SVR ((AT91_REG ) 0xFFFFF080) // (AIC) Source Vector Register #define AT91C_AIC_FFSR ((AT91_REG ) 0xFFFFF148) // (AIC) Fast Forcing Status Register #define AT91C_AIC_ICCR ((AT91_REG ) 0xFFFFF128) // (AIC) Interrupt Clear Command Register #define AT91C_AIC_ISR ((AT91_REG ) 0xFFFFF108) // (AIC) Interrupt Status Register #define AT91C_AIC_IMR ((AT91_REG ) 0xFFFFF110) // (AIC) Interrupt Mask Register #define AT91C_AIC_IPR ((AT91_REG ) 0xFFFFF10C) // (AIC) Interrupt Pending Register #define AT91C_AIC_FFER ((AT91_REG ) 0xFFFFF140) // (AIC) Fast Forcing Enable Register #define AT91C_AIC_IECR ((AT91_REG ) 0xFFFFF120) // (AIC) Interrupt Enable Command Register #define AT91C_AIC_ISCR ((AT91_REG ) 0xFFFFF12C) // (AIC) Interrupt Set Command Register #define AT91C_AIC_FFDR ((AT91_REG ) 0xFFFFF144) // (AIC) Fast Forcing Disable Register #define AT91C_AIC_CISR ((AT91_REG ) 0xFFFFF114) // (AIC) Core Interrupt Status Register #define AT91C_AIC_IDCR ((AT91_REG ) 0xFFFFF124) // (AIC) Interrupt Disable Command Register #define AT91C_AIC_SPU ((AT91_REG ) 0xFFFFF134) // (AIC) Spurious Vector Register // ========== Register definition for PDC_DBGU peripheral ========== #define AT91C_DBGU_TCR ((AT91_REG ) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register #define AT91C_DBGU_RNPR ((AT91_REG ) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register #define AT91C_DBGU_TNPR ((AT91_REG ) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register #define AT91C_DBGU_TPR ((AT91_REG ) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register #define AT91C_DBGU_RPR ((AT91_REG ) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register #define AT91C_DBGU_RCR ((AT91_REG ) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register #define AT91C_DBGU_RNCR ((AT91_REG ) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register #define AT91C_DBGU_PTCR ((AT91_REG ) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register #define AT91C_DBGU_PTSR ((AT91_REG ) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register #define AT91C_DBGU_TNCR ((AT91_REG ) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register // ========== Register definition for DBGU peripheral ========== #define AT91C_DBGU_EXID ((AT91_REG ) 0xFFFFF244) // (DBGU) Chip ID Extension Register #define AT91C_DBGU_BRGR ((AT91_REG ) 0xFFFFF220) // (DBGU) Baud Rate Generator Register #define AT91C_DBGU_IDR ((AT91_REG ) 0xFFFFF20C) // (DBGU) Interrupt Disable Register #define AT91C_DBGU_CSR ((AT91_REG ) 0xFFFFF214) // (DBGU) Channel Status Register #define AT91C_DBGU_CIDR ((AT91_REG ) 0xFFFFF240) // (DBGU) Chip ID Register #define AT91C_DBGU_MR ((AT91_REG ) 0xFFFFF204) // (DBGU) Mode Register #define AT91C_DBGU_IMR ((AT91_REG ) 0xFFFFF210) // (DBGU) Interrupt Mask Register #define AT91C_DBGU_CR ((AT91_REG ) 0xFFFFF200) // (DBGU) Control Register #define AT91C_DBGU_FNTR ((AT91_REG ) 0xFFFFF248) // (DBGU) Force NTRST Register #define AT91C_DBGU_THR ((AT91_REG ) 0xFFFFF21C) // (DBGU) Transmitter Holding Register #define AT91C_DBGU_RHR ((AT91_REG ) 0xFFFFF218) // (DBGU) Receiver Holding Register #define AT91C_DBGU_IER ((AT91_REG ) 0xFFFFF208) // (DBGU) Interrupt Enable Register // ========== Register definition for PIOA peripheral ========== #define AT91C_PIOA_ODR ((AT91_REG ) 0xFFFFF414) // (PIOA) Output Disable Registerr #define AT91C_PIOA_SODR ((AT91_REG ) 0xFFFFF430) // (PIOA) Set Output Data Register #define AT91C_PIOA_ISR ((AT91_REG ) 0xFFFFF44C) // (PIOA) Interrupt Status Register #define AT91C_PIOA_ABSR ((AT91_REG ) 0xFFFFF478) // (PIOA) AB Select Status Register #define AT91C_PIOA_IER ((AT91_REG ) 0xFFFFF440) // (PIOA) Interrupt Enable Register #define AT91C_PIOA_PPUDR ((AT91_REG ) 0xFFFFF460) // (PIOA) Pull-up Disable Register #define AT91C_PIOA_IMR ((AT91_REG ) 0xFFFFF448) // (PIOA) Interrupt Mask Register #define AT91C_PIOA_PER ((AT91_REG ) 0xFFFFF400) // (PIOA) PIO Enable Register #define AT91C_PIOA_IFDR ((AT91_REG ) 0xFFFFF424) // (PIOA) Input Filter Disable Register #define AT91C_PIOA_OWDR ((AT91_REG ) 0xFFFFF4A4) // (PIOA) Output Write Disable Register #define AT91C_PIOA_MDSR ((AT91_REG ) 0xFFFFF458) // (PIOA) Multi-driver Status Register #define AT91C_PIOA_IDR ((AT91_REG ) 0xFFFFF444) // (PIOA) Interrupt Disable Register #define AT91C_PIOA_ODSR ((AT91_REG ) 0xFFFFF438) // (PIOA) Output Data Status Register #define AT91C_PIOA_PPUSR ((AT91_REG ) 0xFFFFF468) // (PIOA) Pull-up Status Register #define AT91C_PIOA_OWSR ((AT91_REG ) 0xFFFFF4A8) // (PIOA) Output Write Status Register #define AT91C_PIOA_BSR ((AT91_REG ) 0xFFFFF474) // (PIOA) Select B Register #define AT91C_PIOA_OWER ((AT91_REG ) 0xFFFFF4A0) // (PIOA) Output Write Enable Register #define AT91C_PIOA_IFER ((AT91_REG ) 0xFFFFF420) // (PIOA) Input Filter Enable Register #define AT91C_PIOA_PDSR ((AT91_REG ) 0xFFFFF43C) // (PIOA) Pin Data Status Register #define AT91C_PIOA_PPUER ((AT91_REG ) 0xFFFFF464) // (PIOA) Pull-up Enable Register #define AT91C_PIOA_OSR ((AT91_REG ) 0xFFFFF418) // (PIOA) Output Status Register #define AT91C_PIOA_ASR ((AT91_REG ) 0xFFFFF470) // (PIOA) Select A Register #define AT91C_PIOA_MDDR ((AT91_REG ) 0xFFFFF454) // (PIOA) Multi-driver Disable Register #define AT91C_PIOA_CODR ((AT91_REG ) 0xFFFFF434) // (PIOA) Clear Output Data Register #define AT91C_PIOA_MDER ((AT91_REG ) 0xFFFFF450) // (PIOA) Multi-driver Enable Register #define AT91C_PIOA_PDR ((AT91_REG ) 0xFFFFF404) // (PIOA) PIO Disable Register #define AT91C_PIOA_IFSR ((AT91_REG ) 0xFFFFF428) // (PIOA) Input Filter Status Register #define AT91C_PIOA_OER ((AT91_REG ) 0xFFFFF410) // (PIOA) Output Enable Register #define AT91C_PIOA_PSR ((AT91_REG ) 0xFFFFF408) // (PIOA) PIO Status Register // ========== Register definition for PIOB peripheral ========== #define AT91C_PIOB_OWDR ((AT91_REG ) 0xFFFFF6A4) // (PIOB) Output Write Disable Register #define AT91C_PIOB_MDER ((AT91_REG ) 0xFFFFF650) // (PIOB) Multi-driver Enable Register #define AT91C_PIOB_PPUSR ((AT91_REG ) 0xFFFFF668) // (PIOB) Pull-up Status Register #define AT91C_PIOB_IMR ((AT91_REG ) 0xFFFFF648) // (PIOB) Interrupt Mask Register #define AT91C_PIOB_ASR ((AT91_REG ) 0xFFFFF670) // (PIOB) Select A Register #define AT91C_PIOB_PPUDR ((AT91_REG ) 0xFFFFF660) // (PIOB) Pull-up Disable Register #define AT91C_PIOB_PSR ((AT91_REG ) 0xFFFFF608) // (PIOB) PIO Status Register #define AT91C_PIOB_IER ((AT91_REG ) 0xFFFFF640) // (PIOB) Interrupt Enable Register #define AT91C_PIOB_CODR ((AT91_REG ) 0xFFFFF634) // (PIOB) Clear Output Data Register #define AT91C_PIOB_OWER ((AT91_REG ) 0xFFFFF6A0) // (PIOB) Output Write Enable Register #define AT91C_PIOB_ABSR ((AT91_REG ) 0xFFFFF678) // (PIOB) AB Select Status Register #define AT91C_PIOB_IFDR ((AT91_REG ) 0xFFFFF624) // (PIOB) Input Filter Disable Register #define AT91C_PIOB_PDSR ((AT91_REG ) 0xFFFFF63C) // (PIOB) Pin Data Status Register #define AT91C_PIOB_IDR ((AT91_REG ) 0xFFFFF644) // (PIOB) Interrupt Disable Register #define AT91C_PIOB_OWSR ((AT91_REG ) 0xFFFFF6A8) // (PIOB) Output Write Status Register #define AT91C_PIOB_PDR ((AT91_REG ) 0xFFFFF604) // (PIOB) PIO Disable Register #define AT91C_PIOB_ODR ((AT91_REG ) 0xFFFFF614) // (PIOB) Output Disable Registerr #define AT91C_PIOB_IFSR ((AT91_REG ) 0xFFFFF628) // (PIOB) Input Filter Status Register #define AT91C_PIOB_PPUER ((AT91_REG ) 0xFFFFF664) // (PIOB) Pull-up Enable Register #define AT91C_PIOB_SODR ((AT91_REG ) 0xFFFFF630) // (PIOB) Set Output Data Register #define AT91C_PIOB_ISR ((AT91_REG ) 0xFFFFF64C) // (PIOB) Interrupt Status Register #define AT91C_PIOB_ODSR ((AT91_REG ) 0xFFFFF638) // (PIOB) Output Data Status Register #define AT91C_PIOB_OSR ((AT91_REG ) 0xFFFFF618) // (PIOB) Output Status Register #define AT91C_PIOB_MDSR ((AT91_REG ) 0xFFFFF658) // (PIOB) Multi-driver Status Register #define AT91C_PIOB_IFER ((AT91_REG ) 0xFFFFF620) // (PIOB) Input Filter Enable Register #define AT91C_PIOB_BSR ((AT91_REG ) 0xFFFFF674) // (PIOB) Select B Register #define AT91C_PIOB_MDDR ((AT91_REG ) 0xFFFFF654) // (PIOB) Multi-driver Disable Register #define AT91C_PIOB_OER ((AT91_REG ) 0xFFFFF610) // (PIOB) Output Enable Register #define AT91C_PIOB_PER ((AT91_REG ) 0xFFFFF600) // (PIOB) PIO Enable Register // ========== Register definition for CKGR peripheral ========== #define AT91C_CKGR_MOR ((AT91_REG ) 0xFFFFFC20) // (CKGR) Main Oscillator Register #define AT91C_CKGR_PLLR ((AT91_REG ) 0xFFFFFC2C) // (CKGR) PLL Register #define AT91C_CKGR_MCFR ((AT91_REG ) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register // ========== Register definition for PMC peripheral ========== #define AT91C_PMC_IDR ((AT91_REG ) 0xFFFFFC64) // (PMC) Interrupt Disable Register #define AT91C_PMC_MOR ((AT91_REG ) 0xFFFFFC20) // (PMC) Main Oscillator Register #define AT91C_PMC_PLLR ((AT91_REG ) 0xFFFFFC2C) // (PMC) PLL Register #define AT91C_PMC_PCER ((AT91_REG ) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register #define AT91C_PMC_PCKR ((AT91_REG ) 0xFFFFFC40) // (PMC) Programmable Clock Register #define AT91C_PMC_MCKR ((AT91_REG ) 0xFFFFFC30) // (PMC) Master Clock Register #define AT91C_PMC_SCDR ((AT91_REG ) 0xFFFFFC04) // (PMC) System Clock Disable Register #define AT91C_PMC_PCDR ((AT91_REG ) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register #define AT91C_PMC_SCSR ((AT91_REG ) 0xFFFFFC08) // (PMC) System Clock Status Register #define AT91C_PMC_PCSR ((AT91_REG ) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register #define AT91C_PMC_MCFR ((AT91_REG ) 0xFFFFFC24) // (PMC) Main Clock Frequency Register #define AT91C_PMC_SCER ((AT91_REG ) 0xFFFFFC00) // (PMC) System Clock Enable Register #define AT91C_PMC_IMR ((AT91_REG ) 0xFFFFFC6C) // (PMC) Interrupt Mask Register #define AT91C_PMC_IER ((AT91_REG ) 0xFFFFFC60) // (PMC) Interrupt Enable Register #define AT91C_PMC_SR ((AT91_REG ) 0xFFFFFC68) // (PMC) Status Register // ========== Register definition for RSTC peripheral ========== #define AT91C_RSTC_RCR ((AT91_REG ) 0xFFFFFD00) // (RSTC) Reset Control Register #define AT91C_RSTC_RMR ((AT91_REG ) 0xFFFFFD08) // (RSTC) Reset Mode Register #define AT91C_RSTC_RSR ((AT91_REG ) 0xFFFFFD04) // (RSTC) Reset Status Register // ========== Register definition for RTTC peripheral ========== #define AT91C_RTTC_RTSR ((AT91_REG ) 0xFFFFFD2C) // (RTTC) Real-time Status Register #define AT91C_RTTC_RTMR ((AT91_REG ) 0xFFFFFD20) // (RTTC) Real-time Mode Register #define AT91C_RTTC_RTVR ((AT91_REG ) 0xFFFFFD28) // (RTTC) Real-time Value Register #define AT91C_RTTC_RTAR ((AT91_REG ) 0xFFFFFD24) // (RTTC) Real-time Alarm Register // ========== Register definition for PITC peripheral ========== #define AT91C_PITC_PIVR ((AT91_REG ) 0xFFFFFD38) // (PITC) Period Interval Value Register #define AT91C_PITC_PISR ((AT91_REG ) 0xFFFFFD34) // (PITC) Period Interval Status Register #define AT91C_PITC_PIIR ((AT91_REG ) 0xFFFFFD3C) // (PITC) Period Interval Image Register #define AT91C_PITC_PIMR ((AT91_REG ) 0xFFFFFD30) // (PITC) Period Interval Mode Register // ========== Register definition for WDTC peripheral ========== #define AT91C_WDTC_WDCR ((AT91_REG ) 0xFFFFFD40) // (WDTC) Watchdog Control Register #define AT91C_WDTC_WDSR ((AT91_REG ) 0xFFFFFD48) // (WDTC) Watchdog Status Register #define AT91C_WDTC_WDMR ((AT91_REG ) 0xFFFFFD44) // (WDTC) Watchdog Mode Register // ========== Register definition for VREG peripheral ========== #define AT91C_VREG_MR ((AT91_REG ) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register // ========== Register definition for MC peripheral ========== #define AT91C_MC_ASR ((AT91_REG ) 0xFFFFFF04) // (MC) MC Abort Status Register #define AT91C_MC_RCR ((AT91_REG ) 0xFFFFFF00) // (MC) MC Remap Control Register #define AT91C_MC_FCR ((AT91_REG ) 0xFFFFFF64) // (MC) MC Flash Command Register #define AT91C_MC_AASR ((AT91_REG ) 0xFFFFFF08) // (MC) MC Abort Address Status Register #define AT91C_MC_FSR ((AT91_REG ) 0xFFFFFF68) // (MC) MC Flash Status Register #define AT91C_MC_FMR ((AT91_REG ) 0xFFFFFF60) // (MC) MC Flash Mode Register // ========== Register definition for PDC_SPI1 peripheral ========== #define AT91C_SPI1_PTCR ((AT91_REG ) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register #define AT91C_SPI1_RPR ((AT91_REG ) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register #define AT91C_SPI1_TNCR ((AT91_REG ) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register #define AT91C_SPI1_TPR ((AT91_REG ) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register #define AT91C_SPI1_TNPR ((AT91_REG ) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register #define AT91C_SPI1_TCR ((AT91_REG ) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register #define AT91C_SPI1_RCR ((AT91_REG ) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register #define AT91C_SPI1_RNPR ((AT91_REG ) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register #define AT91C_SPI1_RNCR ((AT91_REG ) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register #define AT91C_SPI1_PTSR ((AT91_REG ) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register // ========== Register definition for SPI1 peripheral ========== #define AT91C_SPI1_IMR ((AT91_REG ) 0xFFFE401C) // (SPI1) Interrupt Mask Register #define AT91C_SPI1_IER ((AT91_REG ) 0xFFFE4014) // (SPI1) Interrupt Enable Register #define AT91C_SPI1_MR ((AT91_REG ) 0xFFFE4004) // (SPI1) Mode Register #define AT91C_SPI1_RDR ((AT91_REG ) 0xFFFE4008) // (SPI1) Receive Data Register #define AT91C_SPI1_IDR ((AT91_REG ) 0xFFFE4018) // (SPI1) Interrupt Disable Register #define AT91C_SPI1_SR ((AT91_REG ) 0xFFFE4010) // (SPI1) Status Register #define AT91C_SPI1_TDR ((AT91_REG ) 0xFFFE400C) // (SPI1) Transmit Data Register #define AT91C_SPI1_CR ((AT91_REG ) 0xFFFE4000) // (SPI1) Control Register #define AT91C_SPI1_CSR ((AT91_REG ) 0xFFFE4030) // (SPI1) Chip Select Register // ========== Register definition for PDC_SPI0 peripheral ========== #define AT91C_SPI0_PTCR ((AT91_REG ) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register #define AT91C_SPI0_TPR ((AT91_REG ) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register #define AT91C_SPI0_TCR ((AT91_REG ) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register #define AT91C_SPI0_RCR ((AT91_REG ) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register #define AT91C_SPI0_PTSR ((AT91_REG ) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register #define AT91C_SPI0_RNPR ((AT91_REG ) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register #define AT91C_SPI0_RPR ((AT91_REG ) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register #define AT91C_SPI0_TNCR ((AT91_REG ) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register #define AT91C_SPI0_RNCR ((AT91_REG ) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register #define AT91C_SPI0_TNPR ((AT91_REG ) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register // ========== Register definition for SPI0 peripheral ========== #define AT91C_SPI0_IER ((AT91_REG ) 0xFFFE0014) // (SPI0) Interrupt Enable Register #define AT91C_SPI0_SR ((AT91_REG ) 0xFFFE0010) // (SPI0) Status Register #define AT91C_SPI0_IDR ((AT91_REG ) 0xFFFE0018) // (SPI0) Interrupt Disable Register #define AT91C_SPI0_CR ((AT91_REG ) 0xFFFE0000) // (SPI0) Control Register #define AT91C_SPI0_MR ((AT91_REG ) 0xFFFE0004) // (SPI0) Mode Register #define AT91C_SPI0_IMR ((AT91_REG ) 0xFFFE001C) // (SPI0) Interrupt Mask Register #define AT91C_SPI0_TDR ((AT91_REG ) 0xFFFE000C) // (SPI0) Transmit Data Register #define AT91C_SPI0_RDR ((AT91_REG ) 0xFFFE0008) // (SPI0) Receive Data Register #define AT91C_SPI0_CSR ((AT91_REG ) 0xFFFE0030) // (SPI0) Chip Select Register // ========== Register definition for PDC_US1 peripheral ========== #define AT91C_US1_RNCR ((AT91_REG ) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register #define AT91C_US1_PTCR ((AT91_REG ) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register #define AT91C_US1_TCR ((AT91_REG ) 0xFFFC410C) // (PDC_US1) Transmit Counter Register #define AT91C_US1_PTSR ((AT91_REG ) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register #define AT91C_US1_TNPR ((AT91_REG ) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register #define AT91C_US1_RCR ((AT91_REG ) 0xFFFC4104) // (PDC_US1) Receive Counter Register #define AT91C_US1_RNPR ((AT91_REG ) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register #define AT91C_US1_RPR ((AT91_REG ) 0xFFFC4100) // (PDC_US1) Receive Pointer Register #define AT91C_US1_TNCR ((AT91_REG ) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register #define AT91C_US1_TPR ((AT91_REG ) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register // ========== Register definition for US1 peripheral ========== #define AT91C_US1_IF ((AT91_REG ) 0xFFFC404C) // (US1) IRDA_FILTER Register #define AT91C_US1_NER ((AT91_REG ) 0xFFFC4044) // (US1) Nb Errors Register #define AT91C_US1_RTOR ((AT91_REG ) 0xFFFC4024) // (US1) Receiver Time-out Register #define AT91C_US1_CSR ((AT91_REG ) 0xFFFC4014) // (US1) Channel Status Register #define AT91C_US1_IDR ((AT91_REG ) 0xFFFC400C) // (US1) Interrupt Disable Register #define AT91C_US1_IER ((AT91_REG ) 0xFFFC4008) // (US1) Interrupt Enable Register #define AT91C_US1_THR ((AT91_REG ) 0xFFFC401C) // (US1) Transmitter Holding Register #define AT91C_US1_TTGR ((AT91_REG ) 0xFFFC4028) // (US1) Transmitter Time-guard Register #define AT91C_US1_RHR ((AT91_REG ) 0xFFFC4018) // (US1) Receiver Holding Register #define AT91C_US1_BRGR ((AT91_REG ) 0xFFFC4020) // (US1) Baud Rate Generator Register #define AT91C_US1_IMR ((AT91_REG ) 0xFFFC4010) // (US1) Interrupt Mask Register #define AT91C_US1_FIDI ((AT91_REG ) 0xFFFC4040) // (US1) FI_DI_Ratio Register #define AT91C_US1_CR ((AT91_REG ) 0xFFFC4000) // (US1) Control Register #define AT91C_US1_MR ((AT91_REG ) 0xFFFC4004) // (US1) Mode Register // ========== Register definition for PDC_US0 peripheral ========== #define AT91C_US0_TNPR ((AT91_REG ) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register #define AT91C_US0_RNPR ((AT91_REG ) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register #define AT91C_US0_TCR ((AT91_REG ) 0xFFFC010C) // (PDC_US0) Transmit Counter Register #define AT91C_US0_PTCR ((AT91_REG ) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register #define AT91C_US0_PTSR ((AT91_REG ) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register #define AT91C_US0_TNCR ((AT91_REG ) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register #define AT91C_US0_TPR ((AT91_REG ) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register #define AT91C_US0_RCR ((AT91_REG ) 0xFFFC0104) // (PDC_US0) Receive Counter Register #define AT91C_US0_RPR ((AT91_REG ) 0xFFFC0100) // (PDC_US0) Receive Pointer Register #define AT91C_US0_RNCR ((AT91_REG ) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register // ========== Register definition for US0 peripheral ========== #define AT91C_US0_BRGR ((AT91_REG ) 0xFFFC0020) // (US0) Baud Rate Generator Register #define AT91C_US0_NER ((AT91_REG ) 0xFFFC0044) // (US0) Nb Errors Register #define AT91C_US0_CR ((AT91_REG ) 0xFFFC0000) // (US0) Control Register #define AT91C_US0_IMR ((AT91_REG ) 0xFFFC0010) // (US0) Interrupt Mask Register #define AT91C_US0_FIDI ((AT91_REG ) 0xFFFC0040) // (US0) FI_DI_Ratio Register #define AT91C_US0_TTGR ((AT91_REG ) 0xFFFC0028) // (US0) Transmitter Time-guard Register #define AT91C_US0_MR ((AT91_REG ) 0xFFFC0004) // (US0) Mode Register #define AT91C_US0_RTOR ((AT91_REG ) 0xFFFC0024) // (US0) Receiver Time-out Register #define AT91C_US0_CSR ((AT91_REG ) 0xFFFC0014) // (US0) Channel Status Register #define AT91C_US0_RHR ((AT91_REG ) 0xFFFC0018) // (US0) Receiver Holding Register #define AT91C_US0_IDR ((AT91_REG ) 0xFFFC000C) // (US0) Interrupt Disable Register #define AT91C_US0_THR ((AT91_REG ) 0xFFFC001C) // (US0) Transmitter Holding Register #define AT91C_US0_IF ((AT91_REG ) 0xFFFC004C) // (US0) IRDA_FILTER Register #define AT91C_US0_IER ((AT91_REG ) 0xFFFC0008) // (US0) Interrupt Enable Register // ========== Register definition for PDC_SSC peripheral ========== #define AT91C_SSC_TNCR ((AT91_REG ) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register #define AT91C_SSC_RPR ((AT91_REG ) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register #define AT91C_SSC_RNCR ((AT91_REG ) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register #define AT91C_SSC_TPR ((AT91_REG ) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register #define AT91C_SSC_PTCR ((AT91_REG ) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register #define AT91C_SSC_TCR ((AT91_REG ) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register #define AT91C_SSC_RCR ((AT91_REG ) 0xFFFD4104) // (PDC_SSC) Receive Counter Register #define AT91C_SSC_RNPR ((AT91_REG ) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register #define AT91C_SSC_TNPR ((AT91_REG ) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register #define AT91C_SSC_PTSR ((AT91_REG ) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register // ========== Register definition for SSC peripheral ========== #define AT91C_SSC_RHR ((AT91_REG ) 0xFFFD4020) // (SSC) Receive Holding Register #define AT91C_SSC_RSHR ((AT91_REG ) 0xFFFD4030) // (SSC) Receive Sync Holding Register #define AT91C_SSC_TFMR ((AT91_REG ) 0xFFFD401C) // (SSC) Transmit Frame Mode Register #define AT91C_SSC_IDR ((AT91_REG ) 0xFFFD4048) // (SSC) Interrupt Disable Register #define AT91C_SSC_THR ((AT91_REG ) 0xFFFD4024) // (SSC) Transmit Holding Register #define AT91C_SSC_RCMR ((AT91_REG ) 0xFFFD4010) // (SSC) Receive Clock ModeRegister #define AT91C_SSC_IER ((AT91_REG ) 0xFFFD4044) // (SSC) Interrupt Enable Register #define AT91C_SSC_TSHR ((AT91_REG ) 0xFFFD4034) // (SSC) Transmit Sync Holding Register #define AT91C_SSC_SR ((AT91_REG ) 0xFFFD4040) // (SSC) Status Register #define AT91C_SSC_CMR ((AT91_REG ) 0xFFFD4004) // (SSC) Clock Mode Register #define AT91C_SSC_TCMR ((AT91_REG ) 0xFFFD4018) // (SSC) Transmit Clock Mode Register #define AT91C_SSC_CR ((AT91_REG ) 0xFFFD4000) // (SSC) Control Register #define AT91C_SSC_IMR ((AT91_REG ) 0xFFFD404C) // (SSC) Interrupt Mask Register #define AT91C_SSC_RFMR ((AT91_REG ) 0xFFFD4014) // (SSC) Receive Frame Mode Register // ========== Register definition for TWI peripheral ========== #define AT91C_TWI_IER ((AT91_REG ) 0xFFFB8024) // (TWI) Interrupt Enable Register #define AT91C_TWI_CR ((AT91_REG ) 0xFFFB8000) // (TWI) Control Register #define AT91C_TWI_SR ((AT91_REG ) 0xFFFB8020) // (TWI) Status Register #define AT91C_TWI_IMR ((AT91_REG ) 0xFFFB802C) // (TWI) Interrupt Mask Register #define AT91C_TWI_THR ((AT91_REG ) 0xFFFB8034) // (TWI) Transmit Holding Register #define AT91C_TWI_IDR ((AT91_REG ) 0xFFFB8028) // (TWI) Interrupt Disable Register #define AT91C_TWI_IADR ((AT91_REG ) 0xFFFB800C) // (TWI) Internal Address Register #define AT91C_TWI_MMR ((AT91_REG ) 0xFFFB8004) // (TWI) Master Mode Register #define AT91C_TWI_CWGR ((AT91_REG ) 0xFFFB8010) // (TWI) Clock Waveform Generator Register #define AT91C_TWI_RHR ((AT91_REG ) 0xFFFB8030) // (TWI) Receive Holding Register // ========== Register definition for PWMC_CH3 peripheral ========== #define AT91C_PWMC_CH3_CUPDR ((AT91_REG ) 0xFFFCC270) // (PWMC_CH3) Channel Update Register #define AT91C_PWMC_CH3_Reserved ((AT91_REG ) 0xFFFCC274) // (PWMC_CH3) Reserved #define AT91C_PWMC_CH3_CPRDR ((AT91_REG ) 0xFFFCC268) // (PWMC_CH3) Channel Period Register #define AT91C_PWMC_CH3_CDTYR ((AT91_REG ) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register #define AT91C_PWMC_CH3_CCNTR ((AT91_REG ) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register #define AT91C_PWMC_CH3_CMR ((AT91_REG ) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register // ========== Register definition for PWMC_CH2 peripheral ========== #define AT91C_PWMC_CH2_Reserved ((AT91_REG ) 0xFFFCC254) // (PWMC_CH2) Reserved #define AT91C_PWMC_CH2_CMR ((AT91_REG ) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register #define AT91C_PWMC_CH2_CCNTR ((AT91_REG ) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register #define AT91C_PWMC_CH2_CPRDR ((AT91_REG ) 0xFFFCC248) // (PWMC_CH2) Channel Period Register #define AT91C_PWMC_CH2_CUPDR ((AT91_REG ) 0xFFFCC250) // (PWMC_CH2) Channel Update Register #define AT91C_PWMC_CH2_CDTYR ((AT91_REG ) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register // ========== Register definition for PWMC_CH1 peripheral ========== #define AT91C_PWMC_CH1_Reserved ((AT91_REG ) 0xFFFCC234) // (PWMC_CH1) Reserved #define AT91C_PWMC_CH1_CUPDR ((AT91_REG ) 0xFFFCC230) // (PWMC_CH1) Channel Update Register #define AT91C_PWMC_CH1_CPRDR ((AT91_REG ) 0xFFFCC228) // (PWMC_CH1) Channel Period Register #define AT91C_PWMC_CH1_CCNTR ((AT91_REG ) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register #define AT91C_PWMC_CH1_CDTYR ((AT91_REG ) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register #define AT91C_PWMC_CH1_CMR ((AT91_REG ) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register // ========== Register definition for PWMC_CH0 peripheral ========== #define AT91C_PWMC_CH0_Reserved ((AT91_REG ) 0xFFFCC214) // (PWMC_CH0) Reserved #define AT91C_PWMC_CH0_CPRDR ((AT91_REG ) 0xFFFCC208) // (PWMC_CH0) Channel Period Register #define AT91C_PWMC_CH0_CDTYR ((AT91_REG ) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register #define AT91C_PWMC_CH0_CMR ((AT91_REG ) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register #define AT91C_PWMC_CH0_CUPDR ((AT91_REG ) 0xFFFCC210) // (PWMC_CH0) Channel Update Register #define AT91C_PWMC_CH0_CCNTR ((AT91_REG ) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register // ========== Register definition for PWMC peripheral ========== #define AT91C_PWMC_IDR ((AT91_REG ) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register #define AT91C_PWMC_DIS ((AT91_REG ) 0xFFFCC008) // (PWMC) PWMC Disable Register #define AT91C_PWMC_IER ((AT91_REG ) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register #define AT91C_PWMC_VR ((AT91_REG ) 0xFFFCC0FC) // (PWMC) PWMC Version Register #define AT91C_PWMC_ISR ((AT91_REG ) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register #define AT91C_PWMC_SR ((AT91_REG ) 0xFFFCC00C) // (PWMC) PWMC Status Register #define AT91C_PWMC_IMR ((AT91_REG ) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register #define AT91C_PWMC_MR ((AT91_REG ) 0xFFFCC000) // (PWMC) PWMC Mode Register #define AT91C_PWMC_ENA ((AT91_REG ) 0xFFFCC004) // (PWMC) PWMC Enable Register // ========== Register definition for UDP peripheral ========== #define AT91C_UDP_IMR ((AT91_REG ) 0xFFFB0018) // (UDP) Interrupt Mask Register #define AT91C_UDP_FADDR ((AT91_REG ) 0xFFFB0008) // (UDP) Function Address Register #define AT91C_UDP_NUM ((AT91_REG ) 0xFFFB0000) // (UDP) Frame Number Register #define AT91C_UDP_FDR ((AT91_REG ) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register #define AT91C_UDP_ISR ((AT91_REG ) 0xFFFB001C) // (UDP) Interrupt Status Register #define AT91C_UDP_CSR ((AT91_REG ) 0xFFFB0030) // (UDP) Endpoint Control and Status Register #define AT91C_UDP_IDR ((AT91_REG ) 0xFFFB0014) // (UDP) Interrupt Disable Register #define AT91C_UDP_ICR ((AT91_REG ) 0xFFFB0020) // (UDP) Interrupt Clear Register #define AT91C_UDP_RSTEP ((AT91_REG ) 0xFFFB0028) // (UDP) Reset Endpoint Register #define AT91C_UDP_TXVC ((AT91_REG ) 0xFFFB0074) // (UDP) Transceiver Control Register #define AT91C_UDP_GLBSTATE ((AT91_REG ) 0xFFFB0004) // (UDP) Global State Register #define AT91C_UDP_IER ((AT91_REG ) 0xFFFB0010) // (UDP) Interrupt Enable Register // ========== Register definition for TC0 peripheral ========== #define AT91C_TC0_SR ((AT91_REG ) 0xFFFA0020) // (TC0) Status Register #define AT91C_TC0_RC ((AT91_REG ) 0xFFFA001C) // (TC0) Register C #define AT91C_TC0_RB ((AT91_REG ) 0xFFFA0018) // (TC0) Register B #define AT91C_TC0_CCR ((AT91_REG ) 0xFFFA0000) // (TC0) Channel Control Register #define AT91C_TC0_CMR ((AT91_REG ) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) #define AT91C_TC0_IER ((AT91_REG ) 0xFFFA0024) // (TC0) Interrupt Enable Register #define AT91C_TC0_RA ((AT91_REG ) 0xFFFA0014) // (TC0) Register A #define AT91C_TC0_IDR ((AT91_REG ) 0xFFFA0028) // (TC0) Interrupt Disable Register #define AT91C_TC0_CV ((AT91_REG ) 0xFFFA0010) // (TC0) Counter Value #define AT91C_TC0_IMR ((AT91_REG ) 0xFFFA002C) // (TC0) Interrupt Mask Register // ========== Register definition for TC1 peripheral ========== #define AT91C_TC1_RB ((AT91_REG ) 0xFFFA0058) // (TC1) Register B #define AT91C_TC1_CCR ((AT91_REG ) 0xFFFA0040) // (TC1) Channel Control Register #define AT91C_TC1_IER ((AT91_REG ) 0xFFFA0064) // (TC1) Interrupt Enable Register #define AT91C_TC1_IDR ((AT91_REG ) 0xFFFA0068) // (TC1) Interrupt Disable Register #define AT91C_TC1_SR ((AT91_REG ) 0xFFFA0060) // (TC1) Status Register #define AT91C_TC1_CMR ((AT91_REG ) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) #define AT91C_TC1_RA ((AT91_REG ) 0xFFFA0054) // (TC1) Register A #define AT91C_TC1_RC ((AT91_REG ) 0xFFFA005C) // (TC1) Register C #define AT91C_TC1_IMR ((AT91_REG ) 0xFFFA006C) // (TC1) Interrupt Mask Register #define AT91C_TC1_CV ((AT91_REG ) 0xFFFA0050) // (TC1) Counter Value // ========== Register definition for TC2 peripheral ========== #define AT91C_TC2_CMR ((AT91_REG ) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) #define AT91C_TC2_CCR ((AT91_REG ) 0xFFFA0080) // (TC2) Channel Control Register #define AT91C_TC2_CV ((AT91_REG ) 0xFFFA0090) // (TC2) Counter Value #define AT91C_TC2_RA ((AT91_REG ) 0xFFFA0094) // (TC2) Register A #define AT91C_TC2_RB ((AT91_REG ) 0xFFFA0098) // (TC2) Register B #define AT91C_TC2_IDR ((AT91_REG ) 0xFFFA00A8) // (TC2) Interrupt Disable Register #define AT91C_TC2_IMR ((AT91_REG ) 0xFFFA00AC) // (TC2) Interrupt Mask Register #define AT91C_TC2_RC ((AT91_REG ) 0xFFFA009C) // (TC2) Register C #define AT91C_TC2_IER ((AT91_REG ) 0xFFFA00A4) // (TC2) Interrupt Enable Register #define AT91C_TC2_SR ((AT91_REG ) 0xFFFA00A0) // (TC2) Status Register // ========== Register definition for TCB peripheral ========== #define AT91C_TCB_BMR ((AT91_REG ) 0xFFFA00C4) // (TCB) TC Block Mode Register #define AT91C_TCB_BCR ((AT91_REG ) 0xFFFA00C0) // (TCB) TC Block Control Register // ========== Register definition for CAN_MB0 peripheral ========== #define AT91C_CAN_MB0_MDL ((AT91_REG ) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register #define AT91C_CAN_MB0_MAM ((AT91_REG ) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register #define AT91C_CAN_MB0_MCR ((AT91_REG ) 0xFFFD021C) // (CAN_MB0) MailBox Control Register #define AT91C_CAN_MB0_MID ((AT91_REG ) 0xFFFD0208) // (CAN_MB0) MailBox ID Register #define AT91C_CAN_MB0_MSR ((AT91_REG ) 0xFFFD0210) // (CAN_MB0) MailBox Status Register #define AT91C_CAN_MB0_MFID ((AT91_REG ) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register #define AT91C_CAN_MB0_MDH ((AT91_REG ) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register #define AT91C_CAN_MB0_MMR ((AT91_REG ) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register // ========== Register definition for CAN_MB1 peripheral ========== #define AT91C_CAN_MB1_MDL ((AT91_REG ) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register #define AT91C_CAN_MB1_MID ((AT91_REG ) 0xFFFD0228) // (CAN_MB1) MailBox ID Register #define AT91C_CAN_MB1_MMR ((AT91_REG ) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register #define AT91C_CAN_MB1_MSR ((AT91_REG ) 0xFFFD0230) // (CAN_MB1) MailBox Status Register #define AT91C_CAN_MB1_MAM ((AT91_REG ) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register #define AT91C_CAN_MB1_MDH ((AT91_REG ) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register #define AT91C_CAN_MB1_MCR ((AT91_REG ) 0xFFFD023C) // (CAN_MB1) MailBox Control Register #define AT91C_CAN_MB1_MFID ((AT91_REG ) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register // ========== Register definition for CAN_MB2 peripheral ========== #define AT91C_CAN_MB2_MCR ((AT91_REG ) 0xFFFD025C) // (CAN_MB2) MailBox Control Register #define AT91C_CAN_MB2_MDH ((AT91_REG ) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register #define AT91C_CAN_MB2_MID ((AT91_REG ) 0xFFFD0248) // (CAN_MB2) MailBox ID Register #define AT91C_CAN_MB2_MDL ((AT91_REG ) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register #define AT91C_CAN_MB2_MMR ((AT91_REG ) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register #define AT91C_CAN_MB2_MAM ((AT91_REG ) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register #define AT91C_CAN_MB2_MFID ((AT91_REG ) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register #define AT91C_CAN_MB2_MSR ((AT91_REG ) 0xFFFD0250) // (CAN_MB2) MailBox Status Register // ========== Register definition for CAN_MB3 peripheral ========== #define AT91C_CAN_MB3_MFID ((AT91_REG ) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register #define AT91C_CAN_MB3_MAM ((AT91_REG ) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register #define AT91C_CAN_MB3_MID ((AT91_REG ) 0xFFFD0268) // (CAN_MB3) MailBox ID Register #define AT91C_CAN_MB3_MCR ((AT91_REG ) 0xFFFD027C) // (CAN_MB3) MailBox Control Register #define AT91C_CAN_MB3_MMR ((AT91_REG ) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register #define AT91C_CAN_MB3_MSR ((AT91_REG ) 0xFFFD0270) // (CAN_MB3) MailBox Status Register #define AT91C_CAN_MB3_MDL ((AT91_REG ) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register #define AT91C_CAN_MB3_MDH ((AT91_REG ) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register // ========== Register definition for CAN_MB4 peripheral ========== #define AT91C_CAN_MB4_MID ((AT91_REG ) 0xFFFD0288) // (CAN_MB4) MailBox ID Register #define AT91C_CAN_MB4_MMR ((AT91_REG ) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register #define AT91C_CAN_MB4_MDH ((AT91_REG ) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register #define AT91C_CAN_MB4_MFID ((AT91_REG ) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register #define AT91C_CAN_MB4_MSR ((AT91_REG ) 0xFFFD0290) // (CAN_MB4) MailBox Status Register #define AT91C_CAN_MB4_MCR ((AT91_REG ) 0xFFFD029C) // (CAN_MB4) MailBox Control Register #define AT91C_CAN_MB4_MDL ((AT91_REG ) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register #define AT91C_CAN_MB4_MAM ((AT91_REG ) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register // ========== Register definition for CAN_MB5 peripheral ========== #define AT91C_CAN_MB5_MSR ((AT91_REG ) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register #define AT91C_CAN_MB5_MCR ((AT91_REG ) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register #define AT91C_CAN_MB5_MFID ((AT91_REG ) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register #define AT91C_CAN_MB5_MDH ((AT91_REG ) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register #define AT91C_CAN_MB5_MID ((AT91_REG ) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register #define AT91C_CAN_MB5_MMR ((AT91_REG ) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register #define AT91C_CAN_MB5_MDL ((AT91_REG ) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register #define AT91C_CAN_MB5_MAM ((AT91_REG ) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register // ========== Register definition for CAN_MB6 peripheral ========== #define AT91C_CAN_MB6_MFID ((AT91_REG ) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register #define AT91C_CAN_MB6_MID ((AT91_REG ) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register #define AT91C_CAN_MB6_MAM ((AT91_REG ) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register #define AT91C_CAN_MB6_MSR ((AT91_REG ) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register #define AT91C_CAN_MB6_MDL ((AT91_REG ) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register #define AT91C_CAN_MB6_MCR ((AT91_REG ) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register #define AT91C_CAN_MB6_MDH ((AT91_REG ) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register #define AT91C_CAN_MB6_MMR ((AT91_REG ) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register // ========== Register definition for CAN_MB7 peripheral ========== #define AT91C_CAN_MB7_MCR ((AT91_REG ) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register #define AT91C_CAN_MB7_MDH ((AT91_REG ) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register #define AT91C_CAN_MB7_MFID ((AT91_REG ) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register #define AT91C_CAN_MB7_MDL ((AT91_REG ) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register #define AT91C_CAN_MB7_MID ((AT91_REG ) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register #define AT91C_CAN_MB7_MMR ((AT91_REG ) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register #define AT91C_CAN_MB7_MAM ((AT91_REG ) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register #define AT91C_CAN_MB7_MSR ((AT91_REG ) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register // ========== Register definition for CAN peripheral ========== #define AT91C_CAN_TCR ((AT91_REG ) 0xFFFD0024) // (CAN) Transfer Command Register #define AT91C_CAN_IMR ((AT91_REG ) 0xFFFD000C) // (CAN) Interrupt Mask Register #define AT91C_CAN_IER ((AT91_REG ) 0xFFFD0004) // (CAN) Interrupt Enable Register #define AT91C_CAN_ECR ((AT91_REG ) 0xFFFD0020) // (CAN) Error Counter Register #define AT91C_CAN_TIMESTP ((AT91_REG ) 0xFFFD001C) // (CAN) Time Stamp Register #define AT91C_CAN_MR ((AT91_REG ) 0xFFFD0000) // (CAN) Mode Register #define AT91C_CAN_IDR ((AT91_REG ) 0xFFFD0008) // (CAN) Interrupt Disable Register #define AT91C_CAN_ACR ((AT91_REG ) 0xFFFD0028) // (CAN) Abort Command Register #define AT91C_CAN_TIM ((AT91_REG ) 0xFFFD0018) // (CAN) Timer Register #define AT91C_CAN_SR ((AT91_REG ) 0xFFFD0010) // (CAN) Status Register #define AT91C_CAN_BR ((AT91_REG ) 0xFFFD0014) // (CAN) Baudrate Register #define AT91C_CAN_VR ((AT91_REG ) 0xFFFD00FC) // (CAN) Version Register // ========== Register definition for EMAC peripheral ========== #define AT91C_EMAC_ISR ((AT91_REG ) 0xFFFDC024) // (EMAC) Interrupt Status Register #define AT91C_EMAC_SA4H ((AT91_REG ) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes #define AT91C_EMAC_SA1L ((AT91_REG ) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes #define AT91C_EMAC_ELE ((AT91_REG ) 0xFFFDC078) // (EMAC) Excessive Length Errors Register #define AT91C_EMAC_LCOL ((AT91_REG ) 0xFFFDC05C) // (EMAC) Late Collision Register #define AT91C_EMAC_RLE ((AT91_REG ) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register #define AT91C_EMAC_WOL ((AT91_REG ) 0xFFFDC0C4) // (EMAC) Wake On LAN Register #define AT91C_EMAC_DTF ((AT91_REG ) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register #define AT91C_EMAC_TUND ((AT91_REG ) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register #define AT91C_EMAC_NCR ((AT91_REG ) 0xFFFDC000) // (EMAC) Network Control Register #define AT91C_EMAC_SA4L ((AT91_REG ) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes #define AT91C_EMAC_RSR ((AT91_REG ) 0xFFFDC020) // (EMAC) Receive Status Register #define AT91C_EMAC_SA3L ((AT91_REG ) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes #define AT91C_EMAC_TSR ((AT91_REG ) 0xFFFDC014) // (EMAC) Transmit Status Register #define AT91C_EMAC_IDR ((AT91_REG ) 0xFFFDC02C) // (EMAC) Interrupt Disable Register #define AT91C_EMAC_RSE ((AT91_REG ) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register #define AT91C_EMAC_ECOL ((AT91_REG ) 0xFFFDC060) // (EMAC) Excessive Collision Register #define AT91C_EMAC_TID ((AT91_REG ) 0xFFFDC0B8) // (EMAC) Type ID Checking Register #define AT91C_EMAC_HRB ((AT91_REG ) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] #define AT91C_EMAC_TBQP ((AT91_REG ) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer #define AT91C_EMAC_USRIO ((AT91_REG ) 0xFFFDC0C0) // (EMAC) USER Input/Output Register #define AT91C_EMAC_PTR ((AT91_REG ) 0xFFFDC038) // (EMAC) Pause Time Register #define AT91C_EMAC_SA2H ((AT91_REG ) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes #define AT91C_EMAC_ROV ((AT91_REG ) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register #define AT91C_EMAC_ALE ((AT91_REG ) 0xFFFDC054) // (EMAC) Alignment Error Register #define AT91C_EMAC_RJA ((AT91_REG ) 0xFFFDC07C) // (EMAC) Receive Jabbers Register #define AT91C_EMAC_RBQP ((AT91_REG ) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer #define AT91C_EMAC_TPF ((AT91_REG ) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register #define AT91C_EMAC_NCFGR ((AT91_REG ) 0xFFFDC004) // (EMAC) Network Configuration Register #define AT91C_EMAC_HRT ((AT91_REG ) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] #define AT91C_EMAC_USF ((AT91_REG ) 0xFFFDC080) // (EMAC) Undersize Frames Register #define AT91C_EMAC_FCSE ((AT91_REG ) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register #define AT91C_EMAC_TPQ ((AT91_REG ) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register #define AT91C_EMAC_MAN ((AT91_REG ) 0xFFFDC034) // (EMAC) PHY Maintenance Register #define AT91C_EMAC_FTO ((AT91_REG ) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register #define AT91C_EMAC_REV ((AT91_REG ) 0xFFFDC0FC) // (EMAC) Revision Register #define AT91C_EMAC_IMR ((AT91_REG ) 0xFFFDC030) // (EMAC) Interrupt Mask Register #define AT91C_EMAC_SCF ((AT91_REG ) 0xFFFDC044) // (EMAC) Single Collision Frame Register #define AT91C_EMAC_PFR ((AT91_REG ) 0xFFFDC03C) // (EMAC) Pause Frames received Register #define AT91C_EMAC_MCF ((AT91_REG ) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register #define AT91C_EMAC_NSR ((AT91_REG ) 0xFFFDC008) // (EMAC) Network Status Register #define AT91C_EMAC_SA2L ((AT91_REG ) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes #define AT91C_EMAC_FRO ((AT91_REG ) 0xFFFDC04C) // (EMAC) Frames Received OK Register #define AT91C_EMAC_IER ((AT91_REG ) 0xFFFDC028) // (EMAC) Interrupt Enable Register #define AT91C_EMAC_SA1H ((AT91_REG ) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes #define AT91C_EMAC_CSE ((AT91_REG ) 0xFFFDC068) // (EMAC) Carrier Sense Error Register #define AT91C_EMAC_SA3H ((AT91_REG ) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes #define AT91C_EMAC_RRE ((AT91_REG ) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register #define AT91C_EMAC_STE ((AT91_REG ) 0xFFFDC084) // (EMAC) SQE Test Error Register // ========== Register definition for PDC_ADC peripheral ========== #define AT91C_ADC_PTSR ((AT91_REG ) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register #define AT91C_ADC_PTCR ((AT91_REG ) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register #define AT91C_ADC_TNPR ((AT91_REG ) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register #define AT91C_ADC_TNCR ((AT91_REG ) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register #define AT91C_ADC_RNPR ((AT91_REG ) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register #define AT91C_ADC_RNCR ((AT91_REG ) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register #define AT91C_ADC_RPR ((AT91_REG ) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register #define AT91C_ADC_TCR ((AT91_REG ) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register #define AT91C_ADC_TPR ((AT91_REG ) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register #define AT91C_ADC_RCR ((AT91_REG ) 0xFFFD8104) // (PDC_ADC) Receive Counter Register // ========== Register definition for ADC peripheral ========== #define AT91C_ADC_CDR2 ((AT91_REG ) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 #define AT91C_ADC_CDR3 ((AT91_REG ) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 #define AT91C_ADC_CDR0 ((AT91_REG ) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 #define AT91C_ADC_CDR5 ((AT91_REG ) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 #define AT91C_ADC_CHDR ((AT91_REG ) 0xFFFD8014) // (ADC) ADC Channel Disable Register #define AT91C_ADC_SR ((AT91_REG ) 0xFFFD801C) // (ADC) ADC Status Register #define AT91C_ADC_CDR4 ((AT91_REG ) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 #define AT91C_ADC_CDR1 ((AT91_REG ) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 #define AT91C_ADC_LCDR ((AT91_REG ) 0xFFFD8020) // (ADC) ADC Last Converted Data Register #define AT91C_ADC_IDR ((AT91_REG ) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register #define AT91C_ADC_CR ((AT91_REG ) 0xFFFD8000) // (ADC) ADC Control Register #define AT91C_ADC_CDR7 ((AT91_REG ) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 #define AT91C_ADC_CDR6 ((AT91_REG ) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 #define AT91C_ADC_IER ((AT91_REG ) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register #define AT91C_ADC_CHER ((AT91_REG ) 0xFFFD8010) // (ADC) ADC Channel Enable Register #define AT91C_ADC_CHSR ((AT91_REG ) 0xFFFD8018) // (ADC) ADC Channel Status Register #define AT91C_ADC_MR ((AT91_REG ) 0xFFFD8004) // (ADC) ADC Mode Register #define AT91C_ADC_IMR ((AT91_REG ) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register // ========== Register definition for PDC_AES peripheral ========== #define AT91C_AES_TPR ((AT91_REG ) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register #define AT91C_AES_PTCR ((AT91_REG ) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register #define AT91C_AES_RNPR ((AT91_REG ) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register #define AT91C_AES_TNCR ((AT91_REG ) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register #define AT91C_AES_TCR ((AT91_REG ) 0xFFFA410C) // (PDC_AES) Transmit Counter Register #define AT91C_AES_RCR ((AT91_REG ) 0xFFFA4104) // (PDC_AES) Receive Counter Register #define AT91C_AES_RNCR ((AT91_REG ) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register #define AT91C_AES_TNPR ((AT91_REG ) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register #define AT91C_AES_RPR ((AT91_REG ) 0xFFFA4100) // (PDC_AES) Receive Pointer Register #define AT91C_AES_PTSR ((AT91_REG ) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register // ========== Register definition for AES peripheral ========== #define AT91C_AES_IVxR ((AT91_REG ) 0xFFFA4060) // (AES) Initialization Vector x Register #define AT91C_AES_MR ((AT91_REG ) 0xFFFA4004) // (AES) Mode Register #define AT91C_AES_VR ((AT91_REG ) 0xFFFA40FC) // (AES) AES Version Register #define AT91C_AES_ODATAxR ((AT91_REG ) 0xFFFA4050) // (AES) Output Data x Register #define AT91C_AES_IDATAxR ((AT91_REG ) 0xFFFA4040) // (AES) Input Data x Register #define AT91C_AES_CR ((AT91_REG ) 0xFFFA4000) // (AES) Control Register #define AT91C_AES_IDR ((AT91_REG ) 0xFFFA4014) // (AES) Interrupt Disable Register #define AT91C_AES_IMR ((AT91_REG ) 0xFFFA4018) // (AES) Interrupt Mask Register #define AT91C_AES_IER ((AT91_REG ) 0xFFFA4010) // (AES) Interrupt Enable Register #define AT91C_AES_KEYWxR ((AT91_REG ) 0xFFFA4020) // (AES) Key Word x Register #define AT91C_AES_ISR ((AT91_REG ) 0xFFFA401C) // (AES) Interrupt Status Register // ========== Register definition for PDC_TDES peripheral ========== #define AT91C_TDES_RNCR ((AT91_REG ) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register #define AT91C_TDES_TCR ((AT91_REG ) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register #define AT91C_TDES_RCR ((AT91_REG ) 0xFFFA8104) // (PDC_TDES) Receive Counter Register #define AT91C_TDES_TNPR ((AT91_REG ) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register #define AT91C_TDES_RNPR ((AT91_REG ) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register #define AT91C_TDES_RPR ((AT91_REG ) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register #define AT91C_TDES_TNCR ((AT91_REG ) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register #define AT91C_TDES_TPR ((AT91_REG ) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register #define AT91C_TDES_PTSR ((AT91_REG ) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register #define AT91C_TDES_PTCR ((AT91_REG ) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register // ========== Register definition for TDES peripheral ========== #define AT91C_TDES_KEY2WxR ((AT91_REG ) 0xFFFA8028) // (TDES) Key 2 Word x Register #define AT91C_TDES_KEY3WxR ((AT91_REG ) 0xFFFA8030) // (TDES) Key 3 Word x Register #define AT91C_TDES_IDR ((AT91_REG ) 0xFFFA8014) // (TDES) Interrupt Disable Register #define AT91C_TDES_VR ((AT91_REG ) 0xFFFA80FC) // (TDES) TDES Version Register #define AT91C_TDES_IVxR ((AT91_REG ) 0xFFFA8060) // (TDES) Initialization Vector x Register #define AT91C_TDES_ODATAxR ((AT91_REG ) 0xFFFA8050) // (TDES) Output Data x Register #define AT91C_TDES_IMR ((AT91_REG ) 0xFFFA8018) // (TDES) Interrupt Mask Register #define AT91C_TDES_MR ((AT91_REG ) 0xFFFA8004) // (TDES) Mode Register #define AT91C_TDES_CR ((AT91_REG ) 0xFFFA8000) // (TDES) Control Register #define AT91C_TDES_IER ((AT91_REG ) 0xFFFA8010) // (TDES) Interrupt Enable Register #define AT91C_TDES_ISR ((AT91_REG ) 0xFFFA801C) // (TDES) Interrupt Status Register #define AT91C_TDES_IDATAxR ((AT91_REG ) 0xFFFA8040) // (TDES) Input Data x Register #define AT91C_TDES_KEY1WxR ((AT91_REG ) 0xFFFA8020) // (TDES) Key 1 Word x Register // ************************************************************************** // PIO DEFINITIONS FOR AT91SAM7X256 // ************************************************************************* #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 #define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 #define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 #define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 #define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 #define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 #define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 #define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 #define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 #define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 #define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 #define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 #define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 #define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 #define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 #define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock #define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 #define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 #define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync #define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 #define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock #define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 #define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data #define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 #define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data #define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 #define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock #define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 #define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync #define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 #define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data #define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 #define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 #define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input #define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 #define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send #define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 #define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 #define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 #define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send #define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 #define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 #define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 #define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock #define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 #define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send #define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 #define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send #define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 #define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock #define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 #define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable #define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 #define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 #define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 #define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 #define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 #define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 #define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 #define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error #define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input #define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 #define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 #define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 #define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 #define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 #define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 #define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 #define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid #define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 #define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected #define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 #define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 #define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock #define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 #define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 #define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec #define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger #define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 #define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 #define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 #define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 #define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 #define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 #define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 #define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 #define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 #define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 #define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 #define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 #define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A #define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect #define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 #define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B #define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 #define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A #define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready #define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 #define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B #define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator #define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 #define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A #define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 #define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 #define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B #define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 #define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 #define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 #define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 #define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 #define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 #define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 #define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 #define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 #define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 #define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 #define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error #define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 #define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock #define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 #define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output // ************************************************************************* // PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 // ************************************************************************* #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral #define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A #define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B #define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 #define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 #define AT91C_ID_US0 ((unsigned int) 6) // USART 0 #define AT91C_ID_US1 ((unsigned int) 7) // USART 1 #define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller #define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface #define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller #define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port #define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 #define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 #define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 #define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller #define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC #define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter #define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit #define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard #define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved #define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved #define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved #define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved #define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved #define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved #define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved #define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved #define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved #define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved #define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) // ************************************************************************* // BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 // ************************************************************************* #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address #define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address #define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address #define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address #define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address #define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address #define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address #define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address #define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address #define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address #define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address #define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address #define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address #define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address #define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address #define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address #define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address #define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address #define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address #define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address #define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address #define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address #define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address #define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address #define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address #define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address #define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address #define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address #define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address // ************************************************************************* // MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 // *************************************************************************** #define AT91C_ISRAM ((char ) 0x00200000) // Internal SRAM base address #define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) #define AT91C_IFLASH ((char ) 0x00100000) // Internal ROM base address #define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) #define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ { \ unsigned int mask ; \ \ mask = 0x1 << irq_id; \ /* Disable the interrupt on the interrupt controller / \ AT91C_BASE_AIC->AIC_IDCR = mask ; \ / Save the interrupt handler routine pointer and the interrupt priority / \ AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \ / Store the Source Mode Register / \ AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type \| priority ; \ / Clear the interrupt on the interrupt controller */ \ AT91C_BASE_AIC->AIC_ICCR = mask ; \ } #endif	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h	C	oos	208,708
//* ---------------------------------------------------------------------------- //* ATMEL Microcontroller Software Support - ROUSSET - //* ---------------------------------------------------------------------------- //* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR //* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF //* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE //* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, //* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT //* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, //* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING //* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //* ---------------------------------------------------------------------------- //* File Name : lib_AT91SAM7X256.h //* Object : AT91SAM7X256 inlined functions //* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) //* //* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// //* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// //* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// //* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// //* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// //* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// //* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// //* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// //* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// //* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// //* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// //* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// //* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// //* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// //* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// //* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// //* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// //* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// //* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// //* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// //* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// //* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// //* ---------------------------------------------------------------------------- #include "AT91SAM7X256.h" //---------------------------------------------------------------------------- // \fn AT91F_AIC_ConfigureIt //* \brief Interrupt Handler Initialization //*----------------------------------------------------------------------------	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c	C	oos	3,232
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the ARM7 port. * * Components that can be compiled to either ARM or THUMB mode are * contained in this file. The ISR routines, which can only be compiled * to ARM mode are contained in portISR.c. ----------------------------------------------------------/ /* Standard includes. / #include <stdlib.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Processor constants. / #include "AT91SAM7X256.h" / Constants required to setup the task context. / #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) / System mode, ARM mode, interrupts enabled. / #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) #define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) / Constants required to setup the tick ISR. / #define portENABLE_TIMER ( ( unsigned char ) 0x01 ) #define portPRESCALE_VALUE 0x00 #define portINTERRUPT_ON_MATCH ( ( unsigned long ) 0x01 ) #define portRESET_COUNT_ON_MATCH ( ( unsigned long ) 0x02 ) / Constants required to setup the PIT. / #define portPIT_CLOCK_DIVISOR ( ( unsigned long ) 16 ) #define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) portTICK_RATE_MS ) #define portINT_LEVEL_SENSITIVE 0 #define portPIT_ENABLE ( ( unsigned short ) 0x1 << 24 ) #define portPIT_INT_ENABLE ( ( unsigned short ) 0x1 << 25 ) /-----------------------------------------------------------/ /* Setup the timer to generate the tick interrupts. / static void prvSetupTimerInterrupt( void ); / * The scheduler can only be started from ARM mode, so * vPortISRStartFirstSTask() is defined in portISR.c. / extern void vPortISRStartFirstTask( void ); /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been called. * * See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { portSTACK_TYPE pxOriginalTOS; pxOriginalTOS = pxTopOfStack; / To ensure asserts in tasks.c don't fail, although in this case the assert is not really required. / pxTopOfStack--; / Setup the initial stack of the task. The stack is set exactly as expected by the portRESTORE_CONTEXT() macro. / / First on the stack is the return address - which in this case is the start of the task. The offset is added to make the return address appear as it would within an IRQ ISR. / pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; / R14 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 / pxTopOfStack--; / When the task starts is will expect to find the function parameter in R0. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 / pxTopOfStack--; / The last thing onto the stack is the status register, which is set for system mode, with interrupts enabled. / pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; #ifdef THUMB_INTERWORK { /* We want the task to start in thumb mode. / pxTopOfStack \|= portTHUMB_MODE_BIT; } #endif pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This means the interrupt flags cannot always be stored on the stack and will instead be stored in a variable, which is then saved as part of the tasks context. / pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled here already. / prvSetupTimerInterrupt(); / Start the first task. / vPortISRStartFirstTask(); / Should not get here! / return 0; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the ARM port will require this function as there is nothing to return to. / } /-----------------------------------------------------------/ / * Setup the timer 0 to generate the tick interrupts at the required frequency. / static void prvSetupTimerInterrupt( void ) { AT91PS_PITC pxPIT = AT91C_BASE_PITC; / Setup the AIC for PIT interrupts. The interrupt routine chosen depends on whether the preemptive or cooperative scheduler is being used. / #if configUSE_PREEMPTION == 0 extern void ( vNonPreemptiveTick ) ( void ); AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ()(void) ) vNonPreemptiveTick ); #else extern void ( vPreemptiveTick )( void ); AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ()(void) ) vPreemptiveTick ); #endif / Configure the PIT period. / pxPIT->PITC_PIMR = portPIT_ENABLE \| portPIT_INT_ENABLE \| portPIT_COUNTER_VALUE; / Enable the interrupt. Global interrupts are disables at this point so this is safe. / AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91SAM7S/port.c	C	oos	9,435
// - ---------------------------------------------------------------------------- // - ATMEL Microcontroller Software Support - ROUSSET - // - ---------------------------------------------------------------------------- // - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR // - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF // - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE // - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, // - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, // - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, // - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // - ---------------------------------------------------------------------------- // - File Name : AT91SAM7X256.h // - Object : AT91SAM7X256 definitions // - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) // - // - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// // - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// // - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// // - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// // - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// // - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// // - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// // - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// // - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// // - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// // - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// // - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// // - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// // - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// // - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// // - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// // - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// // - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// // - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// // - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// // - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// // - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// // - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// // - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// // - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// // - ---------------------------------------------------------------------------- #ifndef AT91SAM7X256_H #define AT91SAM7X256_H typedef volatile unsigned int AT91_REG;// Hardware register definition // *************************************************************************** // SOFTWARE API DEFINITION FOR System Peripherals // *************************************************************************** typedef struct _AT91S_SYS { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register AT91_REG Reserved2[45]; // AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved3[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved4[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register AT91_REG Reserved5[54]; // AT91_REG PIOA_PER; // PIO Enable Register AT91_REG PIOA_PDR; // PIO Disable Register AT91_REG PIOA_PSR; // PIO Status Register AT91_REG Reserved6[1]; // AT91_REG PIOA_OER; // Output Enable Register AT91_REG PIOA_ODR; // Output Disable Registerr AT91_REG PIOA_OSR; // Output Status Register AT91_REG Reserved7[1]; // AT91_REG PIOA_IFER; // Input Filter Enable Register AT91_REG PIOA_IFDR; // Input Filter Disable Register AT91_REG PIOA_IFSR; // Input Filter Status Register AT91_REG Reserved8[1]; // AT91_REG PIOA_SODR; // Set Output Data Register AT91_REG PIOA_CODR; // Clear Output Data Register AT91_REG PIOA_ODSR; // Output Data Status Register AT91_REG PIOA_PDSR; // Pin Data Status Register AT91_REG PIOA_IER; // Interrupt Enable Register AT91_REG PIOA_IDR; // Interrupt Disable Register AT91_REG PIOA_IMR; // Interrupt Mask Register AT91_REG PIOA_ISR; // Interrupt Status Register AT91_REG PIOA_MDER; // Multi-driver Enable Register AT91_REG PIOA_MDDR; // Multi-driver Disable Register AT91_REG PIOA_MDSR; // Multi-driver Status Register AT91_REG Reserved9[1]; // AT91_REG PIOA_PPUDR; // Pull-up Disable Register AT91_REG PIOA_PPUER; // Pull-up Enable Register AT91_REG PIOA_PPUSR; // Pull-up Status Register AT91_REG Reserved10[1]; // AT91_REG PIOA_ASR; // Select A Register AT91_REG PIOA_BSR; // Select B Register AT91_REG PIOA_ABSR; // AB Select Status Register AT91_REG Reserved11[9]; // AT91_REG PIOA_OWER; // Output Write Enable Register AT91_REG PIOA_OWDR; // Output Write Disable Register AT91_REG PIOA_OWSR; // Output Write Status Register AT91_REG Reserved12[85]; // AT91_REG PIOB_PER; // PIO Enable Register AT91_REG PIOB_PDR; // PIO Disable Register AT91_REG PIOB_PSR; // PIO Status Register AT91_REG Reserved13[1]; // AT91_REG PIOB_OER; // Output Enable Register AT91_REG PIOB_ODR; // Output Disable Registerr AT91_REG PIOB_OSR; // Output Status Register AT91_REG Reserved14[1]; // AT91_REG PIOB_IFER; // Input Filter Enable Register AT91_REG PIOB_IFDR; // Input Filter Disable Register AT91_REG PIOB_IFSR; // Input Filter Status Register AT91_REG Reserved15[1]; // AT91_REG PIOB_SODR; // Set Output Data Register AT91_REG PIOB_CODR; // Clear Output Data Register AT91_REG PIOB_ODSR; // Output Data Status Register AT91_REG PIOB_PDSR; // Pin Data Status Register AT91_REG PIOB_IER; // Interrupt Enable Register AT91_REG PIOB_IDR; // Interrupt Disable Register AT91_REG PIOB_IMR; // Interrupt Mask Register AT91_REG PIOB_ISR; // Interrupt Status Register AT91_REG PIOB_MDER; // Multi-driver Enable Register AT91_REG PIOB_MDDR; // Multi-driver Disable Register AT91_REG PIOB_MDSR; // Multi-driver Status Register AT91_REG Reserved16[1]; // AT91_REG PIOB_PPUDR; // Pull-up Disable Register AT91_REG PIOB_PPUER; // Pull-up Enable Register AT91_REG PIOB_PPUSR; // Pull-up Status Register AT91_REG Reserved17[1]; // AT91_REG PIOB_ASR; // Select A Register AT91_REG PIOB_BSR; // Select B Register AT91_REG PIOB_ABSR; // AB Select Status Register AT91_REG Reserved18[9]; // AT91_REG PIOB_OWER; // Output Write Enable Register AT91_REG PIOB_OWDR; // Output Write Disable Register AT91_REG PIOB_OWSR; // Output Write Status Register AT91_REG Reserved19[341]; // AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved20[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved21[1]; // AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG Reserved22[1]; // AT91_REG PMC_PLLR; // PLL Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved23[3]; // AT91_REG PMC_PCKR[4]; // Programmable Clock Register AT91_REG Reserved24[4]; // AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register AT91_REG Reserved25[36]; // AT91_REG RSTC_RCR; // Reset Control Register AT91_REG RSTC_RSR; // Reset Status Register AT91_REG RSTC_RMR; // Reset Mode Register AT91_REG Reserved26[5]; // AT91_REG RTTC_RTMR; // Real-time Mode Register AT91_REG RTTC_RTAR; // Real-time Alarm Register AT91_REG RTTC_RTVR; // Real-time Value Register AT91_REG RTTC_RTSR; // Real-time Status Register AT91_REG PITC_PIMR; // Period Interval Mode Register AT91_REG PITC_PISR; // Period Interval Status Register AT91_REG PITC_PIVR; // Period Interval Value Register AT91_REG PITC_PIIR; // Period Interval Image Register AT91_REG WDTC_WDCR; // Watchdog Control Register AT91_REG WDTC_WDMR; // Watchdog Mode Register AT91_REG WDTC_WDSR; // Watchdog Status Register AT91_REG Reserved27[5]; // AT91_REG VREG_MR; // Voltage Regulator Mode Register } AT91S_SYS, AT91PS_SYS; // ************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller // *************************************************************************** typedef struct _AT91S_AIC { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register } AT91S_AIC, AT91PS_AIC; // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask // ************************************************************************** // SOFTWARE API DEFINITION FOR Peripheral DMA Controller // *************************************************************************** typedef struct _AT91S_PDC { AT91_REG PDC_RPR; // Receive Pointer Register AT91_REG PDC_RCR; // Receive Counter Register AT91_REG PDC_TPR; // Transmit Pointer Register AT91_REG PDC_TCR; // Transmit Counter Register AT91_REG PDC_RNPR; // Receive Next Pointer Register AT91_REG PDC_RNCR; // Receive Next Counter Register AT91_REG PDC_TNPR; // Transmit Next Pointer Register AT91_REG PDC_TNCR; // Transmit Next Counter Register AT91_REG PDC_PTCR; // PDC Transfer Control Register AT91_REG PDC_PTSR; // PDC Transfer Status Register } AT91S_PDC, AT91PS_PDC; // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Debug Unit // *************************************************************************** typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved0[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved1[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register } AT91S_DBGU, AT91PS_DBGU; // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG // ************************************************************************** // SOFTWARE API DEFINITION FOR Parallel Input Output Controler // *************************************************************************** typedef struct _AT91S_PIO { AT91_REG PIO_PER; // PIO Enable Register AT91_REG PIO_PDR; // PIO Disable Register AT91_REG PIO_PSR; // PIO Status Register AT91_REG Reserved0[1]; // AT91_REG PIO_OER; // Output Enable Register AT91_REG PIO_ODR; // Output Disable Registerr AT91_REG PIO_OSR; // Output Status Register AT91_REG Reserved1[1]; // AT91_REG PIO_IFER; // Input Filter Enable Register AT91_REG PIO_IFDR; // Input Filter Disable Register AT91_REG PIO_IFSR; // Input Filter Status Register AT91_REG Reserved2[1]; // AT91_REG PIO_SODR; // Set Output Data Register AT91_REG PIO_CODR; // Clear Output Data Register AT91_REG PIO_ODSR; // Output Data Status Register AT91_REG PIO_PDSR; // Pin Data Status Register AT91_REG PIO_IER; // Interrupt Enable Register AT91_REG PIO_IDR; // Interrupt Disable Register AT91_REG PIO_IMR; // Interrupt Mask Register AT91_REG PIO_ISR; // Interrupt Status Register AT91_REG PIO_MDER; // Multi-driver Enable Register AT91_REG PIO_MDDR; // Multi-driver Disable Register AT91_REG PIO_MDSR; // Multi-driver Status Register AT91_REG Reserved3[1]; // AT91_REG PIO_PPUDR; // Pull-up Disable Register AT91_REG PIO_PPUER; // Pull-up Enable Register AT91_REG PIO_PPUSR; // Pull-up Status Register AT91_REG Reserved4[1]; // AT91_REG PIO_ASR; // Select A Register AT91_REG PIO_BSR; // Select B Register AT91_REG PIO_ABSR; // AB Select Status Register AT91_REG Reserved5[9]; // AT91_REG PIO_OWER; // Output Write Enable Register AT91_REG PIO_OWDR; // Output Write Disable Register AT91_REG PIO_OWSR; // Output Write Status Register } AT91S_PIO, AT91PS_PIO; // ************************************************************************** // SOFTWARE API DEFINITION FOR Clock Generator Controler // *************************************************************************** typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; // Main Oscillator Register AT91_REG CKGR_MCFR; // Main Clock Frequency Register AT91_REG Reserved0[1]; // AT91_REG CKGR_PLLR; // PLL Register } AT91S_CKGR, AT91PS_CKGR; // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 #define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed #define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter #define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range #define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet #define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 // ************************************************************************** // SOFTWARE API DEFINITION FOR Power Management Controler // *************************************************************************** typedef struct _AT91S_PMC { AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved0[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved1[1]; // AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG Reserved2[1]; // AT91_REG PMC_PLLR; // PLL Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved3[3]; // AT91_REG PMC_PCKR[4]; // Programmable Clock Register AT91_REG Reserved4[4]; // AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register } AT91S_PMC, AT91PS_PMC; // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected #define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask #define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Reset Controller Interface // *************************************************************************** typedef struct _AT91S_RSTC { AT91_REG RSTC_RCR; // Reset Control Register AT91_REG RSTC_RSR; // Reset Status Register AT91_REG RSTC_RMR; // Reset Mode Register } AT91S_RSTC, AT91PS_RSTC; // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status #define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type #define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. #define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable #define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable // ************************************************************************** // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface // *************************************************************************** typedef struct _AT91S_RTTC { AT91_REG RTTC_RTMR; // Real-time Mode Register AT91_REG RTTC_RTAR; // Real-time Alarm Register AT91_REG RTTC_RTVR; // Real-time Value Register AT91_REG RTTC_RTSR; // Real-time Status Register } AT91S_RTTC, AT91PS_RTTC; // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment // ************************************************************************** // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface // *************************************************************************** typedef struct _AT91S_PITC { AT91_REG PITC_PIMR; // Period Interval Mode Register AT91_REG PITC_PISR; // Period Interval Status Register AT91_REG PITC_PIVR; // Period Interval Value Register AT91_REG PITC_PIIR; // Period Interval Image Register } AT91S_PITC, AT91PS_PITC; // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface // *************************************************************************** typedef struct _AT91S_WDTC { AT91_REG WDTC_WDCR; // Watchdog Control Register AT91_REG WDTC_WDMR; // Watchdog Mode Register AT91_REG WDTC_WDSR; // Watchdog Status Register } AT91S_WDTC, AT91PS_WDTC; // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error // ************************************************************************** // SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface // *************************************************************************** typedef struct _AT91S_VREG { AT91_REG VREG_MR; // Voltage Regulator Mode Register } AT91S_VREG, AT91PS_VREG; // -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- #define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode // ************************************************************************** // SOFTWARE API DEFINITION FOR Memory Controller Interface // *************************************************************************** typedef struct _AT91S_MC { AT91_REG MC_RCR; // MC Remap Control Register AT91_REG MC_ASR; // MC Abort Status Register AT91_REG MC_AASR; // MC Abort Address Status Register AT91_REG Reserved0[21]; // AT91_REG MC_FMR; // MC Flash Mode Register AT91_REG MC_FCR; // MC Flash Command Register AT91_REG MC_FSR; // MC Flash Status Register } AT91S_MC, AT91PS_MC; // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status #define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status #define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte #define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word #define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word #define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status #define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read #define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write #define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch #define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- #define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready #define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error #define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error #define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming #define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State #define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations #define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations #define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations #define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations #define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- #define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command #define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. #define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. #define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. #define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. #define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. #define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. #define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. #define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. #define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number #define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- #define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status #define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status #define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status #define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status #define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status #define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status #define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status #define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status #define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status #define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status #define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status #define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status #define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status #define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status #define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status #define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status #define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status #define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status #define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status #define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status #define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status #define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status #define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status #define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status #define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status // ************************************************************************** // SOFTWARE API DEFINITION FOR Serial Parallel Interface // *************************************************************************** typedef struct _AT91S_SPI { AT91_REG SPI_CR; // Control Register AT91_REG SPI_MR; // Mode Register AT91_REG SPI_RDR; // Receive Data Register AT91_REG SPI_TDR; // Transmit Data Register AT91_REG SPI_SR; // Status Register AT91_REG SPI_IER; // Interrupt Enable Register AT91_REG SPI_IDR; // Interrupt Disable Register AT91_REG SPI_IMR; // Interrupt Mask Register AT91_REG Reserved0[4]; // AT91_REG SPI_CSR[4]; // Chip Select Register AT91_REG Reserved1[48]; // AT91_REG SPI_RPR; // Receive Pointer Register AT91_REG SPI_RCR; // Receive Counter Register AT91_REG SPI_TPR; // Transmit Pointer Register AT91_REG SPI_TCR; // Transmit Counter Register AT91_REG SPI_RNPR; // Receive Next Pointer Register AT91_REG SPI_RNCR; // Receive Next Counter Register AT91_REG SPI_TNPR; // Transmit Next Pointer Register AT91_REG SPI_TNCR; // Transmit Next Counter Register AT91_REG SPI_PTCR; // PDC Transfer Control Register AT91_REG SPI_PTSR; // PDC Transfer Status Register } AT91S_SPI, AT91PS_SPI; // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status // -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers // ************************************************************************** // SOFTWARE API DEFINITION FOR Usart // *************************************************************************** typedef struct _AT91S_USART { AT91_REG US_CR; // Control Register AT91_REG US_MR; // Mode Register AT91_REG US_IER; // Interrupt Enable Register AT91_REG US_IDR; // Interrupt Disable Register AT91_REG US_IMR; // Interrupt Mask Register AT91_REG US_CSR; // Channel Status Register AT91_REG US_RHR; // Receiver Holding Register AT91_REG US_THR; // Transmitter Holding Register AT91_REG US_BRGR; // Baud Rate Generator Register AT91_REG US_RTOR; // Receiver Time-out Register AT91_REG US_TTGR; // Transmitter Time-guard Register AT91_REG Reserved0[5]; // AT91_REG US_FIDI; // FI_DI_Ratio Register AT91_REG US_NER; // Nb Errors Register AT91_REG Reserved1[1]; // AT91_REG US_IF; // IRDA_FILTER Register AT91_REG Reserved2[44]; // AT91_REG US_RPR; // Receive Pointer Register AT91_REG US_RCR; // Receive Counter Register AT91_REG US_TPR; // Transmit Pointer Register AT91_REG US_TCR; // Transmit Counter Register AT91_REG US_RNPR; // Receive Next Pointer Register AT91_REG US_RNCR; // Receive Next Counter Register AT91_REG US_TNPR; // Transmit Next Pointer Register AT91_REG US_TNCR; // Transmit Next Counter Register AT91_REG US_PTCR; // PDC Transfer Control Register AT91_REG US_PTSR; // PDC Transfer Status Register } AT91S_USART, AT91PS_USART; // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input // ************************************************************************** // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface // *************************************************************************** typedef struct _AT91S_SSC { AT91_REG SSC_CR; // Control Register AT91_REG SSC_CMR; // Clock Mode Register AT91_REG Reserved0[2]; // AT91_REG SSC_RCMR; // Receive Clock ModeRegister AT91_REG SSC_RFMR; // Receive Frame Mode Register AT91_REG SSC_TCMR; // Transmit Clock Mode Register AT91_REG SSC_TFMR; // Transmit Frame Mode Register AT91_REG SSC_RHR; // Receive Holding Register AT91_REG SSC_THR; // Transmit Holding Register AT91_REG Reserved1[2]; // AT91_REG SSC_RSHR; // Receive Sync Holding Register AT91_REG SSC_TSHR; // Transmit Sync Holding Register AT91_REG Reserved2[2]; // AT91_REG SSC_SR; // Status Register AT91_REG SSC_IER; // Interrupt Enable Register AT91_REG SSC_IDR; // Interrupt Disable Register AT91_REG SSC_IMR; // Interrupt Mask Register AT91_REG Reserved3[44]; // AT91_REG SSC_RPR; // Receive Pointer Register AT91_REG SSC_RCR; // Receive Counter Register AT91_REG SSC_TPR; // Transmit Pointer Register AT91_REG SSC_TCR; // Transmit Counter Register AT91_REG SSC_RNPR; // Receive Next Pointer Register AT91_REG SSC_RNCR; // Receive Next Counter Register AT91_REG SSC_TNPR; // Transmit Next Pointer Register AT91_REG SSC_TNCR; // Transmit Next Counter Register AT91_REG SSC_PTCR; // PDC Transfer Control Register AT91_REG SSC_PTSR; // PDC Transfer Status Register } AT91S_SSC, AT91PS_SSC; // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Two-wire Interface // *************************************************************************** typedef struct _AT91S_TWI { AT91_REG TWI_CR; // Control Register AT91_REG TWI_MMR; // Master Mode Register AT91_REG Reserved0[1]; // AT91_REG TWI_IADR; // Internal Address Register AT91_REG TWI_CWGR; // Clock Waveform Generator Register AT91_REG Reserved1[3]; // AT91_REG TWI_SR; // Status Register AT91_REG TWI_IER; // Interrupt Enable Register AT91_REG TWI_IDR; // Interrupt Disable Register AT91_REG TWI_IMR; // Interrupt Mask Register AT91_REG TWI_RHR; // Receive Holding Register AT91_REG TWI_THR; // Transmit Holding Register } AT91S_TWI, AT91PS_TWI; // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR PWMC Channel Interface // *************************************************************************** typedef struct _AT91S_PWMC_CH { AT91_REG PWMC_CMR; // Channel Mode Register AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register AT91_REG PWMC_CPRDR; // Channel Period Register AT91_REG PWMC_CCNTR; // Channel Counter Register AT91_REG PWMC_CUPDR; // Channel Update Register AT91_REG PWMC_Reserved[3]; // Reserved } AT91S_PWMC_CH, AT91PS_PWMC_CH; // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- #define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx #define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) #define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) #define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) #define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment #define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity #define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- #define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- #define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- #define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- #define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update // ************************************************************************** // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface // *************************************************************************** typedef struct _AT91S_PWMC { AT91_REG PWMC_MR; // PWMC Mode Register AT91_REG PWMC_ENA; // PWMC Enable Register AT91_REG PWMC_DIS; // PWMC Disable Register AT91_REG PWMC_SR; // PWMC Status Register AT91_REG PWMC_IER; // PWMC Interrupt Enable Register AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register AT91_REG PWMC_ISR; // PWMC Interrupt Status Register AT91_REG Reserved0[55]; // AT91_REG PWMC_VR; // PWMC Version Register AT91_REG Reserved1[64]; // AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel } AT91S_PWMC, AT91PS_PWMC; // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- #define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. #define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A #define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) #define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. #define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B #define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- #define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 #define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 #define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 #define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR USB Device Interface // *************************************************************************** typedef struct _AT91S_UDP { AT91_REG UDP_NUM; // Frame Number Register AT91_REG UDP_GLBSTATE; // Global State Register AT91_REG UDP_FADDR; // Function Address Register AT91_REG Reserved0[1]; // AT91_REG UDP_IER; // Interrupt Enable Register AT91_REG UDP_IDR; // Interrupt Disable Register AT91_REG UDP_IMR; // Interrupt Mask Register AT91_REG UDP_ISR; // Interrupt Status Register AT91_REG UDP_ICR; // Interrupt Clear Register AT91_REG Reserved1[1]; // AT91_REG UDP_RSTEP; // Reset Endpoint Register AT91_REG Reserved2[1]; // AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register AT91_REG Reserved3[2]; // AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register AT91_REG Reserved4[3]; // AT91_REG UDP_TXVC; // Transceiver Control Register } AT91S_UDP, AT91PS_UDP; // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt #define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt #define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 #define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) #define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON // ************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface // *************************************************************************** typedef struct _AT91S_TC { AT91_REG TC_CCR; // Channel Control Register AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) AT91_REG Reserved0[2]; // AT91_REG TC_CV; // Counter Value AT91_REG TC_RA; // Register A AT91_REG TC_RB; // Register B AT91_REG TC_RC; // Register C AT91_REG TC_SR; // Status Register AT91_REG TC_IER; // Interrupt Enable Register AT91_REG TC_IDR; // Interrupt Disable Register AT91_REG TC_IMR; // Interrupt Mask Register } AT91S_TC, AT91PS_TC; // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Interface // *************************************************************************** typedef struct _AT91S_TCB { AT91S_TC TCB_TC0; // TC Channel 0 AT91_REG Reserved0[4]; // AT91S_TC TCB_TC1; // TC Channel 1 AT91_REG Reserved1[4]; // AT91S_TC TCB_TC2; // TC Channel 2 AT91_REG Reserved2[4]; // AT91_REG TCB_BCR; // TC Block Control Register AT91_REG TCB_BMR; // TC Block Mode Register } AT91S_TCB, AT91PS_TCB; // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 // ************************************************************************** // SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface // *************************************************************************** typedef struct _AT91S_CAN_MB { AT91_REG CAN_MB_MMR; // MailBox Mode Register AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register AT91_REG CAN_MB_MID; // MailBox ID Register AT91_REG CAN_MB_MFID; // MailBox Family ID Register AT91_REG CAN_MB_MSR; // MailBox Status Register AT91_REG CAN_MB_MDL; // MailBox Data Low Register AT91_REG CAN_MB_MDH; // MailBox Data High Register AT91_REG CAN_MB_MCR; // MailBox Control Register } AT91S_CAN_MB, AT91PS_CAN_MB; // -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- #define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark #define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority #define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type #define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) #define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) #define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) #define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) #define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) #define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) // -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- #define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode #define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode #define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version // -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- // -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- // -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- #define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value #define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code #define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request #define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort #define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready #define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored // -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- // -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- // -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- #define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox #define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command // ************************************************************************** // SOFTWARE API DEFINITION FOR Control Area Network Interface // *************************************************************************** typedef struct _AT91S_CAN { AT91_REG CAN_MR; // Mode Register AT91_REG CAN_IER; // Interrupt Enable Register AT91_REG CAN_IDR; // Interrupt Disable Register AT91_REG CAN_IMR; // Interrupt Mask Register AT91_REG CAN_SR; // Status Register AT91_REG CAN_BR; // Baudrate Register AT91_REG CAN_TIM; // Timer Register AT91_REG CAN_TIMESTP; // Time Stamp Register AT91_REG CAN_ECR; // Error Counter Register AT91_REG CAN_TCR; // Transfer Command Register AT91_REG CAN_ACR; // Abort Command Register AT91_REG Reserved0[52]; // AT91_REG CAN_VR; // Version Register AT91_REG Reserved1[64]; // AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 } AT91S_CAN, AT91PS_CAN; // -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- #define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable #define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode #define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode #define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame #define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame #define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode #define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze #define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat // -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- #define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag #define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag #define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag #define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag #define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag #define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag #define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag #define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag #define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag #define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag #define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag #define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag #define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag #define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag #define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag #define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag #define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag #define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag #define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag #define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag #define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag #define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag #define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag #define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag #define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error #define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error #define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error #define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error #define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error // -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- // -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- // -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- #define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy #define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy #define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy // -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- #define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment #define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment #define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment #define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment #define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler #define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode // -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- #define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field // -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- // -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- #define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter #define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter // -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- #define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field // -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 // *************************************************************************** typedef struct _AT91S_EMAC { AT91_REG EMAC_NCR; // Network Control Register AT91_REG EMAC_NCFGR; // Network Configuration Register AT91_REG EMAC_NSR; // Network Status Register AT91_REG Reserved0[2]; // AT91_REG EMAC_TSR; // Transmit Status Register AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer AT91_REG EMAC_RSR; // Receive Status Register AT91_REG EMAC_ISR; // Interrupt Status Register AT91_REG EMAC_IER; // Interrupt Enable Register AT91_REG EMAC_IDR; // Interrupt Disable Register AT91_REG EMAC_IMR; // Interrupt Mask Register AT91_REG EMAC_MAN; // PHY Maintenance Register AT91_REG EMAC_PTR; // Pause Time Register AT91_REG EMAC_PFR; // Pause Frames received Register AT91_REG EMAC_FTO; // Frames Transmitted OK Register AT91_REG EMAC_SCF; // Single Collision Frame Register AT91_REG EMAC_MCF; // Multiple Collision Frame Register AT91_REG EMAC_FRO; // Frames Received OK Register AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register AT91_REG EMAC_ALE; // Alignment Error Register AT91_REG EMAC_DTF; // Deferred Transmission Frame Register AT91_REG EMAC_LCOL; // Late Collision Register AT91_REG EMAC_ECOL; // Excessive Collision Register AT91_REG EMAC_TUND; // Transmit Underrun Error Register AT91_REG EMAC_CSE; // Carrier Sense Error Register AT91_REG EMAC_RRE; // Receive Ressource Error Register AT91_REG EMAC_ROV; // Receive Overrun Errors Register AT91_REG EMAC_RSE; // Receive Symbol Errors Register AT91_REG EMAC_ELE; // Excessive Length Errors Register AT91_REG EMAC_RJA; // Receive Jabbers Register AT91_REG EMAC_USF; // Undersize Frames Register AT91_REG EMAC_STE; // SQE Test Error Register AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register AT91_REG EMAC_TPF; // Transmitted Pause Frames Register AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] AT91_REG EMAC_HRT; // Hash Address Top[63:32] AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes AT91_REG EMAC_TID; // Type ID Checking Register AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register AT91_REG EMAC_USRIO; // USER Input/Output Register AT91_REG EMAC_WOL; // Wake On LAN Register AT91_REG Reserved1[13]; // AT91_REG EMAC_REV; // Revision Register } AT91S_EMAC, AT91PS_EMAC; // -------- EMAC_NCR : (EMAC Offset: 0x0) -------- #define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. #define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. #define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. #define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. #define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. #define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. #define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. #define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. #define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. #define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. #define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. #define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame #define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- #define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. #define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. #define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. #define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. #define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable #define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. #define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. #define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. #define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) #define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 #define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 #define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 #define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 #define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) #define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) #define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) #define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer #define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer #define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer #define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer #define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable #define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS #define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) #define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- #define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- #define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) #define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go #define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame #define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) #define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- #define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- #define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) #define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) #define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) #define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) #define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) #define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) #define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) #define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) #define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) #define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) #define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) #define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) #define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) #define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) #define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) #define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- #define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- #define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address #define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable #define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable #define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- #define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) #define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) // ************************************************************************** // SOFTWARE API DEFINITION FOR Analog to Digital Convertor // *************************************************************************** typedef struct _AT91S_ADC { AT91_REG ADC_CR; // ADC Control Register AT91_REG ADC_MR; // ADC Mode Register AT91_REG Reserved0[2]; // AT91_REG ADC_CHER; // ADC Channel Enable Register AT91_REG ADC_CHDR; // ADC Channel Disable Register AT91_REG ADC_CHSR; // ADC Channel Status Register AT91_REG ADC_SR; // ADC Status Register AT91_REG ADC_LCDR; // ADC Last Converted Data Register AT91_REG ADC_IER; // ADC Interrupt Enable Register AT91_REG ADC_IDR; // ADC Interrupt Disable Register AT91_REG ADC_IMR; // ADC Interrupt Mask Register AT91_REG ADC_CDR0; // ADC Channel Data Register 0 AT91_REG ADC_CDR1; // ADC Channel Data Register 1 AT91_REG ADC_CDR2; // ADC Channel Data Register 2 AT91_REG ADC_CDR3; // ADC Channel Data Register 3 AT91_REG ADC_CDR4; // ADC Channel Data Register 4 AT91_REG ADC_CDR5; // ADC Channel Data Register 5 AT91_REG ADC_CDR6; // ADC Channel Data Register 6 AT91_REG ADC_CDR7; // ADC Channel Data Register 7 AT91_REG Reserved1[44]; // AT91_REG ADC_RPR; // Receive Pointer Register AT91_REG ADC_RCR; // Receive Counter Register AT91_REG ADC_TPR; // Transmit Pointer Register AT91_REG ADC_TCR; // Transmit Counter Register AT91_REG ADC_RNPR; // Receive Next Pointer Register AT91_REG ADC_RNCR; // Receive Next Counter Register AT91_REG ADC_TNPR; // Transmit Next Pointer Register AT91_REG ADC_TNCR; // Transmit Next Counter Register AT91_REG ADC_PTCR; // PDC Transfer Control Register AT91_REG ADC_PTSR; // PDC Transfer Status Register } AT91S_ADC, AT91PS_ADC; // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- #define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset #define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- #define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable #define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software #define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. #define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection #define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 #define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 #define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 #define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 #define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 #define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 #define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger #define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. #define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution #define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution #define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode #define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode #define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode #define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection #define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time #define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- #define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 #define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 #define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 #define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 #define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 #define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 #define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 #define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- #define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion #define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion #define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion #define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion #define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion #define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion #define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion #define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion #define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error #define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error #define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error #define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error #define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error #define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error #define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error #define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error #define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready #define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun #define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer #define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- #define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- #define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- // ************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Encryption Standard // *************************************************************************** typedef struct _AT91S_AES { AT91_REG AES_CR; // Control Register AT91_REG AES_MR; // Mode Register AT91_REG Reserved0[2]; // AT91_REG AES_IER; // Interrupt Enable Register AT91_REG AES_IDR; // Interrupt Disable Register AT91_REG AES_IMR; // Interrupt Mask Register AT91_REG AES_ISR; // Interrupt Status Register AT91_REG AES_KEYWxR[4]; // Key Word x Register AT91_REG Reserved1[4]; // AT91_REG AES_IDATAxR[4]; // Input Data x Register AT91_REG AES_ODATAxR[4]; // Output Data x Register AT91_REG AES_IVxR[4]; // Initialization Vector x Register AT91_REG Reserved2[35]; // AT91_REG AES_VR; // AES Version Register AT91_REG AES_RPR; // Receive Pointer Register AT91_REG AES_RCR; // Receive Counter Register AT91_REG AES_TPR; // Transmit Pointer Register AT91_REG AES_TCR; // Transmit Counter Register AT91_REG AES_RNPR; // Receive Next Pointer Register AT91_REG AES_RNCR; // Receive Next Counter Register AT91_REG AES_TNPR; // Transmit Next Pointer Register AT91_REG AES_TNCR; // Transmit Next Counter Register AT91_REG AES_PTCR; // PDC Transfer Control Register AT91_REG AES_PTSR; // PDC Transfer Status Register } AT91S_AES, AT91PS_AES; // -------- AES_CR : (AES Offset: 0x0) Control Register -------- #define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing #define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset #define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading // -------- AES_MR : (AES Offset: 0x4) Mode Register -------- #define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode #define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay #define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode #define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. #define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). #define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). #define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode #define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. #define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. #define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. #define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. #define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. #define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode #define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size #define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. #define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. #define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. #define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. #define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. #define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key #define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type #define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. #define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. #define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. #define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. #define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. // -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- #define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY #define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End #define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End #define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full #define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty #define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection // -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- // -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- // -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- #define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status #define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. #define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. #define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. #define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. #define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. #define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. // ************************************************************************** // SOFTWARE API DEFINITION FOR Triple Data Encryption Standard // *************************************************************************** typedef struct _AT91S_TDES { AT91_REG TDES_CR; // Control Register AT91_REG TDES_MR; // Mode Register AT91_REG Reserved0[2]; // AT91_REG TDES_IER; // Interrupt Enable Register AT91_REG TDES_IDR; // Interrupt Disable Register AT91_REG TDES_IMR; // Interrupt Mask Register AT91_REG TDES_ISR; // Interrupt Status Register AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register AT91_REG Reserved1[2]; // AT91_REG TDES_IDATAxR[2]; // Input Data x Register AT91_REG Reserved2[2]; // AT91_REG TDES_ODATAxR[2]; // Output Data x Register AT91_REG Reserved3[2]; // AT91_REG TDES_IVxR[2]; // Initialization Vector x Register AT91_REG Reserved4[37]; // AT91_REG TDES_VR; // TDES Version Register AT91_REG TDES_RPR; // Receive Pointer Register AT91_REG TDES_RCR; // Receive Counter Register AT91_REG TDES_TPR; // Transmit Pointer Register AT91_REG TDES_TCR; // Transmit Counter Register AT91_REG TDES_RNPR; // Receive Next Pointer Register AT91_REG TDES_RNCR; // Receive Next Counter Register AT91_REG TDES_TNPR; // Transmit Next Pointer Register AT91_REG TDES_TNCR; // Transmit Next Counter Register AT91_REG TDES_PTCR; // PDC Transfer Control Register AT91_REG TDES_PTSR; // PDC Transfer Status Register } AT91S_TDES, AT91PS_TDES; // -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- #define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing #define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset // -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- #define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode #define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode #define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode #define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode #define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. #define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). #define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). #define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode #define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. #define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. #define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. #define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. #define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode #define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size #define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. #define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. #define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. #define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. // -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- #define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY #define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End #define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End #define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full #define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty #define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection // -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- // -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- // -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- #define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status #define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. #define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. #define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. #define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. // ************************************************************************** // REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 // *************************************************************************** // ========== Register definition for SYS peripheral ========== // ========== Register definition for AIC peripheral ========== #define AT91C_AIC_IVR ((AT91_REG ) 0xFFFFF100) // (AIC) IRQ Vector Register #define AT91C_AIC_SMR ((AT91_REG ) 0xFFFFF000) // (AIC) Source Mode Register #define AT91C_AIC_FVR ((AT91_REG ) 0xFFFFF104) // (AIC) FIQ Vector Register #define AT91C_AIC_DCR ((AT91_REG ) 0xFFFFF138) // (AIC) Debug Control Register (Protect) #define AT91C_AIC_EOICR ((AT91_REG ) 0xFFFFF130) // (AIC) End of Interrupt Command Register #define AT91C_AIC_SVR ((AT91_REG ) 0xFFFFF080) // (AIC) Source Vector Register #define AT91C_AIC_FFSR ((AT91_REG ) 0xFFFFF148) // (AIC) Fast Forcing Status Register #define AT91C_AIC_ICCR ((AT91_REG ) 0xFFFFF128) // (AIC) Interrupt Clear Command Register #define AT91C_AIC_ISR ((AT91_REG ) 0xFFFFF108) // (AIC) Interrupt Status Register #define AT91C_AIC_IMR ((AT91_REG ) 0xFFFFF110) // (AIC) Interrupt Mask Register #define AT91C_AIC_IPR ((AT91_REG ) 0xFFFFF10C) // (AIC) Interrupt Pending Register #define AT91C_AIC_FFER ((AT91_REG ) 0xFFFFF140) // (AIC) Fast Forcing Enable Register #define AT91C_AIC_IECR ((AT91_REG ) 0xFFFFF120) // (AIC) Interrupt Enable Command Register #define AT91C_AIC_ISCR ((AT91_REG ) 0xFFFFF12C) // (AIC) Interrupt Set Command Register #define AT91C_AIC_FFDR ((AT91_REG ) 0xFFFFF144) // (AIC) Fast Forcing Disable Register #define AT91C_AIC_CISR ((AT91_REG ) 0xFFFFF114) // (AIC) Core Interrupt Status Register #define AT91C_AIC_IDCR ((AT91_REG ) 0xFFFFF124) // (AIC) Interrupt Disable Command Register #define AT91C_AIC_SPU ((AT91_REG ) 0xFFFFF134) // (AIC) Spurious Vector Register // ========== Register definition for PDC_DBGU peripheral ========== #define AT91C_DBGU_TCR ((AT91_REG ) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register #define AT91C_DBGU_RNPR ((AT91_REG ) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register #define AT91C_DBGU_TNPR ((AT91_REG ) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register #define AT91C_DBGU_TPR ((AT91_REG ) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register #define AT91C_DBGU_RPR ((AT91_REG ) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register #define AT91C_DBGU_RCR ((AT91_REG ) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register #define AT91C_DBGU_RNCR ((AT91_REG ) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register #define AT91C_DBGU_PTCR ((AT91_REG ) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register #define AT91C_DBGU_PTSR ((AT91_REG ) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register #define AT91C_DBGU_TNCR ((AT91_REG ) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register // ========== Register definition for DBGU peripheral ========== #define AT91C_DBGU_EXID ((AT91_REG ) 0xFFFFF244) // (DBGU) Chip ID Extension Register #define AT91C_DBGU_BRGR ((AT91_REG ) 0xFFFFF220) // (DBGU) Baud Rate Generator Register #define AT91C_DBGU_IDR ((AT91_REG ) 0xFFFFF20C) // (DBGU) Interrupt Disable Register #define AT91C_DBGU_CSR ((AT91_REG ) 0xFFFFF214) // (DBGU) Channel Status Register #define AT91C_DBGU_CIDR ((AT91_REG ) 0xFFFFF240) // (DBGU) Chip ID Register #define AT91C_DBGU_MR ((AT91_REG ) 0xFFFFF204) // (DBGU) Mode Register #define AT91C_DBGU_IMR ((AT91_REG ) 0xFFFFF210) // (DBGU) Interrupt Mask Register #define AT91C_DBGU_CR ((AT91_REG ) 0xFFFFF200) // (DBGU) Control Register #define AT91C_DBGU_FNTR ((AT91_REG ) 0xFFFFF248) // (DBGU) Force NTRST Register #define AT91C_DBGU_THR ((AT91_REG ) 0xFFFFF21C) // (DBGU) Transmitter Holding Register #define AT91C_DBGU_RHR ((AT91_REG ) 0xFFFFF218) // (DBGU) Receiver Holding Register #define AT91C_DBGU_IER ((AT91_REG ) 0xFFFFF208) // (DBGU) Interrupt Enable Register // ========== Register definition for PIOA peripheral ========== #define AT91C_PIOA_ODR ((AT91_REG ) 0xFFFFF414) // (PIOA) Output Disable Registerr #define AT91C_PIOA_SODR ((AT91_REG ) 0xFFFFF430) // (PIOA) Set Output Data Register #define AT91C_PIOA_ISR ((AT91_REG ) 0xFFFFF44C) // (PIOA) Interrupt Status Register #define AT91C_PIOA_ABSR ((AT91_REG ) 0xFFFFF478) // (PIOA) AB Select Status Register #define AT91C_PIOA_IER ((AT91_REG ) 0xFFFFF440) // (PIOA) Interrupt Enable Register #define AT91C_PIOA_PPUDR ((AT91_REG ) 0xFFFFF460) // (PIOA) Pull-up Disable Register #define AT91C_PIOA_IMR ((AT91_REG ) 0xFFFFF448) // (PIOA) Interrupt Mask Register #define AT91C_PIOA_PER ((AT91_REG ) 0xFFFFF400) // (PIOA) PIO Enable Register #define AT91C_PIOA_IFDR ((AT91_REG ) 0xFFFFF424) // (PIOA) Input Filter Disable Register #define AT91C_PIOA_OWDR ((AT91_REG ) 0xFFFFF4A4) // (PIOA) Output Write Disable Register #define AT91C_PIOA_MDSR ((AT91_REG ) 0xFFFFF458) // (PIOA) Multi-driver Status Register #define AT91C_PIOA_IDR ((AT91_REG ) 0xFFFFF444) // (PIOA) Interrupt Disable Register #define AT91C_PIOA_ODSR ((AT91_REG ) 0xFFFFF438) // (PIOA) Output Data Status Register #define AT91C_PIOA_PPUSR ((AT91_REG ) 0xFFFFF468) // (PIOA) Pull-up Status Register #define AT91C_PIOA_OWSR ((AT91_REG ) 0xFFFFF4A8) // (PIOA) Output Write Status Register #define AT91C_PIOA_BSR ((AT91_REG ) 0xFFFFF474) // (PIOA) Select B Register #define AT91C_PIOA_OWER ((AT91_REG ) 0xFFFFF4A0) // (PIOA) Output Write Enable Register #define AT91C_PIOA_IFER ((AT91_REG ) 0xFFFFF420) // (PIOA) Input Filter Enable Register #define AT91C_PIOA_PDSR ((AT91_REG ) 0xFFFFF43C) // (PIOA) Pin Data Status Register #define AT91C_PIOA_PPUER ((AT91_REG ) 0xFFFFF464) // (PIOA) Pull-up Enable Register #define AT91C_PIOA_OSR ((AT91_REG ) 0xFFFFF418) // (PIOA) Output Status Register #define AT91C_PIOA_ASR ((AT91_REG ) 0xFFFFF470) // (PIOA) Select A Register #define AT91C_PIOA_MDDR ((AT91_REG ) 0xFFFFF454) // (PIOA) Multi-driver Disable Register #define AT91C_PIOA_CODR ((AT91_REG ) 0xFFFFF434) // (PIOA) Clear Output Data Register #define AT91C_PIOA_MDER ((AT91_REG ) 0xFFFFF450) // (PIOA) Multi-driver Enable Register #define AT91C_PIOA_PDR ((AT91_REG ) 0xFFFFF404) // (PIOA) PIO Disable Register #define AT91C_PIOA_IFSR ((AT91_REG ) 0xFFFFF428) // (PIOA) Input Filter Status Register #define AT91C_PIOA_OER ((AT91_REG ) 0xFFFFF410) // (PIOA) Output Enable Register #define AT91C_PIOA_PSR ((AT91_REG ) 0xFFFFF408) // (PIOA) PIO Status Register // ========== Register definition for PIOB peripheral ========== #define AT91C_PIOB_OWDR ((AT91_REG ) 0xFFFFF6A4) // (PIOB) Output Write Disable Register #define AT91C_PIOB_MDER ((AT91_REG ) 0xFFFFF650) // (PIOB) Multi-driver Enable Register #define AT91C_PIOB_PPUSR ((AT91_REG ) 0xFFFFF668) // (PIOB) Pull-up Status Register #define AT91C_PIOB_IMR ((AT91_REG ) 0xFFFFF648) // (PIOB) Interrupt Mask Register #define AT91C_PIOB_ASR ((AT91_REG ) 0xFFFFF670) // (PIOB) Select A Register #define AT91C_PIOB_PPUDR ((AT91_REG ) 0xFFFFF660) // (PIOB) Pull-up Disable Register #define AT91C_PIOB_PSR ((AT91_REG ) 0xFFFFF608) // (PIOB) PIO Status Register #define AT91C_PIOB_IER ((AT91_REG ) 0xFFFFF640) // (PIOB) Interrupt Enable Register #define AT91C_PIOB_CODR ((AT91_REG ) 0xFFFFF634) // (PIOB) Clear Output Data Register #define AT91C_PIOB_OWER ((AT91_REG ) 0xFFFFF6A0) // (PIOB) Output Write Enable Register #define AT91C_PIOB_ABSR ((AT91_REG ) 0xFFFFF678) // (PIOB) AB Select Status Register #define AT91C_PIOB_IFDR ((AT91_REG ) 0xFFFFF624) // (PIOB) Input Filter Disable Register #define AT91C_PIOB_PDSR ((AT91_REG ) 0xFFFFF63C) // (PIOB) Pin Data Status Register #define AT91C_PIOB_IDR ((AT91_REG ) 0xFFFFF644) // (PIOB) Interrupt Disable Register #define AT91C_PIOB_OWSR ((AT91_REG ) 0xFFFFF6A8) // (PIOB) Output Write Status Register #define AT91C_PIOB_PDR ((AT91_REG ) 0xFFFFF604) // (PIOB) PIO Disable Register #define AT91C_PIOB_ODR ((AT91_REG ) 0xFFFFF614) // (PIOB) Output Disable Registerr #define AT91C_PIOB_IFSR ((AT91_REG ) 0xFFFFF628) // (PIOB) Input Filter Status Register #define AT91C_PIOB_PPUER ((AT91_REG ) 0xFFFFF664) // (PIOB) Pull-up Enable Register #define AT91C_PIOB_SODR ((AT91_REG ) 0xFFFFF630) // (PIOB) Set Output Data Register #define AT91C_PIOB_ISR ((AT91_REG ) 0xFFFFF64C) // (PIOB) Interrupt Status Register #define AT91C_PIOB_ODSR ((AT91_REG ) 0xFFFFF638) // (PIOB) Output Data Status Register #define AT91C_PIOB_OSR ((AT91_REG ) 0xFFFFF618) // (PIOB) Output Status Register #define AT91C_PIOB_MDSR ((AT91_REG ) 0xFFFFF658) // (PIOB) Multi-driver Status Register #define AT91C_PIOB_IFER ((AT91_REG ) 0xFFFFF620) // (PIOB) Input Filter Enable Register #define AT91C_PIOB_BSR ((AT91_REG ) 0xFFFFF674) // (PIOB) Select B Register #define AT91C_PIOB_MDDR ((AT91_REG ) 0xFFFFF654) // (PIOB) Multi-driver Disable Register #define AT91C_PIOB_OER ((AT91_REG ) 0xFFFFF610) // (PIOB) Output Enable Register #define AT91C_PIOB_PER ((AT91_REG ) 0xFFFFF600) // (PIOB) PIO Enable Register // ========== Register definition for CKGR peripheral ========== #define AT91C_CKGR_MOR ((AT91_REG ) 0xFFFFFC20) // (CKGR) Main Oscillator Register #define AT91C_CKGR_PLLR ((AT91_REG ) 0xFFFFFC2C) // (CKGR) PLL Register #define AT91C_CKGR_MCFR ((AT91_REG ) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register // ========== Register definition for PMC peripheral ========== #define AT91C_PMC_IDR ((AT91_REG ) 0xFFFFFC64) // (PMC) Interrupt Disable Register #define AT91C_PMC_MOR ((AT91_REG ) 0xFFFFFC20) // (PMC) Main Oscillator Register #define AT91C_PMC_PLLR ((AT91_REG ) 0xFFFFFC2C) // (PMC) PLL Register #define AT91C_PMC_PCER ((AT91_REG ) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register #define AT91C_PMC_PCKR ((AT91_REG ) 0xFFFFFC40) // (PMC) Programmable Clock Register #define AT91C_PMC_MCKR ((AT91_REG ) 0xFFFFFC30) // (PMC) Master Clock Register #define AT91C_PMC_SCDR ((AT91_REG ) 0xFFFFFC04) // (PMC) System Clock Disable Register #define AT91C_PMC_PCDR ((AT91_REG ) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register #define AT91C_PMC_SCSR ((AT91_REG ) 0xFFFFFC08) // (PMC) System Clock Status Register #define AT91C_PMC_PCSR ((AT91_REG ) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register #define AT91C_PMC_MCFR ((AT91_REG ) 0xFFFFFC24) // (PMC) Main Clock Frequency Register #define AT91C_PMC_SCER ((AT91_REG ) 0xFFFFFC00) // (PMC) System Clock Enable Register #define AT91C_PMC_IMR ((AT91_REG ) 0xFFFFFC6C) // (PMC) Interrupt Mask Register #define AT91C_PMC_IER ((AT91_REG ) 0xFFFFFC60) // (PMC) Interrupt Enable Register #define AT91C_PMC_SR ((AT91_REG ) 0xFFFFFC68) // (PMC) Status Register // ========== Register definition for RSTC peripheral ========== #define AT91C_RSTC_RCR ((AT91_REG ) 0xFFFFFD00) // (RSTC) Reset Control Register #define AT91C_RSTC_RMR ((AT91_REG ) 0xFFFFFD08) // (RSTC) Reset Mode Register #define AT91C_RSTC_RSR ((AT91_REG ) 0xFFFFFD04) // (RSTC) Reset Status Register // ========== Register definition for RTTC peripheral ========== #define AT91C_RTTC_RTSR ((AT91_REG ) 0xFFFFFD2C) // (RTTC) Real-time Status Register #define AT91C_RTTC_RTMR ((AT91_REG ) 0xFFFFFD20) // (RTTC) Real-time Mode Register #define AT91C_RTTC_RTVR ((AT91_REG ) 0xFFFFFD28) // (RTTC) Real-time Value Register #define AT91C_RTTC_RTAR ((AT91_REG ) 0xFFFFFD24) // (RTTC) Real-time Alarm Register // ========== Register definition for PITC peripheral ========== #define AT91C_PITC_PIVR ((AT91_REG ) 0xFFFFFD38) // (PITC) Period Interval Value Register #define AT91C_PITC_PISR ((AT91_REG ) 0xFFFFFD34) // (PITC) Period Interval Status Register #define AT91C_PITC_PIIR ((AT91_REG ) 0xFFFFFD3C) // (PITC) Period Interval Image Register #define AT91C_PITC_PIMR ((AT91_REG ) 0xFFFFFD30) // (PITC) Period Interval Mode Register // ========== Register definition for WDTC peripheral ========== #define AT91C_WDTC_WDCR ((AT91_REG ) 0xFFFFFD40) // (WDTC) Watchdog Control Register #define AT91C_WDTC_WDSR ((AT91_REG ) 0xFFFFFD48) // (WDTC) Watchdog Status Register #define AT91C_WDTC_WDMR ((AT91_REG ) 0xFFFFFD44) // (WDTC) Watchdog Mode Register // ========== Register definition for VREG peripheral ========== #define AT91C_VREG_MR ((AT91_REG ) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register // ========== Register definition for MC peripheral ========== #define AT91C_MC_ASR ((AT91_REG ) 0xFFFFFF04) // (MC) MC Abort Status Register #define AT91C_MC_RCR ((AT91_REG ) 0xFFFFFF00) // (MC) MC Remap Control Register #define AT91C_MC_FCR ((AT91_REG ) 0xFFFFFF64) // (MC) MC Flash Command Register #define AT91C_MC_AASR ((AT91_REG ) 0xFFFFFF08) // (MC) MC Abort Address Status Register #define AT91C_MC_FSR ((AT91_REG ) 0xFFFFFF68) // (MC) MC Flash Status Register #define AT91C_MC_FMR ((AT91_REG ) 0xFFFFFF60) // (MC) MC Flash Mode Register // ========== Register definition for PDC_SPI1 peripheral ========== #define AT91C_SPI1_PTCR ((AT91_REG ) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register #define AT91C_SPI1_RPR ((AT91_REG ) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register #define AT91C_SPI1_TNCR ((AT91_REG ) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register #define AT91C_SPI1_TPR ((AT91_REG ) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register #define AT91C_SPI1_TNPR ((AT91_REG ) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register #define AT91C_SPI1_TCR ((AT91_REG ) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register #define AT91C_SPI1_RCR ((AT91_REG ) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register #define AT91C_SPI1_RNPR ((AT91_REG ) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register #define AT91C_SPI1_RNCR ((AT91_REG ) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register #define AT91C_SPI1_PTSR ((AT91_REG ) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register // ========== Register definition for SPI1 peripheral ========== #define AT91C_SPI1_IMR ((AT91_REG ) 0xFFFE401C) // (SPI1) Interrupt Mask Register #define AT91C_SPI1_IER ((AT91_REG ) 0xFFFE4014) // (SPI1) Interrupt Enable Register #define AT91C_SPI1_MR ((AT91_REG ) 0xFFFE4004) // (SPI1) Mode Register #define AT91C_SPI1_RDR ((AT91_REG ) 0xFFFE4008) // (SPI1) Receive Data Register #define AT91C_SPI1_IDR ((AT91_REG ) 0xFFFE4018) // (SPI1) Interrupt Disable Register #define AT91C_SPI1_SR ((AT91_REG ) 0xFFFE4010) // (SPI1) Status Register #define AT91C_SPI1_TDR ((AT91_REG ) 0xFFFE400C) // (SPI1) Transmit Data Register #define AT91C_SPI1_CR ((AT91_REG ) 0xFFFE4000) // (SPI1) Control Register #define AT91C_SPI1_CSR ((AT91_REG ) 0xFFFE4030) // (SPI1) Chip Select Register // ========== Register definition for PDC_SPI0 peripheral ========== #define AT91C_SPI0_PTCR ((AT91_REG ) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register #define AT91C_SPI0_TPR ((AT91_REG ) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register #define AT91C_SPI0_TCR ((AT91_REG ) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register #define AT91C_SPI0_RCR ((AT91_REG ) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register #define AT91C_SPI0_PTSR ((AT91_REG ) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register #define AT91C_SPI0_RNPR ((AT91_REG ) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register #define AT91C_SPI0_RPR ((AT91_REG ) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register #define AT91C_SPI0_TNCR ((AT91_REG ) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register #define AT91C_SPI0_RNCR ((AT91_REG ) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register #define AT91C_SPI0_TNPR ((AT91_REG ) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register // ========== Register definition for SPI0 peripheral ========== #define AT91C_SPI0_IER ((AT91_REG ) 0xFFFE0014) // (SPI0) Interrupt Enable Register #define AT91C_SPI0_SR ((AT91_REG ) 0xFFFE0010) // (SPI0) Status Register #define AT91C_SPI0_IDR ((AT91_REG ) 0xFFFE0018) // (SPI0) Interrupt Disable Register #define AT91C_SPI0_CR ((AT91_REG ) 0xFFFE0000) // (SPI0) Control Register #define AT91C_SPI0_MR ((AT91_REG ) 0xFFFE0004) // (SPI0) Mode Register #define AT91C_SPI0_IMR ((AT91_REG ) 0xFFFE001C) // (SPI0) Interrupt Mask Register #define AT91C_SPI0_TDR ((AT91_REG ) 0xFFFE000C) // (SPI0) Transmit Data Register #define AT91C_SPI0_RDR ((AT91_REG ) 0xFFFE0008) // (SPI0) Receive Data Register #define AT91C_SPI0_CSR ((AT91_REG ) 0xFFFE0030) // (SPI0) Chip Select Register // ========== Register definition for PDC_US1 peripheral ========== #define AT91C_US1_RNCR ((AT91_REG ) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register #define AT91C_US1_PTCR ((AT91_REG ) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register #define AT91C_US1_TCR ((AT91_REG ) 0xFFFC410C) // (PDC_US1) Transmit Counter Register #define AT91C_US1_PTSR ((AT91_REG ) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register #define AT91C_US1_TNPR ((AT91_REG ) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register #define AT91C_US1_RCR ((AT91_REG ) 0xFFFC4104) // (PDC_US1) Receive Counter Register #define AT91C_US1_RNPR ((AT91_REG ) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register #define AT91C_US1_RPR ((AT91_REG ) 0xFFFC4100) // (PDC_US1) Receive Pointer Register #define AT91C_US1_TNCR ((AT91_REG ) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register #define AT91C_US1_TPR ((AT91_REG ) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register // ========== Register definition for US1 peripheral ========== #define AT91C_US1_IF ((AT91_REG ) 0xFFFC404C) // (US1) IRDA_FILTER Register #define AT91C_US1_NER ((AT91_REG ) 0xFFFC4044) // (US1) Nb Errors Register #define AT91C_US1_RTOR ((AT91_REG ) 0xFFFC4024) // (US1) Receiver Time-out Register #define AT91C_US1_CSR ((AT91_REG ) 0xFFFC4014) // (US1) Channel Status Register #define AT91C_US1_IDR ((AT91_REG ) 0xFFFC400C) // (US1) Interrupt Disable Register #define AT91C_US1_IER ((AT91_REG ) 0xFFFC4008) // (US1) Interrupt Enable Register #define AT91C_US1_THR ((AT91_REG ) 0xFFFC401C) // (US1) Transmitter Holding Register #define AT91C_US1_TTGR ((AT91_REG ) 0xFFFC4028) // (US1) Transmitter Time-guard Register #define AT91C_US1_RHR ((AT91_REG ) 0xFFFC4018) // (US1) Receiver Holding Register #define AT91C_US1_BRGR ((AT91_REG ) 0xFFFC4020) // (US1) Baud Rate Generator Register #define AT91C_US1_IMR ((AT91_REG ) 0xFFFC4010) // (US1) Interrupt Mask Register #define AT91C_US1_FIDI ((AT91_REG ) 0xFFFC4040) // (US1) FI_DI_Ratio Register #define AT91C_US1_CR ((AT91_REG ) 0xFFFC4000) // (US1) Control Register #define AT91C_US1_MR ((AT91_REG ) 0xFFFC4004) // (US1) Mode Register // ========== Register definition for PDC_US0 peripheral ========== #define AT91C_US0_TNPR ((AT91_REG ) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register #define AT91C_US0_RNPR ((AT91_REG ) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register #define AT91C_US0_TCR ((AT91_REG ) 0xFFFC010C) // (PDC_US0) Transmit Counter Register #define AT91C_US0_PTCR ((AT91_REG ) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register #define AT91C_US0_PTSR ((AT91_REG ) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register #define AT91C_US0_TNCR ((AT91_REG ) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register #define AT91C_US0_TPR ((AT91_REG ) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register #define AT91C_US0_RCR ((AT91_REG ) 0xFFFC0104) // (PDC_US0) Receive Counter Register #define AT91C_US0_RPR ((AT91_REG ) 0xFFFC0100) // (PDC_US0) Receive Pointer Register #define AT91C_US0_RNCR ((AT91_REG ) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register // ========== Register definition for US0 peripheral ========== #define AT91C_US0_BRGR ((AT91_REG ) 0xFFFC0020) // (US0) Baud Rate Generator Register #define AT91C_US0_NER ((AT91_REG ) 0xFFFC0044) // (US0) Nb Errors Register #define AT91C_US0_CR ((AT91_REG ) 0xFFFC0000) // (US0) Control Register #define AT91C_US0_IMR ((AT91_REG ) 0xFFFC0010) // (US0) Interrupt Mask Register #define AT91C_US0_FIDI ((AT91_REG ) 0xFFFC0040) // (US0) FI_DI_Ratio Register #define AT91C_US0_TTGR ((AT91_REG ) 0xFFFC0028) // (US0) Transmitter Time-guard Register #define AT91C_US0_MR ((AT91_REG ) 0xFFFC0004) // (US0) Mode Register #define AT91C_US0_RTOR ((AT91_REG ) 0xFFFC0024) // (US0) Receiver Time-out Register #define AT91C_US0_CSR ((AT91_REG ) 0xFFFC0014) // (US0) Channel Status Register #define AT91C_US0_RHR ((AT91_REG ) 0xFFFC0018) // (US0) Receiver Holding Register #define AT91C_US0_IDR ((AT91_REG ) 0xFFFC000C) // (US0) Interrupt Disable Register #define AT91C_US0_THR ((AT91_REG ) 0xFFFC001C) // (US0) Transmitter Holding Register #define AT91C_US0_IF ((AT91_REG ) 0xFFFC004C) // (US0) IRDA_FILTER Register #define AT91C_US0_IER ((AT91_REG ) 0xFFFC0008) // (US0) Interrupt Enable Register // ========== Register definition for PDC_SSC peripheral ========== #define AT91C_SSC_TNCR ((AT91_REG ) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register #define AT91C_SSC_RPR ((AT91_REG ) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register #define AT91C_SSC_RNCR ((AT91_REG ) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register #define AT91C_SSC_TPR ((AT91_REG ) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register #define AT91C_SSC_PTCR ((AT91_REG ) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register #define AT91C_SSC_TCR ((AT91_REG ) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register #define AT91C_SSC_RCR ((AT91_REG ) 0xFFFD4104) // (PDC_SSC) Receive Counter Register #define AT91C_SSC_RNPR ((AT91_REG ) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register #define AT91C_SSC_TNPR ((AT91_REG ) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register #define AT91C_SSC_PTSR ((AT91_REG ) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register // ========== Register definition for SSC peripheral ========== #define AT91C_SSC_RHR ((AT91_REG ) 0xFFFD4020) // (SSC) Receive Holding Register #define AT91C_SSC_RSHR ((AT91_REG ) 0xFFFD4030) // (SSC) Receive Sync Holding Register #define AT91C_SSC_TFMR ((AT91_REG ) 0xFFFD401C) // (SSC) Transmit Frame Mode Register #define AT91C_SSC_IDR ((AT91_REG ) 0xFFFD4048) // (SSC) Interrupt Disable Register #define AT91C_SSC_THR ((AT91_REG ) 0xFFFD4024) // (SSC) Transmit Holding Register #define AT91C_SSC_RCMR ((AT91_REG ) 0xFFFD4010) // (SSC) Receive Clock ModeRegister #define AT91C_SSC_IER ((AT91_REG ) 0xFFFD4044) // (SSC) Interrupt Enable Register #define AT91C_SSC_TSHR ((AT91_REG ) 0xFFFD4034) // (SSC) Transmit Sync Holding Register #define AT91C_SSC_SR ((AT91_REG ) 0xFFFD4040) // (SSC) Status Register #define AT91C_SSC_CMR ((AT91_REG ) 0xFFFD4004) // (SSC) Clock Mode Register #define AT91C_SSC_TCMR ((AT91_REG ) 0xFFFD4018) // (SSC) Transmit Clock Mode Register #define AT91C_SSC_CR ((AT91_REG ) 0xFFFD4000) // (SSC) Control Register #define AT91C_SSC_IMR ((AT91_REG ) 0xFFFD404C) // (SSC) Interrupt Mask Register #define AT91C_SSC_RFMR ((AT91_REG ) 0xFFFD4014) // (SSC) Receive Frame Mode Register // ========== Register definition for TWI peripheral ========== #define AT91C_TWI_IER ((AT91_REG ) 0xFFFB8024) // (TWI) Interrupt Enable Register #define AT91C_TWI_CR ((AT91_REG ) 0xFFFB8000) // (TWI) Control Register #define AT91C_TWI_SR ((AT91_REG ) 0xFFFB8020) // (TWI) Status Register #define AT91C_TWI_IMR ((AT91_REG ) 0xFFFB802C) // (TWI) Interrupt Mask Register #define AT91C_TWI_THR ((AT91_REG ) 0xFFFB8034) // (TWI) Transmit Holding Register #define AT91C_TWI_IDR ((AT91_REG ) 0xFFFB8028) // (TWI) Interrupt Disable Register #define AT91C_TWI_IADR ((AT91_REG ) 0xFFFB800C) // (TWI) Internal Address Register #define AT91C_TWI_MMR ((AT91_REG ) 0xFFFB8004) // (TWI) Master Mode Register #define AT91C_TWI_CWGR ((AT91_REG ) 0xFFFB8010) // (TWI) Clock Waveform Generator Register #define AT91C_TWI_RHR ((AT91_REG ) 0xFFFB8030) // (TWI) Receive Holding Register // ========== Register definition for PWMC_CH3 peripheral ========== #define AT91C_PWMC_CH3_CUPDR ((AT91_REG ) 0xFFFCC270) // (PWMC_CH3) Channel Update Register #define AT91C_PWMC_CH3_Reserved ((AT91_REG ) 0xFFFCC274) // (PWMC_CH3) Reserved #define AT91C_PWMC_CH3_CPRDR ((AT91_REG ) 0xFFFCC268) // (PWMC_CH3) Channel Period Register #define AT91C_PWMC_CH3_CDTYR ((AT91_REG ) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register #define AT91C_PWMC_CH3_CCNTR ((AT91_REG ) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register #define AT91C_PWMC_CH3_CMR ((AT91_REG ) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register // ========== Register definition for PWMC_CH2 peripheral ========== #define AT91C_PWMC_CH2_Reserved ((AT91_REG ) 0xFFFCC254) // (PWMC_CH2) Reserved #define AT91C_PWMC_CH2_CMR ((AT91_REG ) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register #define AT91C_PWMC_CH2_CCNTR ((AT91_REG ) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register #define AT91C_PWMC_CH2_CPRDR ((AT91_REG ) 0xFFFCC248) // (PWMC_CH2) Channel Period Register #define AT91C_PWMC_CH2_CUPDR ((AT91_REG ) 0xFFFCC250) // (PWMC_CH2) Channel Update Register #define AT91C_PWMC_CH2_CDTYR ((AT91_REG ) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register // ========== Register definition for PWMC_CH1 peripheral ========== #define AT91C_PWMC_CH1_Reserved ((AT91_REG ) 0xFFFCC234) // (PWMC_CH1) Reserved #define AT91C_PWMC_CH1_CUPDR ((AT91_REG ) 0xFFFCC230) // (PWMC_CH1) Channel Update Register #define AT91C_PWMC_CH1_CPRDR ((AT91_REG ) 0xFFFCC228) // (PWMC_CH1) Channel Period Register #define AT91C_PWMC_CH1_CCNTR ((AT91_REG ) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register #define AT91C_PWMC_CH1_CDTYR ((AT91_REG ) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register #define AT91C_PWMC_CH1_CMR ((AT91_REG ) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register // ========== Register definition for PWMC_CH0 peripheral ========== #define AT91C_PWMC_CH0_Reserved ((AT91_REG ) 0xFFFCC214) // (PWMC_CH0) Reserved #define AT91C_PWMC_CH0_CPRDR ((AT91_REG ) 0xFFFCC208) // (PWMC_CH0) Channel Period Register #define AT91C_PWMC_CH0_CDTYR ((AT91_REG ) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register #define AT91C_PWMC_CH0_CMR ((AT91_REG ) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register #define AT91C_PWMC_CH0_CUPDR ((AT91_REG ) 0xFFFCC210) // (PWMC_CH0) Channel Update Register #define AT91C_PWMC_CH0_CCNTR ((AT91_REG ) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register // ========== Register definition for PWMC peripheral ========== #define AT91C_PWMC_IDR ((AT91_REG ) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register #define AT91C_PWMC_DIS ((AT91_REG ) 0xFFFCC008) // (PWMC) PWMC Disable Register #define AT91C_PWMC_IER ((AT91_REG ) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register #define AT91C_PWMC_VR ((AT91_REG ) 0xFFFCC0FC) // (PWMC) PWMC Version Register #define AT91C_PWMC_ISR ((AT91_REG ) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register #define AT91C_PWMC_SR ((AT91_REG ) 0xFFFCC00C) // (PWMC) PWMC Status Register #define AT91C_PWMC_IMR ((AT91_REG ) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register #define AT91C_PWMC_MR ((AT91_REG ) 0xFFFCC000) // (PWMC) PWMC Mode Register #define AT91C_PWMC_ENA ((AT91_REG ) 0xFFFCC004) // (PWMC) PWMC Enable Register // ========== Register definition for UDP peripheral ========== #define AT91C_UDP_IMR ((AT91_REG ) 0xFFFB0018) // (UDP) Interrupt Mask Register #define AT91C_UDP_FADDR ((AT91_REG ) 0xFFFB0008) // (UDP) Function Address Register #define AT91C_UDP_NUM ((AT91_REG ) 0xFFFB0000) // (UDP) Frame Number Register #define AT91C_UDP_FDR ((AT91_REG ) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register #define AT91C_UDP_ISR ((AT91_REG ) 0xFFFB001C) // (UDP) Interrupt Status Register #define AT91C_UDP_CSR ((AT91_REG ) 0xFFFB0030) // (UDP) Endpoint Control and Status Register #define AT91C_UDP_IDR ((AT91_REG ) 0xFFFB0014) // (UDP) Interrupt Disable Register #define AT91C_UDP_ICR ((AT91_REG ) 0xFFFB0020) // (UDP) Interrupt Clear Register #define AT91C_UDP_RSTEP ((AT91_REG ) 0xFFFB0028) // (UDP) Reset Endpoint Register #define AT91C_UDP_TXVC ((AT91_REG ) 0xFFFB0074) // (UDP) Transceiver Control Register #define AT91C_UDP_GLBSTATE ((AT91_REG ) 0xFFFB0004) // (UDP) Global State Register #define AT91C_UDP_IER ((AT91_REG ) 0xFFFB0010) // (UDP) Interrupt Enable Register // ========== Register definition for TC0 peripheral ========== #define AT91C_TC0_SR ((AT91_REG ) 0xFFFA0020) // (TC0) Status Register #define AT91C_TC0_RC ((AT91_REG ) 0xFFFA001C) // (TC0) Register C #define AT91C_TC0_RB ((AT91_REG ) 0xFFFA0018) // (TC0) Register B #define AT91C_TC0_CCR ((AT91_REG ) 0xFFFA0000) // (TC0) Channel Control Register #define AT91C_TC0_CMR ((AT91_REG ) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) #define AT91C_TC0_IER ((AT91_REG ) 0xFFFA0024) // (TC0) Interrupt Enable Register #define AT91C_TC0_RA ((AT91_REG ) 0xFFFA0014) // (TC0) Register A #define AT91C_TC0_IDR ((AT91_REG ) 0xFFFA0028) // (TC0) Interrupt Disable Register #define AT91C_TC0_CV ((AT91_REG ) 0xFFFA0010) // (TC0) Counter Value #define AT91C_TC0_IMR ((AT91_REG ) 0xFFFA002C) // (TC0) Interrupt Mask Register // ========== Register definition for TC1 peripheral ========== #define AT91C_TC1_RB ((AT91_REG ) 0xFFFA0058) // (TC1) Register B #define AT91C_TC1_CCR ((AT91_REG ) 0xFFFA0040) // (TC1) Channel Control Register #define AT91C_TC1_IER ((AT91_REG ) 0xFFFA0064) // (TC1) Interrupt Enable Register #define AT91C_TC1_IDR ((AT91_REG ) 0xFFFA0068) // (TC1) Interrupt Disable Register #define AT91C_TC1_SR ((AT91_REG ) 0xFFFA0060) // (TC1) Status Register #define AT91C_TC1_CMR ((AT91_REG ) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) #define AT91C_TC1_RA ((AT91_REG ) 0xFFFA0054) // (TC1) Register A #define AT91C_TC1_RC ((AT91_REG ) 0xFFFA005C) // (TC1) Register C #define AT91C_TC1_IMR ((AT91_REG ) 0xFFFA006C) // (TC1) Interrupt Mask Register #define AT91C_TC1_CV ((AT91_REG ) 0xFFFA0050) // (TC1) Counter Value // ========== Register definition for TC2 peripheral ========== #define AT91C_TC2_CMR ((AT91_REG ) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) #define AT91C_TC2_CCR ((AT91_REG ) 0xFFFA0080) // (TC2) Channel Control Register #define AT91C_TC2_CV ((AT91_REG ) 0xFFFA0090) // (TC2) Counter Value #define AT91C_TC2_RA ((AT91_REG ) 0xFFFA0094) // (TC2) Register A #define AT91C_TC2_RB ((AT91_REG ) 0xFFFA0098) // (TC2) Register B #define AT91C_TC2_IDR ((AT91_REG ) 0xFFFA00A8) // (TC2) Interrupt Disable Register #define AT91C_TC2_IMR ((AT91_REG ) 0xFFFA00AC) // (TC2) Interrupt Mask Register #define AT91C_TC2_RC ((AT91_REG ) 0xFFFA009C) // (TC2) Register C #define AT91C_TC2_IER ((AT91_REG ) 0xFFFA00A4) // (TC2) Interrupt Enable Register #define AT91C_TC2_SR ((AT91_REG ) 0xFFFA00A0) // (TC2) Status Register // ========== Register definition for TCB peripheral ========== #define AT91C_TCB_BMR ((AT91_REG ) 0xFFFA00C4) // (TCB) TC Block Mode Register #define AT91C_TCB_BCR ((AT91_REG ) 0xFFFA00C0) // (TCB) TC Block Control Register // ========== Register definition for CAN_MB0 peripheral ========== #define AT91C_CAN_MB0_MDL ((AT91_REG ) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register #define AT91C_CAN_MB0_MAM ((AT91_REG ) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register #define AT91C_CAN_MB0_MCR ((AT91_REG ) 0xFFFD021C) // (CAN_MB0) MailBox Control Register #define AT91C_CAN_MB0_MID ((AT91_REG ) 0xFFFD0208) // (CAN_MB0) MailBox ID Register #define AT91C_CAN_MB0_MSR ((AT91_REG ) 0xFFFD0210) // (CAN_MB0) MailBox Status Register #define AT91C_CAN_MB0_MFID ((AT91_REG ) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register #define AT91C_CAN_MB0_MDH ((AT91_REG ) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register #define AT91C_CAN_MB0_MMR ((AT91_REG ) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register // ========== Register definition for CAN_MB1 peripheral ========== #define AT91C_CAN_MB1_MDL ((AT91_REG ) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register #define AT91C_CAN_MB1_MID ((AT91_REG ) 0xFFFD0228) // (CAN_MB1) MailBox ID Register #define AT91C_CAN_MB1_MMR ((AT91_REG ) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register #define AT91C_CAN_MB1_MSR ((AT91_REG ) 0xFFFD0230) // (CAN_MB1) MailBox Status Register #define AT91C_CAN_MB1_MAM ((AT91_REG ) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register #define AT91C_CAN_MB1_MDH ((AT91_REG ) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register #define AT91C_CAN_MB1_MCR ((AT91_REG ) 0xFFFD023C) // (CAN_MB1) MailBox Control Register #define AT91C_CAN_MB1_MFID ((AT91_REG ) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register // ========== Register definition for CAN_MB2 peripheral ========== #define AT91C_CAN_MB2_MCR ((AT91_REG ) 0xFFFD025C) // (CAN_MB2) MailBox Control Register #define AT91C_CAN_MB2_MDH ((AT91_REG ) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register #define AT91C_CAN_MB2_MID ((AT91_REG ) 0xFFFD0248) // (CAN_MB2) MailBox ID Register #define AT91C_CAN_MB2_MDL ((AT91_REG ) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register #define AT91C_CAN_MB2_MMR ((AT91_REG ) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register #define AT91C_CAN_MB2_MAM ((AT91_REG ) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register #define AT91C_CAN_MB2_MFID ((AT91_REG ) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register #define AT91C_CAN_MB2_MSR ((AT91_REG ) 0xFFFD0250) // (CAN_MB2) MailBox Status Register // ========== Register definition for CAN_MB3 peripheral ========== #define AT91C_CAN_MB3_MFID ((AT91_REG ) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register #define AT91C_CAN_MB3_MAM ((AT91_REG ) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register #define AT91C_CAN_MB3_MID ((AT91_REG ) 0xFFFD0268) // (CAN_MB3) MailBox ID Register #define AT91C_CAN_MB3_MCR ((AT91_REG ) 0xFFFD027C) // (CAN_MB3) MailBox Control Register #define AT91C_CAN_MB3_MMR ((AT91_REG ) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register #define AT91C_CAN_MB3_MSR ((AT91_REG ) 0xFFFD0270) // (CAN_MB3) MailBox Status Register #define AT91C_CAN_MB3_MDL ((AT91_REG ) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register #define AT91C_CAN_MB3_MDH ((AT91_REG ) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register // ========== Register definition for CAN_MB4 peripheral ========== #define AT91C_CAN_MB4_MID ((AT91_REG ) 0xFFFD0288) // (CAN_MB4) MailBox ID Register #define AT91C_CAN_MB4_MMR ((AT91_REG ) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register #define AT91C_CAN_MB4_MDH ((AT91_REG ) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register #define AT91C_CAN_MB4_MFID ((AT91_REG ) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register #define AT91C_CAN_MB4_MSR ((AT91_REG ) 0xFFFD0290) // (CAN_MB4) MailBox Status Register #define AT91C_CAN_MB4_MCR ((AT91_REG ) 0xFFFD029C) // (CAN_MB4) MailBox Control Register #define AT91C_CAN_MB4_MDL ((AT91_REG ) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register #define AT91C_CAN_MB4_MAM ((AT91_REG ) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register // ========== Register definition for CAN_MB5 peripheral ========== #define AT91C_CAN_MB5_MSR ((AT91_REG ) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register #define AT91C_CAN_MB5_MCR ((AT91_REG ) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register #define AT91C_CAN_MB5_MFID ((AT91_REG ) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register #define AT91C_CAN_MB5_MDH ((AT91_REG ) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register #define AT91C_CAN_MB5_MID ((AT91_REG ) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register #define AT91C_CAN_MB5_MMR ((AT91_REG ) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register #define AT91C_CAN_MB5_MDL ((AT91_REG ) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register #define AT91C_CAN_MB5_MAM ((AT91_REG ) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register // ========== Register definition for CAN_MB6 peripheral ========== #define AT91C_CAN_MB6_MFID ((AT91_REG ) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register #define AT91C_CAN_MB6_MID ((AT91_REG ) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register #define AT91C_CAN_MB6_MAM ((AT91_REG ) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register #define AT91C_CAN_MB6_MSR ((AT91_REG ) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register #define AT91C_CAN_MB6_MDL ((AT91_REG ) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register #define AT91C_CAN_MB6_MCR ((AT91_REG ) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register #define AT91C_CAN_MB6_MDH ((AT91_REG ) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register #define AT91C_CAN_MB6_MMR ((AT91_REG ) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register // ========== Register definition for CAN_MB7 peripheral ========== #define AT91C_CAN_MB7_MCR ((AT91_REG ) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register #define AT91C_CAN_MB7_MDH ((AT91_REG ) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register #define AT91C_CAN_MB7_MFID ((AT91_REG ) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register #define AT91C_CAN_MB7_MDL ((AT91_REG ) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register #define AT91C_CAN_MB7_MID ((AT91_REG ) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register #define AT91C_CAN_MB7_MMR ((AT91_REG ) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register #define AT91C_CAN_MB7_MAM ((AT91_REG ) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register #define AT91C_CAN_MB7_MSR ((AT91_REG ) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register // ========== Register definition for CAN peripheral ========== #define AT91C_CAN_TCR ((AT91_REG ) 0xFFFD0024) // (CAN) Transfer Command Register #define AT91C_CAN_IMR ((AT91_REG ) 0xFFFD000C) // (CAN) Interrupt Mask Register #define AT91C_CAN_IER ((AT91_REG ) 0xFFFD0004) // (CAN) Interrupt Enable Register #define AT91C_CAN_ECR ((AT91_REG ) 0xFFFD0020) // (CAN) Error Counter Register #define AT91C_CAN_TIMESTP ((AT91_REG ) 0xFFFD001C) // (CAN) Time Stamp Register #define AT91C_CAN_MR ((AT91_REG ) 0xFFFD0000) // (CAN) Mode Register #define AT91C_CAN_IDR ((AT91_REG ) 0xFFFD0008) // (CAN) Interrupt Disable Register #define AT91C_CAN_ACR ((AT91_REG ) 0xFFFD0028) // (CAN) Abort Command Register #define AT91C_CAN_TIM ((AT91_REG ) 0xFFFD0018) // (CAN) Timer Register #define AT91C_CAN_SR ((AT91_REG ) 0xFFFD0010) // (CAN) Status Register #define AT91C_CAN_BR ((AT91_REG ) 0xFFFD0014) // (CAN) Baudrate Register #define AT91C_CAN_VR ((AT91_REG ) 0xFFFD00FC) // (CAN) Version Register // ========== Register definition for EMAC peripheral ========== #define AT91C_EMAC_ISR ((AT91_REG ) 0xFFFDC024) // (EMAC) Interrupt Status Register #define AT91C_EMAC_SA4H ((AT91_REG ) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes #define AT91C_EMAC_SA1L ((AT91_REG ) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes #define AT91C_EMAC_ELE ((AT91_REG ) 0xFFFDC078) // (EMAC) Excessive Length Errors Register #define AT91C_EMAC_LCOL ((AT91_REG ) 0xFFFDC05C) // (EMAC) Late Collision Register #define AT91C_EMAC_RLE ((AT91_REG ) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register #define AT91C_EMAC_WOL ((AT91_REG ) 0xFFFDC0C4) // (EMAC) Wake On LAN Register #define AT91C_EMAC_DTF ((AT91_REG ) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register #define AT91C_EMAC_TUND ((AT91_REG ) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register #define AT91C_EMAC_NCR ((AT91_REG ) 0xFFFDC000) // (EMAC) Network Control Register #define AT91C_EMAC_SA4L ((AT91_REG ) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes #define AT91C_EMAC_RSR ((AT91_REG ) 0xFFFDC020) // (EMAC) Receive Status Register #define AT91C_EMAC_SA3L ((AT91_REG ) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes #define AT91C_EMAC_TSR ((AT91_REG ) 0xFFFDC014) // (EMAC) Transmit Status Register #define AT91C_EMAC_IDR ((AT91_REG ) 0xFFFDC02C) // (EMAC) Interrupt Disable Register #define AT91C_EMAC_RSE ((AT91_REG ) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register #define AT91C_EMAC_ECOL ((AT91_REG ) 0xFFFDC060) // (EMAC) Excessive Collision Register #define AT91C_EMAC_TID ((AT91_REG ) 0xFFFDC0B8) // (EMAC) Type ID Checking Register #define AT91C_EMAC_HRB ((AT91_REG ) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] #define AT91C_EMAC_TBQP ((AT91_REG ) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer #define AT91C_EMAC_USRIO ((AT91_REG ) 0xFFFDC0C0) // (EMAC) USER Input/Output Register #define AT91C_EMAC_PTR ((AT91_REG ) 0xFFFDC038) // (EMAC) Pause Time Register #define AT91C_EMAC_SA2H ((AT91_REG ) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes #define AT91C_EMAC_ROV ((AT91_REG ) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register #define AT91C_EMAC_ALE ((AT91_REG ) 0xFFFDC054) // (EMAC) Alignment Error Register #define AT91C_EMAC_RJA ((AT91_REG ) 0xFFFDC07C) // (EMAC) Receive Jabbers Register #define AT91C_EMAC_RBQP ((AT91_REG ) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer #define AT91C_EMAC_TPF ((AT91_REG ) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register #define AT91C_EMAC_NCFGR ((AT91_REG ) 0xFFFDC004) // (EMAC) Network Configuration Register #define AT91C_EMAC_HRT ((AT91_REG ) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] #define AT91C_EMAC_USF ((AT91_REG ) 0xFFFDC080) // (EMAC) Undersize Frames Register #define AT91C_EMAC_FCSE ((AT91_REG ) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register #define AT91C_EMAC_TPQ ((AT91_REG ) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register #define AT91C_EMAC_MAN ((AT91_REG ) 0xFFFDC034) // (EMAC) PHY Maintenance Register #define AT91C_EMAC_FTO ((AT91_REG ) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register #define AT91C_EMAC_REV ((AT91_REG ) 0xFFFDC0FC) // (EMAC) Revision Register #define AT91C_EMAC_IMR ((AT91_REG ) 0xFFFDC030) // (EMAC) Interrupt Mask Register #define AT91C_EMAC_SCF ((AT91_REG ) 0xFFFDC044) // (EMAC) Single Collision Frame Register #define AT91C_EMAC_PFR ((AT91_REG ) 0xFFFDC03C) // (EMAC) Pause Frames received Register #define AT91C_EMAC_MCF ((AT91_REG ) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register #define AT91C_EMAC_NSR ((AT91_REG ) 0xFFFDC008) // (EMAC) Network Status Register #define AT91C_EMAC_SA2L ((AT91_REG ) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes #define AT91C_EMAC_FRO ((AT91_REG ) 0xFFFDC04C) // (EMAC) Frames Received OK Register #define AT91C_EMAC_IER ((AT91_REG ) 0xFFFDC028) // (EMAC) Interrupt Enable Register #define AT91C_EMAC_SA1H ((AT91_REG ) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes #define AT91C_EMAC_CSE ((AT91_REG ) 0xFFFDC068) // (EMAC) Carrier Sense Error Register #define AT91C_EMAC_SA3H ((AT91_REG ) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes #define AT91C_EMAC_RRE ((AT91_REG ) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register #define AT91C_EMAC_STE ((AT91_REG ) 0xFFFDC084) // (EMAC) SQE Test Error Register // ========== Register definition for PDC_ADC peripheral ========== #define AT91C_ADC_PTSR ((AT91_REG ) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register #define AT91C_ADC_PTCR ((AT91_REG ) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register #define AT91C_ADC_TNPR ((AT91_REG ) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register #define AT91C_ADC_TNCR ((AT91_REG ) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register #define AT91C_ADC_RNPR ((AT91_REG ) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register #define AT91C_ADC_RNCR ((AT91_REG ) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register #define AT91C_ADC_RPR ((AT91_REG ) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register #define AT91C_ADC_TCR ((AT91_REG ) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register #define AT91C_ADC_TPR ((AT91_REG ) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register #define AT91C_ADC_RCR ((AT91_REG ) 0xFFFD8104) // (PDC_ADC) Receive Counter Register // ========== Register definition for ADC peripheral ========== #define AT91C_ADC_CDR2 ((AT91_REG ) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 #define AT91C_ADC_CDR3 ((AT91_REG ) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 #define AT91C_ADC_CDR0 ((AT91_REG ) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 #define AT91C_ADC_CDR5 ((AT91_REG ) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 #define AT91C_ADC_CHDR ((AT91_REG ) 0xFFFD8014) // (ADC) ADC Channel Disable Register #define AT91C_ADC_SR ((AT91_REG ) 0xFFFD801C) // (ADC) ADC Status Register #define AT91C_ADC_CDR4 ((AT91_REG ) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 #define AT91C_ADC_CDR1 ((AT91_REG ) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 #define AT91C_ADC_LCDR ((AT91_REG ) 0xFFFD8020) // (ADC) ADC Last Converted Data Register #define AT91C_ADC_IDR ((AT91_REG ) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register #define AT91C_ADC_CR ((AT91_REG ) 0xFFFD8000) // (ADC) ADC Control Register #define AT91C_ADC_CDR7 ((AT91_REG ) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 #define AT91C_ADC_CDR6 ((AT91_REG ) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 #define AT91C_ADC_IER ((AT91_REG ) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register #define AT91C_ADC_CHER ((AT91_REG ) 0xFFFD8010) // (ADC) ADC Channel Enable Register #define AT91C_ADC_CHSR ((AT91_REG ) 0xFFFD8018) // (ADC) ADC Channel Status Register #define AT91C_ADC_MR ((AT91_REG ) 0xFFFD8004) // (ADC) ADC Mode Register #define AT91C_ADC_IMR ((AT91_REG ) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register // ========== Register definition for PDC_AES peripheral ========== #define AT91C_AES_TPR ((AT91_REG ) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register #define AT91C_AES_PTCR ((AT91_REG ) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register #define AT91C_AES_RNPR ((AT91_REG ) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register #define AT91C_AES_TNCR ((AT91_REG ) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register #define AT91C_AES_TCR ((AT91_REG ) 0xFFFA410C) // (PDC_AES) Transmit Counter Register #define AT91C_AES_RCR ((AT91_REG ) 0xFFFA4104) // (PDC_AES) Receive Counter Register #define AT91C_AES_RNCR ((AT91_REG ) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register #define AT91C_AES_TNPR ((AT91_REG ) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register #define AT91C_AES_RPR ((AT91_REG ) 0xFFFA4100) // (PDC_AES) Receive Pointer Register #define AT91C_AES_PTSR ((AT91_REG ) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register // ========== Register definition for AES peripheral ========== #define AT91C_AES_IVxR ((AT91_REG ) 0xFFFA4060) // (AES) Initialization Vector x Register #define AT91C_AES_MR ((AT91_REG ) 0xFFFA4004) // (AES) Mode Register #define AT91C_AES_VR ((AT91_REG ) 0xFFFA40FC) // (AES) AES Version Register #define AT91C_AES_ODATAxR ((AT91_REG ) 0xFFFA4050) // (AES) Output Data x Register #define AT91C_AES_IDATAxR ((AT91_REG ) 0xFFFA4040) // (AES) Input Data x Register #define AT91C_AES_CR ((AT91_REG ) 0xFFFA4000) // (AES) Control Register #define AT91C_AES_IDR ((AT91_REG ) 0xFFFA4014) // (AES) Interrupt Disable Register #define AT91C_AES_IMR ((AT91_REG ) 0xFFFA4018) // (AES) Interrupt Mask Register #define AT91C_AES_IER ((AT91_REG ) 0xFFFA4010) // (AES) Interrupt Enable Register #define AT91C_AES_KEYWxR ((AT91_REG ) 0xFFFA4020) // (AES) Key Word x Register #define AT91C_AES_ISR ((AT91_REG ) 0xFFFA401C) // (AES) Interrupt Status Register // ========== Register definition for PDC_TDES peripheral ========== #define AT91C_TDES_RNCR ((AT91_REG ) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register #define AT91C_TDES_TCR ((AT91_REG ) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register #define AT91C_TDES_RCR ((AT91_REG ) 0xFFFA8104) // (PDC_TDES) Receive Counter Register #define AT91C_TDES_TNPR ((AT91_REG ) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register #define AT91C_TDES_RNPR ((AT91_REG ) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register #define AT91C_TDES_RPR ((AT91_REG ) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register #define AT91C_TDES_TNCR ((AT91_REG ) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register #define AT91C_TDES_TPR ((AT91_REG ) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register #define AT91C_TDES_PTSR ((AT91_REG ) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register #define AT91C_TDES_PTCR ((AT91_REG ) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register // ========== Register definition for TDES peripheral ========== #define AT91C_TDES_KEY2WxR ((AT91_REG ) 0xFFFA8028) // (TDES) Key 2 Word x Register #define AT91C_TDES_KEY3WxR ((AT91_REG ) 0xFFFA8030) // (TDES) Key 3 Word x Register #define AT91C_TDES_IDR ((AT91_REG ) 0xFFFA8014) // (TDES) Interrupt Disable Register #define AT91C_TDES_VR ((AT91_REG ) 0xFFFA80FC) // (TDES) TDES Version Register #define AT91C_TDES_IVxR ((AT91_REG ) 0xFFFA8060) // (TDES) Initialization Vector x Register #define AT91C_TDES_ODATAxR ((AT91_REG ) 0xFFFA8050) // (TDES) Output Data x Register #define AT91C_TDES_IMR ((AT91_REG ) 0xFFFA8018) // (TDES) Interrupt Mask Register #define AT91C_TDES_MR ((AT91_REG ) 0xFFFA8004) // (TDES) Mode Register #define AT91C_TDES_CR ((AT91_REG ) 0xFFFA8000) // (TDES) Control Register #define AT91C_TDES_IER ((AT91_REG ) 0xFFFA8010) // (TDES) Interrupt Enable Register #define AT91C_TDES_ISR ((AT91_REG ) 0xFFFA801C) // (TDES) Interrupt Status Register #define AT91C_TDES_IDATAxR ((AT91_REG ) 0xFFFA8040) // (TDES) Input Data x Register #define AT91C_TDES_KEY1WxR ((AT91_REG ) 0xFFFA8020) // (TDES) Key 1 Word x Register // ************************************************************************** // PIO DEFINITIONS FOR AT91SAM7X256 // ************************************************************************* #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 #define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 #define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 #define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 #define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 #define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 #define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 #define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 #define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 #define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 #define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 #define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 #define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 #define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 #define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 #define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock #define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 #define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 #define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync #define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 #define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock #define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 #define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data #define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 #define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data #define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 #define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock #define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 #define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync #define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 #define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data #define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 #define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 #define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input #define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 #define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send #define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 #define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 #define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 #define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send #define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 #define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 #define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 #define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock #define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 #define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send #define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 #define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send #define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 #define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock #define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 #define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable #define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 #define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 #define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 #define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 #define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 #define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 #define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 #define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error #define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input #define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 #define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 #define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 #define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 #define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 #define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 #define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 #define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid #define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 #define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected #define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 #define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 #define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock #define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 #define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 #define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec #define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger #define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 #define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 #define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 #define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 #define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 #define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 #define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 #define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 #define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 #define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 #define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 #define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 #define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A #define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect #define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 #define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B #define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 #define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A #define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready #define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 #define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B #define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator #define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 #define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A #define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 #define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 #define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B #define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 #define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 #define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 #define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 #define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 #define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 #define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 #define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 #define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 #define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 #define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 #define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error #define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 #define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock #define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 #define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output // ************************************************************************* // PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 // ************************************************************************* #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral #define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A #define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B #define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 #define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 #define AT91C_ID_US0 ((unsigned int) 6) // USART 0 #define AT91C_ID_US1 ((unsigned int) 7) // USART 1 #define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller #define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface #define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller #define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port #define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 #define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 #define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 #define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller #define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC #define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter #define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit #define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard #define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved #define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved #define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved #define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved #define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved #define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved #define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved #define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved #define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved #define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved #define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) // ************************************************************************* // BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 // ************************************************************************* #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address #define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address #define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address #define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address #define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address #define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address #define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address #define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address #define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address #define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address #define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address #define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address #define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address #define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address #define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address #define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address #define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address #define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address #define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address #define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address #define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address #define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address #define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address #define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address #define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address #define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address #define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address #define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address #define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address // ************************************************************************* // MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 // *************************************************************************** #define AT91C_ISRAM ((char ) 0x00200000) // Internal SRAM base address #define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) #define AT91C_IFLASH ((char ) 0x00100000) // Internal ROM base address #define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) // - Hardware register definition // - *************************************************************************** // - SOFTWARE API DEFINITION FOR System Peripherals // - ************************************************************************* // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller // - *************************************************************************** // - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #if 0 /_RB_/ AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered // - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status // - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask #endif // - *************************************************************************** // - SOFTWARE API DEFINITION FOR Peripheral DMA Controller // - ************************************************************************* // - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable // - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Debug Unit // - ************************************************************************* // - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits // - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. // - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt // - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Parallel Input Output Controler // - ************************************************************************* // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Clock Generator Controler // - ************************************************************************* // - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time // - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready // - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Power Management Controler // - ************************************************************************* // - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output // - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- // - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- // - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- // - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 // - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask // - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Reset Controller Interface // - ************************************************************************* // - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password // - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. // - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface // - ************************************************************************* // - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart // - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value // - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value // - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface // - ************************************************************************* // - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable // - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status // - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter // - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface // - ************************************************************************* // - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password // - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt // - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface // - ************************************************************************* // - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Memory Controller Interface // - ************************************************************************* // - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit // - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source // - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number // - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key // - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Serial Parallel Interface // - ************************************************************************* // - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer // - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects // - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status // - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status // - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status // - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- // - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- // - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- // - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Usart // - ************************************************************************* // - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable // - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter // - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag // - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- // - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- // - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface // - ************************************************************************* // - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset // - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection // - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection // - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- // - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable // - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable // - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- // - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- // - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Two-wire Interface // - ************************************************************************* // - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset // - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address // - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider // - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged // - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- // - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- // - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR PWMC Channel Interface // - ************************************************************************* // - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period // - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle // - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period // - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter // - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface // - ************************************************************************* // - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) // - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 // - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- // - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- // - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- // - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- // - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- // - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR USB Device Interface // - ************************************************************************* // - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK // - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable // - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable // - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt // - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- // - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- // - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt // - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- // - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 // - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO // - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface // - ************************************************************************* // - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command // - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle // - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror // - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- // - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- // - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Timer Counter Interface // - ************************************************************************* // - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command // - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface // - ************************************************************************* // - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) // - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version // - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- // - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- // - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored // - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- // - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- // - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Control Area Network Interface // - ************************************************************************* // - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat // - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error // - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- // - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- // - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy // - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode // - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field // - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- // - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter // - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field // - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 // - ************************************************************************* // - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame // - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS // - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) // - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) // - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) // - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) // - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- // - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- // - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- // - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) // - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII // - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable // - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Analog to Digital Convertor // - ************************************************************************* // - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion // - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time // - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 // - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- // - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- // - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt // - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted // - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- // - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- // - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- // - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data // - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- // - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- // - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- // - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- // - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- // - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- // - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Advanced Encryption Standard // - ************************************************************************* // - -------- AES_CR : (AES Offset: 0x0) Control Register -------- AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading // - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. // - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection // - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- // - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- // - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. // - ************************************************************************* // - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard // - ************************************************************************* // - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset // - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. // - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection // - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- // - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- // - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. // - ************************************************************************* // - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 // - ************************************************************************* // - ========== Register definition for SYS peripheral ========== // - ========== Register definition for AIC peripheral ========== AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register // - ========== Register definition for PDC_DBGU peripheral ========== AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register // - ========== Register definition for DBGU peripheral ========== AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register // - ========== Register definition for PIOA peripheral ========== AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register // - ========== Register definition for PIOB peripheral ========== AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register // - ========== Register definition for CKGR peripheral ========== AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register // - ========== Register definition for PMC peripheral ========== AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register // - ========== Register definition for RSTC peripheral ========== AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register // - ========== Register definition for RTTC peripheral ========== AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register // - ========== Register definition for PITC peripheral ========== AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register // - ========== Register definition for WDTC peripheral ========== AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register // - ========== Register definition for VREG peripheral ========== AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register // - ========== Register definition for MC peripheral ========== AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register // - ========== Register definition for PDC_SPI1 peripheral ========== AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register // - ========== Register definition for SPI1 peripheral ========== AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register // - ========== Register definition for PDC_SPI0 peripheral ========== AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register // - ========== Register definition for SPI0 peripheral ========== AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register // - ========== Register definition for PDC_US1 peripheral ========== AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register // - ========== Register definition for US1 peripheral ========== AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register // - ========== Register definition for PDC_US0 peripheral ========== AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register // - ========== Register definition for US0 peripheral ========== AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register // - ========== Register definition for PDC_SSC peripheral ========== AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register // - ========== Register definition for SSC peripheral ========== AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register // - ========== Register definition for TWI peripheral ========== AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register // - ========== Register definition for PWMC_CH3 peripheral ========== AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register // - ========== Register definition for PWMC_CH2 peripheral ========== AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register // - ========== Register definition for PWMC_CH1 peripheral ========== AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register // - ========== Register definition for PWMC_CH0 peripheral ========== AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register // - ========== Register definition for PWMC peripheral ========== AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register // - ========== Register definition for UDP peripheral ========== AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register // - ========== Register definition for TC0 peripheral ========== AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register // - ========== Register definition for TC1 peripheral ========== AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value // - ========== Register definition for TC2 peripheral ========== AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register // - ========== Register definition for TCB peripheral ========== AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register // - ========== Register definition for CAN_MB0 peripheral ========== AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register // - ========== Register definition for CAN_MB1 peripheral ========== AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register // - ========== Register definition for CAN_MB2 peripheral ========== AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register // - ========== Register definition for CAN_MB3 peripheral ========== AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register // - ========== Register definition for CAN_MB4 peripheral ========== AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register // - ========== Register definition for CAN_MB5 peripheral ========== AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register // - ========== Register definition for CAN_MB6 peripheral ========== AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register // - ========== Register definition for CAN_MB7 peripheral ========== AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register // - ========== Register definition for CAN peripheral ========== AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register // - ========== Register definition for EMAC peripheral ========== AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register // - ========== Register definition for PDC_ADC peripheral ========== AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register // - ========== Register definition for ADC peripheral ========== AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register // - ========== Register definition for PDC_AES peripheral ========== AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register // - ========== Register definition for AES peripheral ========== AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register // - ========== Register definition for PDC_TDES peripheral ========== AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register // - ========== Register definition for TDES peripheral ========== AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register // - ************************************************************************* // - PIO DEFINITIONS FOR AT91SAM7X256 // - ************************************************************************* AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output // - ************************************************************************* // - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 // - ************************************************************************* AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) AT91C_ID_SYS EQU ( 1) ;- System Peripheral AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 AT91C_ID_US0 EQU ( 6) ;- USART 0 AT91C_ID_US1 EQU ( 7) ;- USART 1 AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface AT91C_ID_PWMC EQU (10) ;- PWM Controller AT91C_ID_UDP EQU (11) ;- USB Device Port AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 AT91C_ID_CAN EQU (15) ;- Control Area Network Controller AT91C_ID_EMAC EQU (16) ;- Ethernet MAC AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard AT91C_ID_20_Reserved EQU (20) ;- Reserved AT91C_ID_21_Reserved EQU (21) ;- Reserved AT91C_ID_22_Reserved EQU (22) ;- Reserved AT91C_ID_23_Reserved EQU (23) ;- Reserved AT91C_ID_24_Reserved EQU (24) ;- Reserved AT91C_ID_25_Reserved EQU (25) ;- Reserved AT91C_ID_26_Reserved EQU (26) ;- Reserved AT91C_ID_27_Reserved EQU (27) ;- Reserved AT91C_ID_28_Reserved EQU (28) ;- Reserved AT91C_ID_29_Reserved EQU (29) ;- Reserved AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) // - ************************************************************************* // - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 // - ************************************************************************* AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address // - ************************************************************************* // - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 // - *************************************************************************** AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) #endif /* AT91SAM7X256_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h	C	oos	357,722
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Components that can be compiled to either ARM or THUMB mode are * contained in port.c The ISR routines, which can only be compiled * to ARM mode, are contained in this file. ----------------------------------------------------------/ /* Changes from V2.5.2 + The critical section management functions have been changed. These no longer modify the stack and are safe to use at all optimisation levels. The functions are now also the same for both ARM and THUMB modes. Changes from V2.6.0 + Removed the 'static' from the definition of vNonPreemptiveTick() to allow the demo to link when using the cooperative scheduler. Changes from V3.2.4 + The assembler statements are now included in a single asm block rather than each line having its own asm block. / / Scheduler includes. / #include "FreeRTOS.h" / Constants required to handle interrupts. / #define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 ) #define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 ) / Constants required to handle critical sections. / #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 ) volatile unsigned long ulCriticalNesting = 9999UL; /-----------------------------------------------------------/ / ISR to handle manual context switches (from a call to taskYIELD()). / void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); / * The scheduler can only be started from ARM mode, hence the inclusion of this * function here. / void vPortISRStartFirstTask( void ); /-----------------------------------------------------------/ void vPortISRStartFirstTask( void ) { / Simply start the scheduler. This is included here as it can only be called from ARM mode. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * Called by portYIELD() or taskYIELD() to manually force a context switch. * * When a context switch is performed from the task level the saved task * context is made to look as if it occurred from within the tick ISR. This * way the same restore context function can be used when restoring the context * saved from the ISR or that saved from a call to vPortYieldProcessor. / void vPortYieldProcessor( void ) { / Within an IRQ ISR the link register has an offset from the true return address, but an SWI ISR does not. Add the offset manually so the same ISR return code can be used in both cases. / __asm volatile ( "ADD LR, LR, #4" ); / Perform the context switch. First save the context of the current task. / portSAVE_CONTEXT(); / Find the highest priority task that is ready to run. / __asm volatile ( "bl vTaskSwitchContext" ); / Restore the context of the new task. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * The ISR used for the scheduler tick. / void vTickISR( void ) __attribute__((naked)); void vTickISR( void ) { / Save the context of the interrupted task. / portSAVE_CONTEXT(); / Increment the RTOS tick count, then look for the highest priority task that is ready to run. / __asm volatile( "bl vTaskIncrementTick" ); #if configUSE_PREEMPTION == 1 __asm volatile( "bl vTaskSwitchContext" ); #endif / Ready for the next interrupt. / T0_IR = portTIMER_MATCH_ISR_BIT; VICVectAddr = portCLEAR_VIC_INTERRUPT; / Restore the context of the new task. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions here to * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then * the utilities are defined as macros in portmacro.h - as per other ports. / #ifdef THUMB_INTERWORK void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); void vPortDisableInterruptsFromThumb( void ) { __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0} \n\t" / Pop R0. / "BX R14" ); / Return back to thumb. / } void vPortEnableInterruptsFromThumb( void ) { __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0} \n\t" / Pop R0. / "BX R14" ); / Return back to thumb. / } #endif / THUMB_INTERWORK / / The code generated by the GCC compiler uses the stack in different ways at different optimisation levels. The interrupt flags can therefore not always be saved to the stack. Instead the critical section nesting level is stored in a variable, which is then saved as part of the stack context. / void vPortEnterCritical( void ) { / Disable interrupts as per portDISABLE_INTERRUPTS(); / __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0}" ); / Pop R0. / / Now interrupts are disabled ulCriticalNesting can be accessed directly. Increment ulCriticalNesting to keep a count of how many times portENTER_CRITICAL() has been called. / ulCriticalNesting++; } void vPortExitCritical( void ) { if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { / Decrement the nesting count as we are leaving a critical section. / ulCriticalNesting--; / If the nesting level has reached zero then interrupts should be re-enabled. / if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { / Enable interrupts as per portEXIT_CRITICAL(). / __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0}" ); / Pop R0. */ } } }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_LPC2000/portISR.c	C	oos	9,559
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE portLONG #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Architecture specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 8 #define portNOP() __asm volatile ( "NOP" ); /-----------------------------------------------------------/ / Scheduler utilities. / / * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but * are included here for efficiency. An attempt to call one from * THUMB mode code will result in a compile time error. / #define portRESTORE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Set the LR to the task stack. / \ __asm volatile ( \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "LDR LR, [R0] \n\t" \ \ / The critical nesting depth is the first item on the stack. / \ / Load it into the ulCriticalNesting variable. / \ "LDR R0, =ulCriticalNesting \n\t" \ "LDMFD LR!, {R1} \n\t" \ "STR R1, [R0] \n\t" \ \ / Get the SPSR from the stack. / \ "LDMFD LR!, {R0} \n\t" \ "MSR SPSR, R0 \n\t" \ \ / Restore all system mode registers for the task. / \ "LDMFD LR, {R0-R14}^ \n\t" \ "NOP \n\t" \ \ / Restore the return address. / \ "LDR LR, [LR, #+60] \n\t" \ \ / And return - correcting the offset in the LR to obtain the / \ / correct address. / \ "SUBS PC, LR, #4 \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } /-----------------------------------------------------------/ #define portSAVE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Push R0 as we are going to use the register. / \ __asm volatile ( \ "STMDB SP!, {R0} \n\t" \ \ / Set R0 to point to the task stack pointer. / \ "STMDB SP,{SP}^ \n\t" \ "NOP \n\t" \ "SUB SP, SP, #4 \n\t" \ "LDMIA SP!,{R0} \n\t" \ \ / Push the return address onto the stack. / \ "STMDB R0!, {LR} \n\t" \ \ / Now we have saved LR we can use it instead of R0. / \ "MOV LR, R0 \n\t" \ \ / Pop R0 so we can save it onto the system mode stack. / \ "LDMIA SP!, {R0} \n\t" \ \ / Push all the system mode registers onto the task stack. / \ "STMDB LR,{R0-LR}^ \n\t" \ "NOP \n\t" \ "SUB LR, LR, #60 \n\t" \ \ / Push the SPSR onto the task stack. / \ "MRS R0, SPSR \n\t" \ "STMDB LR!, {R0} \n\t" \ \ "LDR R0, =ulCriticalNesting \n\t" \ "LDR R0, [R0] \n\t" \ "STMDB LR!, {R0} \n\t" \ \ / Store the new top of stack for the task. / \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "STR LR, [R0] \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } extern void vTaskSwitchContext( void ); #define portYIELD_FROM_ISR() vTaskSwitchContext() #define portYIELD() __asm volatile ( "SWI 0" ) /-----------------------------------------------------------/ / Critical section management. / / * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions in * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not * defined then the utilities are defined as macros here - as per other ports. / #ifdef THUMB_INTERWORK extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else #define portDISABLE_INTERRUPTS() \ __asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #define portENABLE_INTERRUPTS() \ __asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #endif / THUMB_INTERWORK / extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical(); #define portEXIT_CRITICAL() vPortExitCritical(); /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_LPC2000/portmacro.h	C	oos	9,758
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the ARM7 port. * * Components that can be compiled to either ARM or THUMB mode are * contained in this file. The ISR routines, which can only be compiled * to ARM mode are contained in portISR.c. ----------------------------------------------------------/ /* Standard includes. / #include <stdlib.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Constants required to setup the task context. / #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) / System mode, ARM mode, interrupts enabled. / #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) #define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) / Constants required to setup the tick ISR. / #define portENABLE_TIMER ( ( unsigned char ) 0x01 ) #define portPRESCALE_VALUE 0x00 #define portINTERRUPT_ON_MATCH ( ( unsigned long ) 0x01 ) #define portRESET_COUNT_ON_MATCH ( ( unsigned long ) 0x02 ) / Constants required to setup the VIC for the tick ISR. / #define portTIMER_VIC_CHANNEL ( ( unsigned long ) 0x0004 ) #define portTIMER_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0010 ) #define portTIMER_VIC_ENABLE ( ( unsigned long ) 0x0020 ) /-----------------------------------------------------------/ / Setup the timer to generate the tick interrupts. / static void prvSetupTimerInterrupt( void ); / * The scheduler can only be started from ARM mode, so * vPortISRStartFirstSTask() is defined in portISR.c. / extern void vPortISRStartFirstTask( void ); /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been called. * * See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { portSTACK_TYPE pxOriginalTOS; pxOriginalTOS = pxTopOfStack; / To ensure asserts in tasks.c don't fail, although in this case the assert is not really required. / pxTopOfStack--; / Setup the initial stack of the task. The stack is set exactly as expected by the portRESTORE_CONTEXT() macro. / / First on the stack is the return address - which in this case is the start of the task. The offset is added to make the return address appear as it would within an IRQ ISR. / pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; / R14 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 / pxTopOfStack--; / When the task starts is will expect to find the function parameter in R0. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 / pxTopOfStack--; / The last thing onto the stack is the status register, which is set for system mode, with interrupts enabled. / pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00 ) { /* We want the task to start in thumb mode. / pxTopOfStack \|= portTHUMB_MODE_BIT; } pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This means the interrupt flags cannot always be stored on the stack and will instead be stored in a variable, which is then saved as part of the tasks context. / pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled here already. / prvSetupTimerInterrupt(); / Start the first task. / vPortISRStartFirstTask(); / Should not get here! / return 0; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the ARM port will require this function as there is nothing to return to. / } /-----------------------------------------------------------/ / * Setup the timer 0 to generate the tick interrupts at the required frequency. / static void prvSetupTimerInterrupt( void ) { unsigned long ulCompareMatch; extern void ( vTickISR )( void ); / A 1ms tick does not require the use of the timer prescale. This is defaulted to zero but can be used if necessary. / T0_PR = portPRESCALE_VALUE; / Calculate the match value required for our wanted tick rate. / ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; / Protect against divide by zero. Using an if() statement still results in a warning - hence the #if. / #if portPRESCALE_VALUE != 0 { ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); } #endif T0_MR0 = ulCompareMatch; / Generate tick with timer 0 compare match. / T0_MCR = portRESET_COUNT_ON_MATCH \| portINTERRUPT_ON_MATCH; / Setup the VIC for the timer. / VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); VICIntEnable \|= portTIMER_VIC_CHANNEL_BIT; / The ISR installed depends on whether the preemptive or cooperative scheduler is being used. / VICVectAddr0 = ( long ) vTickISR; VICVectCntl0 = portTIMER_VIC_CHANNEL \| portTIMER_VIC_ENABLE; / Start the timer - interrupts are disabled when this function is called so it is okay to do this here. / T0_TCR = portENABLE_TIMER; } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_LPC2000/port.c	C	oos	9,584
/* FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry. MCF5235 Port - Copyright (C) 2006 Christian Walter. This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA A special exception to the GPL can be applied should you wish to distribute a combined work that includes FreeRTOS, without being obliged to provide the source code for any proprietary components. See the licensing section of http://www.FreeRTOS.org for full details of how and when the exception can be applied. *********************************************************************** ************************************************************************* * * * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * * * * This is a concise, step by step, 'hands on' guide that describes both * * general multitasking concepts and FreeRTOS specifics. It presents and * * explains numerous examples that are written using the FreeRTOS API. * * Full source code for all the examples is provided in an accompanying * * .zip file. * * * ************************************************************************* ************************************************************************* Please ensure to read the configuration and relevant port sections of the online documentation. http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif / ------------------------ Data types for Coldfire ----------------------- / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned int #define portBASE_TYPE int #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif / ------------------------ Architecture specifics ------------------------ / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 4 #define portTRAP_YIELD 0 / Trap 0 / #define portIPL_MAX 7 / Only NMI interrupt 7 allowed. / / ------------------------ FreeRTOS macros for port ---------------------- / / * This function must be called when the current state of the active task * should be stored. It must be called immediately after exception * processing from the CPU, i.e. there exists a Coldfire exception frame at * the current position in the stack. The function reserves space on * the stack for the CPU registers and other task dependent values (e.g * ulCriticalNesting) and updates the top of the stack in the TCB. / #define portSAVE_CONTEXT() \ asm volatile ( / reserve space for task state. / \ "lea.l (-64, %sp), %sp\n\t" \ / push data register %d0-%d7/%a0-%a6 on stack. / \ "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t" \ / push ulCriticalNesting counter on stack. / \ "lea.l (60, %sp), %a0\n\t" \ "move.l ulCriticalNesting, (%a0)\n\t" \ / set the new top of the stack in the TCB. / \ "move.l pxCurrentTCB, %a0\n\t" \ "move.l %sp, (%a0)"); /. * This function restores the current active and continues its execution. * It loads the current TCB and restores the processor registers, the * task dependent values (e.g ulCriticalNesting). Finally execution * is continued by executing an rte instruction. / #define portRESTORE_CONTEXT() \ asm volatile ( "move.l pxCurrentTCB, %sp\n\t" \ "move.l (%sp), %sp\n\t" \ / stack pointer now points to the saved registers. / \ "movem.l (%sp), %d0-%d7/%a0-%a6\n\t" \ / restore ulCriticalNesting counter from stack. / \ "lea.l (%sp, 60), %sp\n\t" \ "move.l (%sp)+, ulCriticalNesting\n\t" \ / stack pointer now points to exception frame. / \ "rte\n\t" ); #define portENTER_CRITICAL() \ vPortEnterCritical(); #define portEXIT_CRITICAL() \ vPortExitCritical(); #define portSET_IPL( xIPL ) \ asm_set_ipl( xIPL ) #define portDISABLE_INTERRUPTS() \ do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 ) #define portENABLE_INTERRUPTS() \ do { ( void )portSET_IPL( 0 ); } while( 0 ) #define portYIELD() \ asm volatile ( " trap %0\n\t" : : "i"(portTRAP_YIELD) ) #define portNOP() \ asm volatile ( "nop\n\t" ) #define portENTER_SWITCHING_ISR() \ asm volatile ( "move.w #0x2700, %sr" ); \ / Save the context of the interrupted task. / \ portSAVE_CONTEXT( ); \ { #define portEXIT_SWITCHING_ISR( SwitchRequired ) \ / If a switch is required we call vTaskSwitchContext(). / \ if( SwitchRequired ) \ { \ vTaskSwitchContext( ); \ } \ } \ portRESTORE_CONTEXT( ); / ------------------------ Function prototypes --------------------------- / void vPortEnterCritical( void ); void vPortExitCritical( void ); int asm_set_ipl( unsigned long int uiNewIPL ); / ------------------------ Compiler specifics ---------------------------- / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \ void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) \ void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MCF5235/portmacro.h	C	oos	8,404
/* FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry. MCF5235 Port - Copyright (C) 2006 Christian Walter. This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA A special exception to the GPL can be applied should you wish to distribute a combined work that includes FreeRTOS, without being obliged to provide the source code for any proprietary components. See the licensing section of http://www.FreeRTOS.org for full details of how and when the exception can be applied. *********************************************************************** ************************************************************************* * * * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * * * * This is a concise, step by step, 'hands on' guide that describes both * * general multitasking concepts and FreeRTOS specifics. It presents and * * explains numerous examples that are written using the FreeRTOS API. * * Full source code for all the examples is provided in an accompanying * * .zip file. * * * ************************************************************************* ************************************************************************* Please ensure to read the configuration and relevant port sections of the online documentation. http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #include <stdlib.h> #include "FreeRTOS.h" #include "FreeRTOSConfig.h" #include "task.h" / ------------------------ Types ----------------------------------------- / typedef volatile unsigned long vuint32; typedef volatile unsigned short vuint16; typedef volatile unsigned char vuint8; / ------------------------ Defines --------------------------------------- / #define portVECTOR_TABLE __RAMVEC #define portVECTOR_SYSCALL ( 32 + portTRAP_YIELD ) #define portVECTOR_TIMER ( 64 + 36 ) #define MCF_PIT_PRESCALER 512UL #define MCF_PIT_TIMER_TICKS ( FSYS_2 / MCF_PIT_PRESCALER ) #define MCF_PIT_MODULUS_REGISTER(freq) ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL) #define MCF_PIT_PMR0 ( ( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) ) #define MCF_PIT_PCSR0 ( ( vuint16 )( void * )( &__IPSBAR[ 0x150000 ] ) ) #define MCF_PIT_PCSR_PRE(x) ( ( ( x ) & 0x000F ) << 8 ) #define MCF_PIT_PCSR_EN ( 0x0001 ) #define MCF_PIT_PCSR_RLD ( 0x0002 ) #define MCF_PIT_PCSR_PIF ( 0x0004 ) #define MCF_PIT_PCSR_PIE ( 0x0008 ) #define MCF_PIT_PCSR_OVW ( 0x0010 ) #define MCF_INTC0_ICR36 ( ( vuint8 )( void * )( &__IPSBAR[ 0x000C64 ] ) ) #define MCF_INTC0_IMRH ( ( vuint32 )( void * )( &__IPSBAR[ 0x000C08 ] ) ) #define MCF_INTC0_IMRH_INT_MASK36 ( 0x00000010 ) #define MCF_INTC0_IMRH_MASKALL ( 0x00000001 ) #define MCF_INTC0_ICRn_IP(x) ( ( ( x ) & 0x07 ) << 0 ) #define MCF_INTC0_ICRn_IL(x) ( ( ( x ) & 0x07 ) << 3 ) #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 ) #define portINITIAL_CRITICAL_NESTING ( ( unsigned long ) 10 ) /* ------------------------ Static variables ------------------------------ / volatile unsigned long ulCriticalNesting = portINITIAL_CRITICAL_NESTING; / ------------------------ Static functions ------------------------------ / #if configUSE_PREEMPTION == 0 static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler)); #else static void prvPortPreemptiveTick ( void ); #endif / ------------------------ Start implementation -------------------------- / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { / Place the parameter on the stack in the expected location. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; pxTopOfStack--; /* Place dummy return address on stack. Tasks should never terminate so * we can set this to anything. / pxTopOfStack = ( portSTACK_TYPE ) 0; pxTopOfStack--; /* Create a Motorola Coldfire exception stack frame. First comes the return * address. / pxTopOfStack = ( portSTACK_TYPE ) pxCode; pxTopOfStack--; /* Format, fault-status, vector number for exception stack frame. Task * run in supervisor mode. / pxTopOfStack = 0x40002000UL \| ( portVECTOR_SYSCALL + 32 ) << 18; pxTopOfStack--; /* Set the initial critical section nesting counter to zero. This value * is used to restore the value of ulCriticalNesting. / pxTopOfStack = 0; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xA6; /* A6 / FP / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xA5; /* A5 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xA4; /* A4 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xA3; /* A3 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xA2; /* A2 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xA1; /* A1 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xA0; /* A0 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD7; /* D7 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD6; /* D6 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD5; /* D5 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD4; /* D4 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD3; /* D3 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD2; /* D2 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD1; /* D1 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xD0; /* D0 / return pxTopOfStack; } / * Called by portYIELD() or taskYIELD() to manually force a context switch. / static void prvPortYield( void ) { asm volatile ( "move.w #0x2700, %sr\n\t" ); #if _GCC_USES_FP == 1 asm volatile ( "unlk %fp\n\t" ); #endif / Perform the context switch. First save the context of the current task. / portSAVE_CONTEXT( ); / Find the highest priority task that is ready to run. / vTaskSwitchContext( ); / Restore the context of the new task. / portRESTORE_CONTEXT( ); } #if configUSE_PREEMPTION == 0 / * The ISR used for the scheduler tick depends on whether the cooperative or * the preemptive scheduler is being used. / static void prvPortPreemptiveTick ( void ) { / The cooperative scheduler requires a normal IRQ service routine to * simply increment the system tick. / vTaskIncrementTick( ); MCF_PIT_PCSR0 \|= MCF_PIT_PCSR_PIF; } #else static void prvPortPreemptiveTick( void ) { asm volatile ( "move.w #0x2700, %sr\n\t" ); #if _GCC_USES_FP == 1 asm volatile ( "unlk %fp\n\t" ); #endif portSAVE_CONTEXT( ); MCF_PIT_PCSR0 \|= MCF_PIT_PCSR_PIF; vTaskIncrementTick( ); vTaskSwitchContext( ); portRESTORE_CONTEXT( ); } #endif void vPortEnterCritical() { / FIXME: We should store the old IPL here - How are we supposed to do * this. / ( void )portSET_IPL( portIPL_MAX ); / Now interrupts are disabled ulCriticalNesting can be accessed * directly. Increment ulCriticalNesting to keep a count of how many times * portENTER_CRITICAL() has been called. / ulCriticalNesting++; } void vPortExitCritical() { if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { / Decrement the nesting count as we are leaving a critical section. / ulCriticalNesting--; / If the nesting level has reached zero then interrupts should be re-enabled. / if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { ( void )portSET_IPL( 0 ); } } } portBASE_TYPE xPortStartScheduler( void ) { extern void ( portVECTOR_TABLE[ ] ) ( ); /* Add entry in vector table for yield system call. / portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield; / Add entry in vector table for periodic timer. / portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick; / Configure the timer for the system clock. / if ( configTICK_RATE_HZ > 0) { / Configure prescaler / MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) \| MCF_PIT_PCSR_RLD \| MCF_PIT_PCSR_OVW; / Initialize the periodic timer interrupt. / MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ ); / Configure interrupt priority and level and unmask interrupt. / MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) \| MCF_INTC0_ICRn_IP( 0x1 ); MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 \| MCF_INTC0_IMRH_MASKALL ); / Enable interrupts / MCF_PIT_PCSR0 \|= MCF_PIT_PCSR_PIE \| MCF_PIT_PCSR_EN \| MCF_PIT_PCSR_PIF; } / Restore the context of the first task that is going to run. / portRESTORE_CONTEXT( ); / Should not get here. */ return pdTRUE; } void vPortEndScheduler( void ) { }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MCF5235/port.c	C	oos	10,662
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Components that can be compiled to either ARM or THUMB mode are * contained in port.c The ISR routines, which can only be compiled * to ARM mode, are contained in this file. ----------------------------------------------------------/ /* Changes from V3.2.4 + The assembler statements are now included in a single asm block rather than each line having its own asm block. / / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Constants required to handle interrupts. / #define portCLEAR_AIC_INTERRUPT ( ( unsigned long ) 0 ) / Constants required to handle critical sections. / #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 ) volatile unsigned long ulCriticalNesting = 9999UL; /-----------------------------------------------------------/ / ISR to handle manual context switches (from a call to taskYIELD()). / void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); / * The scheduler can only be started from ARM mode, hence the inclusion of this * function here. / void vPortISRStartFirstTask( void ); /-----------------------------------------------------------/ void vPortISRStartFirstTask( void ) { / Simply start the scheduler. This is included here as it can only be called from ARM mode. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * Called by portYIELD() or taskYIELD() to manually force a context switch. * * When a context switch is performed from the task level the saved task * context is made to look as if it occurred from within the tick ISR. This * way the same restore context function can be used when restoring the context * saved from the ISR or that saved from a call to vPortYieldProcessor. / void vPortYieldProcessor( void ) { / Within an IRQ ISR the link register has an offset from the true return address, but an SWI ISR does not. Add the offset manually so the same ISR return code can be used in both cases. / asm volatile ( "ADD LR, LR, #4" ); / Perform the context switch. First save the context of the current task. / portSAVE_CONTEXT(); / Find the highest priority task that is ready to run. / vTaskSwitchContext(); / Restore the context of the new task. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * The ISR used for the scheduler tick depends on whether the cooperative or * the preemptive scheduler is being used. / #if configUSE_PREEMPTION == 0 / The cooperative scheduler requires a normal IRQ service routine to simply increment the system tick. / void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); void vNonPreemptiveTick( void ) { static volatile unsigned long ulDummy; / Clear tick timer interrupt indication. / ulDummy = portTIMER_REG_BASE_PTR->TC_SR; vTaskIncrementTick(); / Acknowledge the interrupt at AIC level... / AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; } #else / else preemption is turned on / / The preemptive scheduler is defined as "naked" as the full context is saved on entry as part of the context switch. / void vPreemptiveTick( void ) __attribute__((naked)); void vPreemptiveTick( void ) { / Save the context of the interrupted task. / portSAVE_CONTEXT(); / WARNING - Do not use local (stack) variables here. Use globals if you must! / static volatile unsigned long ulDummy; / Clear tick timer interrupt indication. / ulDummy = portTIMER_REG_BASE_PTR->TC_SR; / Increment the RTOS tick count, then look for the highest priority task that is ready to run. / vTaskIncrementTick(); vTaskSwitchContext(); / Acknowledge the interrupt at AIC level... / AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; / Restore the context of the new task. / portRESTORE_CONTEXT(); } #endif /-----------------------------------------------------------/ / * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions here to * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then * the utilities are defined as macros in portmacro.h - as per other ports. / #ifdef THUMB_INTERWORK void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); void vPortDisableInterruptsFromThumb( void ) { asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0} \n\t" / Pop R0. / "BX R14" ); / Return back to thumb. / } void vPortEnableInterruptsFromThumb( void ) { asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0} \n\t" / Pop R0. / "BX R14" ); / Return back to thumb. / } #endif / THUMB_INTERWORK / / The code generated by the GCC compiler uses the stack in different ways at different optimisation levels. The interrupt flags can therefore not always be saved to the stack. Instead the critical section nesting level is stored in a variable, which is then saved as part of the stack context. / void vPortEnterCritical( void ) { / Disable interrupts as per portDISABLE_INTERRUPTS(); / asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0}" ); / Pop R0. / / Now interrupts are disabled ulCriticalNesting can be accessed directly. Increment ulCriticalNesting to keep a count of how many times portENTER_CRITICAL() has been called. / ulCriticalNesting++; } void vPortExitCritical( void ) { if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { / Decrement the nesting count as we are leaving a critical section. / ulCriticalNesting--; / If the nesting level has reached zero then interrupts should be re-enabled. / if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { / Enable interrupts as per portEXIT_CRITICAL(). / asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0}" ); / Pop R0. */ } } }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91FR40008/portISR.c	C	oos	10,037
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Changes from V3.2.3 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. Changes from V3.2.4 + Removed the use of the %0 parameter within the assembler macros and replaced them with hard coded registers. This will ensure the assembler does not select the link register as the temp register as was occasionally happening previously. + The assembler statements are now included in a single asm block rather than each line having its own asm block. Changes from V4.5.0 + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros and replaced them with portYIELD_FROM_ISR() macro. Application code should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() macros as per the V4.5.1 demo code. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE long #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Hardware specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 8 #define portYIELD() asm volatile ( "SWI 0" ) #define portNOP() asm volatile ( "NOP" ) / * These define the timer to use for generating the tick interrupt. * They are put in this file so they can be shared between "port.c" * and "portisr.c". / #define portTIMER_REG_BASE_PTR AT91C_BASE_TC0 #define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0 #define portTIMER_AIC_CHANNEL ( ( unsigned portLONG ) 4 ) /-----------------------------------------------------------/ / Task utilities. / / * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but * are included here for efficiency. An attempt to call one from * THUMB mode code will result in a compile time error. / #define portRESTORE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Set the LR to the task stack. / \ asm volatile ( \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "LDR LR, [R0] \n\t" \ \ / The critical nesting depth is the first item on the stack. / \ / Load it into the ulCriticalNesting variable. / \ "LDR R0, =ulCriticalNesting \n\t" \ "LDMFD LR!, {R1} \n\t" \ "STR R1, [R0] \n\t" \ \ / Get the SPSR from the stack. / \ "LDMFD LR!, {R0} \n\t" \ "MSR SPSR, R0 \n\t" \ \ / Restore all system mode registers for the task. / \ "LDMFD LR, {R0-R14}^ \n\t" \ "NOP \n\t" \ \ / Restore the return address. / \ "LDR LR, [LR, #+60] \n\t" \ \ / And return - correcting the offset in the LR to obtain the / \ / correct address. / \ "SUBS PC, LR, #4 \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } /-----------------------------------------------------------/ #define portSAVE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Push R0 as we are going to use the register. / \ asm volatile ( \ "STMDB SP!, {R0} \n\t" \ \ / Set R0 to point to the task stack pointer. / \ "STMDB SP,{SP}^ \n\t" \ "NOP \n\t" \ "SUB SP, SP, #4 \n\t" \ "LDMIA SP!,{R0} \n\t" \ \ / Push the return address onto the stack. / \ "STMDB R0!, {LR} \n\t" \ \ / Now we have saved LR we can use it instead of R0. / \ "MOV LR, R0 \n\t" \ \ / Pop R0 so we can save it onto the system mode stack. / \ "LDMIA SP!, {R0} \n\t" \ \ / Push all the system mode registers onto the task stack. / \ "STMDB LR,{R0-LR}^ \n\t" \ "NOP \n\t" \ "SUB LR, LR, #60 \n\t" \ \ / Push the SPSR onto the task stack. / \ "MRS R0, SPSR \n\t" \ "STMDB LR!, {R0} \n\t" \ \ "LDR R0, =ulCriticalNesting \n\t" \ "LDR R0, [R0] \n\t" \ "STMDB LR!, {R0} \n\t" \ \ / Store the new top of stack for the task. / \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "STR LR, [R0] \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } #define portYIELD_FROM_ISR() vTaskSwitchContext() / Critical section handling. / / * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions in * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not * defined then the utilities are defined as macros here - as per other ports. / #ifdef THUMB_INTERWORK extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else #define portDISABLE_INTERRUPTS() \ asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #define portENABLE_INTERRUPTS() \ asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #endif / THUMB_INTERWORK / extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical(); #define portEXIT_CRITICAL() vPortExitCritical(); /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h	C	oos	10,752
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the Atmel AT91R40008 * port. * * Components that can be compiled to either ARM or THUMB mode are * contained in this file. The ISR routines, which can only be compiled * to ARM mode are contained in portISR.c. ----------------------------------------------------------/ /* Standard includes. / #include <stdlib.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Hardware specific definitions. / #include "AT91R40008.h" #include "pio.h" #include "aic.h" #include "tc.h" / Constants required to setup the task context. / #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) / System mode, ARM mode, interrupts enabled. / #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) #define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) #define portTICK_PRIORITY_6 ( 6 ) /-----------------------------------------------------------/ / Setup the timer to generate the tick interrupts. / static void prvSetupTimerInterrupt( void ); / * The scheduler can only be started from ARM mode, so * vPortISRStartFirstSTask() is defined in portISR.c. / extern void vPortISRStartFirstTask( void ); /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been called. * * See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { portSTACK_TYPE pxOriginalTOS; pxOriginalTOS = pxTopOfStack; / To ensure asserts in tasks.c don't fail, although in this case the assert is not really required. / pxTopOfStack--; / Setup the initial stack of the task. The stack is set exactly as expected by the portRESTORE_CONTEXT() macro. / / First on the stack is the return address - which in this case is the start of the task. The offset is added to make the return address appear as it would within an IRQ ISR. / pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; / R14 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 / pxTopOfStack--; / When the task starts is will expect to find the function parameter in R0. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 / pxTopOfStack--; / The last thing onto the stack is the status register, which is set for system mode, with interrupts enabled. / pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; #ifdef THUMB_INTERWORK { /* We want the task to start in thumb mode. / pxTopOfStack \|= portTHUMB_MODE_BIT; } #endif pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This means the interrupt flags cannot always be stored on the stack and will instead be stored in a variable, which is then saved as part of the tasks context. / pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled here already. / prvSetupTimerInterrupt(); / Start the first task. / vPortISRStartFirstTask(); / Should not get here! / return 0; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the ARM port will require this function as there is nothing to return to. / } /-----------------------------------------------------------/ / * Setup the tick timer to generate the tick interrupts at the required frequency. / static void prvSetupTimerInterrupt( void ) { volatile unsigned long ulDummy; / Enable clock to the tick timer... / AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; / Stop the tick timer... / portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS; / Start with tick timer interrupts disabled... / portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF; / Clear any pending tick timer interrupts... / ulDummy = portTIMER_REG_BASE_PTR->TC_SR; / Store interrupt handler function address in tick timer vector register... The ISR installed depends on whether the preemptive or cooperative scheduler is being used. / #if configUSE_PREEMPTION == 1 { extern void ( vPreemptiveTick )( void ); AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned long ) vPreemptiveTick; } #else // else use cooperative scheduler { extern void ( vNonPreemptiveTick )( void ); AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned long ) vNonPreemptiveTick; } #endif / Tick timer interrupt level-sensitive, priority 6... / AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE \| portTICK_PRIORITY_6; / Enable the tick timer interrupt... First at timer level / portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; / Then at the AIC level. / AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL); / Calculate timer compare value to achieve the desired tick rate... / if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ 2) ) <= 0xFFFF ) { /* The tick rate is fast enough for us to use the faster timer input clock (main clock / 2). / portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE \| TC_CLKS_MCK2 \| TC_BURST_NONE \| TC_CPCTRG; portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ 2); } else { /* We must use a slower timer input clock (main clock / 8) because the tick rate is too slow for the faster input clock. / portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE \| TC_CLKS_MCK8 \| TC_BURST_NONE \| TC_CPCTRG; portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ 8); } /* Start tick timer... / portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG \| TC_CLKEN; } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_AT91FR40008/port.c	C	oos	10,191
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT int #define portSTACK_TYPE unsigned portSHORT #define portBASE_TYPE portSHORT #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Interrupt control macros. / #define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ) #define portENABLE_INTERRUPTS() asm volatile ( "EINT" ) /-----------------------------------------------------------/ / Critical section control macros. / #define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) #define portENTER_CRITICAL() \ { \ extern volatile unsigned portSHORT usCriticalNesting; \ \ portDISABLE_INTERRUPTS(); \ \ / Now interrupts are disabled ulCriticalNesting can be accessed / \ / directly. Increment ulCriticalNesting to keep a count of how many / \ / times portENTER_CRITICAL() has been called. / \ usCriticalNesting++; \ } #define portEXIT_CRITICAL() \ { \ extern volatile unsigned portSHORT usCriticalNesting; \ \ if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ { \ / Decrement the nesting count as we are leaving a critical section. / \ usCriticalNesting--; \ \ / If the nesting level has reached zero then interrupts should be / \ / re-enabled. / \ if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ { \ portENABLE_INTERRUPTS(); \ } \ } \ } /-----------------------------------------------------------/ / Task utilities. / extern void vPortYield( void ) __attribute__ ( ( naked ) ); #define portYIELD() vPortYield() #define portNOP() asm volatile ( "NOP" ) /-----------------------------------------------------------/ / Hardwware specifics. / #define portBYTE_ALIGNMENT 2 #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MSP430F449/portmacro.h	C	oos	6,243
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Changes from V2.5.2 + usCriticalNesting now has a volatile qualifier. / / Standard includes. / #include <stdlib.h> #include <signal.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" /----------------------------------------------------------- * Implementation of functions defined in portable.h for the MSP430 port. ----------------------------------------------------------/ /* Constants required for hardware setup. The tick ISR runs off the ACLK, not the MCLK. / #define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) #define portINITIAL_CRITICAL_NESTING ( ( unsigned short ) 10 ) #define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) / We require the address of the pxCurrentTCB variable, but don't want to know any details of its type. / typedef void tskTCB; extern volatile tskTCB volatile pxCurrentTCB; /* Most ports implement critical sections by placing the interrupt flags on the stack before disabling interrupts. Exiting the critical section is then simply a case of popping the flags from the stack. As mspgcc does not use a frame pointer this cannot be done as modifying the stack will clobber all the stack variables. Instead each task maintains a count of the critical section nesting depth. Each time a critical section is entered the count is incremented. Each time a critical section is left the count is decremented - with interrupts only being re-enabled if the count is zero. usCriticalNesting will get set to zero when the scheduler starts, but must not be initialised to zero as this will cause problems during the startup sequence. / volatile unsigned short usCriticalNesting = portINITIAL_CRITICAL_NESTING; /-----------------------------------------------------------/ / * Macro to save a task context to the task stack. This simply pushes all the * general purpose msp430 registers onto the stack, followed by the * usCriticalNesting value used by the task. Finally the resultant stack * pointer value is saved into the task control block so it can be retrieved * the next time the task executes. / #define portSAVE_CONTEXT() \ asm volatile ( "push r4 \n\t" \ "push r5 \n\t" \ "push r6 \n\t" \ "push r7 \n\t" \ "push r8 \n\t" \ "push r9 \n\t" \ "push r10 \n\t" \ "push r11 \n\t" \ "push r12 \n\t" \ "push r13 \n\t" \ "push r14 \n\t" \ "push r15 \n\t" \ "mov.w usCriticalNesting, r14 \n\t" \ "push r14 \n\t" \ "mov.w pxCurrentTCB, r12 \n\t" \ "mov.w r1, @r12 \n\t" \ ); / * Macro to restore a task context from the task stack. This is effectively * the reverse of portSAVE_CONTEXT(). First the stack pointer value is * loaded from the task control block. Next the value for usCriticalNesting * used by the task is retrieved from the stack - followed by the value of all * the general purpose msp430 registers. * * The bic instruction ensures there are no low power bits set in the status * register that is about to be popped from the stack. / #define portRESTORE_CONTEXT() \ asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ "mov.w @r12, r1 \n\t" \ "pop r15 \n\t" \ "mov.w r15, usCriticalNesting \n\t" \ "pop r15 \n\t" \ "pop r14 \n\t" \ "pop r13 \n\t" \ "pop r12 \n\t" \ "pop r11 \n\t" \ "pop r10 \n\t" \ "pop r9 \n\t" \ "pop r8 \n\t" \ "pop r7 \n\t" \ "pop r6 \n\t" \ "pop r5 \n\t" \ "pop r4 \n\t" \ "bic #(0xf0),0(r1) \n\t" \ "reti \n\t" \ ); /-----------------------------------------------------------/ / * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but * could have alternatively used the watchdog timer or timer 1. / static void prvSetupTimerInterrupt( void ); /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been called. * * See the header file portable.h. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { /* Place a few bytes of known values on the bottom of the stack. This is just useful for debugging and can be included if required. pxTopOfStack = ( portSTACK_TYPE ) 0x1111; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x2222; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x3333; pxTopOfStack--; / /* The msp430 automatically pushes the PC then SR onto the stack before executing an ISR. We want the stack to look just as if this has happened so place a pointer to the start of the task on the stack first - followed by the flags we want the task to use when it starts up. / pxTopOfStack = ( portSTACK_TYPE ) pxCode; pxTopOfStack--; pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; / Next the general purpose registers. / pxTopOfStack = ( portSTACK_TYPE ) 0x4444; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x5555; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x6666; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x7777; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x8888; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x9999; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; pxTopOfStack--; /* When the task starts is will expect to find the function parameter in R15. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; pxTopOfStack--; /* The code generated by the mspgcc compiler does not maintain separate stack and frame pointers. The portENTER_CRITICAL macro cannot therefore use the stack as per other ports. Instead a variable is used to keep track of the critical section nesting. This variable has to be stored as part of the task context and is initially set to zero. / pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; /* Return a pointer to the top of the stack we have generated so this can be stored in the task control block for the task. / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { / Setup the hardware to generate the tick. Interrupts are disabled when this function is called. / prvSetupTimerInterrupt(); / Restore the context of the first task that is going to run. / portRESTORE_CONTEXT(); / Should not get here as the tasks are now running! / return pdTRUE; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the MSP430 port will get stopped. If required simply disable the tick interrupt here. / } /-----------------------------------------------------------/ / * Manual context switch called by portYIELD or taskYIELD. * * The first thing we do is save the registers so we can use a naked attribute. / void vPortYield( void ) __attribute__ ( ( naked ) ); void vPortYield( void ) { / We want the stack of the task being saved to look exactly as if the task was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the msp430 places the status register onto the stack. As this is a function call and not an ISR we have to do this manually. / asm volatile ( "push r2" ); _DINT(); / Save the context of the current task. / portSAVE_CONTEXT(); / Switch to the highest priority task that is ready to run. / vTaskSwitchContext(); / Restore the context of the new task. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * Hardware initialisation to generate the RTOS tick. This uses timer 0 * but could alternatively use the watchdog timer or timer 1. / static void prvSetupTimerInterrupt( void ) { / Ensure the timer is stopped. / TACTL = 0; / Run the timer of the ACLK. / TACTL = TASSEL_1; / Clear everything to start with. / TACTL \|= TACLR; / Set the compare match value according to the tick rate we want. / TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; / Enable the interrupts. / TACCTL0 = CCIE; / Start up clean. / TACTL \|= TACLR; / Up mode. / TACTL \|= MC_1; } /-----------------------------------------------------------/ / * The interrupt service routine used depends on whether the pre-emptive * scheduler is being used or not. / #if configUSE_PREEMPTION == 1 / * Tick ISR for preemptive scheduler. We can use a naked attribute as * the context is saved at the start of vPortYieldFromTick(). The tick * count is incremented after the context is saved. / interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) ); interrupt (TIMERA0_VECTOR) prvTickISR( void ) { / Save the context of the interrupted task. / portSAVE_CONTEXT(); / Increment the tick count then switch to the highest priority task that is ready to run. / vTaskIncrementTick(); vTaskSwitchContext(); / Restore the context of the new task. / portRESTORE_CONTEXT(); } #else / * Tick ISR for the cooperative scheduler. All this does is increment the * tick count. We don't need to switch context, this can only be done by * manual calls to taskYIELD(); */ interrupt (TIMERA0_VECTOR) prvTickISR( void ); interrupt (TIMERA0_VECTOR) prvTickISR( void ) { vTaskIncrementTick(); } #endif	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MSP430F449/port.c	C	oos	13,030
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / When switching out a task, if the task tag contains a buffer address then save the flop context into the buffer. / #define traceTASK_SWITCHED_OUT() \ if( pxCurrentTCB->pxTaskTag != NULL ) \ { \ extern void vPortSaveFPURegisters( void ); \ vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ } /* When switching in a task, if the task tag contains a buffer address then load the flop context from the buffer. / #define traceTASK_SWITCHED_IN() \ if( pxCurrentTCB->pxTaskTag != NULL ) \ { \ extern void vPortRestoreFPURegisters( void ); \ vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h	C	oos	3,714
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #include "xexception_l.h" #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE portLONG #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / This port uses the critical nesting count from the TCB rather than maintaining a separate value and then saving this value in the task stack. / #define portCRITICAL_NESTING_IN_TCB 1 / Interrupt control macros. / #define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); #define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); /-----------------------------------------------------------/ / Critical section macros. / void vTaskEnterCritical( void ); void vTaskExitCritical( void ); #define portENTER_CRITICAL() vTaskEnterCritical() #define portEXIT_CRITICAL() vTaskExitCritical() /-----------------------------------------------------------/ / Task utilities. / void vPortYield( void ); #define portYIELD() asm volatile ( "SC \n\t NOP" ) #define portYIELD_FROM_ISR() vTaskSwitchContext() /-----------------------------------------------------------/ / Hardware specifics. / #define portBYTE_ALIGNMENT 8 #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portNOP() asm volatile ( "NOP" ) / There are 32 * 32bit floating point regieters, plus the FPSCR to save. / #define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) / Port specific interrupt handling functions. / void vPortSetupInterruptController( void ); portBASE_TYPE xPortInstallInterruptHandler( unsigned portCHAR ucInterruptID, XInterruptHandler pxHandler, void pvCallBackRef ); #ifdef __cplusplus } #endif #endif /* PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/PPC440_Xilinx/portmacro.h	C	oos	5,849
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #include "FreeRTOSConfig.h" .extern pxCurrentTCB .extern vTaskSwitchContext .extern vTaskIncrementTick .extern vPortISRHandler .global vPortStartFirstTask .global vPortYield .global vPortTickISR .global vPortISRWrapper .global vPortSaveFPURegisters .global vPortRestoreFPURegisters .set BChainField, 0 .set NextLRField, BChainField + 4 .set MSRField, NextLRField + 4 .set PCField, MSRField + 4 .set LRField, PCField + 4 .set CTRField, LRField + 4 .set XERField, CTRField + 4 .set CRField, XERField + 4 .set USPRG0Field, CRField + 4 .set r0Field, USPRG0Field + 4 .set r2Field, r0Field + 4 .set r3r31Field, r2Field + 4 .set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) 4 .macro portSAVE_STACK_POINTER_AND_LR /* Get the address of the TCB. / xor R0, R0, R0 addis R2, R0, pxCurrentTCB@ha lwz R2, pxCurrentTCB@l( R2 ) / Store the stack pointer into the TCB / stw SP, 0( R2 ) / Save the link register / stwu R1, -24( R1 ) mflr R0 stw R31, 20( R1 ) stw R0, 28( R1 ) mr R31, r1 .endm .macro portRESTORE_STACK_POINTER_AND_LR / Restore the link register / lwz R11, 0( R1 ) lwz R0, 4( R11 ) mtlr R0 lwz R31, -4( R11 ) mr R1, R11 / Get the address of the TCB. / xor R0, R0, R0 addis SP, R0, pxCurrentTCB@ha lwz SP, pxCurrentTCB@l( R1 ) / Get the task stack pointer from the TCB. / lwz SP, 0( SP ) .endm vPortStartFirstTask: / Get the address of the TCB. / xor R0, R0, R0 addis SP, R0, pxCurrentTCB@ha lwz SP, pxCurrentTCB@l( SP ) / Get the task stack pointer from the TCB. / lwz SP, 0( SP ) / Restore MSR register to SRR1. / lwz R0, MSRField(R1) mtsrr1 R0 / Restore current PC location to SRR0. / lwz R0, PCField(R1) mtsrr0 R0 / Save USPRG0 register / lwz R0, USPRG0Field(R1) mtspr 0x100,R0 / Restore Condition register / lwz R0, CRField(R1) mtcr R0 / Restore Fixed Point Exception register / lwz R0, XERField(R1) mtxer R0 / Restore Counter register / lwz R0, CTRField(R1) mtctr R0 / Restore Link register / lwz R0, LRField(R1) mtlr R0 / Restore remaining GPR registers. / lmw R3,r3r31Field(R1) / Restore r0 and r2. / lwz R0, r0Field(R1) lwz R2, r2Field(R1) / Remove frame from stack / addi R1,R1,IFrameSize / Return into the first task / rfi vPortYield: portSAVE_STACK_POINTER_AND_LR bl vTaskSwitchContext portRESTORE_STACK_POINTER_AND_LR blr vPortTickISR: portSAVE_STACK_POINTER_AND_LR bl vTaskIncrementTick #if configUSE_PREEMPTION == 1 bl vTaskSwitchContext #endif / Clear the interrupt / lis R0, 2048 mttsr R0 portRESTORE_STACK_POINTER_AND_LR blr vPortISRWrapper: portSAVE_STACK_POINTER_AND_LR bl vPortISRHandler portRESTORE_STACK_POINTER_AND_LR blr #if configUSE_FPU == 1 vPortSaveFPURegisters: / Enable APU and mark FPU as present. / mfmsr r0 xor r30, r30, r30 oris r30, r30, 512 ori r30, r30, 8192 or r0, r0, r30 mtmsr r0 #ifdef USE_DP_FPU / Buffer address is in r3. Save each flop register into an offset from this buffer address. / stfd f0, 0(r3) stfd f1, 8(r3) stfd f2, 16(r3) stfd f3, 24(r3) stfd f4, 32(r3) stfd f5, 40(r3) stfd f6, 48(r3) stfd f7, 56(r3) stfd f8, 64(r3) stfd f9, 72(r3) stfd f10, 80(r3) stfd f11, 88(r3) stfd f12, 96(r3) stfd f13, 104(r3) stfd f14, 112(r3) stfd f15, 120(r3) stfd f16, 128(r3) stfd f17, 136(r3) stfd f18, 144(r3) stfd f19, 152(r3) stfd f20, 160(r3) stfd f21, 168(r3) stfd f22, 176(r3) stfd f23, 184(r3) stfd f24, 192(r3) stfd f25, 200(r3) stfd f26, 208(r3) stfd f27, 216(r3) stfd f28, 224(r3) stfd f29, 232(r3) stfd f30, 240(r3) stfd f31, 248(r3) / Also save the FPSCR. / mffs f31 stfs f31, 256(r3) #else / Buffer address is in r3. Save each flop register into an offset from this buffer address. / stfs f0, 0(r3) stfs f1, 4(r3) stfs f2, 8(r3) stfs f3, 12(r3) stfs f4, 16(r3) stfs f5, 20(r3) stfs f6, 24(r3) stfs f7, 28(r3) stfs f8, 32(r3) stfs f9, 36(r3) stfs f10, 40(r3) stfs f11, 44(r3) stfs f12, 48(r3) stfs f13, 52(r3) stfs f14, 56(r3) stfs f15, 60(r3) stfs f16, 64(r3) stfs f17, 68(r3) stfs f18, 72(r3) stfs f19, 76(r3) stfs f20, 80(r3) stfs f21, 84(r3) stfs f22, 88(r3) stfs f23, 92(r3) stfs f24, 96(r3) stfs f25, 100(r3) stfs f26, 104(r3) stfs f27, 108(r3) stfs f28, 112(r3) stfs f29, 116(r3) stfs f30, 120(r3) stfs f31, 124(r3) / Also save the FPSCR. / mffs f31 stfs f31, 128(r3) #endif blr #endif / configUSE_FPU. / #if configUSE_FPU == 1 vPortRestoreFPURegisters: / Enable APU and mark FPU as present. / mfmsr r0 xor r30, r30, r30 oris r30, r30, 512 ori r30, r30, 8192 or r0, r0, r30 mtmsr r0 #ifdef USE_DP_FPU / Buffer address is in r3. Restore each flop register from an offset into this buffer. First the FPSCR. / lfs f31, 256(r3) mtfsf f31, 7 lfd f0, 0(r3) lfd f1, 8(r3) lfd f2, 16(r3) lfd f3, 24(r3) lfd f4, 32(r3) lfd f5, 40(r3) lfd f6, 48(r3) lfd f7, 56(r3) lfd f8, 64(r3) lfd f9, 72(r3) lfd f10, 80(r3) lfd f11, 88(r3) lfd f12, 96(r3) lfd f13, 104(r3) lfd f14, 112(r3) lfd f15, 120(r3) lfd f16, 128(r3) lfd f17, 136(r3) lfd f18, 144(r3) lfd f19, 152(r3) lfd f20, 160(r3) lfd f21, 168(r3) lfd f22, 176(r3) lfd f23, 184(r3) lfd f24, 192(r3) lfd f25, 200(r3) lfd f26, 208(r3) lfd f27, 216(r3) lfd f28, 224(r3) lfd f29, 232(r3) lfd f30, 240(r3) lfd f31, 248(r3) #else / Buffer address is in r3. Restore each flop register from an offset into this buffer. First the FPSCR. / lfs f31, 128(r3) mtfsf f31, 7 lfs f0, 0(r3) lfs f1, 4(r3) lfs f2, 8(r3) lfs f3, 12(r3) lfs f4, 16(r3) lfs f5, 20(r3) lfs f6, 24(r3) lfs f7, 28(r3) lfs f8, 32(r3) lfs f9, 36(r3) lfs f10, 40(r3) lfs f11, 44(r3) lfs f12, 48(r3) lfs f13, 52(r3) lfs f14, 56(r3) lfs f15, 60(r3) lfs f16, 64(r3) lfs f17, 68(r3) lfs f18, 72(r3) lfs f19, 76(r3) lfs f20, 80(r3) lfs f21, 84(r3) lfs f22, 88(r3) lfs f23, 92(r3) lfs f24, 96(r3) lfs f25, 100(r3) lfs f26, 104(r3) lfs f27, 108(r3) lfs f28, 112(r3) lfs f29, 116(r3) lfs f30, 120(r3) lfs f31, 124(r3) #endif blr #endif / configUSE_FPU. */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/PPC440_Xilinx/portasm.S	Unix Assembly	oos	9,595
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the PPC440 port. ----------------------------------------------------------/ /* Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Library includes. / #include "xtime_l.h" #include "xintc.h" #include "xintc_i.h" /-----------------------------------------------------------/ / Definitions to set the initial MSR of each task. / #define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) #define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) #define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) #if configUSE_FPU == 1 #define portAPU_PRESENT ( 1UL << 25UL ) #define portFCM_FPU_PRESENT ( 1UL << 13UL ) #else #define portAPU_PRESENT ( 0UL ) #define portFCM_FPU_PRESENT ( 0UL ) #endif #define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE \| portEXTERNAL_INTERRUPT_ENABLE \| portMACHINE_CHECK_ENABLE \| portAPU_PRESENT \| portFCM_FPU_PRESENT ) extern const unsigned _SDA_BASE_; extern const unsigned _SDA2_BASE_; /-----------------------------------------------------------/ / * Setup the system timer to generate the tick interrupt. / static void prvSetupTimerInterrupt( void ); / * The handler for the tick interrupt - defined in portasm.s. / extern void vPortTickISR( void ); / * The handler for the yield function - defined in portasm.s. / extern void vPortYield( void ); / * Function to start the scheduler running by starting the highest * priority task that has thus far been created. / extern void vPortStartFirstTask( void ); /-----------------------------------------------------------/ / Structure used to hold the state of the interrupt controller. / static XIntc xInterruptController; /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if the task had been * interrupted. * * See the header file portable.h. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { /* Place a known value at the bottom of the stack for debugging. / pxTopOfStack = 0xDEADBEEF; pxTopOfStack--; /* EABI stack frame. / pxTopOfStack -= 20; / Previous backchain and LR, R31 to R4 inclusive. / / Parameters in R13. / pxTopOfStack = ( portSTACK_TYPE ) &_SDA_BASE_; /* address of the first small data area / pxTopOfStack -= 10; / Parameters in R3. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; pxTopOfStack--; /* Parameters in R2. / pxTopOfStack = ( portSTACK_TYPE ) &_SDA2_BASE_; /* address of the second small data area / pxTopOfStack--; / R1 is the stack pointer so is omitted. / pxTopOfStack = 0x10000001UL;; /* R0. / pxTopOfStack--; pxTopOfStack = 0x00000000UL; /* USPRG0. / pxTopOfStack--; pxTopOfStack = 0x00000000UL; /* CR. / pxTopOfStack--; pxTopOfStack = 0x00000000UL; /* XER. / pxTopOfStack--; pxTopOfStack = 0x00000000UL; /* CTR. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) vPortEndScheduler; /* LR. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* SRR0. / pxTopOfStack--; pxTopOfStack = portINITIAL_MSR;/* SRR1. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) vPortEndScheduler;/* Next LR. / pxTopOfStack--; pxTopOfStack = 0x00000000UL;/* Backchain. / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { prvSetupTimerInterrupt(); XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void ) 0 ); vPortStartFirstTask(); /* Should not get here as the tasks are now running! / return pdFALSE; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / Not implemented. / for( ;; ); } /-----------------------------------------------------------/ / * Hardware initialisation to generate the RTOS tick. / static void prvSetupTimerInterrupt( void ) { const unsigned long ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); XTime_DECClearInterrupt(); XTime_FITClearInterrupt(); XTime_WDTClearInterrupt(); XTime_WDTDisableInterrupt(); XTime_FITDisableInterrupt(); XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void ) 0 ); XTime_DECEnableAutoReload(); XTime_DECSetInterval( ulInterval ); XTime_DECEnableInterrupt(); } /-----------------------------------------------------------/ void vPortISRHandler( void pvNullDoNotUse ) { unsigned long ulInterruptStatus, ulInterruptMask = 1UL; portBASE_TYPE xInterruptNumber; XIntc_Config pxInterruptController; XIntc_VectorTableEntry pxTable; / Just to remove compiler warning. / ( void ) pvNullDoNotUse; / Get the configuration by using the device ID - in this case it is assumed that only one interrupt controller is being used. / pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ]; / Which interrupts are pending? / ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress ); for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ ) { if( ulInterruptStatus & 0x01UL ) { / Clear the pending interrupt. / XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask ); / Call the registered handler. / pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] ); pxTable->Handler( pxTable->CallBackRef ); } / Check the next interrupt. / ulInterruptMask <<= 0x01UL; ulInterruptStatus >>= 0x01UL; / Have we serviced all interrupts? / if( ulInterruptStatus == 0UL ) { break; } } } /-----------------------------------------------------------/ void vPortSetupInterruptController( void ) { extern void vPortISRWrapper( void ); / Perform all library calls necessary to initialise the exception table and interrupt controller. This assumes only one interrupt controller is in use. / XExc_mDisableExceptions( XEXC_NON_CRITICAL ); XExc_Init(); / The library functions save the context - we then jump to a wrapper to save the stack into the TCB. The wrapper then calls the handler defined above. / XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL ); XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID ); XIntc_Start( &xInterruptController, XIN_REAL_MODE ); } /-----------------------------------------------------------/ portBASE_TYPE xPortInstallInterruptHandler( unsigned char ucInterruptID, XInterruptHandler pxHandler, void pvCallBackRef ) { portBASE_TYPE xReturn = pdFAIL; /* This function is defined here so the scope of xInterruptController can remain within this file. */ if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) { XIntc_Enable( &xInterruptController, ucInterruptID ); xReturn = pdPASS; } return xReturn; }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/PPC440_Xilinx/port.c	C	oos	10,222
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Hardware includes. / #include <microblaze_exceptions_i.h> #include <microblaze_exceptions_g.h> / The Xilinx library defined exception entry point stacks a number of registers. These definitions are offsets from the stack pointer to the various stacked register values. / #define portexR3_STACK_OFFSET 4 #define portexR4_STACK_OFFSET 5 #define portexR5_STACK_OFFSET 6 #define portexR6_STACK_OFFSET 7 #define portexR7_STACK_OFFSET 8 #define portexR8_STACK_OFFSET 9 #define portexR9_STACK_OFFSET 10 #define portexR10_STACK_OFFSET 11 #define portexR11_STACK_OFFSET 12 #define portexR12_STACK_OFFSET 13 #define portexR15_STACK_OFFSET 16 #define portexR18_STACK_OFFSET 19 #define portexMSR_STACK_OFFSET 20 #define portexR19_STACK_OFFSET -1 / This is defined to equal the size, in bytes, of the stack frame generated by the Xilinx standard library exception entry point. It is required to determine the stack pointer value prior to the exception being entered. / #define portexASM_HANDLER_STACK_FRAME_SIZE 84UL / The number of bytes a MicroBlaze instruction consumes. / #define portexINSTRUCTION_SIZE 4 / Exclude this entire file if the MicroBlaze is not configured to handle exceptions, or the application defined configuration constant configINSTALL_EXCEPTION_HANDLERS is not set to 1. / #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) / This variable is set in the exception entry code, before vPortExceptionHandler is called. / unsigned long pulStackPointerOnFunctionEntry = NULL; /* This is the structure that is filled with the MicroBlaze context as it existed immediately prior to the exception occurrence. A pointer to this structure is passed into the vApplicationExceptionRegisterDump() callback function, if one is defined. / static xPortRegisterDump xRegisterDump; / This is the FreeRTOS exception handler that is installed for all exception types. It is called from vPortExceptionHanlderEntry() - which is itself defined in portasm.S. / void vPortExceptionHandler( void pvExceptionID ); extern void vPortExceptionHandlerEntry( void pvExceptionID ); /-----------------------------------------------------------/ / vApplicationExceptionRegisterDump() is a callback function that the application can optionally define to receive a populated xPortRegisterDump structure. If the application chooses not to define a version of vApplicationExceptionRegisterDump() then this weekly defined default implementation will be called instead. / extern void vApplicationExceptionRegisterDump( xPortRegisterDump xRegisterDump ) __attribute__((weak)); void vApplicationExceptionRegisterDump( xPortRegisterDump xRegisterDump ) { ( void ) xRegisterDump; for( ;; ) { portNOP(); } } /-----------------------------------------------------------/ void vPortExceptionHandler( void pvExceptionID ) { extern void pxCurrentTCB; / Fill an xPortRegisterDump structure with the MicroBlaze context as it was immediately before the exception occurrence. / / First fill in the name and handle of the task that was in the Running state when the exception occurred. / xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; xRegisterDump.pcCurrentTaskName = pcTaskGetTaskName( NULL ); configASSERT( pulStackPointerOnFunctionEntry ); / Obtain the values of registers that were stacked prior to this function being called, and may have changed since they were stacked. / xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; / Obtain the value of all other registers. / xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); xRegisterDump.ulR20 = mfgpr( R20 ); xRegisterDump.ulR21 = mfgpr( R21 ); xRegisterDump.ulR22 = mfgpr( R22 ); xRegisterDump.ulR23 = mfgpr( R23 ); xRegisterDump.ulR24 = mfgpr( R24 ); xRegisterDump.ulR25 = mfgpr( R25 ); xRegisterDump.ulR26 = mfgpr( R26 ); xRegisterDump.ulR27 = mfgpr( R27 ); xRegisterDump.ulR28 = mfgpr( R28 ); xRegisterDump.ulR29 = mfgpr( R29 ); xRegisterDump.ulR30 = mfgpr( R30 ); xRegisterDump.ulR31 = mfgpr( R31 ); xRegisterDump.ulR1_SP = ( ( unsigned long ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; xRegisterDump.ulEAR = mfear(); xRegisterDump.ulESR = mfesr(); xRegisterDump.ulEDR = mfedr(); / Move the saved program counter back to the instruction that was executed when the exception occurred. This is only valid for certain types of exception. / xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; #if XPAR_MICROBLAZE_0_USE_FPU == 1 { xRegisterDump.ulFSR = mffsr(); } #else { xRegisterDump.ulFSR = 0UL; } #endif / Also fill in a string that describes what type of exception this is. The string uses the same ID names as defined in the MicroBlaze standard library exception header files. / switch( ( unsigned long ) pvExceptionID ) { case XEXC_ID_FSL : xRegisterDump.pcExceptionCause = ( signed char const ) "XEXC_ID_FSL"; break; case XEXC_ID_UNALIGNED_ACCESS : xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_UNALIGNED_ACCESS"; break; case XEXC_ID_ILLEGAL_OPCODE : xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_ILLEGAL_OPCODE"; break; case XEXC_ID_M_AXI_I_EXCEPTION : xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION"; break; case XEXC_ID_M_AXI_D_EXCEPTION : xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION"; break; case XEXC_ID_DIV_BY_ZERO : xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_DIV_BY_ZERO"; break; case XEXC_ID_STACK_VIOLATION : xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU"; break; #if XPAR_MICROBLAZE_0_USE_FPU == 1 case XEXC_ID_FPU : xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FPU see ulFSR value"; break; #endif /* XPAR_MICROBLAZE_0_USE_FPU / } / vApplicationExceptionRegisterDump() is a callback function that the application can optionally define to receive the populated xPortRegisterDump structure. If the application chooses not to define a version of vApplicationExceptionRegisterDump() then the weekly defined default implementation within this file will be called instead. / vApplicationExceptionRegisterDump( &xRegisterDump ); / Must not attempt to leave this function! / for( ;; ) { portNOP(); } } /-----------------------------------------------------------/ void vPortExceptionsInstallHandlers( void ) { static unsigned long ulHandlersAlreadyInstalled = pdFALSE; if( ulHandlersAlreadyInstalled == pdFALSE ) { ulHandlersAlreadyInstalled = pdTRUE; #if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1 microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void ) XEXC_ID_UNALIGNED_ACCESS ); #endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS/ #if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void ) XEXC_ID_ILLEGAL_OPCODE ); #endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION/ #if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void ) XEXC_ID_M_AXI_I_EXCEPTION ); #endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION/ #if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void ) XEXC_ID_M_AXI_D_EXCEPTION ); #endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION/ #if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void ) XEXC_ID_IPLB_EXCEPTION ); #endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION/ #if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void ) XEXC_ID_DPLB_EXCEPTION ); #endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION/ #if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void ) XEXC_ID_DIV_BY_ZERO ); #endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION/ #if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void ) XEXC_ID_FPU ); #endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION/ #if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1 microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void ) XEXC_ID_FSL ); #endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION/ } } / Exclude the entire file if the MicroBlaze is not configured to handle exceptions, or the application defined configuration item configINSTALL_EXCEPTION_HANDLERS is not set to 1. / #endif / ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MicroBlazeV8/port_exceptions.c	C	oos	13,791
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif / BSP includes. / #include <mb_interface.h> #include <xparameters.h> /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned long #define portBASE_TYPE long #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Interrupt control macros and functions. / void microblaze_disable_interrupts( void ); void microblaze_enable_interrupts( void ); #define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() #define portENABLE_INTERRUPTS() microblaze_enable_interrupts() /-----------------------------------------------------------/ / Critical section macros. / void vPortEnterCritical( void ); void vPortExitCritical( void ); #define portENTER_CRITICAL() { \ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ microblaze_disable_interrupts(); \ uxCriticalNesting++; \ } #define portEXIT_CRITICAL() { \ extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ / Interrupts are disabled, so we can / \ / access the variable directly. / \ uxCriticalNesting--; \ if( uxCriticalNesting == 0 ) \ { \ / The nesting has unwound and we \ can enable interrupts again. / \ portENABLE_INTERRUPTS(); \ } \ } /-----------------------------------------------------------/ / The yield macro maps directly to the vPortYield() function. / void vPortYield( void ); #define portYIELD() vPortYield() / portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead sets a flag to say that a yield has been requested. The interrupt exit code then checks this flag, and calls vTaskSwitchContext() before restoring a task context, if the flag is not false. This is done to prevent multiple calls to vTaskSwitchContext() being made from a single interrupt, as a single interrupt can result in multiple peripherals being serviced. / extern volatile unsigned long ulTaskSwitchRequested; #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) ulTaskSwitchRequested = 1 /-----------------------------------------------------------/ / Hardware specifics. / #define portBYTE_ALIGNMENT 4 #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portNOP() asm volatile ( "NOP" ) /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) /-----------------------------------------------------------/ / The following structure is used by the FreeRTOS exception handler. It is filled with the MicroBlaze context as it was at the time the exception occurred. This is done as an aid to debugging exception occurrences. / typedef struct PORT_REGISTER_DUMP { / The following structure members hold the values of the MicroBlaze registers at the time the exception was raised. / unsigned long ulR1_SP; unsigned long ulR2_small_data_area; unsigned long ulR3; unsigned long ulR4; unsigned long ulR5; unsigned long ulR6; unsigned long ulR7; unsigned long ulR8; unsigned long ulR9; unsigned long ulR10; unsigned long ulR11; unsigned long ulR12; unsigned long ulR13_read_write_small_data_area; unsigned long ulR14_return_address_from_interrupt; unsigned long ulR15_return_address_from_subroutine; unsigned long ulR16_return_address_from_trap; unsigned long ulR17_return_address_from_exceptions; / The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. / unsigned long ulR18; unsigned long ulR19; unsigned long ulR20; unsigned long ulR21; unsigned long ulR22; unsigned long ulR23; unsigned long ulR24; unsigned long ulR25; unsigned long ulR26; unsigned long ulR27; unsigned long ulR28; unsigned long ulR29; unsigned long ulR30; unsigned long ulR31; unsigned long ulPC; unsigned long ulESR; unsigned long ulMSR; unsigned long ulEAR; unsigned long ulFSR; unsigned long ulEDR; / A human readable description of the exception cause. The strings used are the same as the #define constant names found in the microblaze_exceptions_i.h header file / signed char pcExceptionCause; /* The human readable name of the task that was running at the time the exception occurred. This is the name that was given to the task when the task was created using the FreeRTOS xTaskCreate() API function. / signed char pcCurrentTaskName; /* The handle of the task that was running a the time the exception occurred. / void xCurrentTaskHandle; } xPortRegisterDump; /* * Installs pxHandler as the interrupt handler for the peripheral specified by * the ucInterruptID parameter. * * ucInterruptID: * * The ID of the peripheral that will have pxHandler assigned as its interrupt * handler. Peripheral IDs are defined in the xparameters.h header file, which * is itself part of the BSP project. For example, in the official demo * application for this port, xparameters.h defines the following IDs for the * four possible interrupt sources: * * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. * * * pxHandler: * * A pointer to the interrupt handler function itself. This must be a void * function that takes a (void ) parameter. * * pvCallBackRef: * * The parameter passed into the handler function. In many cases this will not * be used and can be NULL. Some times it is used to pass in a reference to * the peripheral instance variable, so it can be accessed from inside the * handler function. * * * pdPASS is returned if the function executes successfully. Any other value * being returned indicates that the function did not execute correctly. / portBASE_TYPE xPortInstallInterruptHandler( unsigned char ucInterruptID, XInterruptHandler pxHandler, void pvCallBackRef ); /* * Enables the interrupt, within the interrupt controller, for the peripheral * specified by the ucInterruptID parameter. * * ucInterruptID: * * The ID of the peripheral that will have its interrupt enabled in the * interrupt controller. Peripheral IDs are defined in the xparameters.h header * file, which is itself part of the BSP project. For example, in the official * demo application for this port, xparameters.h defines the following IDs for * the four possible interrupt sources: * * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. * / void vPortEnableInterrupt( unsigned char ucInterruptID ); / * Disables the interrupt, within the interrupt controller, for the peripheral * specified by the ucInterruptID parameter. * * ucInterruptID: * * The ID of the peripheral that will have its interrupt disabled in the * interrupt controller. Peripheral IDs are defined in the xparameters.h header * file, which is itself part of the BSP project. For example, in the official * demo application for this port, xparameters.h defines the following IDs for * the four possible interrupt sources: * * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. * / void vPortDisableInterrupt( unsigned char ucInterruptID ); / * This is an application defined callback function used to install the tick * interrupt handler. It is provided as an application callback because the * kernel will run on lots of different MicroBlaze and FPGA configurations - not * all of which will have the same timer peripherals defined or available. This * example uses the AXI Timer 0. If that is available on your hardware platform * then this example callback implementation should not require modification. * The name of the interrupt handler that should be installed is vPortTickISR(), * which the function below declares as an extern. / void vApplicationSetupTimerInterrupt( void ); / * This is an application defined callback function used to clear whichever * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback * function - in this case the interrupt generated by the AXI timer. It is * provided as an application callback because the kernel will run on lots of * different MicroBlaze and FPGA configurations - not all of which will have the * same timer peripherals defined or available. This example uses the AXI Timer 0. * If that is available on your hardware platform then this example callback * implementation should not require modification provided the example definition * of vApplicationSetupTimerInterrupt() is also not modified. / void vApplicationClearTimerInterrupt( void ); / * vPortExceptionsInstallHandlers() is only available when the MicroBlaze * is configured to include exception functionality, and * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h. * * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler * for every possible exception cause. * * vPortExceptionsInstallHandlers() can be called explicitly from application * code. After that is done, the default FreeRTOS exception handler that will * have been installed can be replaced for any specific exception cause by using * the standard Xilinx library function microblaze_register_exception_handler(). * * If vPortExceptionsInstallHandlers() is not called explicitly by the * application, it will be called automatically by the kernel the first time * xPortInstallInterruptHandler() is called. At that time, any exception * handlers that may have already been installed will be replaced. * * See the description of vApplicationExceptionRegisterDump() for information * on the processing performed by the FreeRTOS exception handler. / void vPortExceptionsInstallHandlers( void ); / * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined * in portmacro.h) with the MicroBlaze context, as it was at the time the * exception occurred. The exception handler then calls * vApplicationExceptionRegisterDump(), passing in the completed * xPortRegisterDump structure as its parameter. * * The FreeRTOS kernel provides its own implementation of * vApplicationExceptionRegisterDump(), but the kernel provided implementation * is declared as being 'weak'. The weak definition allows the application * writer to provide their own implementation, should they wish to use the * register dump information. For example, an implementation could be provided * that wrote the register dump data to a display, or a UART port. / void vApplicationExceptionRegisterDump( xPortRegisterDump xRegisterDump ); #ifdef __cplusplus } #endif #endif /* PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MicroBlazeV8/portmacro.h	C	oos	15,552
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / FreeRTOS includes. / #include "FreeRTOSConfig.h" / Xilinx library includes. / #include "microblaze_exceptions_g.h" #include "xparameters.h" / The context is oversized to allow functions called from the ISR to write back into the caller stack. / #if XPAR_MICROBLAZE_0_USE_FPU == 1 #define portCONTEXT_SIZE 136 #define portMINUS_CONTEXT_SIZE -136 #else #define portCONTEXT_SIZE 132 #define portMINUS_CONTEXT_SIZE -132 #endif / Offsets from the stack pointer at which saved registers are placed. / #define portR31_OFFSET 4 #define portR30_OFFSET 8 #define portR29_OFFSET 12 #define portR28_OFFSET 16 #define portR27_OFFSET 20 #define portR26_OFFSET 24 #define portR25_OFFSET 28 #define portR24_OFFSET 32 #define portR23_OFFSET 36 #define portR22_OFFSET 40 #define portR21_OFFSET 44 #define portR20_OFFSET 48 #define portR19_OFFSET 52 #define portR18_OFFSET 56 #define portR17_OFFSET 60 #define portR16_OFFSET 64 #define portR15_OFFSET 68 #define portR14_OFFSET 72 #define portR13_OFFSET 76 #define portR12_OFFSET 80 #define portR11_OFFSET 84 #define portR10_OFFSET 88 #define portR9_OFFSET 92 #define portR8_OFFSET 96 #define portR7_OFFSET 100 #define portR6_OFFSET 104 #define portR5_OFFSET 108 #define portR4_OFFSET 112 #define portR3_OFFSET 116 #define portR2_OFFSET 120 #define portCRITICAL_NESTING_OFFSET 124 #define portMSR_OFFSET 128 #define portFSR_OFFSET 132 .extern pxCurrentTCB .extern XIntc_DeviceInterruptHandler .extern vTaskSwitchContext .extern uxCriticalNesting .extern pulISRStack .extern ulTaskSwitchRequested .extern vPortExceptionHandler .extern pulStackPointerOnFunctionEntry .global _interrupt_handler .global VPortYieldASM .global vPortStartFirstTask .global vPortExceptionHandlerEntry .macro portSAVE_CONTEXT / Make room for the context on the stack. / addik r1, r1, portMINUS_CONTEXT_SIZE / Stack general registers. / swi r31, r1, portR31_OFFSET swi r30, r1, portR30_OFFSET swi r29, r1, portR29_OFFSET swi r28, r1, portR28_OFFSET swi r27, r1, portR27_OFFSET swi r26, r1, portR26_OFFSET swi r25, r1, portR25_OFFSET swi r24, r1, portR24_OFFSET swi r23, r1, portR23_OFFSET swi r22, r1, portR22_OFFSET swi r21, r1, portR21_OFFSET swi r20, r1, portR20_OFFSET swi r19, r1, portR19_OFFSET swi r18, r1, portR18_OFFSET swi r17, r1, portR17_OFFSET swi r16, r1, portR16_OFFSET swi r15, r1, portR15_OFFSET / R14 is saved later as it needs adjustment if a yield is performed. / swi r13, r1, portR13_OFFSET swi r12, r1, portR12_OFFSET swi r11, r1, portR11_OFFSET swi r10, r1, portR10_OFFSET swi r9, r1, portR9_OFFSET swi r8, r1, portR8_OFFSET swi r7, r1, portR7_OFFSET swi r6, r1, portR6_OFFSET swi r5, r1, portR5_OFFSET swi r4, r1, portR4_OFFSET swi r3, r1, portR3_OFFSET swi r2, r1, portR2_OFFSET / Stack the critical section nesting value. / lwi r18, r0, uxCriticalNesting swi r18, r1, portCRITICAL_NESTING_OFFSET / Stack MSR. / mfs r18, rmsr swi r18, r1, portMSR_OFFSET #if XPAR_MICROBLAZE_0_USE_FPU == 1 / Stack FSR. / mfs r18, rfsr swi r18, r1, portFSR_OFFSET #endif / Save the top of stack value to the TCB. / lwi r3, r0, pxCurrentTCB sw r1, r0, r3 .endm .macro portRESTORE_CONTEXT / Load the top of stack value from the TCB. / lwi r18, r0, pxCurrentTCB lw r1, r0, r18 / Restore the general registers. / lwi r31, r1, portR31_OFFSET lwi r30, r1, portR30_OFFSET lwi r29, r1, portR29_OFFSET lwi r28, r1, portR28_OFFSET lwi r27, r1, portR27_OFFSET lwi r26, r1, portR26_OFFSET lwi r25, r1, portR25_OFFSET lwi r24, r1, portR24_OFFSET lwi r23, r1, portR23_OFFSET lwi r22, r1, portR22_OFFSET lwi r21, r1, portR21_OFFSET lwi r20, r1, portR20_OFFSET lwi r19, r1, portR19_OFFSET lwi r17, r1, portR17_OFFSET lwi r16, r1, portR16_OFFSET lwi r15, r1, portR15_OFFSET lwi r14, r1, portR14_OFFSET lwi r13, r1, portR13_OFFSET lwi r12, r1, portR12_OFFSET lwi r11, r1, portR11_OFFSET lwi r10, r1, portR10_OFFSET lwi r9, r1, portR9_OFFSET lwi r8, r1, portR8_OFFSET lwi r7, r1, portR7_OFFSET lwi r6, r1, portR6_OFFSET lwi r5, r1, portR5_OFFSET lwi r4, r1, portR4_OFFSET lwi r3, r1, portR3_OFFSET lwi r2, r1, portR2_OFFSET / Reload the rmsr from the stack. / lwi r18, r1, portMSR_OFFSET mts rmsr, r18 #if XPAR_MICROBLAZE_0_USE_FPU == 1 / Reload the FSR from the stack. / lwi r18, r1, portFSR_OFFSET mts rfsr, r18 #endif / Load the critical nesting value. / lwi r18, r1, portCRITICAL_NESTING_OFFSET swi r18, r0, uxCriticalNesting / Test the critical nesting value. If it is non zero then the task last exited the running state using a yield. If it is zero, then the task last exited the running state through an interrupt. / xori r18, r18, 0 bnei r18, exit_from_yield / r18 was being used as a temporary. Now restore its true value from the stack. / lwi r18, r1, portR18_OFFSET / Remove the stack frame. / addik r1, r1, portCONTEXT_SIZE / Return using rtid so interrupts are re-enabled as this function is exited. / rtid r14, 0 or r0, r0, r0 .endm / This function is used to exit portRESTORE_CONTEXT() if the task being returned to last left the Running state by calling taskYIELD() (rather than being preempted by an interrupt). / .text .align 2 exit_from_yield: / r18 was being used as a temporary. Now restore its true value from the stack. / lwi r18, r1, portR18_OFFSET / Remove the stack frame. / addik r1, r1, portCONTEXT_SIZE / Return to the task. / rtsd r14, 0 or r0, r0, r0 .text .align 2 _interrupt_handler: portSAVE_CONTEXT / Stack the return address. / swi r14, r1, portR14_OFFSET / Switch to the ISR stack. / lwi r1, r0, pulISRStack / The parameter to the interrupt handler. / ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE / Execute any pending interrupts. / bralid r15, XIntc_DeviceInterruptHandler or r0, r0, r0 / See if a new task should be selected to execute. / lwi r18, r0, ulTaskSwitchRequested or r18, r18, r0 / If ulTaskSwitchRequested is already zero, then jump straight to restoring the task that is already in the Running state. / beqi r18, task_switch_not_requested / Set ulTaskSwitchRequested back to zero as a task switch is about to be performed. / swi r0, r0, ulTaskSwitchRequested / ulTaskSwitchRequested was not 0 when tested. Select the next task to execute. / bralid r15, vTaskSwitchContext or r0, r0, r0 task_switch_not_requested: / Restore the context of the next task scheduled to execute. / portRESTORE_CONTEXT .text .align 2 VPortYieldASM: portSAVE_CONTEXT / Modify the return address so a return is done to the instruction after the call to VPortYieldASM. / addi r14, r14, 8 swi r14, r1, portR14_OFFSET / Switch to use the ISR stack. / lwi r1, r0, pulISRStack / Select the next task to execute. / bralid r15, vTaskSwitchContext or r0, r0, r0 / Restore the context of the next task scheduled to execute. / portRESTORE_CONTEXT .text .align 2 vPortStartFirstTask: portRESTORE_CONTEXT #if MICROBLAZE_EXCEPTIONS_ENABLED == 1 .text .align 2 vPortExceptionHandlerEntry: / Take a copy of the stack pointer before vPortExecptionHandler is called, storing its value prior to the function stack frame being created. / swi r1, r0, pulStackPointerOnFunctionEntry bralid r15, vPortExceptionHandler or r0, r0, r0 #endif / MICROBLAZE_EXCEPTIONS_ENABLED */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MicroBlazeV8/portasm.S	Unix Assembly	oos	10,680
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the MicroBlaze port. ----------------------------------------------------------/ /* Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Standard includes. / #include <string.h> / Hardware includes. / #include <xintc_i.h> #include <xil_exception.h> #include <microblaze_exceptions_g.h> / Tasks are started with a critical section nesting of 0 - however, prior to the scheduler being commenced interrupts should not be enabled, so the critical nesting variable is initialised to a non-zero value. / #define portINITIAL_NESTING_VALUE ( 0xff ) / The bit within the MSR register that enabled/disables interrupts. / #define portMSR_IE ( 0x02U ) / If the floating point unit is included in the MicroBlaze build, then the FSR register is saved as part of the task context. portINITIAL_FSR is the value given to the FSR register when the initial context is set up for a task being created. / #define portINITIAL_FSR ( 0U ) /-----------------------------------------------------------/ / * Initialise the interrupt controller instance. / static long prvInitialiseInterruptController( void ); / Ensure the interrupt controller instance variable is initialised before it is * used, and that the initialisation only happens once. / static long prvEnsureInterruptControllerIsInitialised( void ); /-----------------------------------------------------------/ / Counts the nesting depth of calls to portENTER_CRITICAL(). Each task maintains its own count, so this variable is saved as part of the task context. / volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE; / This port uses a separate stack for interrupts. This prevents the stack of every task needing to be large enough to hold an entire interrupt stack on top of the task stack. / unsigned long pulISRStack; /* If an interrupt requests a context switch, then ulTaskSwitchRequested will get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel will call vTaskSwitchContext() to ensure the task that runs immediately after the interrupt exists is the highest priority task that is able to run. This is an unusual mechanism, but is used for this port because a single interrupt can cause the servicing of multiple peripherals - and it is inefficient to call vTaskSwitchContext() multiple times as each peripheral is serviced. / volatile unsigned long ulTaskSwitchRequested = 0UL; / The instance of the interrupt controller used by this port. This is required by the Xilinx library API functions. / static XIntc xInterruptControllerInstance; /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been made. * * See the portable.h header file. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { extern void _SDA2_BASE_, _SDA_BASE_; const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_; const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_; /* Place a few bytes of known values on the bottom of the stack. This is essential for the Microblaze port and these lines must not be omitted. / pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; pxTopOfStack--; #if XPAR_MICROBLAZE_0_USE_FPU == 1 /* The FSR value placed in the initial task context is just 0. / pxTopOfStack = portINITIAL_FSR; pxTopOfStack--; #endif /* The MSR value placed in the initial task context should have interrupts disabled. Each task will enable interrupts automatically when it enters the running state for the first time. / pxTopOfStack = mfmsr() & ~portMSR_IE; pxTopOfStack--; /* First stack an initial value for the critical section nesting. This is initialised to zero. / pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 is always zero. / / R1 is the SP. / / Place an initial value for all the general purpose registers. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - read only small data area. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 - return values and temporaries. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 - return values and temporaries. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. / #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 - other parameters and temporaries. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 - other parameters and temporaries. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 - other parameters and temporaries. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10 - other parameters and temporaries. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11 - temporaries. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12 - temporaries. / pxTopOfStack--; #else pxTopOfStack-= 8; #endif pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - read/write small data area. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14 - return address for interrupt. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) NULL; /* R15 - return address for subroutine. / #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16 - return address for trap (debugger). / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17 - return address for exceptions, if configured. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18 - reserved for assembler and compiler temporaries. / pxTopOfStack--; #else pxTopOfStack -= 4; #endif pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. / #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30 - must be saved across function calls. Callee-save. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31 - must be saved across function calls. Callee-save. / pxTopOfStack--; #else pxTopOfStack -= 13; #endif / Return a pointer to the top of the stack that has been generated so this can be stored in the task control block for the task. / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { extern void ( vPortStartFirstTask )( void ); extern unsigned long _stack[]; / Setup the hardware to generate the tick. Interrupts are disabled when this function is called. This port uses an application defined callback function to install the tick interrupt handler because the kernel will run on lots of different MicroBlaze and FPGA configurations - not all of which will have the same timer peripherals defined or available. An example definition of vApplicationSetupTimerInterrupt() is provided in the official demo application that accompanies this port. / vApplicationSetupTimerInterrupt(); / Reuse the stack from main() as the stack for the interrupts/exceptions. / pulISRStack = ( unsigned long ) _stack; /* Ensure there is enough space for the functions called from the interrupt service routines to write back into the stack frame of the caller. / pulISRStack -= 2; / Restore the context of the first task that is going to run. From here on, the created tasks will be executing. / vPortStartFirstTask(); / Should not get here as the tasks are now running! / return pdFALSE; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / Not implemented. / } /-----------------------------------------------------------/ / * Manual context switch called by portYIELD or taskYIELD. / void vPortYield( void ) { extern void VPortYieldASM( void ); / Perform the context switch in a critical section to assure it is not interrupted by the tick ISR. It is not a problem to do this as each task maintains its own interrupt status. / portENTER_CRITICAL(); { / Jump directly to the yield function to ensure there is no compiler generated prologue code. / asm volatile ( "bralid r14, VPortYieldASM \n\t" \ "or r0, r0, r0 \n\t" ); } portEXIT_CRITICAL(); } /-----------------------------------------------------------/ void vPortEnableInterrupt( unsigned char ucInterruptID ) { long lReturn; / An API function is provided to enable an interrupt in the interrupt controller because the interrupt controller instance variable is private to this file. / lReturn = prvEnsureInterruptControllerIsInitialised(); if( lReturn == pdPASS ) { XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); } configASSERT( lReturn ); } /-----------------------------------------------------------/ void vPortDisableInterrupt( unsigned char ucInterruptID ) { long lReturn; / An API function is provided to disable an interrupt in the interrupt controller because the interrupt controller instance variable is private to this file. / lReturn = prvEnsureInterruptControllerIsInitialised(); if( lReturn == pdPASS ) { XIntc_Disable( &xInterruptControllerInstance, ucInterruptID ); } configASSERT( lReturn ); } /-----------------------------------------------------------/ portBASE_TYPE xPortInstallInterruptHandler( unsigned char ucInterruptID, XInterruptHandler pxHandler, void pvCallBackRef ) { long lReturn; /* An API function is provided to install an interrupt handler because the interrupt controller instance variable is private to this file. / lReturn = prvEnsureInterruptControllerIsInitialised(); if( lReturn == pdPASS ) { lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef ); } if( lReturn == XST_SUCCESS ) { lReturn = pdPASS; } configASSERT( lReturn == pdPASS ); return lReturn; } /-----------------------------------------------------------/ static long prvEnsureInterruptControllerIsInitialised( void ) { static long lInterruptControllerInitialised = pdFALSE; long lReturn; / Ensure the interrupt controller instance variable is initialised before it is used, and that the initialisation only happens once. / if( lInterruptControllerInitialised != pdTRUE ) { lReturn = prvInitialiseInterruptController(); if( lReturn == pdPASS ) { lInterruptControllerInitialised = pdTRUE; } } else { lReturn = pdPASS; } return lReturn; } /-----------------------------------------------------------/ / * Handler for the timer interrupt. This is the handler that the application * defined callback function vApplicationSetupTimerInterrupt() should install. / void vPortTickISR( void pvUnused ) { extern void vApplicationClearTimerInterrupt( void ); /* Ensure the unused parameter does not generate a compiler warning. / ( void ) pvUnused; / This port uses an application defined callback function to clear the tick interrupt because the kernel will run on lots of different MicroBlaze and FPGA configurations - not all of which will have the same timer peripherals defined or available. An example definition of vApplicationClearTimerInterrupt() is provided in the official demo application that accompanies this port. / vApplicationClearTimerInterrupt(); / Increment the RTOS tick - this might cause a task to unblock. / vTaskIncrementTick(); / If the preemptive scheduler is being used then a context switch should be requested in case incrementing the tick unblocked a task, or a time slice should cause another task to enter the Running state. / #if configUSE_PREEMPTION == 1 / Force vTaskSwitchContext() to be called as the interrupt exits. / ulTaskSwitchRequested = 1; #endif } /-----------------------------------------------------------/ static long prvInitialiseInterruptController( void ) { long lStatus; lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE ); if( lStatus == XST_SUCCESS ) { / Initialise the exception table. / Xil_ExceptionInit(); / Service all pending interrupts each time the handler is entered. / XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION ); / Install exception handlers if the MicroBlaze is configured to handle exceptions, and the application defined constant configINSTALL_EXCEPTION_HANDLERS is set to 1. / #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) { vPortExceptionsInstallHandlers(); } #endif / MICROBLAZE_EXCEPTIONS_ENABLED / / Start the interrupt controller. Interrupts are enabled when the scheduler starts. / lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE ); if( lStatus == XST_SUCCESS ) { lStatus = pdPASS; } else { lStatus = pdFAIL; } } configASSERT( lStatus == pdPASS ); return lStatus; } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MicroBlazeV8/port.c	C	oos	18,506
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif #include <machine/ic.h> /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE portLONG #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Architecture specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 4 #define portNOP() __asm__ volatile ( "mov r0, r0" ) #define portCRITICAL_NESTING_IN_TCB 1 #define portIRQ_TRAP_YIELD 31 #define portKERNEL_INTERRUPT_PRIORITY_LEVEL 0 #define portSYSTEM_INTERRUPT_PRIORITY_LEVEL 0 /-----------------------------------------------------------/ / Task utilities. / extern void vPortYield( void ); /---------------------------------------------------------------------------/ #define portYIELD() asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory") /---------------------------------------------------------------------------/ extern void vTaskEnterCritical( void ); extern void vTaskExitCritical( void ); #define portENTER_CRITICAL() vTaskEnterCritical() #define portEXIT_CRITICAL() vTaskExitCritical() /---------------------------------------------------------------------------/ / Critical section management. / #define portDISABLE_INTERRUPTS() ic->cpl = ( portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1 ) #define portENABLE_INTERRUPTS() ic->cpl = portKERNEL_INTERRUPT_PRIORITY_LEVEL /---------------------------------------------------------------------------/ #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext() /---------------------------------------------------------------------------/ #define portSAVE_CONTEXT() \ asm __volatile__ \ ( \ "sub r1, #68 \n" / Make space on the stack for the context. / \ "std r2, [r1] + 0 \n" \ "stq r4, [r1] + 8 \n" \ "stq r8, [r1] + 24 \n" \ "stq r12, [r1] + 40 \n" \ "mov r6, rtt \n" \ "mov r7, psr \n" \ "std r6, [r1] + 56 \n" \ "movhi r2, #16384 \n" / Set the pointer to the IC. / \ "ldub r3, [r2] + 2 \n" / Load the current interrupt mask. / \ "st r3, [r1]+ 64 \n" / Store the interrupt mask on the stack. / \ "ld r2, [r0]+short(pxCurrentTCB) \n" / Load the pointer to the TCB. / \ "st r1, [r2] \n" / Save the stack pointer into the TCB. / \ "mov r14, r1 \n" / Compiler expects r14 to be set to the function stack. / \ ); /---------------------------------------------------------------------------/ #define portRESTORE_CONTEXT() \ asm __volatile__( \ "ld r2, [r0]+short(pxCurrentTCB) \n" / Load the TCB to find the stack pointer and context. / \ "ld r1, [r2] \n" \ "movhi r2, #16384 \n" / Set the pointer to the IC. / \ "ld r3, [r1] + 64 \n" / Load the previous interrupt mask. / \ "stb r3, [r2] + 2 \n" / Set the current interrupt mask to be the previous. / \ "ldd r6, [r1] + 56 \n" / Restore context. / \ "mov rtt, r6 \n" \ "mov psr, r7 \n" \ "ldd r2, [r1] + 0 \n" \ "ldq r4, [r1] + 8 \n" \ "ldq r8, [r1] + 24 \n" \ "ldq r12, [r1] + 40 \n" \ "add r1, #68 \n" \ "rti \n" \ ); /---------------------------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) /---------------------------------------------------------------------------/ #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/CORTUS_APS3/portmacro.h	C	oos	7,981
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Standard includes. / #include <stdlib.h> / Kernel includes. / #include "FreeRTOS.h" #include "task.h" / Machine includes / #include <machine/counter.h> #include <machine/ic.h> /-----------------------------------------------------------/ / The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. / #define portINITIAL_PSR ( 0x00020000 ) /-----------------------------------------------------------/ / * Perform any hardware configuration necessary to generate the tick interrupt. / static void prvSetupTimerInterrupt( void ); /-----------------------------------------------------------/ portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { / Make space on the stack for the context - this leaves a couple of spaces empty. / pxTopOfStack -= 20; / Fill the registers with known values to assist debugging. / pxTopOfStack[ 16 ] = portKERNEL_INTERRUPT_PRIORITY_LEVEL; pxTopOfStack[ 15 ] = portINITIAL_PSR; pxTopOfStack[ 14 ] = ( unsigned long ) pxCode; pxTopOfStack[ 13 ] = 0x00000000UL; / R15. / pxTopOfStack[ 12 ] = 0x00000000UL; / R14. / pxTopOfStack[ 11 ] = 0x0d0d0d0dUL; pxTopOfStack[ 10 ] = 0x0c0c0c0cUL; pxTopOfStack[ 9 ] = 0x0b0b0b0bUL; pxTopOfStack[ 8 ] = 0x0a0a0a0aUL; pxTopOfStack[ 7 ] = 0x09090909UL; pxTopOfStack[ 6 ] = 0x08080808UL; pxTopOfStack[ 5 ] = 0x07070707UL; pxTopOfStack[ 4 ] = 0x06060606UL; pxTopOfStack[ 3 ] = 0x05050505UL; pxTopOfStack[ 2 ] = 0x04040404UL; pxTopOfStack[ 1 ] = 0x03030303UL; pxTopOfStack[ 0 ] = ( unsigned long ) pvParameters; return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { / Set-up the timer interrupt. / prvSetupTimerInterrupt(); / Enable the TRAP yield. / irq[ portIRQ_TRAP_YIELD ].ien = 1; irq[ portIRQ_TRAP_YIELD ].ipl = portKERNEL_INTERRUPT_PRIORITY_LEVEL; / Integrated Interrupt Controller: Enable all interrupts. / ic->ien = 1; / Restore callee saved registers. / portRESTORE_CONTEXT(); / Should not get here. / return 0; } /-----------------------------------------------------------/ static void prvSetupTimerInterrupt( void ) { / Enable timer interrupts / counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1; counter1->value = counter1->reload; counter1->mask = 1; / Set the IRQ Handler priority and enable it. / irq[ IRQ_COUNTER1 ].ien = 1; irq[ IRQ_COUNTER1 ].ipl = portKERNEL_INTERRUPT_PRIORITY_LEVEL; } /-----------------------------------------------------------/ / Trap 31 handler. / void interrupt31_handler( void ) __attribute__((naked)); void interrupt31_handler( void ) { portSAVE_CONTEXT(); __asm volatile ( "call vTaskSwitchContext" ); portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ static void prvProcessTick( void ) __attribute__((noinline)); static void prvProcessTick( void ) { vTaskIncrementTick(); #if configUSE_PREEMPTION == 1 vTaskSwitchContext(); #endif / Clear the Tick Interrupt. / counter1->expired = 0; } /-----------------------------------------------------------/ / Timer 1 interrupt handler, used for tick interrupt. / void interrupt7_handler( void ) __attribute__((naked)); void interrupt7_handler( void ) { portSAVE_CONTEXT(); prvProcessTick(); portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / Nothing to do. Unlikely to want to end. / } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/CORTUS_APS3/port.c	C	oos	6,696
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE long #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Architecture specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 8 /-----------------------------------------------------------/ / Scheduler utilities. / extern void vPortYieldFromISR( void ); #define portYIELD() vPortYieldFromISR() #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() /-----------------------------------------------------------/ / Critical section management. / / * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other * registers. r0 is clobbered. / #define portSET_INTERRUPT_MASK() \ __asm volatile \ ( \ " mov r0, %0 \n" \ " msr basepri, r0 \n" \ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \ ) / * Set basepri back to 0 without effective other registers. * r0 is clobbered. / #define portCLEAR_INTERRUPT_MASK() \ __asm volatile \ ( \ " mov r0, #0 \n" \ " msr basepri, r0 \n" \ :::"r0" \ ) #define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() #define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portNOP() #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM_CM3/portmacro.h	C	oos	5,920
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the ARM CM3 port. ----------------------------------------------------------/ /* Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is defined. The value should also ensure backward compatibility. FreeRTOS.org versions prior to V4.4.0 did not include this definition. / #ifndef configKERNEL_INTERRUPT_PRIORITY #define configKERNEL_INTERRUPT_PRIORITY 255 #endif / Constants required to manipulate the NVIC. / #define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long ) 0xe000e010 ) #define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long ) 0xe000e014 ) #define portNVIC_INT_CTRL ( ( volatile unsigned long ) 0xe000ed04 ) #define portNVIC_SYSPRI2 ( ( volatile unsigned long ) 0xe000ed20 ) #define portNVIC_SYSTICK_CLK 0x00000004 #define portNVIC_SYSTICK_INT 0x00000002 #define portNVIC_SYSTICK_ENABLE 0x00000001 #define portNVIC_PENDSVSET 0x10000000 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) / Constants required to set up the initial stack. / #define portINITIAL_XPSR ( 0x01000000 ) / The priority used by the kernel is assigned to a variable to make access from inline assembler easier. / const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY; / Each task maintains its own interrupt status in the critical nesting variable. / static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; / * Setup the timer to generate the tick interrupts. / static void prvSetupTimerInterrupt( void ); / * Exception handlers. / void xPortPendSVHandler( void ) __attribute__ (( naked )); void xPortSysTickHandler( void ); void vPortSVCHandler( void ) __attribute__ (( naked )); / * Start first task is a separate function so it can be tested in isolation. / void vPortStartFirstTask( void ) __attribute__ (( naked )); /-----------------------------------------------------------/ / * See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { /* Simulate the stack frame as it would be created by a context switch interrupt. / pxTopOfStack--; / Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. / pxTopOfStack = portINITIAL_XPSR; /* xPSR / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC / pxTopOfStack--; pxTopOfStack = 0; /* LR / pxTopOfStack -= 5; / R12, R3, R2 and R1. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 / pxTopOfStack -= 8; / R11, R10, R9, R8, R7, R6, R5 and R4. / return pxTopOfStack; } /-----------------------------------------------------------/ void vPortSVCHandler( void ) { __asm volatile ( " ldr r3, pxCurrentTCBConst2 \n" / Restore the context. / " ldr r1, [r3] \n" / Use pxCurrentTCBConst to get the pxCurrentTCB address. / " ldr r0, [r1] \n" / The first item in pxCurrentTCB is the task top of stack. / " ldmia r0!, {r4-r11} \n" / Pop the registers that are not automatically saved on exception entry and the critical nesting count. / " msr psp, r0 \n" / Restore the task stack pointer. / " mov r0, #0 \n" " msr basepri, r0 \n" " orr r14, #0xd \n" " bx r14 \n" " \n" " .align 2 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } /-----------------------------------------------------------/ void vPortStartFirstTask( void ) { __asm volatile( " ldr r0, =0xE000ED08 \n" / Use the NVIC offset register to locate the stack. / " ldr r0, [r0] \n" " ldr r0, [r0] \n" " msr msp, r0 \n" / Set the msp back to the start of the stack. / " cpsie i \n" / Globally enable interrupts. / " svc 0 \n" / System call to start first task. / " nop \n" ); } /-----------------------------------------------------------/ / * See header file for description. / portBASE_TYPE xPortStartScheduler( void ) { / Make PendSV, CallSV and SysTick the same priroity as the kernel. / (portNVIC_SYSPRI2) \|= portNVIC_PENDSV_PRI; (portNVIC_SYSPRI2) \|= portNVIC_SYSTICK_PRI; / Start the timer that generates the tick ISR. Interrupts are disabled here already. / prvSetupTimerInterrupt(); / Initialise the critical nesting count ready for the first task. / uxCriticalNesting = 0; / Start the first task. / vPortStartFirstTask(); / Should not get here! / return 0; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the CM3 port will require this function as there is nothing to return to. / } /-----------------------------------------------------------/ void vPortYieldFromISR( void ) { / Set a PendSV to request a context switch. / (portNVIC_INT_CTRL) = portNVIC_PENDSVSET; } /-----------------------------------------------------------/ void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); uxCriticalNesting++; } /-----------------------------------------------------------/ void vPortExitCritical( void ) { uxCriticalNesting--; if( uxCriticalNesting == 0 ) { portENABLE_INTERRUPTS(); } } /-----------------------------------------------------------/ void xPortPendSVHandler( void ) { /* This is a naked function. / __asm volatile ( " mrs r0, psp \n" " \n" " ldr r3, pxCurrentTCBConst \n" / Get the location of the current TCB. / " ldr r2, [r3] \n" " \n" " stmdb r0!, {r4-r11} \n" / Save the remaining registers. / " str r0, [r2] \n" / Save the new top of stack into the first member of the TCB. / " \n" " stmdb sp!, {r3, r14} \n" " mov r0, %0 \n" " msr basepri, r0 \n" " bl vTaskSwitchContext \n" " mov r0, #0 \n" " msr basepri, r0 \n" " ldmia sp!, {r3, r14} \n" " \n" / Restore the context, including the critical nesting count. / " ldr r1, [r3] \n" " ldr r0, [r1] \n" / The first item in pxCurrentTCB is the task top of stack. / " ldmia r0!, {r4-r11} \n" / Pop the registers. / " msr psp, r0 \n" " bx r14 \n" " \n" " .align 2 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } /-----------------------------------------------------------/ void xPortSysTickHandler( void ) { unsigned long ulDummy; / If using preemption, also force a context switch. / #if configUSE_PREEMPTION == 1 (portNVIC_INT_CTRL) = portNVIC_PENDSVSET; #endif ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); { vTaskIncrementTick(); } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); } /-----------------------------------------------------------/ /* * Setup the systick timer to generate the tick interrupts at the required * frequency. / void prvSetupTimerInterrupt( void ) { / Configure SysTick to interrupt at the requested rate. / (portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; (portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK \| portNVIC_SYSTICK_INT \| portNVIC_SYSTICK_ENABLE; } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM_CM3/port.c	C	oos	10,720
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned long #define portBASE_TYPE long #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Hardware specifics. / #define portBYTE_ALIGNMENT 4 #define portSTACK_GROWTH -1 #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) /-----------------------------------------------------------/ unsigned portLONG ulPortSetIPL( unsigned portLONG ); #define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) #define portENABLE_INTERRUPTS() ulPortSetIPL( 0 ) extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void ); extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE ); #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) /-----------------------------------------------------------/ / Task utilities. / #define portNOP() asm volatile ( "nop" ) / Note this will overwrite all other bits in the force register, it is done this way for speed. / #define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) __attribute__((noreturn)) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) /-----------------------------------------------------------/ #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \ { \ portYIELD(); \ } #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ColdFire_V2/portmacro.h	C	oos	5,841
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / * Purpose: Lowest level routines for all ColdFire processors. * * Notes: * * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale * supplied source files. / .global ulPortSetIPL .global mcf5xxx_wr_cacr .global __cs3_isr_interrupt_80 .global vPortStartFirstTask .text .macro portSAVE_CONTEXT lea.l (-60, %sp), %sp movem.l %d0-%fp, (%sp) move.l pxCurrentTCB, %a0 move.l %sp, (%a0) .endm .macro portRESTORE_CONTEXT move.l pxCurrentTCB, %a0 move.l (%a0), %sp movem.l (%sp), %d0-%fp lea.l %sp@(60), %sp rte .endm /******************************************************************/ / * This routines changes the IPL to the value passed into the routine. * It also returns the old IPL value back. * Calling convention from C: * old_ipl = asm_set_ipl(new_ipl); * For the Diab Data C compiler, it passes return value thru D0. * Note that only the least significant three bits of the passed * value are used. / ulPortSetIPL: link A6,#-8 movem.l D6-D7,(SP) move.w SR,D7 / current sr / move.l D7,D0 / prepare return value / andi.l #0x0700,D0 / mask out IPL / lsr.l #8,D0 / IPL / move.l 8(A6),D6 / get argument / andi.l #0x07,D6 / least significant three bits / lsl.l #8,D6 / move over to make mask / andi.l #0x0000F8FF,D7 / zero out current IPL / or.l D6,D7 / place new IPL in sr / move.w D7,SR movem.l (SP),D6-D7 lea 8(SP),SP unlk A6 rts /******************************************************************/ mcf5xxx_wr_cacr: move.l 4(sp),d0 .long 0x4e7b0002 / movec d0,cacr / nop rts /******************************************************************/ / Yield interrupt. / __cs3_isr_interrupt_80: portSAVE_CONTEXT jsr vPortYieldHandler portRESTORE_CONTEXT /*******************************************************************/ vPortStartFirstTask: portRESTORE_CONTEXT .end	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ColdFire_V2/portasm.S	Motorola 68K Assembly	oos	5,135
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Kernel includes. / #include "FreeRTOS.h" #include "task.h" #define portINITIAL_FORMAT_VECTOR ( ( portSTACK_TYPE ) 0x4000 ) / Supervisor mode set. / #define portINITIAL_STATUS_REGISTER ( ( portSTACK_TYPE ) 0x2000) / Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This will be set to 0 prior to the first task being started. / static unsigned long ulCriticalNesting = 0x9999UL; /-----------------------------------------------------------/ portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { pxTopOfStack = ( portSTACK_TYPE ) pvParameters; pxTopOfStack--; pxTopOfStack = (portSTACK_TYPE) 0xDEADBEEF; pxTopOfStack--; / Exception stack frame starts with the return address. / pxTopOfStack = ( portSTACK_TYPE ) pxCode; pxTopOfStack--; pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) \| ( portINITIAL_STATUS_REGISTER ); pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0; /FP/ pxTopOfStack -= 14; /* A5 to D0. / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { extern void vPortStartFirstTask( void ); ulCriticalNesting = 0UL; / Configure the interrupts used by this port. / vApplicationSetupInterrupts(); / Start the first task executing. / vPortStartFirstTask(); return pdFALSE; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / Not implemented as there is nothing to return to. / } /-----------------------------------------------------------/ void vPortEnterCritical( void ) { if( ulCriticalNesting == 0UL ) { / Guard against context switches being pended simultaneously with a critical section being entered. / do { portDISABLE_INTERRUPTS(); if( MCF_INTC0_INTFRCL == 0UL ) { break; } portENABLE_INTERRUPTS(); } while( 1 ); } ulCriticalNesting++; } /-----------------------------------------------------------/ void vPortExitCritical( void ) { ulCriticalNesting--; if( ulCriticalNesting == 0 ) { portENABLE_INTERRUPTS(); } } /-----------------------------------------------------------/ void vPortYieldHandler( void ) { unsigned long ulSavedInterruptMask; ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); / Note this will clear all forced interrupts - this is done for speed. */ MCF_INTC0_INTFRCL = 0; vTaskSwitchContext(); portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ColdFire_V2/port.c	C	oos	5,629
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Components that can be compiled to either ARM or THUMB mode are * contained in port.c The ISR routines, which can only be compiled * to ARM mode, are contained in this file. ----------------------------------------------------------/ /* Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Constants required to handle interrupts. / #define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) #define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) / Constants required to handle critical sections. / #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) volatile unsigned portLONG ulCriticalNesting = 9999UL; /-----------------------------------------------------------/ / ISR to handle manual context switches (from a call to taskYIELD()). / void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); / * The scheduler can only be started from ARM mode, hence the inclusion of this * function here. / void vPortISRStartFirstTask( void ); /-----------------------------------------------------------/ void vPortISRStartFirstTask( void ) { / Simply start the scheduler. This is included here as it can only be called from ARM mode. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * Called by portYIELD() or taskYIELD() to manually force a context switch. * * When a context switch is performed from the task level the saved task * context is made to look as if it occurred from within the tick ISR. This * way the same restore context function can be used when restoring the context * saved from the ISR or that saved from a call to vPortYieldProcessor. / void vPortYieldProcessor( void ) { / Within an IRQ ISR the link register has an offset from the true return address, but an SWI ISR does not. Add the offset manually so the same ISR return code can be used in both cases. / __asm volatile ( "ADD LR, LR, #4" ); / Perform the context switch. First save the context of the current task. / portSAVE_CONTEXT(); / Find the highest priority task that is ready to run. / __asm volatile( "bl vTaskSwitchContext" ); / Restore the context of the new task. / portRESTORE_CONTEXT(); } /-----------------------------------------------------------/ / * The ISR used for the scheduler tick depends on whether the cooperative or * the preemptive scheduler is being used. / #if configUSE_PREEMPTION == 0 / The cooperative scheduler requires a normal IRQ service routine to simply increment the system tick. / void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); void vNonPreemptiveTick( void ) { vTaskIncrementTick(); T0IR = 2; VICVectAddr = portCLEAR_VIC_INTERRUPT; } #else / The preemptive scheduler is defined as "naked" as the full context is saved on entry as part of the context switch. / void vPreemptiveTick( void ) __attribute__((naked)); void vPreemptiveTick( void ) { / Save the context of the interrupted task. / portSAVE_CONTEXT(); / Increment the RTOS tick count, then look for the highest priority task that is ready to run. / __asm volatile( "bl vTaskIncrementTick" ); __asm volatile( "bl vTaskSwitchContext" ); / Ready for the next interrupt. / T0IR = 2; VICVectAddr = portCLEAR_VIC_INTERRUPT; / Restore the context of the new task. / portRESTORE_CONTEXT(); } #endif /-----------------------------------------------------------/ / * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions here to * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then * the utilities are defined as macros in portmacro.h - as per other ports. / #ifdef THUMB_INTERWORK void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); void vPortDisableInterruptsFromThumb( void ) { __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0} \n\t" / Pop R0. / "BX R14" ); / Return back to thumb. / } void vPortEnableInterruptsFromThumb( void ) { __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0} \n\t" / Pop R0. / "BX R14" ); / Return back to thumb. / } #endif / THUMB_INTERWORK / / The code generated by the GCC compiler uses the stack in different ways at different optimisation levels. The interrupt flags can therefore not always be saved to the stack. Instead the critical section nesting level is stored in a variable, which is then saved as part of the stack context. / void vPortEnterCritical( void ) { / Disable interrupts as per portDISABLE_INTERRUPTS(); / __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0}" ); / Pop R0. / / Now interrupts are disabled ulCriticalNesting can be accessed directly. Increment ulCriticalNesting to keep a count of how many times portENTER_CRITICAL() has been called. / ulCriticalNesting++; } void vPortExitCritical( void ) { if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { / Decrement the nesting count as we are leaving a critical section. / ulCriticalNesting--; / If the nesting level has reached zero then interrupts should be re-enabled. / if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { / Enable interrupts as per portEXIT_CRITICAL(). / __asm volatile ( "STMDB SP!, {R0} \n\t" / Push R0. / "MRS R0, CPSR \n\t" / Get CPSR. / "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / "MSR CPSR, R0 \n\t" / Write back modified value. / "LDMIA SP!, {R0}" ); / Pop R0. */ } } }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_LPC23xx/portISR.c	C	oos	9,560
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Changes from V3.2.3 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. Changes from V3.2.4 + Removed the use of the %0 parameter within the assembler macros and replaced them with hard coded registers. This will ensure the assembler does not select the link register as the temp register as was occasionally happening previously. + The assembler statements are now included in a single asm block rather than each line having its own asm block. Changes from V4.5.0 + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros and replaced them with portYIELD_FROM_ISR() macro. Application code should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() macros as per the V4.5.1 demo code. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE portLONG #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Architecture specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 8 #define portNOP() __asm volatile ( "NOP" ); /-----------------------------------------------------------/ / Scheduler utilities. / / * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but * are included here for efficiency. An attempt to call one from * THUMB mode code will result in a compile time error. / #define portRESTORE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Set the LR to the task stack. / \ __asm volatile ( \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "LDR LR, [R0] \n\t" \ \ / The critical nesting depth is the first item on the stack. / \ / Load it into the ulCriticalNesting variable. / \ "LDR R0, =ulCriticalNesting \n\t" \ "LDMFD LR!, {R1} \n\t" \ "STR R1, [R0] \n\t" \ \ / Get the SPSR from the stack. / \ "LDMFD LR!, {R0} \n\t" \ "MSR SPSR, R0 \n\t" \ \ / Restore all system mode registers for the task. / \ "LDMFD LR, {R0-R14}^ \n\t" \ "NOP \n\t" \ \ / Restore the return address. / \ "LDR LR, [LR, #+60] \n\t" \ \ / And return - correcting the offset in the LR to obtain the / \ / correct address. / \ "SUBS PC, LR, #4 \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } /-----------------------------------------------------------/ #define portSAVE_CONTEXT() \ { \ extern volatile void volatile pxCurrentTCB; \ extern volatile unsigned portLONG ulCriticalNesting; \ \ /* Push R0 as we are going to use the register. / \ __asm volatile ( \ "STMDB SP!, {R0} \n\t" \ \ / Set R0 to point to the task stack pointer. / \ "STMDB SP,{SP}^ \n\t" \ "NOP \n\t" \ "SUB SP, SP, #4 \n\t" \ "LDMIA SP!,{R0} \n\t" \ \ / Push the return address onto the stack. / \ "STMDB R0!, {LR} \n\t" \ \ / Now we have saved LR we can use it instead of R0. / \ "MOV LR, R0 \n\t" \ \ / Pop R0 so we can save it onto the system mode stack. / \ "LDMIA SP!, {R0} \n\t" \ \ / Push all the system mode registers onto the task stack. / \ "STMDB LR,{R0-LR}^ \n\t" \ "NOP \n\t" \ "SUB LR, LR, #60 \n\t" \ \ / Push the SPSR onto the task stack. / \ "MRS R0, SPSR \n\t" \ "STMDB LR!, {R0} \n\t" \ \ "LDR R0, =ulCriticalNesting \n\t" \ "LDR R0, [R0] \n\t" \ "STMDB LR!, {R0} \n\t" \ \ / Store the new top of stack for the task. / \ "LDR R0, =pxCurrentTCB \n\t" \ "LDR R0, [R0] \n\t" \ "STR LR, [R0] \n\t" \ ); \ ( void ) ulCriticalNesting; \ ( void ) pxCurrentTCB; \ } #define portYIELD_FROM_ISR() vTaskSwitchContext() #define portYIELD() __asm volatile ( "SWI 0" ) /-----------------------------------------------------------/ / Critical section management. / / * The interrupt management utilities can only be called from ARM mode. When * THUMB_INTERWORK is defined the utilities are defined as functions in * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not * defined then the utilities are defined as macros here - as per other ports. / #ifdef THUMB_INTERWORK extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() #else #define portDISABLE_INTERRUPTS() \ __asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "ORR R0, R0, #0xC0 \n\t" / Disable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #define portENABLE_INTERRUPTS() \ __asm volatile ( \ "STMDB SP!, {R0} \n\t" / Push R0. / \ "MRS R0, CPSR \n\t" / Get CPSR. / \ "BIC R0, R0, #0xC0 \n\t" / Enable IRQ, FIQ. / \ "MSR CPSR, R0 \n\t" / Write back modified value. / \ "LDMIA SP!, {R0} " ) / Pop R0. / #endif / THUMB_INTERWORK / extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical(); #define portEXIT_CRITICAL() vPortExitCritical(); /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_LPC23xx/portmacro.h	C	oos	10,522
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the ARM7 port. * * Components that can be compiled to either ARM or THUMB mode are * contained in this file. The ISR routines, which can only be compiled * to ARM mode are contained in portISR.c. ----------------------------------------------------------/ /* Standard includes. / #include <stdlib.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Constants required to setup the task context. / #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) / System mode, ARM mode, interrupts enabled. / #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) #define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) / Constants required to setup the tick ISR. / #define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) #define portPRESCALE_VALUE 0x00 #define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) #define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) / Constants required to setup the VIC for the tick ISR. / #define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) #define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) #define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) /-----------------------------------------------------------/ / Setup the timer to generate the tick interrupts. / static void prvSetupTimerInterrupt( void ); / * The scheduler can only be started from ARM mode, so * vPortISRStartFirstSTask() is defined in portISR.c. / extern void vPortISRStartFirstTask( void ); /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been called. * * See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { portSTACK_TYPE pxOriginalTOS; pxOriginalTOS = pxTopOfStack; / To ensure asserts in tasks.c don't fail, although in this case the assert is not really required. / pxTopOfStack--; / Setup the initial stack of the task. The stack is set exactly as expected by the portRESTORE_CONTEXT() macro. / / First on the stack is the return address - which in this case is the start of the task. The offset is added to make the return address appear as it would within an IRQ ISR. / pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; / R14 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 / pxTopOfStack--; / When the task starts is will expect to find the function parameter in R0. / pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 / pxTopOfStack--; / The last thing onto the stack is the status register, which is set for system mode, with interrupts enabled. / pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00 ) { /* We want the task to start in thumb mode. / pxTopOfStack \|= portTHUMB_MODE_BIT; } pxTopOfStack--; /* Some optimisation levels use the stack differently to others. This means the interrupt flags cannot always be stored on the stack and will instead be stored in a variable, which is then saved as part of the tasks context. / pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { /* Start the timer that generates the tick ISR. Interrupts are disabled here already. / prvSetupTimerInterrupt(); / Start the first task. / vPortISRStartFirstTask(); / Should not get here! / return 0; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the ARM port will require this function as there is nothing to return to. / } /-----------------------------------------------------------/ / * Setup the timer 0 to generate the tick interrupts at the required frequency. / static void prvSetupTimerInterrupt( void ) { unsigned portLONG ulCompareMatch; PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) \| (0x01 << 2); T0TCR = 2; / Stop and reset the timer / T0CTCR = 0; / Timer mode / / A 1ms tick does not require the use of the timer prescale. This is defaulted to zero but can be used if necessary. / T0PR = portPRESCALE_VALUE; / Calculate the match value required for our wanted tick rate. / ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; / Protect against divide by zero. Using an if() statement still results in a warning - hence the #if. / #if portPRESCALE_VALUE != 0 { ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); } #endif T0MR1 = ulCompareMatch; / Generate tick with timer 0 compare match. / T0MCR = (3 << 3); / Reset timer on match and generate interrupt / / Setup the VIC for the timer. / VICIntEnable = 0x00000010; / The ISR installed depends on whether the preemptive or cooperative scheduler is being used. / #if configUSE_PREEMPTION == 1 { extern void ( vPreemptiveTick )( void ); VICVectAddr4 = ( portLONG ) vPreemptiveTick; } #else { extern void ( vNonPreemptiveTick )( void ); VICVectAddr4 = ( portLONG ) vNonPreemptiveTick; } #endif VICVectCntl4 = 1; / Start the timer - interrupts are disabled when this function is called so it is okay to do this here. / T0TCR = portENABLE_TIMER; } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ARM7_LPC23xx/port.c	C	oos	9,921
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Changes from V1.2.3 + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it base 16. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT int #define portSTACK_TYPE unsigned portCHAR #define portBASE_TYPE char #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Critical section management. / #define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \ asm volatile ( "cli" :: ); \ asm volatile ( "push __tmp_reg__" :: ) #define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \ asm volatile ( "out __SREG__, __tmp_reg__" :: ) #define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: ); #define portENABLE_INTERRUPTS() asm volatile ( "sei" :: ); /-----------------------------------------------------------/ / Architecture specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 1 #define portNOP() asm volatile ( "nop" ); /-----------------------------------------------------------/ / Kernel utilities. / extern void vPortYield( void ) __attribute__ ( ( naked ) ); #define portYIELD() vPortYield() /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ATMega323/portmacro.h	C	oos	5,359
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Changes from V2.6.0 + AVR port - Replaced the inb() and outb() functions with direct memory access. This allows the port to be built with the 20050414 build of WinAVR. / #include <stdlib.h> #include <avr/interrupt.h> #include "FreeRTOS.h" #include "task.h" /----------------------------------------------------------- * Implementation of functions defined in portable.h for the AVR port. ----------------------------------------------------------/ /* Start tasks with interrupts enables. / #define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 ) / Hardware constants for timer 1. / #define portCLEAR_COUNTER_ON_MATCH ( ( unsigned char ) 0x08 ) #define portPRESCALE_64 ( ( unsigned char ) 0x03 ) #define portCLOCK_PRESCALER ( ( unsigned long ) 64 ) #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned char ) 0x10 ) /-----------------------------------------------------------/ / We require the address of the pxCurrentTCB variable, but don't want to know any details of its type. / typedef void tskTCB; extern volatile tskTCB volatile pxCurrentTCB; /-----------------------------------------------------------/ /* * Macro to save all the general purpose registers, the save the stack pointer * into the TCB. * * The first thing we do is save the flags then disable interrupts. This is to * guard our stack against having a context switch interrupt after we have already * pushed the registers onto the stack - causing the 32 registers to be on the * stack twice. * * r1 is set to zero as the compiler expects it to be thus, however some * of the math routines make use of R1. * * The interrupts will have been disabled during the call to portSAVE_CONTEXT() * so we need not worry about reading/writing to the stack pointer. / #define portSAVE_CONTEXT() \ asm volatile ( "push r0 \n\t" \ "in r0, __SREG__ \n\t" \ "cli \n\t" \ "push r0 \n\t" \ "push r1 \n\t" \ "clr r1 \n\t" \ "push r2 \n\t" \ "push r3 \n\t" \ "push r4 \n\t" \ "push r5 \n\t" \ "push r6 \n\t" \ "push r7 \n\t" \ "push r8 \n\t" \ "push r9 \n\t" \ "push r10 \n\t" \ "push r11 \n\t" \ "push r12 \n\t" \ "push r13 \n\t" \ "push r14 \n\t" \ "push r15 \n\t" \ "push r16 \n\t" \ "push r17 \n\t" \ "push r18 \n\t" \ "push r19 \n\t" \ "push r20 \n\t" \ "push r21 \n\t" \ "push r22 \n\t" \ "push r23 \n\t" \ "push r24 \n\t" \ "push r25 \n\t" \ "push r26 \n\t" \ "push r27 \n\t" \ "push r28 \n\t" \ "push r29 \n\t" \ "push r30 \n\t" \ "push r31 \n\t" \ "lds r26, pxCurrentTCB \n\t" \ "lds r27, pxCurrentTCB + 1 \n\t" \ "in r0, 0x3d \n\t" \ "st x+, r0 \n\t" \ "in r0, 0x3e \n\t" \ "st x+, r0 \n\t" \ ); / * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during * the context save so we can write to the stack pointer. / #define portRESTORE_CONTEXT() \ asm volatile ( "lds r26, pxCurrentTCB \n\t" \ "lds r27, pxCurrentTCB + 1 \n\t" \ "ld r28, x+ \n\t" \ "out __SP_L__, r28 \n\t" \ "ld r29, x+ \n\t" \ "out __SP_H__, r29 \n\t" \ "pop r31 \n\t" \ "pop r30 \n\t" \ "pop r29 \n\t" \ "pop r28 \n\t" \ "pop r27 \n\t" \ "pop r26 \n\t" \ "pop r25 \n\t" \ "pop r24 \n\t" \ "pop r23 \n\t" \ "pop r22 \n\t" \ "pop r21 \n\t" \ "pop r20 \n\t" \ "pop r19 \n\t" \ "pop r18 \n\t" \ "pop r17 \n\t" \ "pop r16 \n\t" \ "pop r15 \n\t" \ "pop r14 \n\t" \ "pop r13 \n\t" \ "pop r12 \n\t" \ "pop r11 \n\t" \ "pop r10 \n\t" \ "pop r9 \n\t" \ "pop r8 \n\t" \ "pop r7 \n\t" \ "pop r6 \n\t" \ "pop r5 \n\t" \ "pop r4 \n\t" \ "pop r3 \n\t" \ "pop r2 \n\t" \ "pop r1 \n\t" \ "pop r0 \n\t" \ "out __SREG__, r0 \n\t" \ "pop r0 \n\t" \ ); /-----------------------------------------------------------/ / * Perform hardware setup to enable ticks from timer 1, compare match A. / static void prvSetupTimerInterrupt( void ); /-----------------------------------------------------------/ / * See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { unsigned short usAddress; /* Place a few bytes of known values on the bottom of the stack. This is just useful for debugging. / pxTopOfStack = 0x11; pxTopOfStack--; pxTopOfStack = 0x22; pxTopOfStack--; pxTopOfStack = 0x33; pxTopOfStack--; /* Simulate how the stack would look after a call to vPortYield() generated by the compiler. / /lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. / / The start of the task code will be popped off the stack last, so place it on first. / usAddress = ( unsigned short ) pxCode; pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned short ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned short ) 0x00ff ); pxTopOfStack--; / Next simulate the stack as if after a call to portSAVE_CONTEXT(). portSAVE_CONTEXT places the flags on the stack immediately after r0 to ensure the interrupts get disabled as soon as possible, and so ensuring the stack use is minimal should a context switch interrupt occur. / pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 / pxTopOfStack--; pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; /* Now the remaining registers. The compiler expects R1 to be 0. / pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R1 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R16 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R17 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 / pxTopOfStack--; / Place the parameter on the stack in the expected location. / usAddress = ( unsigned short ) pvParameters; pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned short ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned short ) 0x00ff ); pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x28; /* R28 Y / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x29; /* R29 / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 / pxTopOfStack--; /lint +e950 +e611 +e923 / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { / Setup the hardware to generate the tick. / prvSetupTimerInterrupt(); / Restore the context of the first task that is going to run. / portRESTORE_CONTEXT(); / Simulate a function call end as generated by the compiler. We will now jump to the start of the task the context of which we have just restored. / asm volatile ( "ret" ); / Should not get here. / return pdTRUE; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the AVR port will get stopped. If required simply disable the tick interrupt here. / } /-----------------------------------------------------------/ / * Manual context switch. The first thing we do is save the registers so we * can use a naked attribute. / void vPortYield( void ) __attribute__ ( ( naked ) ); void vPortYield( void ) { portSAVE_CONTEXT(); vTaskSwitchContext(); portRESTORE_CONTEXT(); asm volatile ( "ret" ); } /-----------------------------------------------------------/ / * Context switch function used by the tick. This must be identical to * vPortYield() from the call to vTaskSwitchContext() onwards. The only * difference from vPortYield() is the tick count is incremented as the * call comes from the tick ISR. / void vPortYieldFromTick( void ) __attribute__ ( ( naked ) ); void vPortYieldFromTick( void ) { portSAVE_CONTEXT(); vTaskIncrementTick(); vTaskSwitchContext(); portRESTORE_CONTEXT(); asm volatile ( "ret" ); } /-----------------------------------------------------------/ / * Setup timer 1 compare match A to generate a tick interrupt. / static void prvSetupTimerInterrupt( void ) { unsigned long ulCompareMatch; unsigned char ucHighByte, ucLowByte; / Using 16bit timer 1 to generate the tick. Correct fuses must be selected for the configCPU_CLOCK_HZ clock. / ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; / We only have 16 bits so have to scale to get our required tick rate. / ulCompareMatch /= portCLOCK_PRESCALER; / Adjust for correct value. / ulCompareMatch -= ( unsigned long ) 1; / Setup compare match value for compare match A. Interrupts are disabled before this is called so we need not worry here. / ucLowByte = ( unsigned char ) ( ulCompareMatch & ( unsigned long ) 0xff ); ulCompareMatch >>= 8; ucHighByte = ( unsigned char ) ( ulCompareMatch & ( unsigned long ) 0xff ); OCR1AH = ucHighByte; OCR1AL = ucLowByte; / Setup clock source and compare match behaviour. / ucLowByte = portCLEAR_COUNTER_ON_MATCH \| portPRESCALE_64; TCCR1B = ucLowByte; / Enable the interrupt - this is okay as interrupt are currently globally disabled. / ucLowByte = TIMSK; ucLowByte \|= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; TIMSK = ucLowByte; } /-----------------------------------------------------------/ #if configUSE_PREEMPTION == 1 / * Tick ISR for preemptive scheduler. We can use a naked attribute as * the context is saved at the start of vPortYieldFromTick(). The tick * count is incremented after the context is saved. / void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) ); void SIG_OUTPUT_COMPARE1A( void ) { vPortYieldFromTick(); asm volatile ( "reti" ); } #else / * Tick ISR for the cooperative scheduler. All this does is increment the * tick count. We don't need to switch context, this can only be done by * manual calls to taskYIELD(); */ void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) ); void SIG_OUTPUT_COMPARE1A( void ) { vTaskIncrementTick(); } #endif	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/ATMega323/port.c	C	oos	15,518
/This file has been prepared for Doxygen automatic documentation generation./ /! \file ******************************************************************** * * \brief FreeRTOS port source for AVR32 UC3. * * - Compiler: GNU GCC for AVR32 * - Supported devices: All AVR32 devices can be used. * - AppNote: * * \author Atmel Corporation: http://www.atmel.com \n * Support and FAQ: http://support.atmel.no/ * ****************************************************************************/ / FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / #include <avr32/io.h> #include "intc.h" #include "compiler.h" #ifdef __cplusplus extern "C" { #endif /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE portLONG #define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS ) #define TASK_DELAY_S(x) ( (x)1000 /portTICK_RATE_MS ) #define TASK_DELAY_MIN(x) ( (x)601000/portTICK_RATE_MS ) #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ /* Architecture specifics. / #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 4 #define portNOP() {__asm__ __volatile__ ("nop");} /-----------------------------------------------------------/ /-----------------------------------------------------------/ / INTC-specific. / #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) / * Debug trace. * Activated if and only if configDBG is nonzero. * Prints a formatted string to stdout. * The current source file name and line number are output with a colon before * the formatted string. * A carriage return and a linefeed are appended to the output. * stdout is redirected to the USART configured by configDBG_USART. * The parameters are the same as for the standard printf function. * There is no return value. * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. / #if configDBG #define portDBG_TRACE(...) \ {\ fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\ printf(__VA_ARGS__);\ fputs("\r\n", stdout);\ } #else #define portDBG_TRACE(...) #endif / Critical section management. / #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical(); #define portEXIT_CRITICAL() vPortExitCritical(); / Added as there is no such function in FreeRTOS. / extern void pvPortRealloc( void pv, size_t xSize ); /-----------------------------------------------------------/ /=============================================================================================/ / * Restore Context for cases other than INTi. / #define portRESTORE_CONTEXT() \ { \ extern volatile unsigned portLONG ulCriticalNesting; \ extern volatile void volatile pxCurrentTCB; \ \ __asm__ __volatile__ ( \ /* Set SP to point to new stack / \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\ "orh r8, HI(%[pxCurrentTCB]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "ld.w sp, r0[0] \n\t"\ \ / Restore ulCriticalNesting variable / \ "ld.w r0, sp++ \n\t"\ "mov r8, LO(%[ulCriticalNesting]) \n\t"\ "orh r8, HI(%[ulCriticalNesting]) \n\t"\ "st.w r8[0], r0 \n\t"\ \ / Restore R0..R7 / \ "ldm sp++, r0-r7 \n\t"\ / R0-R7 should not be used below this line / \ / Skip PC and SR (will do it at the end) / \ "sub sp, -24 \n\t"\ /* Restore R8..R12 and LR / \ "ldm sp++, r8-r12, lr \n\t"\ / Restore SR / \ "ld.w r0, sp[-84]\n\t" /* R0 is modified, is restored later. / \ "mtsr %[SR], r0 \n\t"\ / Restore r0 / \ "ld.w r0, sp[-94] \n\t"\ /* Restore PC / \ "ld.w pc, sp[-74]" /* Get PC from stack - PC is the 7th register saved / \ : \ : [ulCriticalNesting] "i" (&ulCriticalNesting), \ [pxCurrentTCB] "i" (&pxCurrentTCB), \ [SR] "i" (AVR32_SR) \ ); \ } / * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. * * Had to make different versions because registers saved on the system stack * are not the same between INT0..3 exceptions and the scall exception. / // Task context stack layout: // R8 () // R9 () // R10 () // R11 () // R12 () // R14/LR () // R15/PC () // SR () // R0 // R1 // R2 // R3 // R4 // R5 // R6 // R7 // ulCriticalNesting // () automatically done for INT0..INT3, but not for SCALL /* * The ISR used for the scheduler tick depends on whether the cooperative or * the preemptive scheduler is being used. / #if configUSE_PREEMPTION == 0 / * portSAVE_CONTEXT_OS_INT() for OS Tick exception. / #define portSAVE_CONTEXT_OS_INT() \ { \ / Save R0..R7 / \ __asm__ __volatile__ ("stm --sp, r0-r7"); \ \ / With the cooperative scheduler, as there is no context switch by interrupt, / \ / there is also no context save. / \ } / * portRESTORE_CONTEXT_OS_INT() for Tick exception. / #define portRESTORE_CONTEXT_OS_INT() \ { \ __asm__ __volatile__ ( \ / Restore R0..R7 / \ "ldm sp++, r0-r7\n\t" \ \ / With the cooperative scheduler, as there is no context switch by interrupt, / \ / there is also no context restore. / \ "rete" \ ); \ } #else / * portSAVE_CONTEXT_OS_INT() for OS Tick exception. / #define portSAVE_CONTEXT_OS_INT() \ { \ extern volatile unsigned portLONG ulCriticalNesting; \ extern volatile void volatile pxCurrentTCB; \ \ /* When we come here / \ / Registers R8..R12, LR, PC and SR had already been pushed to system stack / \ \ __asm__ __volatile__ ( \ / Save R0..R7 / \ "stm --sp, r0-r7 \n\t"\ \ / Save ulCriticalNesting variable - R0 is overwritten / \ "mov r8, LO(%[ulCriticalNesting])\n\t" \ "orh r8, HI(%[ulCriticalNesting])\n\t" \ "ld.w r0, r8[0] \n\t"\ "st.w --sp, r0 \n\t"\ \ / Check if INT0 or higher were being handled (case where the OS tick interrupted another / \ / interrupt handler (which was of a higher priority level but decided to lower its priority / \ / level and allow other lower interrupt level to occur). / \ / In this case we don't want to do a task switch because we don't know what the stack / \ / currently looks like (we don't know what the interrupted interrupt handler was doing). / \ / Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) / \ / will just be restoring the interrupt handler, no way!!! / \ / So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. / \ "ld.w r0, sp[94]\n\t" /* Read SR in stack / \ "bfextu r0, r0, 22, 3\n\t" / Extract the mode bits to R0. / \ "cp.w r0, 1\n\t" / Compare the mode bits with supervisor mode(b'001) / \ "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ \ / Store SP in the first member of the structure pointed to by pxCurrentTCB / \ / NOTE: we don't enter a critical section here because all interrupt handlers / \ / MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as / \ / portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. / \ / => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. / \ "mov r8, LO(%[pxCurrentTCB])\n\t" \ "orh r8, HI(%[pxCurrentTCB])\n\t" \ "ld.w r0, r8[0]\n\t" \ "st.w r0[0], sp\n" \ \ "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \ : \ : [ulCriticalNesting] "i" (&ulCriticalNesting), \ [pxCurrentTCB] "i" (&pxCurrentTCB), \ [LINE] "i" (__LINE__) \ ); \ } / * portRESTORE_CONTEXT_OS_INT() for Tick exception. / #define portRESTORE_CONTEXT_OS_INT() \ { \ extern volatile unsigned portLONG ulCriticalNesting; \ extern volatile void volatile pxCurrentTCB; \ \ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another / \ / interrupt handler (which was of a higher priority level but decided to lower its priority / \ / level and allow other lower interrupt level to occur). / \ / In this case we don't want to do a task switch because we don't know what the stack / \ / currently looks like (we don't know what the interrupted interrupt handler was doing). / \ / Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) / \ / will just be restoring the interrupt handler, no way!!! / \ __asm__ __volatile__ ( \ "ld.w r0, sp[94]\n\t" /* Read SR in stack / \ "bfextu r0, r0, 22, 3\n\t" / Extract the mode bits to R0. / \ "cp.w r0, 1\n\t" / Compare the mode bits with supervisor mode(b'001) / \ "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \ : \ : [LINE] "i" (__LINE__) \ ); \ \ / Else / \ / because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. / \ / A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. /\ portENTER_CRITICAL(); \ vTaskSwitchContext(); \ portEXIT_CRITICAL(); \ \ / Restore all registers / \ \ __asm__ __volatile__ ( \ / Set SP to point to new stack / \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\ "orh r8, HI(%[pxCurrentTCB]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "ld.w sp, r0[0] \n"\ \ "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ \ / Restore ulCriticalNesting variable / \ "ld.w r0, sp++ \n\t" \ "mov r8, LO(%[ulCriticalNesting]) \n\t"\ "orh r8, HI(%[ulCriticalNesting]) \n\t"\ "st.w r8[0], r0 \n\t"\ \ / Restore R0..R7 / \ "ldm sp++, r0-r7 \n\t"\ \ / Now, the stack should be R8..R12, LR, PC and SR / \ "rete" \ : \ : [ulCriticalNesting] "i" (&ulCriticalNesting), \ [pxCurrentTCB] "i" (&pxCurrentTCB), \ [LINE] "i" (__LINE__) \ ); \ } #endif / * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. * * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. * / #define portSAVE_CONTEXT_SCALL() \ { \ extern volatile unsigned portLONG ulCriticalNesting; \ extern volatile void volatile pxCurrentTCB; \ \ /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. / \ / If SR[M2:M0] == 001 / \ / PC and SR are on the stack. / \ / Else (other modes) / \ / Nothing on the stack. / \ \ / WARNING NOTE: the else case cannot happen as it is strictly forbidden to call / \ / vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) / \ / in an interrupt\|exception handler. / \ \ __asm__ __volatile__ ( \ / in order to save R0-R7 / \ "sub sp, 64 \n\t"\ /* Save R0..R7 / \ "stm --sp, r0-r7 \n\t"\ \ / in order to save R8-R12 and LR / \ / do not use SP if interrupts occurs, SP must be left at bottom of stack / \ "sub r7, sp,-164 \n\t"\ /* Copy PC and SR in other places in the stack. / \ "ld.w r0, r7[-24] \n\t" /* Read SR /\ "st.w r7[-84], r0 \n\t" /* Copy SR /\ "ld.w r0, r7[-14] \n\t" /* Read PC /\ "st.w r7[-74], r0 \n\t" /* Copy PC /\ \ / Save R8..R12 and LR on the stack. / \ "stm --r7, r8-r12, lr \n\t"\ \ / Arriving here we have the following stack organizations: / \ / R8..R12, LR, PC, SR, R0..R7. / \ \ / Now we can finalize the save. / \ \ / Save ulCriticalNesting variable - R0 is overwritten / \ "mov r8, LO(%[ulCriticalNesting]) \n\t"\ "orh r8, HI(%[ulCriticalNesting]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "st.w --sp, r0" \ : \ : [ulCriticalNesting] "i" (&ulCriticalNesting) \ ); \ \ / Disable the its which may cause a context switch (i.e. cause a change of / \ / pxCurrentTCB). / \ / Basically, all accesses to the pxCurrentTCB structure should be put in a / \ / critical section because it is a global structure. / \ portENTER_CRITICAL(); \ \ / Store SP in the first member of the structure pointed to by pxCurrentTCB / \ __asm__ __volatile__ ( \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\ "orh r8, HI(%[pxCurrentTCB]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "st.w r0[0], sp" \ : \ : [pxCurrentTCB] "i" (&pxCurrentTCB) \ ); \ } / * portRESTORE_CONTEXT() for SupervisorCALL exception. / #define portRESTORE_CONTEXT_SCALL() \ { \ extern volatile unsigned portLONG ulCriticalNesting; \ extern volatile void volatile pxCurrentTCB; \ \ /* Restore all registers / \ \ / Set SP to point to new stack / \ __asm__ __volatile__ ( \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\ "orh r8, HI(%[pxCurrentTCB]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "ld.w sp, r0[0]" \ : \ : [pxCurrentTCB] "i" (&pxCurrentTCB) \ ); \ \ / Leave pxCurrentTCB variable access critical section / \ portEXIT_CRITICAL(); \ \ __asm__ __volatile__ ( \ / Restore ulCriticalNesting variable / \ "ld.w r0, sp++ \n\t"\ "mov r8, LO(%[ulCriticalNesting]) \n\t"\ "orh r8, HI(%[ulCriticalNesting]) \n\t"\ "st.w r8[0], r0 \n\t"\ \ / skip PC and SR / \ / do not use SP if interrupts occurs, SP must be left at bottom of stack / \ "sub r7, sp, -104 \n\t"\ /* Restore r8-r12 and LR / \ "ldm r7++, r8-r12, lr \n\t"\ \ / RETS will take care of the extra PC and SR restore. / \ / So, we have to prepare the stack for this. / \ "ld.w r0, r7[-84] \n\t" /* Read SR /\ "st.w r7[-24], r0 \n\t" /* Copy SR /\ "ld.w r0, r7[-74] \n\t" /* Read PC /\ "st.w r7[-14], r0 \n\t" /* Copy PC /\ \ / Restore R0..R7 / \ "ldm sp++, r0-r7 \n\t"\ \ "sub sp, -64 \n\t"\ \ "rets" \ : \ : [ulCriticalNesting] "i" (&ulCriticalNesting) \ ); \ } /* * The ISR used depends on whether the cooperative or * the preemptive scheduler is being used. / #if configUSE_PREEMPTION == 0 / * ISR entry and exit macros. These are only required if a task switch * is required from the ISR. / #define portENTER_SWITCHING_ISR() \ { \ / Save R0..R7 / \ __asm__ __volatile__ ("stm --sp, r0-r7"); \ \ / With the cooperative scheduler, as there is no context switch by interrupt, / \ / there is also no context save. / \ } / * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 / #define portEXIT_SWITCHING_ISR() \ { \ __asm__ __volatile__ ( \ / Restore R0..R7 / \ "ldm sp++, r0-r7 \n\t"\ \ / With the cooperative scheduler, as there is no context switch by interrupt, / \ / there is also no context restore. / \ "rete" \ ); \ } #else / * ISR entry and exit macros. These are only required if a task switch * is required from the ISR. / #define portENTER_SWITCHING_ISR() \ { \ extern volatile unsigned portLONG ulCriticalNesting; \ extern volatile void volatile pxCurrentTCB; \ \ /* When we come here / \ / Registers R8..R12, LR, PC and SR had already been pushed to system stack / \ \ __asm__ __volatile__ ( \ / Save R0..R7 / \ "stm --sp, r0-r7 \n\t"\ \ / Save ulCriticalNesting variable - R0 is overwritten / \ "mov r8, LO(%[ulCriticalNesting]) \n\t"\ "orh r8, HI(%[ulCriticalNesting]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "st.w --sp, r0 \n\t"\ \ / Check if INT0 or higher were being handled (case where the OS tick interrupted another / \ / interrupt handler (which was of a higher priority level but decided to lower its priority / \ / level and allow other lower interrupt level to occur). / \ / In this case we don't want to do a task switch because we don't know what the stack / \ / currently looks like (we don't know what the interrupted interrupt handler was doing). / \ / Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) / \ / will just be restoring the interrupt handler, no way!!! / \ / So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. / \ "ld.w r0, sp[94] \n\t" /* Read SR in stack /\ "bfextu r0, r0, 22, 3 \n\t" / Extract the mode bits to R0. /\ "cp.w r0, 1 \n\t" / Compare the mode bits with supervisor mode(b'001) /\ "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ \ / Store SP in the first member of the structure pointed to by pxCurrentTCB / \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\ "orh r8, HI(%[pxCurrentTCB]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "st.w r0[0], sp \n"\ \ "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ : \ : [ulCriticalNesting] "i" (&ulCriticalNesting), \ [pxCurrentTCB] "i" (&pxCurrentTCB), \ [LINE] "i" (__LINE__) \ ); \ } / * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 / #define portEXIT_SWITCHING_ISR() \ { \ extern volatile unsigned portLONG ulCriticalNesting; \ extern volatile void volatile pxCurrentTCB; \ \ __asm__ __volatile__ ( \ /* Check if INT0 or higher were being handled (case where the OS tick interrupted another / \ / interrupt handler (which was of a higher priority level but decided to lower its priority / \ / level and allow other lower interrupt level to occur). / \ / In this case it's of no use to switch context and restore a new SP because we purposedly / \ / did not previously save SP in its TCB. / \ "ld.w r0, sp[94] \n\t" /* Read SR in stack /\ "bfextu r0, r0, 22, 3 \n\t" / Extract the mode bits to R0. /\ "cp.w r0, 1 \n\t" / Compare the mode bits with supervisor mode(b'001) /\ "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\ \ / If a switch is required then we just need to call / \ / vTaskSwitchContext() as the context has already been / \ / saved. / \ "cp.w r12, 1 \n\t" / Check if Switch context is required. /\ "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ : \ : [LINE] "i" (__LINE__) \ ); \ \ / A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. / \ portENTER_CRITICAL(); \ vTaskSwitchContext(); \ portEXIT_CRITICAL(); \ \ __asm__ __volatile__ ( \ "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\ / Restore the context of which ever task is now the highest / \ / priority that is ready to run. / \ \ / Restore all registers / \ \ / Set SP to point to new stack / \ "mov r8, LO(%[pxCurrentTCB]) \n\t"\ "orh r8, HI(%[pxCurrentTCB]) \n\t"\ "ld.w r0, r8[0] \n\t"\ "ld.w sp, r0[0] \n"\ \ "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ \ / Restore ulCriticalNesting variable / \ "ld.w r0, sp++ \n\t"\ "mov r8, LO(%[ulCriticalNesting]) \n\t"\ "orh r8, HI(%[ulCriticalNesting]) \n\t"\ "st.w r8[0], r0 \n\t"\ \ / Restore R0..R7 / \ "ldm sp++, r0-r7 \n\t"\ \ / Now, the stack should be R8..R12, LR, PC and SR / \ "rete" \ : \ : [ulCriticalNesting] "i" (&ulCriticalNesting), \ [pxCurrentTCB] "i" (&pxCurrentTCB), \ [LINE] "i" (__LINE__) \ ); \ } #endif #define portYIELD() {__asm__ __volatile__ ("scall");} / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/AVR32_UC3/portmacro.h	C	oos	30,359
/This file is prepared for Doxygen automatic documentation generation./ /! \file ******************************************************************** * * \brief Exception and interrupt vectors. * * This file maps all events supported by an AVR32UC. * * - Compiler: GNU GCC for AVR32 * - Supported devices: All AVR32UC devices with an INTC module can be used. * - AppNote: * * \author Atmel Corporation: http://www.atmel.com \n * Support and FAQ: http://support.atmel.no/ * *****************************************************************************/ / Copyright (c) 2007, Atmel Corporation All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. The name of ATMEL may not be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. / #include <avr32/io.h> #include "intc.h" //! @{ //! \verbatim .section .exception, "ax", @progbits // Start of Exception Vector Table. // EVBA must be aligned with a power of two strictly greater than the EVBA- // relative offset of the last vector. .balign 0x200 // Export symbol. .global _evba .type _evba, @function _evba: .org 0x000 // Unrecoverable Exception. _handle_Unrecoverable_Exception: rjmp $ .org 0x004 // TLB Multiple Hit: UNUSED IN AVR32UC. _handle_TLB_Multiple_Hit: rjmp $ .org 0x008 // Bus Error Data Fetch. _handle_Bus_Error_Data_Fetch: rjmp $ .org 0x00C // Bus Error Instruction Fetch. _handle_Bus_Error_Instruction_Fetch: rjmp $ .org 0x010 // NMI. _handle_NMI: rjmp $ .org 0x014 // Instruction Address. _handle_Instruction_Address: rjmp $ .org 0x018 // ITLB Protection. _handle_ITLB_Protection: rjmp $ .org 0x01C // Breakpoint. _handle_Breakpoint: rjmp $ .org 0x020 // Illegal Opcode. _handle_Illegal_Opcode: rjmp $ .org 0x024 // Unimplemented Instruction. _handle_Unimplemented_Instruction: rjmp $ .org 0x028 // Privilege Violation. _handle_Privilege_Violation: rjmp $ .org 0x02C // Floating-Point: UNUSED IN AVR32UC. _handle_Floating_Point: rjmp $ .org 0x030 // Coprocessor Absent: UNUSED IN AVR32UC. _handle_Coprocessor_Absent: rjmp $ .org 0x034 // Data Address (Read). _handle_Data_Address_Read: rjmp $ .org 0x038 // Data Address (Write). _handle_Data_Address_Write: rjmp $ .org 0x03C // DTLB Protection (Read). _handle_DTLB_Protection_Read: rjmp $ .org 0x040 // DTLB Protection (Write). _handle_DTLB_Protection_Write: rjmp $ .org 0x044 // DTLB Modified: UNUSED IN AVR32UC. _handle_DTLB_Modified: rjmp $ .org 0x050 // ITLB Miss: UNUSED IN AVR32UC. _handle_ITLB_Miss: rjmp $ .org 0x060 // DTLB Miss (Read): UNUSED IN AVR32UC. _handle_DTLB_Miss_Read: rjmp $ .org 0x070 // DTLB Miss (Write): UNUSED IN AVR32UC. _handle_DTLB_Miss_Write: rjmp $ .org 0x100 // Supervisor Call. _handle_Supervisor_Call: lda.w pc, SCALLYield // Interrupt support. // The interrupt controller must provide the offset address relative to EVBA. // Important note: // All interrupts call a C function named _get_interrupt_handler. // This function will read group and interrupt line number to then return in // R12 a pointer to a user-provided interrupt handler. .balign 4 _int0: // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the // CPU upon interrupt entry. #if 1 // B1832: interrupt stack changed to exception stack if exception is detected. mfsr r12, AVR32_SR bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE cp.w r12, 0b110 brlo _int0_normal lddsp r12, sp[0 4] stdsp sp[6 * 4], r12 lddsp r12, sp[1 * 4] stdsp sp[7 * 4], r12 lddsp r12, sp[3 * 4] sub sp, -6 * 4 rete _int0_normal: #endif mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. call _get_interrupt_handler cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. rete // If this was a spurious interrupt (R12 == NULL), return from event handler. _int1: // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the // CPU upon interrupt entry. #if 1 // B1832: interrupt stack changed to exception stack if exception is detected. mfsr r12, AVR32_SR bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE cp.w r12, 0b110 brlo _int1_normal lddsp r12, sp[0 * 4] stdsp sp[6 * 4], r12 lddsp r12, sp[1 * 4] stdsp sp[7 * 4], r12 lddsp r12, sp[3 * 4] sub sp, -6 * 4 rete _int1_normal: #endif mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. call _get_interrupt_handler cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. rete // If this was a spurious interrupt (R12 == NULL), return from event handler. _int2: // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the // CPU upon interrupt entry. #if 1 // B1832: interrupt stack changed to exception stack if exception is detected. mfsr r12, AVR32_SR bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE cp.w r12, 0b110 brlo _int2_normal lddsp r12, sp[0 * 4] stdsp sp[6 * 4], r12 lddsp r12, sp[1 * 4] stdsp sp[7 * 4], r12 lddsp r12, sp[3 * 4] sub sp, -6 * 4 rete _int2_normal: #endif mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. call _get_interrupt_handler cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. rete // If this was a spurious interrupt (R12 == NULL), return from event handler. _int3: // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the // CPU upon interrupt entry. #if 1 // B1832: interrupt stack changed to exception stack if exception is detected. mfsr r12, AVR32_SR bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE cp.w r12, 0b110 brlo _int3_normal lddsp r12, sp[0 * 4] stdsp sp[6 * 4], r12 lddsp r12, sp[1 * 4] stdsp sp[7 * 4], r12 lddsp r12, sp[3 * 4] sub sp, -6 * 4 rete _int3_normal: #endif mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. call _get_interrupt_handler cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. rete // If this was a spurious interrupt (R12 == NULL), return from event handler. // Constant data area. .balign 4 // Values to store in the interrupt priority registers for the various interrupt priority levels. // The interrupt priority registers contain the interrupt priority level and // the EVBA-relative interrupt vector offset. .global ipr_val .type ipr_val, @object ipr_val: .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) \| (_int0 - _evba),\ (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) \| (_int1 - _evba),\ (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) \| (_int2 - _evba),\ (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) \| (_int3 - _evba) //! \endverbatim //! @}	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/AVR32_UC3/exception.S	Unix Assembly	oos	9,645
/This file has been prepared for Doxygen automatic documentation generation./ /! \file ******************************************************************** * * \brief FreeRTOS port source for AVR32 UC3. * * - Compiler: GNU GCC for AVR32 * - Supported devices: All AVR32 devices can be used. * - AppNote: * * \author Atmel Corporation: http://www.atmel.com \n * Support and FAQ: http://support.atmel.no/ * ****************************************************************************/ / FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / Standard includes. / #include <sys/cpu.h> #include <sys/usart.h> #include <malloc.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / AVR32 UC3 includes. / #include <avr32/io.h> #include "gpio.h" #if( configTICK_USE_TC==1 ) #include "tc.h" #endif / Constants required to setup the task context. / #define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) / AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 / #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 ) / Each task maintains its own critical nesting variable. / #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 ) volatile unsigned long ulCriticalNesting = 9999UL; #if( configTICK_USE_TC==0 ) static void prvScheduleNextTick( void ); #else static void prvClearTcInt( void ); #endif / Setup the timer to generate the tick interrupts. / static void prvSetupTimerInterrupt( void ); /-----------------------------------------------------------/ / * Low-level initialization routine called during startup, before the main * function. * This version comes in replacement to the default one provided by Newlib. * Newlib's _init_startup only calls init_exceptions, but Newlib's exception * vectors are not compatible with the SCALL management in the current FreeRTOS * port. More low-level initializations are besides added here. / void _init_startup(void) { / Import the Exception Vector Base Address. / extern void _evba; #if configHEAP_INIT extern void __heap_start__; extern void __heap_end__; portBASE_TYPE pxMem; #endif /* Load the Exception Vector Base Address in the corresponding system register. / Set_system_register( AVR32_EVBA, ( int ) &_evba ); / Enable exceptions. / ENABLE_ALL_EXCEPTIONS(); / Initialize interrupt handling. / INTC_init_interrupts(); #if configHEAP_INIT / Initialize the heap used by malloc. / for( pxMem = &__heap_start__; pxMem < ( portBASE_TYPE )&__heap_end__; ) { pxMem++ = 0xA5A5A5A5; } #endif / Give the used CPU clock frequency to Newlib, so it can work properly. / set_cpu_hz( configCPU_CLOCK_HZ ); / Code section present if and only if the debug trace is activated. / #if configDBG { static const gpio_map_t DBG_USART_GPIO_MAP = { { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } }; / Initialize the USART used for the debug trace with the configured parameters. / set_usart_base( ( void ) configDBG_USART ); gpio_enable_module( DBG_USART_GPIO_MAP, sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); usart_init( configDBG_USART_BAUDRATE ); } #endif } /-----------------------------------------------------------/ /* * malloc, realloc and free are meant to be called through respectively * pvPortMalloc, pvPortRealloc and vPortFree. * The latter functions call the former ones from within sections where tasks * are suspended, so the latter functions are task-safe. __malloc_lock and * __malloc_unlock use the same mechanism to also keep the former functions * task-safe as they may be called directly from Newlib's functions. * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable * interrupts during memory allocation management as this may be a very time- * consuming process. / / * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a * safe section as memory allocation management uses global data. * See the aforementioned details. / void __malloc_lock(struct _reent ptr) { vTaskSuspendAll(); } /* * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee * a safe section as memory allocation management uses global data. * See the aforementioned details. / void __malloc_unlock(struct _reent ptr) { xTaskResumeAll(); } /-----------------------------------------------------------/ /* Added as there is no such function in FreeRTOS. / void pvPortRealloc( void pv, size_t xWantedSize ) { void pvReturn; vTaskSuspendAll(); { pvReturn = realloc( pv, xWantedSize ); } xTaskResumeAll(); return pvReturn; } /-----------------------------------------------------------/ /* The cooperative scheduler requires a normal IRQ service routine to simply increment the system tick. / / The preemptive scheduler is defined as "naked" as the full context is saved on entry as part of the context switch. / __attribute__((__naked__)) static void vTick( void ) { / Save the context of the interrupted task. / portSAVE_CONTEXT_OS_INT(); #if( configTICK_USE_TC==1 ) / Clear the interrupt flag. / prvClearTcInt(); #else / Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) clock cycles from now. / prvScheduleNextTick(); #endif / Because FreeRTOS is not supposed to run with nested interrupts, put all OS calls in a critical section . / portENTER_CRITICAL(); vTaskIncrementTick(); portEXIT_CRITICAL(); / Restore the context of the "elected task". / portRESTORE_CONTEXT_OS_INT(); } /-----------------------------------------------------------/ __attribute__((__naked__)) void SCALLYield( void ) { / Save the context of the interrupted task. / portSAVE_CONTEXT_SCALL(); vTaskSwitchContext(); portRESTORE_CONTEXT_SCALL(); } /-----------------------------------------------------------/ / The code generated by the GCC compiler uses the stack in different ways at different optimisation levels. The interrupt flags can therefore not always be saved to the stack. Instead the critical section nesting level is stored in a variable, which is then saved as part of the stack context. / __attribute__((__noinline__)) void vPortEnterCritical( void ) { / Disable interrupts / portDISABLE_INTERRUPTS(); / Now interrupts are disabled ulCriticalNesting can be accessed directly. Increment ulCriticalNesting to keep a count of how many times portENTER_CRITICAL() has been called. / ulCriticalNesting++; } /-----------------------------------------------------------/ __attribute__((__noinline__)) void vPortExitCritical( void ) { if(ulCriticalNesting > portNO_CRITICAL_NESTING) { ulCriticalNesting--; if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { / Enable all interrupt/exception. / portENABLE_INTERRUPTS(); } } } /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been called. * * See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as expected by the portRESTORE_CONTEXT() macro. / / When the task starts, it will expect to find the function parameter in R12. / pxTopOfStack--; pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 / pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 / pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR / pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC / pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR / pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 / pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 / pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { / Start the timer that generates the tick ISR. Interrupts are disabled here already. / prvSetupTimerInterrupt(); / Start the first task. / portRESTORE_CONTEXT(); / Should not get here! / return 0; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / It is unlikely that the AVR32 port will require this function as there is nothing to return to. / } /-----------------------------------------------------------/ / Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) clock cycles from now. / #if( configTICK_USE_TC==0 ) static void prvScheduleFirstTick(void) { unsigned long lCycles; lCycles = Get_system_register(AVR32_COUNT); lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception // generation feature does not get disabled. if(0 == lCycles) { lCycles++; } Set_system_register(AVR32_COMPARE, lCycles); } __attribute__((__noinline__)) static void prvScheduleNextTick(void) { unsigned long lCycles, lCount; lCycles = Get_system_register(AVR32_COMPARE); lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception // generation feature does not get disabled. if(0 == lCycles) { lCycles++; } lCount = Get_system_register(AVR32_COUNT); if( lCycles < lCount ) { // We missed a tick, recover for the next. lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); } Set_system_register(AVR32_COMPARE, lCycles); } #else __attribute__((__noinline__)) static void prvClearTcInt(void) { AVR32_TC.channel[configTICK_TC_CHANNEL].sr; } #endif /-----------------------------------------------------------/ / Setup the timer to generate the tick interrupts. / static void prvSetupTimerInterrupt(void) { #if( configTICK_USE_TC==1 ) volatile avr32_tc_t tc = &AVR32_TC; // Options for waveform genration. tc_waveform_opt_t waveform_opt = { .channel = configTICK_TC_CHANNEL, /* Channel selection. / .bswtrg = TC_EVT_EFFECT_NOOP, / Software trigger effect on TIOB. / .beevt = TC_EVT_EFFECT_NOOP, / External event effect on TIOB. / .bcpc = TC_EVT_EFFECT_NOOP, / RC compare effect on TIOB. / .bcpb = TC_EVT_EFFECT_NOOP, / RB compare effect on TIOB. / .aswtrg = TC_EVT_EFFECT_NOOP, / Software trigger effect on TIOA. / .aeevt = TC_EVT_EFFECT_NOOP, / External event effect on TIOA. / .acpc = TC_EVT_EFFECT_NOOP, / RC compare effect on TIOA: toggle. / .acpa = TC_EVT_EFFECT_NOOP, / RA compare effect on TIOA: toggle (other possibilities are none, set and clear). / .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/ Waveform selection: Up mode without automatic trigger on RC compare. / .enetrg = FALSE, / External event trigger enable. / .eevt = 0, / External event selection. / .eevtedg = TC_SEL_NO_EDGE, / External event edge selection. / .cpcdis = FALSE, / Counter disable when RC compare. / .cpcstop = FALSE, / Counter clock stopped with RC compare. / .burst = FALSE, / Burst signal selection. / .clki = FALSE, / Clock inversion. / .tcclks = TC_CLOCK_SOURCE_TC2 / Internal source clock 2. / }; tc_interrupt_t tc_interrupt = { .etrgs=0, .ldrbs=0, .ldras=0, .cpcs =1, .cpbs =0, .cpas =0, .lovrs=0, .covfs=0, }; #endif / Disable all interrupt/exception. / portDISABLE_INTERRUPTS(); / Register the compare interrupt handler to the interrupt controller and enable the compare interrupt. / #if( configTICK_USE_TC==1 ) { INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0); / Initialize the timer/counter. / tc_init_waveform(tc, &waveform_opt); / Set the compare triggers. Remember TC counter is 16-bits, so counting second is not possible! That's why we configure it to count ms. / tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); / Start the timer/counter. */ tc_start(tc, configTICK_TC_CHANNEL); } #else { INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0); prvScheduleFirstTick(); } #endif }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/AVR32_UC3/port.c	C	oos	16,901
.extern pxCurrentTCB .extern vTaskISRHandler .extern vTaskSwitchContext .extern uxCriticalNesting .extern pulISRStack .global __FreeRTOS_interrupt_handler .global VPortYieldASM .global vStartFirstTask .macro portSAVE_CONTEXT /* Make room for the context on the stack. / addik r1, r1, -132 / Save r31 so it can then be used. / swi r31, r1, 4 / Copy the msr into r31 - this is stacked later. / mfs r31, rmsr / Stack general registers. / swi r30, r1, 12 swi r29, r1, 16 swi r28, r1, 20 swi r27, r1, 24 swi r26, r1, 28 swi r25, r1, 32 swi r24, r1, 36 swi r23, r1, 40 swi r22, r1, 44 swi r21, r1, 48 swi r20, r1, 52 swi r19, r1, 56 swi r18, r1, 60 swi r17, r1, 64 swi r16, r1, 68 swi r15, r1, 72 swi r13, r1, 80 swi r12, r1, 84 swi r11, r1, 88 swi r10, r1, 92 swi r9, r1, 96 swi r8, r1, 100 swi r7, r1, 104 swi r6, r1, 108 swi r5, r1, 112 swi r4, r1, 116 swi r3, r1, 120 swi r2, r1, 124 / Stack the critical section nesting value. / lwi r3, r0, uxCriticalNesting swi r3, r1, 128 / Save the top of stack value to the TCB. / lwi r3, r0, pxCurrentTCB sw r1, r0, r3 .endm .macro portRESTORE_CONTEXT / Load the top of stack value from the TCB. / lwi r3, r0, pxCurrentTCB lw r1, r0, r3 / Restore the general registers. / lwi r31, r1, 4 lwi r30, r1, 12 lwi r29, r1, 16 lwi r28, r1, 20 lwi r27, r1, 24 lwi r26, r1, 28 lwi r25, r1, 32 lwi r24, r1, 36 lwi r23, r1, 40 lwi r22, r1, 44 lwi r21, r1, 48 lwi r20, r1, 52 lwi r19, r1, 56 lwi r18, r1, 60 lwi r17, r1, 64 lwi r16, r1, 68 lwi r15, r1, 72 lwi r14, r1, 76 lwi r13, r1, 80 lwi r12, r1, 84 lwi r11, r1, 88 lwi r10, r1, 92 lwi r9, r1, 96 lwi r8, r1, 100 lwi r7, r1, 104 lwi r6, r1, 108 lwi r5, r1, 112 lwi r4, r1, 116 lwi r2, r1, 124 / Load the critical nesting value. / lwi r3, r1, 128 swi r3, r0, uxCriticalNesting / Obtain the MSR value from the stack. / lwi r3, r1, 8 / Are interrupts enabled in the MSR? If so return using an return from interrupt instruction to ensure interrupts are enabled only once the task is running again. / andi r3, r3, 2 beqid r3, 36 or r0, r0, r0 / Reload the rmsr from the stack, clear the enable interrupt bit in the value before saving back to rmsr register, then return enabling interrupts as we return. / lwi r3, r1, 8 andi r3, r3, ~2 mts rmsr, r3 lwi r3, r1, 120 addik r1, r1, 132 rtid r14, 0 or r0, r0, r0 / Reload the rmsr from the stack, place it in the rmsr register, and return without enabling interrupts. / lwi r3, r1, 8 mts rmsr, r3 lwi r3, r1, 120 addik r1, r1, 132 rtsd r14, 0 or r0, r0, r0 .endm .text .align 2 __FreeRTOS_interrupt_handler: portSAVE_CONTEXT / Entered via an interrupt so interrupts must be enabled in msr. / ori r31, r31, 2 / Stack msr. / swi r31, r1, 8 / Stack the return address. As we entered via an interrupt we do not need to modify the return address prior to stacking. / swi r14, r1, 76 / Now switch to use the ISR stack. / lwi r3, r0, pulISRStack add r1, r3, r0 bralid r15, vTaskISRHandler or r0, r0, r0 portRESTORE_CONTEXT VPortYieldASM: portSAVE_CONTEXT / Stack msr. / swi r31, r1, 8 / Modify the return address so we return to the instruction after the exception. / addi r14, r14, 8 swi r14, r1, 76 / Now switch to use the ISR stack. */ lwi r3, r0, pulISRStack add r1, r3, r0 bralid r15, vTaskSwitchContext or r0, r0, r0 portRESTORE_CONTEXT vStartFirstTask: portRESTORE_CONTEXT	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MicroBlaze/portasm.s	Unix Assembly	oos	3,702
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned portLONG #define portBASE_TYPE portLONG #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Interrupt control macros. / void microblaze_disable_interrupts( void ); void microblaze_enable_interrupts( void ); #define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() #define portENABLE_INTERRUPTS() microblaze_enable_interrupts() /-----------------------------------------------------------/ / Critical section macros. / void vPortEnterCritical( void ); void vPortExitCritical( void ); #define portENTER_CRITICAL() { \ extern unsigned portBASE_TYPE uxCriticalNesting; \ microblaze_disable_interrupts(); \ uxCriticalNesting++; \ } #define portEXIT_CRITICAL() { \ extern unsigned portBASE_TYPE uxCriticalNesting; \ / Interrupts are disabled, so we can / \ / access the variable directly. / \ uxCriticalNesting--; \ if( uxCriticalNesting == 0 ) \ { \ / The nesting has unwound and we \ can enable interrupts again. / \ portENABLE_INTERRUPTS(); \ } \ } /-----------------------------------------------------------/ / Task utilities. / void vPortYield( void ); #define portYIELD() vPortYield() void vTaskSwitchContext(); #define portYIELD_FROM_ISR() vTaskSwitchContext() /-----------------------------------------------------------/ / Hardware specifics. / #define portBYTE_ALIGNMENT 4 #define portSTACK_GROWTH ( -1 ) #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portNOP() asm volatile ( "NOP" ) /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MicroBlaze/portmacro.h	C	oos	5,969
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the MicroBlaze port. ----------------------------------------------------------/ /* Scheduler includes. / #include "FreeRTOS.h" #include "task.h" / Standard includes. / #include <string.h> / Hardware includes. / #include <xintc.h> #include <xintc_i.h> #include <xtmrctr.h> / Tasks are started with interrupts enabled. / #define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 ) / Tasks are started with a critical section nesting of 0 - however prior to the scheduler being commenced we don't want the critical nesting level to reach zero, so it is initialised to a high value. / #define portINITIAL_NESTING_VALUE ( 0xff ) / Our hardware setup only uses one counter. / #define portCOUNTER_0 0 / The stack used by the ISR is filled with a known value to assist in debugging. / #define portISR_STACK_FILL_VALUE 0x55555555 / Counts the nesting depth of calls to portENTER_CRITICAL(). Each task maintains it's own count, so this variable is saved as part of the task context. / volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE; / To limit the amount of stack required by each task, this port uses a separate stack for interrupts. / unsigned long pulISRStack; /-----------------------------------------------------------/ /* * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but * could have alternatively used the watchdog timer or timer 1. / static void prvSetupTimerInterrupt( void ); /-----------------------------------------------------------/ / * Initialise the stack of a task to look exactly as if a call to * portSAVE_CONTEXT had been made. * * See the header file portable.h. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { extern void _SDA2_BASE_, _SDA_BASE_; const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_; const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_; /* Place a few bytes of known values on the bottom of the stack. This is essential for the Microblaze port and these lines must not be omitted. The parameter value will overwrite the 0x22222222 value during the function prologue. / pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x33333333; pxTopOfStack--; /* First stack an initial value for the critical section nesting. This is initialised to zero as tasks are started with interrupts enabled. / pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. / / Place an initial value for all the general purpose registers. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. / pxTopOfStack--; / The MSR is stacked between R30 and R31. / pxTopOfStack = portINITIAL_MSR_STATE; pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x1f; / R31. / pxTopOfStack--; / Return a pointer to the top of the stack we have generated so this can be stored in the task control block for the task. / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { extern void ( __FreeRTOS_interrupt_Handler )( void ); extern void ( vStartFirstTask )( void ); / Setup the FreeRTOS interrupt handler. Code copied from crt0.s. / asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ "sw r6, r1, r0 \n\t" \ "lhu r7, r1, r0 \n\t" \ "shi r7, r0, 0x12 \n\t" \ "shi r6, r0, 0x16 " ); / Setup the hardware to generate the tick. Interrupts are disabled when this function is called. / prvSetupTimerInterrupt(); / Allocate the stack to be used by the interrupt handler. / pulISRStack = ( unsigned long ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) ); /* Restore the context of the first task that is going to run. / if( pulISRStack != NULL ) { / Fill the ISR stack with a known value to facilitate debugging. / memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE sizeof( portSTACK_TYPE ) ); pulISRStack += ( configMINIMAL_STACK_SIZE - 1 ); /* Kick off the first task. / vStartFirstTask(); } / Should not get here as the tasks are now running! / return pdFALSE; } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / Not implemented. / } /-----------------------------------------------------------/ / * Manual context switch called by portYIELD or taskYIELD. / void vPortYield( void ) { extern void VPortYieldASM( void ); / Perform the context switch in a critical section to assure it is not interrupted by the tick ISR. It is not a problem to do this as each task maintains it's own interrupt status. / portENTER_CRITICAL(); / Jump directly to the yield function to ensure there is no compiler generated prologue code. / asm volatile ( "bralid r14, VPortYieldASM \n\t" \ "or r0, r0, r0 \n\t" ); portEXIT_CRITICAL(); } /-----------------------------------------------------------/ / * Hardware initialisation to generate the RTOS tick. / static void prvSetupTimerInterrupt( void ) { XTmrCtr xTimer; const unsigned long ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; unsigned portBASE_TYPE uxMask; / The OPB timer1 is used to generate the tick. Use the provided library functions to enable the timer and set the tick frequency. / XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID ); XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue ); XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK \| XTC_CSR_INT_OCCURED_MASK ); / Set the timer interrupt enable bit while maintaining the other bit states. / uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); uxMask \|= XPAR_OPB_TIMER_1_INTERRUPT_MASK; XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK \| XTC_CSR_ENABLE_INT_MASK \| XTC_CSR_AUTO_RELOAD_MASK \| XTC_CSR_DOWN_COUNT_MASK \| XTC_CSR_INT_OCCURED_MASK ); XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 ); } /-----------------------------------------------------------/ / * The interrupt handler placed in the interrupt vector when the scheduler is * started. The task context has already been saved when this is called. * This handler determines the interrupt source and calls the relevant * peripheral handler. / void vTaskISRHandler( void ) { static unsigned long ulPending; / Which interrupts are pending? / ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) ); if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS ) { static XIntc_VectorTableEntry pxTablePtr; static XIntc_Config pxConfig; static unsigned long ulInterruptMask; ulInterruptMask = ( unsigned long ) 1 << ulPending; / Get the configuration data using the device ID / pxConfig = &XIntc_ConfigTable[ ( unsigned long ) XPAR_INTC_SINGLE_DEVICE_ID ]; pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] ); if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) { XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); pxTablePtr->Handler( pxTablePtr->CallBackRef ); } else { pxTablePtr->Handler( pxTablePtr->CallBackRef ); XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); } } } /-----------------------------------------------------------/ / * Handler for the timer interrupt. / void vTickISR( void pvBaseAddress ) { unsigned long ulCSR; /* Increment the RTOS tick - this might cause a task to unblock. / vTaskIncrementTick(); / Clear the timer interrupt / ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR ); / If we are using the preemptive scheduler then we also need to determine if this tick should cause a context switch. / #if configUSE_PREEMPTION == 1 vTaskSwitchContext(); #endif } /-----------------------------------------------------------*/	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/GCC/MicroBlaze/port.c	C	oos	13,814
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE long #define portLONG long #define portSHORT int #define portSTACK_TYPE unsigned portSHORT #define portBASE_TYPE portSHORT #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ / Critical section handling. / #define portENTER_CRITICAL() __asm{ pushf } \ __asm{ cli } \ #define portEXIT_CRITICAL() __asm{ popf } #define portDISABLE_INTERRUPTS() __asm{ cli } #define portENABLE_INTERRUPTS() __asm{ sti } /-----------------------------------------------------------/ / Hardware specifics. / #define portNOP() __asm{ nop } #define portSTACK_GROWTH ( -1 ) #define portSWITCH_INT_NUMBER 0x80 #define portYIELD() __asm{ int portSWITCH_INT_NUMBER } #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 2 #define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) / Start the tasks with interrupts enabled. / /-----------------------------------------------------------/ / Compiler specifics. / #define portINPUT_BYTE( xAddr ) inp( xAddr ) #define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) #define portINPUT_WORD( xAddr ) inpw( xAddr ) #define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void pvParameters ) #define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h	C	oos	5,376
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / typedef void tskTCB; extern volatile tskTCB volatile pxCurrentTCB; extern void vTaskSwitchContext( void ); /* * Saves the stack pointer for one task into its TCB, calls * vTaskSwitchContext() to update the TCB being used, then restores the stack * from the new TCB read to run the task. / void portSWITCH_CONTEXT( void ); / * Load the stack pointer from the TCB of the task which is going to be first * to execute. Then force an IRET so the registers and IP are popped off the * stack. / void portFIRST_CONTEXT( void ); #define portSWITCH_CONTEXT() \ asm { mov ax, seg pxCurrentTCB } \ asm { mov ds, ax } \ asm { les bx, pxCurrentTCB } / Save the stack pointer into the TCB. / \ asm { mov es:0x2[ bx ], ss } \ asm { mov es:[ bx ], sp } \ asm { call far ptr vTaskSwitchContext } / Perform the switch. / \ asm { mov ax, seg pxCurrentTCB } / Restore the stack pointer from the TCB. */ \ asm { mov ds, ax } \ asm { les bx, dword ptr pxCurrentTCB } \ asm { mov ss, es:[ bx + 2 ] } \ asm { mov sp, es:[ bx ] } #define portFIRST_CONTEXT() \ asm { mov ax, seg pxCurrentTCB } \ asm { mov ds, ax } \ asm { les bx, dword ptr pxCurrentTCB } \ asm { mov ss, es:[ bx + 2 ] } \ asm { mov sp, es:[ bx ] } \ asm { pop bp } \ asm { pop di } \ asm { pop si } \ asm { pop ds } \ asm { pop es } \ asm { pop dx } \ asm { pop cx } \ asm { pop bx } \ asm { pop ax } \ asm { iret }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h	C	oos	4,717
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the Tern EE 186 * port. ----------------------------------------------------------/ /* Library includes. / #include <embedded.h> #include <ae.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" #include "portasm.h" / The timer increments every four clocks, hence the divide by 4. / #define portTIMER_COMPARE ( unsigned short ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( unsigned long ) 4 ) / From the RDC data sheet. / #define portENABLE_TIMER_AND_INTERRUPT ( unsigned short ) 0xe001 / Interrupt control. / #define portEIO_REGISTER 0xff22 #define portCLEAR_INTERRUPT 0x0008 / Setup the hardware to generate the required tick frequency. / static void prvSetupTimerInterrupt( void ); / The ISR used depends on whether the preemptive or cooperative scheduler is being used. / #if( configUSE_PREEMPTION == 1 ) / Tick service routine used by the scheduler when preemptive scheduling is being used. / static void __interrupt __far prvPreemptiveTick( void ); #else / Tick service routine used by the scheduler when cooperative scheduling is being used. / static void __interrupt __far prvNonPreemptiveTick( void ); #endif / Trap routine used by taskYIELD() to manually cause a context switch. / static void __interrupt __far prvYieldProcessor( void ); / The timer initialisation functions leave interrupts enabled, which is not what we want. This ISR is installed temporarily in case the timer fires before we get a change to disable interrupts again. / static void __interrupt __far prvDummyISR( void ); /-----------------------------------------------------------/ / See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { portSTACK_TYPE DS_Reg = 0; /* Place a few bytes of known values on the bottom of the stack. This is just useful for debugging. / pxTopOfStack = 0x1111; pxTopOfStack--; pxTopOfStack = 0x2222; pxTopOfStack--; pxTopOfStack = 0x3333; pxTopOfStack--; /* We are going to start the scheduler using a return from interrupt instruction to load the program counter, so first there would be the function call with parameters preamble. / pxTopOfStack = FP_SEG( pvParameters ); pxTopOfStack--; pxTopOfStack = FP_OFF( pvParameters ); pxTopOfStack--; pxTopOfStack = FP_SEG( pxCode ); pxTopOfStack--; pxTopOfStack = FP_OFF( pxCode ); pxTopOfStack--; / Next the status register and interrupt return address. / pxTopOfStack = portINITIAL_SW; pxTopOfStack--; pxTopOfStack = FP_SEG( pxCode ); pxTopOfStack--; pxTopOfStack = FP_OFF( pxCode ); pxTopOfStack--; /* The remaining registers would be pushed on the stack by our context switch function. These are loaded with values simply to make debugging easier. / pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES / pxTopOfStack--; / We need the true data segment. / __asm{ MOV DS_Reg, DS }; pxTopOfStack = DS_Reg; /* DS / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { / This is called with interrupts already disabled. / / Put our manual switch (yield) function on a known vector. / setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); / Setup the tick interrupt. / prvSetupTimerInterrupt(); / Kick off the scheduler by setting up the context of the first task. / portFIRST_CONTEXT(); / Should not get here! / return pdFALSE; } /-----------------------------------------------------------/ static void __interrupt __far prvDummyISR( void ) { / The timer initialisation functions leave interrupts enabled, which is not what we want. This ISR is installed temporarily in case the timer fires before we get a change to disable interrupts again. / outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); } /-----------------------------------------------------------/ / The ISR used depends on whether the preemptive or cooperative scheduler is being used. / #if( configUSE_PREEMPTION == 1 ) static void __interrupt __far prvPreemptiveTick( void ) { / Get the scheduler to update the task states following the tick. / vTaskIncrementTick(); / Switch in the context of the next task to be run. / portSWITCH_CONTEXT(); / Reset interrupt. / outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); } #else static void __interrupt __far prvNonPreemptiveTick( void ) { / Same as preemptive tick, but the cooperative scheduler is being used so we don't have to switch in the context of the next task. / vTaskIncrementTick(); / Reset interrupt. / outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); } #endif /-----------------------------------------------------------/ static void __interrupt __far prvYieldProcessor( void ) { / Switch in the context of the next task to be run. / portSWITCH_CONTEXT(); } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / Not implemented. / } /-----------------------------------------------------------/ static void prvSetupTimerInterrupt( void ) { const unsigned short usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT; const unsigned short usT2_IRQ = 0x13; / Configure the timer, the dummy handler is used here as the init function leaves interrupts enabled. / t2_init( usTimerAMode, usTimerACompare, prvDummyISR ); / Disable interrupts again before installing the real handlers. / portDISABLE_INTERRUPTS(); #if( configUSE_PREEMPTION == 1 ) / Tick service routine used by the scheduler when preemptive scheduling is being used. / setvect( usT2_IRQ, prvPreemptiveTick ); #else / Tick service routine used by the scheduler when cooperative scheduling is being used. */ setvect( usT2_IRQ, prvNonPreemptiveTick ); #endif }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/Paradigm/Tern_EE/large_untested/port.c	C	oos	9,688
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. ----------------------------------------------------------- / /* Type definitions. / #define portCHAR char #define portFLOAT float #define portDOUBLE long #define portLONG long #define portSHORT int #define portSTACK_TYPE unsigned portSHORT #define portBASE_TYPE portSHORT typedef void ( __interrupt __far pxISR )(); #if( configUSE_16_BIT_TICKS == 1 ) typedef unsigned portSHORT portTickType; #define portMAX_DELAY ( portTickType ) 0xffff #else typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif /-----------------------------------------------------------/ /* Critical section handling. / #define portENTER_CRITICAL() __asm{ pushf } \ __asm{ cli } \ #define portEXIT_CRITICAL() __asm{ popf } #define portDISABLE_INTERRUPTS() __asm{ cli } #define portENABLE_INTERRUPTS() __asm{ sti } /-----------------------------------------------------------/ / Hardware specifics. / #define portNOP() __asm{ nop } #define portSTACK_GROWTH ( -1 ) #define portSWITCH_INT_NUMBER 0x80 #define portYIELD() __asm{ int portSWITCH_INT_NUMBER } #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 2 #define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) / Start the tasks with interrupts enabled. / /-----------------------------------------------------------/ / Compiler specifics. / #define portINPUT_BYTE( xAddr ) inp( xAddr ) #define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) #define portINPUT_WORD( xAddr ) inpw( xAddr ) #define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) /-----------------------------------------------------------/ / Task function macros as described on the FreeRTOS.org WEB site. / #define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void pvParameters ) #define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void pvParameters ) #ifdef __cplusplus } #endif #endif / PORTMACRO_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/Paradigm/Tern_EE/small/portmacro.h	C	oos	5,422
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PORT_ASM_H #define PORT_ASM_H typedef void tskTCB; extern volatile tskTCB volatile pxCurrentTCB; extern void vTaskSwitchContext( void ); /* * Saves the stack pointer for one task into its TCB, calls * vTaskSwitchContext() to update the TCB being used, then restores the stack * from the new TCB read to run the task. / void portEND_SWITCHING_ISR( void ); / * Load the stack pointer from the TCB of the task which is going to be first * to execute. Then force an IRET so the registers and IP are popped off the * stack. */ void portFIRST_CONTEXT( void ); #define portEND_SWITCHING_ISR() \ asm { mov bx, [pxCurrentTCB] } \ asm { mov word ptr [bx], sp } \ asm { call far ptr vTaskSwitchContext } \ asm { mov bx, [pxCurrentTCB] } \ asm { mov sp, [bx] } #define portFIRST_CONTEXT() \ asm { mov bx, [pxCurrentTCB] } \ asm { mov sp, [bx] } \ asm { pop bp } \ asm { pop di } \ asm { pop si } \ asm { pop ds } \ asm { pop es } \ asm { pop dx } \ asm { pop cx } \ asm { pop bx } \ asm { pop ax } \ asm { iret } #endif	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/Paradigm/Tern_EE/small/portasm.h	C	oos	4,295
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Implementation of functions defined in portable.h for the Tern EE 186 * port. ----------------------------------------------------------/ /* Library includes. / #include <embedded.h> #include <ae.h> / Scheduler includes. / #include "FreeRTOS.h" #include "task.h" #include "portasm.h" / The timer increments every four clocks, hence the divide by 4. / #define portPRESCALE_VALUE ( 16 ) #define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ 4UL ) ) /* From the RDC data sheet. / #define portENABLE_TIMER_AND_INTERRUPT ( unsigned short ) 0xe00b #define portENABLE_TIMER ( unsigned short ) 0xC001 / Interrupt control. / #define portEIO_REGISTER 0xff22 #define portCLEAR_INTERRUPT 0x0008 / Setup the hardware to generate the required tick frequency. / static void prvSetupTimerInterrupt( void ); / The ISR used depends on whether the preemptive or cooperative scheduler is being used. / #if( configUSE_PREEMPTION == 1 ) / Tick service routine used by the scheduler when preemptive scheduling is being used. / static void __interrupt __far prvPreemptiveTick( void ); #else / Tick service routine used by the scheduler when cooperative scheduling is being used. / static void __interrupt __far prvNonPreemptiveTick( void ); #endif / Trap routine used by taskYIELD() to manually cause a context switch. / static void __interrupt __far prvYieldProcessor( void ); /-----------------------------------------------------------/ / See header file for description. / portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ) { portSTACK_TYPE DS_Reg = 0; /* We need the true data segment. / __asm{ MOV DS_Reg, DS }; / Place a few bytes of known values on the bottom of the stack. This is just useful for debugging. / pxTopOfStack = 0x1111; pxTopOfStack--; pxTopOfStack = 0x2222; pxTopOfStack--; pxTopOfStack = 0x3333; pxTopOfStack--; /* We are going to start the scheduler using a return from interrupt instruction to load the program counter, so first there would be the function call with parameters preamble. / pxTopOfStack = FP_OFF( pvParameters ); pxTopOfStack--; pxTopOfStack = FP_OFF( pxCode ); pxTopOfStack--; / Next the status register and interrupt return address. / pxTopOfStack = portINITIAL_SW; pxTopOfStack--; pxTopOfStack = FP_SEG( pxCode ); pxTopOfStack--; pxTopOfStack = FP_OFF( pxCode ); pxTopOfStack--; /* The remaining registers would be pushed on the stack by our context switch function. These are loaded with values simply to make debugging easier. / pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES / pxTopOfStack--; pxTopOfStack = DS_Reg; /* DS / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI / pxTopOfStack--; pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP / return pxTopOfStack; } /-----------------------------------------------------------/ portBASE_TYPE xPortStartScheduler( void ) { / This is called with interrupts already disabled. / / Put our manual switch (yield) function on a known vector. / setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); / Setup the tick interrupt. / prvSetupTimerInterrupt(); / Kick off the scheduler by setting up the context of the first task. / portFIRST_CONTEXT(); / Should not get here! / return pdFALSE; } /-----------------------------------------------------------/ / The ISR used depends on whether the preemptive or cooperative scheduler is being used. / #if( configUSE_PREEMPTION == 1 ) static void __interrupt __far prvPreemptiveTick( void ) { / Get the scheduler to update the task states following the tick. / vTaskIncrementTick(); / Switch in the context of the next task to be run. / portEND_SWITCHING_ISR(); / Reset interrupt. / outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); } #else static void __interrupt __far prvNonPreemptiveTick( void ) { / Same as preemptive tick, but the cooperative scheduler is being used so we don't have to switch in the context of the next task. / vTaskIncrementTick(); / Reset interrupt. / outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); } #endif /-----------------------------------------------------------/ static void __interrupt __far prvYieldProcessor( void ) { / Switch in the context of the next task to be run. / portEND_SWITCHING_ISR(); } /-----------------------------------------------------------/ void vPortEndScheduler( void ) { / Not implemented. / } /-----------------------------------------------------------/ static void prvSetupTimerInterrupt( void ) { const unsigned long ulCompareValue = portTIMER_COMPARE; unsigned short usTimerCompare; usTimerCompare = ( unsigned short ) ( ulCompareValue >> 4 ); t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL ); #if( configUSE_PREEMPTION == 1 ) / Tick service routine used by the scheduler when preemptive scheduling is being used. / t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick ); #else / Tick service routine used by the scheduler when cooperative scheduling is being used. */ t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick ); #endif }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/portable/Paradigm/Tern_EE/small/port.c	C	oos	8,896
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #include "FreeRTOS.h" #include "task.h" #include "croutine.h" / * Some kernel aware debuggers require data to be viewed to be global, rather * than file scope. / #ifdef portREMOVE_STATIC_QUALIFIER #define static #endif / Lists for ready and blocked co-routines. --------------------/ static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /< Prioritised ready co-routines. / static xList xDelayedCoRoutineList1; /< Delayed co-routines. / static xList xDelayedCoRoutineList2; /< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. / static xList pxDelayedCoRoutineList; /< Points to the delayed co-routine list currently being used. / static xList * pxOverflowDelayedCoRoutineList; /< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. / static xList xPendingReadyCoRoutineList; /< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. / /* Other file private variables. --------------------------------/ corCRCB pxCurrentCoRoutine = NULL; static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; static portTickType xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; /* The initial state of the co-routine when it is created. / #define corINITIAL_STATE ( 0 ) / * Place the co-routine represented by pxCRCB into the appropriate ready queue * for the priority. It is inserted at the end of the list. * * This macro accesses the co-routine ready lists and therefore must not be * used from within an ISR. / #define prvAddCoRoutineToReadyQueue( pxCRCB ) \ { \ if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ { \ uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ } \ vListInsertEnd( ( xList ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ } /* * Utility to ready all the lists used by the scheduler. This is called * automatically upon the creation of the first co-routine. / static void prvInitialiseCoRoutineLists( void ); / * Co-routines that are readied by an interrupt cannot be placed directly into * the ready lists (there is no mutual exclusion). Instead they are placed in * in the pending ready list in order that they can later be moved to the ready * list by the co-routine scheduler. / static void prvCheckPendingReadyList( void ); / * Macro that looks at the list of co-routines that are currently delayed to * see if any require waking. * * Co-routines are stored in the queue in the order of their wake time - * meaning once one co-routine has been found whose timer has not expired * we need not look any further down the list. / static void prvCheckDelayedList( void ); /-----------------------------------------------------------/ signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) { signed portBASE_TYPE xReturn; corCRCB pxCoRoutine; /* Allocate the memory that will store the co-routine control block. / pxCoRoutine = ( corCRCB ) pvPortMalloc( sizeof( corCRCB ) ); if( pxCoRoutine ) { /* If pxCurrentCoRoutine is NULL then this is the first co-routine to be created and the co-routine data structures need initialising. / if( pxCurrentCoRoutine == NULL ) { pxCurrentCoRoutine = pxCoRoutine; prvInitialiseCoRoutineLists(); } / Check the priority is within limits. / if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) { uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; } / Fill out the co-routine control block from the function parameters. / pxCoRoutine->uxState = corINITIAL_STATE; pxCoRoutine->uxPriority = uxPriority; pxCoRoutine->uxIndex = uxIndex; pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; / Initialise all the other co-routine control block parameters. / vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); / Set the co-routine control block as a link back from the xListItem. This is so we can get back to the containing CRCB from a generic item in a list. / listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); / Event lists are always in priority order. / listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); / Now the co-routine has been initialised it can be added to the ready list at the correct priority. / prvAddCoRoutineToReadyQueue( pxCoRoutine ); xReturn = pdPASS; } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; } return xReturn; } /-----------------------------------------------------------/ void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList pxEventList ) { portTickType xTimeToWake; /* Calculate the time to wake - this may overflow but this is not a problem. / xTimeToWake = xCoRoutineTickCount + xTicksToDelay; / We must remove ourselves from the ready list before adding ourselves to the blocked list as the same list item is used for both lists. / vListRemove( ( xListItem ) &( pxCurrentCoRoutine->xGenericListItem ) ); /* The list item will be inserted in wake time order. / listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); if( xTimeToWake < xCoRoutineTickCount ) { / Wake time has overflowed. Place this item in the overflow list. / vListInsert( ( xList ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); } else { /* The wake time has not overflowed, so we can use the current block list. / vListInsert( ( xList ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); } if( pxEventList ) { /* Also add the co-routine to an event list. If this is done then the function must be called with interrupts disabled. / vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); } } /-----------------------------------------------------------/ static void prvCheckPendingReadyList( void ) { / Are there any co-routines waiting to get moved to the ready list? These are co-routines that have been readied by an ISR. The ISR cannot access the ready lists itself. / while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) { corCRCB pxUnblockedCRCB; /* The pending ready list can be accessed by an ISR. / portDISABLE_INTERRUPTS(); { pxUnblockedCRCB = ( corCRCB ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); } portENABLE_INTERRUPTS(); vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); } } /-----------------------------------------------------------/ static void prvCheckDelayedList( void ) { corCRCB pxCRCB; xPassedTicks = xTaskGetTickCount() - xLastTickCount; while( xPassedTicks ) { xCoRoutineTickCount++; xPassedTicks--; / If the tick count has overflowed we need to swap the ready lists. / if( xCoRoutineTickCount == 0 ) { xList pxTemp; /* Tick count has overflowed so we need to swap the delay lists. If there are any items in pxDelayedCoRoutineList here then there is an error! / pxTemp = pxDelayedCoRoutineList; pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; pxOverflowDelayedCoRoutineList = pxTemp; } / See if this tick has made a timeout expire. / while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) { pxCRCB = ( corCRCB ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) { /* Timeout not yet expired. / break; } portDISABLE_INTERRUPTS(); { / The event could have occurred just before this critical section. If this is the case then the generic list item will have been moved to the pending ready list and the following line is still valid. Also the pvContainer parameter will have been set to NULL so the following lines are also valid. / vListRemove( &( pxCRCB->xGenericListItem ) ); / Is the co-routine waiting on an event also? / if( pxCRCB->xEventListItem.pvContainer ) { vListRemove( &( pxCRCB->xEventListItem ) ); } } portENABLE_INTERRUPTS(); prvAddCoRoutineToReadyQueue( pxCRCB ); } } xLastTickCount = xCoRoutineTickCount; } /-----------------------------------------------------------/ void vCoRoutineSchedule( void ) { / See if any co-routines readied by events need moving to the ready lists. / prvCheckPendingReadyList(); / See if any delayed co-routines have timed out. / prvCheckDelayedList(); / Find the highest priority queue that contains ready co-routines. / while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) { if( uxTopCoRoutineReadyPriority == 0 ) { / No more co-routines to check. / return; } --uxTopCoRoutineReadyPriority; } / listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines of the same priority get an equal share of the processor time. / listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); / Call the co-routine. / ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); return; } /-----------------------------------------------------------/ static void prvInitialiseCoRoutineLists( void ) { unsigned portBASE_TYPE uxPriority; for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) { vListInitialise( ( xList ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); } vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); vListInitialise( ( xList * ) &xPendingReadyCoRoutineList ); /* Start with pxDelayedCoRoutineList using list1 and the pxOverflowDelayedCoRoutineList using list2. / pxDelayedCoRoutineList = &xDelayedCoRoutineList1; pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; } /-----------------------------------------------------------/ signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList pxEventList ) { corCRCB pxUnblockedCRCB; signed portBASE_TYPE xReturn; / This function is called from within an interrupt. It can only access event lists and the pending ready list. This function assumes that a check has already been made to ensure pxEventList is not empty. / pxUnblockedCRCB = ( corCRCB ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); vListInsertEnd( ( xList * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) { xReturn = pdTRUE; } else { xReturn = pdFALSE; } return xReturn; }	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/croutine.c	C	oos	14,871
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / / * This is the list implementation used by the scheduler. While it is tailored * heavily for the schedulers needs, it is also available for use by * application code. * * xLists can only store pointers to xListItems. Each xListItem contains a * numeric value (xItemValue). Most of the time the lists are sorted in * descending item value order. * * Lists are created already containing one list item. The value of this * item is the maximum possible that can be stored, it is therefore always at * the end of the list and acts as a marker. The list member pxHead always * points to this marker - even though it is at the tail of the list. This * is because the tail contains a wrap back pointer to the true head of * the list. * * In addition to it's value, each list item contains a pointer to the next * item in the list (pxNext), a pointer to the list it is in (pxContainer) * and a pointer to back to the object that contains it. These later two * pointers are included for efficiency of list manipulation. There is * effectively a two way link between the object containing the list item and * the list item itself. * * * \page ListIntroduction List Implementation * \ingroup FreeRTOSIntro / #ifndef LIST_H #define LIST_H #ifdef __cplusplus extern "C" { #endif / * Definition of the only type of object that a list can contain. / struct xLIST_ITEM { portTickType xItemValue; /< The value being listed. In most cases this is used to sort the list in descending order. / volatile struct xLIST_ITEM pxNext; /< Pointer to the next xListItem in the list. / volatile struct xLIST_ITEM * pxPrevious;/< Pointer to the previous xListItem in the list. / void * pvOwner; /< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. / void * pvContainer; /< Pointer to the list in which this list item is placed (if any). / }; typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. / struct xMINI_LIST_ITEM { portTickType xItemValue; volatile struct xLIST_ITEM pxNext; volatile struct xLIST_ITEM pxPrevious; }; typedef struct xMINI_LIST_ITEM xMiniListItem; / * Definition of the type of queue used by the scheduler. / typedef struct xLIST { volatile unsigned portBASE_TYPE uxNumberOfItems; volatile xListItem pxIndex; /< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). / volatile xMiniListItem xListEnd; /< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. / } xList; /* * Access macro to set the owner of a list item. The owner of a list item * is the object (usually a TCB) that contains the list item. * * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER * \ingroup LinkedList / #define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void ) ( pxOwner ) /* * Access macro to set the value of the list item. In most cases the value is * used to sort the list in descending order. * * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE * \ingroup LinkedList / #define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = ( xValue ) / * Access macro the retrieve the value of the list item. The value can * represent anything - for example a the priority of a task, or the time at * which a task should be unblocked. * * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE * \ingroup LinkedList / #define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) / * Access macro the retrieve the value of the list item at the head of a given * list. * * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE * \ingroup LinkedList / #define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->xItemValue ) / * Access macro to determine if a list contains any items. The macro will * only have the value true if the list is empty. * * \page listLIST_IS_EMPTY listLIST_IS_EMPTY * \ingroup LinkedList / #define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) / * Access macro to return the number of items in the list. / #define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) / * Access function to obtain the owner of the next entry in a list. * * The list member pxIndex is used to walk through a list. Calling * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list * and returns that entries pxOwner parameter. Using multiple calls to this * function it is therefore possible to move through every item contained in * a list. * * The pxOwner parameter of a list item is a pointer to the object that owns * the list item. In the scheduler this is normally a task control block. * The pxOwner parameter effectively creates a two way link between the list * item and its owner. * * @param pxList The list from which the next item owner is to be returned. * * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY * \ingroup LinkedList / #define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ { \ xList const pxConstList = ( pxList ); \ /* Increment the index to the next item and return the item, ensuring / \ / we don't return the marker used at the end of the list. / \ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ if( ( pxConstList )->pxIndex == ( xListItem ) &( ( pxConstList )->xListEnd ) ) \ { \ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ } \ ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ } /* * Access function to obtain the owner of the first entry in a list. Lists * are normally sorted in ascending item value order. * * This function returns the pxOwner member of the first item in the list. * The pxOwner parameter of a list item is a pointer to the object that owns * the list item. In the scheduler this is normally a task control block. * The pxOwner parameter effectively creates a two way link between the list * item and its owner. * * @param pxList The list from which the owner of the head item is to be * returned. * * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY * \ingroup LinkedList / #define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) / * Check to see if a list item is within a list. The list item maintains a * "container" pointer that points to the list it is in. All this macro does * is check to see if the container and the list match. * * @param pxList The list we want to know if the list item is within. * @param pxListItem The list item we want to know if is in the list. * @return pdTRUE is the list item is in the list, otherwise pdFALSE. * pointer against / #define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void ) ( pxList ) ) /* * Must be called before a list is used! This initialises all the members * of the list structure and inserts the xListEnd item into the list as a * marker to the back of the list. * * @param pxList Pointer to the list being initialised. * * \page vListInitialise vListInitialise * \ingroup LinkedList / void vListInitialise( xList pxList ); /* * Must be called before a list item is used. This sets the list container to * null so the item does not think that it is already contained in a list. * * @param pxItem Pointer to the list item being initialised. * * \page vListInitialiseItem vListInitialiseItem * \ingroup LinkedList / void vListInitialiseItem( xListItem pxItem ); /* * Insert a list item into a list. The item will be inserted into the list in * a position determined by its item value (descending item value order). * * @param pxList The list into which the item is to be inserted. * * @param pxNewListItem The item to that is to be placed in the list. * * \page vListInsert vListInsert * \ingroup LinkedList / void vListInsert( xList pxList, xListItem pxNewListItem ); / * Insert a list item into a list. The item will be inserted in a position * such that it will be the last item within the list returned by multiple * calls to listGET_OWNER_OF_NEXT_ENTRY. * * The list member pvIndex is used to walk through a list. Calling * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. * Placing an item in a list using vListInsertEnd effectively places the item * in the list position pointed to by pvIndex. This means that every other * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before * the pvIndex parameter again points to the item being inserted. * * @param pxList The list into which the item is to be inserted. * * @param pxNewListItem The list item to be inserted into the list. * * \page vListInsertEnd vListInsertEnd * \ingroup LinkedList / void vListInsertEnd( xList pxList, xListItem pxNewListItem ); / * Remove an item from a list. The list item has a pointer to the list that * it is in, so only the list item need be passed into the function. * * @param vListRemove The item to be removed. The item will remove itself from * the list pointed to by it's pxContainer parameter. * * \page vListRemove vListRemove * \ingroup LinkedList / void vListRemove( xListItem pxItemToRemove ); #ifdef __cplusplus } #endif #endif	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/list.h	C	oos	12,949
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef TASK_H #define TASK_H #ifndef INC_FREERTOS_H #error "include FreeRTOS.h must appear in source files before include task.h" #endif #include "portable.h" #include "list.h" #ifdef __cplusplus extern "C" { #endif /----------------------------------------------------------- * MACROS AND DEFINITIONS ----------------------------------------------------------/ #define tskKERNEL_VERSION_NUMBER "V7.0.1" /** * task. h * * Type by which tasks are referenced. For example, a call to xTaskCreate * returns (via a pointer parameter) an xTaskHandle variable that can then * be used as a parameter to vTaskDelete to delete the task. * * \page xTaskHandle xTaskHandle * \ingroup Tasks / typedef void xTaskHandle; /* * Used internally only. / typedef struct xTIME_OUT { portBASE_TYPE xOverflowCount; portTickType xTimeOnEntering; } xTimeOutType; / * Defines the memory ranges allocated to the task when an MPU is used. / typedef struct xMEMORY_REGION { void pvBaseAddress; unsigned long ulLengthInBytes; unsigned long ulParameters; } xMemoryRegion; /* * Parameters required to create an MPU protected task. / typedef struct xTASK_PARAMTERS { pdTASK_CODE pvTaskCode; const signed char const pcName; unsigned short usStackDepth; void pvParameters; unsigned portBASE_TYPE uxPriority; portSTACK_TYPE puxStackBuffer; xMemoryRegion xRegions[ portNUM_CONFIGURABLE_REGIONS ]; } xTaskParameters; /* * Defines the priority used by the idle task. This must not be modified. * * \ingroup TaskUtils / #define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0U ) /* * task. h * * Macro for forcing a context switch. * * \page taskYIELD taskYIELD * \ingroup SchedulerControl / #define taskYIELD() portYIELD() /* * task. h * * Macro to mark the start of a critical code region. Preemptive context * switches cannot occur when in a critical region. * * NOTE: This may alter the stack (depending on the portable implementation) * so must be used with care! * * \page taskENTER_CRITICAL taskENTER_CRITICAL * \ingroup SchedulerControl / #define taskENTER_CRITICAL() portENTER_CRITICAL() /* * task. h * * Macro to mark the end of a critical code region. Preemptive context * switches cannot occur when in a critical region. * * NOTE: This may alter the stack (depending on the portable implementation) * so must be used with care! * * \page taskEXIT_CRITICAL taskEXIT_CRITICAL * \ingroup SchedulerControl / #define taskEXIT_CRITICAL() portEXIT_CRITICAL() /* * task. h * * Macro to disable all maskable interrupts. * * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS * \ingroup SchedulerControl / #define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() /* * task. h * * Macro to enable microcontroller interrupts. * * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS * \ingroup SchedulerControl / #define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() / Definitions returned by xTaskGetSchedulerState(). / #define taskSCHEDULER_NOT_STARTED 0 #define taskSCHEDULER_RUNNING 1 #define taskSCHEDULER_SUSPENDED 2 /----------------------------------------------------------- * TASK CREATION API ----------------------------------------------------------/ /** * task. h <pre> portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const char const pcName, unsigned short usStackDepth, void pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle pvCreatedTask );</pre> * * Create a new task and add it to the list of tasks that are ready to run. * * xTaskCreate() can only be used to create a task that has unrestricted * access to the entire microcontroller memory map. Systems that include MPU * support can alternatively create an MPU constrained task using * xTaskCreateRestricted(). * * @param pvTaskCode Pointer to the task entry function. Tasks * must be implemented to never return (i.e. continuous loop). * * @param pcName A descriptive name for the task. This is mainly used to * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default * is 16. * * @param usStackDepth The size of the task stack specified as the number of * variables the stack can hold - not the number of bytes. For example, if * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes * will be allocated for stack storage. * * @param pvParameters Pointer that will be used as the parameter for the task * being created. * * @param uxPriority The priority at which the task should run. Systems that * include MPU support can optionally create tasks in a privileged (system) * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For * example, to create a privileged task at priority 2 the uxPriority parameter * should be set to ( 2 \| portPRIVILEGE_BIT ). * * @param pvCreatedTask Used to pass back a handle by which the created task * can be referenced. * * @return pdPASS if the task was successfully created and added to a ready * list, otherwise an error code defined in the file errors. h * * Example usage: <pre> // Task to be created. void vTaskCode( void * pvParameters ) { for( ;; ) { // Task code goes here. } } // Function that creates a task. void vOtherFunction( void ) { static unsigned char ucParameterToPass; xTaskHandle xHandle; // Create the task, storing the handle. Note that the passed parameter ucParameterToPass // must exist for the lifetime of the task, so in this case is declared static. If it was just an // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time // the new task attempts to access it. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle ); // Use the handle to delete the task. vTaskDelete( xHandle ); } </pre> * \defgroup xTaskCreate xTaskCreate * \ingroup Tasks / #define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ) ) /* * task. h <pre> portBASE_TYPE xTaskCreateRestricted( xTaskParameters pxTaskDefinition, xTaskHandle pxCreatedTask );</pre> * xTaskCreateRestricted() should only be used in systems that include an MPU * implementation. * * Create a new task and add it to the list of tasks that are ready to run. * The function parameters define the memory regions and associated access * permissions allocated to the task. * * @param pxTaskDefinition Pointer to a structure that contains a member * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API * documentation) plus an optional stack buffer and the memory region * definitions. * * @param pxCreatedTask Used to pass back a handle by which the created task * can be referenced. * * @return pdPASS if the task was successfully created and added to a ready * list, otherwise an error code defined in the file errors. h * * Example usage: <pre> // Create an xTaskParameters structure that defines the task to be created. static const xTaskParameters xCheckTaskParameters = { vATask, // pvTaskCode - the function that implements the task. "ATask", // pcName - just a text name for the task to assist debugging. 100, // usStackDepth - the stack size DEFINED IN WORDS. NULL, // pvParameters - passed into the task function as the function parameters. ( 1UL \| portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state. cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack. // xRegions - Allocate up to three separate memory regions for access by // the task, with appropriate access permissions. Different processors have // different memory alignment requirements - refer to the FreeRTOS documentation // for full information. { // Base address Length Parameters { cReadWriteArray, 32, portMPU_REGION_READ_WRITE }, { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY }, { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE } } }; int main( void ) { xTaskHandle xHandle; // Create a task from the const structure defined above. The task handle // is requested (the second parameter is not NULL) but in this case just for // demonstration purposes as its not actually used. xTaskCreateRestricted( &xRegTest1Parameters, &xHandle ); // Start the scheduler. vTaskStartScheduler(); // Will only get here if there was insufficient memory to create the idle // task. for( ;; ); } </pre> * \defgroup xTaskCreateRestricted xTaskCreateRestricted * \ingroup Tasks / #define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) ) /* * task. h <pre> void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion const pxRegions );</pre> * * Memory regions are assigned to a restricted task when the task is created by * a call to xTaskCreateRestricted(). These regions can be redefined using * vTaskAllocateMPURegions(). * * @param xTask The handle of the task being updated. * * @param xRegions A pointer to an xMemoryRegion structure that contains the * new memory region definitions. * * Example usage: <pre> // Define an array of xMemoryRegion structures that configures an MPU region // allowing read/write access for 1024 bytes starting at the beginning of the // ucOneKByte array. The other two of the maximum 3 definable regions are // unused so set to zero. static const xMemoryRegion xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] = { // Base address Length Parameters { ucOneKByte, 1024, portMPU_REGION_READ_WRITE }, { 0, 0, 0 }, { 0, 0, 0 } }; void vATask( void pvParameters ) { // This task was created such that it has access to certain regions of // memory as defined by the MPU configuration. At some point it is // desired that these MPU regions are replaced with that defined in the // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions() // for this purpose. NULL is used as the task handle to indicate that this // function should modify the MPU regions of the calling task. vTaskAllocateMPURegions( NULL, xAltRegions ); // Now the task can continue its function, but from this point on can only // access its stack and the ucOneKByte array (unless any other statically // defined or shared regions have been declared elsewhere). } </pre> \defgroup xTaskCreateRestricted xTaskCreateRestricted * \ingroup Tasks / void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion const pxRegions ) PRIVILEGED_FUNCTION; /** * task. h * <pre>void vTaskDelete( xTaskHandle pxTask );</pre> * * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. * See the configuration section for more information. * * Remove a task from the RTOS real time kernels management. The task being * deleted will be removed from all ready, blocked, suspended and event lists. * * NOTE: The idle task is responsible for freeing the kernel allocated * memory from tasks that have been deleted. It is therefore important that * the idle task is not starved of microcontroller processing time if your * application makes any calls to vTaskDelete (). Memory allocated by the * task code is not automatically freed, and should be freed before the task * is deleted. * * See the demo application file death.c for sample code that utilises * vTaskDelete (). * * @param pxTask The handle of the task to be deleted. Passing NULL will * cause the calling task to be deleted. * * Example usage: <pre> void vOtherFunction( void ) { xTaskHandle xHandle; // Create the task, storing the handle. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); // Use the handle to delete the task. vTaskDelete( xHandle ); } </pre> * \defgroup vTaskDelete vTaskDelete * \ingroup Tasks / void vTaskDelete( xTaskHandle pxTaskToDelete ) PRIVILEGED_FUNCTION; /----------------------------------------------------------- * TASK CONTROL API ----------------------------------------------------------/ /** * task. h * <pre>void vTaskDelay( portTickType xTicksToDelay );</pre> * * Delay a task for a given number of ticks. The actual time that the * task remains blocked depends on the tick rate. The constant * portTICK_RATE_MS can be used to calculate real time from the tick * rate - with the resolution of one tick period. * * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. * See the configuration section for more information. * * * vTaskDelay() specifies a time at which the task wishes to unblock relative to * the time at which vTaskDelay() is called. For example, specifying a block * period of 100 ticks will cause the task to unblock 100 ticks after * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method * of controlling the frequency of a cyclical task as the path taken through the * code, as well as other task and interrupt activity, will effect the frequency * at which vTaskDelay() gets called and therefore the time at which the task * next executes. See vTaskDelayUntil() for an alternative API function designed * to facilitate fixed frequency execution. It does this by specifying an * absolute time (rather than a relative time) at which the calling task should * unblock. * * @param xTicksToDelay The amount of time, in tick periods, that * the calling task should block. * * Example usage: void vTaskFunction( void * pvParameters ) { void vTaskFunction( void * pvParameters ) { // Block for 500ms. const portTickType xDelay = 500 / portTICK_RATE_MS; for( ;; ) { // Simply toggle the LED every 500ms, blocking between each toggle. vToggleLED(); vTaskDelay( xDelay ); } } * \defgroup vTaskDelay vTaskDelay * \ingroup TaskCtrl / void vTaskDelay( portTickType xTicksToDelay ) PRIVILEGED_FUNCTION; /* * task. h * <pre>void vTaskDelayUntil( portTickType pxPreviousWakeTime, portTickType xTimeIncrement );</pre> * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. * See the configuration section for more information. * * Delay a task until a specified time. This function can be used by cyclical * tasks to ensure a constant execution frequency. * * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will * cause a task to block for the specified number of ticks from the time vTaskDelay () is * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed * execution frequency as the time between a task starting to execute and that task * calling vTaskDelay () may not be fixed [the task may take a different path though the * code between calls, or may get interrupted or preempted a different number of times * each time it executes]. * * Whereas vTaskDelay () specifies a wake time relative to the time at which the function * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to * unblock. * * The constant portTICK_RATE_MS can be used to calculate real time from the tick * rate - with the resolution of one tick period. * * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the * task was last unblocked. The variable must be initialised with the current time * prior to its first use (see the example below). Following this the variable is * automatically updated within vTaskDelayUntil (). * * @param xTimeIncrement The cycle time period. The task will be unblocked at * time pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the same xTimeIncrement parameter value will cause the task to execute with * a fixed interface period. * * Example usage: <pre> // Perform an action every 10 ticks. void vTaskFunction( void * pvParameters ) { portTickType xLastWakeTime; const portTickType xFrequency = 10; // Initialise the xLastWakeTime variable with the current time. xLastWakeTime = xTaskGetTickCount (); for( ;; ) { // Wait for the next cycle. vTaskDelayUntil( &xLastWakeTime, xFrequency ); // Perform action here. } } </pre> * \defgroup vTaskDelayUntil vTaskDelayUntil * \ingroup TaskCtrl / void vTaskDelayUntil( portTickType const pxPreviousWakeTime, portTickType xTimeIncrement ) PRIVILEGED_FUNCTION; /** * task. h * <pre>unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );</pre> * * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. * See the configuration section for more information. * * Obtain the priority of any task. * * @param pxTask Handle of the task to be queried. Passing a NULL * handle results in the priority of the calling task being returned. * * @return The priority of pxTask. * * Example usage: <pre> void vAFunction( void ) { xTaskHandle xHandle; // Create a task, storing the handle. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); // ... // Use the handle to obtain the priority of the created task. // It was created with tskIDLE_PRIORITY, but may have changed // it itself. if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY ) { // The task has changed it's priority. } // ... // Is our priority higher than the created task? if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) ) { // Our priority (obtained using NULL handle) is higher. } } </pre> * \defgroup uxTaskPriorityGet uxTaskPriorityGet * \ingroup TaskCtrl / unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) PRIVILEGED_FUNCTION; /* * task. h * <pre>void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );</pre> * * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. * See the configuration section for more information. * * Set the priority of any task. * * A context switch will occur before the function returns if the priority * being set is higher than the currently executing task. * * @param pxTask Handle to the task for which the priority is being set. * Passing a NULL handle results in the priority of the calling task being set. * * @param uxNewPriority The priority to which the task will be set. * * Example usage: <pre> void vAFunction( void ) { xTaskHandle xHandle; // Create a task, storing the handle. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); // ... // Use the handle to raise the priority of the created task. vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 ); // ... // Use a NULL handle to raise our priority to the same value. vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 ); } </pre> * \defgroup vTaskPrioritySet vTaskPrioritySet * \ingroup TaskCtrl / void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) PRIVILEGED_FUNCTION; /* * task. h * <pre>void vTaskSuspend( xTaskHandle pxTaskToSuspend );</pre> * * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. * See the configuration section for more information. * * Suspend any task. When suspended a task will never get any microcontroller * processing time, no matter what its priority. * * Calls to vTaskSuspend are not accumulative - * i.e. calling vTaskSuspend () twice on the same task still only requires one * call to vTaskResume () to ready the suspended task. * * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL * handle will cause the calling task to be suspended. * * Example usage: <pre> void vAFunction( void ) { xTaskHandle xHandle; // Create a task, storing the handle. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); // ... // Use the handle to suspend the created task. vTaskSuspend( xHandle ); // ... // The created task will not run during this period, unless // another task calls vTaskResume( xHandle ). //... // Suspend ourselves. vTaskSuspend( NULL ); // We cannot get here unless another task calls vTaskResume // with our handle as the parameter. } </pre> * \defgroup vTaskSuspend vTaskSuspend * \ingroup TaskCtrl / void vTaskSuspend( xTaskHandle pxTaskToSuspend ) PRIVILEGED_FUNCTION; /* * task. h * <pre>void vTaskResume( xTaskHandle pxTaskToResume );</pre> * * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. * See the configuration section for more information. * * Resumes a suspended task. * * A task that has been suspended by one of more calls to vTaskSuspend () * will be made available for running again by a single call to * vTaskResume (). * * @param pxTaskToResume Handle to the task being readied. * * Example usage: <pre> void vAFunction( void ) { xTaskHandle xHandle; // Create a task, storing the handle. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); // ... // Use the handle to suspend the created task. vTaskSuspend( xHandle ); // ... // The created task will not run during this period, unless // another task calls vTaskResume( xHandle ). //... // Resume the suspended task ourselves. vTaskResume( xHandle ); // The created task will once again get microcontroller processing // time in accordance with it priority within the system. } </pre> * \defgroup vTaskResume vTaskResume * \ingroup TaskCtrl / void vTaskResume( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION; /* * task. h * <pre>void xTaskResumeFromISR( xTaskHandle pxTaskToResume );</pre> * * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be * available. See the configuration section for more information. * * An implementation of vTaskResume() that can be called from within an ISR. * * A task that has been suspended by one of more calls to vTaskSuspend () * will be made available for running again by a single call to * xTaskResumeFromISR (). * * @param pxTaskToResume Handle to the task being readied. * * \defgroup vTaskResumeFromISR vTaskResumeFromISR * \ingroup TaskCtrl / portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION; /----------------------------------------------------------- * SCHEDULER CONTROL ----------------------------------------------------------/ /** * task. h * <pre>void vTaskStartScheduler( void );</pre> * * Starts the real time kernel tick processing. After calling the kernel * has control over which tasks are executed and when. This function * does not return until an executing task calls vTaskEndScheduler (). * * At least one task should be created via a call to xTaskCreate () * before calling vTaskStartScheduler (). The idle task is created * automatically when the first application task is created. * * See the demo application file main.c for an example of creating * tasks and starting the kernel. * * Example usage: <pre> void vAFunction( void ) { // Create at least one task before starting the kernel. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); // Start the real time kernel with preemption. vTaskStartScheduler (); // Will not get here unless a task calls vTaskEndScheduler () } </pre> * * \defgroup vTaskStartScheduler vTaskStartScheduler * \ingroup SchedulerControl / void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; /* * task. h * <pre>void vTaskEndScheduler( void );</pre> * * Stops the real time kernel tick. All created tasks will be automatically * deleted and multitasking (either preemptive or cooperative) will * stop. Execution then resumes from the point where vTaskStartScheduler () * was called, as if vTaskStartScheduler () had just returned. * * See the demo application file main. c in the demo/PC directory for an * example that uses vTaskEndScheduler (). * * vTaskEndScheduler () requires an exit function to be defined within the * portable layer (see vPortEndScheduler () in port. c for the PC port). This * performs hardware specific operations such as stopping the kernel tick. * * vTaskEndScheduler () will cause all of the resources allocated by the * kernel to be freed - but will not free resources allocated by application * tasks. * * Example usage: <pre> void vTaskCode( void * pvParameters ) { for( ;; ) { // Task code goes here. // At some point we want to end the real time kernel processing // so call ... vTaskEndScheduler (); } } void vAFunction( void ) { // Create at least one task before starting the kernel. xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); // Start the real time kernel with preemption. vTaskStartScheduler (); // Will only get here when the vTaskCode () task has called // vTaskEndScheduler (). When we get here we are back to single task // execution. } </pre> * * \defgroup vTaskEndScheduler vTaskEndScheduler * \ingroup SchedulerControl / void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; /* * task. h * <pre>void vTaskSuspendAll( void );</pre> * * Suspends all real time kernel activity while keeping interrupts (including the * kernel tick) enabled. * * After calling vTaskSuspendAll () the calling task will continue to execute * without risk of being swapped out until a call to xTaskResumeAll () has been * made. * * API functions that have the potential to cause a context switch (for example, * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler * is suspended. * * Example usage: <pre> void vTask1( void * pvParameters ) { for( ;; ) { // Task code goes here. // ... // At some point the task wants to perform a long operation during // which it does not want to get swapped out. It cannot use // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the // operation may cause interrupts to be missed - including the // ticks. // Prevent the real time kernel swapping out the task. vTaskSuspendAll (); // Perform the operation here. There is no need to use critical // sections as we have all the microcontroller processing time. // During this time interrupts will still operate and the kernel // tick count will be maintained. // ... // The operation is complete. Restart the kernel. xTaskResumeAll (); } } </pre> * \defgroup vTaskSuspendAll vTaskSuspendAll * \ingroup SchedulerControl / void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; /* * task. h * <pre>char xTaskResumeAll( void );</pre> * * Resumes real time kernel activity following a call to vTaskSuspendAll (). * After a call to vTaskSuspendAll () the kernel will take control of which * task is executing at any time. * * @return If resuming the scheduler caused a context switch then pdTRUE is * returned, otherwise pdFALSE is returned. * * Example usage: <pre> void vTask1( void * pvParameters ) { for( ;; ) { // Task code goes here. // ... // At some point the task wants to perform a long operation during // which it does not want to get swapped out. It cannot use // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the // operation may cause interrupts to be missed - including the // ticks. // Prevent the real time kernel swapping out the task. vTaskSuspendAll (); // Perform the operation here. There is no need to use critical // sections as we have all the microcontroller processing time. // During this time interrupts will still operate and the real // time kernel tick count will be maintained. // ... // The operation is complete. Restart the kernel. We want to force // a context switch - but there is no point if resuming the scheduler // caused a context switch already. if( !xTaskResumeAll () ) { taskYIELD (); } } } </pre> * \defgroup xTaskResumeAll xTaskResumeAll * \ingroup SchedulerControl / signed portBASE_TYPE xTaskResumeAll( void ) PRIVILEGED_FUNCTION; /* * task. h * <pre>signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask );</pre> * * Utility task that simply returns pdTRUE if the task referenced by xTask is * currently in the Suspended state, or pdFALSE if the task referenced by xTask * is in any other state. * / signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask ) PRIVILEGED_FUNCTION; /----------------------------------------------------------- * TASK UTILITIES ----------------------------------------------------------/ /** * task. h * <PRE>portTickType xTaskGetTickCount( void );</PRE> * * @return The count of ticks since vTaskStartScheduler was called. * * \page xTaskGetTickCount xTaskGetTickCount * \ingroup TaskUtils / portTickType xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; /* * task. h * <PRE>portTickType xTaskGetTickCountFromISR( void );</PRE> * * @return The count of ticks since vTaskStartScheduler was called. * * This is a version of xTaskGetTickCount() that is safe to be called from an * ISR - provided that portTickType is the natural word size of the * microcontroller being used or interrupt nesting is either not supported or * not being used. * * \page xTaskGetTickCount xTaskGetTickCount * \ingroup TaskUtils / portTickType xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; /* * task. h * <PRE>unsigned short uxTaskGetNumberOfTasks( void );</PRE> * * @return The number of tasks that the real time kernel is currently managing. * This includes all ready, blocked and suspended tasks. A task that * has been deleted but not yet freed by the idle task will also be * included in the count. * * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks * \ingroup TaskUtils / unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; /* * task. h * <PRE>signed char pcTaskGetTaskName( xTaskHandle xTaskToQuery );</PRE> * @return The text (human readable) name of the task referenced by the handle * xTaskToQueury. A task can query its own name by either passing in its own * handle, or by setting xTaskToQuery to NULL. INCLUDE_pcTaskGetTaskName must be * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available. * * \page pcTaskGetTaskName pcTaskGetTaskName * \ingroup TaskUtils / signed char pcTaskGetTaskName( xTaskHandle xTaskToQuery ); /** * task. h * <PRE>void vTaskList( char pcWriteBuffer );</PRE> * configUSE_TRACE_FACILITY must be defined as 1 for this function to be * available. See the configuration section for more information. * * NOTE: This function will disable interrupts for its duration. It is * not intended for normal application runtime use but as a debug aid. * * Lists all the current tasks, along with their current state and stack * usage high water mark. * * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or * suspended ('S'). * * @param pcWriteBuffer A buffer into which the above mentioned details * will be written, in ascii form. This buffer is assumed to be large * enough to contain the generated report. Approximately 40 bytes per * task should be sufficient. * * \page vTaskList vTaskList * \ingroup TaskUtils / void vTaskList( signed char pcWriteBuffer ) PRIVILEGED_FUNCTION; /** * task. h * <PRE>void vTaskGetRunTimeStats( char pcWriteBuffer );</PRE> * configGENERATE_RUN_TIME_STATS must be defined as 1 for this function * to be available. The application must also then provide definitions * for portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and * portGET_RUN_TIME_COUNTER_VALUE to configure a peripheral timer/counter * and return the timers current count value respectively. The counter * should be at least 10 times the frequency of the tick count. * * NOTE: This function will disable interrupts for its duration. It is * not intended for normal application runtime use but as a debug aid. * * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total * accumulated execution time being stored for each task. The resolution * of the accumulated time value depends on the frequency of the timer * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. * Calling vTaskGetRunTimeStats() writes the total execution time of each * task into a buffer, both as an absolute count value and as a percentage * of the total system execution time. * * @param pcWriteBuffer A buffer into which the execution times will be * written, in ascii form. This buffer is assumed to be large enough to * contain the generated report. Approximately 40 bytes per task should * be sufficient. * * \page vTaskGetRunTimeStats vTaskGetRunTimeStats * \ingroup TaskUtils / void vTaskGetRunTimeStats( signed char pcWriteBuffer ) PRIVILEGED_FUNCTION; /** * task. h * <PRE>void vTaskStartTrace( char * pcBuffer, unsigned portBASE_TYPE uxBufferSize );</PRE> * * Starts a real time kernel activity trace. The trace logs the identity of * which task is running when. * * The trace file is stored in binary format. A separate DOS utility called * convtrce.exe is used to convert this into a tab delimited text file which * can be viewed and plotted in a spread sheet. * * @param pcBuffer The buffer into which the trace will be written. * * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue * until either the buffer in full, or ulTaskEndTrace () is called. * * \page vTaskStartTrace vTaskStartTrace * \ingroup TaskUtils / void vTaskStartTrace( signed char pcBuffer, unsigned long ulBufferSize ) PRIVILEGED_FUNCTION; /** * task. h * <PRE>unsigned long ulTaskEndTrace( void );</PRE> * * Stops a kernel activity trace. See vTaskStartTrace (). * * @return The number of bytes that have been written into the trace buffer. * * \page usTaskEndTrace usTaskEndTrace * \ingroup TaskUtils / unsigned long ulTaskEndTrace( void ) PRIVILEGED_FUNCTION; /* * task.h * <PRE>unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask );</PRE> * * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for * this function to be available. * * Returns the high water mark of the stack associated with xTask. That is, * the minimum free stack space there has been (in words, so on a 32 bit machine * a value of 1 means 4 bytes) since the task started. The smaller the returned * number the closer the task has come to overflowing its stack. * * @param xTask Handle of the task associated with the stack to be checked. * Set xTask to NULL to check the stack of the calling task. * * @return The smallest amount of free stack space there has been (in bytes) * since the task referenced by xTask was created. / unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask ) PRIVILEGED_FUNCTION; / When using trace macros it is sometimes necessary to include tasks.h before FreeRTOS.h. When this is done pdTASK_HOOK_CODE will not yet have been defined, so the following two prototypes will cause a compilation error. This can be fixed by simply guarding against the inclusion of these two prototypes unless they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration constant. / #ifdef configUSE_APPLICATION_TASK_TAG #if configUSE_APPLICATION_TASK_TAG == 1 /* * task.h * <pre>void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );</pre> * * Sets pxHookFunction to be the task hook function used by the task xTask. * Passing xTask as NULL has the effect of setting the calling tasks hook * function. / void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction ) PRIVILEGED_FUNCTION; /* * task.h * <pre>void xTaskGetApplicationTaskTag( xTaskHandle xTask );</pre> * * Returns the pxHookFunction value assigned to the task xTask. / pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask ) PRIVILEGED_FUNCTION; #endif / configUSE_APPLICATION_TASK_TAG ==1 / #endif / ifdef configUSE_APPLICATION_TASK_TAG / /* * task.h * <pre>portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );</pre> * * Calls the hook function associated with xTask. Passing xTask as NULL has * the effect of calling the Running tasks (the calling task) hook function. * * pvParameter is passed to the hook function for the task to interpret as it * wants. / portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void pvParameter ) PRIVILEGED_FUNCTION; /** * xTaskGetIdleTaskHandle() is only available if * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. * * Simply returns the handle of the idle task. It is not valid to call * xTaskGetIdleTaskHandle() before the scheduler has been started. / xTaskHandle xTaskGetIdleTaskHandle( void ); /----------------------------------------------------------- * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES ----------------------------------------------------------/ /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. * * Called from the real time kernel tick (either preemptive or cooperative), * this increments the tick count and checks if any tasks that are blocked * for a finite period required removing from a blocked list and placing on * a ready list. / void vTaskIncrementTick( void ) PRIVILEGED_FUNCTION; / * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. * * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. * * Removes the calling task from the ready list and places it both * on the list of tasks waiting for a particular event, and the * list of delayed tasks. The task will be removed from both lists * and replaced on the ready list should either the event occur (and * there be no higher priority tasks waiting on the same event) or * the delay period expires. * * @param pxEventList The list containing tasks that are blocked waiting * for the event to occur. * * @param xTicksToWait The maximum amount of time that the task should wait * for the event to occur. This is specified in kernel ticks,the constant * portTICK_RATE_MS can be used to convert kernel ticks into a real time * period. / void vTaskPlaceOnEventList( const xList const pxEventList, portTickType xTicksToWait ) PRIVILEGED_FUNCTION; /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. * * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. * * This function performs nearly the same function as vTaskPlaceOnEventList(). * The difference being that this function does not permit tasks to block * indefinitely, whereas vTaskPlaceOnEventList() does. * * @return pdTRUE if the task being removed has a higher priority than the task * making the call, otherwise pdFALSE. / void vTaskPlaceOnEventListRestricted( const xList const pxEventList, portTickType xTicksToWait ) PRIVILEGED_FUNCTION; /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. * * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. * * Removes a task from both the specified event list and the list of blocked * tasks, and places it on a ready queue. * * xTaskRemoveFromEventList () will be called if either an event occurs to * unblock a task, or the block timeout period expires. * * @return pdTRUE if the task being removed has a higher priority than the task * making the call, otherwise pdFALSE. / signed portBASE_TYPE xTaskRemoveFromEventList( const xList const pxEventList ) PRIVILEGED_FUNCTION; /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. * * Sets the pointer to the current TCB to the TCB of the highest priority task * that is ready to run. / void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; / * Return the handle of the calling task. / xTaskHandle xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; / * Capture the current time status for future reference. / void vTaskSetTimeOutState( xTimeOutType const pxTimeOut ) PRIVILEGED_FUNCTION; /* * Compare the time status now with that previously captured to see if the * timeout has expired. / portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType const pxTimeOut, portTickType * const pxTicksToWait ) PRIVILEGED_FUNCTION; /* * Shortcut used by the queue implementation to prevent unnecessary call to * taskYIELD(); / void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; / * Returns the scheduler state as taskSCHEDULER_RUNNING, * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. / portBASE_TYPE xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; / * Raises the priority of the mutex holder to that of the calling task should * the mutex holder have a priority less than the calling task. / void vTaskPriorityInherit( xTaskHandle const pxMutexHolder ) PRIVILEGED_FUNCTION; /* * Set the priority of a task back to its proper priority in the case that it * inherited a higher priority while it was holding a semaphore. / void vTaskPriorityDisinherit( xTaskHandle const pxMutexHolder ) PRIVILEGED_FUNCTION; /* * Generic version of the task creation function which is in turn called by the * xTaskCreate() and xTaskCreateRestricted() macros. / signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pxTaskCode, const signed char const pcName, unsigned short usStackDepth, void pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle pxCreatedTask, portSTACK_TYPE puxStackBuffer, const xMemoryRegion const xRegions ) PRIVILEGED_FUNCTION; #ifdef __cplusplus } #endif #endif /* TASK_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/task.h	C	oos	46,909
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / /----------------------------------------------------------- * Portable layer API. Each function must be defined for each port. ----------------------------------------------------------/ #ifndef PORTABLE_H #define PORTABLE_H /* Include the macro file relevant to the port being used. / #ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" typedef void ( __interrupt __far pxISR )(); #endif #ifdef OPEN_WATCOM_FLASH_LITE_186_PORT #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" typedef void ( __interrupt __far pxISR )(); #endif #ifdef GCC_MEGA_AVR #include "../portable/GCC/ATMega323/portmacro.h" #endif #ifdef IAR_MEGA_AVR #include "../portable/IAR/ATMega323/portmacro.h" #endif #ifdef MPLAB_PIC24_PORT #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" #endif #ifdef MPLAB_DSPIC_PORT #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" #endif #ifdef MPLAB_PIC18F_PORT #include "..\..\Source\portable\MPLAB\PIC18F\portmacro.h" #endif #ifdef MPLAB_PIC32MX_PORT #include "..\..\Source\portable\MPLAB\PIC32MX\portmacro.h" #endif #ifdef _FEDPICC #include "libFreeRTOS/Include/portmacro.h" #endif #ifdef SDCC_CYGNAL #include "../../Source/portable/SDCC/Cygnal/portmacro.h" #endif #ifdef GCC_ARM7 #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" #endif #ifdef GCC_ARM7_ECLIPSE #include "portmacro.h" #endif #ifdef ROWLEY_LPC23xx #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" #endif #ifdef IAR_MSP430 #include "..\..\Source\portable\IAR\MSP430\portmacro.h" #endif #ifdef GCC_MSP430 #include "../../Source/portable/GCC/MSP430F449/portmacro.h" #endif #ifdef ROWLEY_MSP430 #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" #endif #ifdef ARM7_LPC21xx_KEIL_RVDS #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" #endif #ifdef SAM7_GCC #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" #endif #ifdef SAM7_IAR #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" #endif #ifdef SAM9XE_IAR #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" #endif #ifdef LPC2000_IAR #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" #endif #ifdef STR71X_IAR #include "..\..\Source\portable\IAR\STR71x\portmacro.h" #endif #ifdef STR75X_IAR #include "..\..\Source\portable\IAR\STR75x\portmacro.h" #endif #ifdef STR75X_GCC #include "..\..\Source\portable\GCC\STR75x\portmacro.h" #endif #ifdef STR91X_IAR #include "..\..\Source\portable\IAR\STR91x\portmacro.h" #endif #ifdef GCC_H8S #include "../../Source/portable/GCC/H8S2329/portmacro.h" #endif #ifdef GCC_AT91FR40008 #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" #endif #ifdef RVDS_ARMCM3_LM3S102 #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" #endif #ifdef GCC_ARMCM3_LM3S102 #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" #endif #ifdef GCC_ARMCM3 #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" #endif #ifdef IAR_ARM_CM3 #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" #endif #ifdef IAR_ARMCM3_LM #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" #endif #ifdef HCS12_CODE_WARRIOR #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" #endif #ifdef MICROBLAZE_GCC #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" #endif #ifdef TERN_EE #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" #endif #ifdef GCC_HCS12 #include "../../Source/portable/GCC/HCS12/portmacro.h" #endif #ifdef GCC_MCF5235 #include "../../Source/portable/GCC/MCF5235/portmacro.h" #endif #ifdef COLDFIRE_V2_GCC #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" #endif #ifdef COLDFIRE_V2_CODEWARRIOR #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" #endif #ifdef GCC_PPC405 #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" #endif #ifdef GCC_PPC440 #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" #endif #ifdef _16FX_SOFTUNE #include "..\..\Source\portable\Softune\MB96340\portmacro.h" #endif #ifdef BCC_INDUSTRIAL_PC_PORT / A short file name has to be used in place of the normal FreeRTOSConfig.h when using the Borland compiler. / #include "frconfig.h" #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" typedef void ( __interrupt __far pxISR )(); #endif #ifdef BCC_FLASH_LITE_186_PORT /* A short file name has to be used in place of the normal FreeRTOSConfig.h when using the Borland compiler. / #include "frconfig.h" #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" typedef void ( __interrupt __far pxISR )(); #endif #ifdef __GNUC__ #ifdef __AVR32_AVR32A__ #include "portmacro.h" #endif #endif #ifdef __ICCAVR32__ #ifdef __CORE__ #if __CORE__ == __AVR32A__ #include "portmacro.h" #endif #endif #endif #ifdef __91467D #include "portmacro.h" #endif #ifdef __96340 #include "portmacro.h" #endif #ifdef __IAR_V850ES_Fx3__ #include "../../Source/portable/IAR/V850ES/portmacro.h" #endif #ifdef __IAR_V850ES_Jx3__ #include "../../Source/portable/IAR/V850ES/portmacro.h" #endif #ifdef __IAR_V850ES_Jx3_L__ #include "../../Source/portable/IAR/V850ES/portmacro.h" #endif #ifdef __IAR_V850ES_Jx2__ #include "../../Source/portable/IAR/V850ES/portmacro.h" #endif #ifdef __IAR_V850ES_Hx2__ #include "../../Source/portable/IAR/V850ES/portmacro.h" #endif #ifdef __IAR_78K0R_Kx3__ #include "../../Source/portable/IAR/78K0R/portmacro.h" #endif #ifdef __IAR_78K0R_Kx3L__ #include "../../Source/portable/IAR/78K0R/portmacro.h" #endif /* Catch all to ensure portmacro.h is included in the build. Newer demos have the path as part of the project options, rather than as relative from the project location. If portENTER_CRITICAL() has not been defined then portmacro.h has not yet been included - as every portmacro.h provides a portENTER_CRITICAL() definition. Check the demo application for your demo to find the path to the correct portmacro.h file. / #ifndef portENTER_CRITICAL #include "portmacro.h" #endif #if portBYTE_ALIGNMENT == 8 #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) #endif #if portBYTE_ALIGNMENT == 4 #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) #endif #if portBYTE_ALIGNMENT == 2 #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) #endif #if portBYTE_ALIGNMENT == 1 #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) #endif #ifndef portBYTE_ALIGNMENT_MASK #error "Invalid portBYTE_ALIGNMENT definition" #endif #ifndef portNUM_CONFIGURABLE_REGIONS #define portNUM_CONFIGURABLE_REGIONS 1 #endif #ifdef __cplusplus extern "C" { #endif #include "mpu_wrappers.h" / * Setup the stack of a new task so it is ready to be placed under the * scheduler control. The registers have to be placed on the stack in * the order that the port expects to find them. * / #if( portUSING_MPU_WRAPPERS == 1 ) portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters, portBASE_TYPE xRunPrivileged ) PRIVILEGED_FUNCTION; #else portSTACK_TYPE pxPortInitialiseStack( portSTACK_TYPE pxTopOfStack, pdTASK_CODE pxCode, void pvParameters ); #endif / * Map to the memory management routines required for the port. / void pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; void vPortFree( void pv ) PRIVILEGED_FUNCTION; void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; / * Setup the hardware ready for the scheduler to take control. This generally * sets up a tick interrupt and sets timers for the correct tick frequency. / portBASE_TYPE xPortStartScheduler( void ) PRIVILEGED_FUNCTION; / * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so * the hardware is left in its original condition after the scheduler stops * executing. / void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; / * The structures and methods of manipulating the MPU are contained within the * port layer. * * Fills the xMPUSettings structure with the memory region information * contained in xRegions. / #if( portUSING_MPU_WRAPPERS == 1 ) struct xMEMORY_REGION; void vPortStoreTaskMPUSettings( xMPU_SETTINGS xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE pxBottomOfStack, unsigned short usStackDepth ) PRIVILEGED_FUNCTION; #endif #ifdef __cplusplus } #endif #endif / PORTABLE_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/portable.h	C	oos	11,780
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef INC_FREERTOS_H #define INC_FREERTOS_H / * Include the generic headers required for the FreeRTOS port being used. / #include <stddef.h> / Basic FreeRTOS definitions. / #include "projdefs.h" / Application specific configuration options. / #include "FreeRTOSConfig.h" / Definitions specific to the port being used. / #include "portable.h" / Defines the prototype to which the application task hook function must conform. / typedef portBASE_TYPE (pdTASK_HOOK_CODE)( void * ); /* * Check all the required application specific macros have been defined. * These macros are application specific and (as downloaded) are defined * within FreeRTOSConfig.h. / #ifndef configUSE_PREEMPTION #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef configUSE_IDLE_HOOK #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef configUSE_TICK_HOOK #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef configUSE_CO_ROUTINES #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef INCLUDE_vTaskPrioritySet #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef INCLUDE_uxTaskPriorityGet #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef INCLUDE_vTaskDelete #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef INCLUDE_vTaskSuspend #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef INCLUDE_vTaskDelayUntil #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef INCLUDE_vTaskDelay #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef configUSE_16_BIT_TICKS #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif #ifndef INCLUDE_xTaskGetIdleTaskHandle #define INCLUDE_xTaskGetIdleTaskHandle 0 #endif #ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 #endif #ifndef INCLUDE_pcTaskGetTaskName #define INCLUDE_pcTaskGetTaskName 0 #endif #ifndef configUSE_APPLICATION_TASK_TAG #define configUSE_APPLICATION_TASK_TAG 0 #endif #ifndef INCLUDE_uxTaskGetStackHighWaterMark #define INCLUDE_uxTaskGetStackHighWaterMark 0 #endif #ifndef configUSE_RECURSIVE_MUTEXES #define configUSE_RECURSIVE_MUTEXES 0 #endif #ifndef configUSE_MUTEXES #define configUSE_MUTEXES 0 #endif #ifndef configUSE_TIMERS #define configUSE_TIMERS 0 #endif #ifndef configUSE_COUNTING_SEMAPHORES #define configUSE_COUNTING_SEMAPHORES 0 #endif #ifndef configUSE_ALTERNATIVE_API #define configUSE_ALTERNATIVE_API 0 #endif #ifndef portCRITICAL_NESTING_IN_TCB #define portCRITICAL_NESTING_IN_TCB 0 #endif #ifndef configMAX_TASK_NAME_LEN #define configMAX_TASK_NAME_LEN 16 #endif #ifndef configIDLE_SHOULD_YIELD #define configIDLE_SHOULD_YIELD 1 #endif #if configMAX_TASK_NAME_LEN < 1 #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h #endif #ifndef INCLUDE_xTaskResumeFromISR #define INCLUDE_xTaskResumeFromISR 1 #endif #ifndef configASSERT #define configASSERT( x ) #endif / The timers module relies on xTaskGetSchedulerState(). / #if configUSE_TIMERS == 1 #ifndef configTIMER_TASK_PRIORITY #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. #endif / configTIMER_TASK_PRIORITY / #ifndef configTIMER_QUEUE_LENGTH #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. #endif / configTIMER_QUEUE_LENGTH / #ifndef configTIMER_TASK_STACK_DEPTH #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. #endif / configTIMER_TASK_STACK_DEPTH / #endif / configUSE_TIMERS / #ifndef INCLUDE_xTaskGetSchedulerState #define INCLUDE_xTaskGetSchedulerState 0 #endif #ifndef INCLUDE_xTaskGetCurrentTaskHandle #define INCLUDE_xTaskGetCurrentTaskHandle 0 #endif #ifndef portSET_INTERRUPT_MASK_FROM_ISR #define portSET_INTERRUPT_MASK_FROM_ISR() 0 #endif #ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue #endif #ifndef configQUEUE_REGISTRY_SIZE #define configQUEUE_REGISTRY_SIZE 0U #endif #if ( configQUEUE_REGISTRY_SIZE < 1 ) #define vQueueAddToRegistry( xQueue, pcName ) #define vQueueUnregisterQueue( xQueue ) #endif #ifndef portPOINTER_SIZE_TYPE #define portPOINTER_SIZE_TYPE unsigned long #endif / Remove any unused trace macros. / #ifndef traceSTART / Used to perform any necessary initialisation - for example, open a file into which trace is to be written. / #define traceSTART() #endif #ifndef traceEND / Use to close a trace, for example close a file into which trace has been written. / #define traceEND() #endif #ifndef traceTASK_SWITCHED_IN / Called after a task has been selected to run. pxCurrentTCB holds a pointer to the task control block of the selected task. / #define traceTASK_SWITCHED_IN() #endif #ifndef traceTASK_SWITCHED_OUT / Called before a task has been selected to run. pxCurrentTCB holds a pointer to the task control block of the task being switched out. / #define traceTASK_SWITCHED_OUT() #endif #ifndef traceBLOCKING_ON_QUEUE_RECEIVE / Task is about to block because it cannot read from a queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore upon which the read was attempted. pxCurrentTCB points to the TCB of the task that attempted the read. / #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) #endif #ifndef traceBLOCKING_ON_QUEUE_SEND / Task is about to block because it cannot write to a queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore upon which the write was attempted. pxCurrentTCB points to the TCB of the task that attempted the write. / #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) #endif #ifndef configCHECK_FOR_STACK_OVERFLOW #define configCHECK_FOR_STACK_OVERFLOW 0 #endif / The following event macros are embedded in the kernel API calls. / #ifndef traceQUEUE_CREATE #define traceQUEUE_CREATE( pxNewQueue ) #endif #ifndef traceQUEUE_CREATE_FAILED #define traceQUEUE_CREATE_FAILED() #endif #ifndef traceCREATE_MUTEX #define traceCREATE_MUTEX( pxNewQueue ) #endif #ifndef traceCREATE_MUTEX_FAILED #define traceCREATE_MUTEX_FAILED() #endif #ifndef traceGIVE_MUTEX_RECURSIVE #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) #endif #ifndef traceGIVE_MUTEX_RECURSIVE_FAILED #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) #endif #ifndef traceTAKE_MUTEX_RECURSIVE #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) #endif #ifndef traceTAKE_MUTEX_RECURSIVE_FAILED #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) #endif #ifndef traceCREATE_COUNTING_SEMAPHORE #define traceCREATE_COUNTING_SEMAPHORE() #endif #ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED #define traceCREATE_COUNTING_SEMAPHORE_FAILED() #endif #ifndef traceQUEUE_SEND #define traceQUEUE_SEND( pxQueue ) #endif #ifndef traceQUEUE_SEND_FAILED #define traceQUEUE_SEND_FAILED( pxQueue ) #endif #ifndef traceQUEUE_RECEIVE #define traceQUEUE_RECEIVE( pxQueue ) #endif #ifndef traceQUEUE_PEEK #define traceQUEUE_PEEK( pxQueue ) #endif #ifndef traceQUEUE_RECEIVE_FAILED #define traceQUEUE_RECEIVE_FAILED( pxQueue ) #endif #ifndef traceQUEUE_SEND_FROM_ISR #define traceQUEUE_SEND_FROM_ISR( pxQueue ) #endif #ifndef traceQUEUE_SEND_FROM_ISR_FAILED #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) #endif #ifndef traceQUEUE_RECEIVE_FROM_ISR #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) #endif #ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) #endif #ifndef traceQUEUE_DELETE #define traceQUEUE_DELETE( pxQueue ) #endif #ifndef traceTASK_CREATE #define traceTASK_CREATE( pxNewTCB ) #endif #ifndef traceTASK_CREATE_FAILED #define traceTASK_CREATE_FAILED() #endif #ifndef traceTASK_DELETE #define traceTASK_DELETE( pxTaskToDelete ) #endif #ifndef traceTASK_DELAY_UNTIL #define traceTASK_DELAY_UNTIL() #endif #ifndef traceTASK_DELAY #define traceTASK_DELAY() #endif #ifndef traceTASK_PRIORITY_SET #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) #endif #ifndef traceTASK_SUSPEND #define traceTASK_SUSPEND( pxTaskToSuspend ) #endif #ifndef traceTASK_RESUME #define traceTASK_RESUME( pxTaskToResume ) #endif #ifndef traceTASK_RESUME_FROM_ISR #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) #endif #ifndef traceTASK_INCREMENT_TICK #define traceTASK_INCREMENT_TICK( xTickCount ) #endif #ifndef traceTIMER_CREATE #define traceTIMER_CREATE( pxNewTimer ) #endif #ifndef traceTIMER_CREATE_FAILED #define traceTIMER_CREATE_FAILED() #endif #ifndef traceTIMER_COMMAND_SEND #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) #endif #ifndef traceTIMER_EXPIRED #define traceTIMER_EXPIRED( pxTimer ) #endif #ifndef traceTIMER_COMMAND_RECEIVED #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) #endif #ifndef configGENERATE_RUN_TIME_STATS #define configGENERATE_RUN_TIME_STATS 0 #endif #if ( configGENERATE_RUN_TIME_STATS == 1 ) #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. #endif / portCONFIGURE_TIMER_FOR_RUN_TIME_STATS / #ifndef portGET_RUN_TIME_COUNTER_VALUE #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. #endif / portALT_GET_RUN_TIME_COUNTER_VALUE / #endif / portGET_RUN_TIME_COUNTER_VALUE / #endif / configGENERATE_RUN_TIME_STATS / #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() #endif #ifndef configUSE_MALLOC_FAILED_HOOK #define configUSE_MALLOC_FAILED_HOOK 0 #endif #ifndef portPRIVILEGE_BIT #define portPRIVILEGE_BIT ( ( unsigned portBASE_TYPE ) 0x00 ) #endif #ifndef portYIELD_WITHIN_API #define portYIELD_WITHIN_API portYIELD #endif #ifndef pvPortMallocAligned #define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) ) #endif #ifndef vPortFreeAligned #define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree ) #endif #endif / INC_FREERTOS_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/FreeRTOS.h	C	oos	15,417
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef STACK_MACROS_H #define STACK_MACROS_H / * Call the stack overflow hook function if the stack of the task being swapped * out is currently overflowed, or looks like it might have overflowed in the * past. * * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check * the current stack state only - comparing the current top of stack value to * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 * will also cause the last few stack bytes to be checked to ensure the value * to which the bytes were set when the task was created have not been * overwritten. Note this second test does not guarantee that an overflowed * stack will always be recognised. / /-----------------------------------------------------------/ #if( configCHECK_FOR_STACK_OVERFLOW == 0 ) / FreeRTOSConfig.h is not set to check for stack overflows. / #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() #endif / configCHECK_FOR_STACK_OVERFLOW == 0 / /-----------------------------------------------------------/ #if( configCHECK_FOR_STACK_OVERFLOW == 1 ) / FreeRTOSConfig.h is only set to use the first method of overflow checking. / #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() #endif /-----------------------------------------------------------/ #if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) ) / Only the current stack state is to be checked. / #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \ { \ / Is the currently saved stack pointer within the stack limit? / \ if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ { \ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ } \ } #endif / configCHECK_FOR_STACK_OVERFLOW > 0 / /-----------------------------------------------------------/ #if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) ) / Only the current stack state is to be checked. / #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \ { \ \ / Is the currently saved stack pointer within the stack limit? / \ if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ { \ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ } \ } #endif / configCHECK_FOR_STACK_OVERFLOW == 1 / /-----------------------------------------------------------/ #if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \ { \ static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ \ \ / Has the extremity of the task stack ever been written over? / \ if( memcmp( ( void ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ { \ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ } \ } #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) / /-----------------------------------------------------------/ #if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \ { \ char pcEndOfStack = ( char * ) pxCurrentTCB->pxEndOfStack; \ static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ \ \ pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ \ /* Has the extremity of the task stack ever been written over? / \ if( memcmp( ( void ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ { \ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ } \ } #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) / /-----------------------------------------------------------/ #endif / STACK_MACROS_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/StackMacros.h	C	oos	8,580
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef SEMAPHORE_H #define SEMAPHORE_H #ifndef INC_FREERTOS_H #error "#include FreeRTOS.h" must appear in source files before "#include semphr.h" #endif #include "queue.h" typedef xQueueHandle xSemaphoreHandle; #define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned char ) 1U ) #define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned char ) 0U ) #define semGIVE_BLOCK_TIME ( ( portTickType ) 0U ) /* * semphr. h * <pre>vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )</pre> * * <i>Macro</i> that implements a semaphore by using the existing queue mechanism. * The queue length is 1 as this is a binary semaphore. The data size is 0 * as we don't want to actually store any data - we just want to know if the * queue is empty or full. * * This type of semaphore can be used for pure synchronisation between tasks or * between an interrupt and a task. The semaphore need not be given back once * obtained, so one task/interrupt can continuously 'give' the semaphore while * another continuously 'takes' the semaphore. For this reason this type of * semaphore does not use a priority inheritance mechanism. For an alternative * that does use priority inheritance see xSemaphoreCreateMutex(). * * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. * * Example usage: <pre> xSemaphoreHandle xSemaphore; void vATask( void * pvParameters ) { // Semaphore cannot be used before a call to vSemaphoreCreateBinary (). // This is a macro so pass the variable in directly. vSemaphoreCreateBinary( xSemaphore ); if( xSemaphore != NULL ) { // The semaphore was created successfully. // The semaphore can now be used. } } </pre> * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary * \ingroup Semaphores / #define vSemaphoreCreateBinary( xSemaphore ) { \ ( xSemaphore ) = xQueueCreate( ( unsigned portBASE_TYPE ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ if( ( xSemaphore ) != NULL ) \ { \ xSemaphoreGive( ( xSemaphore ) ); \ } \ } /* * semphr. h * <pre>xSemaphoreTake( * xSemaphoreHandle xSemaphore, * portTickType xBlockTime * )</pre> * * <i>Macro</i> to obtain a semaphore. The semaphore must have previously been * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or * xSemaphoreCreateCounting(). * * @param xSemaphore A handle to the semaphore being taken - obtained when * the semaphore was created. * * @param xBlockTime The time in ticks to wait for the semaphore to become * available. The macro portTICK_RATE_MS can be used to convert this to a * real time. A block time of zero can be used to poll the semaphore. A block * time of portMAX_DELAY can be used to block indefinitely (provided * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). * * @return pdTRUE if the semaphore was obtained. pdFALSE * if xBlockTime expired without the semaphore becoming available. * * Example usage: <pre> xSemaphoreHandle xSemaphore = NULL; // A task that creates a semaphore. void vATask( void * pvParameters ) { // Create the semaphore to guard a shared resource. vSemaphoreCreateBinary( xSemaphore ); } // A task that uses the semaphore. void vAnotherTask( void * pvParameters ) { // ... Do other things. if( xSemaphore != NULL ) { // See if we can obtain the semaphore. If the semaphore is not available // wait 10 ticks to see if it becomes free. if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE ) { // We were able to obtain the semaphore and can now access the // shared resource. // ... // We have finished accessing the shared resource. Release the // semaphore. xSemaphoreGive( xSemaphore ); } else { // We could not obtain the semaphore and can therefore not access // the shared resource safely. } } } </pre> * \defgroup xSemaphoreTake xSemaphoreTake * \ingroup Semaphores / #define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueGenericReceive( ( xQueueHandle ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE ) /* * semphr. h * xSemaphoreTakeRecursive( * xSemaphoreHandle xMutex, * portTickType xBlockTime * ) * * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore. * The mutex must have previously been created using a call to * xSemaphoreCreateRecursiveMutex(); * * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this * macro to be available. * * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). * * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex * doesn't become available again until the owner has called * xSemaphoreGiveRecursive() for each successful 'take' request. For example, * if a task successfully 'takes' the same mutex 5 times then the mutex will * not be available to any other task until it has also 'given' the mutex back * exactly five times. * * @param xMutex A handle to the mutex being obtained. This is the * handle returned by xSemaphoreCreateRecursiveMutex(); * * @param xBlockTime The time in ticks to wait for the semaphore to become * available. The macro portTICK_RATE_MS can be used to convert this to a * real time. A block time of zero can be used to poll the semaphore. If * the task already owns the semaphore then xSemaphoreTakeRecursive() will * return immediately no matter what the value of xBlockTime. * * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime * expired without the semaphore becoming available. * * Example usage: <pre> xSemaphoreHandle xMutex = NULL; // A task that creates a mutex. void vATask( void * pvParameters ) { // Create the mutex to guard a shared resource. xMutex = xSemaphoreCreateRecursiveMutex(); } // A task that uses the mutex. void vAnotherTask( void * pvParameters ) { // ... Do other things. if( xMutex != NULL ) { // See if we can obtain the mutex. If the mutex is not available // wait 10 ticks to see if it becomes free. if( xSemaphoreTakeRecursive( xSemaphore, ( portTickType ) 10 ) == pdTRUE ) { // We were able to obtain the mutex and can now access the // shared resource. // ... // For some reason due to the nature of the code further calls to // xSemaphoreTakeRecursive() are made on the same mutex. In real // code these would not be just sequential calls as this would make // no sense. Instead the calls are likely to be buried inside // a more complex call structure. xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ); xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ); // The mutex has now been 'taken' three times, so will not be // available to another task until it has also been given back // three times. Again it is unlikely that real code would have // these calls sequentially, but instead buried in a more complex // call structure. This is just for illustrative purposes. xSemaphoreGiveRecursive( xMutex ); xSemaphoreGiveRecursive( xMutex ); xSemaphoreGiveRecursive( xMutex ); // Now the mutex can be taken by other tasks. } else { // We could not obtain the mutex and can therefore not access // the shared resource safely. } } } </pre> * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive * \ingroup Semaphores / #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) / * xSemaphoreAltTake() is an alternative version of xSemaphoreTake(). * * The source code that implements the alternative (Alt) API is much * simpler because it executes everything from within a critical section. * This is the approach taken by many other RTOSes, but FreeRTOS.org has the * preferred fully featured API too. The fully featured API has more * complex code that takes longer to execute, but makes much less use of * critical sections. Therefore the alternative API sacrifices interrupt * responsiveness to gain execution speed, whereas the fully featured API * sacrifices execution speed to ensure better interrupt responsiveness. / #define xSemaphoreAltTake( xSemaphore, xBlockTime ) xQueueAltGenericReceive( ( xQueueHandle ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE ) /* * semphr. h * <pre>xSemaphoreGive( xSemaphoreHandle xSemaphore )</pre> * * <i>Macro</i> to release a semaphore. The semaphore must have previously been * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). * * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for * an alternative which can be used from an ISR. * * This macro must also not be used on semaphores created using * xSemaphoreCreateRecursiveMutex(). * * @param xSemaphore A handle to the semaphore being released. This is the * handle returned when the semaphore was created. * * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. * Semaphores are implemented using queues. An error can occur if there is * no space on the queue to post a message - indicating that the * semaphore was not first obtained correctly. * * Example usage: <pre> xSemaphoreHandle xSemaphore = NULL; void vATask( void * pvParameters ) { // Create the semaphore to guard a shared resource. vSemaphoreCreateBinary( xSemaphore ); if( xSemaphore != NULL ) { if( xSemaphoreGive( xSemaphore ) != pdTRUE ) { // We would expect this call to fail because we cannot give // a semaphore without first "taking" it! } // Obtain the semaphore - don't block if the semaphore is not // immediately available. if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) ) { // We now have the semaphore and can access the shared resource. // ... // We have finished accessing the shared resource so can free the // semaphore. if( xSemaphoreGive( xSemaphore ) != pdTRUE ) { // We would not expect this call to fail because we must have // obtained the semaphore to get here. } } } } </pre> * \defgroup xSemaphoreGive xSemaphoreGive * \ingroup Semaphores / #define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( xQueueHandle ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) /* * semphr. h * <pre>xSemaphoreGiveRecursive( xSemaphoreHandle xMutex )</pre> * * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore. * The mutex must have previously been created using a call to * xSemaphoreCreateRecursiveMutex(); * * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this * macro to be available. * * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). * * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex * doesn't become available again until the owner has called * xSemaphoreGiveRecursive() for each successful 'take' request. For example, * if a task successfully 'takes' the same mutex 5 times then the mutex will * not be available to any other task until it has also 'given' the mutex back * exactly five times. * * @param xMutex A handle to the mutex being released, or 'given'. This is the * handle returned by xSemaphoreCreateMutex(); * * @return pdTRUE if the semaphore was given. * * Example usage: <pre> xSemaphoreHandle xMutex = NULL; // A task that creates a mutex. void vATask( void * pvParameters ) { // Create the mutex to guard a shared resource. xMutex = xSemaphoreCreateRecursiveMutex(); } // A task that uses the mutex. void vAnotherTask( void * pvParameters ) { // ... Do other things. if( xMutex != NULL ) { // See if we can obtain the mutex. If the mutex is not available // wait 10 ticks to see if it becomes free. if( xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ) == pdTRUE ) { // We were able to obtain the mutex and can now access the // shared resource. // ... // For some reason due to the nature of the code further calls to // xSemaphoreTakeRecursive() are made on the same mutex. In real // code these would not be just sequential calls as this would make // no sense. Instead the calls are likely to be buried inside // a more complex call structure. xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ); xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ); // The mutex has now been 'taken' three times, so will not be // available to another task until it has also been given back // three times. Again it is unlikely that real code would have // these calls sequentially, it would be more likely that the calls // to xSemaphoreGiveRecursive() would be called as a call stack // unwound. This is just for demonstrative purposes. xSemaphoreGiveRecursive( xMutex ); xSemaphoreGiveRecursive( xMutex ); xSemaphoreGiveRecursive( xMutex ); // Now the mutex can be taken by other tasks. } else { // We could not obtain the mutex and can therefore not access // the shared resource safely. } } } </pre> * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive * \ingroup Semaphores / #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) / * xSemaphoreAltGive() is an alternative version of xSemaphoreGive(). * * The source code that implements the alternative (Alt) API is much * simpler because it executes everything from within a critical section. * This is the approach taken by many other RTOSes, but FreeRTOS.org has the * preferred fully featured API too. The fully featured API has more * complex code that takes longer to execute, but makes much less use of * critical sections. Therefore the alternative API sacrifices interrupt * responsiveness to gain execution speed, whereas the fully featured API * sacrifices execution speed to ensure better interrupt responsiveness. / #define xSemaphoreAltGive( xSemaphore ) xQueueAltGenericSend( ( xQueueHandle ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) /* * semphr. h * <pre> xSemaphoreGiveFromISR( xSemaphoreHandle xSemaphore, signed portBASE_TYPE pxHigherPriorityTaskWoken )</pre> * <i>Macro</i> to release a semaphore. The semaphore must have previously been * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting(). * * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) * must not be used with this macro. * * This macro can be used from an ISR. * * @param xSemaphore A handle to the semaphore being released. This is the * handle returned when the semaphore was created. * * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set * pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task to unblock, and the unblocked task has a priority higher than the currently * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then * a context switch should be requested before the interrupt is exited. * * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. * * Example usage: <pre> \#define LONG_TIME 0xffff \#define TICKS_TO_WAIT 10 xSemaphoreHandle xSemaphore = NULL; // Repetitive task. void vATask( void * pvParameters ) { for( ;; ) { // We want this task to run every 10 ticks of a timer. The semaphore // was created before this task was started. // Block waiting for the semaphore to become available. if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE ) { // It is time to execute. // ... // We have finished our task. Return to the top of the loop where // we will block on the semaphore until it is time to execute // again. Note when using the semaphore for synchronisation with an // ISR in this manner there is no need to 'give' the semaphore back. } } } // Timer ISR void vTimerISR( void * pvParameters ) { static unsigned char ucLocalTickCount = 0; static signed portBASE_TYPE xHigherPriorityTaskWoken; // A timer tick has occurred. // ... Do other time functions. // Is it time for vATask () to run? xHigherPriorityTaskWoken = pdFALSE; ucLocalTickCount++; if( ucLocalTickCount >= TICKS_TO_WAIT ) { // Unblock the task by releasing the semaphore. xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken ); // Reset the count so we release the semaphore again in 10 ticks time. ucLocalTickCount = 0; } if( xHigherPriorityTaskWoken != pdFALSE ) { // We can force a context switch here. Context switching from an // ISR uses port specific syntax. Check the demo task for your port // to find the syntax required. } } </pre> * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR * \ingroup Semaphores / #define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueueHandle ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) /* * semphr. h * <pre>xSemaphoreHandle xSemaphoreCreateMutex( void )</pre> * * <i>Macro</i> that implements a mutex semaphore by using the existing queue * mechanism. * * Mutexes created using this macro can be accessed using the xSemaphoreTake() * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and * xSemaphoreGiveRecursive() macros should not be used. * * This type of semaphore uses a priority inheritance mechanism so a task * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the * semaphore it is no longer required. * * Mutex type semaphores cannot be used from within interrupt service routines. * * See vSemaphoreCreateBinary() for an alternative implementation that can be * used for pure synchronisation (where one task or interrupt always 'gives' the * semaphore and another always 'takes' the semaphore) and from within interrupt * service routines. * * @return xSemaphore Handle to the created mutex semaphore. Should be of type * xSemaphoreHandle. * * Example usage: <pre> xSemaphoreHandle xSemaphore; void vATask( void * pvParameters ) { // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). // This is a macro so pass the variable in directly. xSemaphore = xSemaphoreCreateMutex(); if( xSemaphore != NULL ) { // The semaphore was created successfully. // The semaphore can now be used. } } </pre> * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex * \ingroup Semaphores / #define xSemaphoreCreateMutex() xQueueCreateMutex() /* * semphr. h * <pre>xSemaphoreHandle xSemaphoreCreateRecursiveMutex( void )</pre> * * <i>Macro</i> that implements a recursive mutex by using the existing queue * mechanism. * * Mutexes created using this macro can be accessed using the * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The * xSemaphoreTake() and xSemaphoreGive() macros should not be used. * * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex * doesn't become available again until the owner has called * xSemaphoreGiveRecursive() for each successful 'take' request. For example, * if a task successfully 'takes' the same mutex 5 times then the mutex will * not be available to any other task until it has also 'given' the mutex back * exactly five times. * * This type of semaphore uses a priority inheritance mechanism so a task * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the * semaphore it is no longer required. * * Mutex type semaphores cannot be used from within interrupt service routines. * * See vSemaphoreCreateBinary() for an alternative implementation that can be * used for pure synchronisation (where one task or interrupt always 'gives' the * semaphore and another always 'takes' the semaphore) and from within interrupt * service routines. * * @return xSemaphore Handle to the created mutex semaphore. Should be of type * xSemaphoreHandle. * * Example usage: <pre> xSemaphoreHandle xSemaphore; void vATask( void * pvParameters ) { // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). // This is a macro so pass the variable in directly. xSemaphore = xSemaphoreCreateRecursiveMutex(); if( xSemaphore != NULL ) { // The semaphore was created successfully. // The semaphore can now be used. } } </pre> * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex * \ingroup Semaphores / #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex() /* * semphr. h * <pre>xSemaphoreHandle xSemaphoreCreateCounting( unsigned portBASE_TYPE uxMaxCount, unsigned portBASE_TYPE uxInitialCount )</pre> * * <i>Macro</i> that creates a counting semaphore by using the existing * queue mechanism. * * Counting semaphores are typically used for two things: * * 1) Counting events. * * In this usage scenario an event handler will 'give' a semaphore each time * an event occurs (incrementing the semaphore count value), and a handler * task will 'take' a semaphore each time it processes an event * (decrementing the semaphore count value). The count value is therefore * the difference between the number of events that have occurred and the * number that have been processed. In this case it is desirable for the * initial count value to be zero. * * 2) Resource management. * * In this usage scenario the count value indicates the number of resources * available. To obtain control of a resource a task must first obtain a * semaphore - decrementing the semaphore count value. When the count value * reaches zero there are no free resources. When a task finishes with the * resource it 'gives' the semaphore back - incrementing the semaphore count * value. In this case it is desirable for the initial count value to be * equal to the maximum count value, indicating that all resources are free. * * @param uxMaxCount The maximum count value that can be reached. When the * semaphore reaches this value it can no longer be 'given'. * * @param uxInitialCount The count value assigned to the semaphore when it is * created. * * @return Handle to the created semaphore. Null if the semaphore could not be * created. * * Example usage: <pre> xSemaphoreHandle xSemaphore; void vATask( void * pvParameters ) { xSemaphoreHandle xSemaphore = NULL; // Semaphore cannot be used before a call to xSemaphoreCreateCounting(). // The max value to which the semaphore can count should be 10, and the // initial value assigned to the count should be 0. xSemaphore = xSemaphoreCreateCounting( 10, 0 ); if( xSemaphore != NULL ) { // The semaphore was created successfully. // The semaphore can now be used. } } </pre> * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting * \ingroup Semaphores / #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) /* * semphr. h * <pre>void vSemaphoreDelete( xSemaphoreHandle xSemaphore );</pre> * * Delete a semaphore. This function must be used with care. For example, * do not delete a mutex type semaphore if the mutex is held by a task. * * @param xSemaphore A handle to the semaphore to be deleted. * * \page vSemaphoreDelete vSemaphoreDelete * \ingroup Semaphores / #define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( xQueueHandle ) xSemaphore ) #endif / SEMAPHORE_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/semphr.h	C	oos	28,498
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef TIMERS_H #define TIMERS_H #ifndef INC_FREERTOS_H #error "include FreeRTOS.h must appear in source files before include timers.h" #endif #include "portable.h" #include "list.h" #include "task.h" #ifdef __cplusplus extern "C" { #endif / IDs for commands that can be sent/received on the timer queue. These are to be used solely through the macros that make up the public software timer API, as defined below. / #define tmrCOMMAND_START 0 #define tmrCOMMAND_STOP 1 #define tmrCOMMAND_CHANGE_PERIOD 2 #define tmrCOMMAND_DELETE 3 /----------------------------------------------------------- * MACROS AND DEFINITIONS ----------------------------------------------------------/ /** * Type by which software timers are referenced. For example, a call to * xTimerCreate() returns an xTimerHandle variable that can then be used to * reference the subject timer in calls to other software timer API functions * (for example, xTimerStart(), xTimerReset(), etc.). / typedef void xTimerHandle; /* Define the prototype to which timer callback functions must conform. / typedef void (tmrTIMER_CALLBACK)( xTimerHandle xTimer ); /** * xTimerHandle xTimerCreate( const signed char pcTimerName, portTickType xTimerPeriod, * unsigned portBASE_TYPE uxAutoReload, * void * pvTimerID, * tmrTIMER_CALLBACK pxCallbackFunction ); * * Creates a new software timer instance. This allocates the storage required * by the new timer, initialises the new timers internal state, and returns a * handle by which the new timer can be referenced. * * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the * active state. * * @param pcTimerName A text name that is assigned to the timer. This is done * purely to assist debugging. The kernel itself only ever references a timer by * its handle, and never by its name. * * @param xTimerPeriod The timer period. The time is defined in tick periods so * the constant portTICK_RATE_MS can be used to convert a time that has been * specified in milliseconds. For example, if the timer must expire after 100 * ticks, then xTimerPeriod should be set to 100. Alternatively, if the timer * must expire after 500ms, then xPeriod can be set to ( 500 / portTICK_RATE_MS ) * provided configTICK_RATE_HZ is less than or equal to 1000. * * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will * expire repeatedly with a frequency set by the xTimerPeriod parameter. If * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and * enter the dormant state after it expires. * * @param pvTimerID An identifier that is assigned to the timer being created. * Typically this would be used in the timer callback function to identify which * timer expired when the same callback function is assigned to more than one * timer. * * @param pxCallbackFunction The function to call when the timer expires. * Callback functions must have the prototype defined by tmrTIMER_CALLBACK, * which is "void vCallbackFunction( xTimerHandle xTimer );". * * @return If the timer is successfully create then a handle to the newly * created timer is returned. If the timer cannot be created (because either * there is insufficient FreeRTOS heap remaining to allocate the timer * structures, or the timer period was set to 0) then 0 is returned. * * Example usage: * * * #define NUM_TIMERS 5 * * // An array to hold handles to the created timers. * xTimerHandle xTimers[ NUM_TIMERS ]; * * // An array to hold a count of the number of times each timer expires. * long lExpireCounters[ NUM_TIMERS ] = { 0 }; * * // Define a callback function that will be used by multiple timer instances. * // The callback function does nothing but count the number of times the * // associated timer expires, and stop the timer once the timer has expired * // 10 times. * void vTimerCallback( xTimerHandle pxTimer ) * { * long lArrayIndex; * const long xMaxExpiryCountBeforeStopping = 10; * * // Optionally do something if the pxTimer parameter is NULL. * configASSERT( pxTimer ); * * // Which timer expired? * lArrayIndex = ( long ) pvTimerGetTimerID( pxTimer ); * * // Increment the number of times that pxTimer has expired. * lExpireCounters[ lArrayIndex ] += 1; * * // If the timer has expired 10 times then stop it from running. * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping ) * { * // Do not use a block time if calling a timer API function from a * // timer callback function, as doing so could cause a deadlock! * xTimerStop( pxTimer, 0 ); * } * } * * void main( void ) * { * long x; * * // Create then start some timers. Starting the timers before the scheduler * // has been started means the timers will start running immediately that * // the scheduler starts. * for( x = 0; x < NUM_TIMERS; x++ ) * { * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel. * ( 100 * x ), // The timer period in ticks. * pdTRUE, // The timers will auto-reload themselves when they expire. * ( void * ) x, // Assign each timer a unique id equal to its array index. * vTimerCallback // Each timer calls the same callback when it expires. * ); * * if( xTimers[ x ] == NULL ) * { * // The timer was not created. * } * else * { * // Start the timer. No block time is specified, and even if one was * // it would be ignored because the scheduler has not yet been * // started. * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS ) * { * // The timer could not be set into the Active state. * } * } * } * * // ... * // Create tasks here. * // ... * * // Starting the scheduler will start the timers running as they have already * // been set into the active state. * xTaskStartScheduler(); * * // Should not reach here. * for( ;; ); * } / xTimerHandle xTimerCreate( const signed char pcTimerName, portTickType xTimerPeriodInTicks, unsigned portBASE_TYPE uxAutoReload, void * pvTimerID, tmrTIMER_CALLBACK pxCallbackFunction ) PRIVILEGED_FUNCTION; /** * void pvTimerGetTimerID( xTimerHandle xTimer ); * Returns the ID assigned to the timer. * * IDs are assigned to timers using the pvTimerID parameter of the call to * xTimerCreated() that was used to create the timer. * * If the same callback function is assigned to multiple timers then the timer * ID can be used within the callback function to identify which timer actually * expired. * * @param xTimer The timer being queried. * * @return The ID assigned to the timer being queried. * * Example usage: * * See the xTimerCreate() API function example usage scenario. / void pvTimerGetTimerID( xTimerHandle xTimer ) PRIVILEGED_FUNCTION; /** * portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer ); * * Queries a timer to see if it is active or dormant. * * A timer will be dormant if: * 1) It has been created but not started, or * 2) It is an expired on-shot timer that has not been restarted. * * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the * active state. * * @param xTimer The timer being queried. * * @return pdFALSE will be returned if the timer is dormant. A value other than * pdFALSE will be returned if the timer is active. * * Example usage: * * // This function assumes xTimer has already been created. * void vAFunction( xTimerHandle xTimer ) * { * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" * { * // xTimer is active, do something. * } * else * { * // xTimer is not active, do something else. * } * } / portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer ) PRIVILEGED_FUNCTION; /* * xTimerGetTimerDaemonTaskHandle() is only available if * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h. * * Simply returns the handle of the timer service/daemon task. It it not valid * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. / xTaskHandle xTimerGetTimerDaemonTaskHandle( void ); /* * portBASE_TYPE xTimerStart( xTimerHandle xTimer, portTickType xBlockTime ); * * Timer functionality is provided by a timer service/daemon task. Many of the * public FreeRTOS timer API functions send commands to the timer service task * though a queue called the timer command queue. The timer command queue is * private to the kernel itself and is not directly accessible to application * code. The length of the timer command queue is set by the * configTIMER_QUEUE_LENGTH configuration constant. * * xTimerStart() starts a timer that was previously created using the * xTimerCreate() API function. If the timer had already been started and was * already in the active state, then xTimerStart() has equivalent functionality * to the xTimerReset() API function. * * Starting a timer ensures the timer is in the active state. If the timer * is not stopped, deleted, or reset in the mean time, the callback function * associated with the timer will get called 'n' ticks after xTimerStart() was * called, where 'n' is the timers defined period. * * It is valid to call xTimerStart() before the scheduler has been started, but * when this is done the timer will not actually start until the scheduler is * started, and the timers expiry time will be relative to when the scheduler is * started, not relative to when xTimerStart() was called. * * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart() * to be available. * * @param xTimer The handle of the timer being started/restarted. * * @param xBlockTime Specifies the time, in ticks, that the calling task should * be held in the Blocked state to wait for the start command to be successfully * sent to the timer command queue, should the queue already be full when * xTimerStart() was called. xBlockTime is ignored if xTimerStart() is called * before the scheduler is started. * * @return pdFAIL will be returned if the start command could not be sent to * the timer command queue even after xBlockTime ticks had passed. pdPASS will * be returned if the command was successfully sent to the timer command queue. * When the command is actually processed will depend on the priority of the * timer service/daemon task relative to other tasks in the system, although the * timers expiry time is relative to when xTimerStart() is actually called. The * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY * configuration constant. * * Example usage: * * See the xTimerCreate() API function example usage scenario. * / #define xTimerStart( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xBlockTime ) ) /* * portBASE_TYPE xTimerStop( xTimerHandle xTimer, portTickType xBlockTime ); * * Timer functionality is provided by a timer service/daemon task. Many of the * public FreeRTOS timer API functions send commands to the timer service task * though a queue called the timer command queue. The timer command queue is * private to the kernel itself and is not directly accessible to application * code. The length of the timer command queue is set by the * configTIMER_QUEUE_LENGTH configuration constant. * * xTimerStop() stops a timer that was previously started using either of the * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(), * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions. * * Stopping a timer ensures the timer is not in the active state. * * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop() * to be available. * * @param xTimer The handle of the timer being stopped. * * @param xBlockTime Specifies the time, in ticks, that the calling task should * be held in the Blocked state to wait for the stop command to be successfully * sent to the timer command queue, should the queue already be full when * xTimerStop() was called. xBlockTime is ignored if xTimerStop() is called * before the scheduler is started. * * @return pdFAIL will be returned if the stop command could not be sent to * the timer command queue even after xBlockTime ticks had passed. pdPASS will * be returned if the command was successfully sent to the timer command queue. * When the command is actually processed will depend on the priority of the * timer service/daemon task relative to other tasks in the system. The timer * service/daemon task priority is set by the configTIMER_TASK_PRIORITY * configuration constant. * * Example usage: * * See the xTimerCreate() API function example usage scenario. * / #define xTimerStop( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xBlockTime ) ) /* * portBASE_TYPE xTimerChangePeriod( xTimerHandle xTimer, * portTickType xNewPeriod, * portTickType xBlockTime ); * * Timer functionality is provided by a timer service/daemon task. Many of the * public FreeRTOS timer API functions send commands to the timer service task * though a queue called the timer command queue. The timer command queue is * private to the kernel itself and is not directly accessible to application * code. The length of the timer command queue is set by the * configTIMER_QUEUE_LENGTH configuration constant. * * xTimerChangePeriod() changes the period of a timer that was previously * created using the xTimerCreate() API function. * * xTimerChangePeriod() can be called to change the period of an active or * dormant state timer. * * The configUSE_TIMERS configuration constant must be set to 1 for * xTimerChangePeriod() to be available. * * @param xTimer The handle of the timer that is having its period changed. * * @param xNewPeriod The new period for xTimer. Timer periods are specified in * tick periods, so the constant portTICK_RATE_MS can be used to convert a time * that has been specified in milliseconds. For example, if the timer must * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, * if the timer must expire after 500ms, then xNewPeriod can be set to * ( 500 / portTICK_RATE_MS ) provided configTICK_RATE_HZ is less than * or equal to 1000. * * @param xBlockTime Specifies the time, in ticks, that the calling task should * be held in the Blocked state to wait for the change period command to be * successfully sent to the timer command queue, should the queue already be * full when xTimerChangePeriod() was called. xBlockTime is ignored if * xTimerChangePeriod() is called before the scheduler is started. * * @return pdFAIL will be returned if the change period command could not be * sent to the timer command queue even after xBlockTime ticks had passed. * pdPASS will be returned if the command was successfully sent to the timer * command queue. When the command is actually processed will depend on the * priority of the timer service/daemon task relative to other tasks in the * system. The timer service/daemon task priority is set by the * configTIMER_TASK_PRIORITY configuration constant. * * Example usage: * * // This function assumes xTimer has already been created. If the timer * // referenced by xTimer is already active when it is called, then the timer * // is deleted. If the timer referenced by xTimer is not active when it is * // called, then the period of the timer is set to 500ms and the timer is * // started. * void vAFunction( xTimerHandle xTimer ) * { * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" * { * // xTimer is already active - delete it. * xTimerDelete( xTimer ); * } * else * { * // xTimer is not active, change its period to 500ms. This will also * // cause the timer to start. Block for a maximum of 100 ticks if the * // change period command cannot immediately be sent to the timer * // command queue. * if( xTimerChangePeriod( xTimer, 500 / portTICK_RATE_MS, 100 ) == pdPASS ) * { * // The command was successfully sent. * } * else * { * // The command could not be sent, even after waiting for 100 ticks * // to pass. Take appropriate action here. * } * } * } / #define xTimerChangePeriod( xTimer, xNewPeriod, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xBlockTime ) ) /* * portBASE_TYPE xTimerDelete( xTimerHandle xTimer, portTickType xBlockTime ); * * Timer functionality is provided by a timer service/daemon task. Many of the * public FreeRTOS timer API functions send commands to the timer service task * though a queue called the timer command queue. The timer command queue is * private to the kernel itself and is not directly accessible to application * code. The length of the timer command queue is set by the * configTIMER_QUEUE_LENGTH configuration constant. * * xTimerDelete() deletes a timer that was previously created using the * xTimerCreate() API function. * * The configUSE_TIMERS configuration constant must be set to 1 for * xTimerDelete() to be available. * * @param xTimer The handle of the timer being deleted. * * @param xBlockTime Specifies the time, in ticks, that the calling task should * be held in the Blocked state to wait for the delete command to be * successfully sent to the timer command queue, should the queue already be * full when xTimerDelete() was called. xBlockTime is ignored if xTimerDelete() * is called before the scheduler is started. * * @return pdFAIL will be returned if the delete command could not be sent to * the timer command queue even after xBlockTime ticks had passed. pdPASS will * be returned if the command was successfully sent to the timer command queue. * When the command is actually processed will depend on the priority of the * timer service/daemon task relative to other tasks in the system. The timer * service/daemon task priority is set by the configTIMER_TASK_PRIORITY * configuration constant. * * Example usage: * * See the xTimerChangePeriod() API function example usage scenario. / #define xTimerDelete( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xBlockTime ) ) /* * portBASE_TYPE xTimerReset( xTimerHandle xTimer, portTickType xBlockTime ); * * Timer functionality is provided by a timer service/daemon task. Many of the * public FreeRTOS timer API functions send commands to the timer service task * though a queue called the timer command queue. The timer command queue is * private to the kernel itself and is not directly accessible to application * code. The length of the timer command queue is set by the * configTIMER_QUEUE_LENGTH configuration constant. * * xTimerReset() re-starts a timer that was previously created using the * xTimerCreate() API function. If the timer had already been started and was * already in the active state, then xTimerReset() will cause the timer to * re-evaluate its expiry time so that it is relative to when xTimerReset() was * called. If the timer was in the dormant state then xTimerReset() has * equivalent functionality to the xTimerStart() API function. * * Resetting a timer ensures the timer is in the active state. If the timer * is not stopped, deleted, or reset in the mean time, the callback function * associated with the timer will get called 'n' ticks after xTimerReset() was * called, where 'n' is the timers defined period. * * It is valid to call xTimerReset() before the scheduler has been started, but * when this is done the timer will not actually start until the scheduler is * started, and the timers expiry time will be relative to when the scheduler is * started, not relative to when xTimerReset() was called. * * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset() * to be available. * * @param xTimer The handle of the timer being reset/started/restarted. * * @param xBlockTime Specifies the time, in ticks, that the calling task should * be held in the Blocked state to wait for the reset command to be successfully * sent to the timer command queue, should the queue already be full when * xTimerReset() was called. xBlockTime is ignored if xTimerReset() is called * before the scheduler is started. * * @return pdFAIL will be returned if the reset command could not be sent to * the timer command queue even after xBlockTime ticks had passed. pdPASS will * be returned if the command was successfully sent to the timer command queue. * When the command is actually processed will depend on the priority of the * timer service/daemon task relative to other tasks in the system, although the * timers expiry time is relative to when xTimerStart() is actually called. The * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY * configuration constant. * * Example usage: * * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass * // without a key being pressed, then the LCD back-light is switched off. In * // this case, the timer is a one-shot timer. * * xTimerHandle xBacklightTimer = NULL; * * // The callback function assigned to the one-shot timer. In this case the * // parameter is not used. * void vBacklightTimerCallback( xTimerHandle pxTimer ) * { * // The timer expired, therefore 5 seconds must have passed since a key * // was pressed. Switch off the LCD back-light. * vSetBacklightState( BACKLIGHT_OFF ); * } * * // The key press event handler. * void vKeyPressEventHandler( char cKey ) * { * // Ensure the LCD back-light is on, then reset the timer that is * // responsible for turning the back-light off after 5 seconds of * // key inactivity. Wait 10 ticks for the command to be successfully sent * // if it cannot be sent immediately. * vSetBacklightState( BACKLIGHT_ON ); * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS ) * { * // The reset command was not executed successfully. Take appropriate * // action here. * } * * // Perform the rest of the key processing here. * } * * void main( void ) * { * long x; * * // Create then start the one-shot timer that is responsible for turning * // the back-light off if no keys are pressed within a 5 second period. * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel. * ( 5000 / portTICK_RATE_MS), // The timer period in ticks. * pdFALSE, // The timer is a one-shot timer. * 0, // The id is not used by the callback so can take any value. * vBacklightTimerCallback // The callback function that switches the LCD back-light off. * ); * * if( xBacklightTimer == NULL ) * { * // The timer was not created. * } * else * { * // Start the timer. No block time is specified, and even if one was * // it would be ignored because the scheduler has not yet been * // started. * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS ) * { * // The timer could not be set into the Active state. * } * } * * // ... * // Create tasks here. * // ... * * // Starting the scheduler will start the timer running as it has already * // been set into the active state. * xTaskStartScheduler(); * * // Should not reach here. * for( ;; ); * } / #define xTimerReset( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xBlockTime ) ) /* * portBASE_TYPE xTimerStartFromISR( xTimerHandle xTimer, * portBASE_TYPE pxHigherPriorityTaskWoken ); * A version of xTimerStart() that can be called from an interrupt service * routine. * * @param xTimer The handle of the timer being started/restarted. * * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most * of its time in the Blocked state, waiting for messages to arrive on the timer * command queue. Calling xTimerStartFromISR() writes a message to the timer * command queue, so has the potential to transition the timer service/daemon * task out of the Blocked state. If calling xTimerStartFromISR() causes the * timer service/daemon task to leave the Blocked state, and the timer service/ * daemon task has a priority equal to or greater than the currently executing * task (the task that was interrupted), then pxHigherPriorityTaskWoken will get set to pdTRUE internally within the xTimerStartFromISR() function. If * xTimerStartFromISR() sets this value to pdTRUE then a context switch should * be performed before the interrupt exits. * * @return pdFAIL will be returned if the start command could not be sent to * the timer command queue. pdPASS will be returned if the command was * successfully sent to the timer command queue. When the command is actually * processed will depend on the priority of the timer service/daemon task * relative to other tasks in the system, although the timers expiry time is * relative to when xTimerStartFromISR() is actually called. The timer service/daemon * task priority is set by the configTIMER_TASK_PRIORITY configuration constant. * * Example usage: * * // This scenario assumes xBacklightTimer has already been created. When a * // key is pressed, an LCD back-light is switched on. If 5 seconds pass * // without a key being pressed, then the LCD back-light is switched off. In * // this case, the timer is a one-shot timer, and unlike the example given for * // the xTimerReset() function, the key press event handler is an interrupt * // service routine. * * // The callback function assigned to the one-shot timer. In this case the * // parameter is not used. * void vBacklightTimerCallback( xTimerHandle pxTimer ) * { * // The timer expired, therefore 5 seconds must have passed since a key * // was pressed. Switch off the LCD back-light. * vSetBacklightState( BACKLIGHT_OFF ); * } * * // The key press interrupt service routine. * void vKeyPressEventInterruptHandler( void ) * { * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; * * // Ensure the LCD back-light is on, then restart the timer that is * // responsible for turning the back-light off after 5 seconds of * // key inactivity. This is an interrupt service routine so can only * // call FreeRTOS API functions that end in "FromISR". * vSetBacklightState( BACKLIGHT_ON ); * * // xTimerStartFromISR() or xTimerResetFromISR() could be called here * // as both cause the timer to re-calculate its expiry time. * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was * // declared (in this function). * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) * { * // The start command was not executed successfully. Take appropriate * // action here. * } * * // Perform the rest of the key processing here. * * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch * // should be performed. The syntax required to perform a context switch * // from inside an ISR varies from port to port, and from compiler to * // compiler. Inspect the demos for the port you are using to find the * // actual syntax required. * if( xHigherPriorityTaskWoken != pdFALSE ) * { * // Call the interrupt safe yield function here (actual function * // depends on the FreeRTOS port being used. * } * } / #define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) /* * portBASE_TYPE xTimerStopFromISR( xTimerHandle xTimer, * portBASE_TYPE pxHigherPriorityTaskWoken ); * A version of xTimerStop() that can be called from an interrupt service * routine. * * @param xTimer The handle of the timer being stopped. * * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most * of its time in the Blocked state, waiting for messages to arrive on the timer * command queue. Calling xTimerStopFromISR() writes a message to the timer * command queue, so has the potential to transition the timer service/daemon * task out of the Blocked state. If calling xTimerStopFromISR() causes the * timer service/daemon task to leave the Blocked state, and the timer service/ * daemon task has a priority equal to or greater than the currently executing * task (the task that was interrupted), then pxHigherPriorityTaskWoken will get set to pdTRUE internally within the xTimerStopFromISR() function. If * xTimerStopFromISR() sets this value to pdTRUE then a context switch should * be performed before the interrupt exits. * * @return pdFAIL will be returned if the stop command could not be sent to * the timer command queue. pdPASS will be returned if the command was * successfully sent to the timer command queue. When the command is actually * processed will depend on the priority of the timer service/daemon task * relative to other tasks in the system. The timer service/daemon task * priority is set by the configTIMER_TASK_PRIORITY configuration constant. * * Example usage: * * // This scenario assumes xTimer has already been created and started. When * // an interrupt occurs, the timer should be simply stopped. * * // The interrupt service routine that stops the timer. * void vAnExampleInterruptServiceRoutine( void ) * { * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; * * // The interrupt has occurred - simply stop the timer. * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined * // (within this function). As this is an interrupt service routine, only * // FreeRTOS API functions that end in "FromISR" can be used. * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) * { * // The stop command was not executed successfully. Take appropriate * // action here. * } * * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch * // should be performed. The syntax required to perform a context switch * // from inside an ISR varies from port to port, and from compiler to * // compiler. Inspect the demos for the port you are using to find the * // actual syntax required. * if( xHigherPriorityTaskWoken != pdFALSE ) * { * // Call the interrupt safe yield function here (actual function * // depends on the FreeRTOS port being used. * } * } / #define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0, ( pxHigherPriorityTaskWoken ), 0U ) /* * portBASE_TYPE xTimerChangePeriodFromISR( xTimerHandle xTimer, * portTickType xNewPeriod, * portBASE_TYPE pxHigherPriorityTaskWoken ); * A version of xTimerChangePeriod() that can be called from an interrupt * service routine. * * @param xTimer The handle of the timer that is having its period changed. * * @param xNewPeriod The new period for xTimer. Timer periods are specified in * tick periods, so the constant portTICK_RATE_MS can be used to convert a time * that has been specified in milliseconds. For example, if the timer must * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, * if the timer must expire after 500ms, then xNewPeriod can be set to * ( 500 / portTICK_RATE_MS ) provided configTICK_RATE_HZ is less than * or equal to 1000. * * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most * of its time in the Blocked state, waiting for messages to arrive on the timer * command queue. Calling xTimerChangePeriodFromISR() writes a message to the * timer command queue, so has the potential to transition the timer service/ * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR() * causes the timer service/daemon task to leave the Blocked state, and the * timer service/daemon task has a priority equal to or greater than the * currently executing task (the task that was interrupted), then * pxHigherPriorityTaskWoken will get set to pdTRUE internally within the xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets * this value to pdTRUE then a context switch should be performed before the * interrupt exits. * * @return pdFAIL will be returned if the command to change the timers period * could not be sent to the timer command queue. pdPASS will be returned if the * command was successfully sent to the timer command queue. When the command * is actually processed will depend on the priority of the timer service/daemon * task relative to other tasks in the system. The timer service/daemon task * priority is set by the configTIMER_TASK_PRIORITY configuration constant. * * Example usage: * * // This scenario assumes xTimer has already been created and started. When * // an interrupt occurs, the period of xTimer should be changed to 500ms. * * // The interrupt service routine that changes the period of xTimer. * void vAnExampleInterruptServiceRoutine( void ) * { * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; * * // The interrupt has occurred - change the period of xTimer to 500ms. * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined * // (within this function). As this is an interrupt service routine, only * // FreeRTOS API functions that end in "FromISR" can be used. * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) * { * // The command to change the timers period was not executed * // successfully. Take appropriate action here. * } * * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch * // should be performed. The syntax required to perform a context switch * // from inside an ISR varies from port to port, and from compiler to * // compiler. Inspect the demos for the port you are using to find the * // actual syntax required. * if( xHigherPriorityTaskWoken != pdFALSE ) * { * // Call the interrupt safe yield function here (actual function * // depends on the FreeRTOS port being used. * } * } / #define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U ) /* * portBASE_TYPE xTimerResetFromISR( xTimerHandle xTimer, * portBASE_TYPE pxHigherPriorityTaskWoken ); * A version of xTimerReset() that can be called from an interrupt service * routine. * * @param xTimer The handle of the timer that is to be started, reset, or * restarted. * * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most * of its time in the Blocked state, waiting for messages to arrive on the timer * command queue. Calling xTimerResetFromISR() writes a message to the timer * command queue, so has the potential to transition the timer service/daemon * task out of the Blocked state. If calling xTimerResetFromISR() causes the * timer service/daemon task to leave the Blocked state, and the timer service/ * daemon task has a priority equal to or greater than the currently executing * task (the task that was interrupted), then pxHigherPriorityTaskWoken will get set to pdTRUE internally within the xTimerResetFromISR() function. If * xTimerResetFromISR() sets this value to pdTRUE then a context switch should * be performed before the interrupt exits. * * @return pdFAIL will be returned if the reset command could not be sent to * the timer command queue. pdPASS will be returned if the command was * successfully sent to the timer command queue. When the command is actually * processed will depend on the priority of the timer service/daemon task * relative to other tasks in the system, although the timers expiry time is * relative to when xTimerResetFromISR() is actually called. The timer service/daemon * task priority is set by the configTIMER_TASK_PRIORITY configuration constant. * * Example usage: * * // This scenario assumes xBacklightTimer has already been created. When a * // key is pressed, an LCD back-light is switched on. If 5 seconds pass * // without a key being pressed, then the LCD back-light is switched off. In * // this case, the timer is a one-shot timer, and unlike the example given for * // the xTimerReset() function, the key press event handler is an interrupt * // service routine. * * // The callback function assigned to the one-shot timer. In this case the * // parameter is not used. * void vBacklightTimerCallback( xTimerHandle pxTimer ) * { * // The timer expired, therefore 5 seconds must have passed since a key * // was pressed. Switch off the LCD back-light. * vSetBacklightState( BACKLIGHT_OFF ); * } * * // The key press interrupt service routine. * void vKeyPressEventInterruptHandler( void ) * { * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; * * // Ensure the LCD back-light is on, then reset the timer that is * // responsible for turning the back-light off after 5 seconds of * // key inactivity. This is an interrupt service routine so can only * // call FreeRTOS API functions that end in "FromISR". * vSetBacklightState( BACKLIGHT_ON ); * * // xTimerStartFromISR() or xTimerResetFromISR() could be called here * // as both cause the timer to re-calculate its expiry time. * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was * // declared (in this function). * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) * { * // The reset command was not executed successfully. Take appropriate * // action here. * } * * // Perform the rest of the key processing here. * * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch * // should be performed. The syntax required to perform a context switch * // from inside an ISR varies from port to port, and from compiler to * // compiler. Inspect the demos for the port you are using to find the * // actual syntax required. * if( xHigherPriorityTaskWoken != pdFALSE ) * { * // Call the interrupt safe yield function here (actual function * // depends on the FreeRTOS port being used. * } * } / #define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) / * Functions beyond this part are not part of the public API and are intended * for use by the kernel only. / portBASE_TYPE xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; portBASE_TYPE xTimerGenericCommand( xTimerHandle xTimer, portBASE_TYPE xCommandID, portTickType xOptionalValue, portBASE_TYPE pxHigherPriorityTaskWoken, portTickType xBlockTime ) PRIVILEGED_FUNCTION; #ifdef __cplusplus } #endif #endif /* TIMERS_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/timers.h	C	oos	44,681
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef MPU_WRAPPERS_H #define MPU_WRAPPERS_H / This file redefines API functions to be called through a wrapper macro, but only for ports that are using the MPU. / #ifdef portUSING_MPU_WRAPPERS / MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is included from queue.c or task.c to prevent it from having an effect within those files. / #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE #define xTaskGenericCreate MPU_xTaskGenericCreate #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions #define vTaskDelete MPU_vTaskDelete #define vTaskDelayUntil MPU_vTaskDelayUntil #define vTaskDelay MPU_vTaskDelay #define uxTaskPriorityGet MPU_uxTaskPriorityGet #define vTaskPrioritySet MPU_vTaskPrioritySet #define vTaskSuspend MPU_vTaskSuspend #define xTaskIsTaskSuspended MPU_xTaskIsTaskSuspended #define vTaskResume MPU_vTaskResume #define vTaskSuspendAll MPU_vTaskSuspendAll #define xTaskResumeAll MPU_xTaskResumeAll #define xTaskGetTickCount MPU_xTaskGetTickCount #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks #define vTaskList MPU_vTaskList #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats #define vTaskStartTrace MPU_vTaskStartTrace #define ulTaskEndTrace MPU_ulTaskEndTrace #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState #define xQueueCreate MPU_xQueueCreate #define xQueueCreateMutex MPU_xQueueCreateMutex #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore #define xQueueGenericSend MPU_xQueueGenericSend #define xQueueAltGenericSend MPU_xQueueAltGenericSend #define xQueueAltGenericReceive MPU_xQueueAltGenericReceive #define xQueueGenericReceive MPU_xQueueGenericReceive #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting #define vQueueDelete MPU_vQueueDelete #define pvPortMalloc MPU_pvPortMalloc #define vPortFree MPU_vPortFree #define xPortGetFreeHeapSize MPU_xPortGetFreeHeapSize #define vPortInitialiseBlocks MPU_vPortInitialiseBlocks #if configQUEUE_REGISTRY_SIZE > 0 #define vQueueAddToRegistry MPU_vQueueAddToRegistry #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue #endif / Remove the privileged function macro. / #define PRIVILEGED_FUNCTION #else / MPU_WRAPPERS_INCLUDED_FROM_API_FILE / / Ensure API functions go in the privileged execution section. / #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions"))) #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) //#define PRIVILEGED_DATA #endif / MPU_WRAPPERS_INCLUDED_FROM_API_FILE / #else / portUSING_MPU_WRAPPERS / #define PRIVILEGED_FUNCTION #define PRIVILEGED_DATA #define portUSING_MPU_WRAPPERS 0 #endif / portUSING_MPU_WRAPPERS / #endif / MPU_WRAPPERS_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/mpu_wrappers.h	C	oos	6,412
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef PROJDEFS_H #define PROJDEFS_H / Defines the prototype to which task functions must conform. / typedef void (pdTASK_CODE)( void * ); #define pdTRUE ( 1 ) #define pdFALSE ( 0 ) #define pdPASS ( 1 ) #define pdFAIL ( 0 ) #define errQUEUE_EMPTY ( 0 ) #define errQUEUE_FULL ( 0 ) /* Error definitions. / #define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) #define errNO_TASK_TO_RUN ( -2 ) #define errQUEUE_BLOCKED ( -4 ) #define errQUEUE_YIELD ( -5 ) #endif / PROJDEFS_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/projdefs.h	C	oos	3,526
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef QUEUE_H #define QUEUE_H #ifndef INC_FREERTOS_H #error "#include FreeRTOS.h" must appear in source files before "#include queue.h" #endif #ifdef __cplusplus extern "C" { #endif #include "mpu_wrappers.h" /* * Type by which queues are referenced. For example, a call to xQueueCreate * returns (via a pointer parameter) an xQueueHandle variable that can then * be used as a parameter to xQueueSend(), xQueueReceive(), etc. / typedef void xQueueHandle; /* For internal use only. / #define queueSEND_TO_BACK ( 0 ) #define queueSEND_TO_FRONT ( 1 ) /* * queue. h * <pre> xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); * </pre> * * Creates a new queue instance. This allocates the storage required by the * new queue and returns a handle for the queue. * * @param uxQueueLength The maximum number of items that the queue can contain. * * @param uxItemSize The number of bytes each item in the queue will require. * Items are queued by copy, not by reference, so this is the number of bytes * that will be copied for each posted item. Each item on the queue must be * the same size. * * @return If the queue is successfully create then a handle to the newly * created queue is returned. If the queue cannot be created then 0 is * returned. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; }; void vATask( void pvParameters ) { xQueueHandle xQueue1, xQueue2; // Create a queue capable of containing 10 unsigned long values. xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) ); if( xQueue1 == 0 ) { // Queue was not created and must not be used. } // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue2 = xQueueCreate( 10, sizeof( struct AMessage ) ); if( xQueue2 == 0 ) { // Queue was not created and must not be used. } // ... Rest of task code. } </pre> * \defgroup xQueueCreate xQueueCreate * \ingroup QueueManagement / xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); /* * queue. h * <pre> portBASE_TYPE xQueueSendToToFront( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); * </pre> * * This is a macro that calls xQueueGenericSend(). * * Post an item to the front of a queue. The item is queued by copy, not by * reference. This function must not be called from an interrupt service * routine. See xQueueSendFromISR () for an alternative which may be used * in an ISR. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param xTicksToWait The maximum amount of time the task should block * waiting for space to become available on the queue, should it already * be full. The call will return immediately if this is set to 0 and the * queue is full. The time is defined in tick periods so the constant * portTICK_RATE_MS should be used to convert to real time if this is required. * * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; } xMessage; unsigned long ulVar = 10UL; void vATask( void pvParameters ) { xQueueHandle xQueue1, xQueue2; struct AMessage pxMessage; // Create a queue capable of containing 10 unsigned long values. xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) ); // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); // ... if( xQueue1 != 0 ) { // Send an unsigned long. Wait for 10 ticks for space to become // available if necessary. if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS ) { // Failed to post the message, even after 10 ticks. } } if( xQueue2 != 0 ) { // Send a pointer to a struct AMessage object. Don't block if the // queue is already full. pxMessage = & xMessage; xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 ); } // ... Rest of task code. } </pre> * \defgroup xQueueSend xQueueSend * \ingroup QueueManagement / #define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) /* * queue. h * <pre> portBASE_TYPE xQueueSendToBack( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); * </pre> * * This is a macro that calls xQueueGenericSend(). * * Post an item to the back of a queue. The item is queued by copy, not by * reference. This function must not be called from an interrupt service * routine. See xQueueSendFromISR () for an alternative which may be used * in an ISR. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param xTicksToWait The maximum amount of time the task should block * waiting for space to become available on the queue, should it already * be full. The call will return immediately if this is set to 0 and the queue * is full. The time is defined in tick periods so the constant * portTICK_RATE_MS should be used to convert to real time if this is required. * * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; } xMessage; unsigned long ulVar = 10UL; void vATask( void pvParameters ) { xQueueHandle xQueue1, xQueue2; struct AMessage pxMessage; // Create a queue capable of containing 10 unsigned long values. xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) ); // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); // ... if( xQueue1 != 0 ) { // Send an unsigned long. Wait for 10 ticks for space to become // available if necessary. if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS ) { // Failed to post the message, even after 10 ticks. } } if( xQueue2 != 0 ) { // Send a pointer to a struct AMessage object. Don't block if the // queue is already full. pxMessage = & xMessage; xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 ); } // ... Rest of task code. } </pre> * \defgroup xQueueSend xQueueSend * \ingroup QueueManagement / #define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) /* * queue. h * <pre> portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); * </pre> * * This is a macro that calls xQueueGenericSend(). It is included for * backward compatibility with versions of FreeRTOS.org that did not * include the xQueueSendToFront() and xQueueSendToBack() macros. It is * equivalent to xQueueSendToBack(). * * Post an item on a queue. The item is queued by copy, not by reference. * This function must not be called from an interrupt service routine. * See xQueueSendFromISR () for an alternative which may be used in an ISR. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param xTicksToWait The maximum amount of time the task should block * waiting for space to become available on the queue, should it already * be full. The call will return immediately if this is set to 0 and the * queue is full. The time is defined in tick periods so the constant * portTICK_RATE_MS should be used to convert to real time if this is required. * * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; } xMessage; unsigned long ulVar = 10UL; void vATask( void pvParameters ) { xQueueHandle xQueue1, xQueue2; struct AMessage pxMessage; // Create a queue capable of containing 10 unsigned long values. xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) ); // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); // ... if( xQueue1 != 0 ) { // Send an unsigned long. Wait for 10 ticks for space to become // available if necessary. if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS ) { // Failed to post the message, even after 10 ticks. } } if( xQueue2 != 0 ) { // Send a pointer to a struct AMessage object. Don't block if the // queue is already full. pxMessage = & xMessage; xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 ); } // ... Rest of task code. } </pre> * \defgroup xQueueSend xQueueSend * \ingroup QueueManagement / #define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) /* * queue. h * <pre> portBASE_TYPE xQueueGenericSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait portBASE_TYPE xCopyPosition ); * </pre> * * It is preferred that the macros xQueueSend(), xQueueSendToFront() and * xQueueSendToBack() are used in place of calling this function directly. * * Post an item on a queue. The item is queued by copy, not by reference. * This function must not be called from an interrupt service routine. * See xQueueSendFromISR () for an alternative which may be used in an ISR. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param xTicksToWait The maximum amount of time the task should block * waiting for space to become available on the queue, should it already * be full. The call will return immediately if this is set to 0 and the * queue is full. The time is defined in tick periods so the constant * portTICK_RATE_MS should be used to convert to real time if this is required. * * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the * item at the back of the queue, or queueSEND_TO_FRONT to place the item * at the front of the queue (for high priority messages). * * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; } xMessage; unsigned long ulVar = 10UL; void vATask( void pvParameters ) { xQueueHandle xQueue1, xQueue2; struct AMessage pxMessage; // Create a queue capable of containing 10 unsigned long values. xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) ); // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); // ... if( xQueue1 != 0 ) { // Send an unsigned long. Wait for 10 ticks for space to become // available if necessary. if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10, queueSEND_TO_BACK ) != pdPASS ) { // Failed to post the message, even after 10 ticks. } } if( xQueue2 != 0 ) { // Send a pointer to a struct AMessage object. Don't block if the // queue is already full. pxMessage = & xMessage; xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0, queueSEND_TO_BACK ); } // ... Rest of task code. } </pre> * \defgroup xQueueSend xQueueSend * \ingroup QueueManagement / signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); /** * queue. h * <pre> portBASE_TYPE xQueuePeek( xQueueHandle xQueue, void pvBuffer, portTickType xTicksToWait );</pre> * This is a macro that calls the xQueueGenericReceive() function. * * Receive an item from a queue without removing the item from the queue. * The item is received by copy so a buffer of adequate size must be * provided. The number of bytes copied into the buffer was defined when * the queue was created. * * Successfully received items remain on the queue so will be returned again * by the next call, or a call to xQueueReceive(). * * This macro must not be used in an interrupt service routine. * * @param pxQueue The handle to the queue from which the item is to be * received. * * @param pvBuffer Pointer to the buffer into which the received item will * be copied. * * @param xTicksToWait The maximum amount of time the task should block * waiting for an item to receive should the queue be empty at the time * of the call. The time is defined in tick periods so the constant * portTICK_RATE_MS should be used to convert to real time if this is required. * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue * is empty. * * @return pdTRUE if an item was successfully received from the queue, * otherwise pdFALSE. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; } xMessage; xQueueHandle xQueue; // Task to create a queue and post a value. void vATask( void pvParameters ) { struct AMessage pxMessage; // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); if( xQueue == 0 ) { // Failed to create the queue. } // ... // Send a pointer to a struct AMessage object. Don't block if the // queue is already full. pxMessage = & xMessage; xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 ); // ... Rest of task code. } // Task to peek the data from the queue. void vADifferentTask( void pvParameters ) { struct AMessage pxRxedMessage; if( xQueue != 0 ) { // Peek a message on the created queue. Block for 10 ticks if a // message is not immediately available. if( xQueuePeek( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) ) { // pcRxedMessage now points to the struct AMessage variable posted // by vATask, but the item still remains on the queue. } } // ... Rest of task code. } </pre> * \defgroup xQueueReceive xQueueReceive * \ingroup QueueManagement / #define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE ) /* * queue. h * <pre> portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void pvBuffer, portTickType xTicksToWait );</pre> * This is a macro that calls the xQueueGenericReceive() function. * * Receive an item from a queue. The item is received by copy so a buffer of * adequate size must be provided. The number of bytes copied into the buffer * was defined when the queue was created. * * Successfully received items are removed from the queue. * * This function must not be used in an interrupt service routine. See * xQueueReceiveFromISR for an alternative that can. * * @param pxQueue The handle to the queue from which the item is to be * received. * * @param pvBuffer Pointer to the buffer into which the received item will * be copied. * * @param xTicksToWait The maximum amount of time the task should block * waiting for an item to receive should the queue be empty at the time * of the call. xQueueReceive() will return immediately if xTicksToWait * is zero and the queue is empty. The time is defined in tick periods so the * constant portTICK_RATE_MS should be used to convert to real time if this is * required. * * @return pdTRUE if an item was successfully received from the queue, * otherwise pdFALSE. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; } xMessage; xQueueHandle xQueue; // Task to create a queue and post a value. void vATask( void pvParameters ) { struct AMessage pxMessage; // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); if( xQueue == 0 ) { // Failed to create the queue. } // ... // Send a pointer to a struct AMessage object. Don't block if the // queue is already full. pxMessage = & xMessage; xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 ); // ... Rest of task code. } // Task to receive from the queue. void vADifferentTask( void pvParameters ) { struct AMessage pxRxedMessage; if( xQueue != 0 ) { // Receive a message on the created queue. Block for 10 ticks if a // message is not immediately available. if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) ) { // pcRxedMessage now points to the struct AMessage variable posted // by vATask. } } // ... Rest of task code. } </pre> * \defgroup xQueueReceive xQueueReceive * \ingroup QueueManagement / #define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE ) /* * queue. h * <pre> portBASE_TYPE xQueueGenericReceive( xQueueHandle xQueue, void pvBuffer, portTickType xTicksToWait portBASE_TYPE xJustPeek );</pre> * It is preferred that the macro xQueueReceive() be used rather than calling * this function directly. * * Receive an item from a queue. The item is received by copy so a buffer of * adequate size must be provided. The number of bytes copied into the buffer * was defined when the queue was created. * * This function must not be used in an interrupt service routine. See * xQueueReceiveFromISR for an alternative that can. * * @param pxQueue The handle to the queue from which the item is to be * received. * * @param pvBuffer Pointer to the buffer into which the received item will * be copied. * * @param xTicksToWait The maximum amount of time the task should block * waiting for an item to receive should the queue be empty at the time * of the call. The time is defined in tick periods so the constant * portTICK_RATE_MS should be used to convert to real time if this is required. * xQueueGenericReceive() will return immediately if the queue is empty and * xTicksToWait is 0. * * @param xJustPeek When set to true, the item received from the queue is not * actually removed from the queue - meaning a subsequent call to * xQueueReceive() will return the same item. When set to false, the item * being received from the queue is also removed from the queue. * * @return pdTRUE if an item was successfully received from the queue, * otherwise pdFALSE. * * Example usage: <pre> struct AMessage { char ucMessageID; char ucData[ 20 ]; } xMessage; xQueueHandle xQueue; // Task to create a queue and post a value. void vATask( void pvParameters ) { struct AMessage pxMessage; // Create a queue capable of containing 10 pointers to AMessage structures. // These should be passed by pointer as they contain a lot of data. xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); if( xQueue == 0 ) { // Failed to create the queue. } // ... // Send a pointer to a struct AMessage object. Don't block if the // queue is already full. pxMessage = & xMessage; xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 ); // ... Rest of task code. } // Task to receive from the queue. void vADifferentTask( void pvParameters ) { struct AMessage pxRxedMessage; if( xQueue != 0 ) { // Receive a message on the created queue. Block for 10 ticks if a // message is not immediately available. if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) ) { // pcRxedMessage now points to the struct AMessage variable posted // by vATask. } } // ... Rest of task code. } </pre> * \defgroup xQueueReceive xQueueReceive * \ingroup QueueManagement / signed portBASE_TYPE xQueueGenericReceive( xQueueHandle xQueue, void const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeek ); /** * queue. h * <pre>unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue );</pre> * * Return the number of messages stored in a queue. * * @param xQueue A handle to the queue being queried. * * @return The number of messages available in the queue. * * \page uxQueueMessagesWaiting uxQueueMessagesWaiting * \ingroup QueueManagement / unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue ); /* * queue. h * <pre>void vQueueDelete( xQueueHandle xQueue );</pre> * * Delete a queue - freeing all the memory allocated for storing of items * placed on the queue. * * @param xQueue A handle to the queue to be deleted. * * \page vQueueDelete vQueueDelete * \ingroup QueueManagement / void vQueueDelete( xQueueHandle pxQueue ); /* * queue. h * <pre> portBASE_TYPE xQueueSendToFrontFromISR( xQueueHandle pxQueue, const void pvItemToQueue, portBASE_TYPE pxHigherPriorityTaskWoken ); </pre> * * This is a macro that calls xQueueGenericSendFromISR(). * * Post an item to the front of a queue. It is safe to use this macro from * within an interrupt service routine. * * Items are queued by copy not reference so it is preferable to only * queue small items, especially when called from an ISR. In most cases * it would be preferable to store a pointer to the item being queued. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set * pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task to unblock, and the unblocked task has a priority higher than the currently * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then * a context switch should be requested before the interrupt is exited. * * @return pdTRUE if the data was successfully sent to the queue, otherwise * errQUEUE_FULL. * * Example usage for buffered IO (where the ISR can obtain more than one value * per call): <pre> void vBufferISR( void ) { char cIn; portBASE_TYPE xHigherPrioritTaskWoken; // We have not woken a task at the start of the ISR. xHigherPriorityTaskWoken = pdFALSE; // Loop until the buffer is empty. do { // Obtain a byte from the buffer. cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); // Post the byte. xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); } while( portINPUT_BYTE( BUFFER_COUNT ) ); // Now the buffer is empty we can switch context if necessary. if( xHigherPriorityTaskWoken ) { taskYIELD (); } } </pre> * * \defgroup xQueueSendFromISR xQueueSendFromISR * \ingroup QueueManagement / #define xQueueSendToFrontFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) /* * queue. h * <pre> portBASE_TYPE xQueueSendToBackFromISR( xQueueHandle pxQueue, const void pvItemToQueue, portBASE_TYPE pxHigherPriorityTaskWoken ); </pre> * * This is a macro that calls xQueueGenericSendFromISR(). * * Post an item to the back of a queue. It is safe to use this macro from * within an interrupt service routine. * * Items are queued by copy not reference so it is preferable to only * queue small items, especially when called from an ISR. In most cases * it would be preferable to store a pointer to the item being queued. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set * pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task to unblock, and the unblocked task has a priority higher than the currently * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then * a context switch should be requested before the interrupt is exited. * * @return pdTRUE if the data was successfully sent to the queue, otherwise * errQUEUE_FULL. * * Example usage for buffered IO (where the ISR can obtain more than one value * per call): <pre> void vBufferISR( void ) { char cIn; portBASE_TYPE xHigherPriorityTaskWoken; // We have not woken a task at the start of the ISR. xHigherPriorityTaskWoken = pdFALSE; // Loop until the buffer is empty. do { // Obtain a byte from the buffer. cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); // Post the byte. xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); } while( portINPUT_BYTE( BUFFER_COUNT ) ); // Now the buffer is empty we can switch context if necessary. if( xHigherPriorityTaskWoken ) { taskYIELD (); } } </pre> * * \defgroup xQueueSendFromISR xQueueSendFromISR * \ingroup QueueManagement / #define xQueueSendToBackFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) /* * queue. h * <pre> portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void pvItemToQueue, portBASE_TYPE pxHigherPriorityTaskWoken ); </pre> * * This is a macro that calls xQueueGenericSendFromISR(). It is included * for backward compatibility with versions of FreeRTOS.org that did not * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() * macros. * * Post an item to the back of a queue. It is safe to use this function from * within an interrupt service routine. * * Items are queued by copy not reference so it is preferable to only * queue small items, especially when called from an ISR. In most cases * it would be preferable to store a pointer to the item being queued. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set * pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task to unblock, and the unblocked task has a priority higher than the currently * running task. If xQueueSendFromISR() sets this value to pdTRUE then * a context switch should be requested before the interrupt is exited. * * @return pdTRUE if the data was successfully sent to the queue, otherwise * errQUEUE_FULL. * * Example usage for buffered IO (where the ISR can obtain more than one value * per call): <pre> void vBufferISR( void ) { char cIn; portBASE_TYPE xHigherPriorityTaskWoken; // We have not woken a task at the start of the ISR. xHigherPriorityTaskWoken = pdFALSE; // Loop until the buffer is empty. do { // Obtain a byte from the buffer. cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); // Post the byte. xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); } while( portINPUT_BYTE( BUFFER_COUNT ) ); // Now the buffer is empty we can switch context if necessary. if( xHigherPriorityTaskWoken ) { // Actual macro used here is port specific. taskYIELD_FROM_ISR (); } } </pre> * * \defgroup xQueueSendFromISR xQueueSendFromISR * \ingroup QueueManagement / #define xQueueSendFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) /* * queue. h * <pre> portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void pvItemToQueue, portBASE_TYPE pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ); </pre> * * It is preferred that the macros xQueueSendFromISR(), * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place * of calling this function directly. * * Post an item on a queue. It is safe to use this function from within an * interrupt service routine. * * Items are queued by copy not reference so it is preferable to only * queue small items, especially when called from an ISR. In most cases * it would be preferable to store a pointer to the item being queued. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set * pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task to unblock, and the unblocked task has a priority higher than the currently * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then * a context switch should be requested before the interrupt is exited. * * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the * item at the back of the queue, or queueSEND_TO_FRONT to place the item * at the front of the queue (for high priority messages). * * @return pdTRUE if the data was successfully sent to the queue, otherwise * errQUEUE_FULL. * * Example usage for buffered IO (where the ISR can obtain more than one value * per call): <pre> void vBufferISR( void ) { char cIn; portBASE_TYPE xHigherPriorityTaskWokenByPost; // We have not woken a task at the start of the ISR. xHigherPriorityTaskWokenByPost = pdFALSE; // Loop until the buffer is empty. do { // Obtain a byte from the buffer. cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); // Post each byte. xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK ); } while( portINPUT_BYTE( BUFFER_COUNT ) ); // Now the buffer is empty we can switch context if necessary. Note that the // name of the yield function required is port specific. if( xHigherPriorityTaskWokenByPost ) { taskYIELD_YIELD_FROM_ISR(); } } </pre> * * \defgroup xQueueSendFromISR xQueueSendFromISR * \ingroup QueueManagement / signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void const pvItemToQueue, signed portBASE_TYPE pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ); /* * queue. h * <pre> portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void pvBuffer, portBASE_TYPE pxTaskWoken ); * </pre> * * Receive an item from a queue. It is safe to use this function from within an * interrupt service routine. * * @param pxQueue The handle to the queue from which the item is to be * received. * * @param pvBuffer Pointer to the buffer into which the received item will * be copied. * * @param pxTaskWoken A task may be blocked waiting for space to become * available on the queue. If xQueueReceiveFromISR causes such a task to * unblock pxTaskWoken will get set to pdTRUE, otherwise pxTaskWoken will * remain unchanged. * * @return pdTRUE if an item was successfully received from the queue, * otherwise pdFALSE. * * Example usage: <pre> xQueueHandle xQueue; // Function to create a queue and post some values. void vAFunction( void pvParameters ) { char cValueToPost; const portTickType xBlockTime = ( portTickType )0xff; // Create a queue capable of containing 10 characters. xQueue = xQueueCreate( 10, sizeof( char ) ); if( xQueue == 0 ) { // Failed to create the queue. } // ... // Post some characters that will be used within an ISR. If the queue // is full then this task will block for xBlockTime ticks. cValueToPost = 'a'; xQueueSend( xQueue, ( void ) &cValueToPost, xBlockTime ); cValueToPost = 'b'; xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime ); // ... keep posting characters ... this task may block when the queue // becomes full. cValueToPost = 'c'; xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime ); } // ISR that outputs all the characters received on the queue. void vISR_Routine( void ) { portBASE_TYPE xTaskWokenByReceive = pdFALSE; char cRxedChar; while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) ) { // A character was received. Output the character now. vOutputCharacter( cRxedChar ); // If removing the character from the queue woke the task that was // posting onto the queue cTaskWokenByReceive will have been set to // pdTRUE. No matter how many times this loop iterates only one // task will be woken. } if( cTaskWokenByPost != ( char ) pdFALSE; { taskYIELD (); } } </pre> * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR * \ingroup QueueManagement / signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void const pvBuffer, signed portBASE_TYPE pxTaskWoken ); / * Utilities to query queue that are safe to use from an ISR. These utilities * should be used only from witin an ISR, or within a critical section. / signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue ); signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue ); unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue ); / * xQueueAltGenericSend() is an alternative version of xQueueGenericSend(). * Likewise xQueueAltGenericReceive() is an alternative version of * xQueueGenericReceive(). * * The source code that implements the alternative (Alt) API is much * simpler because it executes everything from within a critical section. * This is the approach taken by many other RTOSes, but FreeRTOS.org has the * preferred fully featured API too. The fully featured API has more * complex code that takes longer to execute, but makes much less use of * critical sections. Therefore the alternative API sacrifices interrupt * responsiveness to gain execution speed, whereas the fully featured API * sacrifices execution speed to ensure better interrupt responsiveness. / signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ); #define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) #define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) #define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE ) #define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE ) /* * The functions defined above are for passing data to and from tasks. The * functions below are the equivalents for passing data to and from * co-routines. * * These functions are called from the co-routine macro implementation and * should not be called directly from application code. Instead use the macro * wrappers defined within croutine.h. / signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void pvBuffer, signed portBASE_TYPE pxTaskWoken ); signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void pvItemToQueue, portTickType xTicksToWait ); signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void pvBuffer, portTickType xTicksToWait ); /* * For internal use only. Use xSemaphoreCreateMutex() or * xSemaphoreCreateCounting() instead of calling these functions directly. / xQueueHandle xQueueCreateMutex( void ); xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ); / * For internal use only. Use xSemaphoreTakeMutexRecursive() or * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. / portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime ); portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex ); / * The registry is provided as a means for kernel aware debuggers to * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add * a queue, semaphore or mutex handle to the registry if you want the handle * to be available to a kernel aware debugger. If you are not using a kernel * aware debugger then this function can be ignored. * * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 * within FreeRTOSConfig.h for the registry to be available. Its value * does not effect the number of queues, semaphores and mutexes that can be * created - just the number that the registry can hold. * * @param xQueue The handle of the queue being added to the registry. This * is the handle returned by a call to xQueueCreate(). Semaphore and mutex * handles can also be passed in here. * * @param pcName The name to be associated with the handle. This is the * name that the kernel aware debugger will display. / #if configQUEUE_REGISTRY_SIZE > 0U void vQueueAddToRegistry( xQueueHandle xQueue, signed char pcName ); #endif /* Not a public API function, hence the 'Restricted' in the name. / void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait ); #ifdef __cplusplus } #endif #endif / QUEUE_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/queue.h	C	oos	44,191
/* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. *************************************************************************** * * * FreeRTOS tutorial books are available in pdf and paperback. * * Complete, revised, and edited pdf reference manuals are also * * available. * * * * Purchasing FreeRTOS documentation will not only help you, by * * ensuring you get running as quickly as possible and with an * * in-depth knowledge of how to use FreeRTOS, it will also help * * the FreeRTOS project to continue with its mission of providing * * professional grade, cross platform, de facto standard solutions * * for microcontrollers - completely free of charge! * * * * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * * * * Thank you for using FreeRTOS, and thank you for your support! * * * *************************************************************************** This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation AND MODIFIED BY the FreeRTOS exception. >>>NOTE<<< The modification to the GPL is included to allow you to distribute a combined work that includes FreeRTOS without being obliged to provide the source code for proprietary components outside of the FreeRTOS kernel. FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the FreeRTOS license exception along with FreeRTOS; if not it can be viewed here: http://www.freertos.org/a00114.html and also obtained by writing to Richard Barry, contact details for whom are available on the FreeRTOS WEB site. 1 tab == 4 spaces! http://www.FreeRTOS.org - Documentation, latest information, license and contact details. http://www.SafeRTOS.com - A version that is certified for use in safety critical systems. http://www.OpenRTOS.com - Commercial support, development, porting, licensing and training services. / #ifndef CO_ROUTINE_H #define CO_ROUTINE_H #ifndef INC_FREERTOS_H #error "include FreeRTOS.h must appear in source files before include croutine.h" #endif #include "list.h" #ifdef __cplusplus extern "C" { #endif / Used to hide the implementation of the co-routine control block. The control block structure however has to be included in the header due to the macro implementation of the co-routine functionality. / typedef void xCoRoutineHandle; /* Defines the prototype to which co-routine functions must conform. / typedef void (crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); typedef struct corCoRoutineControlBlock { crCOROUTINE_CODE pxCoRoutineFunction; xListItem xGenericListItem; /< List item used to place the CRCB in ready and blocked queues. / xListItem xEventListItem; /< List item used to place the CRCB in event lists. / unsigned portBASE_TYPE uxPriority; /< The priority of the co-routine in relation to other co-routines. / unsigned portBASE_TYPE uxIndex; /< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. / unsigned short uxState; /< Used internally by the co-routine implementation. / } corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. / /* * croutine. h <pre> portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex );</pre> * Create a new co-routine and add it to the list of co-routines that are * ready to run. * * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine * functions require special syntax - see the co-routine section of the WEB * documentation for more information. * * @param uxPriority The priority with respect to other co-routines at which * the co-routine will run. * * @param uxIndex Used to distinguish between different co-routines that * execute the same function. See the example below and the co-routine section * of the WEB documentation for further information. * * @return pdPASS if the co-routine was successfully created and added to a ready * list, otherwise an error code defined with ProjDefs.h. * * Example usage: <pre> // Co-routine to be created. void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { // Variables in co-routines must be declared static if they must maintain value across a blocking call. // This may not be necessary for const variables. static const char cLedToFlash[ 2 ] = { 5, 6 }; static const portTickType uxFlashRates[ 2 ] = { 200, 400 }; // Must start every co-routine with a call to crSTART(); crSTART( xHandle ); for( ;; ) { // This co-routine just delays for a fixed period, then toggles // an LED. Two co-routines are created using this function, so // the uxIndex parameter is used to tell the co-routine which // LED to flash and how long to delay. This assumes xQueue has // already been created. vParTestToggleLED( cLedToFlash[ uxIndex ] ); crDELAY( xHandle, uxFlashRates[ uxIndex ] ); } // Must end every co-routine with a call to crEND(); crEND(); } // Function that creates two co-routines. void vOtherFunction( void ) { unsigned char ucParameterToPass; xTaskHandle xHandle; // Create two co-routines at priority 0. The first is given index 0 // so (from the code above) toggles LED 5 every 200 ticks. The second // is given index 1 so toggles LED 6 every 400 ticks. for( uxIndex = 0; uxIndex < 2; uxIndex++ ) { xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex ); } } </pre> * \defgroup xCoRoutineCreate xCoRoutineCreate * \ingroup Tasks / signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); /* * croutine. h <pre> void vCoRoutineSchedule( void );</pre> * Run a co-routine. * * vCoRoutineSchedule() executes the highest priority co-routine that is able * to run. The co-routine will execute until it either blocks, yields or is * preempted by a task. Co-routines execute cooperatively so one * co-routine cannot be preempted by another, but can be preempted by a task. * * If an application comprises of both tasks and co-routines then * vCoRoutineSchedule should be called from the idle task (in an idle task * hook). * * Example usage: <pre> // This idle task hook will schedule a co-routine each time it is called. // The rest of the idle task will execute between co-routine calls. void vApplicationIdleHook( void ) { vCoRoutineSchedule(); } // Alternatively, if you do not require any other part of the idle task to // execute, the idle task hook can call vCoRoutineScheduler() within an // infinite loop. void vApplicationIdleHook( void ) { for( ;; ) { vCoRoutineSchedule(); } } </pre> * \defgroup vCoRoutineSchedule vCoRoutineSchedule * \ingroup Tasks / void vCoRoutineSchedule( void ); /* * croutine. h * <pre> crSTART( xCoRoutineHandle xHandle );</pre> * * This macro MUST always be called at the start of a co-routine function. * * Example usage: <pre> // Co-routine to be created. void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { // Variables in co-routines must be declared static if they must maintain value across a blocking call. static long ulAVariable; // Must start every co-routine with a call to crSTART(); crSTART( xHandle ); for( ;; ) { // Co-routine functionality goes here. } // Must end every co-routine with a call to crEND(); crEND(); }</pre> * \defgroup crSTART crSTART * \ingroup Tasks / #define crSTART( pxCRCB ) switch( ( ( corCRCB )( pxCRCB ) )->uxState ) { case 0: /** * croutine. h * <pre> crEND();</pre> * * This macro MUST always be called at the end of a co-routine function. * * Example usage: <pre> // Co-routine to be created. void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { // Variables in co-routines must be declared static if they must maintain value across a blocking call. static long ulAVariable; // Must start every co-routine with a call to crSTART(); crSTART( xHandle ); for( ;; ) { // Co-routine functionality goes here. } // Must end every co-routine with a call to crEND(); crEND(); }</pre> * \defgroup crSTART crSTART * \ingroup Tasks / #define crEND() } / * These macros are intended for internal use by the co-routine implementation * only. The macros should not be used directly by application writers. / #define crSET_STATE0( xHandle ) ( ( corCRCB )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): #define crSET_STATE1( xHandle ) ( ( corCRCB * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): /** * croutine. h <pre> crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );</pre> * Delay a co-routine for a fixed period of time. * * crDELAY can only be called from the co-routine function itself - not * from within a function called by the co-routine function. This is because * co-routines do not maintain their own stack. * * @param xHandle The handle of the co-routine to delay. This is the xHandle * parameter of the co-routine function. * * @param xTickToDelay The number of ticks that the co-routine should delay * for. The actual amount of time this equates to is defined by * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS * can be used to convert ticks to milliseconds. * * Example usage: <pre> // Co-routine to be created. void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { // Variables in co-routines must be declared static if they must maintain value across a blocking call. // This may not be necessary for const variables. // We are to delay for 200ms. static const xTickType xDelayTime = 200 / portTICK_RATE_MS; // Must start every co-routine with a call to crSTART(); crSTART( xHandle ); for( ;; ) { // Delay for 200ms. crDELAY( xHandle, xDelayTime ); // Do something here. } // Must end every co-routine with a call to crEND(); crEND(); }</pre> * \defgroup crDELAY crDELAY * \ingroup Tasks / #define crDELAY( xHandle, xTicksToDelay ) \ if( ( xTicksToDelay ) > 0 ) \ { \ vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ } \ crSET_STATE0( ( xHandle ) ); /* * <pre> crQUEUE_SEND( xCoRoutineHandle xHandle, xQueueHandle pxQueue, void pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE pxResult )</pre> * * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. * * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas * xQueueSend() and xQueueReceive() can only be used from tasks. * * crQUEUE_SEND can only be called from the co-routine function itself - not * from within a function called by the co-routine function. This is because * co-routines do not maintain their own stack. * * See the co-routine section of the WEB documentation for information on * passing data between tasks and co-routines and between ISR's and * co-routines. * * @param xHandle The handle of the calling co-routine. This is the xHandle * parameter of the co-routine function. * * @param pxQueue The handle of the queue on which the data will be posted. * The handle is obtained as the return value when the queue is created using * the xQueueCreate() API function. * * @param pvItemToQueue A pointer to the data being posted onto the queue. * The number of bytes of each queued item is specified when the queue is * created. This number of bytes is copied from pvItemToQueue into the queue * itself. * * @param xTickToDelay The number of ticks that the co-routine should block * to wait for space to become available on the queue, should space not be * available immediately. The actual amount of time this equates to is defined * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example * below). * * @param pxResult The variable pointed to by pxResult will be set to pdPASS if * data was successfully posted onto the queue, otherwise it will be set to an * error defined within ProjDefs.h. * * Example usage: <pre> // Co-routine function that blocks for a fixed period then posts a number onto // a queue. static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { // Variables in co-routines must be declared static if they must maintain value across a blocking call. static portBASE_TYPE xNumberToPost = 0; static portBASE_TYPE xResult; // Co-routines must begin with a call to crSTART(). crSTART( xHandle ); for( ;; ) { // This assumes the queue has already been created. crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult ); if( xResult != pdPASS ) { // The message was not posted! } // Increment the number to be posted onto the queue. xNumberToPost++; // Delay for 100 ticks. crDELAY( xHandle, 100 ); } // Co-routines must end with a call to crEND(). crEND(); }</pre> * \defgroup crQUEUE_SEND crQUEUE_SEND * \ingroup Tasks / #define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ { \ ( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ if( ( pxResult ) == errQUEUE_BLOCKED ) \ { \ crSET_STATE0( ( xHandle ) ); \ pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ } \ if( pxResult == errQUEUE_YIELD ) \ { \ crSET_STATE1( ( xHandle ) ); \ pxResult = pdPASS; \ } \ } /** * croutine. h * <pre> crQUEUE_RECEIVE( xCoRoutineHandle xHandle, xQueueHandle pxQueue, void pvBuffer, portTickType xTicksToWait, portBASE_TYPE pxResult )</pre> * * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. * * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas * xQueueSend() and xQueueReceive() can only be used from tasks. * * crQUEUE_RECEIVE can only be called from the co-routine function itself - not * from within a function called by the co-routine function. This is because * co-routines do not maintain their own stack. * * See the co-routine section of the WEB documentation for information on * passing data between tasks and co-routines and between ISR's and * co-routines. * * @param xHandle The handle of the calling co-routine. This is the xHandle * parameter of the co-routine function. * * @param pxQueue The handle of the queue from which the data will be received. * The handle is obtained as the return value when the queue is created using * the xQueueCreate() API function. * * @param pvBuffer The buffer into which the received item is to be copied. * The number of bytes of each queued item is specified when the queue is * created. This number of bytes is copied into pvBuffer. * * @param xTickToDelay The number of ticks that the co-routine should block * to wait for data to become available from the queue, should data not be * available immediately. The actual amount of time this equates to is defined * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the * crQUEUE_SEND example). * * @param pxResult The variable pointed to by pxResult will be set to pdPASS if * data was successfully retrieved from the queue, otherwise it will be set to * an error code as defined within ProjDefs.h. * * Example usage: <pre> // A co-routine receives the number of an LED to flash from a queue. It // blocks on the queue until the number is received. static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { // Variables in co-routines must be declared static if they must maintain value across a blocking call. static portBASE_TYPE xResult; static unsigned portBASE_TYPE uxLEDToFlash; // All co-routines must start with a call to crSTART(). crSTART( xHandle ); for( ;; ) { // Wait for data to become available on the queue. crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); if( xResult == pdPASS ) { // We received the LED to flash - flash it! vParTestToggleLED( uxLEDToFlash ); } } crEND(); }</pre> * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE * \ingroup Tasks / #define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ { \ ( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ if( ( pxResult ) == errQUEUE_BLOCKED ) \ { \ crSET_STATE0( ( xHandle ) ); \ ( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ } \ if( ( pxResult ) == errQUEUE_YIELD ) \ { \ crSET_STATE1( ( xHandle ) ); \ ( pxResult ) = pdPASS; \ } \ } /** * croutine. h * <pre> crQUEUE_SEND_FROM_ISR( xQueueHandle pxQueue, void pvItemToQueue, portBASE_TYPE xCoRoutinePreviouslyWoken )</pre> * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() * functions used by tasks. * * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and * xQueueReceiveFromISR() can only be used to pass data between a task and and * ISR. * * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue * that is being used from within a co-routine. * * See the co-routine section of the WEB documentation for information on * passing data between tasks and co-routines and between ISR's and * co-routines. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvItemToQueue A pointer to the item that is to be placed on the * queue. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from pvItemToQueue * into the queue storage area. * * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto * the same queue multiple times from a single interrupt. The first call * should always pass in pdFALSE. Subsequent calls should pass in * the value returned from the previous call. * * @return pdTRUE if a co-routine was woken by posting onto the queue. This is * used by the ISR to determine if a context switch may be required following * the ISR. * * Example usage: <pre> // A co-routine that blocks on a queue waiting for characters to be received. static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { char cRxedChar; portBASE_TYPE xResult; // All co-routines must start with a call to crSTART(). crSTART( xHandle ); for( ;; ) { // Wait for data to become available on the queue. This assumes the // queue xCommsRxQueue has already been created! crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); // Was a character received? if( xResult == pdPASS ) { // Process the character here. } } // All co-routines must end with a call to crEND(). crEND(); } // An ISR that uses a queue to send characters received on a serial port to // a co-routine. void vUART_ISR( void ) { char cRxedChar; portBASE_TYPE xCRWokenByPost = pdFALSE; // We loop around reading characters until there are none left in the UART. while( UART_RX_REG_NOT_EMPTY() ) { // Obtain the character from the UART. cRxedChar = UART_RX_REG; // Post the character onto a queue. xCRWokenByPost will be pdFALSE // the first time around the loop. If the post causes a co-routine // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE. // In this manner we can ensure that if more than one co-routine is // blocked on the queue only one is woken by this ISR no matter how // many characters are posted to the queue. xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost ); } }</pre> * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR * \ingroup Tasks / #define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) /* * croutine. h * <pre> crQUEUE_SEND_FROM_ISR( xQueueHandle pxQueue, void pvBuffer, portBASE_TYPE pxCoRoutineWoken )</pre> * * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() * functions used by tasks. * * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and * xQueueReceiveFromISR() can only be used to pass data between a task and and * ISR. * * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data * from a queue that is being used from within a co-routine (a co-routine * posted to the queue). * * See the co-routine section of the WEB documentation for information on * passing data between tasks and co-routines and between ISR's and * co-routines. * * @param xQueue The handle to the queue on which the item is to be posted. * * @param pvBuffer A pointer to a buffer into which the received item will be * placed. The size of the items the queue will hold was defined when the * queue was created, so this many bytes will be copied from the queue into * pvBuffer. * * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a * co-routine to unblock pxCoRoutineWoken will get set to pdTRUE, otherwise pxCoRoutineWoken will remain unchanged. * @return pdTRUE an item was successfully received from the queue, otherwise * pdFALSE. * * Example usage: <pre> // A co-routine that posts a character to a queue then blocks for a fixed // period. The character is incremented each time. static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) { // cChar holds its value while this co-routine is blocked and must therefore // be declared static. static char cCharToTx = 'a'; portBASE_TYPE xResult; // All co-routines must start with a call to crSTART(). crSTART( xHandle ); for( ;; ) { // Send the next character to the queue. crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult ); if( xResult == pdPASS ) { // The character was successfully posted to the queue. } else { // Could not post the character to the queue. } // Enable the UART Tx interrupt to cause an interrupt in this // hypothetical UART. The interrupt will obtain the character // from the queue and send it. ENABLE_RX_INTERRUPT(); // Increment to the next character then block for a fixed period. // cCharToTx will maintain its value across the delay as it is // declared static. cCharToTx++; if( cCharToTx > 'x' ) { cCharToTx = 'a'; } crDELAY( 100 ); } // All co-routines must end with a call to crEND(). crEND(); } // An ISR that uses a queue to receive characters to send on a UART. void vUART_ISR( void ) { char cCharToTx; portBASE_TYPE xCRWokenByPost = pdFALSE; while( UART_TX_REG_EMPTY() ) { // Are there any characters in the queue waiting to be sent? // xCRWokenByPost will automatically be set to pdTRUE if a co-routine // is woken by the post - ensuring that only a single co-routine is // woken no matter how many times we go around this loop. if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) ) { SEND_CHARACTER( cCharToTx ); } } }</pre> * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR * \ingroup Tasks / #define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) / * This function is intended for internal use by the co-routine macros only. * The macro nature of the co-routine implementation requires that the * prototype appears here. The function should not be used by application * writers. * * Removes the current co-routine from its ready list and places it in the * appropriate delayed list. / void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList pxEventList ); /* * This function is intended for internal use by the queue implementation only. * The function should not be used by application writers. * * Removes the highest priority co-routine from the event list and places it in * the pending ready list. / signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList pxEventList ); #ifdef __cplusplus } #endif #endif /* CO_ROUTINE_H */	zz314326255--adkping	adkping/iNEMO-accessory/FreeRTOSv7.0.2/Source/include/croutine.h	C	oos	28,423
/* * Copyright (C) 2011 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / #include <Max3421e.h> #include <Usb.h> #include <AndroidAccessory.h> #define USB_ACCESSORY_VENDOR_ID 0x18D1 #define USB_ACCESSORY_PRODUCT_ID 0x2D00 #define USB_ACCESSORY_ADB_PRODUCT_ID 0x2D01 #define ACCESSORY_STRING_MANUFACTURER 0 #define ACCESSORY_STRING_MODEL 1 #define ACCESSORY_STRING_DESCRIPTION 2 #define ACCESSORY_STRING_VERSION 3 #define ACCESSORY_STRING_URI 4 #define ACCESSORY_STRING_SERIAL 5 #define ACCESSORY_GET_PROTOCOL 51 #define ACCESSORY_SEND_STRING 52 #define ACCESSORY_START 53 AndroidAccessory::AndroidAccessory(const char manufacturer, const char model, const char description, const char version, const char uri, const char serial) : manufacturer(manufacturer), model(model), description(description), version(version), uri(uri), serial(serial), connected(false) { } void AndroidAccessory::powerOn(void) { max.powerOn(); delay(200); } int AndroidAccessory::getProtocol(byte addr) { uint16_t protocol = -1; usb.ctrlReq(addr, 0, USB_SETUP_DEVICE_TO_HOST \| USB_SETUP_TYPE_VENDOR \| USB_SETUP_RECIPIENT_DEVICE, ACCESSORY_GET_PROTOCOL, 0, 0, 0, 2, (char )&protocol); return protocol; } void AndroidAccessory::sendString(byte addr, int index, const char str) { usb.ctrlReq(addr, 0, USB_SETUP_HOST_TO_DEVICE \| USB_SETUP_TYPE_VENDOR \| USB_SETUP_RECIPIENT_DEVICE, ACCESSORY_SEND_STRING, 0, 0, index, strlen(str) + 1, (char )str); } bool AndroidAccessory::switchDevice(byte addr) { int protocol = getProtocol(addr); if (protocol == 1) { Serial.print("device supports protcol 1\n"); } else { Serial.print("could not read device protocol version\n"); return false; } sendString(addr, ACCESSORY_STRING_MANUFACTURER, manufacturer); sendString(addr, ACCESSORY_STRING_MODEL, model); sendString(addr, ACCESSORY_STRING_DESCRIPTION, description); sendString(addr, ACCESSORY_STRING_VERSION, version); sendString(addr, ACCESSORY_STRING_URI, uri); sendString(addr, ACCESSORY_STRING_SERIAL, serial); usb.ctrlReq(addr, 0, USB_SETUP_HOST_TO_DEVICE \| USB_SETUP_TYPE_VENDOR \| USB_SETUP_RECIPIENT_DEVICE, ACCESSORY_START, 0, 0, 0, 0, NULL); while (usb.getUsbTaskState() != USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE) { max.Task(); usb.Task(); } return true; } // Finds the first bulk IN and bulk OUT endpoints bool AndroidAccessory::findEndpoints(byte addr, EP_RECORD inEp, EP_RECORD outEp) { int len; byte err; uint8_t p; err = usb.getConfDescr(addr, 0, 4, 0, (char )descBuff); if (err) { Serial.print("Can't get config descriptor length\n"); return false; } len = descBuff[2] \| ((int)descBuff[3] << 8); if (len > sizeof(descBuff)) { Serial.print("config descriptor too large\n"); /* might want to truncate here / return false; } err = usb.getConfDescr(addr, 0, len, 0, (char )descBuff); if (err) { Serial.print("Can't get config descriptor\n"); return false; } p = descBuff; inEp->epAddr = 0; outEp->epAddr = 0; while (p < (descBuff + len)){ uint8_t descLen = p[0]; uint8_t descType = p[1]; USB_ENDPOINT_DESCRIPTOR epDesc; EP_RECORD ep; switch (descType) { case USB_DESCRIPTOR_CONFIGURATION: Serial.print("config desc\n"); break; case USB_DESCRIPTOR_INTERFACE: Serial.print("interface desc\n"); break; case USB_DESCRIPTOR_ENDPOINT: epDesc = (USB_ENDPOINT_DESCRIPTOR )p; if (!inEp->epAddr && (epDesc->bEndpointAddress & 0x80)) ep = inEp; else if (!outEp->epAddr) ep = outEp; else ep = NULL; if (ep) { ep->epAddr = epDesc->bEndpointAddress & 0x7f; ep->Attr = epDesc->bmAttributes; ep->MaxPktSize = epDesc->wMaxPacketSize; ep->sndToggle = bmSNDTOG0; ep->rcvToggle = bmRCVTOG0; } break; default: Serial.print("unkown desc type "); Serial.println( descType, HEX); break; } p += descLen; } if (!(inEp->epAddr && outEp->epAddr)) Serial.println("can't find accessory endpoints"); return inEp->epAddr && outEp->epAddr; } bool AndroidAccessory::configureAndroid(void) { byte err; EP_RECORD inEp, outEp; if (!findEndpoints(1, &inEp, &outEp)) return false; memset(&epRecord, 0x0, sizeof(epRecord)); epRecord[inEp.epAddr] = inEp; if (outEp.epAddr != inEp.epAddr) epRecord[outEp.epAddr] = outEp; in = inEp.epAddr; out = outEp.epAddr; Serial.println(inEp.epAddr, HEX); Serial.println(outEp.epAddr, HEX); epRecord[0] = (usb.getDevTableEntry(0,0)); usb.setDevTableEntry(1, epRecord); err = usb.setConf( 1, 0, 1 ); if (err) { Serial.print("Can't set config to 1\n"); return false; } usb.setUsbTaskState( USB_STATE_RUNNING ); return true; } bool AndroidAccessory::isConnected(void) { USB_DEVICE_DESCRIPTOR devDesc = (USB_DEVICE_DESCRIPTOR ) descBuff; byte err; max.Task(); usb.Task(); if (!connected && usb.getUsbTaskState() >= USB_STATE_CONFIGURING && usb.getUsbTaskState() != USB_STATE_RUNNING) { Serial.print("\nDevice addressed... "); Serial.print("Requesting device descriptor.\n"); err = usb.getDevDescr(1, 0, 0x12, (char ) devDesc); if (err) { Serial.print("\nDevice descriptor cannot be retrieved. Trying again\n"); return false; } if (isAccessoryDevice(devDesc)) { Serial.print("found android acessory device\n"); connected = configureAndroid(); } else { Serial.print("found possible device. swithcing to serial mode\n"); switchDevice(1); } } else if (usb.getUsbTaskState() == USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE) { if (connected) Serial.println("disconnect\n"); connected = false; } return connected; } int AndroidAccessory::read(void buff, int len, unsigned int nakLimit) { return usb.newInTransfer(1, in, len, (char )buff, nakLimit); } int AndroidAccessory::write(void buff, int len) { usb.outTransfer(1, out, len, (char *)buff); return len; }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/AndroidAccessory/AndroidAccessory.cpp	C++	oos	7,917
/* * Copyright (C) 2011 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / #ifndef __AndroidAccessory_h__ #define __AndroidAccessory_h__ #include "WProgram.h" class AndroidAccessory { private: const char manufacturer; const char model; const char description; const char version; const char uri; const char serial; MAX3421E max; USB usb; bool connected; uint8_t in; uint8_t out; EP_RECORD epRecord[8]; uint8_t descBuff[256]; bool isAccessoryDevice(USB_DEVICE_DESCRIPTOR desc) { return desc->idVendor == 0x18d1 && (desc->idProduct == 0x2D00 \|\| desc->idProduct == 0x2D01); } int getProtocol(byte addr); void sendString(byte addr, int index, const char str); bool switchDevice(byte addr); bool findEndpoints(byte addr, EP_RECORD inEp, EP_RECORD outEp); bool configureAndroid(void); public: AndroidAccessory(const char manufacturer, const char model, const char description, const char version, const char uri, const char serial); void powerOn(void); bool isConnected(void); int read(void buff, int len, unsigned int nakLimit = USB_NAK_LIMIT); int write(void buff, int len); }; #endif / __AndroidAccessory_h__ */	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/AndroidAccessory/AndroidAccessory.h	C++	oos	1,914
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. / / MAX3421E functions / #ifndef _MAX3421E_H_ #define _MAX3421E_H_ //#include <Spi.h> //#include <WProgram.h> #include "WProgram.h" #include "Max3421e_constants.h" class MAX3421E / : public SPI / { // byte vbusState; public: MAX3421E( void ); byte getVbusState( void ); // void toggle( byte pin ); static void regWr( byte, byte ); char bytesWr( byte, byte, char * ); static void gpioWr( byte ); byte regRd( byte ); char * bytesRd( byte, byte, char * ); byte gpioRd( void ); boolean reset(); boolean vbusPwr ( boolean ); void busprobe( void ); void powerOn(); byte IntHandler(); byte GpxHandler(); byte Task(); private: static void pinInit(void); static void setRST(uint8_t val); static uint8_t readINT(void); static uint8_t readGPX(void); static void spi_init() { uint8_t tmp; // initialize SPI pins pinMode(SCK_PIN, OUTPUT); pinMode(MOSI_PIN, OUTPUT); pinMode(MISO_PIN, INPUT); pinMode(SS_PIN, OUTPUT); /* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E / SPCR = 0x50; SPSR = 0x01; /*/ tmp = SPSR; tmp = SPDR; } // void init(); friend class Max_LCD; }; #endif //_MAX3421E_H_	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/Max3421e.h	C++	oos	3,085
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. / //this code is heavily borrowed from official Arduino source v.0017 // link to original http://code.google.com/p/arduino/source/browse/trunk/hardware/libraries/LiquidCrystal/LiquidCrystal.cpp #include "Max_LCD.h" #include "Max3421e.h" #include <stdio.h> #include <string.h> #include <inttypes.h> #include "WProgram.h" // When the display powers up, it is configured as follows: // // 1. Display clear // 2. Function set: // DL = 1; 8-bit interface data // N = 0; 1-line display // F = 0; 5x8 dot character font // 3. Display on/off control: // D = 0; Display off // C = 0; Cursor off // B = 0; Blinking off // 4. Entry mode set: // I/D = 1; Increment by 1 // S = 0; No shift // // Note, however, that resetting the Arduino doesn't reset the LCD, so we // can't assume that it's in that state when a sketch starts // pin definition and set/clear #define RS 0x04 // RS pin #define E 0x08 // E pin #define SET_RS lcdPins \|= RS #define CLR_RS lcdPins &= ~RS #define SET_E lcdPins \|= E #define CLR_E lcdPins &= ~E #define SENDlcdPins() MAX3421E::gpioWr( lcdPins ) #define LCD_sendcmd(a) { CLR_RS; \ sendbyte(a); \ } #define LCD_sendchar(a) { SET_RS; \ sendbyte(a); \ } static byte lcdPins; //copy of LCD pins Max_LCD::Max_LCD() { lcdPins = 0; } void Max_LCD::init() { _displayfunction = LCD_4BITMODE \| LCD_1LINE \| LCD_5x8DOTS; // MAX3421E::gpioWr(0x55); begin(16, 1); } void Max_LCD::begin(uint8_t cols, uint8_t lines, uint8_t dotsize) { if (lines > 1) { _displayfunction \|= LCD_2LINE; } _numlines = lines; _currline = 0; // for some 1 line displays you can select a 10 pixel high font if ((dotsize != 0) && (lines == 1)) { _displayfunction \|= LCD_5x10DOTS; } // SEE PAGE 45/46 FOR INITIALIZATION SPECIFICATION! // according to datasheet, we need at least 40ms after power rises above 2.7V // before sending commands. Arduino can turn on way befer 4.5V so we'll wait 50 delayMicroseconds(50000); lcdPins = 0x30; SET_E; SENDlcdPins(); CLR_E; SENDlcdPins(); delayMicroseconds(10000); // wait min 4.1ms //second try SET_E; SENDlcdPins(); CLR_E; SENDlcdPins(); delayMicroseconds(10000); // wait min 4.1ms // third go! SET_E; SENDlcdPins(); CLR_E; SENDlcdPins(); delayMicroseconds(10000); // finally, set to 4-bit interface lcdPins = 0x20; //SET_RS; SET_E; SENDlcdPins(); //CLR_RS; CLR_E; SENDlcdPins(); delayMicroseconds(10000); // finally, set # lines, font size, etc. command(LCD_FUNCTIONSET \| _displayfunction); // turn the display on with no cursor or blinking default _displaycontrol = LCD_DISPLAYON \| LCD_CURSOROFF \| LCD_BLINKOFF; display(); // clear it off clear(); // Initialize to default text direction (for romance languages) _displaymode = LCD_ENTRYLEFT \| LCD_ENTRYSHIFTDECREMENT; // set the entry mode command(LCD_ENTRYMODESET \| _displaymode); } /********* high level commands, for the user! / void Max_LCD::clear() { command(LCD_CLEARDISPLAY); // clear display, set cursor position to zero delayMicroseconds(2000); // this command takes a long time! } void Max_LCD::home() { command(LCD_RETURNHOME); // set cursor position to zero delayMicroseconds(2000); // this command takes a long time! } void Max_LCD::setCursor(uint8_t col, uint8_t row) { int row_offsets[] = { 0x00, 0x40, 0x14, 0x54 }; if ( row > _numlines ) { row = _numlines-1; // we count rows starting w/0 } command(LCD_SETDDRAMADDR \| (col + row_offsets[row])); } // Turn the display on/off (quickly) void Max_LCD::noDisplay() { _displaycontrol &= ~LCD_DISPLAYON; command(LCD_DISPLAYCONTROL \| _displaycontrol); } void Max_LCD::display() { _displaycontrol \|= LCD_DISPLAYON; command(LCD_DISPLAYCONTROL \| _displaycontrol); } // Turns the underline cursor on/off void Max_LCD::noCursor() { _displaycontrol &= ~LCD_CURSORON; command(LCD_DISPLAYCONTROL \| _displaycontrol); } void Max_LCD::cursor() { _displaycontrol \|= LCD_CURSORON; command(LCD_DISPLAYCONTROL \| _displaycontrol); } // Turn on and off the blinking cursor void Max_LCD::noBlink() { _displaycontrol &= ~LCD_BLINKON; command(LCD_DISPLAYCONTROL \| _displaycontrol); } void Max_LCD::blink() { _displaycontrol \|= LCD_BLINKON; command(LCD_DISPLAYCONTROL \| _displaycontrol); } // These commands scroll the display without changing the RAM void Max_LCD::scrollDisplayLeft(void) { command(LCD_CURSORSHIFT \| LCD_DISPLAYMOVE \| LCD_MOVELEFT); } void Max_LCD::scrollDisplayRight(void) { command(LCD_CURSORSHIFT \| LCD_DISPLAYMOVE \| LCD_MOVERIGHT); } // This is for text that flows Left to Right void Max_LCD::leftToRight(void) { _displaymode \|= LCD_ENTRYLEFT; command(LCD_ENTRYMODESET \| _displaymode); } // This is for text that flows Right to Left void Max_LCD::rightToLeft(void) { _displaymode &= ~LCD_ENTRYLEFT; command(LCD_ENTRYMODESET \| _displaymode); } // This will 'right justify' text from the cursor void Max_LCD::autoscroll(void) { _displaymode \|= LCD_ENTRYSHIFTINCREMENT; command(LCD_ENTRYMODESET \| _displaymode); } // This will 'left justify' text from the cursor void Max_LCD::noAutoscroll(void) { _displaymode &= ~LCD_ENTRYSHIFTINCREMENT; command(LCD_ENTRYMODESET \| _displaymode); } // Allows us to fill the first 8 CGRAM locations // with custom characters void Max_LCD::createChar(uint8_t location, uint8_t charmap[]) { location &= 0x7; // we only have 8 locations 0-7 command(LCD_SETCGRAMADDR \| (location << 3)); for (int i=0; i<8; i++) { write(charmap[i]); } } /********** mid level commands, for sending data/cmds */ inline void Max_LCD::command(uint8_t value) { LCD_sendcmd(value); delayMicroseconds(100); } inline void Max_LCD::write(uint8_t value) { LCD_sendchar(value); } void Max_LCD::sendbyte( uint8_t val ) { lcdPins &= 0x0f; //prepare place for the upper nibble lcdPins \|= ( val & 0xf0 ); //copy upper nibble to LCD variable SET_E; //send SENDlcdPins(); delayMicroseconds(2); CLR_E; delayMicroseconds(2); SENDlcdPins(); lcdPins &= 0x0f; //prepare place for the lower nibble lcdPins \|= ( val << 4 ) & 0xf0; //copy lower nibble to LCD variable SET_E; //send SENDlcdPins(); CLR_E; SENDlcdPins(); delayMicroseconds(100); }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/Max_LCD.cpp	C++	oos	8,475
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. / / MAX3421E USB host controller support / #include "Max3421e.h" // #include "Max3421e_constants.h" static byte vbusState; / Functions / #define INT PE6 #define INT_PORT PORTE #define INT_DDR DDRE #define INT_PIN PINE #define RST PJ2 #define RST_PORT PORTJ #define RST_DDR DDRJ #define RST_PIN PINJ #define GPX PJ3 #define GPX_PORT PORTJ #define GPX_DDR DDRJ #define GPX_PIN PINJ void MAX3421E::setRST(uint8_t val) { if (val == LOW) RST_PORT &= ~_BV(RST); else RST_PORT \|= _BV(RST); } uint8_t MAX3421E::readINT(void) { return INT_PIN & _BV(INT) ? HIGH : LOW; } uint8_t MAX3421E::readGPX(void) { // return GPX_PIN & _BV(GPX) ? HIGH : LOW; return LOW; } void MAX3421E::pinInit(void) { INT_DDR &= ~_BV(INT); RST_DDR \|= _BV(RST); digitalWrite(MAX_SS,HIGH); setRST(HIGH); } / Constructor / MAX3421E::MAX3421E() { spi_init(); pinInit(); } byte MAX3421E::getVbusState( void ) { return( vbusState ); } / initialization / //void MAX3421E::init() //{ // / setup pins / // pinMode( MAX_INT, INPUT); // pinMode( MAX_GPX, INPUT ); // pinMode( MAX_SS, OUTPUT ); // //pinMode( BPNT_0, OUTPUT ); // //pinMode( BPNT_1, OUTPUT ); // //digitalWrite( BPNT_0, LOW ); // //digitalWrite( BPNT_1, LOW ); // Deselect_MAX3421E; // pinMode( MAX_RESET, OUTPUT ); // digitalWrite( MAX_RESET, HIGH ); //release MAX3421E from reset //} //byte MAX3421E::getVbusState( void ) //{ // return( vbusState ); //} //void MAX3421E::toggle( byte pin ) //{ // digitalWrite( pin, HIGH ); // digitalWrite( pin, LOW ); //} / Single host register write / void MAX3421E::regWr( byte reg, byte val) { digitalWrite(MAX_SS,LOW); SPDR = ( reg \| 0x02 ); while(!( SPSR & ( 1 << SPIF ))); SPDR = val; while(!( SPSR & ( 1 << SPIF ))); digitalWrite(MAX_SS,HIGH); return; } / multiple-byte write / / returns a pointer to a memory position after last written / char MAX3421E::bytesWr( byte reg, byte nbytes, char * data ) { digitalWrite(MAX_SS,LOW); SPDR = ( reg \| 0x02 ); while( nbytes-- ) { while(!( SPSR & ( 1 << SPIF ))); //check if previous byte was sent SPDR = ( data ); // send next data byte data++; // advance data pointer } while(!( SPSR & ( 1 << SPIF ))); digitalWrite(MAX_SS,HIGH); return( data ); } / GPIO write. GPIO byte is split between 2 registers, so two writes are needed to write one byte / / GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 / / upper 4 bits of IOPINS1, IOPINS2 are read-only, so no masking is necessary / void MAX3421E::gpioWr( byte val ) { regWr( rIOPINS1, val ); val = val >>4; regWr( rIOPINS2, val ); return; } / Single host register read / byte MAX3421E::regRd( byte reg ) { byte tmp; digitalWrite(MAX_SS,LOW); SPDR = reg; while(!( SPSR & ( 1 << SPIF ))); SPDR = 0; //send empty byte while(!( SPSR & ( 1 << SPIF ))); digitalWrite(MAX_SS,HIGH); return( SPDR ); } / multiple-bytes register read / / returns a pointer to a memory position after last read / char MAX3421E::bytesRd ( byte reg, byte nbytes, char * data ) { digitalWrite(MAX_SS,LOW); SPDR = reg; while(!( SPSR & ( 1 << SPIF ))); //wait while( nbytes ) { SPDR = 0; //send empty byte nbytes--; while(!( SPSR & ( 1 << SPIF ))); data = SPDR; data++; } digitalWrite(MAX_SS,HIGH); return( data ); } / GPIO read. See gpioWr for explanation / / GPIN pins are in high nibbles of IOPINS1, IOPINS2 / byte MAX3421E::gpioRd( void ) { byte tmpbyte = 0; tmpbyte = regRd( rIOPINS2 ); //pins 4-7 tmpbyte &= 0xf0; //clean lower nibble tmpbyte \|= ( regRd( rIOPINS1 ) >>4 ) ; //shift low bits and OR with upper from previous operation. Upper nibble zeroes during shift, at least with this compiler return( tmpbyte ); } / reset MAX3421E using chip reset bit. SPI configuration is not affected / boolean MAX3421E::reset() { byte tmp = 0; regWr( rUSBCTL, bmCHIPRES ); //Chip reset. This stops the oscillator regWr( rUSBCTL, 0x00 ); //Remove the reset while(!(regRd( rUSBIRQ ) & bmOSCOKIRQ )) { //wait until the PLL is stable tmp++; //timeout after 256 attempts if( tmp == 0 ) { return( false ); } } return( true ); } / turn USB power on/off / / does nothing, returns TRUE. Left for compatibility with old sketches / / will be deleted eventually / /// ON pin of VBUS switch (MAX4793 or similar) is connected to GPOUT7 / /// OVERLOAD pin of Vbus switch is connected to GPIN7 / /// OVERLOAD state low. NO OVERLOAD or VBUS OFF state high. / boolean MAX3421E::vbusPwr ( boolean action ) { // byte tmp; // tmp = regRd( rIOPINS2 ); //copy of IOPINS2 // if( action ) { //turn on by setting GPOUT7 // tmp \|= bmGPOUT7; // } // else { //turn off by clearing GPOUT7 // tmp &= ~bmGPOUT7; // } // regWr( rIOPINS2, tmp ); //send GPOUT7 // if( action ) { // delay( 60 ); // } // if (( regRd( rIOPINS2 ) & bmGPIN7 ) == 0 ) { // check if overload is present. MAX4793 /FLAG ( pin 4 ) goes low if overload // return( false ); // } return( true ); // power on/off successful } / probe bus to determine device presense and speed and switch host to this speed / void MAX3421E::busprobe( void ) { byte bus_sample; bus_sample = regRd( rHRSL ); //Get J,K status bus_sample &= ( bmJSTATUS\|bmKSTATUS ); //zero the rest of the byte switch( bus_sample ) { //start full-speed or low-speed host case( bmJSTATUS ): if(( regRd( rMODE ) & bmLOWSPEED ) == 0 ) { regWr( rMODE, MODE_FS_HOST ); //start full-speed host vbusState = FSHOST; } else { regWr( rMODE, MODE_LS_HOST); //start low-speed host vbusState = LSHOST; } break; case( bmKSTATUS ): if(( regRd( rMODE ) & bmLOWSPEED ) == 0 ) { regWr( rMODE, MODE_LS_HOST ); //start low-speed host vbusState = LSHOST; } else { regWr( rMODE, MODE_FS_HOST ); //start full-speed host vbusState = FSHOST; } break; case( bmSE1 ): //illegal state vbusState = SE1; break; case( bmSE0 ): //disconnected state regWr( rMODE, bmDPPULLDN\|bmDMPULLDN\|bmHOST\|bmSEPIRQ); vbusState = SE0; break; }//end switch( bus_sample ) } / MAX3421E initialization after power-on / void MAX3421E::powerOn() { / Configure full-duplex SPI, interrupt pulse / regWr( rPINCTL,( bmFDUPSPI + bmINTLEVEL + bmGPXB )); //Full-duplex SPI, level interrupt, GPX if( reset() == false ) { //stop/start the oscillator Serial.println("Error: OSCOKIRQ failed to assert"); } / configure host operation / regWr( rMODE, bmDPPULLDN\|bmDMPULLDN\|bmHOST\|bmSEPIRQ ); // set pull-downs, Host, Separate GPIN IRQ on GPX regWr( rHIEN, bmCONDETIE\|bmFRAMEIE ); //connection detection / check if device is connected / regWr( rHCTL,bmSAMPLEBUS ); // sample USB bus while(!(regRd( rHCTL ) & bmSAMPLEBUS )); //wait for sample operation to finish busprobe(); //check if anything is connected regWr( rHIRQ, bmCONDETIRQ ); //clear connection detect interrupt regWr( rCPUCTL, 0x01 ); //enable interrupt pin } / MAX3421 state change task and interrupt handler / byte MAX3421E::Task( void ) { byte rcode = 0; byte pinvalue; //Serial.print("Vbus state: "); //Serial.println( vbusState, HEX ); pinvalue = readINT(); if( pinvalue == LOW ) { rcode = IntHandler(); } pinvalue = readGPX(); if( pinvalue == LOW ) { GpxHandler(); } // usbSM(); //USB state machine return( rcode ); } byte MAX3421E::IntHandler() { byte HIRQ; byte HIRQ_sendback = 0x00; HIRQ = regRd( rHIRQ ); //determine interrupt source //if( HIRQ & bmFRAMEIRQ ) { //->1ms SOF interrupt handler // HIRQ_sendback \|= bmFRAMEIRQ; //}//end FRAMEIRQ handling if( HIRQ & bmCONDETIRQ ) { busprobe(); HIRQ_sendback \|= bmCONDETIRQ; } / End HIRQ interrupts handling, clear serviced IRQs */ regWr( rHIRQ, HIRQ_sendback ); return( HIRQ_sendback ); } byte MAX3421E::GpxHandler() { byte GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register // if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload // vbusPwr( OFF ); //attempt powercycle // delay( 1000 ); // vbusPwr( ON ); // regWr( rGPINIRQ, bmGPINIRQ7 ); // } return( GPINIRQ ); } //void MAX3421E::usbSM( void ) //USB state machine //{ // // //}	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/Max3421e.cpp	C++	oos	11,857
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. / / USB functions / #ifndef _usb_h_ #define _usb_h_ #include <Max3421e.h> #include "ch9.h" / Common setup data constant combinations / #define bmREQ_GET_DESCR USB_SETUP_DEVICE_TO_HOST\|USB_SETUP_TYPE_STANDARD\|USB_SETUP_RECIPIENT_DEVICE //get descriptor request type #define bmREQ_SET USB_SETUP_HOST_TO_DEVICE\|USB_SETUP_TYPE_STANDARD\|USB_SETUP_RECIPIENT_DEVICE //set request type for all but 'set feature' and 'set interface' #define bmREQ_CL_GET_INTF USB_SETUP_DEVICE_TO_HOST\|USB_SETUP_TYPE_CLASS\|USB_SETUP_RECIPIENT_INTERFACE //get interface request type / HID requests / #define bmREQ_HIDOUT USB_SETUP_HOST_TO_DEVICE\|USB_SETUP_TYPE_CLASS\|USB_SETUP_RECIPIENT_INTERFACE #define bmREQ_HIDIN USB_SETUP_DEVICE_TO_HOST\|USB_SETUP_TYPE_CLASS\|USB_SETUP_RECIPIENT_INTERFACE #define bmREQ_HIDREPORT USB_SETUP_DEVICE_TO_HOST\|USB_SETUP_TYPE_STANDARD\|USB_SETUP_RECIPIENT_INTERFACE #define USB_XFER_TIMEOUT 5000 //USB transfer timeout in milliseconds, per section 9.2.6.1 of USB 2.0 spec #define USB_NAK_LIMIT 32000 //NAK limit for a transfer. o meand NAKs are not counted #define USB_RETRY_LIMIT 3 //retry limit for a transfer #define USB_SETTLE_DELAY 200 //settle delay in milliseconds #define USB_NAK_NOWAIT 1 //used in Richard's PS2/Wiimote code #define USB_NUMDEVICES 2 //number of USB devices / USB state machine states / #define USB_STATE_MASK 0xf0 #define USB_STATE_DETACHED 0x10 #define USB_DETACHED_SUBSTATE_INITIALIZE 0x11 #define USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE 0x12 #define USB_DETACHED_SUBSTATE_ILLEGAL 0x13 #define USB_ATTACHED_SUBSTATE_SETTLE 0x20 #define USB_ATTACHED_SUBSTATE_RESET_DEVICE 0x30 #define USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE 0x40 #define USB_ATTACHED_SUBSTATE_WAIT_SOF 0x50 #define USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE 0x60 #define USB_STATE_ADDRESSING 0x70 #define USB_STATE_CONFIGURING 0x80 #define USB_STATE_RUNNING 0x90 #define USB_STATE_ERROR 0xa0 // byte usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE / USB Setup Packet Structure / typedef struct { union { // offset description byte bmRequestType; // 0 Bit-map of request type struct { byte recipient: 5; // Recipient of the request byte type: 2; // Type of request byte direction: 1; // Direction of data X-fer }; }ReqType_u; byte bRequest; // 1 Request union { unsigned int wValue; // 2 Depends on bRequest struct { byte wValueLo; byte wValueHi; }; }wVal_u; unsigned int wIndex; // 4 Depends on bRequest unsigned int wLength; // 6 Depends on bRequest } SETUP_PKT, PSETUP_PKT; /* Endpoint information structure / / bToggle of endpoint 0 initialized to 0xff / / during enumeration bToggle is set to 00 / typedef struct { byte epAddr; //copy from endpoint descriptor. Bit 7 indicates direction ( ignored for control endpoints ) byte Attr; // Endpoint transfer type. unsigned int MaxPktSize; // Maximum packet size. byte Interval; // Polling interval in frames. byte sndToggle; //last toggle value, bitmask for HCTL toggle bits byte rcvToggle; //last toggle value, bitmask for HCTL toggle bits / not sure if both are necessary / } EP_RECORD; / device record structure / typedef struct { EP_RECORD epinfo; //device endpoint information byte devclass; //device class } DEV_RECORD; class USB : public MAX3421E { //data structures /* device table. Filled during enumeration / / index corresponds to device address / / each entry contains pointer to endpoint structure / / and device class to use in various places / //DEV_RECORD devtable[ USB_NUMDEVICES + 1 ]; //EP_RECORD dev0ep; //Endpoint data structure used during enumeration for uninitialized device //byte usb_task_state; public: USB( void ); byte getUsbTaskState( void ); void setUsbTaskState( byte state ); EP_RECORD getDevTableEntry( byte addr, byte ep ); void setDevTableEntry( byte addr, EP_RECORD* eprecord_ptr ); byte ctrlReq( byte addr, byte ep, byte bmReqType, byte bRequest, byte wValLo, byte wValHi, unsigned int wInd, unsigned int nbytes, char* dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); /* Control requests / byte getDevDescr( byte addr, byte ep, unsigned int nbytes, char dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte getConfDescr( byte addr, byte ep, unsigned int nbytes, byte conf, char* dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte getStrDescr( byte addr, byte ep, unsigned int nbytes, byte index, unsigned int langid, char* dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte setAddr( byte oldaddr, byte ep, byte newaddr, unsigned int nak_limit = USB_NAK_LIMIT ); byte setConf( byte addr, byte ep, byte conf_value, unsigned int nak_limit = USB_NAK_LIMIT ); /*/ byte setProto( byte addr, byte ep, byte interface, byte protocol, unsigned int nak_limit = USB_NAK_LIMIT ); byte getProto( byte addr, byte ep, byte interface, char dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte getReportDescr( byte addr, byte ep, unsigned int nbytes, char* dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte setReport( byte addr, byte ep, unsigned int nbytes, byte interface, byte report_type, byte report_id, char* dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte getReport( byte addr, byte ep, unsigned int nbytes, byte interface, byte report_type, byte report_id, char* dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte getIdle( byte addr, byte ep, byte interface, byte reportID, char* dataptr, unsigned int nak_limit = USB_NAK_LIMIT ); byte setIdle( byte addr, byte ep, byte interface, byte reportID, byte duration, unsigned int nak_limit = USB_NAK_LIMIT ); /*/ byte ctrlData( byte addr, byte ep, unsigned int nbytes, char dataptr, boolean direction, unsigned int nak_limit = USB_NAK_LIMIT ); byte ctrlStatus( byte ep, boolean direction, unsigned int nak_limit = USB_NAK_LIMIT ); byte inTransfer( byte addr, byte ep, unsigned int nbytes, char* data, unsigned int nak_limit = USB_NAK_LIMIT ); int newInTransfer( byte addr, byte ep, unsigned int nbytes, char* data, unsigned int nak_limit = USB_NAK_LIMIT); byte outTransfer( byte addr, byte ep, unsigned int nbytes, char* data, unsigned int nak_limit = USB_NAK_LIMIT ); byte dispatchPkt( byte token, byte ep, unsigned int nak_limit = USB_NAK_LIMIT ); void Task( void ); private: void init(); }; //get device descriptor inline byte USB::getDevDescr( byte addr, byte ep, unsigned int nbytes, char* dataptr, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, 0x00, USB_DESCRIPTOR_DEVICE, 0x0000, nbytes, dataptr, nak_limit )); } //get configuration descriptor inline byte USB::getConfDescr( byte addr, byte ep, unsigned int nbytes, byte conf, char* dataptr, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, conf, USB_DESCRIPTOR_CONFIGURATION, 0x0000, nbytes, dataptr, nak_limit )); } //get string descriptor inline byte USB::getStrDescr( byte addr, byte ep, unsigned int nbytes, byte index, unsigned int langid, char* dataptr, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, index, USB_DESCRIPTOR_STRING, langid, nbytes, dataptr, nak_limit )); } //set address inline byte USB::setAddr( byte oldaddr, byte ep, byte newaddr, unsigned int nak_limit ) { return( ctrlReq( oldaddr, ep, bmREQ_SET, USB_REQUEST_SET_ADDRESS, newaddr, 0x00, 0x0000, 0x0000, NULL, nak_limit )); } //set configuration inline byte USB::setConf( byte addr, byte ep, byte conf_value, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_SET, USB_REQUEST_SET_CONFIGURATION, conf_value, 0x00, 0x0000, 0x0000, NULL, nak_limit )); } //class requests inline byte USB::setProto( byte addr, byte ep, byte interface, byte protocol, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_HIDOUT, HID_REQUEST_SET_PROTOCOL, protocol, 0x00, interface, 0x0000, NULL, nak_limit )); } inline byte USB::getProto( byte addr, byte ep, byte interface, char* dataptr, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_PROTOCOL, 0x00, 0x00, interface, 0x0001, dataptr, nak_limit )); } //get HID report descriptor inline byte USB::getReportDescr( byte addr, byte ep, unsigned int nbytes, char* dataptr, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_HIDREPORT, USB_REQUEST_GET_DESCRIPTOR, 0x00, HID_DESCRIPTOR_REPORT, 0x0000, nbytes, dataptr, nak_limit )); } inline byte USB::setReport( byte addr, byte ep, unsigned int nbytes, byte interface, byte report_type, byte report_id, char* dataptr, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_HIDOUT, HID_REQUEST_SET_REPORT, report_id, report_type, interface, nbytes, dataptr, nak_limit )); } inline byte USB::getReport( byte addr, byte ep, unsigned int nbytes, byte interface, byte report_type, byte report_id, char* dataptr, unsigned int nak_limit ) { // ** RI 04/11/09 return( ctrlReq( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_REPORT, report_id, report_type, interface, nbytes, dataptr, nak_limit )); } /* returns one byte of data in dataptr / inline byte USB::getIdle( byte addr, byte ep, byte interface, byte reportID, char dataptr, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_IDLE, reportID, 0, interface, 0x0001, dataptr, nak_limit )); } inline byte USB::setIdle( byte addr, byte ep, byte interface, byte reportID, byte duration, unsigned int nak_limit ) { return( ctrlReq( addr, ep, bmREQ_HIDOUT, HID_REQUEST_SET_IDLE, reportID, duration, interface, 0x0000, NULL, nak_limit )); } #endif //_usb_h_	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/Usb.h	C++	oos	12,552
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. / / USB chapter 9 structures / #ifndef _ch9_h_ #define _ch9_h_ / Misc.USB constants / #define DEV_DESCR_LEN 18 //device descriptor length #define CONF_DESCR_LEN 9 //configuration descriptor length #define INTR_DESCR_LEN 9 //interface descriptor length #define EP_DESCR_LEN 7 //endpoint descriptor length / Standard Device Requests / #define USB_REQUEST_GET_STATUS 0 // Standard Device Request - GET STATUS #define USB_REQUEST_CLEAR_FEATURE 1 // Standard Device Request - CLEAR FEATURE #define USB_REQUEST_SET_FEATURE 3 // Standard Device Request - SET FEATURE #define USB_REQUEST_SET_ADDRESS 5 // Standard Device Request - SET ADDRESS #define USB_REQUEST_GET_DESCRIPTOR 6 // Standard Device Request - GET DESCRIPTOR #define USB_REQUEST_SET_DESCRIPTOR 7 // Standard Device Request - SET DESCRIPTOR #define USB_REQUEST_GET_CONFIGURATION 8 // Standard Device Request - GET CONFIGURATION #define USB_REQUEST_SET_CONFIGURATION 9 // Standard Device Request - SET CONFIGURATION #define USB_REQUEST_GET_INTERFACE 10 // Standard Device Request - GET INTERFACE #define USB_REQUEST_SET_INTERFACE 11 // Standard Device Request - SET INTERFACE #define USB_REQUEST_SYNCH_FRAME 12 // Standard Device Request - SYNCH FRAME #define USB_FEATURE_ENDPOINT_HALT 0 // CLEAR/SET FEATURE - Endpoint Halt #define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1 // CLEAR/SET FEATURE - Device remote wake-up #define USB_FEATURE_TEST_MODE 2 // CLEAR/SET FEATURE - Test mode / Setup Data Constants / #define USB_SETUP_HOST_TO_DEVICE 0x00 // Device Request bmRequestType transfer direction - host to device transfer #define USB_SETUP_DEVICE_TO_HOST 0x80 // Device Request bmRequestType transfer direction - device to host transfer #define USB_SETUP_TYPE_STANDARD 0x00 // Device Request bmRequestType type - standard #define USB_SETUP_TYPE_CLASS 0x20 // Device Request bmRequestType type - class #define USB_SETUP_TYPE_VENDOR 0x40 // Device Request bmRequestType type - vendor #define USB_SETUP_RECIPIENT_DEVICE 0x00 // Device Request bmRequestType recipient - device #define USB_SETUP_RECIPIENT_INTERFACE 0x01 // Device Request bmRequestType recipient - interface #define USB_SETUP_RECIPIENT_ENDPOINT 0x02 // Device Request bmRequestType recipient - endpoint #define USB_SETUP_RECIPIENT_OTHER 0x03 // Device Request bmRequestType recipient - other / USB descriptors / #define USB_DESCRIPTOR_DEVICE 0x01 // bDescriptorType for a Device Descriptor. #define USB_DESCRIPTOR_CONFIGURATION 0x02 // bDescriptorType for a Configuration Descriptor. #define USB_DESCRIPTOR_STRING 0x03 // bDescriptorType for a String Descriptor. #define USB_DESCRIPTOR_INTERFACE 0x04 // bDescriptorType for an Interface Descriptor. #define USB_DESCRIPTOR_ENDPOINT 0x05 // bDescriptorType for an Endpoint Descriptor. #define USB_DESCRIPTOR_DEVICE_QUALIFIER 0x06 // bDescriptorType for a Device Qualifier. #define USB_DESCRIPTOR_OTHER_SPEED 0x07 // bDescriptorType for a Other Speed Configuration. #define USB_DESCRIPTOR_INTERFACE_POWER 0x08 // bDescriptorType for Interface Power. #define USB_DESCRIPTOR_OTG 0x09 // bDescriptorType for an OTG Descriptor. / OTG SET FEATURE Constants / #define OTG_FEATURE_B_HNP_ENABLE 3 // SET FEATURE OTG - Enable B device to perform HNP #define OTG_FEATURE_A_HNP_SUPPORT 4 // SET FEATURE OTG - A device supports HNP #define OTG_FEATURE_A_ALT_HNP_SUPPORT 5 // SET FEATURE OTG - Another port on the A device supports HNP / USB Endpoint Transfer Types / #define USB_TRANSFER_TYPE_CONTROL 0x00 // Endpoint is a control endpoint. #define USB_TRANSFER_TYPE_ISOCHRONOUS 0x01 // Endpoint is an isochronous endpoint. #define USB_TRANSFER_TYPE_BULK 0x02 // Endpoint is a bulk endpoint. #define USB_TRANSFER_TYPE_INTERRUPT 0x03 // Endpoint is an interrupt endpoint. #define bmUSB_TRANSFER_TYPE 0x03 // bit mask to separate transfer type from ISO attributes / Standard Feature Selectors for CLEAR_FEATURE Requests / #define USB_FEATURE_ENDPOINT_STALL 0 // Endpoint recipient #define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1 // Device recipient #define USB_FEATURE_TEST_MODE 2 // Device recipient / HID constants. Not part of chapter 9 / / Class-Specific Requests / #define HID_REQUEST_GET_REPORT 0x01 #define HID_REQUEST_GET_IDLE 0x02 #define HID_REQUEST_GET_PROTOCOL 0x03 #define HID_REQUEST_SET_REPORT 0x09 #define HID_REQUEST_SET_IDLE 0x0A #define HID_REQUEST_SET_PROTOCOL 0x0B / Class Descriptor Types / #define HID_DESCRIPTOR_HID 0x21 #define HID_DESCRIPTOR_REPORT 0x22 #define HID_DESRIPTOR_PHY 0x23 / Protocol Selection / #define BOOT_PROTOCOL 0x00 #define RPT_PROTOCOL 0x01 / HID Interface Class Code / #define HID_INTF 0x03 / HID Interface Class SubClass Codes / #define BOOT_INTF_SUBCLASS 0x01 / HID Interface Class Protocol Codes / #define HID_PROTOCOL_NONE 0x00 #define HID_PROTOCOL_KEYBOARD 0x01 #define HID_PROTOCOL_MOUSE 0x02 / descriptor data structures / / Device descriptor structure / typedef struct { byte bLength; // Length of this descriptor. byte bDescriptorType; // DEVICE descriptor type (USB_DESCRIPTOR_DEVICE). unsigned int bcdUSB; // USB Spec Release Number (BCD). byte bDeviceClass; // Class code (assigned by the USB-IF). 0xFF-Vendor specific. byte bDeviceSubClass; // Subclass code (assigned by the USB-IF). byte bDeviceProtocol; // Protocol code (assigned by the USB-IF). 0xFF-Vendor specific. byte bMaxPacketSize0; // Maximum packet size for endpoint 0. unsigned int idVendor; // Vendor ID (assigned by the USB-IF). unsigned int idProduct; // Product ID (assigned by the manufacturer). unsigned int bcdDevice; // Device release number (BCD). byte iManufacturer; // Index of String Descriptor describing the manufacturer. byte iProduct; // Index of String Descriptor describing the product. byte iSerialNumber; // Index of String Descriptor with the device's serial number. byte bNumConfigurations; // Number of possible configurations. } USB_DEVICE_DESCRIPTOR; / Configuration descriptor structure / typedef struct { byte bLength; // Length of this descriptor. byte bDescriptorType; // CONFIGURATION descriptor type (USB_DESCRIPTOR_CONFIGURATION). unsigned int wTotalLength; // Total length of all descriptors for this configuration. byte bNumInterfaces; // Number of interfaces in this configuration. byte bConfigurationValue; // Value of this configuration (1 based). byte iConfiguration; // Index of String Descriptor describing the configuration. byte bmAttributes; // Configuration characteristics. byte bMaxPower; // Maximum power consumed by this configuration. } USB_CONFIGURATION_DESCRIPTOR; / Interface descriptor structure / typedef struct { byte bLength; // Length of this descriptor. byte bDescriptorType; // INTERFACE descriptor type (USB_DESCRIPTOR_INTERFACE). byte bInterfaceNumber; // Number of this interface (0 based). byte bAlternateSetting; // Value of this alternate interface setting. byte bNumEndpoints; // Number of endpoints in this interface. byte bInterfaceClass; // Class code (assigned by the USB-IF). 0xFF-Vendor specific. byte bInterfaceSubClass; // Subclass code (assigned by the USB-IF). byte bInterfaceProtocol; // Protocol code (assigned by the USB-IF). 0xFF-Vendor specific. byte iInterface; // Index of String Descriptor describing the interface. } USB_INTERFACE_DESCRIPTOR; / Endpoint descriptor structure / typedef struct { byte bLength; // Length of this descriptor. byte bDescriptorType; // ENDPOINT descriptor type (USB_DESCRIPTOR_ENDPOINT). byte bEndpointAddress; // Endpoint address. Bit 7 indicates direction (0=OUT, 1=IN). byte bmAttributes; // Endpoint transfer type. unsigned int wMaxPacketSize; // Maximum packet size. byte bInterval; // Polling interval in frames. } USB_ENDPOINT_DESCRIPTOR; / HID descriptor */ typedef struct { byte bLength; byte bDescriptorType; unsigned int bcdHID; byte bCountryCode; byte bNumDescriptors; byte bDescrType; unsigned int wDescriptorLength; } USB_HID_DESCRIPTOR; #endif // _ch9_h_	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/ch9.h	C	oos	11,103
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ //HD44780 compatible LCD display via MAX3421E GPOUT support header //pinout: D[4-7] -> GPOUT[4-7], RS-> GPOUT[2], E ->GPOUT[3] // //this code is heavily borrowed from official Arduino source v.0017 // link to original http://code.google.com/p/arduino/source/browse/trunk/hardware/libraries/LiquidCrystal/LiquidCrystal.h // #ifndef _Max_LCD_h_ #define _Max_LCD_h_ #include <inttypes.h> #include "Print.h" // commands #define LCD_CLEARDISPLAY 0x01 #define LCD_RETURNHOME 0x02 #define LCD_ENTRYMODESET 0x04 #define LCD_DISPLAYCONTROL 0x08 #define LCD_CURSORSHIFT 0x10 #define LCD_FUNCTIONSET 0x20 #define LCD_SETCGRAMADDR 0x40 #define LCD_SETDDRAMADDR 0x80 // flags for display entry mode #define LCD_ENTRYRIGHT 0x00 #define LCD_ENTRYLEFT 0x02 #define LCD_ENTRYSHIFTINCREMENT 0x01 #define LCD_ENTRYSHIFTDECREMENT 0x00 // flags for display on/off control #define LCD_DISPLAYON 0x04 #define LCD_DISPLAYOFF 0x00 #define LCD_CURSORON 0x02 #define LCD_CURSOROFF 0x00 #define LCD_BLINKON 0x01 #define LCD_BLINKOFF 0x00 // flags for display/cursor shift #define LCD_DISPLAYMOVE 0x08 #define LCD_CURSORMOVE 0x00 #define LCD_MOVERIGHT 0x04 #define LCD_MOVELEFT 0x00 // flags for function set #define LCD_8BITMODE 0x10 #define LCD_4BITMODE 0x00 #define LCD_2LINE 0x08 #define LCD_1LINE 0x00 #define LCD_5x10DOTS 0x04 #define LCD_5x8DOTS 0x00 class Max_LCD : public Print { public: Max_LCD(); void init(); void begin(uint8_t cols, uint8_t rows, uint8_t charsize = LCD_5x8DOTS); void clear(); void home(); void noDisplay(); void display(); void noBlink(); void blink(); void noCursor(); void cursor(); void scrollDisplayLeft(); void scrollDisplayRight(); void leftToRight(); void rightToLeft(); void autoscroll(); void noAutoscroll(); void createChar(uint8_t, uint8_t[]); void setCursor(uint8_t, uint8_t); virtual void write(uint8_t); void command(uint8_t); private: void sendbyte( uint8_t val ); uint8_t _displayfunction; //tokill uint8_t _displaycontrol; uint8_t _displaymode; uint8_t _initialized; uint8_t _numlines,_currline; }; #endif	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/Max_LCD.h	C++	oos	3,796
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. / / USB functions / #include "Usb.h" static byte usb_error = 0; static byte usb_task_state; DEV_RECORD devtable[ USB_NUMDEVICES + 1 ]; EP_RECORD dev0ep; //Endpoint data structure used during enumeration for uninitialized device / constructor / USB::USB () { usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE; //set up state machine init(); } / Initialize data structures / void USB::init() { byte i; for( i = 0; i < ( USB_NUMDEVICES + 1 ); i++ ) { devtable[ i ].epinfo = NULL; //clear device table devtable[ i ].devclass = 0; } devtable[ 0 ].epinfo = &dev0ep; //set single ep for uninitialized device // not necessary dev0ep.MaxPktSize = 8; //minimum possible dev0ep.sndToggle = bmSNDTOG0; //set DATA0/1 toggles to 0 dev0ep.rcvToggle = bmRCVTOG0; } byte USB::getUsbTaskState( void ) { return( usb_task_state ); } void USB::setUsbTaskState( byte state ) { usb_task_state = state; } EP_RECORD USB::getDevTableEntry( byte addr, byte ep ) { EP_RECORD* ptr; ptr = devtable[ addr ].epinfo; ptr += ep; return( ptr ); } /* set device table entry / / each device is different and has different number of endpoints. This function plugs endpoint record structure, defined in application, to devtable / void USB::setDevTableEntry( byte addr, EP_RECORD eprecord_ptr ) { devtable[ addr ].epinfo = eprecord_ptr; //return(); } /* Control transfer. Sets address, endpoint, fills control packet with necessary data, dispatches control packet, and initiates bulk IN transfer, / / depending on request. Actual requests are defined as inlines / / return codes: / / 00 = success / / 01-0f = non-zero HRSLT / byte USB::ctrlReq( byte addr, byte ep, byte bmReqType, byte bRequest, byte wValLo, byte wValHi, unsigned int wInd, unsigned int nbytes, char dataptr, unsigned int nak_limit ) { boolean direction = false; //request direction, IN or OUT byte rcode; SETUP_PKT setup_pkt; regWr( rPERADDR, addr ); //set peripheral address if( bmReqType & 0x80 ) { direction = true; //determine request direction } /* fill in setup packet / setup_pkt.ReqType_u.bmRequestType = bmReqType; setup_pkt.bRequest = bRequest; setup_pkt.wVal_u.wValueLo = wValLo; setup_pkt.wVal_u.wValueHi = wValHi; setup_pkt.wIndex = wInd; setup_pkt.wLength = nbytes; bytesWr( rSUDFIFO, 8, ( char )&setup_pkt ); //transfer to setup packet FIFO rcode = dispatchPkt( tokSETUP, ep, nak_limit ); //dispatch packet //Serial.println("Setup packet"); //DEBUG if( rcode ) { //return HRSLT if not zero Serial.print("Setup packet error: "); Serial.print( rcode, HEX ); return( rcode ); } //Serial.println( direction, HEX ); if( dataptr != NULL ) { //data stage, if present rcode = ctrlData( addr, ep, nbytes, dataptr, direction ); } if( rcode ) { //return error Serial.print("Data packet error: "); Serial.print( rcode, HEX ); return( rcode ); } rcode = ctrlStatus( ep, direction ); //status stage return( rcode ); } /* Control transfer with status stage and no data stage / / Assumed peripheral address is already set / byte USB::ctrlStatus( byte ep, boolean direction, unsigned int nak_limit ) { byte rcode; if( direction ) { //GET rcode = dispatchPkt( tokOUTHS, ep, nak_limit ); } else { rcode = dispatchPkt( tokINHS, ep, nak_limit ); } return( rcode ); } / Control transfer with data stage. Stages 2 and 3 of control transfer. Assumes preipheral address is set and setup packet has been sent / byte USB::ctrlData( byte addr, byte ep, unsigned int nbytes, char dataptr, boolean direction, unsigned int nak_limit ) { byte rcode; if( direction ) { //IN transfer devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1; rcode = inTransfer( addr, ep, nbytes, dataptr, nak_limit ); return( rcode ); } else { //OUT transfer devtable[ addr ].epinfo[ ep ].sndToggle = bmSNDTOG1; rcode = outTransfer( addr, ep, nbytes, dataptr, nak_limit ); return( rcode ); } } /* IN transfer to arbitrary endpoint. Assumes PERADDR is set. Handles multiple packets if necessary. Transfers 'nbytes' bytes. / / Keep sending INs and writes data to memory area pointed by 'data' / / rcode 0 if no errors. rcode 01-0f is relayed from dispatchPkt(). Rcode f0 means RCVDAVIRQ error, fe USB xfer timeout / byte USB::inTransfer( byte addr, byte ep, unsigned int nbytes, char data, unsigned int nak_limit ) { byte rcode; byte pktsize; byte maxpktsize = devtable[ addr ].epinfo[ ep ].MaxPktSize; unsigned int xfrlen = 0; regWr( rHCTL, devtable[ addr ].epinfo[ ep ].rcvToggle ); //set toggle value while( 1 ) { // use a 'return' to exit this loop rcode = dispatchPkt( tokIN, ep, nak_limit ); //IN packet to EP-'endpoint'. Function takes care of NAKS. if( rcode ) { return( rcode ); //should be 0, indicating ACK. Else return error code. } /* check for RCVDAVIRQ and generate error if not present / / the only case when absense of RCVDAVIRQ makes sense is when toggle error occured. Need to add handling for that / if(( regRd( rHIRQ ) & bmRCVDAVIRQ ) == 0 ) { return ( 0xf0 ); //receive error } pktsize = regRd( rRCVBC ); //number of received bytes data = bytesRd( rRCVFIFO, pktsize, data ); regWr( rHIRQ, bmRCVDAVIRQ ); // Clear the IRQ & free the buffer xfrlen += pktsize; // add this packet's byte count to total transfer length / The transfer is complete under two conditions: / / 1. The device sent a short packet (L.T. maxPacketSize) / / 2. 'nbytes' have been transferred. / if (( pktsize < maxpktsize ) \|\| (xfrlen >= nbytes )) { // have we transferred 'nbytes' bytes? if( regRd( rHRSL ) & bmRCVTOGRD ) { //save toggle value devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1; } else { devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG0; } return( 0 ); } }//while( 1 ) } int USB::newInTransfer( byte addr, byte ep, unsigned int nbytes, char data, unsigned int nak_limit ) { byte rcode; byte pktsize; byte maxpktsize = devtable[ addr ].epinfo[ ep ].MaxPktSize; unsigned int xfrlen = 0; regWr( rHCTL, devtable[ addr ].epinfo[ ep ].rcvToggle ); //set toggle value while( 1 ) { // use a 'return' to exit this loop rcode = dispatchPkt( tokIN, ep, nak_limit ); //IN packet to EP-'endpoint'. Function takes care of NAKS. if( rcode ) { return -1; //should be 0, indicating ACK. Else return error code. } /* check for RCVDAVIRQ and generate error if not present / / the only case when absense of RCVDAVIRQ makes sense is when toggle error occured. Need to add handling for that / if(( regRd( rHIRQ ) & bmRCVDAVIRQ ) == 0 ) { return -1; //receive error } pktsize = regRd( rRCVBC ); //number of received bytes data = bytesRd( rRCVFIFO, pktsize, data ); regWr( rHIRQ, bmRCVDAVIRQ ); // Clear the IRQ & free the buffer xfrlen += pktsize; // add this packet's byte count to total transfer length / The transfer is complete under two conditions: / / 1. The device sent a short packet (L.T. maxPacketSize) / / 2. 'nbytes' have been transferred. / if (( pktsize < maxpktsize ) \|\| (xfrlen >= nbytes )) { // have we transferred 'nbytes' bytes? if( regRd( rHRSL ) & bmRCVTOGRD ) { //save toggle value devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1; } else { devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG0; } return xfrlen; } }//while( 1 ) } / OUT transfer to arbitrary endpoint. Assumes PERADDR is set. Handles multiple packets if necessary. Transfers 'nbytes' bytes. / / Handles NAK bug per Maxim Application Note 4000 for single buffer transfer / / rcode 0 if no errors. rcode 01-0f is relayed from HRSL / / major part of this function borrowed from code shared by Richard Ibbotson / byte USB::outTransfer( byte addr, byte ep, unsigned int nbytes, char data, unsigned int nak_limit ) { byte rcode, retry_count; char* data_p = data; //local copy of the data pointer unsigned int bytes_tosend, nak_count; unsigned int bytes_left = nbytes; byte maxpktsize = devtable[ addr ].epinfo[ ep ].MaxPktSize; unsigned long timeout = millis() + USB_XFER_TIMEOUT; if (!maxpktsize) { //todo: move this check close to epinfo init. Make it 1< pktsize <64 return 0xFE; } regWr( rHCTL, devtable[ addr ].epinfo[ ep ].sndToggle ); //set toggle value while( bytes_left ) { retry_count = 0; nak_count = 0; bytes_tosend = ( bytes_left >= maxpktsize ) ? maxpktsize : bytes_left; bytesWr( rSNDFIFO, bytes_tosend, data_p ); //filling output FIFO regWr( rSNDBC, bytes_tosend ); //set number of bytes regWr( rHXFR, ( tokOUT \| ep )); //dispatch packet while(!(regRd( rHIRQ ) & bmHXFRDNIRQ )); //wait for the completion IRQ regWr( rHIRQ, bmHXFRDNIRQ ); //clear IRQ rcode = ( regRd( rHRSL ) & 0x0f ); while( rcode && ( timeout > millis())) { switch( rcode ) { case hrNAK: nak_count++; if( nak_limit && ( nak_count == USB_NAK_LIMIT )) { return( rcode); //return NAK } break; case hrTIMEOUT: retry_count++; if( retry_count == USB_RETRY_LIMIT ) { return( rcode ); //return TIMEOUT } break; default: return( rcode ); }//switch( rcode... /* process NAK according to Host out NAK bug / regWr( rSNDBC, 0 ); regWr( rSNDFIFO, data_p ); regWr( rSNDBC, bytes_tosend ); regWr( rHXFR, ( tokOUT \| ep )); //dispatch packet while(!(regRd( rHIRQ ) & bmHXFRDNIRQ )); //wait for the completion IRQ regWr( rHIRQ, bmHXFRDNIRQ ); //clear IRQ rcode = ( regRd( rHRSL ) & 0x0f ); }//while( rcode && .... bytes_left -= bytes_tosend; data_p += bytes_tosend; }//while( bytes_left... devtable[ addr ].epinfo[ ep ].sndToggle = ( regRd( rHRSL ) & bmSNDTOGRD ) ? bmSNDTOG1 : bmSNDTOG0; //update toggle return( rcode ); //should be 0 in all cases } /* dispatch usb packet. Assumes peripheral address is set and relevant buffer is loaded/empty / / If NAK, tries to re-send up to nak_limit times / / If nak_limit == 0, do not count NAKs, exit after timeout / / If bus timeout, re-sends up to USB_RETRY_LIMIT times / / return codes 0x00-0x0f are HRSLT( 0x00 being success ), 0xff means timeout / byte USB::dispatchPkt( byte token, byte ep, unsigned int nak_limit ) { unsigned long timeout = millis() + USB_XFER_TIMEOUT; byte tmpdata; byte rcode; unsigned int nak_count = 0; char retry_count = 0; while( timeout > millis() ) { regWr( rHXFR, ( token\|ep )); //launch the transfer rcode = 0xff; while( millis() < timeout ) { //wait for transfer completion tmpdata = regRd( rHIRQ ); if( tmpdata & bmHXFRDNIRQ ) { regWr( rHIRQ, bmHXFRDNIRQ ); //clear the interrupt rcode = 0x00; break; }//if( tmpdata & bmHXFRDNIRQ }//while ( millis() < timeout if( rcode != 0x00 ) { //exit if timeout return( rcode ); } rcode = ( regRd( rHRSL ) & 0x0f ); //analyze transfer result switch( rcode ) { case hrNAK: nak_count ++; if( nak_limit && ( nak_count == nak_limit )) { return( rcode ); } break; case hrTIMEOUT: retry_count ++; if( retry_count == USB_RETRY_LIMIT ) { return( rcode ); } break; default: return( rcode ); }//switch( rcode }//while( timeout > millis() return( rcode ); } / USB main task. Performs enumeration/cleanup / void USB::Task( void ) //USB state machine { byte i; byte rcode; static byte tmpaddr; byte tmpdata; static unsigned long delay = 0; USB_DEVICE_DESCRIPTOR buf; tmpdata = getVbusState(); / modify USB task state if Vbus changed / switch( tmpdata ) { case SE1: //illegal state usb_task_state = USB_DETACHED_SUBSTATE_ILLEGAL; break; case SE0: //disconnected if(( usb_task_state & USB_STATE_MASK ) != USB_STATE_DETACHED ) { usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE; } break; case FSHOST: //attached case LSHOST: if(( usb_task_state & USB_STATE_MASK ) == USB_STATE_DETACHED ) { delay = millis() + USB_SETTLE_DELAY; usb_task_state = USB_ATTACHED_SUBSTATE_SETTLE; } break; }// switch( tmpdata //Serial.print("USB task state: "); //Serial.println( usb_task_state, HEX ); switch( usb_task_state ) { case USB_DETACHED_SUBSTATE_INITIALIZE: init(); usb_task_state = USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE; break; case USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE: //just sit here break; case USB_DETACHED_SUBSTATE_ILLEGAL: //just sit here break; case USB_ATTACHED_SUBSTATE_SETTLE: //setlle time for just attached device if( delay < millis() ) { usb_task_state = USB_ATTACHED_SUBSTATE_RESET_DEVICE; } break; case USB_ATTACHED_SUBSTATE_RESET_DEVICE: regWr( rHCTL, bmBUSRST ); //issue bus reset usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE; break; case USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE: if(( regRd( rHCTL ) & bmBUSRST ) == 0 ) { tmpdata = regRd( rMODE ) \| bmSOFKAENAB; //start SOF generation regWr( rMODE, tmpdata ); // regWr( rMODE, bmSOFKAENAB ); usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_SOF; delay = millis() + 20; //20ms wait after reset per USB spec } break; case USB_ATTACHED_SUBSTATE_WAIT_SOF: //todo: change check order if( regRd( rHIRQ ) & bmFRAMEIRQ ) { //when first SOF received we can continue if( delay < millis() ) { //20ms passed usb_task_state = USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE; } } break; case USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE: // toggle( BPNT_0 ); devtable[ 0 ].epinfo->MaxPktSize = 8; //set max.packet size to min.allowed rcode = getDevDescr( 0, 0, 8, ( char )&buf ); if( rcode == 0 ) { devtable[ 0 ].epinfo->MaxPktSize = buf.bMaxPacketSize0; usb_task_state = USB_STATE_ADDRESSING; } else { usb_error = USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE; usb_task_state = USB_STATE_ERROR; } break; case USB_STATE_ADDRESSING: for( i = 1; i < USB_NUMDEVICES; i++ ) { if( devtable[ i ].epinfo == NULL ) { devtable[ i ].epinfo = devtable[ 0 ].epinfo; //set correct MaxPktSize //temporary record //until plugged with real device endpoint structure rcode = setAddr( 0, 0, i ); if( rcode == 0 ) { tmpaddr = i; usb_task_state = USB_STATE_CONFIGURING; } else { usb_error = USB_STATE_ADDRESSING; //set address error usb_task_state = USB_STATE_ERROR; } break; //break if address assigned or error occured during address assignment attempt } }//for( i = 1; i < USB_NUMDEVICES; i++ if( usb_task_state == USB_STATE_ADDRESSING ) { //no vacant place in devtable usb_error = 0xfe; usb_task_state = USB_STATE_ERROR; } break; case USB_STATE_CONFIGURING: break; case USB_STATE_RUNNING: break; case USB_STATE_ERROR: break; }// switch( usb_task_state }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/Usb.cpp	C++	oos	20,111
/* * Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com * MAX3421E USB host controller support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the authors nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. / / MAX3421E register/bit names and bitmasks / #ifndef _MAX3421Econstants_h_ #define _MAX3421Econstants_h_ / SPI pins for diffrent Arduinos / #if defined(__AVR_ATmega1280__) \|\| (__AVR_ATmega2560__) #define SCK_PIN 52 #define MISO_PIN 50 #define MOSI_PIN 51 #define SS_PIN 53 #endif #if defined(__AVR_ATmega168__) \|\| defined(__AVR_ATmega328P__) #define SCK_PIN 13 #define MISO_PIN 12 #define MOSI_PIN 11 #define SS_PIN 10 #endif #define MAX_SS 53 #define MAX_INT 9 #define MAX_GPX 8 #define MAX_RESET 7 / "Breakpoint" pins for debugging / //#define BPNT_0 3 //#define BPNT_1 2 //#define Select_MAX3421E digitalWrite(MAX_SS,LOW) //#define Deselect_MAX3421E digitalWrite(MAX_SS,HIGH) / / #define ON true #define OFF false / VBUS states / #define SE0 0 #define SE1 1 #define FSHOST 2 #define LSHOST 3 / MAX3421E command byte format: rrrrr0wa where 'r' is register number / // // MAX3421E Registers in HOST mode. // #define rRCVFIFO 0x08 //1<<3 #define rSNDFIFO 0x10 //2<<3 #define rSUDFIFO 0x20 //4<<3 #define rRCVBC 0x30 //6<<3 #define rSNDBC 0x38 //7<<3 #define rUSBIRQ 0x68 //13<<3 / USBIRQ Bits / #define bmVBUSIRQ 0x40 //b6 #define bmNOVBUSIRQ 0x20 //b5 #define bmOSCOKIRQ 0x01 //b0 #define rUSBIEN 0x70 //14<<3 / USBIEN Bits / #define bmVBUSIE 0x40 //b6 #define bmNOVBUSIE 0x20 //b5 #define bmOSCOKIE 0x01 //b0 #define rUSBCTL 0x78 //15<<3 / USBCTL Bits / #define bmCHIPRES 0x20 //b5 #define bmPWRDOWN 0x10 //b4 #define rCPUCTL 0x80 //16<<3 / CPUCTL Bits / #define bmPUSLEWID1 0x80 //b7 #define bmPULSEWID0 0x40 //b6 #define bmIE 0x01 //b0 #define rPINCTL 0x88 //17<<3 / PINCTL Bits / #define bmFDUPSPI 0x10 //b4 #define bmINTLEVEL 0x08 //b3 #define bmPOSINT 0x04 //b2 #define bmGPXB 0x02 //b1 #define bmGPXA 0x01 //b0 // GPX pin selections #define GPX_OPERATE 0x00 #define GPX_VBDET 0x01 #define GPX_BUSACT 0x02 #define GPX_SOF 0x03 #define rREVISION 0x90 //18<<3 #define rIOPINS1 0xa0 //20<<3 / IOPINS1 Bits / #define bmGPOUT0 0x01 #define bmGPOUT1 0x02 #define bmGPOUT2 0x04 #define bmGPOUT3 0x08 #define bmGPIN0 0x10 #define bmGPIN1 0x20 #define bmGPIN2 0x40 #define bmGPIN3 0x80 #define rIOPINS2 0xa8 //21<<3 / IOPINS2 Bits / #define bmGPOUT4 0x01 #define bmGPOUT5 0x02 #define bmGPOUT6 0x04 #define bmGPOUT7 0x08 #define bmGPIN4 0x10 #define bmGPIN5 0x20 #define bmGPIN6 0x40 #define bmGPIN7 0x80 #define rGPINIRQ 0xb0 //22<<3 / GPINIRQ Bits / #define bmGPINIRQ0 0x01 #define bmGPINIRQ1 0x02 #define bmGPINIRQ2 0x04 #define bmGPINIRQ3 0x08 #define bmGPINIRQ4 0x10 #define bmGPINIRQ5 0x20 #define bmGPINIRQ6 0x40 #define bmGPINIRQ7 0x80 #define rGPINIEN 0xb8 //23<<3 / GPINIEN Bits / #define bmGPINIEN0 0x01 #define bmGPINIEN1 0x02 #define bmGPINIEN2 0x04 #define bmGPINIEN3 0x08 #define bmGPINIEN4 0x10 #define bmGPINIEN5 0x20 #define bmGPINIEN6 0x40 #define bmGPINIEN7 0x80 #define rGPINPOL 0xc0 //24<<3 / GPINPOL Bits / #define bmGPINPOL0 0x01 #define bmGPINPOL1 0x02 #define bmGPINPOL2 0x04 #define bmGPINPOL3 0x08 #define bmGPINPOL4 0x10 #define bmGPINPOL5 0x20 #define bmGPINPOL6 0x40 #define bmGPINPOL7 0x80 #define rHIRQ 0xc8 //25<<3 / HIRQ Bits / #define bmBUSEVENTIRQ 0x01 // indicates BUS Reset Done or BUS Resume #define bmRWUIRQ 0x02 #define bmRCVDAVIRQ 0x04 #define bmSNDBAVIRQ 0x08 #define bmSUSDNIRQ 0x10 #define bmCONDETIRQ 0x20 #define bmFRAMEIRQ 0x40 #define bmHXFRDNIRQ 0x80 #define rHIEN 0xd0 //26<<3 / HIEN Bits / #define bmBUSEVENTIE 0x01 #define bmRWUIE 0x02 #define bmRCVDAVIE 0x04 #define bmSNDBAVIE 0x08 #define bmSUSDNIE 0x10 #define bmCONDETIE 0x20 #define bmFRAMEIE 0x40 #define bmHXFRDNIE 0x80 #define rMODE 0xd8 //27<<3 / MODE Bits / #define bmHOST 0x01 #define bmLOWSPEED 0x02 #define bmHUBPRE 0x04 #define bmSOFKAENAB 0x08 #define bmSEPIRQ 0x10 #define bmDELAYISO 0x20 #define bmDMPULLDN 0x40 #define bmDPPULLDN 0x80 #define rPERADDR 0xe0 //28<<3 #define rHCTL 0xe8 //29<<3 / HCTL Bits / #define bmBUSRST 0x01 #define bmFRMRST 0x02 #define bmSAMPLEBUS 0x04 #define bmSIGRSM 0x08 #define bmRCVTOG0 0x10 #define bmRCVTOG1 0x20 #define bmSNDTOG0 0x40 #define bmSNDTOG1 0x80 #define rHXFR 0xf0 //30<<3 / Host transfer token values for writing the HXFR register (R30) / / OR this bit field with the endpoint number in bits 3:0 / #define tokSETUP 0x10 // HS=0, ISO=0, OUTNIN=0, SETUP=1 #define tokIN 0x00 // HS=0, ISO=0, OUTNIN=0, SETUP=0 #define tokOUT 0x20 // HS=0, ISO=0, OUTNIN=1, SETUP=0 #define tokINHS 0x80 // HS=1, ISO=0, OUTNIN=0, SETUP=0 #define tokOUTHS 0xA0 // HS=1, ISO=0, OUTNIN=1, SETUP=0 #define tokISOIN 0x40 // HS=0, ISO=1, OUTNIN=0, SETUP=0 #define tokISOOUT 0x60 // HS=0, ISO=1, OUTNIN=1, SETUP=0 #define rHRSL 0xf8 //31<<3 / HRSL Bits / #define bmRCVTOGRD 0x10 #define bmSNDTOGRD 0x20 #define bmKSTATUS 0x40 #define bmJSTATUS 0x80 #define bmSE0 0x00 //SE0 - disconnect state #define bmSE1 0xc0 //SE1 - illegal state / Host error result codes, the 4 LSB's in the HRSL register */ #define hrSUCCESS 0x00 #define hrBUSY 0x01 #define hrBADREQ 0x02 #define hrUNDEF 0x03 #define hrNAK 0x04 #define hrSTALL 0x05 #define hrTOGERR 0x06 #define hrWRONGPID 0x07 #define hrBADBC 0x08 #define hrPIDERR 0x09 #define hrPKTERR 0x0A #define hrCRCERR 0x0B #define hrKERR 0x0C #define hrJERR 0x0D #define hrTIMEOUT 0x0E #define hrBABBLE 0x0F #define MODE_FS_HOST (bmDPPULLDN\|bmDMPULLDN\|bmHOST\|bmSOFKAENAB) #define MODE_LS_HOST (bmDPPULLDN\|bmDMPULLDN\|bmHOST\|bmLOWSPEED\|bmSOFKAENAB) #endif //_MAX3421Econstants_h_	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/arduino_libs/USB_Host_Shield/Max3421e_constants.h	C	oos	7,979
#include <Max3421e.h> #include <Usb.h> #include <AndroidAccessory.h> AndroidAccessory acc("STMicroelectronics", "adkping", "Just pings data", "2.0", "http://www.st.com", "1234567890123456"); char sendBuffer[]="ArduinoAccessory!"; char receiveBuffer[128]; int len; void setup(); void loop(); void mainPhase(); void setup() { Serial.begin(115200); Serial.print("\r\nStart"); acc.powerOn(); } void loop() { if (acc.isConnected()) { Serial.print("\r\nInside acc.isconnected, calling mainphase..."); mainPhase(); Serial.print("\r\nExited from mainphase..."); } Serial.print("\r\nTest loop..."); delay(10); } void mainPhase(){ while(1){ len=acc.write(sendBuffer,17); Serial.print("\r\nSent accessory name... Total chars sent:"); Serial.print(len); Serial.print("\r\nReceived from accessory: "); len = acc.read(receiveBuffer, sizeof(receiveBuffer), 1); Serial.print(receiveBuffer); Serial.print(" Total chars received: "); Serial.print(len); delay(1000); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/firmware/demokit/demokit.pde	Processing	oos	1,156
package com.google.android.DemoKit; import android.text.SpannableStringBuilder; import android.text.style.RelativeSizeSpan; import android.text.style.SubscriptSpan; import android.view.ViewGroup; import android.widget.TextView; public class ServoController implements Slider.SliderPositionListener { private final int mServoNumber; private final byte mCommandTarget; private TextView mLabel; private Slider mSlider; private DemoKitActivity mActivity; public ServoController(DemoKitActivity activity, int servoNumber) { mActivity = activity; mServoNumber = servoNumber; mCommandTarget = (byte) (servoNumber - 1 + 0x10); } public void attachToView(ViewGroup targetView) { mLabel = (TextView) targetView.getChildAt(0); SpannableStringBuilder ssb = new SpannableStringBuilder("Servo"); ssb.append(String.valueOf(mServoNumber)); ssb.setSpan(new SubscriptSpan(), 5, 6, 0); ssb.setSpan(new RelativeSizeSpan(0.7f), 5, 6, 0); mLabel.setText(ssb); mSlider = (Slider) targetView.getChildAt(1); mSlider.setPositionListener(this); } public void onPositionChange(double value) { byte v = (byte) (value * 255); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND, mCommandTarget, v); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/ServoController.java	Java	oos	1,224
package com.google.android.DemoKit; import android.content.Context; import android.content.res.Resources; import android.graphics.Canvas; import android.graphics.Rect; import android.graphics.drawable.Drawable; import android.util.AttributeSet; import android.view.MotionEvent; import android.view.View; public class Slider extends View { interface SliderPositionListener { void onPositionChange(double value); } private Drawable mIndicator; private Drawable mBackground; private double mPosition; private SliderPositionListener mListener; private boolean mVertical; public Slider(Context context) { super(context); initSliderView(context, false); } public Slider(Context context, AttributeSet attrs) { super(context, attrs); initSliderView(context, false); } public void setSliderBackground(Drawable background) { mBackground = background; invalidate(); } public void setPositionListener(SliderPositionListener listener) { mListener = listener; } public void setPosition(double position) { if (mPosition != position) { invalidate(); mPosition = position; if (mListener != null) { mListener.onPositionChange(mPosition); } } } private OnTouchListener mClickListener = new OnTouchListener() { public boolean onTouch(View v, MotionEvent m) { Rect r = new Rect(); getDrawingRect(r); double position; if (mVertical) { double y = m.getY(); position = Math.max(0, (r.bottom - y) / r.height()); } else { double x = m.getX(); position = Math.max(0, (x - r.left) / r.width()); } position = Math.min(1, position); setPosition(position); return true; } }; protected void initSliderView(Context context, boolean vertical) { mPosition = 0; mVertical = vertical; Resources res = context.getResources(); if (mVertical) { mBackground = res .getDrawable(R.drawable.scrubber_vertical_blue_holo_dark); } else { mBackground = res .getDrawable(R.drawable.scrubber_horizontal_holo_dark); } mIndicator = res.getDrawable(R.drawable.scrubber_control_holo_dark); this.setOnTouchListener(mClickListener); } protected void onDraw(Canvas canvas) { Rect r = new Rect(); getDrawingRect(r); if (mVertical) { int lineX = r.centerX(); int bgW = mBackground.getIntrinsicWidth() / 2; if (bgW == 0) { bgW = 5; } mBackground.setBounds(lineX - bgW, r.top + 10, lineX + bgW, r.bottom - 10); mBackground.draw(canvas); final int kMargin = 48; int indicatorY = (int) (r.bottom - (r.height() - kMargin) * mPosition) - kMargin / 2; Utilities.centerAround(lineX, indicatorY, mIndicator); mIndicator.draw(canvas); } else { int lineY = r.centerY(); int bgH = mBackground.getIntrinsicHeight() / 2; if (bgH == 0) { bgH = 5; } mBackground.setBounds(r.left + 10, lineY - bgH, r.right - 10, lineY + bgH); mBackground.draw(canvas); final int kMargin = 48; int indicatorX = (int) ((r.width() - kMargin) * mPosition) + r.left + kMargin / 2; Utilities.centerAround(indicatorX, lineY, mIndicator); mIndicator.draw(canvas); } } protected void onMeasure(int widthMeasureSpec, int heightMeasureSpec) { super.onMeasure(widthMeasureSpec, heightMeasureSpec); if (mVertical) { setMeasuredDimension(mIndicator.getIntrinsicWidth(), getMeasuredHeight()); } else { setMeasuredDimension(getMeasuredWidth(), mIndicator.getIntrinsicHeight()); } } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/Slider.java	Java	oos	3,458
package com.google.android.DemoKit; import android.content.Context; import android.content.res.Resources; import android.graphics.Canvas; import android.graphics.Color; import android.graphics.Paint; import android.graphics.drawable.Drawable; import android.util.AttributeSet; import android.view.View; public class JoystickView extends View { private Drawable mJoystickBackground; private Drawable mJoystickPressed; private Drawable mJoystickNormal; private int fX; private int fY; Boolean fPressed; private Paint mLabelPaint; private String mLabelText; public JoystickView(Context context) { super(context); initJoystickView(context); } public JoystickView(Context context, AttributeSet attrs) { super(context, attrs); initJoystickView(context); } public void setPosition(int x, int y) { fX = x; fY = y; mLabelText = String.format("%d,%d", fX, fY); invalidate(); } public void setPressed(boolean pressed) { fPressed = pressed; invalidate(); } private void initJoystickView(Context context) { fX = fY = 0; fPressed = false; Resources r = context.getResources(); mJoystickBackground = r.getDrawable(R.drawable.joystick_background); int w = mJoystickBackground.getIntrinsicWidth(); int h = mJoystickBackground.getIntrinsicHeight(); mJoystickBackground.setBounds(0, 0, w, h); mJoystickPressed = r.getDrawable(R.drawable.joystick_pressed_holo_dark); mJoystickNormal = r.getDrawable(R.drawable.joystick_normal_holo_dark); Utilities.centerAround(w / 2 - 4, h / 2 + 4, mJoystickNormal); Utilities.centerAround(w / 2 - 4, h / 2 + 4, mJoystickPressed); mLabelPaint = new Paint(); mLabelPaint.setColor(Color.WHITE); mLabelPaint.setTextSize(24); mLabelPaint.setAntiAlias(true); mLabelPaint.setShadowLayer(1, 2, 2, Color.BLACK); setPosition(0, 0); } @Override protected void onDraw(Canvas canvas) { mJoystickBackground.draw(canvas); Drawable indicator = fPressed ? mJoystickPressed : mJoystickNormal; int w = mJoystickBackground.getIntrinsicWidth(); int h = mJoystickBackground.getIntrinsicHeight(); int x = w / 2 - 4 + fX; int y = h / 2 + 4 + fY; Utilities.centerAround(x, y, indicator); indicator.draw(canvas); canvas.drawText(mLabelText, x + 12, y + 8, mLabelPaint); } @Override protected void onMeasure(int widthMeasureSpec, int heightMeasureSpec) { setMeasuredDimension(mJoystickBackground.getIntrinsicWidth(), mJoystickBackground.getIntrinsicHeight()); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/JoystickView.java	Java	oos	2,466
package com.google.android.DemoKit; import android.graphics.drawable.Drawable; import android.os.Bundle; import android.view.View; import android.view.View.OnClickListener; import android.widget.LinearLayout; import android.widget.TextView; public class DemoKitPhone extends BaseActivity implements OnClickListener { static final String TAG = "DemoKitPhone"; /** Called when the activity is first created. */ TextView mInputLabel; TextView mOutputLabel; LinearLayout mInputContainer; LinearLayout mOutputContainer; Drawable mFocusedTabImage; Drawable mNormalTabImage; OutputController mOutputController; @Override protected void hideControls() { super.hideControls(); mOutputController = null; } public void onCreate(Bundle savedInstanceState) { mFocusedTabImage = getResources().getDrawable( R.drawable.tab_focused_holo_dark); mNormalTabImage = getResources().getDrawable( R.drawable.tab_normal_holo_dark); super.onCreate(savedInstanceState); } protected void showControls() { super.showControls(); mOutputController = new OutputController(this, false); mOutputController.accessoryAttached(); mInputLabel = (TextView) findViewById(R.id.inputLabel); mOutputLabel = (TextView) findViewById(R.id.outputLabel); mInputContainer = (LinearLayout) findViewById(R.id.inputContainer); mOutputContainer = (LinearLayout) findViewById(R.id.outputContainer); mInputLabel.setOnClickListener(this); mOutputLabel.setOnClickListener(this); showTabContents(true); } void showTabContents(Boolean showInput) { if (showInput) { mInputContainer.setVisibility(View.VISIBLE); mInputLabel.setBackgroundDrawable(mFocusedTabImage); mOutputContainer.setVisibility(View.GONE); mOutputLabel.setBackgroundDrawable(mNormalTabImage); } else { mInputContainer.setVisibility(View.GONE); mInputLabel.setBackgroundDrawable(mNormalTabImage); mOutputContainer.setVisibility(View.VISIBLE); mOutputLabel.setBackgroundDrawable(mFocusedTabImage); } } public void onClick(View v) { int vId = v.getId(); switch (vId) { case R.id.inputLabel: showTabContents(true); break; case R.id.outputLabel: showTabContents(false); break; } } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/DemoKitPhone.java	Java	oos	2,206
package com.google.android.DemoKit; import com.google.android.DemoKit.Slider.SliderPositionListener; import android.content.res.Resources; import android.graphics.drawable.Drawable; import android.text.SpannableStringBuilder; import android.text.style.RelativeSizeSpan; import android.text.style.SubscriptSpan; import android.view.View; import android.view.View.OnClickListener; import android.view.ViewGroup; import android.widget.TextView; public class ColorLEDController { private int mLEDNumber; private Drawable mGreen; private Drawable mRed; private Drawable mBlue; private DemoKitActivity mActivity; class LedValueUpdater implements Slider.SliderPositionListener { private TextView mTarget; private final byte mCommandTarget; LedValueUpdater(TextView target, int colorIndex) { mTarget = target; mCommandTarget = (byte) ((mLEDNumber - 1) * 3 + colorIndex); } public void onPositionChange(double value) { int v = (int) (255 * value); mTarget.setText(String.valueOf(v)); if (mActivity != null) { mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND, mCommandTarget, (byte) v); } } } class LabelClickListener implements OnClickListener { final private double mValue; private final Slider mSlider; public LabelClickListener(Slider slider, double value) { mSlider = slider; mValue = value; } public void onClick(View v) { mSlider.setPosition(mValue); } } public ColorLEDController(DemoKitActivity activity, int number, Resources res, boolean vertical) { mActivity = activity; mLEDNumber = number; if (vertical) { mRed = res.getDrawable(R.drawable.scrubber_vertical_red_holo_dark); mGreen = res .getDrawable(R.drawable.scrubber_vertical_green_holo_dark); mBlue = res .getDrawable(R.drawable.scrubber_vertical_blue_holo_dark); } else { mRed = res .getDrawable(R.drawable.scrubber_horizontal_red_holo_dark); mGreen = res .getDrawable(R.drawable.scrubber_horizontal_green_holo_dark); mBlue = res .getDrawable(R.drawable.scrubber_horizontal_blue_holo_dark); } } public void attachToView(ViewGroup targetView) { for (int i = 0; i < 3; ++i) { ViewGroup g = (ViewGroup) targetView.getChildAt(i); TextView label = (TextView) g.getChildAt(0); Slider slider = (Slider) g.getChildAt(1); TextView valueText = (TextView) g.getChildAt(2); SliderPositionListener positionListener = new LedValueUpdater( valueText, i); slider.setPositionListener(positionListener); LabelClickListener leftLabelListener = new LabelClickListener( slider, 0); label.setOnClickListener(leftLabelListener); LabelClickListener rightLabelListener = new LabelClickListener( slider, 1); valueText.setOnClickListener(rightLabelListener); valueText.setText("0"); if (i == 0) { String labelText = "Led"; SpannableStringBuilder ssb = new SpannableStringBuilder( labelText); ssb.append(String.valueOf(mLEDNumber)); int spanStart = labelText.length(); int spanEnd = spanStart + 1; ssb.setSpan(new SubscriptSpan(), spanStart, spanEnd, 0); ssb.setSpan(new RelativeSizeSpan(0.7f), spanStart, spanEnd, 0); label.setText(ssb); slider.setSliderBackground(mRed); } else { label.setText(""); if (i == 1) { slider.setSliderBackground(mGreen); } else { slider.setSliderBackground(mBlue); } } } } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/ColorLEDController.java	Java	oos	3,415
package com.google.android.DemoKit; public class DemoKitTablet extends BaseActivity { private OutputController mOutputController; protected void hideControls() { super.hideControls(); mOutputController = null; } protected void showControls() { super.showControls(); mOutputController = new OutputController(this, true); mOutputController.accessoryAttached(); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/DemoKitTablet.java	Java	oos	381
/* * Copyright (C) 2011 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package com.google.android.DemoKit; import android.content.Context; import android.graphics.; import android.util.AttributeSet; import android.view.MotionEvent; import android.view.View; /* This class was masterfully pilfered, Carmen-Sandiego style, from our awesome sample app * ApiDemos. To see how it looks as a dialog, check out: * http://developer.android.com/resources/samples/ApiDemos/src/com/example/android/apis/graphics/ColorPickerDialog.html * / public class ColorWheel extends View { public interface OnColorChangedListener { void colorChanged(int color); } / / private OnColorChangedListener mListener; private int mInitialColor; private Paint mPaint; private Paint mCenterPaint; private final int[] mColors; public void setOnColorChangedListener(OnColorChangedListener l) { mListener = l; } public ColorWheel(Context c, AttributeSet attributes) { super(c, attributes); mColors = new int[] { 0xFFFF0000, 0xFFFF00FF, 0xFF0000FF, 0xFF00FFFF, 0xFF00FF00, 0xFFFFFF00, 0xFFFF0000 }; Shader s = new SweepGradient(0, 0, mColors, null); mPaint = new Paint(Paint.ANTI_ALIAS_FLAG); mPaint.setShader(s); mPaint.setStyle(Paint.Style.STROKE); mPaint.setStrokeWidth(32); mCenterPaint = new Paint(Paint.ANTI_ALIAS_FLAG); mCenterPaint.setColor(0); mCenterPaint.setStrokeWidth(5); } private boolean mTrackingCenter; private boolean mHighlightCenter; @Override protected void onDraw(Canvas canvas) { super.onDraw(canvas); float r = CENTER_X - mPaint.getStrokeWidth()0.5f; canvas.translate(CENTER_X, CENTER_X); canvas.drawOval(new RectF(-r, -r, r, r), mPaint); canvas.drawCircle(0, 0, CENTER_RADIUS, mCenterPaint); if (mTrackingCenter) { int c = mCenterPaint.getColor(); mCenterPaint.setStyle(Paint.Style.STROKE); if (mHighlightCenter) { mCenterPaint.setAlpha(0xFF); } else { mCenterPaint.setAlpha(0x80); } canvas.drawCircle(0, 0, CENTER_RADIUS + mCenterPaint.getStrokeWidth(), mCenterPaint); mCenterPaint.setStyle(Paint.Style.FILL); mCenterPaint.setColor(c); } } @Override protected void onMeasure(int widthMeasureSpec, int heightMeasureSpec) { setMeasuredDimension(CENTER_X2, CENTER_Y2); } private static final int CENTER_X = 200; private static final int CENTER_Y = 200; private static final int CENTER_RADIUS = 64; private int floatToByte(float x) { int n = java.lang.Math.round(x); return n; } private int pinToByte(int n) { if (n < 0) { n = 0; } else if (n > 255) { n = 255; } return n; } private int ave(int s, int d, float p) { return s + java.lang.Math.round(p * (d - s)); } private int interpColor(int colors[], float unit) { if (unit <= 0) { return colors[0]; } if (unit >= 1) { return colors[colors.length - 1]; } float p = unit * (colors.length - 1); int i = (int)p; p -= i; // now p is just the fractional part [0...1) and i is the index int c0 = colors[i]; int c1 = colors[i+1]; int a = ave(Color.alpha(c0), Color.alpha(c1), p); int r = ave(Color.red(c0), Color.red(c1), p); int g = ave(Color.green(c0), Color.green(c1), p); int b = ave(Color.blue(c0), Color.blue(c1), p); return Color.argb(a, r, g, b); } private int rotateColor(int color, float rad) { float deg = rad * 180 / 3.1415927f; int r = Color.red(color); int g = Color.green(color); int b = Color.blue(color); ColorMatrix cm = new ColorMatrix(); ColorMatrix tmp = new ColorMatrix(); cm.setRGB2YUV(); tmp.setRotate(0, deg); cm.postConcat(tmp); tmp.setYUV2RGB(); cm.postConcat(tmp); final float[] a = cm.getArray(); int ir = floatToByte(a[0] * r + a[1] * g + a[2] * b); int ig = floatToByte(a[5] * r + a[6] * g + a[7] * b); int ib = floatToByte(a[10] * r + a[11] * g + a[12] * b); return Color.argb(Color.alpha(color), pinToByte(ir), pinToByte(ig), pinToByte(ib)); } private static final float PI = 3.1415926f; @Override public boolean onTouchEvent(MotionEvent event) { float x = event.getX() - CENTER_X; float y = event.getY() - CENTER_Y; boolean inCenter = java.lang.Math.sqrt(xx + yy) <= CENTER_RADIUS; switch (event.getAction()) { case MotionEvent.ACTION_DOWN: mTrackingCenter = inCenter; if (inCenter) { mHighlightCenter = true; invalidate(); break; } case MotionEvent.ACTION_MOVE: if (mTrackingCenter) { if (mHighlightCenter != inCenter) { mHighlightCenter = inCenter; invalidate(); } } else { float angle = (float)java.lang.Math.atan2(y, x); // need to turn angle [-PI ... PI] into unit [0....1] float unit = angle/(2*PI); if (unit < 0) { unit += 1; } mCenterPaint.setColor(interpColor(mColors, unit)); invalidate(); mListener.colorChanged(mCenterPaint.getColor()); } break; case MotionEvent.ACTION_UP: if (mTrackingCenter) { if (inCenter) { mListener.colorChanged(mCenterPaint.getColor()); } mListener.colorChanged(0); // mListener.colorChanged(mCenterPaint.getColor()); mTrackingCenter = false; // so we draw w/o halo invalidate(); } break; } return true; } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/ColorWheel.java	Java	oos	7,371
package com.google.android.DemoKit; import android.view.ViewGroup; public class OutputController extends AccessoryController { private boolean mVertical; OutputController(DemoKitActivity hostActivity, boolean vertical) { super(hostActivity); mVertical = vertical; } protected void onAccesssoryAttached() { setupServoController(1, R.id.servo1); setupServoController(2, R.id.servo2); setupServoController(3, R.id.servo3); setupLedController(1, R.id.leds1); setupLedController(2, R.id.leds2); setupLedController(3, R.id.leds3); setupRelayController(1, R.id.relay1); setupRelayController(2, R.id.relay2); } private void setupServoController(int servoIndex, int viewId) { ServoController sc = new ServoController(mHostActivity, servoIndex); sc.attachToView((ViewGroup) findViewById(viewId)); } private void setupLedController(int index, int viewId) { ColorLEDController ledC = new ColorLEDController(mHostActivity, index, getResources(), mVertical); ledC.attachToView((ViewGroup) findViewById(viewId)); } private void setupRelayController(int index, int viewId) { RelayController r = new RelayController(mHostActivity, index, getResources()); r.attachToView((ViewGroup) findViewById(viewId)); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/OutputController.java	Java	oos	1,254
package com.google.android.DemoKit; import android.graphics.drawable.Drawable; public class Utilities { static void centerAround(int x, int y, Drawable d) { int w = d.getIntrinsicWidth(); int h = d.getIntrinsicHeight(); int left = x - w / 2; int top = y - h / 2; int right = left + w; int bottom = top + h; d.setBounds(left, top, right, bottom); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/Utilities.java	Java	oos	369
package com.google.android.DemoKit; import android.os.Bundle; import android.view.Menu; import android.view.MenuItem; public class BaseActivity extends DemoKitActivity { private InputController mInputController; public BaseActivity() { super(); } @Override public void onCreate(Bundle savedInstanceState) { super.onCreate(savedInstanceState); if (mAccessory != null) { showControls(); } else { hideControls(); } } @Override public boolean onCreateOptionsMenu(Menu menu) { menu.add("Simulate"); menu.add("Quit"); return true; } @Override public boolean onOptionsItemSelected(MenuItem item) { if (item.getTitle() == "Simulate") { showControls(); } else if (item.getTitle() == "Quit") { finish(); System.exit(0); } return true; } protected void enableControls(boolean enable) { if (enable) { showControls(); } else { hideControls(); } } protected void hideControls() { setContentView(R.layout.no_device); mInputController = null; } protected void showControls() { setContentView(R.layout.main); mInputController = new InputController(this); mInputController.accessoryAttached(); } protected void handleJoyMessage(JoyMsg j) { if (mInputController != null) { mInputController.joystickMoved(j.getX(), j.getY()); } } protected void handleLightMessage(LightMsg l) { if (mInputController != null) { mInputController.setLightValue(l.getLight()); } } protected void handleTemperatureMessage(TemperatureMsg t) { if (mInputController != null) { mInputController.setTemperature(t.getTemperature()); } } protected void handleSwitchMessage(SwitchMsg o) { if (mInputController != null) { byte sw = o.getSw(); if (sw >= 0 && sw < 4) { mInputController.switchStateChanged(sw, o.getState() != 0); } else if (sw == 4) { mInputController .joystickButtonSwitchStateChanged(o.getState() != 0); } } } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/BaseActivity.java	Java	oos	1,931
/* * Copyright (C) 2011 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package com.google.android.DemoKit; import android.app.Activity; import android.content.ActivityNotFoundException; import android.content.Intent; import android.os.Bundle; import android.util.Log; / This Activity does nothing but receive USB_DEVICE_ATTACHED events from the * USB service and springboards to the main Gallery activity */ public final class UsbAccessoryActivity extends Activity { static final String TAG = "UsbAccessoryActivity"; @Override protected void onCreate(Bundle savedInstanceState) { super.onCreate(savedInstanceState); Intent intent = DemoKitLaunch.createIntent(this); intent.addFlags(Intent.FLAG_ACTIVITY_NEW_TASK \| Intent.FLAG_ACTIVITY_CLEAR_TOP); try { startActivity(intent); } catch (ActivityNotFoundException e) { Log.e(TAG, "unable to start DemoKit activity", e); } finish(); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/UsbAccessoryActivity.java	Java	oos	1,469
package com.google.android.DemoKit; import android.app.Activity; import android.content.ActivityNotFoundException; import android.content.Intent; import android.os.Bundle; import android.util.Log; import android.view.Display; public class DemoKitLaunch extends Activity { static final String TAG = "DemoKitLaunch"; static Intent createIntent(Activity activity) { Display display = activity.getWindowManager().getDefaultDisplay(); int maxExtent = Math.max(display.getWidth(), display.getHeight()); Intent intent; if (maxExtent > 1200) { Log.i(TAG, "starting tablet ui"); intent = new Intent(activity, DemoKitTablet.class); } else { Log.i(TAG, "starting phone ui"); intent = new Intent(activity, DemoKitPhone.class); } return intent; } @Override protected void onCreate(Bundle savedInstanceState) { super.onCreate(savedInstanceState); Intent intent = createIntent(this); intent.addFlags(Intent.FLAG_ACTIVITY_NEW_TASK \| Intent.FLAG_ACTIVITY_CLEAR_TOP); try { startActivity(intent); } catch (ActivityNotFoundException e) { Log.e(TAG, "unable to start DemoKit activity", e); } finish(); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/DemoKitLaunch.java	Java	oos	1,150
/* * Copyright (C) 2011 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package com.google.android.DemoKit; import java.io.FileDescriptor; import java.io.FileInputStream; import java.io.FileOutputStream; import java.io.IOException; import android.app.Activity; import android.app.PendingIntent; import android.content.BroadcastReceiver; import android.content.Context; import android.content.Intent; import android.content.IntentFilter; import android.os.Bundle; import android.os.Handler; import android.os.Message; import android.os.ParcelFileDescriptor; import android.util.Log; import android.widget.SeekBar; import com.android.future.usb.UsbAccessory; import com.android.future.usb.UsbManager; public class DemoKitActivity extends Activity implements Runnable { private static final String TAG = "DemoKit"; private static final String ACTION_USB_PERMISSION = "com.google.android.DemoKit.action.USB_PERMISSION"; private UsbManager mUsbManager; private PendingIntent mPermissionIntent; private boolean mPermissionRequestPending; UsbAccessory mAccessory; ParcelFileDescriptor mFileDescriptor; FileInputStream mInputStream; FileOutputStream mOutputStream; private static final int MESSAGE_SWITCH = 1; private static final int MESSAGE_TEMPERATURE = 2; private static final int MESSAGE_LIGHT = 3; private static final int MESSAGE_JOY = 4; public static final byte LED_SERVO_COMMAND = 2; public static final byte RELAY_COMMAND = 3; protected class SwitchMsg { private byte sw; private byte state; public SwitchMsg(byte sw, byte state) { this.sw = sw; this.state = state; } public byte getSw() { return sw; } public byte getState() { return state; } } protected class TemperatureMsg { private int temperature; public TemperatureMsg(int temperature) { this.temperature = temperature; } public int getTemperature() { return temperature; } } protected class LightMsg { private int light; public LightMsg(int light) { this.light = light; } public int getLight() { return light; } } protected class JoyMsg { private int x; private int y; public JoyMsg(int x, int y) { this.x = x; this.y = y; } public int getX() { return x; } public int getY() { return y; } } private final BroadcastReceiver mUsbReceiver = new BroadcastReceiver() { @Override public void onReceive(Context context, Intent intent) { String action = intent.getAction(); if (ACTION_USB_PERMISSION.equals(action)) { synchronized (this) { UsbAccessory accessory = UsbManager.getAccessory(intent); if (intent.getBooleanExtra( UsbManager.EXTRA_PERMISSION_GRANTED, false)) { openAccessory(accessory); } else { Log.d(TAG, "permission denied for accessory " + accessory); } mPermissionRequestPending = false; } } else if (UsbManager.ACTION_USB_ACCESSORY_DETACHED.equals(action)) { UsbAccessory accessory = UsbManager.getAccessory(intent); if (accessory != null && accessory.equals(mAccessory)) { closeAccessory(); } } } }; /* Called when the activity is first created. / @Override public void onCreate(Bundle savedInstanceState) { super.onCreate(savedInstanceState); mUsbManager = UsbManager.getInstance(this); mPermissionIntent = PendingIntent.getBroadcast(this, 0, new Intent( ACTION_USB_PERMISSION), 0); IntentFilter filter = new IntentFilter(ACTION_USB_PERMISSION); filter.addAction(UsbManager.ACTION_USB_ACCESSORY_DETACHED); registerReceiver(mUsbReceiver, filter); if (getLastNonConfigurationInstance() != null) { mAccessory = (UsbAccessory) getLastNonConfigurationInstance(); openAccessory(mAccessory); } setContentView(R.layout.main); enableControls(false); } @Override public Object onRetainNonConfigurationInstance() { if (mAccessory != null) { return mAccessory; } else { return super.onRetainNonConfigurationInstance(); } } @Override public void onResume() { super.onResume(); Intent intent = getIntent(); if (mInputStream != null && mOutputStream != null) { return; } UsbAccessory[] accessories = mUsbManager.getAccessoryList(); UsbAccessory accessory = (accessories == null ? null : accessories[0]); if (accessory != null) { if (mUsbManager.hasPermission(accessory)) { openAccessory(accessory); } else { synchronized (mUsbReceiver) { if (!mPermissionRequestPending) { mUsbManager.requestPermission(accessory, mPermissionIntent); mPermissionRequestPending = true; } } } } else { Log.d(TAG, "mAccessory is null"); } } @Override public void onPause() { super.onPause(); closeAccessory(); } @Override public void onDestroy() { unregisterReceiver(mUsbReceiver); super.onDestroy(); } private void openAccessory(UsbAccessory accessory) { mFileDescriptor = mUsbManager.openAccessory(accessory); if (mFileDescriptor != null) { mAccessory = accessory; FileDescriptor fd = mFileDescriptor.getFileDescriptor(); mInputStream = new FileInputStream(fd); mOutputStream = new FileOutputStream(fd); Thread thread = new Thread(null, this, "DemoKit"); thread.start(); Log.d(TAG, "accessory opened"); enableControls(true); } else { Log.d(TAG, "accessory open fail"); } } private void closeAccessory() { enableControls(false); try { if (mFileDescriptor != null) { mFileDescriptor.close(); } } catch (IOException e) { } finally { mFileDescriptor = null; mAccessory = null; } } protected void enableControls(boolean enable) { } private int composeInt(byte hi, byte lo) { int val = (int) hi & 0xff; val = 256; val += (int) lo & 0xff; return val; } public void run() { int ret = 0; byte[] buffer = new byte[16384]; int i; while (ret >= 0) { try { ret = mInputStream.read(buffer); } catch (IOException e) { break; } i = 0; while (i < ret) { int len = ret - i; switch (buffer[i]) { case 0x1: if (len >= 3) { Message m = Message.obtain(mHandler, MESSAGE_SWITCH); m.obj = new SwitchMsg(buffer[i + 1], buffer[i + 2]); mHandler.sendMessage(m); } i += 3; break; case 0x4: if (len >= 3) { Message m = Message.obtain(mHandler, MESSAGE_TEMPERATURE); m.obj = new TemperatureMsg(composeInt(buffer[i + 1], buffer[i + 2])); mHandler.sendMessage(m); } i += 3; break; case 0x5: if (len >= 3) { Message m = Message.obtain(mHandler, MESSAGE_LIGHT); m.obj = new LightMsg(composeInt(buffer[i + 1], buffer[i + 2])); mHandler.sendMessage(m); } i += 3; break; case 0x6: if (len >= 3) { Message m = Message.obtain(mHandler, MESSAGE_JOY); m.obj = new JoyMsg(buffer[i + 1], buffer[i + 2]); mHandler.sendMessage(m); } i += 3; break; default: Log.d(TAG, "unknown msg: " + buffer[i]); i = len; break; } } } } Handler mHandler = new Handler() { @Override public void handleMessage(Message msg) { switch (msg.what) { case MESSAGE_SWITCH: SwitchMsg o = (SwitchMsg) msg.obj; handleSwitchMessage(o); break; case MESSAGE_TEMPERATURE: TemperatureMsg t = (TemperatureMsg) msg.obj; handleTemperatureMessage(t); break; case MESSAGE_LIGHT: LightMsg l = (LightMsg) msg.obj; handleLightMessage(l); break; case MESSAGE_JOY: JoyMsg j = (JoyMsg) msg.obj; handleJoyMessage(j); break; } } }; public void sendCommand(byte command, byte target, int value) { byte[] buffer = new byte[3]; if (value > 255) value = 255; buffer[0] = command; buffer[1] = target; buffer[2] = (byte) value; if (mOutputStream != null && buffer[1] != -1) { try { mOutputStream.write(buffer); } catch (IOException e) { Log.e(TAG, "write failed", e); } } } protected void handleJoyMessage(JoyMsg j) { } protected void handleLightMessage(LightMsg l) { } protected void handleTemperatureMessage(TemperatureMsg t) { } protected void handleSwitchMessage(SwitchMsg o) { } public void onStartTrackingTouch(SeekBar seekBar) { } public void onStopTrackingTouch(SeekBar seekBar) { } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/DemoKitActivity.java	Java	oos	8,859
package com.google.android.DemoKit; import android.content.res.Resources; import android.graphics.drawable.Drawable; import android.text.SpannableStringBuilder; import android.text.style.RelativeSizeSpan; import android.text.style.SubscriptSpan; import android.view.ViewGroup; import android.widget.CompoundButton; import android.widget.CompoundButton.OnCheckedChangeListener; import android.widget.TextView; import android.widget.ToggleButton; public class RelayController implements OnCheckedChangeListener { private final int mRelayNumber; private final byte mCommandTarget; private DemoKitActivity mActivity; private TextView mLabel; private ToggleButton mButton; private Drawable mOffBackground; private Drawable mOnBackground; public RelayController(DemoKitActivity activity, int relayNumber, Resources res) { mActivity = activity; mRelayNumber = relayNumber; mCommandTarget = (byte) (relayNumber - 1); mOffBackground = res .getDrawable(R.drawable.toggle_button_off_holo_dark); mOnBackground = res.getDrawable(R.drawable.toggle_button_on_holo_dark); } public void attachToView(ViewGroup targetView) { mLabel = (TextView) targetView.getChildAt(0); SpannableStringBuilder ssb = new SpannableStringBuilder("Relay"); ssb.append(String.valueOf(mRelayNumber)); ssb.setSpan(new SubscriptSpan(), 5, 6, 0); ssb.setSpan(new RelativeSizeSpan(0.7f), 5, 6, 0); mLabel.setText(ssb); mButton = (ToggleButton) targetView.getChildAt(1); mButton.setOnCheckedChangeListener(this); } public void onCheckedChanged(CompoundButton arg0, boolean isChecked) { if (isChecked) { mButton.setBackgroundDrawable(mOnBackground); } else { mButton.setBackgroundDrawable(mOffBackground); } if (mActivity != null) { mActivity.sendCommand(DemoKitActivity.RELAY_COMMAND, mCommandTarget, isChecked ? 1 : 0); } } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/RelayController.java	Java	oos	1,858
package com.google.android.DemoKit; import android.content.Context; import android.util.AttributeSet; public class VerticalSlider extends Slider { public VerticalSlider(Context context) { super(context); initSliderView(context, true); } public VerticalSlider(Context context, AttributeSet attrs) { super(context, attrs); initSliderView(context, true); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/VerticalSlider.java	Java	oos	372
package com.google.android.DemoKit; import android.content.res.Resources; import android.view.View; public abstract class AccessoryController { protected DemoKitActivity mHostActivity; public AccessoryController(DemoKitActivity activity) { mHostActivity = activity; } protected View findViewById(int id) { return mHostActivity.findViewById(id); } protected Resources getResources() { return mHostActivity.getResources(); } void accessoryAttached() { onAccesssoryAttached(); } abstract protected void onAccesssoryAttached(); }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/AccessoryController.java	Java	oos	552
package com.google.android.DemoKit; import android.graphics.Color; import android.text.SpannableStringBuilder; import android.text.style.RelativeSizeSpan; import android.text.style.SubscriptSpan; import android.view.ViewGroup; import android.widget.TextView; public class ColorWheelLEDController implements ColorWheel.OnColorChangedListener { private DemoKitActivity mActivity; public ColorWheelLEDController(DemoKitActivity activity) { mActivity = activity; } public void colorChanged(int color) { int red = Color.red(color) / 8; int green = Color.green(color) / 8; int blue = Color.blue(color) / 8; mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)0,(byte)red); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)1,(byte)green); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)2,(byte)blue); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)3,(byte)red); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)4,(byte)green); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)5,(byte)blue); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)6,(byte)red); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)7,(byte)green); mActivity.sendCommand(DemoKitActivity.LED_SERVO_COMMAND,(byte)8,(byte)blue); } }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/src/com/google/android/DemoKit/ColorWheelLEDController.java	Java	oos	1,362
# # Copyright (C) 2011 The Android Open Source Project # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # LOCAL_PATH:= $(call my-dir) include $(CLEAR_VARS) LOCAL_MODULE_TAGS := tests LOCAL_SRC_FILES := $(call all-subdir-java-files) LOCAL_PACKAGE_NAME := DemoKit LOCAL_JAVA_LIBRARIES := com.android.future.usb.accessory include $(BUILD_PACKAGE)	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/app/Android.mk	Makefile	oos	848
{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf350 {\fonttbl\f0\fnil\fcharset0 Verdana;} {\colortbl;\red255\green255\blue255;\red191\green191\blue191;} \margl1440\margr1440\vieww19000\viewh10420\viewkind0 \deftab720 \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrt\brdrnil \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clmgf \clvertalc \clshdrawnil \clwWidth5940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clmrg \clvertalc \clshdrawnil \clwWidth5940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \f0\fs20 \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PCBA,MEGAARDUINO REV 02\cell \pard\intbl\itap1\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clmgf \clvertalc \clshdrawnil \clwWidth5940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clmrg \clvertalc \clshdrawnil \clwWidth5940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 The Android Open Source Project\cell \pard\intbl\itap1\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Copyright (C) 2011\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ID\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Description\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Quantity\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Ref Des\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MFG\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MFG P/N\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Notes\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PCB, ASHIELD, MEGAARDUINO_REDUCED\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CERM .1UF 10% 16V X7R 0603\cell \pard\intbl\itap1\pardeftab720\qr \cf0 4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C1,C2,C3,C4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 AVX\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 0603YC104KAT2A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 22UF 10V Y5V 1206\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TDK\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C3216Y5V1A226Z\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODE SWITCH LL 250V SOD-323\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 D1,D2,D3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ON SEMI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 BAS21AHT1G\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODE SCHOTTKY 20V 3A SMB\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 D4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODES INC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 B320B-13-F\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN HEADER 1x6 .100 STR 15AU\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 J1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FCI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 68000-206HLF\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MOUNTS ON BACK SIDE\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 7\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN HEADER 1x8 .100 STR 15AU\cell \pard\intbl\itap1\pardeftab720\qr \cf0 5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 J2,J3,J4,J5,J6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FCI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 68001-208HLF\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MOUNTS ON BACK SIDE\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 8\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SW NAV JOYSTICK MOD CONTACTLESS\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 JOY1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 AUSTRIAMICROSYSTEMS\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N50P111\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 9\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RELAY PWR SPDT 1A 5VDC PCB\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 K1, K2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TE CONNECTIVITY\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TSC-105L3H,000\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clmgf \clvertalc \clshdrawnil \clwWidth6240\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clmrg \clvertalc \clshdrawnil \clwWidth6240\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 10\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LED RED/GREEN/BLUE PLCC4 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LED1,LED2,LED3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CREE\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CLV1A-FKB-CJ1M1F1BB7R4S3\cell \pard\intbl\itap1\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 11\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LED INGAN GREEN CLEAR 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LED4,LED5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIALIGHT\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 598-8081-107F\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \ul \ulc0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 \ulnone 12\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC SENSOR PHOTO ILLUMINANCE SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LS1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TOSHIBA\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TPS852(T)\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 13\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MOSFET N-CH 50V 173MA SOT-23\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Q1,Q2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 NXP\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 BSN20,215\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 14\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TRANS NPN 40V 600MA SOT23\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Q3,Q4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 NXP\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MMBT2222A,215\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 15\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 1.0K OHM 1/10W 5% 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R1,R2,R3,R4,R18,R19\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-3GEYJ102V\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 16\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 91 OHM 1/10W 5% 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R10,R11,R13,R14,R16,R17\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-3GEYJ910V\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clheight240 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clheight240 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clheight240 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clheight240 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clheight240 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clheight240 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clheight240 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 17\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 51K OHM 1/10W 5% 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R20\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-3GEYJ513V\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 18\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 10M OHM 5% 1/10W 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R21\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-3GEYJ106V\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 19\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 4.7K OHM 1/10W 5% 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R5,R6,R7,R8,R22\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-3GEYJ472V\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 20\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 150 OHM 1/10W 5% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R9,R12,R15\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-3GEYJ151V\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 21\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SWITCH TACT 6MM 160GF H=4.3MM\cell \pard\intbl\itap1\pardeftab720\qr \cf0 4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 S1,S2,S3,S4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 OMRON\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 B3S-1000P\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 22\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN HEADER 3X 1x3 .100" STR GOLD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SC1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MOLEX\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 90120-0763\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LOADED SIDE BY SIDE\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 23\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC SENSOR THERMAL 3.1V TO-92-3\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TS1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MICROCHIP TECH\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MCP9701A-E/TO\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 24\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TERM BLOCK 6POS SIDE ENT 3.5MM\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 X2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TE CONNECTIVITY\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 284391-6\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 25\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DOC, SCHEMATIC, ASHIELD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 26\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DOC, ASSY INSTRUCTIONS\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrt\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth260\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4700\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth1020\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2580\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth3180\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth2840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 27\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DOC, GERBER PACKAGE\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \lastrow\row }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/hardware/eng/shield/Ashield BOM rev 02.rtf	Rich Text Format	oos	63,843
{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf350 {\fonttbl\f0\fnil\fcharset0 Verdana;} {\colortbl;\red255\green255\blue255;\red191\green191\blue191;} \paperw15840\paperh12240\margl1440\margr1440\vieww25100\viewh15040\viewkind0 \deftab720 \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrt\brdrnil \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \f0\fs20 \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PCBA, MEGA2560 Bill of Materials rev 01\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 The Android Open Source Project\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Copyright (C) 2011\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ID\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Description\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 QTY\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Ref Des\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MFG\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MFG P/N\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Notes\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PCB, MEGA2560\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN HEADER FEMALE 8POS .1" GOLD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ADCH, ADCL, COMMUNICATION, PWMH, PWML\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SULLINS\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PPPC081LFBN-RC\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER .47UF 50V X7R 20% 0603\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TDK\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C1608X7R1H474M\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 100PF 50V 5% C0G 0402\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C10\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MURATA\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 GRM1555C1H101JZ01D\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 4.7PF 50V C0G 0402\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C12, C13\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TDK\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C1005C0G1H4R7B\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 1.0UF 10V X7R 10% 0603\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C18, C34, C35\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 AVX\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 0603YC105KAT2A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 7\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP 22UF 50V ELECT HD SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 EEE-HD1H220P\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 8\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 13PF 50V C0G 0402\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C27, C28\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TDK\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C1005C0G1H130J\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 9\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 4.7UF 50V X5R 1206\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 KEMET\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C1206C475K5PACTU\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 10\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER .22UF 50V X7R 0603\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MURATA\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 GCM188R71H224KA64D\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 11\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 470PF 50V X7R 10% 0402\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TDK\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C1005X7R1H471K\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 12\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER 22UF 6.3V X5R 1206\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TAIYO YUDEN\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 JMK316BJ226KL-T\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 13\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CERAMIC .01UF 50V X7R 0402\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C7, C24\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 YAGEO\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CC0402KRX7R9BB103\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 14\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CAP CER .1UF 16V X7R 0402\cell \pard\intbl\itap1\pardeftab720\qr \cf0 19\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 C8, C9, C11, C14, C15, C16, C17, C19, C20, C21, C22, C23, C25, C26, C29, C30, C31, C32, C33\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MURATA\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 GRM155R71C104KA88D\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 15\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN RCPT 5POS MICRO USB R/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 COMPUTER\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MOLEX\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 47346-0001\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 16\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODE SCHOTTKY 3A 100V SMB\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 D1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MICRO COMMERCIAL\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SK310B-TP\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 17\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODE SCHOTTKY 2A 40V PWRDI 123\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 D2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODES INC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DFLS240L-7\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 18\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODE SW DUAL 75V 200MW SC70-3\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 D3, D4, D5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DIODES INC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 BAV99W-7-F\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 19\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN POWER JACK 2.1MM PCB\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DC_IN\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CUI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PJ-202A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 20\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FUSE PTC RESETTABLE SMD 0805\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 F1, F2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 BOURNS\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MF-PSMF050X-2\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 21\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FERRITE 700MA 120 OHM 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FB1, FB2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LAIRD\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LI0603G121R-10\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 22\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LED YELLOW CLEAR THIN 0603 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 L, RX, TX\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LITE ON\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LTST-C191KSKT\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 23\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 INDUCTOR SHIELD PWR 6.8UH SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 L1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 COILTRONICS\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DR74-6R8-R\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 24\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LED GREEN RECT CLEAR 0603\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ON\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LITE ON\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LTST-C194KGKT\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 25\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN RCPT USB TYPE A R/A PCB\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PHONE\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FCI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 87520-0010BLF\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 26\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN HEADER FEMALE 6POS .1" GOLD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 POWER\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SULLINS\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PPPC061LFBN-RC\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 27\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 16.2K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R1, R2, R3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF1622X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 28\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 11.0K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R10, R11, R19, R29\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF1102X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 29\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 100 OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R14\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF1000X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 30\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 33.0 OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 6\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R15, R23, R24, R22, R27, R28\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF33R0X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 31\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 5.90K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R20\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF5901X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 32\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 4.70K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R21, R25, R26, R30\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF4701X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 33\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 536K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF5363X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 34\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 1.00K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 7\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R5, R6, R9, R12, R16, R17, R18\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF1001X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 35\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 100K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R7\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF1003X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 36\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RES 40.2K OHM 1/10W 1% 0402 SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 R8\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PANASONIC\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ERJ-2RKF4022X\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 37\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SWITCH TACT 6MM SMD MOM 160GF\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 RESET\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 OMRON\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 B3S-1000\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 38\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MOSFET P-CH 20V 2A SSOT3\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 T1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FAIRCHILD\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FDN340P\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 39\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC REG 2A STP DWN 10-DFN\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LINEAR TECH\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LT3480EDD#PBF\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 40\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC USB FS SERIAL UART 28-SSOP\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FTDI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 FT232RL-REEL\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 41\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC AVR MCU 256K 16MHZ 100TQFP\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U3\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ATMEL\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 ATMEGA2560-16AU\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 42\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC BUFFER SCHMIT TRIG SOT553\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U4\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SN74LVC1G17DRLR\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 43\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC LDO REG 3.3V 150MA SOT23-5\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U5\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 LP2985-33DBVR\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 44\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC VOLT-LEVEL TRANSLATOR 14TSSOP\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U6, U8\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TI\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 TXB0104PWR\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 45\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC USB PERIPH/HOST CNTRL 32TQFN\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U7\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MAXIM\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MAX3421EETJ+\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 46\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 IC USB PERIPH/HOST CNTRL 32TQFP\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 U7\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MAXIM\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 MAX3421EEHJ+\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DUAL FOOTPRINT \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 47\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CRYSTAL 16.000000 MHZ 8PF SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 X1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 NDK\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 NX5032GA-16.000000MHZ\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 48\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CRYSTAL 12.000000 MHZ 8PF SMD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 X2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 NDK\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 NX5032GA-12.000000MHZ\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 49\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 CONN HEADER FMAL 18x2 .1" DL GOLD\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 XIO\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SULLINS\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 PPPC182LFBN-RC\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 50\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 VARISTOR TVS 18V 10PF 0603\cell \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 Z1, Z2\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 AVX\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 USB0001DP\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 51\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DOC, SCHEMATIC, MEGA2560\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 52\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DOC, ASSY INSTRUCTIONS\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 53\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 DOC, GERBER PACKAGE\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrt\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth20\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth900\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth3640\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth2860\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth2800\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth8500\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 54\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 SW, STK500BOOT_V2_MEGA2560.hex\cell \pard\intbl\itap1\pardeftab720\qr \cf0 0\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\ql\qnatural \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \lastrow\row }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/hardware/eng/m256c/mega2560 BOM rev 01.rtf	Rich Text Format	oos	116,901
{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf350 {\fonttbl\f0\fnil\fcharset0 Verdana;} {\colortbl;\red255\green255\blue255;\red191\green191\blue191;} \margl1440\margr1440\vieww18680\viewh7380\viewkind0 \deftab720 \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrt\brdrnil \trbrdrl\brdrnil \trbrdrr\brdrnil \clmgf \clvertalc \clshdrawnil \clwWidth5100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clmrg \clvertalc \clshdrawnil \clwWidth5100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720 \f0\fs20 \cf0 TLA, Android ADK REV 01\cell \pard\intbl\itap1\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clmgf \clvertalc \clshdrawnil \clwWidth5100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clmrg \clvertalc \clshdrawnil \clwWidth5100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720 \cf0 The Android Open Source Project\cell \pard\intbl\itap1\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clmgf \clvertalc \clshdrawnil \clwWidth5100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clmrg \clvertalc \clshdrawnil \clwWidth5100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720 \cf0 Copyright (C) 2011\cell \pard\intbl\itap1\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720 \cf0 ID\cell \pard\intbl\itap1\pardeftab720 \cf0 Description\cell \pard\intbl\itap1\pardeftab720 \cf0 Quantity\cell \pard\intbl\itap1\pardeftab720 \cf0 Ref Des\cell \pard\intbl\itap1\pardeftab720 \cf0 MFG\cell \pard\intbl\itap1\pardeftab720 \cf0 MFG P/N\cell \pard\intbl\itap1\pardeftab720 \cf0 Notes\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720 \cf0 PCBA,MEGAARDUINO REV 02\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720 \cf0 N/A\cell \pard\intbl\itap1\pardeftab720 \cf0 N/A\cell \pard\intbl\itap1\pardeftab720 \cf0 N/A\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 2\cell \pard\intbl\itap1\pardeftab720 \cf0 PCBA, MEGA2560 REV 01\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720 \cf0 N\cell \pard\intbl\itap1\pardeftab720 \cf0 N\cell \pard\intbl\itap1\pardeftab720 \cf0 N\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720 \cf0 SUB-MICRO STANDARD SERVO\cell \pard\intbl\itap1\pardeftab720\qr \cf0 3\cell \pard\intbl\itap1\pardeftab720 \cf0 N/A\cell \pard\intbl\itap1\pardeftab720 \cf0 BLUE ARROW\cell \pard\intbl\itap1\pardeftab720 \cf0 S03611\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 4\cell \pard\intbl\itap1\pardeftab720 \cf0 AC ADAPTOR, SMALL OUTLINE, AC 100-240V, 50/60HZ, 0.3A, AR021-258\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720 \cf0 N/A\cell \pard\intbl\itap1\pardeftab720 \cf0 UNIFIVE\cell \pard\intbl\itap1\pardeftab720 \cf0 UN310-1210\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clmgf \clvertalc \clshdrawnil \clwWidth8100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clmrg \clvertalc \clshdrawnil \clwWidth8100\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 5\cell \pard\intbl\itap1\pardeftab720 \cf0 USB CABLE, MICRO USB TO USB, PVC, 28AWG, L=3'\cell \pard\intbl\itap1\pardeftab720\qr \cf0 1\cell \pard\intbl\itap1\pardeftab720 \cf0 N/A\cell \pard\intbl\itap1\pardeftab720 \cf0 JESS LINK\cell \pard\intbl\itap1\pardeftab720 \cf0 ELM20110311\cell \pard\intbl\itap1\cell \row \itap1\trowd \taflags1 \trgaph108\trleft-108 \trbrdrl\brdrnil \trbrdrt\brdrnil \trbrdrr\brdrnil \clvertalc \clshdrawnil \clwWidth840\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx1234 \clvertalc \clshdrawnil \clwWidth4040\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx2468 \clvertalc \clshdrawnil \clwWidth980\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx3702 \clvertalc \clshdrawnil \clwWidth1400\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx4937 \clvertalc \clshdrawnil \clwWidth1940\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx6171 \clvertalc \clshdrawnil \clwWidth1740\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx7405 \clvertalc \clshdrawnil \clwWidth6140\clftsWidth3 \clbrdrt\brdrs\brdrw20\brdrcf2 \clbrdrl\brdrs\brdrw20\brdrcf2 \clbrdrb\brdrs\brdrw20\brdrcf2 \clbrdrr\brdrs\brdrw20\brdrcf2 \clpadl100 \clpadr100 \gaph\cellx8640 \pard\intbl\itap1\pardeftab720\qr \cf0 6\cell \pard\intbl\itap1\pardeftab720 \cf0 RUBBER FEET, CLEAR, 0.315 INCHES (8.0 MM) X 0.110 INCHES (2.8 MM) \cell \pard\intbl\itap1\pardeftab720\qr \cf0 4\cell \pard\intbl\itap1\pardeftab720 \cf0 N/A\cell \pard\intbl\itap1\pardeftab720 \cf0 3M\cell \pard\intbl\itap1\pardeftab720 \cf0 SJ5376\cell \pard\intbl\itap1\pardeftab720\qr \cf0 \cell \lastrow\row }	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/hardware/TLA, Android ADK BOM rev 01.rtf	Rich Text Format	oos	21,372
G75* G70* %OFA0B0% %FSLAX24Y24% %IPPOS% %LPD% %AMOC8* 5,1,8,0,0,1.08239X$1,22.5* % %ADD10C,0.0060% %ADD11C,0.0080% %ADD12C,0.0120% %ADD13R,0.0150X0.0007% %ADD14R,0.0225X0.0008% %ADD15R,0.0285X0.0007% %ADD16R,0.0330X0.0008% %ADD17R,0.0337X0.0008% %ADD18R,0.0375X0.0007% %ADD19R,0.0420X0.0008% %ADD20R,0.0450X0.0007% %ADD21R,0.0480X0.0008% %ADD22R,0.0510X0.0007% %ADD23R,0.0533X0.0008% %ADD24R,0.0555X0.0007% %ADD25R,0.0585X0.0008% %ADD26R,0.0600X0.0007% %ADD27R,0.0623X0.0008% %ADD28R,0.0645X0.0007% %ADD29R,0.0660X0.0008% %ADD30R,0.0675X0.0007% %ADD31R,0.0697X0.0008% %ADD32R,0.0713X0.0007% %ADD33R,0.0727X0.0008% %ADD34R,0.0743X0.0007% %ADD35R,0.0757X0.0008% %ADD36R,0.0773X0.0007% %ADD37R,0.0787X0.0008% %ADD38R,0.0795X0.0007% %ADD39R,0.0810X0.0008% %ADD40R,0.0825X0.0007% %ADD41R,0.0840X0.0008% %ADD42R,0.0847X0.0007% %ADD43R,0.0855X0.0008% %ADD44R,0.0870X0.0007% %ADD45R,0.0877X0.0008% %ADD46R,0.0885X0.0007% %ADD47R,0.0900X0.0008% %ADD48R,0.0907X0.0007% %ADD49R,0.0915X0.0008% %ADD50R,0.0923X0.0007% %ADD51R,0.0930X0.0008% %ADD52R,0.0937X0.0007% %ADD53R,0.0945X0.0008% %ADD54R,0.0953X0.0007% %ADD55R,0.0960X0.0008% %ADD56R,0.0960X0.0007% %ADD57R,0.0967X0.0007% %ADD58R,0.0975X0.0008% %ADD59R,0.0975X0.0007% %ADD60R,0.0983X0.0008% %ADD61R,0.0990X0.0007% %ADD62R,0.0990X0.0008% %ADD63R,0.0997X0.0007% %ADD64R,0.1005X0.0008% %ADD65R,0.1005X0.0007% %ADD66R,0.1013X0.0008% %ADD67R,0.1020X0.0007% %ADD68R,0.1020X0.0008% %ADD69R,0.1027X0.0008% %ADD70R,0.1027X0.0007% %ADD71R,0.1035X0.0008% %ADD72R,0.1035X0.0007% %ADD73R,0.1043X0.0008% %ADD74R,0.1043X0.0007% %ADD75R,0.1050X0.0007% %ADD76R,0.1050X0.0008% %ADD77R,0.3728X0.0007% %ADD78R,0.3802X0.0008% %ADD79R,0.3862X0.0007% %ADD80R,0.3908X0.0008% %ADD81R,0.3952X0.0007% %ADD82R,0.3998X0.0008% %ADD83R,0.4028X0.0007% %ADD84R,0.4058X0.0008% %ADD85R,0.4088X0.0007% %ADD86R,0.4118X0.0008% %ADD87R,0.4132X0.0007% %ADD88R,0.4162X0.0008% %ADD89R,0.4178X0.0007% %ADD90R,0.4208X0.0008% %ADD91R,0.4222X0.0007% %ADD92R,0.4245X0.0008% %ADD93R,0.4268X0.0007% %ADD94R,0.4282X0.0008% %ADD95R,0.4298X0.0007% %ADD96R,0.4312X0.0008% %ADD97R,0.4328X0.0007% %ADD98R,0.4342X0.0008% %ADD99R,0.4358X0.0007% %ADD100R,0.4372X0.0008% %ADD101R,0.4388X0.0007% %ADD102R,0.4402X0.0008% %ADD103R,0.4418X0.0007% %ADD104R,0.4432X0.0008% %ADD105R,0.4432X0.0007% %ADD106R,0.4448X0.0008% %ADD107R,0.4462X0.0007% %ADD108R,0.4478X0.0008% %ADD109R,0.4478X0.0007% %ADD110R,0.4492X0.0008% %ADD111R,0.4508X0.0007% %ADD112R,0.4508X0.0008% %ADD113R,0.4522X0.0007% %ADD114R,0.4522X0.0008% %ADD115R,0.4538X0.0007% %ADD116R,0.4545X0.0008% %ADD117R,0.4552X0.0007% %ADD118R,0.4560X0.0008% %ADD119R,0.4568X0.0007% %ADD120R,0.4575X0.0008% %ADD121R,0.4582X0.0007% %ADD122R,0.4582X0.0008% %ADD123R,0.4598X0.0007% %ADD124R,0.4598X0.0008% %ADD125R,0.4605X0.0007% %ADD126R,0.4612X0.0008% %ADD127R,0.4612X0.0007% %ADD128R,0.4620X0.0008% %ADD129R,0.4628X0.0007% %ADD130R,0.4628X0.0008% %ADD131R,0.4642X0.0008% %ADD132R,0.4642X0.0007% %ADD133R,0.4658X0.0008% %ADD134R,0.4658X0.0007% %ADD135R,0.4665X0.0008% %ADD136R,0.4672X0.0007% %ADD137R,0.4672X0.0008% %ADD138R,0.0128X0.0007% %ADD139R,0.0218X0.0008% %ADD140R,0.0278X0.0007% %ADD141R,0.0322X0.0008% %ADD142R,0.0368X0.0007% %ADD143R,0.0405X0.0008% %ADD144R,0.0412X0.0008% %ADD145R,0.0442X0.0007% %ADD146R,0.0472X0.0008% %ADD147R,0.0502X0.0007% %ADD148R,0.0532X0.0008% %ADD149R,0.0548X0.0007% %ADD150R,0.0578X0.0008% %ADD151R,0.0592X0.0007% %ADD152R,0.0622X0.0008% %ADD153R,0.0638X0.0007% %ADD154R,0.0652X0.0008% %ADD155R,0.0698X0.0008% %ADD156R,0.0712X0.0007% %ADD157R,0.0728X0.0008% %ADD158R,0.0742X0.0007% %ADD159R,0.0758X0.0008% %ADD160R,0.0772X0.0007% %ADD161R,0.0788X0.0008% %ADD162R,0.0818X0.0007% %ADD163R,0.0832X0.0008% %ADD164R,0.0848X0.0007% %ADD165R,0.0862X0.0007% %ADD166R,0.0878X0.0008% %ADD167R,0.0892X0.0008% %ADD168R,0.0908X0.0007% %ADD169R,0.0908X0.0008% %ADD170R,0.0922X0.0007% %ADD171R,0.0938X0.0007% %ADD172R,0.0952X0.0007% %ADD173R,0.0952X0.0008% %ADD174R,0.0968X0.0007% %ADD175R,0.0968X0.0008% %ADD176R,0.0982X0.0008% %ADD177R,0.0982X0.0007% %ADD178R,0.0998X0.0008% %ADD179R,0.0998X0.0007% %ADD180R,0.1012X0.0008% %ADD181R,0.1012X0.0007% %ADD182R,0.1028X0.0007% %ADD183R,0.1028X0.0008% %ADD184R,0.1042X0.0007% %ADD185R,0.1042X0.0008% %ADD186R,0.0802X0.0007% %ADD187R,0.0682X0.0007% %ADD188R,0.0142X0.0007% %ADD189R,0.4710X0.0007% %ADD190R,0.4710X0.0008% %ADD191R,0.4702X0.0008% %ADD192R,0.4702X0.0007% %ADD193R,0.4695X0.0008% %ADD194R,0.4695X0.0007% %ADD195R,0.4688X0.0007% %ADD196R,0.4688X0.0008% %ADD197R,0.4680X0.0008% %ADD198R,0.4680X0.0007% %ADD199R,0.4665X0.0007% %ADD200R,0.4650X0.0008% %ADD201R,0.4635X0.0007% %ADD202R,0.4590X0.0007% %ADD203R,0.4575X0.0007% %ADD204R,0.4568X0.0008% %ADD205R,0.4552X0.0008% %ADD206R,0.4538X0.0008% %ADD207R,0.4530X0.0007% %ADD208R,0.4515X0.0008% %ADD209R,0.4500X0.0007% %ADD210R,0.4492X0.0007% %ADD211R,0.4485X0.0008% %ADD212R,0.4470X0.0007% %ADD213R,0.4462X0.0008% %ADD214R,0.4455X0.0008% %ADD215R,0.4448X0.0007% %ADD216R,0.4425X0.0007% %ADD217R,0.4418X0.0008% %ADD218R,0.4402X0.0007% %ADD219R,0.4395X0.0008% %ADD220R,0.4380X0.0008% %ADD221R,0.4372X0.0007% %ADD222R,0.4358X0.0008% %ADD223R,0.4350X0.0007% %ADD224R,0.4335X0.0007% %ADD225R,0.4328X0.0008% %ADD226R,0.2048X0.0007% %ADD227R,0.2002X0.0008% %ADD228R,0.1972X0.0007% %ADD229R,0.1942X0.0008% %ADD230R,0.1912X0.0007% %ADD231R,0.1898X0.0008% %ADD232R,0.1882X0.0007% %ADD233R,0.0923X0.0008% %ADD234R,0.1868X0.0008% %ADD235R,0.0915X0.0007% %ADD236R,0.1852X0.0007% %ADD237R,0.1838X0.0008% %ADD238R,0.0900X0.0007% %ADD239R,0.1822X0.0007% %ADD240R,0.0893X0.0007% %ADD241R,0.0885X0.0008% %ADD242R,0.1822X0.0008% %ADD243R,0.0878X0.0007% %ADD244R,0.1808X0.0007% %ADD245R,0.0870X0.0008% %ADD246R,0.1792X0.0008% %ADD247R,0.1792X0.0007% %ADD248R,0.0855X0.0007% %ADD249R,0.1778X0.0008% %ADD250R,0.0840X0.0007% %ADD251R,0.1778X0.0007% %ADD252R,0.0833X0.0007% %ADD253R,0.1762X0.0007% %ADD254R,0.0825X0.0008% %ADD255R,0.1762X0.0008% %ADD256R,0.0817X0.0007% %ADD257R,0.0817X0.0008% %ADD258R,0.0810X0.0007% %ADD259R,0.1748X0.0007% %ADD260R,0.0802X0.0008% %ADD261R,0.1748X0.0008% %ADD262R,0.0795X0.0008% %ADD263R,0.0787X0.0007% %ADD264R,0.0780X0.0007% %ADD265R,0.0780X0.0008% %ADD266R,0.0765X0.0008% %ADD267R,0.0765X0.0007% %ADD268R,0.0758X0.0007% %ADD269R,0.0757X0.0007% %ADD270R,0.0750X0.0008% %ADD271R,0.1800X0.0007% %ADD272R,0.1808X0.0008% %ADD273R,0.0750X0.0007% %ADD274R,0.1838X0.0007% %ADD275R,0.1852X0.0008% %ADD276R,0.1868X0.0007% %ADD277R,0.1882X0.0008% %ADD278R,0.1898X0.0007% %ADD279R,0.1928X0.0008% %ADD280R,0.1942X0.0007% %ADD281R,0.1972X0.0008% %ADD282R,0.2018X0.0007% %ADD283R,0.0818X0.0008% %ADD284R,0.2078X0.0008% %ADD285R,0.3840X0.0007% %ADD286R,0.3832X0.0008% %ADD287R,0.3818X0.0007% %ADD288R,0.3788X0.0007% %ADD289R,0.3780X0.0008% %ADD290R,0.3772X0.0007% %ADD291R,0.3758X0.0008% %ADD292R,0.3742X0.0007% %ADD293R,0.3728X0.0008% %ADD294R,0.3720X0.0007% %ADD295R,0.3705X0.0008% %ADD296R,0.3698X0.0007% %ADD297R,0.3682X0.0008% %ADD298R,0.3668X0.0007% %ADD299R,0.3652X0.0008% %ADD300R,0.3638X0.0007% %ADD301R,0.3622X0.0008% %ADD302R,0.3608X0.0007% %ADD303R,0.3600X0.0008% %ADD304R,0.3585X0.0007% %ADD305R,0.3570X0.0008% %ADD306R,0.3555X0.0007% %ADD307R,0.3548X0.0008% %ADD308R,0.3532X0.0007% %ADD309R,0.3518X0.0008% %ADD310R,0.3502X0.0007% %ADD311R,0.3488X0.0008% %ADD312R,0.3472X0.0007% %ADD313R,0.3458X0.0008% %ADD314R,0.3442X0.0007% %ADD315R,0.3428X0.0008% %ADD316R,0.3412X0.0007% %ADD317R,0.3398X0.0008% %ADD318R,0.3375X0.0007% %ADD319R,0.3360X0.0008% %ADD320R,0.3345X0.0007% %ADD321R,0.3330X0.0008% %ADD322R,0.3308X0.0007% %ADD323R,0.3292X0.0008% %ADD324R,0.3278X0.0007% %ADD325R,0.3262X0.0008% %ADD326R,0.3248X0.0007% %ADD327R,0.3232X0.0008% %ADD328R,0.3210X0.0007% %ADD329R,0.3188X0.0008% %ADD330R,0.3172X0.0007% %ADD331R,0.3158X0.0008% %ADD332R,0.3142X0.0007% %ADD333R,0.3120X0.0008% %ADD334R,0.3098X0.0007% %ADD335R,0.3082X0.0008% %ADD336R,0.3068X0.0007% %ADD337R,0.3045X0.0008% %ADD338R,0.3022X0.0007% %ADD339R,0.3008X0.0008% %ADD340R,0.2985X0.0007% %ADD341R,0.2962X0.0008% %ADD342R,0.2948X0.0007% %ADD343R,0.2925X0.0008% %ADD344R,0.2902X0.0007% %ADD345R,0.2888X0.0008% %ADD346R,0.2858X0.0007% %ADD347R,0.2842X0.0008% %ADD348R,0.2820X0.0007% %ADD349R,0.2798X0.0008% %ADD350R,0.2775X0.0007% %ADD351R,0.2752X0.0008% %ADD352R,0.2730X0.0007% %ADD353R,0.2708X0.0008% %ADD354R,0.2678X0.0007% %ADD355R,0.2662X0.0008% %ADD356R,0.2632X0.0007% %ADD357R,0.2610X0.0008% %ADD358R,0.2588X0.0007% %ADD359R,0.2558X0.0008% %ADD360R,0.2535X0.0007% %ADD361R,0.2512X0.0008% %ADD362R,0.2482X0.0007% %ADD363R,0.2452X0.0008% %ADD364R,0.2430X0.0007% %ADD365R,0.2408X0.0008% %ADD366R,0.2378X0.0007% %ADD367R,0.2348X0.0008% %ADD368R,0.2318X0.0007% %ADD369R,0.2318X0.0008% %ADD370R,0.2332X0.0008% %ADD371R,0.2348X0.0007% %ADD372R,0.2362X0.0007% %ADD373R,0.2362X0.0008% %ADD374R,0.2205X0.0008% %ADD375R,0.0165X0.0008% %ADD376R,0.0172X0.0007% %ADD377R,0.2002X0.0007% %ADD378R,0.0173X0.0007% %ADD379R,0.1935X0.0007% %ADD380R,0.0172X0.0008% %ADD381R,0.1860X0.0007% %ADD382R,0.0165X0.0007% %ADD383R,0.0173X0.0008% %ADD384R,0.1740X0.0008% %ADD385R,0.1702X0.0007% %ADD386R,0.1658X0.0008% %ADD387R,0.1612X0.0007% %ADD388R,0.1568X0.0008% %ADD389R,0.1522X0.0007% %ADD390R,0.1470X0.0008% %ADD391R,0.1418X0.0007% %ADD392R,0.1365X0.0008% %ADD393R,0.1312X0.0007% %ADD394R,0.1252X0.0008% %ADD395R,0.1192X0.0007% %ADD396R,0.1132X0.0008% %ADD397R,0.1058X0.0007% %ADD398R,0.0720X0.0007% %ADD399R,0.0608X0.0008% %ADD400R,0.0458X0.0007% %ADD401R,0.0240X0.0008% %ADD402R,0.0157X0.0008% %ADD403R,0.0157X0.0007% %ADD404R,0.0150X0.0008% %ADD405R,0.0142X0.0008% %ADD406R,0.0128X0.0008% %ADD407R,0.0112X0.0007% %ADD408R,0.0098X0.0008% %ADD409R,0.0075X0.0007% %ADD410R,0.0038X0.0008% %ADD411R,0.1120X0.0020% %ADD412R,0.0640X0.0020% %ADD413R,0.0160X0.0020% %ADD414R,0.0320X0.0020% %ADD415R,0.0480X0.0020% %ADD416R,0.0800X0.0020% %ADD417R,0.1440X0.0020% %ADD418R,0.0960X0.0020% %ADD419R,0.1280X0.0020% %ADD420R,0.1600X0.0020% D10 X001091Y008247D02* X001034Y008304D01* X001034Y008417D01* X001091Y008474D01* X001317Y008474D01* X001374Y008417D01* X001374Y008304D01* X001317Y008247D01* X001091Y008247D01* X001034Y008616D02* X001034Y008786D01* X001091Y008842D01* X001204Y008842D01* X001261Y008786D01* X001261Y008616D01* X000921Y008616D01* X001091Y008984D02* X001204Y008984D01* X001261Y009041D01* X001261Y009154D01* X001204Y009211D01* X001147Y009211D01* X001147Y008984D01* X001091Y008984D02* X001034Y009041D01* X001034Y009154D01* X001034Y009352D02* X001261Y009352D01* X001261Y009522D01* X001204Y009579D01* X001034Y009579D01* X001091Y010089D02* X001034Y010145D01* X001034Y010259D01* X001091Y010316D01* X001147Y010316D01* X001204Y010259D01* X001204Y010145D01* X001261Y010089D01* X001317Y010089D01* X001374Y010145D01* X001374Y010259D01* X001317Y010316D01* X001204Y010457D02* X001091Y010457D01* X001034Y010514D01* X001034Y010627D01* X001091Y010684D01* X001204Y010684D01* X001261Y010627D01* X001261Y010514D01* X001204Y010457D01* X001261Y010825D02* X001091Y010825D01* X001034Y010882D01* X001034Y011052D01* X001261Y011052D01* X001261Y011194D02* X001034Y011194D01* X001147Y011194D02* X001261Y011307D01* X001261Y011364D01* X001204Y011501D02* X001091Y011501D01* X001034Y011557D01* X001034Y011727D01* X001091Y011869D02* X001204Y011869D01* X001261Y011926D01* X001261Y012039D01* X001204Y012096D01* X001147Y012096D01* X001147Y011869D01* X001091Y011869D02* X001034Y011926D01* X001034Y012039D01* X001261Y011727D02* X001261Y011557D01* X001204Y011501D01* X001784Y011566D02* X001954Y011566D01* X002011Y011509D01* X002011Y011339D01* X001784Y011339D01* X001784Y011197D02* X002011Y011197D01* X002124Y011084D01* X002011Y010970D01* X001784Y010970D01* X001954Y010970D02* X001954Y011197D01* X002534Y011118D02* X002704Y011118D01* X002761Y011061D01* X002761Y010948D01* X002704Y010891D01* X002761Y010750D02* X002477Y010750D01* X002421Y010693D01* X002421Y010636D01* X002534Y010580D02* X002534Y010750D01* X002534Y010891D02* X002874Y010891D01* X002761Y010750D02* X002761Y010580D01* X002704Y010523D01* X002591Y010523D01* X002534Y010580D01* X002534Y010391D02* X002534Y010277D01* X002534Y010334D02* X002761Y010334D01* X002761Y010277D01* X002874Y010334D02* X002931Y010334D01* X002761Y010141D02* X002761Y010084D01* X002647Y009970D01* X002534Y009970D02* X002761Y009970D01* X002761Y009829D02* X002477Y009829D01* X002421Y009772D01* X002421Y009716D01* X002534Y009659D02* X002534Y009829D01* X002534Y009659D02* X002591Y009602D01* X002761Y009602D01* X002704Y009461D02* X002591Y009461D01* X002534Y009404D01* X002534Y009234D01* X002421Y009234D02* X002761Y009234D01* X002761Y009404D01* X002704Y009461D01* X002704Y009092D02* X002761Y009036D01* X002761Y008922D01* X002704Y008866D01* X002591Y008866D01* X002534Y008922D01* X002534Y009036D01* X002591Y009092D01* X002704Y009092D01* X002124Y009497D02* X002124Y009724D01* X002124Y009611D02* X001784Y009611D01* X001784Y009866D02* X002124Y009866D01* X002011Y009922D02* X002011Y010036D01* X001954Y010092D01* X001784Y010092D01* X001841Y010234D02* X001954Y010234D01* X002011Y010291D01* X002011Y010404D01* X001954Y010461D01* X001897Y010461D01* X001897Y010234D01* X001841Y010234D02* X001784Y010291D01* X001784Y010404D01* X002011Y009922D02* X001954Y009866D01* X002591Y008724D02* X002534Y008667D01* X002534Y008554D01* X002591Y008497D01* X002817Y008497D01* X002874Y008554D01* X002874Y008667D01* X002817Y008724D01* X002761Y011259D02* X002761Y011373D01* X002817Y011316D02* X002591Y011316D01* X002534Y011373D01* X002647Y011873D02* X002761Y011873D01* X002874Y011987D01* X002817Y012119D02* X002591Y012119D01* X002534Y012175D01* X002534Y012289D01* X002591Y012346D01* X002534Y012487D02* X002647Y012601D01* X002761Y012601D01* X002874Y012487D01* X002817Y012346D02* X002874Y012289D01* X002874Y012175D01* X002817Y012119D01* X002647Y011873D02* X002534Y011987D01* X002124Y011934D02* X001784Y011934D01* X001784Y011764D01* X001841Y011707D01* X001954Y011707D01* X002011Y011764D01* X002011Y011934D01* X002011Y012075D02* X001784Y012075D01* X001897Y012075D02* X002011Y012189D01* X002011Y012245D01* X001954Y012382D02* X001841Y012382D01* X001784Y012439D01* X001784Y012552D01* X001841Y012609D01* X001954Y012609D01* X002011Y012552D01* X002011Y012439D01* X001954Y012382D01* X001374Y012605D02* X001374Y012776D01* X001317Y012832D01* X001204Y012832D01* X001147Y012776D01* X001147Y012605D01* X001034Y012605D02* X001374Y012605D01* X001784Y012751D02* X001784Y012864D01* X001784Y012807D02* X002011Y012807D01* X002011Y012751D01* X002124Y012807D02* X002181Y012807D01* X001954Y012996D02* X002011Y013053D01* X002011Y013223D01* X002124Y013223D02* X001784Y013223D01* X001784Y013053D01* X001841Y012996D01* X001954Y012996D01* X002534Y013101D02* X002761Y013328D01* X002817Y013328D01* X002874Y013271D01* X002874Y013158D01* X002817Y013101D01* X002534Y013101D02* X002534Y013328D01* X002591Y013469D02* X002534Y013526D01* X002534Y013639D01* X002591Y013696D01* X002817Y013696D01* X002591Y013469D01* X002817Y013469D01* X002874Y013526D01* X002874Y013639D01* X002817Y013696D01* X002761Y013838D02* X002874Y013951D01* X002534Y013951D01* X002534Y013838D02* X002534Y014064D01* X002534Y014206D02* X002534Y014433D01* X002534Y014319D02* X002874Y014319D01* X002761Y014206D01* X001431Y013762D02* X001374Y013762D01* X001261Y013762D02* X000977Y013762D01* X000921Y013706D01* X000921Y013649D01* X001091Y013508D02* X001204Y013508D01* X001261Y013451D01* X001261Y013337D01* X001204Y013281D01* X001091Y013281D01* X001034Y013337D01* X001034Y013451D01* X001091Y013508D01* X001091Y013894D02* X001204Y013894D01* X001261Y013951D01* X001261Y014065D01* X001204Y014121D01* X001147Y014121D01* X001147Y013894D01* X001091Y013894D02* X001034Y013951D01* X001034Y014065D01* X001091Y014263D02* X001034Y014319D01* X001034Y014490D01* X001091Y014688D02* X001034Y014745D01* X001091Y014688D02* X001317Y014688D01* X001261Y014631D02* X001261Y014745D01* X001261Y014490D02* X001261Y014319D01* X001204Y014263D01* X001091Y014263D01* X001261Y013144D02* X001261Y013087D01* X001147Y012974D01* X001034Y012974D02* X001261Y012974D01* D11* X015227Y021132D02* X015297Y021202D01* X015297Y021482D01* X015367Y021412D02* X015227Y021412D01* X015604Y021412D02* X015604Y021132D01* X015674Y021132D02* X015534Y021132D01* X015604Y021412D02* X015674Y021412D01* X015604Y021553D02* X015604Y021623D01* X015848Y021412D02* X016058Y021272D01* X015848Y021132D01* X016058Y021132D02* X016058Y021553D01* X016238Y021342D02* X016308Y021412D01* X016448Y021412D01* X016518Y021342D01* X016518Y021202D01* X016448Y021132D01* X016308Y021132D01* X016238Y021202D01* X016238Y021342D01* X016698Y021342D02* X016698Y021132D01* X016838Y021132D02* X016838Y021342D01* X016768Y021412D01* X016698Y021342D01* X016838Y021342D02* X016908Y021412D01* X016979Y021412D01* X016979Y021132D01* X017159Y021272D02* X017439Y021272D01* X017439Y021202D02* X017439Y021342D01* X017369Y021412D01* X017229Y021412D01* X017159Y021342D01* X017159Y021272D01* X017229Y021132D02* X017369Y021132D01* X017439Y021202D01* X017619Y021132D02* X017829Y021132D01* X017899Y021202D01* X017899Y021342D01* X017829Y021412D01* X017619Y021412D01* X017619Y021553D02* X017619Y021132D01* X018079Y021553D02* X018360Y021132D01* X018540Y021132D02* X018540Y021342D01* X018610Y021412D01* X018680Y021342D01* X018680Y021132D01* X018820Y021132D02* X018820Y021412D01* X018750Y021412D01* X018680Y021342D01* X019000Y021342D02* X019000Y021202D01* X019070Y021132D01* X019210Y021132D01* X019280Y021202D01* X019280Y021342D01* X019210Y021412D01* X019070Y021412D01* X019000Y021342D01* X019460Y021412D02* X019671Y021412D01* X019741Y021342D01* X019741Y021202D01* X019671Y021132D01* X019460Y021132D01* X019901Y021132D02* X019971Y021132D01* X019971Y021202D01* X019901Y021202D01* X019901Y021132D01* X020151Y021132D02* X020361Y021132D01* X020431Y021202D01* X020431Y021342D01* X020361Y021412D01* X020151Y021412D01* X020151Y021553D02* X020151Y021132D01* X020598Y021132D02* X020738Y021132D01* X020668Y021132D02* X020668Y021412D01* X020738Y021412D01* X020668Y021553D02* X020668Y021623D01* X020918Y021342D02* X020988Y021412D01* X021128Y021412D01* X021198Y021342D01* X021198Y021202D01* X021128Y021132D01* X020988Y021132D01* X020918Y021202D01* X020918Y021342D01* X021372Y021412D02* X021442Y021412D01* X021582Y021272D01* X021582Y021132D02* X021582Y021412D01* X021762Y021412D02* X021972Y021412D01* X022042Y021342D01* X022042Y021202D01* X021972Y021132D01* X021762Y021132D01* X021762Y021553D01* X022222Y021342D02* X022222Y021132D01* X022222Y021342D02* X022293Y021412D01* X022503Y021412D01* X022503Y021132D01* X022683Y021132D02* X022893Y021132D01* X022963Y021202D01* X022893Y021272D01* X022683Y021272D01* X022683Y021342D02* X022683Y021132D01* X022683Y021342D02* X022753Y021412D01* X022893Y021412D01* X023123Y021202D02* X023123Y021132D01* X023193Y021132D01* X023193Y021202D01* X023123Y021202D01* X023373Y021132D02* X023373Y021342D01* X023443Y021412D01* X023584Y021412D01* X023584Y021272D02* X023373Y021272D01* X023373Y021132D02* X023584Y021132D01* X023654Y021202D01* X023584Y021272D01* X023834Y021553D02* X024114Y021132D01* X024294Y021553D02* X024574Y021132D01* X024734Y021132D02* X024804Y021132D01* X024804Y021202D01* X024734Y021202D01* X024734Y021132D01* X024734Y021342D02* X024804Y021342D01* X024804Y021412D01* X024734Y021412D01* X024734Y021342D01* X024985Y021342D02* X024985Y021202D01* X025055Y021132D01* X025265Y021132D01* X025265Y020992D02* X025265Y021412D01* X025055Y021412D01* X024985Y021342D01* X025432Y021412D02* X025572Y021412D01* X025502Y021482D02* X025502Y021202D01* X025432Y021132D01* X025738Y021132D02* X025809Y021202D01* X025809Y021482D01* X025879Y021412D02* X025738Y021412D01* X026059Y021342D02* X026059Y021132D01* X026059Y021342D02* X026129Y021412D01* X026269Y021412D01* X026339Y021342D01* X026339Y021132D02* X026339Y021553D01* D12* X024566Y009405D02* X023941Y009405D01* X023941Y008780D01* X023941Y007530D02* X023941Y006905D01* X024566Y006905D01* X035816Y006905D02* X036441Y006905D01* X036441Y007530D01* X036441Y008780D02* X036441Y009092D01* X036129Y009405D01* X035816Y009405D01* D13* X018053Y006842D03* X019800Y006842D03* X020378Y015242D03* X017475Y015242D03* D14* X015870Y012550D03* X021983Y012550D03* X019800Y006850D03* X018053Y006850D03* D15* X018053Y006857D03* X019800Y006857D03* X021983Y012542D03* X015870Y012542D03* D16* X015870Y012535D03* X021983Y012535D03* X019800Y006865D03* D17* X018049Y006865D03* D18* X018053Y006872D03* X019800Y006872D03* X021983Y012527D03* X015870Y012527D03* D19* X018053Y006880D03* X019800Y006880D03* D20* X019800Y006887D03* X018053Y006887D03* D21* X018053Y006895D03* X019800Y006895D03* D22* X019800Y006902D03* X018053Y006902D03* D23* X018049Y006910D03* X019804Y006910D03* D24* X019800Y006917D03* X018053Y006917D03* X015870Y012482D03* X021983Y012482D03* D25* X019800Y006925D03* X018053Y006925D03* D26* X018053Y006932D03* X019800Y006932D03* X021983Y012467D03* X015870Y012467D03* D27* X018049Y006940D03* X019804Y006940D03* D28* X019800Y006947D03* X018053Y006947D03* D29* X018053Y006955D03* X019800Y006955D03* X021983Y012445D03* X015870Y012445D03* D30* X015870Y009452D03* X021983Y009452D03* X019800Y006962D03* X018053Y006962D03* D31* X018049Y006970D03* X019804Y006970D03* D32* X019804Y006977D03* X018049Y006977D03* D33* X018049Y006985D03* X019804Y006985D03* D34* X019804Y006992D03* X018049Y006992D03* D35* X018049Y007000D03* X019804Y007000D03* X020554Y013780D03* X020539Y013795D03* X017314Y013795D03* D36* X017374Y013862D03* X018049Y007007D03* X019804Y007007D03* D37* X019804Y007015D03* X018049Y007015D03* X017269Y013705D03* X020584Y013705D03* D38* X020588Y013697D03* X020460Y013877D03* X017393Y013877D03* X015870Y009512D03* X021983Y009512D03* X019800Y007022D03* X018053Y007022D03* D39* X018053Y007030D03* X019800Y007030D03* X021983Y009520D03* X015870Y009520D03* X015870Y012370D03* X017258Y013660D03* X021983Y012370D03* D40* X021983Y012362D03* X019800Y007037D03* X018053Y007037D03* D41* X018053Y007045D03* X019800Y007045D03* X020603Y013630D03* X017250Y013630D03* D42* X018049Y007052D03* X019804Y007052D03* D43* X019800Y007060D03* X018053Y007060D03* X015870Y009550D03* X021983Y009550D03* X021983Y012340D03* X020603Y013615D03* X017250Y013615D03* X015870Y012340D03* D44* X017250Y013592D03* X018053Y007067D03* X019800Y007067D03* D45* X019804Y007075D03* X018049Y007075D03* D46* X018053Y007082D03* X019800Y007082D03* X021983Y009572D03* X015870Y009572D03* X015870Y012317D03* X021983Y012317D03* D47* X020603Y013570D03* X017250Y013570D03* X018053Y007090D03* X019800Y007090D03* D48* X019804Y007097D03* X018049Y007097D03* D49* X018053Y007105D03* X019800Y007105D03* X021983Y012295D03* X015870Y012295D03* D50* X018049Y007112D03* X019804Y007112D03* D51* X019800Y007120D03* X018053Y007120D03* X015870Y009610D03* X021983Y009610D03* X021983Y012280D03* X015870Y012280D03* D52* X017254Y013547D03* X020599Y013547D03* X019804Y007127D03* X018049Y007127D03* D53* X018053Y007135D03* X019800Y007135D03* X021983Y009625D03* X015870Y009625D03* X015870Y012265D03* X017258Y013540D03* X020595Y013540D03* X021983Y012265D03* D54* X019804Y007142D03* X018049Y007142D03* D55* X018053Y007150D03* X019800Y007150D03* X021983Y012250D03* X015870Y012250D03* D56* X019800Y007157D03* D57* X018049Y007157D03* D58* X018053Y007165D03* X019800Y007165D03* X020588Y013525D03* X017265Y013525D03* D59* X015870Y012227D03* X021983Y012227D03* X021983Y009662D03* X015870Y009662D03* X018053Y007172D03* X019800Y007172D03* D60* X019804Y007180D03* X018049Y007180D03* D61* X018053Y007187D03* X019800Y007187D03* X017273Y013517D03* D62* X018053Y007195D03* X019800Y007195D03* D63* X019804Y007202D03* X018049Y007202D03* X020584Y013517D03* D64* X019800Y007210D03* X018053Y007210D03* D65* X018053Y007217D03* X019800Y007217D03* X021983Y009707D03* X015870Y009707D03* X015870Y012182D03* X021983Y012182D03* D66* X019804Y007225D03* X018049Y007225D03* D67* X018053Y007232D03* X018053Y007247D03* X019800Y007247D03* X019800Y007232D03* D68* X019800Y007240D03* X018053Y007240D03* X015870Y009730D03* X021983Y009730D03* X021983Y012160D03* X015870Y012160D03* D69* X018049Y007255D03* X019804Y007255D03* D70* X019804Y007262D03* X018049Y007262D03* D71* X018053Y007270D03* X018053Y007285D03* X019800Y007285D03* X019800Y007270D03* X021983Y009775D03* X015870Y009775D03* X015870Y012115D03* X021983Y012115D03* D72* X021983Y012122D03* X015870Y012122D03* X015870Y009767D03* X021983Y009767D03* X019800Y007292D03* X019800Y007277D03* X018053Y007277D03* X018053Y007292D03* D73* X018049Y007300D03* X018049Y007315D03* X019804Y007315D03* X019804Y007300D03* D74* X019804Y007307D03* X018049Y007307D03* D75* X018053Y007322D03* X018053Y007337D03* X018053Y007352D03* X018053Y007367D03* X018053Y007382D03* X018053Y007397D03* X018053Y007412D03* X018053Y007427D03* X018053Y007442D03* X018053Y007457D03* X018053Y007472D03* X018053Y007487D03* X018053Y007502D03* X018053Y007517D03* X018053Y007532D03* X018053Y007547D03* X018053Y007562D03* X018053Y007577D03* X018053Y007592D03* X018053Y007607D03* X018053Y007622D03* X018053Y007637D03* X018053Y007652D03* X018053Y007667D03* X018053Y007682D03* X018053Y007697D03* X018053Y007712D03* X018053Y007727D03* X018053Y007742D03* X018053Y007757D03* X018053Y007772D03* X018053Y007787D03* X018053Y007802D03* X018053Y007817D03* X018053Y007832D03* X018053Y007847D03* X018053Y007862D03* X018053Y007877D03* X018053Y007892D03* X018053Y007907D03* X018053Y007922D03* X018053Y007937D03* X018053Y007952D03* X018053Y007967D03* X018053Y007982D03* X018053Y007997D03* X018053Y008012D03* X018053Y008027D03* X018053Y008042D03* X018053Y008057D03* X018053Y008072D03* X018053Y008087D03* X018053Y008102D03* X018053Y008117D03* X018053Y008132D03* X018053Y008147D03* X018053Y008162D03* X018053Y008177D03* X018053Y008192D03* X018053Y008207D03* X018053Y008222D03* X018053Y008237D03* X018053Y008252D03* X018053Y008267D03* X018053Y008282D03* X018053Y008297D03* X018053Y008312D03* X018053Y008327D03* X018053Y008342D03* X018053Y008357D03* X018053Y008372D03* X018053Y008387D03* X018053Y008402D03* X018053Y008417D03* X018053Y008432D03* X018053Y008447D03* X018053Y008462D03* X018053Y008477D03* X018053Y008492D03* X018053Y008507D03* X019800Y008507D03* X019800Y008492D03* X019800Y008477D03* X019800Y008462D03* X019800Y008447D03* X019800Y008432D03* X019800Y008417D03* X019800Y008402D03* X019800Y008387D03* X019800Y008372D03* X019800Y008357D03* X019800Y008342D03* X019800Y008327D03* X019800Y008312D03* X019800Y008297D03* X019800Y008282D03* X019800Y008267D03* X019800Y008252D03* X019800Y008237D03* X019800Y008222D03* X019800Y008207D03* X019800Y008192D03* X019800Y008177D03* X019800Y008162D03* X019800Y008147D03* X019800Y008132D03* X019800Y008117D03* X019800Y008102D03* X019800Y008087D03* X019800Y008072D03* X019800Y008057D03* X019800Y008042D03* X019800Y008027D03* X019800Y008012D03* X019800Y007997D03* X019800Y007982D03* X019800Y007967D03* X019800Y007952D03* X019800Y007937D03* X019800Y007922D03* X019800Y007907D03* X019800Y007892D03* X019800Y007877D03* X019800Y007862D03* X019800Y007847D03* X019800Y007832D03* X019800Y007817D03* X019800Y007802D03* X019800Y007787D03* X019800Y007772D03* X019800Y007757D03* X019800Y007742D03* X019800Y007727D03* X019800Y007712D03* X019800Y007697D03* X019800Y007682D03* X019800Y007667D03* X019800Y007652D03* X019800Y007637D03* X019800Y007622D03* X019800Y007607D03* X019800Y007592D03* X019800Y007577D03* X019800Y007562D03* X019800Y007547D03* X019800Y007532D03* X019800Y007517D03* X019800Y007502D03* X019800Y007487D03* X019800Y007472D03* X019800Y007457D03* X019800Y007442D03* X019800Y007427D03* X019800Y007412D03* X019800Y007397D03* X019800Y007382D03* X019800Y007367D03* X019800Y007352D03* X019800Y007337D03* X019800Y007322D03* X021983Y009842D03* X021983Y009857D03* X021983Y009872D03* X021983Y009887D03* X021983Y009902D03* X021983Y009917D03* X021983Y009932D03* X021983Y009947D03* X021983Y009962D03* X021983Y009977D03* X021983Y009992D03* X021983Y010007D03* X021983Y010022D03* X021983Y010037D03* X021983Y010052D03* X021983Y010067D03* X021983Y010082D03* X021983Y010097D03* X021983Y010112D03* X021983Y010127D03* X021983Y010142D03* X021983Y010157D03* X021983Y010172D03* X021983Y010187D03* X021983Y010202D03* X021983Y010217D03* X021983Y010232D03* X021983Y010247D03* X021983Y010262D03* X021983Y010277D03* X021983Y010292D03* X021983Y010307D03* X021983Y010322D03* X021983Y010337D03* X021983Y010352D03* X021983Y010367D03* X021983Y010382D03* X021983Y010397D03* X021983Y010412D03* X021983Y010427D03* X021983Y010442D03* X021983Y010457D03* X021983Y010472D03* X021983Y010487D03* X021983Y010502D03* X021983Y010517D03* X021983Y010532D03* X021983Y010547D03* X021983Y010562D03* X021983Y010577D03* X021983Y010592D03* X021983Y010607D03* X021983Y010622D03* X021983Y010637D03* X021983Y010652D03* X021983Y010667D03* X021983Y010682D03* X021983Y010697D03* X021983Y010712D03* X021983Y010727D03* X021983Y010742D03* X021983Y010757D03* X021983Y010772D03* X021983Y010787D03* X021983Y010802D03* X021983Y010817D03* X021983Y010832D03* X021983Y010847D03* X021983Y010862D03* X021983Y010877D03* X021983Y010892D03* X021983Y010907D03* X021983Y010922D03* X021983Y010937D03* X021983Y010952D03* X021983Y010967D03* X021983Y010982D03* X021983Y010997D03* X021983Y011012D03* X021983Y011027D03* X021983Y011042D03* X021983Y011057D03* X021983Y011072D03* X021983Y011087D03* X021983Y011102D03* X021983Y011117D03* X021983Y011132D03* X021983Y011147D03* X021983Y011162D03* X021983Y011177D03* X021983Y011192D03* X021983Y011207D03* X021983Y011222D03* X021983Y011237D03* X021983Y011252D03* X021983Y011267D03* X021983Y011282D03* X021983Y011297D03* X021983Y011312D03* X021983Y011327D03* X021983Y011342D03* X021983Y011357D03* X021983Y011372D03* X021983Y011387D03* X021983Y011402D03* X021983Y011417D03* X021983Y011432D03* X021983Y011447D03* X021983Y011462D03* X021983Y011477D03* X021983Y011492D03* X021983Y011507D03* X021983Y011522D03* X021983Y011537D03* X021983Y011552D03* X021983Y011567D03* X021983Y011582D03* X021983Y011597D03* X021983Y011612D03* X021983Y011627D03* X021983Y011642D03* X021983Y011657D03* X021983Y011672D03* X021983Y011687D03* X021983Y011702D03* X021983Y011717D03* X021983Y011732D03* X021983Y011747D03* X021983Y011762D03* X021983Y011777D03* X021983Y011792D03* X021983Y011807D03* X021983Y011822D03* X021983Y011837D03* X021983Y011852D03* X021983Y011867D03* X021983Y011882D03* X021983Y011897D03* X021983Y011912D03* X021983Y011927D03* X021983Y011942D03* X021983Y011957D03* X021983Y011972D03* X021983Y011987D03* X021983Y012002D03* X021983Y012017D03* X021983Y012032D03* X021983Y012047D03* X020565Y013502D03* X015870Y012032D03* X015870Y012017D03* X015870Y012002D03* X015870Y011987D03* X015870Y011972D03* X015870Y011957D03* X015870Y011942D03* X015870Y011927D03* X015870Y011912D03* X015870Y011897D03* X015870Y011882D03* X015870Y011867D03* X015870Y011852D03* X015870Y011837D03* X015870Y011822D03* X015870Y011807D03* X015870Y011792D03* X015870Y011777D03* X015870Y011762D03* X015870Y011747D03* X015870Y011732D03* X015870Y011717D03* X015870Y011702D03* X015870Y011687D03* X015870Y011672D03* X015870Y011657D03* X015870Y011642D03* X015870Y011627D03* X015870Y011612D03* X015870Y011597D03* X015870Y011582D03* X015870Y011567D03* X015870Y011552D03* X015870Y011537D03* X015870Y011522D03* X015870Y011507D03* X015870Y011492D03* X015870Y011477D03* X015870Y011462D03* X015870Y011447D03* X015870Y011432D03* X015870Y011417D03* X015870Y011402D03* X015870Y011387D03* X015870Y011372D03* X015870Y011357D03* X015870Y011342D03* X015870Y011327D03* X015870Y011312D03* X015870Y011297D03* X015870Y011282D03* X015870Y011267D03* X015870Y011252D03* X015870Y011237D03* X015870Y011222D03* X015870Y011207D03* X015870Y011192D03* X015870Y011177D03* X015870Y011162D03* X015870Y011147D03* X015870Y011132D03* X015870Y011117D03* X015870Y011102D03* X015870Y011087D03* X015870Y011072D03* X015870Y011057D03* X015870Y011042D03* X015870Y011027D03* X015870Y011012D03* X015870Y010997D03* X015870Y010982D03* X015870Y010967D03* X015870Y010952D03* X015870Y010937D03* X015870Y010922D03* X015870Y010907D03* X015870Y010892D03* X015870Y010877D03* X015870Y010862D03* X015870Y010847D03* X015870Y010832D03* X015870Y010817D03* X015870Y010802D03* X015870Y010787D03* X015870Y010772D03* X015870Y010757D03* X015870Y010742D03* X015870Y010727D03* X015870Y010712D03* X015870Y010697D03* X015870Y010682D03* X015870Y010667D03* X015870Y010652D03* X015870Y010637D03* X015870Y010622D03* X015870Y010607D03* X015870Y010592D03* X015870Y010577D03* X015870Y010562D03* X015870Y010547D03* X015870Y010532D03* X015870Y010517D03* X015870Y010502D03* X015870Y010487D03* X015870Y010472D03* X015870Y010457D03* X015870Y010442D03* X015870Y010427D03* X015870Y010412D03* X015870Y010397D03* X015870Y010382D03* X015870Y010367D03* X015870Y010352D03* X015870Y010337D03* X015870Y010322D03* X015870Y010307D03* X015870Y010292D03* X015870Y010277D03* X015870Y010262D03* X015870Y010247D03* X015870Y010232D03* X015870Y010217D03* X015870Y010202D03* X015870Y010187D03* X015870Y010172D03* X015870Y010157D03* X015870Y010142D03* X015870Y010127D03* X015870Y010112D03* X015870Y010097D03* X015870Y010082D03* X015870Y010067D03* X015870Y010052D03* X015870Y010037D03* X015870Y010022D03* X015870Y010007D03* X015870Y009992D03* X015870Y009977D03* X015870Y009962D03* X015870Y009947D03* X015870Y009932D03* X015870Y009917D03* X015870Y009902D03* X015870Y009887D03* X015870Y009872D03* X015870Y009857D03* D76* X015870Y009850D03* X015870Y009865D03* X015870Y009880D03* X015870Y009895D03* X015870Y009910D03* X015870Y009925D03* X015870Y009940D03* X015870Y009955D03* X015870Y009970D03* X015870Y009985D03* X015870Y010000D03* X015870Y010015D03* X015870Y010030D03* X015870Y010045D03* X015870Y010060D03* X015870Y010075D03* X015870Y010090D03* X015870Y010105D03* X015870Y010120D03* X015870Y010135D03* X015870Y010150D03* X015870Y010165D03* X015870Y010180D03* X015870Y010195D03* X015870Y010210D03* X015870Y010225D03* X015870Y010240D03* X015870Y010255D03* X015870Y010270D03* X015870Y010285D03* X015870Y010300D03* X015870Y010315D03* X015870Y010330D03* X015870Y010345D03* X015870Y010360D03* X015870Y010375D03* X015870Y010390D03* X015870Y010405D03* X015870Y010420D03* X015870Y010435D03* X015870Y010450D03* X015870Y010465D03* X015870Y010480D03* X015870Y010495D03* X015870Y010510D03* X015870Y010525D03* X015870Y010540D03* X015870Y010555D03* X015870Y010570D03* X015870Y010585D03* X015870Y010600D03* X015870Y010615D03* X015870Y010630D03* X015870Y010645D03* X015870Y010660D03* X015870Y010675D03* X015870Y010690D03* X015870Y010705D03* X015870Y010720D03* X015870Y010735D03* X015870Y010750D03* X015870Y010765D03* X015870Y010780D03* X015870Y010795D03* X015870Y010810D03* X015870Y010825D03* X015870Y010840D03* X015870Y010855D03* X015870Y010870D03* X015870Y010885D03* X015870Y010900D03* X015870Y010915D03* X015870Y010930D03* X015870Y010945D03* X015870Y010960D03* X015870Y010975D03* X015870Y010990D03* X015870Y011005D03* X015870Y011020D03* X015870Y011035D03* X015870Y011050D03* X015870Y011065D03* X015870Y011080D03* X015870Y011095D03* X015870Y011110D03* X015870Y011125D03* X015870Y011140D03* X015870Y011155D03* X015870Y011170D03* X015870Y011185D03* X015870Y011200D03* X015870Y011215D03* X015870Y011230D03* X015870Y011245D03* X015870Y011260D03* X015870Y011275D03* X015870Y011290D03* X015870Y011305D03* X015870Y011320D03* X015870Y011335D03* X015870Y011350D03* X015870Y011365D03* X015870Y011380D03* X015870Y011395D03* X015870Y011410D03* X015870Y011425D03* X015870Y011440D03* X015870Y011455D03* X015870Y011470D03* X015870Y011485D03* X015870Y011500D03* X015870Y011515D03* X015870Y011530D03* X015870Y011545D03* X015870Y011560D03* X015870Y011575D03* X015870Y011590D03* X015870Y011605D03* X015870Y011620D03* X015870Y011635D03* X015870Y011650D03* X015870Y011665D03* X015870Y011680D03* X015870Y011695D03* X015870Y011710D03* X015870Y011725D03* X015870Y011740D03* X015870Y011755D03* X015870Y011770D03* X015870Y011785D03* X015870Y011800D03* X015870Y011815D03* X015870Y011830D03* X015870Y011845D03* X015870Y011860D03* X015870Y011875D03* X015870Y011890D03* X015870Y011905D03* X015870Y011920D03* X015870Y011935D03* X015870Y011950D03* X015870Y011965D03* X015870Y011980D03* X015870Y011995D03* X015870Y012010D03* X015870Y012025D03* X015870Y012040D03* X021983Y012040D03* X021983Y012025D03* X021983Y012010D03* X021983Y011995D03* X021983Y011980D03* X021983Y011965D03* X021983Y011950D03* X021983Y011935D03* X021983Y011920D03* X021983Y011905D03* X021983Y011890D03* X021983Y011875D03* X021983Y011860D03* X021983Y011845D03* X021983Y011830D03* X021983Y011815D03* X021983Y011800D03* X021983Y011785D03* X021983Y011770D03* X021983Y011755D03* X021983Y011740D03* X021983Y011725D03* X021983Y011710D03* X021983Y011695D03* X021983Y011680D03* X021983Y011665D03* X021983Y011650D03* X021983Y011635D03* X021983Y011620D03* X021983Y011605D03* X021983Y011590D03* X021983Y011575D03* X021983Y011560D03* X021983Y011545D03* X021983Y011530D03* X021983Y011515D03* X021983Y011500D03* X021983Y011485D03* X021983Y011470D03* X021983Y011455D03* X021983Y011440D03* X021983Y011425D03* X021983Y011410D03* X021983Y011395D03* X021983Y011380D03* X021983Y011365D03* X021983Y011350D03* X021983Y011335D03* X021983Y011320D03* X021983Y011305D03* X021983Y011290D03* X021983Y011275D03* X021983Y011260D03* X021983Y011245D03* X021983Y011230D03* X021983Y011215D03* X021983Y011200D03* X021983Y011185D03* X021983Y011170D03* X021983Y011155D03* X021983Y011140D03* X021983Y011125D03* X021983Y011110D03* X021983Y011095D03* X021983Y011080D03* X021983Y011065D03* X021983Y011050D03* X021983Y011035D03* X021983Y011020D03* X021983Y011005D03* X021983Y010990D03* X021983Y010975D03* X021983Y010960D03* X021983Y010945D03* X021983Y010930D03* X021983Y010915D03* X021983Y010900D03* X021983Y010885D03* X021983Y010870D03* X021983Y010855D03* X021983Y010840D03* X021983Y010825D03* X021983Y010810D03* X021983Y010795D03* X021983Y010780D03* X021983Y010765D03* X021983Y010750D03* X021983Y010735D03* X021983Y010720D03* X021983Y010705D03* X021983Y010690D03* X021983Y010675D03* X021983Y010660D03* X021983Y010645D03* X021983Y010630D03* X021983Y010615D03* X021983Y010600D03* X021983Y010585D03* X021983Y010570D03* X021983Y010555D03* X021983Y010540D03* X021983Y010525D03* X021983Y010510D03* X021983Y010495D03* X021983Y010480D03* X021983Y010465D03* X021983Y010450D03* X021983Y010435D03* X021983Y010420D03* X021983Y010405D03* X021983Y010390D03* X021983Y010375D03* X021983Y010360D03* X021983Y010345D03* X021983Y010330D03* X021983Y010315D03* X021983Y010300D03* X021983Y010285D03* X021983Y010270D03* X021983Y010255D03* X021983Y010240D03* X021983Y010225D03* X021983Y010210D03* X021983Y010195D03* X021983Y010180D03* X021983Y010165D03* X021983Y010150D03* X021983Y010135D03* X021983Y010120D03* X021983Y010105D03* X021983Y010090D03* X021983Y010075D03* X021983Y010060D03* X021983Y010045D03* X021983Y010030D03* X021983Y010015D03* X021983Y010000D03* X021983Y009985D03* X021983Y009970D03* X021983Y009955D03* X021983Y009940D03* X021983Y009925D03* X021983Y009910D03* X021983Y009895D03* X021983Y009880D03* X021983Y009865D03* X021983Y009850D03* X019800Y008515D03* X019800Y008500D03* X019800Y008485D03* X019800Y008470D03* X019800Y008455D03* X019800Y008440D03* X019800Y008425D03* X019800Y008410D03* X019800Y008395D03* X019800Y008380D03* X019800Y008365D03* X019800Y008350D03* X019800Y008335D03* X019800Y008320D03* X019800Y008305D03* X019800Y008290D03* X019800Y008275D03* X019800Y008260D03* X019800Y008245D03* X019800Y008230D03* X019800Y008215D03* X019800Y008200D03* X019800Y008185D03* X019800Y008170D03* X019800Y008155D03* X019800Y008140D03* X019800Y008125D03* X019800Y008110D03* X019800Y008095D03* X019800Y008080D03* X019800Y008065D03* X019800Y008050D03* X019800Y008035D03* X019800Y008020D03* X019800Y008005D03* X019800Y007990D03* X019800Y007975D03* X019800Y007960D03* X019800Y007945D03* X019800Y007930D03* X019800Y007915D03* X019800Y007900D03* X019800Y007885D03* X019800Y007870D03* X019800Y007855D03* X019800Y007840D03* X019800Y007825D03* X019800Y007810D03* X019800Y007795D03* X019800Y007780D03* X019800Y007765D03* X019800Y007750D03* X019800Y007735D03* X019800Y007720D03* X019800Y007705D03* X019800Y007690D03* X019800Y007675D03* X019800Y007660D03* X019800Y007645D03* X019800Y007630D03* X019800Y007615D03* X019800Y007600D03* X019800Y007585D03* X019800Y007570D03* X019800Y007555D03* X019800Y007540D03* X019800Y007525D03* X019800Y007510D03* X019800Y007495D03* X019800Y007480D03* X019800Y007465D03* X019800Y007450D03* X019800Y007435D03* X019800Y007420D03* X019800Y007405D03* X019800Y007390D03* X019800Y007375D03* X019800Y007360D03* X019800Y007345D03* X019800Y007330D03* X018053Y007330D03* X018053Y007345D03* X018053Y007360D03* X018053Y007375D03* X018053Y007390D03* X018053Y007405D03* X018053Y007420D03* X018053Y007435D03* X018053Y007450D03* X018053Y007465D03* X018053Y007480D03* X018053Y007495D03* X018053Y007510D03* X018053Y007525D03* X018053Y007540D03* X018053Y007555D03* X018053Y007570D03* X018053Y007585D03* X018053Y007600D03* X018053Y007615D03* X018053Y007630D03* X018053Y007645D03* X018053Y007660D03* X018053Y007675D03* X018053Y007690D03* X018053Y007705D03* X018053Y007720D03* X018053Y007735D03* X018053Y007750D03* X018053Y007765D03* X018053Y007780D03* X018053Y007795D03* X018053Y007810D03* X018053Y007825D03* X018053Y007840D03* X018053Y007855D03* X018053Y007870D03* X018053Y007885D03* X018053Y007900D03* X018053Y007915D03* X018053Y007930D03* X018053Y007945D03* X018053Y007960D03* X018053Y007975D03* X018053Y007990D03* X018053Y008005D03* X018053Y008020D03* X018053Y008035D03* X018053Y008050D03* X018053Y008065D03* X018053Y008080D03* X018053Y008095D03* X018053Y008110D03* X018053Y008125D03* X018053Y008140D03* X018053Y008155D03* X018053Y008170D03* X018053Y008185D03* X018053Y008200D03* X018053Y008215D03* X018053Y008230D03* X018053Y008245D03* X018053Y008260D03* X018053Y008275D03* X018053Y008290D03* X018053Y008305D03* X018053Y008320D03* X018053Y008335D03* X018053Y008350D03* X018053Y008365D03* X018053Y008380D03* X018053Y008395D03* X018053Y008410D03* X018053Y008425D03* X018053Y008440D03* X018053Y008455D03* X018053Y008470D03* X018053Y008485D03* X018053Y008500D03* X018053Y008515D03* D77* X018926Y008522D03* D78* X018926Y008530D03* X018926Y013915D03* D79* X018926Y008537D03* D80* X018926Y008545D03* D81* X018926Y008552D03* D82* X018926Y008560D03* D83* X018926Y008567D03* D84* X018926Y008575D03* D85* X018926Y008582D03* D86* X018926Y008590D03* D87* X018926Y008597D03* D88* X018926Y008605D03* D89* X018926Y008612D03* D90* X018926Y008620D03* D91* X018926Y008627D03* D92* X018923Y008635D03* D93* X018926Y008642D03* D94* X018926Y008650D03* D95* X018926Y008657D03* D96* X018926Y008665D03* D97* X018926Y008672D03* D98* X018926Y008680D03* X018926Y013480D03* D99* X018926Y013457D03* X018926Y008687D03* D100* X018926Y008695D03* X018926Y013450D03* D101* X018926Y013427D03* X018926Y008702D03* D102* X018926Y008710D03* X018926Y013405D03* D103* X018926Y013397D03* X018926Y008717D03* D104* X018926Y008725D03* X018926Y013375D03* D105* X018926Y013367D03* X018926Y008732D03* D106* X018926Y008740D03* X018926Y013360D03* D107* X018926Y013337D03* X018926Y008747D03* D108* X018926Y008755D03* X018926Y013315D03* D109* X018926Y013307D03* X018926Y008762D03* D110* X018926Y008770D03* X018926Y013285D03* D111* X018926Y013262D03* X018926Y008777D03* D112* X018926Y008785D03* X018926Y013270D03* D113* X018926Y013247D03* X018926Y008792D03* D114* X018926Y008800D03* X018926Y013240D03* D115* X018926Y013217D03* X018926Y008807D03* D116* X018923Y008815D03* X018930Y013210D03* D117* X018926Y013202D03* X018926Y013187D03* X018926Y008822D03* D118* X018923Y008830D03* X018930Y013180D03* D119* X018926Y013172D03* X018926Y008837D03* D120* X018923Y008845D03* D121* X018926Y008852D03* X018926Y013142D03* D122* X018926Y013135D03* X018926Y013150D03* X018926Y008860D03* D123* X018926Y008867D03* X018926Y013112D03* D124* X018926Y013105D03* X018926Y013120D03* X018926Y008875D03* D125* X018923Y008882D03* X018930Y013097D03* D126* X018926Y013090D03* X018926Y013075D03* X018926Y008890D03* D127* X018926Y008897D03* X018926Y013067D03* X018926Y013082D03* D128* X018930Y013060D03* X018923Y008905D03* D129* X018926Y008912D03* X018926Y008927D03* X018926Y013037D03* X018926Y013052D03* D130* X018926Y013045D03* X018926Y013030D03* X018926Y008920D03* D131* X018926Y008935D03* X018926Y008950D03* X018926Y013000D03* X018926Y013015D03* D132* X018926Y013007D03* X018926Y012992D03* X018926Y008957D03* X018926Y008942D03* D133* X018926Y008965D03* X018926Y008980D03* X018926Y008995D03* X018926Y012955D03* X018926Y012970D03* D134* X018926Y012977D03* X018926Y012962D03* X018926Y012947D03* X018926Y009002D03* X018926Y008987D03* X018926Y008972D03* D135* X018923Y009010D03* X018930Y012940D03* D136* X018926Y012917D03* X018926Y012902D03* X018926Y012452D03* X018926Y012437D03* X018926Y012422D03* X018926Y012407D03* X018926Y012392D03* X018926Y012377D03* X018926Y012362D03* X018926Y012347D03* X018926Y012332D03* X018926Y012317D03* X018926Y012302D03* X018926Y012287D03* X018926Y012272D03* X018926Y012257D03* X018926Y012242D03* X018926Y012227D03* X018926Y012212D03* X018926Y012197D03* X018926Y012182D03* X018926Y012167D03* X018926Y012152D03* X018926Y012137D03* X018926Y012122D03* X018926Y012107D03* X018926Y012092D03* X018926Y012077D03* X018926Y012062D03* X018926Y012047D03* X018926Y012032D03* X018926Y012017D03* X018926Y012002D03* X018926Y011987D03* X018926Y011972D03* X018926Y011957D03* X018926Y011942D03* X018926Y011927D03* X018926Y011912D03* X018926Y011897D03* X018926Y011882D03* X018926Y011867D03* X018926Y011852D03* X018926Y011837D03* X018926Y011822D03* X018926Y011807D03* X018926Y011792D03* X018926Y011777D03* X018926Y011762D03* X018926Y011747D03* X018926Y011732D03* X018926Y011717D03* X018926Y011702D03* X018926Y011687D03* X018926Y011672D03* X018926Y011657D03* X018926Y011642D03* X018926Y011627D03* X018926Y011612D03* X018926Y011597D03* X018926Y011582D03* X018926Y011567D03* X018926Y011552D03* X018926Y011537D03* X018926Y011522D03* X018926Y011507D03* X018926Y011492D03* X018926Y011477D03* X018926Y011462D03* X018926Y011447D03* X018926Y011432D03* X018926Y011417D03* X018926Y011402D03* X018926Y011387D03* X018926Y011372D03* X018926Y011357D03* X018926Y011342D03* X018926Y011327D03* X018926Y011312D03* X018926Y011297D03* X018926Y011282D03* X018926Y011267D03* X018926Y011252D03* X018926Y011237D03* X018926Y011222D03* X018926Y011207D03* X018926Y011192D03* X018926Y011177D03* X018926Y011162D03* X018926Y011147D03* X018926Y011132D03* X018926Y011117D03* X018926Y011102D03* X018926Y011087D03* X018926Y011072D03* X018926Y011057D03* X018926Y011042D03* X018926Y011027D03* X018926Y011012D03* X018926Y010997D03* X018926Y010982D03* X018926Y010967D03* X018926Y010952D03* X018926Y010937D03* X018926Y010922D03* X018926Y010907D03* X018926Y010892D03* X018926Y010877D03* X018926Y010862D03* X018926Y010847D03* X018926Y010832D03* X018926Y010817D03* X018926Y010802D03* X018926Y010787D03* X018926Y010772D03* X018926Y010757D03* X018926Y010742D03* X018926Y010727D03* X018926Y010712D03* X018926Y010697D03* X018926Y010682D03* X018926Y010667D03* X018926Y010652D03* X018926Y010637D03* X018926Y010622D03* X018926Y010607D03* X018926Y010592D03* X018926Y010577D03* X018926Y010562D03* X018926Y010547D03* X018926Y010532D03* X018926Y010517D03* X018926Y010502D03* X018926Y010487D03* X018926Y010472D03* X018926Y010457D03* X018926Y010442D03* X018926Y010427D03* X018926Y010412D03* X018926Y010397D03* X018926Y010382D03* X018926Y010367D03* X018926Y010352D03* X018926Y010337D03* X018926Y010322D03* X018926Y010307D03* X018926Y010292D03* X018926Y010277D03* X018926Y010262D03* X018926Y010247D03* X018926Y010232D03* X018926Y010217D03* X018926Y010202D03* X018926Y010187D03* X018926Y010172D03* X018926Y010157D03* X018926Y010142D03* X018926Y010127D03* X018926Y010112D03* X018926Y010097D03* X018926Y010082D03* X018926Y010067D03* X018926Y010052D03* X018926Y010037D03* X018926Y010022D03* X018926Y010007D03* X018926Y009992D03* X018926Y009977D03* X018926Y009962D03* X018926Y009947D03* X018926Y009932D03* X018926Y009917D03* X018926Y009902D03* X018926Y009887D03* X018926Y009872D03* X018926Y009857D03* X018926Y009842D03* X018926Y009827D03* X018926Y009812D03* X018926Y009797D03* X018926Y009782D03* X018926Y009767D03* X018926Y009752D03* X018926Y009737D03* X018926Y009722D03* X018926Y009707D03* X018926Y009692D03* X018926Y009677D03* X018926Y009662D03* X018926Y009647D03* X018926Y009632D03* X018926Y009617D03* X018926Y009602D03* X018926Y009587D03* X018926Y009572D03* X018926Y009557D03* X018926Y009542D03* X018926Y009527D03* X018926Y009512D03* X018926Y009497D03* X018926Y009482D03* X018926Y009467D03* X018926Y009452D03* X018926Y009437D03* X018926Y009422D03* X018926Y009407D03* X018926Y009392D03* X018926Y009377D03* X018926Y009362D03* X018926Y009347D03* X018926Y009332D03* X018926Y009317D03* X018926Y009302D03* X018926Y009287D03* X018926Y009272D03* X018926Y009257D03* X018926Y009242D03* X018926Y009227D03* X018926Y009212D03* X018926Y009197D03* X018926Y009182D03* X018926Y009167D03* X018926Y009152D03* X018926Y009137D03* X018926Y009122D03* X018926Y009107D03* X018926Y009092D03* X018926Y009077D03* X018926Y009062D03* X018926Y009047D03* X018926Y009032D03* X018926Y009017D03* D137* X018926Y009025D03* X018926Y009040D03* X018926Y009055D03* X018926Y009070D03* X018926Y009085D03* X018926Y009100D03* X018926Y009115D03* X018926Y009130D03* X018926Y009145D03* X018926Y009160D03* X018926Y009175D03* X018926Y009190D03* X018926Y009205D03* X018926Y009220D03* X018926Y009235D03* X018926Y009250D03* X018926Y009265D03* X018926Y009280D03* X018926Y009295D03* X018926Y009310D03* X018926Y009325D03* X018926Y009340D03* X018926Y009355D03* X018926Y009370D03* X018926Y009385D03* X018926Y009400D03* X018926Y009415D03* X018926Y009430D03* X018926Y009445D03* X018926Y009460D03* X018926Y009475D03* X018926Y009490D03* X018926Y009505D03* X018926Y009520D03* X018926Y009535D03* X018926Y009550D03* X018926Y009565D03* X018926Y009580D03* X018926Y009595D03* X018926Y009610D03* X018926Y009625D03* X018926Y009640D03* X018926Y009655D03* X018926Y009670D03* X018926Y009685D03* X018926Y009700D03* X018926Y009715D03* X018926Y009730D03* X018926Y009745D03* X018926Y009760D03* X018926Y009775D03* X018926Y009790D03* X018926Y009805D03* X018926Y009820D03* X018926Y009835D03* X018926Y009850D03* X018926Y009865D03* X018926Y009880D03* X018926Y009895D03* X018926Y009910D03* X018926Y009925D03* X018926Y009940D03* X018926Y009955D03* X018926Y009970D03* X018926Y009985D03* X018926Y010000D03* X018926Y010015D03* X018926Y010030D03* X018926Y010045D03* X018926Y010060D03* X018926Y010075D03* X018926Y010090D03* X018926Y010105D03* X018926Y010120D03* X018926Y010135D03* X018926Y010150D03* X018926Y010165D03* X018926Y010180D03* X018926Y010195D03* X018926Y010210D03* X018926Y010225D03* X018926Y010240D03* X018926Y010255D03* X018926Y010270D03* X018926Y010285D03* X018926Y010300D03* X018926Y010315D03* X018926Y010330D03* X018926Y010345D03* X018926Y010360D03* X018926Y010375D03* X018926Y010390D03* X018926Y010405D03* X018926Y010420D03* X018926Y010435D03* X018926Y010450D03* X018926Y010465D03* X018926Y010480D03* X018926Y010495D03* X018926Y010510D03* X018926Y010525D03* X018926Y010540D03* X018926Y010555D03* X018926Y010570D03* X018926Y010585D03* X018926Y010600D03* X018926Y010615D03* X018926Y010630D03* X018926Y010645D03* X018926Y010660D03* X018926Y010675D03* X018926Y010690D03* X018926Y010705D03* X018926Y010720D03* X018926Y010735D03* X018926Y010750D03* X018926Y010765D03* X018926Y010780D03* X018926Y010795D03* X018926Y010810D03* X018926Y010825D03* X018926Y010840D03* X018926Y010855D03* X018926Y010870D03* X018926Y010885D03* X018926Y010900D03* X018926Y010915D03* X018926Y010930D03* X018926Y010945D03* X018926Y010960D03* X018926Y010975D03* X018926Y010990D03* X018926Y011005D03* X018926Y011020D03* X018926Y011035D03* X018926Y011050D03* X018926Y011065D03* X018926Y011080D03* X018926Y011095D03* X018926Y011110D03* X018926Y011125D03* X018926Y011140D03* X018926Y011155D03* X018926Y011170D03* X018926Y011185D03* X018926Y011200D03* X018926Y011215D03* X018926Y011230D03* X018926Y011245D03* X018926Y011260D03* X018926Y011275D03* X018926Y011290D03* X018926Y011305D03* X018926Y011320D03* X018926Y011335D03* X018926Y011350D03* X018926Y011365D03* X018926Y011380D03* X018926Y011395D03* X018926Y011410D03* X018926Y011425D03* X018926Y011440D03* X018926Y011455D03* X018926Y011470D03* X018926Y011485D03* X018926Y011500D03* X018926Y011515D03* X018926Y011530D03* X018926Y011545D03* X018926Y011560D03* X018926Y011575D03* X018926Y011590D03* X018926Y011605D03* X018926Y011620D03* X018926Y011635D03* X018926Y011650D03* X018926Y011665D03* X018926Y011680D03* X018926Y011695D03* X018926Y011710D03* X018926Y011725D03* X018926Y011740D03* X018926Y011755D03* X018926Y011770D03* X018926Y011785D03* X018926Y011800D03* X018926Y011815D03* X018926Y011830D03* X018926Y011845D03* X018926Y011860D03* X018926Y011875D03* X018926Y011890D03* X018926Y011905D03* X018926Y011920D03* X018926Y011935D03* X018926Y011950D03* X018926Y011965D03* X018926Y011980D03* X018926Y011995D03* X018926Y012010D03* X018926Y012025D03* X018926Y012040D03* X018926Y012055D03* X018926Y012070D03* X018926Y012085D03* X018926Y012100D03* X018926Y012115D03* X018926Y012130D03* X018926Y012145D03* X018926Y012160D03* X018926Y012175D03* X018926Y012190D03* X018926Y012205D03* X018926Y012220D03* X018926Y012235D03* X018926Y012250D03* X018926Y012265D03* X018926Y012280D03* X018926Y012295D03* X018926Y012310D03* X018926Y012325D03* X018926Y012340D03* X018926Y012355D03* X018926Y012370D03* X018926Y012385D03* X018926Y012400D03* X018926Y012415D03* X018926Y012430D03* X018926Y012445D03* X018926Y012460D03* X018926Y012895D03* X018926Y012910D03* X018926Y012925D03* D138* X017471Y015257D03* X020381Y015257D03* X021986Y009332D03* X015866Y009332D03* D139* X015866Y009340D03* X021986Y009340D03* D140* X021986Y009347D03* X015866Y009347D03* D141* X015866Y009355D03* X021986Y009355D03* D142* X021986Y009362D03* X015866Y009362D03* D143* X021983Y009370D03* D144* X015866Y009370D03* X015866Y012520D03* X021986Y012520D03* D145* X021986Y012512D03* X015866Y012512D03* X015866Y009377D03* X021986Y009377D03* D146* X021986Y009385D03* X015866Y009385D03* X015866Y012505D03* X021986Y012505D03* D147* X021986Y012497D03* X015866Y012497D03* X015866Y009392D03* X021986Y009392D03* D148* X021986Y009400D03* X015866Y009400D03* X015866Y012490D03* X021986Y012490D03* D149* X021986Y009407D03* X015866Y009407D03* D150* X015866Y009415D03* X021986Y009415D03* X021986Y012475D03* X015866Y012475D03* D151* X015866Y009422D03* X021986Y009422D03* D152* X021986Y009430D03* X015866Y009430D03* X015866Y012460D03* X021986Y012460D03* D153* X021986Y012452D03* X015866Y012452D03* X015866Y009437D03* X021986Y009437D03* D154* X021986Y009445D03* X015866Y009445D03* D155* X015866Y009460D03* X021986Y009460D03* X021986Y012430D03* X015866Y012430D03* D156* X015866Y012422D03* X021986Y012422D03* X021986Y009467D03* X015866Y009467D03* D157* X015866Y009475D03* X021986Y009475D03* X021986Y012415D03* X015866Y012415D03* D158* X015866Y012407D03* X021986Y012407D03* X021986Y009482D03* X015866Y009482D03* D159* X015866Y009490D03* X021986Y009490D03* X021986Y012400D03* X020561Y013765D03* X020531Y013810D03* X020516Y013825D03* X017321Y013810D03* X017291Y013765D03* X015866Y012400D03* D160* X015866Y012392D03* X017276Y013727D03* X020576Y013727D03* X021986Y012392D03* X021986Y009497D03* X015866Y009497D03* D161* X015866Y009505D03* X021986Y009505D03* X021986Y012385D03* X020471Y013870D03* X017381Y013870D03* X015866Y012385D03* D162* X015866Y012362D03* X015866Y009527D03* X021986Y009527D03* D163* X021986Y009535D03* X015866Y009535D03* X015866Y012355D03* X021986Y012355D03* D164* X021986Y012347D03* X015866Y012347D03* X015866Y009542D03* X021986Y009542D03* D165* X021986Y009557D03* X015866Y009557D03* X015866Y012332D03* X020606Y013607D03* X021986Y012332D03* D166* X021986Y012325D03* X015866Y012325D03* X015866Y009565D03* X021986Y009565D03* D167* X021986Y009580D03* X015866Y009580D03* X015866Y012310D03* X021986Y012310D03* D168* X021986Y012302D03* X015866Y012302D03* X015866Y009587D03* X021986Y009587D03* X018926Y014762D03* D169* X015866Y009595D03* X021986Y009595D03* D170* X021986Y009602D03* X015866Y009602D03* X015866Y012287D03* X021986Y012287D03* D171* X021986Y012272D03* X015866Y012272D03* X015866Y009617D03* X021986Y009617D03* D172* X021986Y009632D03* X015866Y009632D03* X015866Y012257D03* X021986Y012257D03* D173* X021986Y009640D03* X015866Y009640D03* D174* X015866Y009647D03* X021986Y009647D03* X021986Y012242D03* X020591Y013532D03* X017261Y013532D03* X015866Y012242D03* D175* X015866Y012235D03* X021986Y012235D03* X021986Y009655D03* X015866Y009655D03* D176* X015866Y009670D03* X021986Y009670D03* X021986Y012220D03* X015866Y012220D03* X018926Y014755D03* D177* X015866Y012212D03* X021986Y012212D03* X021986Y009677D03* X015866Y009677D03* D178* X015866Y009685D03* X015866Y009700D03* X021986Y009700D03* X021986Y009685D03* X021986Y012190D03* X021986Y012205D03* X015866Y012205D03* X015866Y012190D03* D179* X015866Y012197D03* X021986Y012197D03* X021986Y009692D03* X015866Y009692D03* D180* X015866Y009715D03* X021986Y009715D03* X021986Y012175D03* X020576Y013510D03* X017276Y013510D03* X015866Y012175D03* D181* X015866Y012167D03* X021986Y012167D03* X021986Y009722D03* X015866Y009722D03* D182* X015866Y009737D03* X015866Y009752D03* X021986Y009752D03* X021986Y009737D03* X021986Y012137D03* X021986Y012152D03* X015866Y012152D03* X015866Y012137D03* D183* X015866Y012130D03* X015866Y012145D03* X021986Y012145D03* X021986Y012130D03* X021986Y009760D03* X021986Y009745D03* X015866Y009760D03* X015866Y009745D03* D184* X015866Y009782D03* X015866Y009797D03* X015866Y009812D03* X015866Y009827D03* X015866Y009842D03* X021986Y009827D03* X021986Y009812D03* X021986Y009797D03* X021986Y009782D03* X021986Y012062D03* X021986Y012077D03* X021986Y012092D03* X021986Y012107D03* X017291Y013502D03* X015866Y012107D03* X015866Y012092D03* X015866Y012077D03* X015866Y012062D03* X015866Y012047D03* D185* X015866Y012055D03* X015866Y012070D03* X015866Y012085D03* X015866Y012100D03* X021986Y012100D03* X021986Y012085D03* X021986Y012070D03* X021986Y012055D03* X021986Y009835D03* X021986Y009820D03* X021986Y009805D03* X021986Y009790D03* X015866Y009805D03* X015866Y009820D03* X015866Y009835D03* X015866Y009790D03* D186* X015866Y012377D03* X017261Y013682D03* X020591Y013682D03* X021986Y012377D03* D187* X021986Y012437D03* X015866Y012437D03* D188* X015866Y012557D03* X021986Y012557D03* D189* X018930Y012647D03* X018930Y012662D03* X018930Y012677D03* D190* X018930Y012670D03* X018930Y012655D03* D191* X018926Y012685D03* X018926Y012700D03* X018926Y012715D03* X018926Y012730D03* X018926Y012745D03* X018926Y012760D03* X018926Y012775D03* X018926Y012790D03* D192* X018926Y012797D03* X018926Y012782D03* X018926Y012767D03* X018926Y012752D03* X018926Y012737D03* X018926Y012722D03* X018926Y012707D03* X018926Y012692D03* D193* X018930Y012805D03* X018930Y012820D03* D194* X018930Y012812D03* D195* X018926Y012827D03* X018926Y012842D03* X018926Y012857D03* X018926Y012872D03* D196* X018926Y012865D03* X018926Y012850D03* X018926Y012835D03* D197* X018930Y012880D03* D198* X018930Y012887D03* D199* X018930Y012932D03* D200* X018930Y012985D03* D201* X018930Y013022D03* D202* X018930Y013127D03* D203* X018930Y013157D03* D204* X018926Y013165D03* D205* X018926Y013195D03* D206* X018926Y013225D03* D207* X018930Y013232D03* D208* X018930Y013255D03* D209* X018930Y013277D03* D210* X018926Y013292D03* D211* X018930Y013300D03* D212* X018930Y013322D03* D213* X018926Y013330D03* D214* X018930Y013345D03* D215* X018926Y013352D03* D216* X018930Y013382D03* D217* X018926Y013390D03* D218* X018926Y013412D03* D219* X018930Y013420D03* D220* X018930Y013435D03* D221* X018926Y013442D03* D222* X018926Y013465D03* D223* X018930Y013472D03* D224* X018930Y013487D03* D225* X018926Y013495D03* D226* X018926Y013502D03* D227* X018926Y013510D03* D228* X018926Y013517D03* D229* X018926Y013525D03* D230* X018926Y013532D03* D231* X018926Y013540D03* X018926Y014620D03* D232* X018926Y013547D03* D233* X017254Y013555D03* X020599Y013555D03* D234* X018926Y013555D03* D235* X017250Y013562D03* X020603Y013562D03* D236* X018926Y013562D03* D237* X018926Y013570D03* D238* X020603Y013577D03* D239* X018926Y013577D03* X018926Y013802D03* D240* X017254Y013577D03* D241* X017250Y013585D03* X020603Y013585D03* D242* X018926Y013585D03* X018926Y013810D03* X018926Y014635D03* D243* X020606Y013592D03* D244* X018926Y013592D03* D245* X017250Y013600D03* X020603Y013600D03* D246* X018926Y013600D03* X018926Y013780D03* D247* X018926Y013607D03* D248* X017250Y013607D03* D249* X018926Y013615D03* X018926Y013630D03* X018926Y013765D03* D250* X017250Y013622D03* X020603Y013622D03* D251* X018926Y013622D03* X018926Y013757D03* X018926Y013772D03* X018926Y014642D03* D252* X017254Y013637D03* X020599Y013637D03* D253* X018926Y013637D03* X018926Y013652D03* X018926Y013727D03* X018926Y013742D03* D254* X017250Y013645D03* X020603Y013645D03* D255* X018926Y013645D03* X018926Y013660D03* X018926Y013735D03* X018926Y013750D03* D256* X017254Y013652D03* X020599Y013652D03* D257* X020599Y013660D03* D258* X020595Y013667D03* X017258Y013667D03* D259* X018926Y013667D03* X018926Y013682D03* X018926Y013697D03* X018926Y013712D03* D260* X017261Y013675D03* X020591Y013675D03* D261* X018926Y013675D03* X018926Y013690D03* X018926Y013705D03* X018926Y013720D03* D262* X017265Y013690D03* X020588Y013690D03* D263* X017269Y013697D03* D264* X017273Y013712D03* X020483Y013862D03* X020580Y013712D03* D265* X020580Y013720D03* X017273Y013720D03* D266* X017280Y013735D03* X017288Y013750D03* X017348Y013840D03* X017363Y013855D03* X020490Y013855D03* X020505Y013840D03* X020565Y013750D03* X020573Y013735D03* D267* X020573Y013742D03* X020565Y013757D03* X020498Y013847D03* X017355Y013847D03* X017280Y013742D03* D268* X017291Y013757D03* X017306Y013787D03* X020516Y013832D03* X020546Y013787D03* D269* X020554Y013772D03* X020524Y013817D03* X017329Y013817D03* X017299Y013772D03* D270* X017303Y013780D03* X017333Y013825D03* D271* X018923Y013787D03* D272* X018926Y013795D03* D273* X017340Y013832D03* X017318Y013802D03* X020535Y013802D03* D274* X018926Y013817D03* D275* X018926Y013825D03* D276* X018926Y013832D03* D277* X018926Y013840D03* D278* X018926Y013847D03* D279* X018926Y013855D03* D280* X018926Y013862D03* D281* X018926Y013870D03* X018926Y014605D03* D282* X018926Y013877D03* D283* X017411Y013885D03* X020441Y013885D03* X018926Y014770D03* D284* X018926Y013885D03* D285* X018930Y013892D03* D286* X018926Y013900D03* D287* X018926Y013907D03* D288* X018926Y013922D03* D289* X018930Y013930D03* D290* X018926Y013937D03* D291* X018926Y013945D03* D292* X018926Y013952D03* D293* X018926Y013960D03* D294* X018930Y013967D03* D295* X018930Y013975D03* D296* X018926Y013982D03* D297* X018926Y013990D03* D298* X018926Y013997D03* D299* X018926Y014005D03* D300* X018926Y014012D03* D301* X018926Y014020D03* D302* X018926Y014027D03* D303* X018930Y014035D03* D304* X018930Y014042D03* D305* X018930Y014050D03* D306* X018930Y014057D03* D307* X018926Y014065D03* D308* X018926Y014072D03* D309* X018926Y014080D03* D310* X018926Y014087D03* D311* X018926Y014095D03* D312* X018926Y014102D03* D313* X018926Y014110D03* D314* X018926Y014117D03* D315* X018926Y014125D03* D316* X018926Y014132D03* D317* X018926Y014140D03* D318* X018930Y014147D03* D319* X018930Y014155D03* D320* X018930Y014162D03* D321* X018930Y014170D03* D322* X018926Y014177D03* D323* X018926Y014185D03* D324* X018926Y014192D03* D325* X018926Y014200D03* D326* X018926Y014207D03* D327* X018926Y014215D03* D328* X018930Y014222D03* D329* X018926Y014230D03* D330* X018926Y014237D03* D331* X018926Y014245D03* D332* X018926Y014252D03* D333* X018930Y014260D03* D334* X018926Y014267D03* D335* X018926Y014275D03* D336* X018926Y014282D03* D337* X018930Y014290D03* D338* X018926Y014297D03* D339* X018926Y014305D03* D340* X018930Y014312D03* D341* X018926Y014320D03* D342* X018926Y014327D03* D343* X018930Y014335D03* D344* X018926Y014342D03* D345* X018926Y014350D03* D346* X018926Y014357D03* D347* X018926Y014365D03* D348* X018930Y014372D03* D349* X018926Y014380D03* D350* X018930Y014387D03* D351* X018926Y014395D03* D352* X018930Y014402D03* D353* X018926Y014410D03* D354* X018926Y014417D03* D355* X018926Y014425D03* D356* X018926Y014432D03* D357* X018930Y014440D03* D358* X018926Y014447D03* D359* X018926Y014455D03* D360* X018930Y014462D03* D361* X018926Y014470D03* D362* X018926Y014477D03* D363* X018926Y014485D03* D364* X018930Y014492D03* D365* X018926Y014500D03* D366* X018926Y014507D03* X018926Y014582D03* D367* X018926Y014560D03* X018926Y014515D03* D368* X018926Y014522D03* X018926Y014537D03* D369* X018926Y014530D03* D370* X018926Y014545D03* D371* X018926Y014552D03* D372* X018926Y014567D03* D373* X018926Y014575D03* D374* X019013Y014590D03* D375* X020040Y014605D03* X020048Y014620D03* X020100Y014710D03* X020108Y014725D03* X020115Y014740D03* X020123Y014755D03* X020130Y014770D03* X020190Y014875D03* X020198Y014890D03* X020205Y014905D03* X020213Y014920D03* X020273Y015025D03* X020280Y015040D03* X020288Y015055D03* X020295Y015070D03* X020355Y015175D03* X020363Y015190D03* X020370Y015205D03* X017820Y014590D03* X017813Y014605D03* X017753Y014710D03* X017745Y014725D03* X017738Y014740D03* X017730Y014755D03* X017723Y014770D03* X017670Y014860D03* X017663Y014875D03* X017655Y014890D03* X017648Y014905D03* X017640Y014920D03* X017580Y015025D03* X017573Y015040D03* X017565Y015055D03* X017558Y015070D03* X017498Y015175D03* X017490Y015190D03* X017483Y015205D03* D376* X017486Y015197D03* X017501Y015167D03* X017561Y015062D03* X017576Y015032D03* X017591Y015002D03* X017636Y014927D03* X017651Y014897D03* X017666Y014867D03* X017726Y014762D03* X017741Y014732D03* X017756Y014702D03* X017816Y014597D03* X020036Y014597D03* X020051Y014627D03* X020096Y014702D03* X020111Y014732D03* X020126Y014762D03* X020186Y014867D03* X020201Y014897D03* X020216Y014927D03* X020276Y015032D03* X020291Y015062D03* X020351Y015167D03* X020366Y015197D03* D377* X018926Y014597D03* D378* X017809Y014612D03* X017749Y014717D03* X017734Y014747D03* X017719Y014777D03* X017674Y014852D03* X017659Y014882D03* X017644Y014912D03* X017584Y015017D03* X017569Y015047D03* X017554Y015077D03* X017494Y015182D03* X020044Y014612D03* X020104Y014717D03* X020119Y014747D03* X020134Y014777D03* X020179Y014852D03* X020194Y014882D03* X020209Y014912D03* X020269Y015017D03* X020284Y015047D03* X020299Y015077D03* X020359Y015182D03* D379* X018930Y014612D03* D380* X017801Y014620D03* X017786Y014650D03* X017771Y014680D03* X017711Y014785D03* X017696Y014815D03* X017681Y014845D03* X017621Y014950D03* X017606Y014980D03* X017591Y015010D03* X017546Y015085D03* X017531Y015115D03* X017516Y015145D03* X020066Y014650D03* X020081Y014680D03* X020141Y014785D03* X020156Y014815D03* X020171Y014845D03* X020231Y014950D03* X020246Y014980D03* X020261Y015010D03* X020306Y015085D03* X020321Y015115D03* X020336Y015145D03* D381* X018930Y014627D03* D382* X017798Y014627D03* X017790Y014642D03* X017783Y014657D03* X017775Y014672D03* X017768Y014687D03* X017708Y014792D03* X017700Y014807D03* X017693Y014822D03* X017685Y014837D03* X017625Y014942D03* X017618Y014957D03* X017610Y014972D03* X017603Y014987D03* X017543Y015092D03* X017535Y015107D03* X017528Y015122D03* X017520Y015137D03* X017513Y015152D03* X017483Y015212D03* X020063Y014642D03* X020070Y014657D03* X020078Y014672D03* X020085Y014687D03* X020145Y014792D03* X020153Y014807D03* X020160Y014822D03* X020168Y014837D03* X020228Y014942D03* X020235Y014957D03* X020243Y014972D03* X020250Y014987D03* X020258Y015002D03* X020310Y015092D03* X020318Y015107D03* X020325Y015122D03* X020333Y015137D03* X020340Y015152D03* X020370Y015212D03* D383* X020344Y015160D03* X020329Y015130D03* X020314Y015100D03* X020254Y014995D03* X020239Y014965D03* X020224Y014935D03* X020179Y014860D03* X020164Y014830D03* X020149Y014800D03* X020089Y014695D03* X020074Y014665D03* X020059Y014635D03* X017794Y014635D03* X017779Y014665D03* X017764Y014695D03* X017704Y014800D03* X017689Y014830D03* X017629Y014935D03* X017614Y014965D03* X017599Y014995D03* X017539Y015100D03* X017524Y015130D03* X017509Y015160D03* D384* X018930Y014650D03* D385* X018926Y014657D03* D386* X018926Y014665D03* D387* X018926Y014672D03* D388* X018926Y014680D03* D389* X018926Y014687D03* D390* X018930Y014695D03* D391* X018926Y014702D03* D392* X018930Y014710D03* D393* X018926Y014717D03* D394* X018926Y014725D03* D395* X018926Y014732D03* D396* X018926Y014740D03* D397* X018926Y014747D03* D398* X018930Y014777D03* D399* X018926Y014785D03* D400* X018926Y014792D03* D401* X018930Y014800D03* D402* X017479Y015220D03* X020374Y015220D03* D403* X020374Y015227D03* X017479Y015227D03* D404* X017475Y015235D03* X020378Y015235D03* D405* X020381Y015250D03* X017471Y015250D03* D406* X017471Y015265D03* X020381Y015265D03* D407* X020381Y015272D03* X017471Y015272D03* D408* X017471Y015280D03* X020381Y015280D03* D409* X020378Y015287D03* X017475Y015287D03* D410* X017471Y015295D03* X020381Y015295D03* D411* X013669Y016877D03* X013669Y016897D03* X013669Y016917D03* X013669Y016937D03* X013669Y016957D03* X013669Y016977D03* X013669Y016997D03* X013669Y017017D03* X013669Y017837D03* X013669Y017857D03* X013669Y017877D03* X013669Y017897D03* X013669Y017917D03* X013669Y017937D03* X013669Y017957D03* X013669Y017977D03* X010629Y018317D03* X010629Y018337D03* X010629Y018357D03* X010629Y018377D03* X010629Y018397D03* X010629Y018417D03* X010629Y018437D03* X010629Y018457D03* X010149Y020397D03* X010149Y020417D03* X010149Y020437D03* X010149Y020457D03* X010149Y020477D03* X010149Y020497D03* X010149Y020517D03* X010149Y020537D03* X010149Y021357D03* X010149Y021377D03* X010149Y021397D03* X010149Y021417D03* X010149Y021437D03* X010149Y021457D03* X010149Y021477D03* X010149Y021497D03* X013669Y021497D03* X013669Y021477D03* X013669Y021457D03* X013669Y021437D03* X013669Y021417D03* X013669Y021397D03* X013669Y021377D03* X013669Y021357D03* X013669Y020537D03* X013669Y020517D03* X013669Y020497D03* X013669Y020477D03* X013669Y020457D03* X013669Y020437D03* X013669Y020417D03* X013669Y020397D03* D412* X013429Y019897D03* X013429Y019877D03* X013429Y019857D03* X013429Y019837D03* X013429Y019817D03* X013429Y019797D03* X013429Y019777D03* X013429Y019757D03* X012309Y019737D03* X012309Y019717D03* X012309Y019697D03* X012309Y019677D03* X012309Y019657D03* X012309Y019637D03* X012309Y019617D03* X012309Y019597D03* X013429Y019257D03* X013429Y019237D03* X013429Y019217D03* X013429Y019197D03* X013429Y019177D03* X013429Y019157D03* X013429Y019137D03* X013429Y019117D03* X013909Y018297D03* X013909Y018277D03* X013909Y018257D03* X013909Y018237D03* X013909Y018217D03* X013909Y018197D03* X013909Y018177D03* X013909Y018157D03* X011349Y017497D03* X011349Y017477D03* X011349Y017457D03* X011349Y017437D03* X011349Y017417D03* X011349Y017397D03* X011349Y017377D03* X011349Y017357D03* X012309Y017017D03* X012309Y016997D03* X012309Y016977D03* X012309Y016957D03* X012309Y016937D03* X012309Y016917D03* X012309Y016897D03* X012309Y016877D03* X010389Y016877D03* X010389Y016897D03* X010389Y016917D03* X010389Y016937D03* X010389Y016957D03* X010389Y016977D03* X010389Y016997D03* X010389Y017017D03* X010709Y019437D03* X010709Y019457D03* X010709Y019477D03* X010709Y019497D03* X010709Y019517D03* X010709Y019537D03* X010709Y019557D03* X010709Y019577D03* X011509Y021197D03* X011509Y021217D03* X011509Y021237D03* X011509Y021257D03* X011509Y021277D03* X011509Y021297D03* X011509Y021317D03* X011509Y021337D03* X012469Y021177D03* X012469Y021157D03* X012469Y021137D03* X012469Y021117D03* X012469Y021097D03* X012469Y021077D03* X012469Y021057D03* X012469Y021037D03* D413* X012549Y021017D03* X012549Y020997D03* X012549Y020977D03* X012549Y020957D03* X012549Y020937D03* X012549Y020917D03* X012549Y020897D03* X012549Y020877D03* X012869Y020877D03* X012869Y020897D03* X012869Y020917D03* X012869Y020937D03* X012869Y020957D03* X012869Y020977D03* X012869Y020997D03* X012869Y021017D03* X013189Y021017D03* X013189Y020997D03* X013189Y020977D03* X013189Y020957D03* X013189Y020937D03* X013189Y020917D03* X013189Y020897D03* X013189Y020877D03* X013189Y020857D03* X013189Y020837D03* X013189Y020817D03* X013189Y020797D03* X013189Y020777D03* X013189Y020757D03* X013189Y020737D03* X013189Y020717D03* X013189Y020697D03* X013189Y020677D03* X013189Y020657D03* X013189Y020637D03* X013189Y020617D03* X013189Y020597D03* X013189Y020577D03* X013189Y020557D03* X012869Y020537D03* X012869Y020517D03* X012869Y020497D03* X012869Y020477D03* X012869Y020457D03* X012869Y020437D03* X012869Y020417D03* X012869Y020397D03* X012869Y020377D03* X012869Y020357D03* X012869Y020337D03* X012869Y020317D03* X012869Y020297D03* X012869Y020277D03* X012869Y020257D03* X012869Y020237D03* X012709Y020217D03* X012709Y020197D03* X012709Y020177D03* X012709Y020157D03* X012709Y020137D03* X012709Y020117D03* X012709Y020097D03* X012709Y020077D03* X013029Y020057D03* X013029Y020037D03* X013029Y020017D03* X013029Y019997D03* X013029Y019977D03* X013029Y019957D03* X013029Y019937D03* X013029Y019917D03* X013189Y020077D03* X013189Y020097D03* X013189Y020117D03* X013189Y020137D03* X013189Y020157D03* X013189Y020177D03* X013189Y020197D03* X013189Y020217D03* X013669Y020057D03* X013669Y020037D03* X013669Y020017D03* X013669Y019997D03* X013669Y019977D03* X013669Y019957D03* X013669Y019937D03* X013669Y019917D03* X013669Y019737D03* X013669Y019717D03* X013669Y019697D03* X013669Y019677D03* X013669Y019657D03* X013669Y019637D03* X013669Y019617D03* X013669Y019597D03* X013189Y019577D03* X013189Y019557D03* X013189Y019537D03* X013189Y019517D03* X013189Y019497D03* X013189Y019477D03* X013189Y019457D03* X013189Y019437D03* X012869Y019437D03* X012869Y019457D03* X012869Y019477D03* X012869Y019497D03* X012869Y019517D03* X012869Y019537D03* X012869Y019557D03* X012869Y019577D03* X012869Y019597D03* X012869Y019617D03* X012869Y019637D03* X012869Y019657D03* X012869Y019677D03* X012869Y019697D03* X012869Y019717D03* X012869Y019737D03* X012709Y019417D03* X012709Y019397D03* X012709Y019377D03* X012709Y019357D03* X012709Y019337D03* X012709Y019317D03* X012709Y019297D03* X012709Y019277D03* X012389Y019277D03* X012389Y019297D03* X012389Y019317D03* X012389Y019337D03* X012389Y019357D03* X012389Y019377D03* X012389Y019397D03* X012389Y019417D03* X012069Y019437D03* X012069Y019457D03* X012069Y019477D03* X012069Y019497D03* X012069Y019517D03* X012069Y019537D03* X012069Y019557D03* X012069Y019577D03* X011749Y019577D03* X011749Y019557D03* X011749Y019537D03* X011749Y019517D03* X011749Y019497D03* X011749Y019477D03* X011749Y019457D03* X011749Y019437D03* X011749Y019917D03* X011749Y019937D03* X011749Y019957D03* X011749Y019977D03* X011749Y019997D03* X011749Y020017D03* X011749Y020037D03* X011749Y020057D03* X011909Y020397D03* X011909Y020417D03* X011909Y020437D03* X011909Y020457D03* X011909Y020477D03* X011909Y020497D03* X011909Y020517D03* X011909Y020537D03* X012229Y020537D03* X012229Y020517D03* X012229Y020497D03* X012229Y020477D03* X012229Y020457D03* X012229Y020437D03* X012229Y020417D03* X012229Y020397D03* X012229Y020557D03* X012229Y020577D03* X012229Y020597D03* X012229Y020617D03* X012229Y020637D03* X012229Y020657D03* X012229Y020677D03* X012229Y020697D03* X012549Y020537D03* X012549Y020517D03* X012549Y020497D03* X012549Y020477D03* X012549Y020457D03* X012549Y020437D03* X012549Y020417D03* X012549Y020397D03* X012229Y020057D03* X012229Y020037D03* X012229Y020017D03* X012229Y019997D03* X012229Y019977D03* X012229Y019957D03* X012229Y019937D03* X012229Y019917D03* X011589Y020397D03* X011589Y020417D03* X011589Y020437D03* X011589Y020457D03* X011589Y020477D03* X011589Y020497D03* X011589Y020517D03* X011589Y020537D03* X011269Y020537D03* X011269Y020517D03* X011269Y020497D03* X011269Y020477D03* X011269Y020457D03* X011269Y020437D03* X011269Y020417D03* X011269Y020397D03* X011269Y020557D03* X011269Y020577D03* X011269Y020597D03* X011269Y020617D03* X011269Y020637D03* X011269Y020657D03* X011269Y020677D03* X011269Y020697D03* X010949Y020697D03* X010949Y020677D03* X010949Y020657D03* X010949Y020637D03* X010949Y020617D03* X010949Y020597D03* X010949Y020577D03* X010949Y020557D03* X010949Y020537D03* X010949Y020517D03* X010949Y020497D03* X010949Y020477D03* X010949Y020457D03* X010949Y020437D03* X010949Y020417D03* X010949Y020397D03* X010629Y020557D03* X010629Y020577D03* X010629Y020597D03* X010629Y020617D03* X010629Y020637D03* X010629Y020657D03* X010629Y020677D03* X010629Y020697D03* X010629Y020717D03* X010629Y020737D03* X010629Y020757D03* X010629Y020777D03* X010629Y020797D03* X010629Y020817D03* X010629Y020837D03* X010629Y020857D03* X010629Y020877D03* X010629Y020897D03* X010629Y020917D03* X010629Y020937D03* X010629Y020957D03* X010629Y020977D03* X010629Y020997D03* X010629Y021017D03* X010629Y021037D03* X010629Y021057D03* X010629Y021077D03* X010629Y021097D03* X010629Y021117D03* X010629Y021137D03* X010629Y021157D03* X010629Y021177D03* X010629Y021197D03* X010629Y021217D03* X010629Y021237D03* X010629Y021257D03* X010629Y021277D03* X010629Y021297D03* X010629Y021317D03* X010629Y021337D03* X010949Y021337D03* X010949Y021317D03* X010949Y021297D03* X010949Y021277D03* X010949Y021257D03* X010949Y021237D03* X010949Y021217D03* X010949Y021197D03* X011909Y021357D03* X011909Y021377D03* X011909Y021397D03* X011909Y021417D03* X011909Y021437D03* X011909Y021457D03* X011909Y021477D03* X011909Y021497D03* X012389Y021497D03* X012389Y021477D03* X012389Y021457D03* X012389Y021437D03* X012389Y021417D03* X012389Y021397D03* X012389Y021377D03* X012389Y021357D03* X012709Y021357D03* X012709Y021377D03* X012709Y021397D03* X012709Y021417D03* X012709Y021437D03* X012709Y021457D03* X012709Y021477D03* X012709Y021497D03* X013189Y021337D03* X013189Y021317D03* X013189Y021297D03* X013189Y021277D03* X013189Y021257D03* X013189Y021237D03* X013189Y021217D03* X013189Y021197D03* X013189Y021177D03* X013189Y021157D03* X013189Y021137D03* X013189Y021117D03* X013189Y021097D03* X013189Y021077D03* X013189Y021057D03* X013189Y021037D03* X014149Y021037D03* X014149Y021017D03* X014149Y020997D03* X014149Y020977D03* X014149Y020957D03* X014149Y020937D03* X014149Y020917D03* X014149Y020897D03* X014149Y020877D03* X014149Y020857D03* X014149Y020837D03* X014149Y020817D03* X014149Y020797D03* X014149Y020777D03* X014149Y020757D03* X014149Y020737D03* X014149Y020717D03* X014149Y020697D03* X014149Y020677D03* X014149Y020657D03* X014149Y020637D03* X014149Y020617D03* X014149Y020597D03* X014149Y020577D03* X014149Y020557D03* X014149Y020057D03* X014149Y020037D03* X014149Y020017D03* X014149Y019997D03* X014149Y019977D03* X014149Y019957D03* X014149Y019937D03* X014149Y019917D03* X014149Y019417D03* X014149Y019397D03* X014149Y019377D03* X014149Y019357D03* X014149Y019337D03* X014149Y019317D03* X014149Y019297D03* X014149Y019277D03* X013029Y019097D03* X013029Y019077D03* X013029Y019057D03* X013029Y019037D03* X013029Y019017D03* X013029Y018997D03* X013029Y018977D03* X013029Y018957D03* X013029Y018777D03* X013029Y018757D03* X013029Y018737D03* X013029Y018717D03* X013029Y018697D03* X013029Y018677D03* X013029Y018657D03* X013029Y018637D03* X013189Y018617D03* X013189Y018597D03* X013189Y018577D03* X013189Y018557D03* X013189Y018537D03* X013189Y018517D03* X013189Y018497D03* X013189Y018477D03* X013029Y018457D03* X013029Y018437D03* X013029Y018417D03* X013029Y018397D03* X013029Y018377D03* X013029Y018357D03* X013029Y018337D03* X013029Y018317D03* X012869Y018137D03* X012869Y018117D03* X012869Y018097D03* X012869Y018077D03* X012869Y018057D03* X012869Y018037D03* X012869Y018017D03* X012869Y017997D03* X012549Y018157D03* X012549Y018177D03* X012549Y018197D03* X012549Y018217D03* X012549Y018237D03* X012549Y018257D03* X012549Y018277D03* X012549Y018297D03* X012549Y018317D03* X012549Y018337D03* X012549Y018357D03* X012549Y018377D03* X012549Y018397D03* X012549Y018417D03* X012549Y018437D03* X012549Y018457D03* X012709Y018637D03* X012709Y018657D03* X012709Y018677D03* X012709Y018697D03* X012709Y018717D03* X012709Y018737D03* X012709Y018757D03* X012709Y018777D03* X012229Y018797D03* X012229Y018817D03* X012229Y018837D03* X012229Y018857D03* X012229Y018877D03* X012229Y018897D03* X012229Y018917D03* X012229Y018937D03* X012229Y018957D03* X012229Y018977D03* X012229Y018997D03* X012229Y019017D03* X012229Y019037D03* X012229Y019057D03* X012229Y019077D03* X012229Y019097D03* X011909Y019097D03* X011909Y019077D03* X011909Y019057D03* X011909Y019037D03* X011909Y019017D03* X011909Y018997D03* X011909Y018977D03* X011909Y018957D03* X011749Y018937D03* X011749Y018917D03* X011749Y018897D03* X011749Y018877D03* X011749Y018857D03* X011749Y018837D03* X011749Y018817D03* X011749Y018797D03* X011429Y018797D03* X011429Y018817D03* X011429Y018837D03* X011429Y018857D03* X011429Y018877D03* X011429Y018897D03* X011429Y018917D03* X011429Y018937D03* X011429Y018957D03* X011429Y018977D03* X011429Y018997D03* X011429Y019017D03* X011429Y019037D03* X011429Y019057D03* X011429Y019077D03* X011429Y019097D03* X010949Y018937D03* X010949Y018917D03* X010949Y018897D03* X010949Y018877D03* X010949Y018857D03* X010949Y018837D03* X010949Y018817D03* X010949Y018797D03* X009669Y018777D03* X009669Y018757D03* X009669Y018737D03* X009669Y018717D03* X009669Y018697D03* X009669Y018677D03* X009669Y018657D03* X009669Y018637D03* X009669Y018617D03* X009669Y018597D03* X009669Y018577D03* X009669Y018557D03* X009669Y018537D03* X009669Y018517D03* X009669Y018497D03* X009669Y018477D03* X009669Y018137D03* X009669Y018117D03* X009669Y018097D03* X009669Y018077D03* X009669Y018057D03* X009669Y018037D03* X009669Y018017D03* X009669Y017997D03* X009669Y017657D03* X009669Y017637D03* X009669Y017617D03* X009669Y017597D03* X009669Y017577D03* X009669Y017557D03* X009669Y017537D03* X009669Y017517D03* X010629Y017837D03* X010629Y017857D03* X010629Y017877D03* X010629Y017897D03* X010629Y017917D03* X010629Y017937D03* X010629Y017957D03* X010629Y017977D03* X010949Y017977D03* X010949Y017957D03* X010949Y017937D03* X010949Y017917D03* X010949Y017897D03* X010949Y017877D03* X010949Y017857D03* X010949Y017837D03* X010949Y017817D03* X010949Y017797D03* X010949Y017777D03* X010949Y017757D03* X010949Y017737D03* X010949Y017717D03* X010949Y017697D03* X010949Y017677D03* X010789Y017497D03* X010789Y017477D03* X010789Y017457D03* X010789Y017437D03* X010789Y017417D03* X010789Y017397D03* X010789Y017377D03* X010789Y017357D03* X011269Y017177D03* X011269Y017157D03* X011269Y017137D03* X011269Y017117D03* X011269Y017097D03* X011269Y017077D03* X011269Y017057D03* X011269Y017037D03* X011589Y017017D03* X011589Y016997D03* X011589Y016977D03* X011589Y016957D03* X011589Y016937D03* X011589Y016917D03* X011589Y016897D03* X011589Y016877D03* X011589Y017197D03* X011589Y017217D03* X011589Y017237D03* X011589Y017257D03* X011589Y017277D03* X011589Y017297D03* X011589Y017317D03* X011589Y017337D03* X012069Y017517D03* X012069Y017537D03* X012069Y017557D03* X012069Y017577D03* X012069Y017597D03* X012069Y017617D03* X012069Y017637D03* X012069Y017657D03* X011749Y017837D03* X011749Y017857D03* X011749Y017877D03* X011749Y017897D03* X011749Y017917D03* X011749Y017937D03* X011749Y017957D03* X011749Y017977D03* X011269Y017817D03* X011269Y017797D03* X011269Y017777D03* X011269Y017757D03* X011269Y017737D03* X011269Y017717D03* X011269Y017697D03* X011269Y017677D03* X010949Y017997D03* X010949Y018017D03* X010949Y018037D03* X010949Y018057D03* X010949Y018077D03* X010949Y018097D03* X010949Y018117D03* X010949Y018137D03* X012549Y017817D03* X012549Y017797D03* X012549Y017777D03* X012549Y017757D03* X012549Y017737D03* X012549Y017717D03* X012549Y017697D03* X012549Y017677D03* X012709Y017657D03* X012709Y017637D03* X012709Y017617D03* X012709Y017597D03* X012709Y017577D03* X012709Y017557D03* X012709Y017537D03* X012709Y017517D03* X012709Y017497D03* X012709Y017477D03* X012709Y017457D03* X012709Y017437D03* X012709Y017417D03* X012709Y017397D03* X012709Y017377D03* X012709Y017357D03* X012869Y017177D03* X012869Y017157D03* X012869Y017137D03* X012869Y017117D03* X012869Y017097D03* X012869Y017077D03* X012869Y017057D03* X012869Y017037D03* X013189Y017037D03* X013189Y017057D03* X013189Y017077D03* X013189Y017097D03* X013189Y017117D03* X013189Y017137D03* X013189Y017157D03* X013189Y017177D03* X013189Y017197D03* X013189Y017217D03* X013189Y017237D03* X013189Y017257D03* X013189Y017277D03* X013189Y017297D03* X013189Y017317D03* X013189Y017337D03* X013189Y017357D03* X013189Y017377D03* X013189Y017397D03* X013189Y017417D03* X013189Y017437D03* X013189Y017457D03* X013189Y017477D03* X013189Y017497D03* X013189Y017517D03* X013189Y017537D03* X013189Y017557D03* X013189Y017577D03* X013189Y017597D03* X013189Y017617D03* X013189Y017637D03* X013189Y017657D03* X013189Y017677D03* X013189Y017697D03* X013189Y017717D03* X013189Y017737D03* X013189Y017757D03* X013189Y017777D03* X013189Y017797D03* X013189Y017817D03* X014149Y017817D03* X014149Y017797D03* X014149Y017777D03* X014149Y017757D03* X014149Y017737D03* X014149Y017717D03* X014149Y017697D03* X014149Y017677D03* X014149Y017657D03* X014149Y017637D03* X014149Y017617D03* X014149Y017597D03* X014149Y017577D03* X014149Y017557D03* X014149Y017537D03* X014149Y017517D03* X014149Y017497D03* X014149Y017477D03* X014149Y017457D03* X014149Y017437D03* X014149Y017417D03* X014149Y017397D03* X014149Y017377D03* X014149Y017357D03* X014149Y017337D03* X014149Y017317D03* X014149Y017297D03* X014149Y017277D03* X014149Y017257D03* X014149Y017237D03* X014149Y017217D03* X014149Y017197D03* X014149Y017177D03* X014149Y017157D03* X014149Y017137D03* X014149Y017117D03* X014149Y017097D03* X014149Y017077D03* X014149Y017057D03* X014149Y017037D03* X012389Y017037D03* X012389Y017057D03* X012389Y017077D03* X012389Y017097D03* X012389Y017117D03* X012389Y017137D03* X012389Y017157D03* X012389Y017177D03* X010949Y017017D03* X010949Y016997D03* X010949Y016977D03* X010949Y016957D03* X010949Y016937D03* X010949Y016917D03* X010949Y016897D03* X010949Y016877D03* X009669Y016877D03* X009669Y016897D03* X009669Y016917D03* X009669Y016937D03* X009669Y016957D03* X009669Y016977D03* X009669Y016997D03* X009669Y017017D03* X013829Y018317D03* X013829Y018337D03* X013829Y018357D03* X013829Y018377D03* X013829Y018397D03* X013829Y018417D03* X013829Y018437D03* X013829Y018457D03* X013989Y018637D03* X013989Y018657D03* X013989Y018677D03* X013989Y018697D03* X013989Y018717D03* X013989Y018737D03* X013989Y018757D03* X013989Y018777D03* X013349Y018777D03* X013349Y018757D03* X013349Y018737D03* X013349Y018717D03* X013349Y018697D03* X013349Y018677D03* X013349Y018657D03* X013349Y018637D03* X011109Y019597D03* X011109Y019617D03* X011109Y019637D03* X011109Y019657D03* X011109Y019677D03* X011109Y019697D03* X011109Y019717D03* X011109Y019737D03* X011109Y019757D03* X011109Y019777D03* X011109Y019797D03* X011109Y019817D03* X011109Y019837D03* X011109Y019857D03* X011109Y019877D03* X011109Y019897D03* X010629Y019417D03* X010629Y019397D03* X010629Y019377D03* X010629Y019357D03* X010629Y019337D03* X010629Y019317D03* X010629Y019297D03* X010629Y019277D03* X010149Y019277D03* X010149Y019297D03* X010149Y019317D03* X010149Y019337D03* X010149Y019357D03* X010149Y019377D03* X010149Y019397D03* X010149Y019417D03* X010149Y019437D03* X010149Y019457D03* X010149Y019477D03* X010149Y019497D03* X010149Y019517D03* X010149Y019537D03* X010149Y019557D03* X010149Y019577D03* X010149Y019597D03* X010149Y019617D03* X010149Y019637D03* X010149Y019657D03* X010149Y019677D03* X010149Y019697D03* X010149Y019717D03* X010149Y019737D03* X010149Y020077D03* X010149Y020097D03* X010149Y020117D03* X010149Y020137D03* X010149Y020157D03* X010149Y020177D03* X010149Y020197D03* X010149Y020217D03* X009669Y020557D03* X009669Y020577D03* X009669Y020597D03* X009669Y020617D03* X009669Y020637D03* X009669Y020657D03* X009669Y020677D03* X009669Y020697D03* X009669Y020717D03* X009669Y020737D03* X009669Y020757D03* X009669Y020777D03* X009669Y020797D03* X009669Y020817D03* X009669Y020837D03* X009669Y020857D03* X009669Y020877D03* X009669Y020897D03* X009669Y020917D03* X009669Y020937D03* X009669Y020957D03* X009669Y020977D03* X009669Y020997D03* X009669Y021017D03* X009669Y021037D03* X009669Y021057D03* X009669Y021077D03* X009669Y021097D03* X009669Y021117D03* X009669Y021137D03* X009669Y021157D03* X009669Y021177D03* X009669Y021197D03* X009669Y021217D03* X009669Y021237D03* X009669Y021257D03* X009669Y021277D03* X009669Y021297D03* X009669Y021317D03* X009669Y021337D03* X014149Y021337D03* X014149Y021317D03* X014149Y021297D03* X014149Y021277D03* X014149Y021257D03* X014149Y021237D03* X014149Y021217D03* X014149Y021197D03* X014149Y021177D03* X014149Y021157D03* X014149Y021137D03* X014149Y021117D03* X014149Y021097D03* X014149Y021077D03* X014149Y021057D03* X009669Y019897D03* X009669Y019877D03* X009669Y019857D03* X009669Y019837D03* X009669Y019817D03* X009669Y019797D03* X009669Y019777D03* X009669Y019757D03* X009829Y019577D03* X009829Y019557D03* X009829Y019537D03* X009829Y019517D03* X009829Y019497D03* X009829Y019477D03* X009829Y019457D03* X009829Y019437D03* X009669Y019417D03* X009669Y019397D03* X009669Y019377D03* X009669Y019357D03* X009669Y019337D03* X009669Y019317D03* X009669Y019297D03* X009669Y019277D03* X009669Y019257D03* X009669Y019237D03* X009669Y019217D03* X009669Y019197D03* X009669Y019177D03* X009669Y019157D03* X009669Y019137D03* X009669Y019117D03* X009669Y019097D03* X009669Y019077D03* X009669Y019057D03* X009669Y019037D03* X009669Y019017D03* X009669Y018997D03* X009669Y018977D03* X009669Y018957D03* D414* X010069Y019117D03* X010069Y019137D03* X010069Y019157D03* X010069Y019177D03* X010069Y019197D03* X010069Y019217D03* X010069Y019237D03* X010069Y019257D03* X010229Y019097D03* X010229Y019077D03* X010229Y019057D03* X010229Y019037D03* X010229Y019017D03* X010229Y018997D03* X010229Y018977D03* X010229Y018957D03* X010069Y018777D03* X010069Y018757D03* X010069Y018737D03* X010069Y018717D03* X010069Y018697D03* X010069Y018677D03* X010069Y018657D03* X010069Y018637D03* X010549Y018637D03* X010549Y018657D03* X010549Y018677D03* X010549Y018697D03* X010549Y018717D03* X010549Y018737D03* X010549Y018757D03* X010549Y018777D03* X010549Y018797D03* X010549Y018817D03* X010549Y018837D03* X010549Y018857D03* X010549Y018877D03* X010549Y018897D03* X010549Y018917D03* X010549Y018937D03* X010549Y019117D03* X010549Y019137D03* X010549Y019157D03* X010549Y019177D03* X010549Y019197D03* X010549Y019217D03* X010549Y019237D03* X010549Y019257D03* X011029Y019257D03* X011029Y019237D03* X011029Y019217D03* X011029Y019197D03* X011029Y019177D03* X011029Y019157D03* X011029Y019137D03* X011029Y019117D03* X011029Y018777D03* X011029Y018757D03* X011029Y018737D03* X011029Y018717D03* X011029Y018697D03* X011029Y018677D03* X011029Y018657D03* X011029Y018637D03* X011189Y018617D03* X011189Y018597D03* X011189Y018577D03* X011189Y018557D03* X011189Y018537D03* X011189Y018517D03* X011189Y018497D03* X011189Y018477D03* X011669Y018297D03* X011669Y018277D03* X011669Y018257D03* X011669Y018237D03* X011669Y018217D03* X011669Y018197D03* X011669Y018177D03* X011669Y018157D03* X011349Y017977D03* X011349Y017957D03* X011349Y017937D03* X011349Y017917D03* X011349Y017897D03* X011349Y017877D03* X011349Y017857D03* X011349Y017837D03* X011989Y017817D03* X011989Y017797D03* X011989Y017777D03* X011989Y017757D03* X011989Y017737D03* X011989Y017717D03* X011989Y017697D03* X011989Y017677D03* X012149Y017837D03* X012149Y017857D03* X012149Y017877D03* X012149Y017897D03* X012149Y017917D03* X012149Y017937D03* X012149Y017957D03* X012149Y017977D03* X012469Y017997D03* X012469Y018017D03* X012469Y018037D03* X012469Y018057D03* X012469Y018077D03* X012469Y018097D03* X012469Y018117D03* X012469Y018137D03* X012629Y017977D03* X012629Y017957D03* X012629Y017937D03* X012629Y017917D03* X012629Y017897D03* X012629Y017877D03* X012629Y017857D03* X012629Y017837D03* X012789Y017337D03* X012789Y017317D03* X012789Y017297D03* X012789Y017277D03* X012789Y017257D03* X012789Y017237D03* X012789Y017217D03* X012789Y017197D03* X012309Y017197D03* X012309Y017217D03* X012309Y017237D03* X012309Y017257D03* X012309Y017277D03* X012309Y017297D03* X012309Y017317D03* X012309Y017337D03* X011669Y017177D03* X011669Y017157D03* X011669Y017137D03* X011669Y017117D03* X011669Y017097D03* X011669Y017077D03* X011669Y017057D03* X011669Y017037D03* X010389Y017197D03* X010389Y017217D03* X010389Y017237D03* X010389Y017257D03* X010389Y017277D03* X010389Y017297D03* X010389Y017317D03* X010389Y017337D03* X010229Y017677D03* X010229Y017697D03* X010229Y017717D03* X010229Y017737D03* X010229Y017757D03* X010229Y017777D03* X010229Y017797D03* X010229Y017817D03* X010229Y017997D03* X010229Y018017D03* X010229Y018037D03* X010229Y018057D03* X010229Y018077D03* X010229Y018097D03* X010229Y018117D03* X010229Y018137D03* X012629Y018957D03* X012629Y018977D03* X012629Y018997D03* X012629Y019017D03* X012629Y019037D03* X012629Y019057D03* X012629Y019077D03* X012629Y019097D03* X012789Y019117D03* X012789Y019137D03* X012789Y019157D03* X012789Y019177D03* X012789Y019197D03* X012789Y019217D03* X012789Y019237D03* X012789Y019257D03* X013589Y019437D03* X013589Y019457D03* X013589Y019477D03* X013589Y019497D03* X013589Y019517D03* X013589Y019537D03* X013589Y019557D03* X013589Y019577D03* X014069Y019577D03* X014069Y019557D03* X014069Y019537D03* X014069Y019517D03* X014069Y019497D03* X014069Y019477D03* X014069Y019457D03* X014069Y019437D03* X014069Y019757D03* X014069Y019777D03* X014069Y019797D03* X014069Y019817D03* X014069Y019837D03* X014069Y019857D03* X014069Y019877D03* X014069Y019897D03* X013909Y020077D03* X013909Y020097D03* X013909Y020117D03* X013909Y020137D03* X013909Y020157D03* X013909Y020177D03* X013909Y020197D03* X013909Y020217D03* X012789Y020557D03* X012789Y020577D03* X012789Y020597D03* X012789Y020617D03* X012789Y020637D03* X012789Y020657D03* X012789Y020677D03* X012789Y020697D03* X011989Y020877D03* X011989Y020897D03* X011989Y020917D03* X011989Y020937D03* X011989Y020957D03* X011989Y020977D03* X011989Y020997D03* X011989Y021017D03* X011349Y020857D03* X011349Y020837D03* X011349Y020817D03* X011349Y020797D03* X011349Y020777D03* X011349Y020757D03* X011349Y020737D03* X011349Y020717D03* X011989Y020377D03* X011989Y020357D03* X011989Y020337D03* X011989Y020317D03* X011989Y020297D03* X011989Y020277D03* X011989Y020257D03* X011989Y020237D03* X011029Y020057D03* X011029Y020037D03* X011029Y020017D03* X011029Y019997D03* X011029Y019977D03* X011029Y019957D03* X011029Y019937D03* X011029Y019917D03* X010549Y019917D03* X010549Y019937D03* X010549Y019957D03* X010549Y019977D03* X010549Y019997D03* X010549Y020017D03* X010549Y020037D03* X010549Y020057D03* X010549Y020077D03* X010549Y020097D03* X010549Y020117D03* X010549Y020137D03* X010549Y020157D03* X010549Y020177D03* X010549Y020197D03* X010549Y020217D03* X009749Y020057D03* X009749Y020037D03* X009749Y020017D03* X009749Y019997D03* X009749Y019977D03* X009749Y019957D03* X009749Y019937D03* X009749Y019917D03* X010389Y019897D03* X010389Y019877D03* X010389Y019857D03* X010389Y019837D03* X010389Y019817D03* X010389Y019797D03* X010389Y019777D03* X010389Y019757D03* X011669Y019737D03* X011669Y019717D03* X011669Y019697D03* X011669Y019677D03* X011669Y019657D03* X011669Y019637D03* X011669Y019617D03* X011669Y019597D03* X012629Y019757D03* X012629Y019777D03* X012629Y019797D03* X012629Y019817D03* X012629Y019837D03* X012629Y019857D03* X012629Y019877D03* X012629Y019897D03* X014069Y018937D03* X014069Y018917D03* X014069Y018897D03* X014069Y018877D03* X014069Y018857D03* X014069Y018837D03* X014069Y018817D03* X014069Y018797D03* X014069Y018617D03* X014069Y018597D03* X014069Y018577D03* X014069Y018557D03* X014069Y018537D03* X014069Y018517D03* X014069Y018497D03* X014069Y018477D03* X013429Y018457D03* X013429Y018437D03* X013429Y018417D03* X013429Y018397D03* X013429Y018377D03* X013429Y018357D03* X013429Y018337D03* X013429Y018317D03* D415* X013029Y018297D03* X013029Y018277D03* X013029Y018257D03* X013029Y018237D03* X013029Y018217D03* X013029Y018197D03* X013029Y018177D03* X013029Y018157D03* X012549Y018477D03* X012549Y018497D03* X012549Y018517D03* X012549Y018537D03* X012549Y018557D03* X012549Y018577D03* X012549Y018597D03* X012549Y018617D03* X012069Y018637D03* X012069Y018657D03* X012069Y018677D03* X012069Y018697D03* X012069Y018717D03* X012069Y018737D03* X012069Y018757D03* X012069Y018777D03* X011909Y018617D03* X011909Y018597D03* X011909Y018577D03* X011909Y018557D03* X011909Y018537D03* X011909Y018517D03* X011909Y018497D03* X011909Y018477D03* X011749Y018137D03* X011749Y018117D03* X011749Y018097D03* X011749Y018077D03* X011749Y018057D03* X011749Y018037D03* X011749Y018017D03* X011749Y017997D03* X013669Y017657D03* X013669Y017637D03* X013669Y017617D03* X013669Y017597D03* X013669Y017577D03* X013669Y017557D03* X013669Y017537D03* X013669Y017517D03* X013669Y017497D03* X013669Y017477D03* X013669Y017457D03* X013669Y017437D03* X013669Y017417D03* X013669Y017397D03* X013669Y017377D03* X013669Y017357D03* X013669Y017337D03* X013669Y017317D03* X013669Y017297D03* X013669Y017277D03* X013669Y017257D03* X013669Y017237D03* X013669Y017217D03* X013669Y017197D03* X010949Y017197D03* X010949Y017217D03* X010949Y017237D03* X010949Y017257D03* X010949Y017277D03* X010949Y017297D03* X010949Y017317D03* X010949Y017337D03* X010789Y017177D03* X010789Y017157D03* X010789Y017137D03* X010789Y017117D03* X010789Y017097D03* X010789Y017077D03* X010789Y017057D03* X010789Y017037D03* X009829Y017197D03* X009829Y017217D03* X009829Y017237D03* X009829Y017257D03* X009829Y017277D03* X009829Y017297D03* X009829Y017317D03* X009829Y017337D03* X013349Y018797D03* X013349Y018817D03* X013349Y018837D03* X013349Y018857D03* X013349Y018877D03* X013349Y018897D03* X013349Y018917D03* X013349Y018937D03* X013669Y018957D03* X013669Y018977D03* X013669Y018997D03* X013669Y019017D03* X013669Y019037D03* X013669Y019057D03* X013669Y019077D03* X013669Y019097D03* X013669Y019277D03* X013669Y019297D03* X013669Y019317D03* X013669Y019337D03* X013669Y019357D03* X013669Y019377D03* X013669Y019397D03* X013669Y019417D03* X011589Y019757D03* X011589Y019777D03* X011589Y019797D03* X011589Y019817D03* X011589Y019837D03* X011589Y019857D03* X011589Y019877D03* X011589Y019897D03* X010629Y019737D03* X010629Y019717D03* X010629Y019697D03* X010629Y019677D03* X010629Y019657D03* X010629Y019637D03* X010629Y019617D03* X010629Y019597D03* X010949Y019097D03* X010949Y019077D03* X010949Y019057D03* X010949Y019037D03* X010949Y019017D03* X010949Y018997D03* X010949Y018977D03* X010949Y018957D03* X011749Y020557D03* X011749Y020577D03* X011749Y020597D03* X011749Y020617D03* X011749Y020637D03* X011749Y020657D03* X011749Y020677D03* X011749Y020697D03* X011269Y020877D03* X011269Y020897D03* X011269Y020917D03* X011269Y020937D03* X011269Y020957D03* X011269Y020977D03* X011269Y020997D03* X011269Y021017D03* X010149Y021017D03* X010149Y020997D03* X010149Y020977D03* X010149Y020957D03* X010149Y020937D03* X010149Y020917D03* X010149Y020897D03* X010149Y020877D03* X010149Y020857D03* X010149Y020837D03* X010149Y020817D03* X010149Y020797D03* X010149Y020777D03* X010149Y020757D03* X010149Y020737D03* X010149Y020717D03* X010149Y021037D03* X010149Y021057D03* X010149Y021077D03* X010149Y021097D03* X010149Y021117D03* X010149Y021137D03* X010149Y021157D03* X010149Y021177D03* X013669Y021177D03* X013669Y021157D03* X013669Y021137D03* X013669Y021117D03* X013669Y021097D03* X013669Y021077D03* X013669Y021057D03* X013669Y021037D03* X013669Y021017D03* X013669Y020997D03* X013669Y020977D03* X013669Y020957D03* X013669Y020937D03* X013669Y020917D03* X013669Y020897D03* X013669Y020877D03* X013669Y020857D03* X013669Y020837D03* X013669Y020817D03* X013669Y020797D03* X013669Y020777D03* X013669Y020757D03* X013669Y020737D03* X013669Y020717D03* D416* X011269Y021037D03* X011269Y021057D03* X011269Y021077D03* X011269Y021097D03* X011269Y021117D03* X011269Y021137D03* X011269Y021157D03* X011269Y021177D03* X011909Y019257D03* X011909Y019237D03* X011909Y019217D03* X011909Y019197D03* X011909Y019177D03* X011909Y019157D03* X011909Y019137D03* X011909Y019117D03* X009989Y017977D03* X009989Y017957D03* X009989Y017937D03* X009989Y017917D03* X009989Y017897D03* X009989Y017877D03* X009989Y017857D03* X009989Y017837D03* X010149Y017497D03* X010149Y017477D03* X010149Y017457D03* X010149Y017437D03* X010149Y017417D03* X010149Y017397D03* X010149Y017377D03* X010149Y017357D03* D417* X010949Y017517D03* X010949Y017537D03* X010949Y017557D03* X010949Y017577D03* X010949Y017597D03* X010949Y017617D03* X010949Y017637D03* X010949Y017657D03* D418* X010549Y018157D03* X010549Y018177D03* X010549Y018197D03* X010549Y018217D03* X010549Y018237D03* X010549Y018257D03* X010549Y018277D03* X010549Y018297D03* D419* X011509Y019277D03* X011509Y019297D03* X011509Y019317D03* X011509Y019337D03* X011509Y019357D03* X011509Y019377D03* X011509Y019397D03* X011509Y019417D03* D420* X011669Y020077D03* X011669Y020097D03* X011669Y020117D03* X011669Y020137D03* X011669Y020157D03* X011669Y020177D03* X011669Y020197D03* X011669Y020217D03* M02*	zz314326255--adkping	adkping/arduino-accessory/adk_release_0512/ADK_release_0512/hardware/fab/shield/ashield_blk.pls	PLSQL	oos	99,785
/* * \file adkping.c * \author David Siorpaes * * Inspired from http://android.serverbox.ch/?p=262#comments / #include <stdio.h> #include <usb.h> #include <libusb.h> #include <string.h> #include <unistd.h> / Nexus-One IDs / #define VID 0x18D1 #define PID 0x4E11 / PID used with USB debugging disabled / #define PID_DBG 0x4E12 / PID used with USB debugging enabled / / Google Accessory IDs / #define ACCESSORY_VID 0x18D1 #define ACCESSORY_PID 0x2D00 #define ACCESSORY_PID_DBG 0x2D01 / Nexus-One Accessory device end points / #define IN 0x83 #define OUT 0x03 unsigned char buffer[128]; static int mainPhase(); static int deInit(void); static void error(int code); static void status(int code); static int setupAccessory( char manufacturer, char* modelName, char* description, char* version, char* uri, char* serialNumber); static struct libusb_device_handle* handle; int main(int argc, char argv[]) { int err; libusb_init(NULL); libusb_set_debug(NULL, 3); / Try to open directly accessory. If it's not there, try to switch phone to it / handle = libusb_open_device_with_vid_pid(NULL, ACCESSORY_VID, ACCESSORY_PID_DBG); //if(handle) //libusb_reset_device(handle); if(handle == NULL){ printf("Device not in Accessory mode. Trying to switch it to it...\n"); err = setupAccessory("STMicroelectronics", "adkping", "Just pings data", "2.0", "http://www.st.com", "1234567890123456"); if(err < 0){ fprintf(stdout, "Sorry, can't set up accessory, giving up\n"); deInit(); return -1; } } / Do some stuff / if(mainPhase() < 0){ fprintf(stdout, "Error during main phase\n"); deInit(); return -1; } deInit(); fprintf(stdout, "Done, no errors\n"); return 0; } static int mainPhase(){ int response = 0; static int transferred; int i; struct libusb_config_descriptor config_desc; const struct libusb_interface_descriptor* interface_desc; response = libusb_get_descriptor(handle, LIBUSB_DT_CONFIG, 0, buffer, LIBUSB_DT_CONFIG_SIZE); //response = libusb_get_descriptor(handle, LIBUSB_DT_INTERFACE, 0, buffer, LIBUSB_DT_INTERFACE_SIZE); if(response < 0){error(response);return -1;} config_desc = (struct libusb_config_descriptor)buffer; printf("bLength %i\n", config_desc->bLength); printf("bNumInterfaces %i\n", config_desc->bNumInterfaces); printf("MaxPower %i\n", config_desc->MaxPower); / Send our host name to device / memset(buffer, 0x0, sizeof(buffer)); gethostname((char)buffer, sizeof(buffer)); response = libusb_bulk_transfer(handle, OUT, buffer, sizeof(buffer), &transferred, 5000); if(response < 0){ error(response); return -1; } else{ printf("Done, transferred %i bytes\n", transferred); status(response); } /* Receive back device response / memset(buffer, 0x0, sizeof(buffer)); response = libusb_bulk_transfer(handle, IN, buffer, sizeof(buffer), &transferred, 5000); if(response < 0){ error(response); return -1; } else{ printf("Done, received %i bytes\n", transferred); status(response); } printf("Received: %s\n", buffer); for(i=0; i<sizeof(buffer); i++) printf("%i ", buffer[i]); printf("\n"); return 0; } static int deInit(){ //TODO free all transfers individually... //if(ctrlTransfer != NULL) // libusb_free_transfer(ctrlTransfer); if(handle != NULL){ libusb_release_interface (handle, 0); libusb_close(handle); } libusb_exit(NULL); return 0; } int connectAccessory(void) { int response; int tries = 5; / Try connecting to Accessory device with proper PID/VID / for(;;){ tries--; if((handle = libusb_open_device_with_vid_pid(NULL, ACCESSORY_VID, ACCESSORY_PID_DBG)) == NULL){ if(tries < 0){ return -1; } }else{ break; } sleep(1); } / Set configuration to 1 as per ADK protocol / response = libusb_set_configuration(handle, 1); if(response < 0){ error(response); return -1; } response = libusb_claim_interface(handle, 0); if(response < 0){ error(response); return -1; } fprintf(stdout, "Interface claimed, ready to transfer data\n"); return 0; } /* * Attempts to put USB device in Accessory mode. * On success, PID/VID switches to accessory PID/VID * and proper application is launched. Application must match * Accessory manufacturer, model and version which are defined in * "android.hardware.us.action.USB_ACCESSORY_ATTACHED" meta-data / static int setupAccessory( char manufacturer, char* modelName, char* description, char* version, char* uri, char* serialNumber){ unsigned char ioBuffer[2]; int devVersion; int response; /* Open Nexus One device / if((handle = libusb_open_device_with_vid_pid(NULL, VID, PID_DBG)) == NULL){ fprintf(stdout, "Problem acquireing handle\n"); return -1; } libusb_claim_interface(handle, 0); //libusb_reset_device(handle); / Send GET_PROTOCOL (0x51) request to figure out whether the device supports ADK * If protocol is not 0 the device supports it / response = libusb_control_transfer( handle, //handle 0xC0, //bmRequestType 51, //bRequest 0, //wValue 0, //wIndex ioBuffer, //data 2, //wLength 0 //timeout ); if(response < 0){ error(response); return -1; } / Extract protocol version to check whether Accessory mode is supported / devVersion = ioBuffer[1] << 8 \| ioBuffer[0]; fprintf(stdout,"Version Code Device: %d\n", devVersion); if(devVersion == 0){ fprintf(stdout,"Sorry, device is not supporting Accessory mode\n"); return -1; } usleep(1000);//sometimes hangs on the next transfer :( / Accessory mode is supported: send out IDs / response = libusb_control_transfer(handle,0x40,52,0,0,(unsigned char)manufacturer,strlen(manufacturer),0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,1,(unsigned char)modelName,strlen(modelName)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,2,(unsigned char)description,strlen(description)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,3,(unsigned char)version,strlen(version)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,4,(unsigned char)uri,strlen(uri)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,5,(unsigned char)serialNumber,strlen(serialNumber)+1,0); if(response < 0){error(response);return -1;} fprintf(stdout,"Accessory Identification sent\n"); / Request device to start up in accessory mode / response = libusb_control_transfer(handle,0x40,53,0,0,NULL,0,0); if(response < 0){ error(response); return -1; } fprintf(stdout,"Attempted to put device into accessory mode\n"); / Close phone handles as we need to connect to Accessory device in a while */ if(handle != NULL){ libusb_release_interface(handle, 0); libusb_close(handle); } response = connectAccessory(); if(response < 0){ fprintf(stderr, "Could not connect to Accessory device\n"); return -1; } return 0; } static void error(int code){ fprintf(stdout,"\n"); switch(code){ case LIBUSB_ERROR_IO: fprintf(stdout,"Error: LIBUSB_ERROR_IO\nInput/output error.\n"); break; case LIBUSB_ERROR_INVALID_PARAM: fprintf(stdout,"Error: LIBUSB_ERROR_INVALID_PARAM\nInvalid parameter.\n"); break; case LIBUSB_ERROR_ACCESS: fprintf(stdout,"Error: LIBUSB_ERROR_ACCESS\nAccess denied (insufficient permissions).\n"); break; case LIBUSB_ERROR_NO_DEVICE: fprintf(stdout,"Error: LIBUSB_ERROR_NO_DEVICE\nNo such device (it may have been disconnected).\n"); break; case LIBUSB_ERROR_NOT_FOUND: fprintf(stdout,"Error: LIBUSB_ERROR_NOT_FOUND\nEntity not found.\n"); break; case LIBUSB_ERROR_BUSY: fprintf(stdout,"Error: LIBUSB_ERROR_BUSY\nResource busy.\n"); break; case LIBUSB_ERROR_TIMEOUT: fprintf(stdout,"Error: LIBUSB_ERROR_TIMEOUT\nOperation timed out.\n"); break; case LIBUSB_ERROR_OVERFLOW: fprintf(stdout,"Error: LIBUSB_ERROR_OVERFLOW\nOverflow.\n"); break; case LIBUSB_ERROR_PIPE: fprintf(stdout,"Error: LIBUSB_ERROR_PIPE\nPipe error.\n"); break; case LIBUSB_ERROR_INTERRUPTED: fprintf(stdout,"Error:LIBUSB_ERROR_INTERRUPTED\nSystem call interrupted (perhaps due to signal).\n"); break; case LIBUSB_ERROR_NO_MEM: fprintf(stdout,"Error: LIBUSB_ERROR_NO_MEM\nInsufficient memory.\n"); break; case LIBUSB_ERROR_NOT_SUPPORTED: fprintf(stdout,"Error: LIBUSB_ERROR_NOT_SUPPORTED\nOperation not supported or unimplemented on this platform.\n"); break; case LIBUSB_ERROR_OTHER: fprintf(stdout,"Error: LIBUSB_ERROR_OTHER\nOther error.\n"); break; default: fprintf(stdout, "Error: unkown error\n"); } } static void status(int code){ fprintf(stdout,"\n"); switch(code){ case LIBUSB_TRANSFER_COMPLETED: fprintf(stdout,"Success: LIBUSB_TRANSFER_COMPLETED\nTransfer completed.\n"); break; case LIBUSB_TRANSFER_ERROR: fprintf(stdout,"Error: LIBUSB_TRANSFER_ERROR\nTransfer failed.\n"); break; case LIBUSB_TRANSFER_TIMED_OUT: fprintf(stdout,"Error: LIBUSB_TRANSFER_TIMED_OUT\nTransfer timed out.\n"); break; case LIBUSB_TRANSFER_CANCELLED: fprintf(stdout,"Error: LIBUSB_TRANSFER_CANCELLED\nTransfer was cancelled.\n"); break; case LIBUSB_TRANSFER_STALL: fprintf(stdout,"Error: LIBUSB_TRANSFER_STALL\nFor bulk/interrupt endpoints: halt condition detected (endpoint stalled).\nFor control endpoints: control request not supported.\n"); break; case LIBUSB_TRANSFER_NO_DEVICE: fprintf(stdout,"Error: LIBUSB_TRANSFER_NO_DEVICE\nDevice was disconnected.\n"); break; case LIBUSB_TRANSFER_OVERFLOW: fprintf(stdout,"Error: LIBUSB_TRANSFER_OVERFLOW\nDevice sent more data than requested.\n"); break; default: fprintf(stdout,"Error: unknown error\nTry again(?)\n"); break; } }	zz314326255--adkping	adkping/pc-accessory/adkping.c	C	oos	9,881
#include <stdio.h> #include <libusb.h> #include <string.h> #define ENDPOINT_BULK_IN 0x83 #define ENDPOINT_BULK_OUT 0x03 // Have tried 0x00, 0x01 and 0x02 #define VID 0x18D1 #define PID 0x4E11 #define ACCESSORY_PID 0x2D00 #define ACCESSORY_ADB_PID 0x2D01 // Can't get this to work, if ADB is active, can't get handle on device /* ON OSX gcc adktest.c -I/usr/local/include -o adktest -lusb-1.0.0 -I/usr/local/include -I/usr/local/include/libusb-1.0 ON UBUNTU gcc adktest.c -I/usr/include -o adktest -lusb-1.0 -I/usr/include -I/usr/include/libusb-1.0 Testing on Nexus One with Gingerbread 2.3.4 / static int transferTest(); static int init(void); static int shutdown(void); static void error(int code); static void status(int code); static int setupAccessory( const char manufacturer, const char* modelName, const char* description, const char* version, const char* uri, const char* serialNumber); //static static struct libusb_device_handle* handle; int main (int argc, char argv[]){ if(init() < 0) return; if(setupAccessory( "PCHost", "PCHost1", "Description", "1.0", "http://www.mycompany.com", "SerialNumber") < 0){ fprintf(stdout, "Error setting up accessory\n"); shutdown(); return -1; }; if(transferTest() < 0){ fprintf(stdout, "Error in transferTest\n"); shutdown(); return -1; } shutdown(); fprintf(stdout, "Finished\n"); return 0; } static int transferTest(){ // TEST BULK IN/OUT const static int PACKET_BULK_LEN=64; const static int TIMEOUT=5000; int r,i; int transferred; char answer[PACKET_BULK_LEN]; char question[PACKET_BULK_LEN]; for (i=0;i<PACKET_BULK_LEN; i++) question[i]=i; // FAILS HERE* r = libusb_bulk_transfer(handle, ENDPOINT_BULK_OUT, question, PACKET_BULK_LEN, &transferred,TIMEOUT); if (r < 0) { fprintf(stderr, "Bulk write error %d\n", r); error(r); return r; } fprintf(stdout, "Wrote %d bytes", r); r = libusb_bulk_transfer(handle, ENDPOINT_BULK_IN, answer,PACKET_BULK_LEN, &transferred, TIMEOUT); if (r < 0) { fprintf(stderr, "Bulk read error %d\n", r); error(r); return r; } fprintf(stdout, "Read %d bytes", r); if (transferred < PACKET_BULK_LEN) { fprintf(stderr, "Bulk transfer short read (%d)\n", r); error(r); return -1; } printf("Bulk Transfer Loop Test Result:\n"); // for (i=0;i< PACKET_BULK_LEN;i++) printf("%i, %i,\n ",question[i],answer[i]); for(i = 0;i < PACKET_BULK_LEN; i++) { if(i%8 == 0) printf("\n"); printf("%02x, %02x; ",question[i],answer[i]); } printf("\n\n"); return 0; } static int init(){ libusb_init(NULL); if((handle = libusb_open_device_with_vid_pid(NULL, VID, PID)) == NULL){ fprintf(stdout, "Problem acquiring handle\n"); return -1; } libusb_claim_interface(handle, 0); return 0; } static int shutdown(){ if(handle != NULL) libusb_release_interface (handle, 0); libusb_exit(NULL); return 0; } static int setupAccessory( const char* manufacturer, const char* modelName, const char* description, const char* version, const char* uri, const char* serialNumber){ unsigned char ioBuffer[2]; int devVersion; int response; response = libusb_control_transfer( handle, //handle 0xC0, //bmRequestType 51, //bRequest 0, //wValue 0, //wIndex ioBuffer, //data 2, //wLength 0 //timeout ); if(response < 0){error(response);return-1;} devVersion = ioBuffer[1] << 8 \| ioBuffer[0]; fprintf(stdout,"Version Code Device: %d\n", devVersion); usleep(1000);//sometimes hangs on the next transfer :( response = libusb_control_transfer(handle,0x40,52,0,0,(char)manufacturer,strlen(manufacturer),0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,1,(char)modelName,strlen(modelName)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,2,(char)description,strlen(description)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,3,(char)version,strlen(version)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,4,(char)uri,strlen(uri)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,5,(char)serialNumber,strlen(serialNumber)+1,0); if(response < 0){error(response);return -1;} fprintf(stdout,"Accessory Identification sent\n", devVersion); response = libusb_control_transfer(handle,0x40,53,0,0,NULL,0,0); if(response < 0){error(response);return -1;} fprintf(stdout,"Attempted to put device into accessory mode\n", devVersion); if(handle != NULL) libusb_release_interface (handle, 0); int tries = 4; for(;;){ tries--; if((handle = libusb_open_device_with_vid_pid(NULL, VID, ACCESSORY_PID)) == NULL){ if(tries < 0){ return -1; } }else{ break; } sleep(1); } libusb_claim_interface(handle, 0); fprintf(stdout, "Interface claimed, ready to transfer data\n"); return 0; } // error reporting function left out for brevity	zz314326255--adkping	adkping/pc-accessory/libusb-adk-examples/adktest.c	C	oos	5,257
gcc simplectrl.c -I/usr/include/ -o simplectrl -lusb-1.0 -I/usr/include/ -I/usr/include/libusb-1.0 gcc adktest.c -I/usr/include/ -o adktest -lusb-1.0 -I/usr/include/ -I/usr/include/libusb-1.0	zz314326255--adkping	adkping/pc-accessory/libusb-adk-examples/build.sh	Shell	oos	193
/* * simplectrl.c * This file is part of OsciPrime * * Copyright (C) 2011 - Manuel Di Cerbo * * OsciPrime is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * OsciPrime is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with OsciPrime; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, * Boston, MA 02110-1301 USA / #include <stdio.h> #include <usb.h> #include <libusb.h> #include <string.h> #include <unistd.h> #define IN 0x85 #define OUT 0x07 #define VID 0x18D1 #define PID 0x4E22 #define ACCESSORY_PID 0x2D01 #define ACCESSORY_PID_ALT 0x2D00 #define LEN 2 / If you are on Ubuntu you will require libusb as well as the headers... We installed the headers with "apt-get source libusb" gcc simplectrl.c -I/usr/include/ -o simplectrl -lusb-1.0 -I/usr/include/ -I/usr/include/libusb-1.0 Tested for Nexus S with Gingerbread 2.3.4 / static int mainPhase(); static int init(void); static int deInit(void); static void error(int code); static void status(int code); static int setupAccessory( const char manufacturer, const char* modelName, const char* description, const char* version, const char* uri, const char* serialNumber); //static static struct libusb_device_handle* handle; static char stop; static char success = 0; int main (int argc, char argv[]){ if(init() < 0) return; //doTransfer(); if(setupAccessory( "Manufacturer", "Model", "Description", "VersionName", "http://neuxs-computing.ch", "2254711SerialNo.") < 0){ fprintf(stdout, "Error setting up accessory\n"); deInit(); return -1; }; if(mainPhase() < 0){ fprintf(stdout, "Error during main phase\n"); deInit(); return -1; } deInit(); fprintf(stdout, "Done, no errors\n"); return 0; } static int mainPhase(){ unsigned char buffer[500000]; int response = 0; static int transferred; response = libusb_bulk_transfer(handle,IN,buffer,16384, &transferred,0); if(response < 0){error(response);return -1;} response = libusb_bulk_transfer(handle,IN,buffer,500000, &transferred,0); if(response < 0){error(response);return -1;} } static int init(){ libusb_init(NULL); if((handle = libusb_open_device_with_vid_pid(NULL, VID, PID)) == NULL){ fprintf(stdout, "Problem acquireing handle\n"); return -1; } libusb_claim_interface(handle, 0); return 0; } static int deInit(){ //TODO free all transfers individually... //if(ctrlTransfer != NULL) // libusb_free_transfer(ctrlTransfer); if(handle != NULL) libusb_release_interface (handle, 0); libusb_exit(NULL); return 0; } static int setupAccessory( const char manufacturer, const char* modelName, const char* description, const char* version, const char* uri, const char* serialNumber){ unsigned char ioBuffer[2]; int devVersion; int response; int tries = 5; response = libusb_control_transfer( handle, //handle 0xC0, //bmRequestType 51, //bRequest 0, //wValue 0, //wIndex ioBuffer, //data 2, //wLength 0 //timeout ); if(response < 0){error(response);return-1;} devVersion = ioBuffer[1] << 8 \| ioBuffer[0]; fprintf(stdout,"Verion Code Device: %d\n", devVersion); usleep(1000);//sometimes hangs on the next transfer :( response = libusb_control_transfer(handle,0x40,52,0,0,(char)manufacturer,strlen(manufacturer),0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,1,(char)modelName,strlen(modelName)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,2,(char)description,strlen(description)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,3,(char)version,strlen(version)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,4,(char)uri,strlen(uri)+1,0); if(response < 0){error(response);return -1;} response = libusb_control_transfer(handle,0x40,52,0,5,(char)serialNumber,strlen(serialNumber)+1,0); if(response < 0){error(response);return -1;} fprintf(stdout,"Accessory Identification sent\n", devVersion); response = libusb_control_transfer(handle,0x40,53,0,0,NULL,0,0); if(response < 0){error(response);return -1;} fprintf(stdout,"Attempted to put device into accessory mode\n", devVersion); if(handle != NULL) libusb_release_interface (handle, 0); for(;;){//attempt to connect to new PID, if that doesn't work try ACCESSORY_PID_ALT tries--; if((handle = libusb_open_device_with_vid_pid(NULL, VID, ACCESSORY_PID)) == NULL){ if(tries < 0){ return -1; } }else{ break; } sleep(1); } libusb_claim_interface(handle, 0); fprintf(stdout, "Interface claimed, ready to transfer data\n"); return 0; } static void error(int code){ fprintf(stdout,"\n"); switch(code){ case LIBUSB_ERROR_IO: fprintf(stdout,"Error: LIBUSB_ERROR_IO\nInput/output error.\n"); break; case LIBUSB_ERROR_INVALID_PARAM: fprintf(stdout,"Error: LIBUSB_ERROR_INVALID_PARAM\nInvalid parameter.\n"); break; case LIBUSB_ERROR_ACCESS: fprintf(stdout,"Error: LIBUSB_ERROR_ACCESS\nAccess denied (insufficient permissions).\n"); break; case LIBUSB_ERROR_NO_DEVICE: fprintf(stdout,"Error: LIBUSB_ERROR_NO_DEVICE\nNo such device (it may have been disconnected).\n"); break; case LIBUSB_ERROR_NOT_FOUND: fprintf(stdout,"Error: LIBUSB_ERROR_NOT_FOUND\nEntity not found.\n"); break; case LIBUSB_ERROR_BUSY: fprintf(stdout,"Error: LIBUSB_ERROR_BUSY\nResource busy.\n"); break; case LIBUSB_ERROR_TIMEOUT: fprintf(stdout,"Error: LIBUSB_ERROR_TIMEOUT\nOperation timed out.\n"); break; case LIBUSB_ERROR_OVERFLOW: fprintf(stdout,"Error: LIBUSB_ERROR_OVERFLOW\nOverflow.\n"); break; case LIBUSB_ERROR_PIPE: fprintf(stdout,"Error: LIBUSB_ERROR_PIPE\nPipe error.\n"); break; case LIBUSB_ERROR_INTERRUPTED: fprintf(stdout,"Error:LIBUSB_ERROR_INTERRUPTED\nSystem call interrupted (perhaps due to signal).\n"); break; case LIBUSB_ERROR_NO_MEM: fprintf(stdout,"Error: LIBUSB_ERROR_NO_MEM\nInsufficient memory.\n"); break; case LIBUSB_ERROR_NOT_SUPPORTED: fprintf(stdout,"Error: LIBUSB_ERROR_NOT_SUPPORTED\nOperation not supported or unimplemented on this platform.\n"); break; case LIBUSB_ERROR_OTHER: fprintf(stdout,"Error: LIBUSB_ERROR_OTHER\nOther error.\n"); break; default: fprintf(stdout, "Error: unkown error\n"); } } static void status(int code){ fprintf(stdout,"\n"); switch(code){ case LIBUSB_TRANSFER_COMPLETED: fprintf(stdout,"Success: LIBUSB_TRANSFER_COMPLETED\nTransfer completed.\n"); break; case LIBUSB_TRANSFER_ERROR: fprintf(stdout,"Error: LIBUSB_TRANSFER_ERROR\nTransfer failed.\n"); break; case LIBUSB_TRANSFER_TIMED_OUT: fprintf(stdout,"Error: LIBUSB_TRANSFER_TIMED_OUT\nTransfer timed out.\n"); break; case LIBUSB_TRANSFER_CANCELLED: fprintf(stdout,"Error: LIBUSB_TRANSFER_CANCELLED\nTransfer was cancelled.\n"); break; case LIBUSB_TRANSFER_STALL: fprintf(stdout,"Error: LIBUSB_TRANSFER_STALL\nFor bulk/interrupt endpoints: halt condition detected (endpoint stalled).\nFor control endpoints: control request not supported.\n"); break; case LIBUSB_TRANSFER_NO_DEVICE: fprintf(stdout,"Error: LIBUSB_TRANSFER_NO_DEVICE\nDevice was disconnected.\n"); break; case LIBUSB_TRANSFER_OVERFLOW: fprintf(stdout,"Error: LIBUSB_TRANSFER_OVERFLOW\nDevice sent more data than requested.\n"); break; default: fprintf(stdout,"Error: unknown error\nTry again(?)\n"); break; } }	zz314326255--adkping	adkping/pc-accessory/libusb-adk-examples/simplectrl.c	C	oos	7,953
TARGET = adkping CFLAGS += -Wall -I/usr/include/ -I/usr/include/libusb-1.0 -lusb-1.0 all: $(TARGET) clean: rm -rf $(TARGET) .o ~	zz314326255--adkping	adkping/pc-accessory/Makefile	Makefile	oos	136
SOURCE = Report PAPER = a4 LATEXMK = ./tools/latexmk OBJS = bbl ilg ind blg glo out aux dvi log ps backup bak toc idx DS_Stor .PHONY: all print bib clean deep-clean dvi all: update show update: deep-clean bib preview: $(LATEXMK) -dvi -pvc -silent $(SOURCE).tex dvi: $(SOURCE).dvi $(SOURCE).dvi: $(SOURCE).tex latex $< latex $< ps: $(SOURCE).ps $(SOURCE).ps: $(SOURCE).dvi dvips -Ppdf -G0 -t$(PAPER) -o $@ $< pdf: $(SOURCE).pdf $(SOURCE).pdf: $(SOURCE).ps ps2pdf -dSubsetFonts=true -dMaxSubsetPct=100 -dEmbedAllFonts=true \ -dUseFlateCompression=true -dCompatibilityLevel=1.4 \ -dPDFSETTINGS=/prepress -sPAPERSIZE=$(PAPER) $< $@ bib: $(SOURCE).bbl $(SOURCE).bbl : $(SOURCE).bib latex $(SOURCE).tex bibtex $(SOURCE) rm -f $(SOURCE).dvi report: $(SOURCE).pdf pdffonts $< > fonts.log cat fonts.log show: pdf kill -9 `ps aux \| grep $(SOURCE).pdf \| grep -v grep \ \| awk '{print $2}'` >/dev/null 2>&1 \|\| true gnome-open $(SOURCE).pdf clean: for e in $(OBJS); do \ find . -path './.git' -prune -o -name ".$$e" \ -exec rm -f \{\} \; ;\ done find . -path './.git' -prune -o -name "~" -exec rm -f \{\} \; deep-clean: clean rm -rf .bbl .pdf *.fdb_latexmk	zz314326255--adkping	iNEMO-accessory/report/Makefile	Makefile	oos	1,189
% VDE Template for EUSAR Papers % Provided by Barbara Lang und Siegmar Lampe % University of Bremen, January 2002 % English version by Jens Fischer % German Aerospace Center (DLR), December 2005 % Additional modifications by Matthias Wei{\ss} % FGAN, January 2009 %----------------------------------------------------------------------------- % Type of publication \documentclass[a4paper,10pt]{article} %----------------------------------------------------------------------------- % Other packets: Most packets may be downloaded from www.dante.de and % "tcilatex.tex" can be found at (December 2005): % http://www.mackichan.com/techtalk/v30/UsingFloat.htm % Not all packets are necessarily needed: \usepackage[T1]{fontenc} \usepackage[latin1]{inputenc} %\usepackage{ngerman} % in german language if required \usepackage[nooneline,bf]{caption} % Figure descriptions from left margin \usepackage{times} \usepackage{multicol} \usepackage{amsmath} \usepackage{amssymb} \usepackage[dvips]{graphicx} \usepackage{epsfig} \usepackage[usenames,dvipsnames]{xcolor} \usepackage{pstricks} \usepackage{wrapfig} \usepackage{epstopdf} \usepackage{tabularx} \input{tcilatex} %----------------------------------------------------------------------------- % Page Setup \textheight24cm \textwidth17cm \columnsep6mm \oddsidemargin-5mm % depending on print drivers! \evensidemargin-5mm % required margin size: 2cm \headheight0cm \headsep0cm \topmargin0cm \parindent0cm \pagestyle{empty} % delete footer and header %---------------------------------------------------------------------------- %hyperref \usepackage[breaklinks]{hyperref} \hypersetup{ bookmarks=true, % show bookmarks bar? pdftoolbar=true, % show Acrobat’s toolbar? pdfmenubar=true, % show Acrobat’s menu? pdffitwindow=false, pdftitle={Android Open ADK on iNEMO platform}, % title pdfauthor={Gianazza Andrea}, % author pdfsubject={Demo application showing the support of Android ADK to STM32 microcontrollers family}, pdfkeywords={STM} {ADK} {Android} {Embedded Systems} } %---------------------------------------------------------------------------- % Environment definitions \newenvironment{mytitle}{\begin{LARGE}\bf}{\end{LARGE}\\}% \newenvironment{mysubtitle}{\bf}{\\[1.5ex]}% \newenvironment{myabstract}{\begin{Large}\bf}{\end{Large}\\[2.5ex]}% %----------------------------------------------------------------------------- % Using Pictures and tables: % - Instead "table" write "tablehere" without parameters % - Instead "figure" write "figurehere " without parameters % - Please insert a blank line before and after \begin{figuerhere} ... \end{figurehere} % % CAUTION: The first reference to a figure/table in the text should be formatted fat. % \makeatletter \newenvironment{tablehere}{\def\@captype{table}}{} \newenvironment{figurehere}{\def\@captype{figure}\vspace{2ex}}{\vspace{2ex}} \def\hlinewd#1{% \noalign{\ifnum0=`}\fi\hrule \@height #1 % \futurelet\reserved@a\@xhline} \makeatother \renewcommand{\arraystretch}{1.2} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \begin{document} % Please use capital letters in the beginning of important words as for example \begin{mytitle}Android Open ADK on iNEMO platform\end{mytitle} \begin{mysubtitle}Demo application showing the support of Android Open ADK to STM32 microcontrollers' family\end{mysubtitle} % % Please do not insert a line here % \\ Gianazza Andrea\\ Matr. 755119, (g.gianazza87@gmail.com)\\ \hspace{10ex} Scolari Alberto\\ Matr. 123456, (al.scolari@alice.it)\\ \hspace{10ex} Turri Matteo\\ Matr. 123456, (matteoturri89@gmail.com)\\ \begin{flushright} \emph{Report for the master course of Embedded Systems}\\ \emph{Reviser: PhD. Patrick Bellasi (bellasi@elet.polimi.it)} \end{flushright} Received: \today \\ \hspace{10ex} \begin{myabstract} Abstract \end{myabstract} In 2011 Google presented the Android Open Accessory Development Kit (ADK), a software framework that allows external USB hardware to easily communicate with Android-powered devices. Several distributors started to produce Android Open Accessory compatible development boards, in order to promote the diffusion of USB accessories for Android. The aim of this work is to show the support of Android Open ADK to STM32 microcontrollers family, porting the Windows iNEMO demo application to Android. \vspace{4ex} % Please do not remove or reduce this space here. \begin{multicols}{2} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \input{sections/sec1} \input{sections/sec2} \input{sections/sec3} \input{sections/sec4} \input{sections/sec5} \input{sections/sec6} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % We suggest the use of JabRef for editing your bibliography file (Report.bib) %\bibliographystyle{splncs} \nocite{} \bibliographystyle{ieeetr} \bibliography{Report} \end{multicols} \end{document}	zz314326255--adkping	iNEMO-accessory/report/Report.tex	TeX	oos	4,993
\section{Conclusions} \label{conclusions} The results obtained with this work can be summarized as follows: \begin{itemize} \item Added the support of Android Open ADK to STM32 microcontrollers' family. \item Defined a communication protocol for the exchange of messages between the iNEMO board and the Android device. \item Implemented the communication protocol both in the firmware and in the Android application. \item Implemented a set of task in the firmware that guarantees a correct communication with the Android device. \item Implemented a complete Android application that can establish a communication with the iNEMO board and show to the user the data originated from the sensors integrated on the board (for now in a textual way). The user can also change the acquisition parameters and choose which sensors have to be monitored. \end{itemize} Future developments for this work: \begin{itemize} \item Show the data originated from the sensors in a graphical way (sliding graphs as in the Windows application iNEMO Suite). \item Implement a complete compilation chain based on gcc and Makefile, in order to get rid of the limitations imposed by Keil uVision IDE. \item Improve the graphic of the application. \end{itemize}	zz314326255--adkping	iNEMO-accessory/report/sections/sec6.tex	TeX	oos	1,249