code stringlengths 1 2.01M | repo_name stringlengths 3 62 | path stringlengths 1 267 | language stringclasses 231 values | license stringclasses 13 values | size int64 1 2.01M |
|---|---|---|---|---|---|
;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
;* File Name : cortexm3_macro.s
;* Author : MCD Application Team
;* Date First Issued : 02/19/2007
;* Description : Instruction wrappers for special Cortex-M3 instructions.
;*******************************************************************************
; History:
; 04/02/2007: V0.2
; 02/19/2007: V0.1
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
SECTION .text:CODE(2)
; Exported functions
EXPORT __WFI
EXPORT __WFE
EXPORT __SEV
EXPORT __ISB
EXPORT __DSB
EXPORT __DMB
EXPORT __SVC
EXPORT __MRS_CONTROL
EXPORT __MSR_CONTROL
EXPORT __MRS_PSP
EXPORT __MSR_PSP
EXPORT __MRS_MSP
EXPORT __MSR_MSP
EXPORT __SETPRIMASK
EXPORT __RESETPRIMASK
EXPORT __SETFAULTMASK
EXPORT __RESETFAULTMASK
EXPORT __BASEPRICONFIG
EXPORT __GetBASEPRI
EXPORT __REV_HalfWord
EXPORT __REV_Word
;*******************************************************************************
; Function Name : __WFI
; Description : Assembler function for the WFI instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFI
WFI
BX r14
;*******************************************************************************
; Function Name : __WFE
; Description : Assembler function for the WFE instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFE
WFE
BX r14
;*******************************************************************************
; Function Name : __SEV
; Description : Assembler function for the SEV instruction.
; Input : None
; Return : None
;*******************************************************************************
__SEV
SEV
BX r14
;*******************************************************************************
; Function Name : __ISB
; Description : Assembler function for the ISB instruction.
; Input : None
; Return : None
;*******************************************************************************
__ISB
ISB
BX r14
;*******************************************************************************
; Function Name : __DSB
; Description : Assembler function for the DSB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DSB
DSB
BX r14
;*******************************************************************************
; Function Name : __DMB
; Description : Assembler function for the DMB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DMB
DMB
BX r14
;*******************************************************************************
; Function Name : __SVC
; Description : Assembler function for the SVC instruction.
; Input : None
; Return : None
;*******************************************************************************
__SVC
SVC 0x01
BX r14
;*******************************************************************************
; Function Name : __MRS_CONTROL
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Cortex-M3 CONTROL register value.
;*******************************************************************************
__MRS_CONTROL
MRS r0, CONTROL
BX r14
;*******************************************************************************
; Function Name : __MSR_CONTROL
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Cortex-M3 CONTROL register new value.
; Return : None
;*******************************************************************************
__MSR_CONTROL
MSR CONTROL, r0
ISB
BX r14
;*******************************************************************************
; Function Name : __MRS_PSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Process Stack value.
;*******************************************************************************
__MRS_PSP
MRS r0, PSP
BX r14
;*******************************************************************************
; Function Name : __MSR_PSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Process Stack new value.
; Return : None
;*******************************************************************************
__MSR_PSP
MSR PSP, r0 ; set Process Stack value
BX r14
;*******************************************************************************
; Function Name : __MRS_MSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Main Stack value.
;*******************************************************************************
__MRS_MSP
MRS r0, MSP
BX r14
;*******************************************************************************
; Function Name : __MSR_MSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Main Stack new value.
; Return : None
;*******************************************************************************
__MSR_MSP
MSR MSP, r0 ; set Main Stack value
BX r14
;*******************************************************************************
; Function Name : __SETPRIMASK
; Description : Assembler function to set the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETPRIMASK
CPSID i
BX r14
;*******************************************************************************
; Function Name : __RESETPRIMASK
; Description : Assembler function to reset the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETPRIMASK
CPSIE i
BX r14
;*******************************************************************************
; Function Name : __SETFAULTMASK
; Description : Assembler function to set the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETFAULTMASK
CPSID f
BX r14
;*******************************************************************************
; Function Name : __RESETFAULTMASK
; Description : Assembler function to reset the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETFAULTMASK
CPSIE f
BX r14
;*******************************************************************************
; Function Name : __BASEPRICONFIG
; Description : Assembler function to set the Base Priority.
; Input : - r0 : Base Priority new value
; Return : None
;*******************************************************************************
__BASEPRICONFIG
MSR BASEPRI, r0
BX r14
;*******************************************************************************
; Function Name : __GetBASEPRI
; Description : Assembler function to get the Base Priority value.
; Input : None
; Return : - r0 : Base Priority value
;*******************************************************************************
__GetBASEPRI
MRS r0, BASEPRI_MAX
BX r14
;*******************************************************************************
; Function Name : __REV_HalfWord
; Description : Reverses the byte order in HalfWord(16-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_HalfWord
REV16 r0, r0
BX r14
;*******************************************************************************
; Function Name : __REV_Word
; Description : Reverses the byte order in Word(32-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_Word
REV r0, r0
BX r14
END
;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/cortexm3_macro.s | Unix Assembly | oos | 9,440 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : lcd.c
* Author : MCD Application Team
* Date First Issued : mm/dd/yyyy
* Description : This file includes the LCD driver for AM-240320LTNQW00H
* liquid Crystal Display Module of STM32F10x-EVAL.
********************************************************************************
* History:
* mm/dd/yyyy
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
#include "lcd.h"
#include "spi_flash.h"
#include "FreeRTOS.h"
#include "task.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ASCII Table: each character is 16 column (16dots large)
and 24 raw (24 dots high) */
const uc16 ASCII_Table[] =
{
/* Space ' ' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '!' */
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '"' */
0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '#' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
/* '$' */
0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
/* '%' */
0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
/* '&' */
0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ''' */
0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '(' */
0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
/* ')' */
0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
/* '*' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '+' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ',' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
/* '-' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '.' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '/' */
0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '0' */
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '1' */
0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '2' */
0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '3' */
0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '4' */
0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '5' */
0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '6' */
0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '7' */
0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '8' */
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '9' */
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ':' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ';' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
/* '<' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '=' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '>' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '?' */
0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '@' */
0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'A' */
0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'B' */
0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'C' */
0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'D' */
0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'E' */
0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'F' */
0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'G' */
0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'H' */
0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'I' */
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'J' */
0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'K' */
0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'L' */
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'M' */
0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'N' */
0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'O' */
0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'P' */
0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'Q' */
0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'R' */
0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'S' */
0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'T' */
0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'U' */
0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'V' */
0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'W' */
0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'X' */
0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'Y' */
0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'Z' */
0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '[' */
0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
/* '\' */
0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ']' */
0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
/* '^' */
0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '_' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* ''' */
0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'a' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'b' */
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'c' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'd' */
0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'e' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'f' */
0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'g' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
/* 'h' */
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'i' */
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'j' */
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
/* 'k' */
0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'l' */
0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'm' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'n' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'o' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'p' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
/* 'q' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
/* 'r' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 's' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 't' */
0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'u' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'v' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'w' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'x' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* 'y' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
/* 'z' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/* '{' */
0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
/* '|' */
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
/* '}' */
0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
/* '~' */
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Global variables to set the written text color */
static vu16 TextColor = 0x0000, BackColor = 0xFFFF;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
static u32 StrLength(u8 *Str);
/*******************************************************************************
* Function Name : LCD_Init
* Description : Initializes LCD.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_Init(void)
{
/* Configure the LCD Control pins --------------------------------------------*/
LCD_CtrlLinesConfig();
/* Configure the SPI2 interface ----------------------------------------------*/
LCD_SPIConfig();
/* Enable the LCD Oscillator -------------------------------------------------*/
LCD_WriteReg(R1, 0x10);
LCD_WriteReg(R0, 0xA0);
LCD_WriteReg(R3, 0x01);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R3, 0x00);
LCD_WriteReg(R43, 0x04);
LCD_WriteReg(R40, 0x18);
LCD_WriteReg(R26, 0x05);
LCD_WriteReg(R37, 0x05);
LCD_WriteReg(R25, 0x00);
/* LCD Power On --------------------------------------------------------------*/
LCD_WriteReg(R28, 0x73);
LCD_WriteReg(R36, 0x74);
LCD_WriteReg(R30, 0x01);
LCD_WriteReg(R24, 0xC1);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R24, 0xE1);
LCD_WriteReg(R24, 0xF1);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R24, 0xF5);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R27, 0x09);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R31, 0x11);
LCD_WriteReg(R32, 0x0E);
LCD_WriteReg(R30, 0x81);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
/* Chip Set ------------------------------------------------------------------*/
LCD_WriteReg(R157, 0x00);
LCD_WriteReg(R192, 0x00);
LCD_WriteReg(R14, 0x00);
LCD_WriteReg(R15, 0x00);
LCD_WriteReg(R16, 0x00);
LCD_WriteReg(R17, 0x00);
LCD_WriteReg(R18, 0x00);
LCD_WriteReg(R19, 0x00);
LCD_WriteReg(R20, 0x00);
LCD_WriteReg(R21, 0x00);
LCD_WriteReg(R22, 0x00);
LCD_WriteReg(R23, 0x00);
LCD_WriteReg(R52, 0x01);
LCD_WriteReg(R53, 0x00);
LCD_WriteReg(R75, 0x00);
LCD_WriteReg(R76, 0x00);
LCD_WriteReg(R78, 0x00);
LCD_WriteReg(R79, 0x00);
LCD_WriteReg(R80, 0x00);
LCD_WriteReg(R60, 0x00);
LCD_WriteReg(R61, 0x00);
LCD_WriteReg(R62, 0x01);
LCD_WriteReg(R63, 0x3F);
LCD_WriteReg(R64, 0x02);
LCD_WriteReg(R65, 0x02);
LCD_WriteReg(R66, 0x00);
LCD_WriteReg(R67, 0x00);
LCD_WriteReg(R68, 0x00);
LCD_WriteReg(R69, 0x00);
LCD_WriteReg(R70, 0xEF);
LCD_WriteReg(R71, 0x00);
LCD_WriteReg(R72, 0x00);
LCD_WriteReg(R73, 0x01);
LCD_WriteReg(R74, 0x3F);
LCD_WriteReg(R29, 0x08); /* R29:Gate scan direction setting */
LCD_WriteReg(R134, 0x00);
LCD_WriteReg(R135, 0x30);
LCD_WriteReg(R136, 0x02);
LCD_WriteReg(R137, 0x05);
LCD_WriteReg(R141, 0x01); /* R141:Register set-up mode for one line clock */
LCD_WriteReg(R139, 0x20); /* R139:One line SYSCLK number in one-line */
LCD_WriteReg(R51, 0x01); /* R51:N line inversion setting */
LCD_WriteReg(R55, 0x01); /* R55:Scanning method setting */
LCD_WriteReg(R118, 0x00);
/* Gamma Set -----------------------------------------------------------------*/
LCD_WriteReg(R143, 0x10);
LCD_WriteReg(R144, 0x67);
LCD_WriteReg(R145, 0x07);
LCD_WriteReg(R146, 0x65);
LCD_WriteReg(R147, 0x07);
LCD_WriteReg(R148, 0x01);
LCD_WriteReg(R149, 0x76);
LCD_WriteReg(R150, 0x56);
LCD_WriteReg(R151, 0x00);
LCD_WriteReg(R152, 0x06);
LCD_WriteReg(R153, 0x03);
LCD_WriteReg(R154, 0x00);
/* Display On ----------------------------------------------------------------*/
LCD_WriteReg(R1, 0x50);
LCD_WriteReg(R5, 0x04);
LCD_WriteReg(R0, 0x80);
LCD_WriteReg(R59, 0x01);
vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
LCD_WriteReg(R0, 0x20);
}
/*******************************************************************************
* Function Name : LCD_SetTextColor
* Description : Sets the Text color.
* Input : - Color: specifies the Text color code RGB(5-6-5).
* Output : - TextColor: Text color global variable used by LCD_DrawChar
* and LCD_DrawPicture functions.
* Return : None
*******************************************************************************/
void LCD_SetTextColor(vu16 Color)
{
TextColor = Color;
}
/*******************************************************************************
* Function Name : LCD_SetBackColor
* Description : Sets the Background color.
* Input : - Color: specifies the Background color code RGB(5-6-5).
* Output : - BackColor: Background color global variable used by
* LCD_DrawChar and LCD_DrawPicture functions.
* Return : None
*******************************************************************************/
void LCD_SetBackColor(vu16 Color)
{
BackColor = Color;
}
/*******************************************************************************
* Function Name : LCD_ClearLine
* Description : Clears the selected line.
* Input : - Line: the Line to be cleared.
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* Output : None
* Return : None
*******************************************************************************/
void LCD_ClearLine(u8 Line)
{
LCD_DisplayStringLine(Line, " ");
}
/*******************************************************************************
* Function Name : LCD_Clear
* Description : Clears the hole LCD.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_Clear(void)
{
u32 index = 0;
LCD_SetCursor(0x00, 0x013F);
for(index = 0; index < 0x12C00; index++)
{
LCD_WriteRAM(White);
}
}
/*******************************************************************************
* Function Name : LCD_SetCursor
* Description : Sets the cursor position.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* Output : None
* Return : None
*******************************************************************************/
void LCD_SetCursor(u8 Xpos, u16 Ypos)
{
LCD_WriteReg(R66, Xpos);
LCD_WriteReg(R67, ((Ypos & 0x100)>> 8));
LCD_WriteReg(R68, (Ypos & 0xFF));
}
/*******************************************************************************
* Function Name : LCD_DrawChar
* Description : Draws a character on LCD.
* Input : - Xpos: the Line where to display the character shape.
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - Ypos: start column address.
* - c: pointer to the character data.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c)
{
u32 index = 0, i = 0;
u8 Xaddress = 0;
Xaddress = Xpos;
LCD_SetCursor(Xaddress, Ypos);
for(index = 0; index < 24; index++)
{
for(i = 0; i < 16; i++)
{
if((c[index] & (1 << i)) == 0x00)
{
LCD_WriteRAM(BackColor);
}
else
{
LCD_WriteRAM(TextColor);
}
}
Xaddress++;
LCD_SetCursor(Xaddress, Ypos);
}
}
/*******************************************************************************
* Function Name : LCD_DisplayChar
* Description : Displays one character (16dots width, 24dots height).
* Input : - Line: the Line where to display the character shape .
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - Column: start column address.
* - Ascii: character ascii code, must be between 0x20 and 0x7E.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii)
{
Ascii -= 32;
LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]);
}
/*******************************************************************************
* Function Name : LCD_DisplayStringLine
* Description : Displays a maximum of 20 char on the LCD.
* Input : - Line: the Line where to display the character shape .
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - *ptr: pointer to string to display on LCD.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayStringLine(u8 Line, u8 *ptr)
{
u32 i = 0;
u16 refcolumn = 319;
/* Send the string character by character on lCD */
while ((*ptr != 0) & (i < 20))
{
/* Display one character on LCD */
LCD_DisplayChar(Line, refcolumn, *ptr);
/* Decrement the column position by 16 */
refcolumn -= 16;
/* Point on the next character */
ptr++;
/* Increment the character counter */
i++;
}
}
/*******************************************************************************
* Function Name : LCD_DisplayString
* Description : Displays a maximum of 200 char on the LCD.
* Input : - Line: the starting Line where to display the character shape.
* This parameter can be one of the following values:
* - Linex: where x can be 0..9
* - *ptr: pointer to string to display on LCD.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayString(u8 Line, u8 *ptr)
{
u32 i = 0, column = 0, index = 0, spaceindex = 0;
u16 refcolumn = 319;
u32 length = 0;
/* Get the string length */
length = StrLength(ptr);
if(length > 200)
{
/* Set the Cursor position */
LCD_SetCursor(Line, 0x013F);
/* Clear the Selected Line */
LCD_ClearLine(Line);
LCD_DisplayStringLine(Line, " String too long ");
}
else
{
/* Set the Cursor position */
LCD_SetCursor(Line, 0x013F);
/* Clear the Selected Line */
LCD_ClearLine(Line);
while(length--)
{
if(index == 20)
{
if(*ptr == 0x20)
{
ptr++;
}
else
{
for(i = 0; i < spaceindex; i++)
{
LCD_DisplayChar(Line, column, ' ');
column -= 16;
}
ptr -= (spaceindex - 1);
length += (spaceindex - 1);
}
Line += 24;
/* Clear the Selected Line */
LCD_ClearLine(Line);
refcolumn = 319;
index = 0;
}
/* Display one character on LCD */
LCD_DisplayChar(Line, refcolumn, *ptr);
/* Increment character number in one line */
index++;
/* Decrement the column position by 16 */
refcolumn -= 16;
/* Point on the next character */
ptr++;
/* Increment the number of character after the last space */
spaceindex++;
if(*ptr == 0x20)
{
spaceindex = 0;
column = refcolumn - 16;
}
}
}
}
/*******************************************************************************
* Function Name : LCD_ScrollText
* Description :
* Input :
* Output : None
* Return : None
*******************************************************************************/
void LCD_ScrollText(u8 Line, u8 *ptr)
{
u32 i = 0, length = 0, x = 0;
u16 refcolumn = 319;
/* Get the string length */
length = StrLength(ptr);
while(1)
{
/* Send the string character by character on lCD */
while ((*ptr != 0) & (i < 20))
{
/* Display one character on LCD */
LCD_DisplayChar(Line, refcolumn, *ptr);
/* Decrement the column position by 16 */
refcolumn -= 16;
/* Point on the next character */
ptr++;
/* Increment the character counter */
i++;
}
vTaskDelay( 100 / portTICK_RATE_MS );
i = 0;
//LCD_ClearLine(Line);
ptr -= length;
x++;
if(refcolumn < 16)
{
x = 0;
}
refcolumn = 319 - (x * 16);
}
}
/*******************************************************************************
* Function Name : LCD_SetDisplayWindow
* Description : Sets a display window
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Height: display window height.
* - Width: display window width.
* Output : None
* Return : None
*******************************************************************************/
void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
{
LCD_WriteReg(R1, 0xD0);
LCD_WriteReg(R5, 0x14);
LCD_WriteReg(R69, Xpos);
LCD_WriteReg(R70, (Xpos + Height + 1));
LCD_WriteReg(R71, ((Ypos & 0x100)>> 8));
LCD_WriteReg(R72, (Ypos & 0xFF));
LCD_WriteReg(R73, (((Ypos + Width + 1) & 0x100)>> 8));
LCD_WriteReg(R74, ((Ypos + Width + 1) & 0xFF));
LCD_SetCursor(Xpos, Ypos);
}
/*******************************************************************************
* Function Name : LCD_DrawLine
* Description : Displays a line.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Length: line length.
* - Direction: line direction.
* This parameter can be one of the following values: Vertical
* or Horizontal.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction)
{
u32 i = 0;
LCD_SetCursor(Xpos, Ypos);
if(Direction == Horizontal)
{
for(i = 0; i < Length; i++)
{
LCD_WriteRAM(TextColor);
}
}
else
{
for(i = 0; i < Length; i++)
{
LCD_WriteRAM(TextColor);
Xpos++;
LCD_SetCursor(Xpos, Ypos);
}
}
}
/*******************************************************************************
* Function Name : LCD_DrawRect
* Description : Displays a rectangle.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Height: display rectangle height.
* - Width: display rectangle width.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
{
LCD_DrawLine(Xpos, Ypos, Width, Horizontal);
LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal);
LCD_DrawLine(Xpos, Ypos, Height, Vertical);
LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical);
}
/*******************************************************************************
* Function Name : LCD_DrawCircle
* Description : Displays a circle.
* Input : - Xpos: specifies the X position.
* - Ypos: specifies the Y position.
* - Height: display rectangle height.
* - Width: display rectangle width.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius)
{
s32 D; /* Decision Variable */
u32 CurX; /* Current X Value */
u32 CurY; /* Current Y Value */
D = 3 - (Radius << 1);
CurX = 0;
CurY = Radius;
while (CurX <= CurY)
{
LCD_SetCursor(Xpos + CurX, Ypos + CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos + CurX, Ypos - CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurX, Ypos + CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurX, Ypos - CurY);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos + CurY, Ypos + CurX);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos + CurY, Ypos - CurX);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurY, Ypos + CurX);
LCD_WriteRAM(TextColor);
LCD_SetCursor(Xpos - CurY, Ypos - CurX);
LCD_WriteRAM(TextColor);
if (D < 0)
{
D += (CurX << 2) + 6;
}
else
{
D += ((CurX - CurY) << 2) + 10;
CurY--;
}
CurX++;
}
}
/*******************************************************************************
* Function Name : LCD_DrawMonoPict
* Description : Displays a monocolor picture.
* Input : - Pict: pointer to the picture array.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawMonoPict(uc32 *Pict)
{
u32 index = 0, i = 0;
LCD_SetCursor(0, 319);
for(index = 0; index < 2400; index++)
{
for(i = 0; i < 32; i++)
{
if((Pict[index] & (1 << i)) == 0x00)
{
LCD_WriteRAM(BackColor);
}
else
{
LCD_WriteRAM(TextColor);
}
}
}
}
/*******************************************************************************
* Function Name : LCD_DrawBMP
* Description : Displays a bitmap picture loaded in the SPI Flash.
* Input : - BmpAddress: Bmp picture address in the SPI Flash.
* Output : None
* Return : None
*******************************************************************************/
void LCD_DrawBMP(u32 BmpAddress)
{
u32 i = 0;
LCD_WriteReg(R1, 0xD0);
LCD_WriteReg(R5, 0x04);
LCD_SetCursor(239, 0x013F);
SPI_FLASH_StartReadSequence(BmpAddress);
/* Disable SPI1 */
SPI_Cmd(SPI1, DISABLE);
/* SPI in 16-bit mode */
SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);
/* Enable SPI1 */
SPI_Cmd(SPI1, ENABLE);
for(i = 0; i < 76800; i++)
{
LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5)));
}
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(1);
/* Disable SPI1 */
SPI_Cmd(SPI1, DISABLE);
/* SPI in 8-bit mode */
SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);
/* Enable SPI1 */
SPI_Cmd(SPI1, ENABLE);
}
/*******************************************************************************
* Function Name : LCD_WriteReg
* Description : Writes to the selected LCD register.
* Input : - LCD_Reg: address of the selected register.
* - LCD_RegValue: value to write to the selected register.
* Output : None
* Return : None
*******************************************************************************/
void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue)
{
u16 tmp = 0;
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
tmp = LCD_Reg << 8;
tmp |= LCD_RegValue;
SPI_SendData(SPI2, tmp);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
}
/*******************************************************************************
* Function Name : LCD_ReadReg
* Description : Reads the selected LCD Register.
* Input : None
* Output : None
* Return : LCD Register Value.
*******************************************************************************/
u8 LCD_ReadReg(u8 LCD_Reg)
{
u16 tmp = 0;
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
SPI_SendData(SPI2, LCD_Reg);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
SPI_SendData(SPI2, 0xFF);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)== RESET)
{
}
tmp = SPI_ReceiveData(SPI2);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
return tmp;
}
/*******************************************************************************
* Function Name : LCD_WriteRAM
* Description : Writes to the LCD RAM.
* Input : - RGB_Code: the pixel color in RGB mode (5-6-5).
* Output : None
* Return : None
*******************************************************************************/
void LCD_WriteRAM(u16 RGB_Code)
{
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
SPI_SendData(SPI2, RGB_Code);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
}
/*******************************************************************************
* Function Name : LCD_ReadRAM
* Description : Reads the LCD RAM.
* Input : None
* Output : None
* Return : LCD RAM Value.
*******************************************************************************/
u16 LCD_ReadRAM(void)
{
u16 tmp = 0;
LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
{
}
SPI_SendData(SPI2, 0xFF);
while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)==RESET)
{
}
tmp = SPI_ReceiveData(SPI2);
LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
return tmp;
}
/*******************************************************************************
* Function Name : LCD_PowerOn
* Description :
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_PowerOn(void)
{
/* Power On Set */
LCD_WriteReg(R28, 0x73);
LCD_WriteReg(R36, 0x74);
LCD_WriteReg(R30, 0x01);
LCD_WriteReg(R24, 0xC1);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R24, 0xE1);
LCD_WriteReg(R24, 0xF1);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R24, 0xF5);
vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */
LCD_WriteReg(R27, 0x09);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
LCD_WriteReg(R31, 0x11);
LCD_WriteReg(R32, 0x0E);
LCD_WriteReg(R30, 0x81);
vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */
}
/*******************************************************************************
* Function Name : LCD_DisplayOn
* Description : Enables the Display.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayOn(void)
{
LCD_WriteReg(R1, 0x50);
LCD_WriteReg(R5, 0x04);
/* Display On */
LCD_WriteReg(R0, 0x80);
LCD_WriteReg(R59, 0x01);
vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
LCD_WriteReg(R0, 0x20);
}
/*******************************************************************************
* Function Name : LCD_DisplayOff
* Description : Disables the Display.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_DisplayOff(void)
{
/* Display Off */
LCD_WriteReg(R0, 0xA0);
vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */
LCD_WriteReg(R59, 0x00);
}
/*******************************************************************************
* Function Name : LCD_CtrlLinesConfig
* Description : Configures LCD control lines in Output Push-Pull mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_CtrlLinesConfig(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Configure NCS (PB.02) in Output Push-Pull mode */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/* Configure NWR(RNW), RS (PD.15, PD.07) in Output Push-Pull mode */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_15;
GPIO_Init(GPIOD, &GPIO_InitStructure);
}
/*******************************************************************************
* Function Name : LCD_CtrlLinesWrite
* Description : Sets or reset LCD control lines.
* Input : - GPIOx: where x can be B or D to select the GPIO peripheral.
* - CtrlPins: the Control line. This parameter can be:
* - CtrlPin_NCS: Chip Select pin (PB.02)
* - CtrlPin_NWR: Read/Write Selection pin (PD.15)
* - CtrlPin_RS: Register/RAM Selection pin (PD.07)
* - BitVal: specifies the value to be written to the selected bit.
* This parameter can be:
* - Bit_RESET: to clear the port pin
* - Bit_SET: to set the port pin
* Output : None
* Return : None
*******************************************************************************/
void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal)
{
/* Set or Reset the control line */
GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
}
/*******************************************************************************
* Function Name : LCD_SPIConfig
* Description : Configures the SPI2 interface.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LCD_SPIConfig(void)
{
SPI_InitTypeDef SPI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable GPIOA clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
/* Enable SPI2 clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
/* Configure SPI2 pins: NSS, SCK, MISO and MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/* SPI2 Config */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_Init(SPI2, &SPI_InitStructure);
/* SPI2 enable */
SPI_Cmd(SPI2, ENABLE);
}
/*******************************************************************************
* Function Name : StrLength
* Description : Returns length of string.
* Input : - Str: Character Pointer.
* Output : None
* Return : String length.
*******************************************************************************/
static u32 StrLength(u8 *Str)
{
u32 Index = 0;
/* Increment the Index unless the end of string */
for(Index = 0; *Str != '\0'; Str++, Index++)
{
}
return Index;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/lcd.c | C | oos | 53,242 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_pwr.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the PWR firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_PDDS_Set ((u32)0x00000002)
#define CR_DS_Mask ((u32)0xFFFFFFFC)
#define CR_CWUF_Set ((u32)0x00000004)
#define CR_PLS_Mask ((u32)0xFFFFFF1F)
/* --------- Cortex System Control register bit mask ---------------- */
/* Cortex System Control register address */
#define SCB_SysCtrl ((u32)0xE000ED10)
/* SLEEPDEEP bit mask */
#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : PWR_DeInit
* Description : Deinitializes the PWR peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/*******************************************************************************
* Function Name : PWR_BackupAccessCmd
* Description : Enables or disables access to the RTC and backup registers.
* Input : - NewState: new state of the access to the RTC and backup
* registers. This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_DBP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDCmd
* Description : Enables or disables the Power Voltage Detector(PVD).
* Input : - NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_PVDE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDLevelConfig
* Description : Configures the value detected by the Power Voltage Detector(PVD).
* Input : - PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_Mask;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/*******************************************************************************
* Function Name : PWR_WakeUpPinCmd
* Description : Enables or disables the WakeUp Pin functionality.
* Input : - NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CSR_EWUP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_EnterSTOPMode
* Description : Enters STOP mode.
* Input : - PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* - PWR_Regulator_ON: STOP mode with regulator ON
* - PWR_Regulator_LowPower: STOP mode with
* regulator in low power mode
* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or
* WFE instruction.
* This parameter can be one of the following values:
* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_PWR_REGULATOR(PWR_Regulator));
assert(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_Mask;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
}
/*******************************************************************************
* Function Name : PWR_EnterSTANDBYMode
* Description : Enters STANDBY mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wake-up flag */
PWR->CR |= CR_CWUF_Set;
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Request Wait For Interrupt */
__WFI();
}
/*******************************************************************************
* Function Name : PWR_GetFlagStatus
* Description : Checks whether the specified PWR flag is set or not.
* Input : - PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* - PWR_FLAG_PVDO: PVD Output
* Output : None
* Return : The new state of PWR_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/*******************************************************************************
* Function Name : PWR_ClearFlag
* Description : Clears the PWR's pending flags.
* Input : - PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* Output : None
* Return : None
*******************************************************************************/
void PWR_ClearFlag(u32 PWR_FLAG)
{
/* Check the parameters */
assert(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_pwr.c | C | oos | 11,242 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_systick.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the SysTick firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_systick.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- SysTick registers bit mask -------------------- */
/* CTRL TICKINT Mask */
#define CTRL_TICKINT_Set ((u32)0x00000002)
#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)
/* SysTick Flag Mask */
#define FLAG_Mask ((u8)0x1F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SysTick_CLKSourceConfig
* Description : Configures the SysTick clock source.
* Input : - SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
* selected as SysTick clock source.
* - SysTick_CLKSource_HCLK: AHB clock selected as
* SysTick clock source.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)
{
/* Check the parameters */
assert(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/*******************************************************************************
* Function Name : SysTick_SetReload
* Description : Sets SysTick Reload value.
* Input : - Reload: SysTick Reload new value.
* This parameter must be a number between 1 and 0xFFFFFF.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_SetReload(u32 Reload)
{
/* Check the parameters */
assert(IS_SYSTICK_RELOAD(Reload));
SysTick->LOAD = Reload;
}
/*******************************************************************************
* Function Name : SysTick_CounterCmd
* Description : Enables or disables the SysTick counter.
* Input : - SysTick_Counter: new state of the SysTick counter.
* This parameter can be one of the following values:
* - SysTick_Counter_Disable: Disable counter
* - SysTick_Counter_Enable: Enable counter
* - SysTick_Counter_Clear: Clear counter value to 0
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CounterCmd(u32 SysTick_Counter)
{
/* Check the parameters */
assert(IS_SYSTICK_COUNTER(SysTick_Counter));
if (SysTick_Counter == SysTick_Counter_Clear)
{
SysTick->VAL = SysTick_Counter_Clear;
}
else
{
if (SysTick_Counter == SysTick_Counter_Enable)
{
SysTick->CTRL |= SysTick_Counter_Enable;
}
else
{
SysTick->CTRL &= SysTick_Counter_Disable;
}
}
}
/*******************************************************************************
* Function Name : SysTick_ITConfig
* Description : Enables or disables the SysTick Interrupt.
* Input : - NewState: new state of the SysTick Interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SysTick->CTRL |= CTRL_TICKINT_Set;
}
else
{
SysTick->CTRL &= CTRL_TICKINT_Reset;
}
}
/*******************************************************************************
* Function Name : SysTick_GetCounter
* Description : Gets SysTick counter value.
* Input : None
* Output : None
* Return : SysTick current value
*******************************************************************************/
u32 SysTick_GetCounter(void)
{
return(SysTick->VAL);
}
/*******************************************************************************
* Function Name : SysTick_GetFlagStatus
* Description : Checks whether the specified SysTick flag is set or not.
* Input : - SysTick_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - SysTick_FLAG_COUNT
* - SysTick_FLAG_SKEW
* - SysTick_FLAG_NOREF
* Output : None
* Return : None
*******************************************************************************/
FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)
{
u32 tmp = 0;
u32 statusreg = 0;
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert(IS_SYSTICK_FLAG(SysTick_FLAG));
/* Get the SysTick register index */
tmp = SysTick_FLAG >> 5;
if (tmp == 1) /* The flag to check is in CTRL register */
{
statusreg = SysTick->CTRL;
}
else /* The flag to check is in CALIB register */
{
statusreg = SysTick->CALIB;
}
/* Get the flag position */
tmp = SysTick_FLAG & FLAG_Mask;
if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_systick.c | C | oos | 7,196 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_gpio.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the GPIO firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ RCC registers bit address in the alias region ----------- */
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
/* --- EVENTCR Register ---*/
/* Alias word address of EVOE bit */
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
#define EVOE_BitNumber ((u8)0x07)
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)
#define LSB_MASK ((u16)0xFFFF)
#define DBGAFR_POSITION_MASK ((u32)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((u32)0xF8FFFFFF)
#define DBGAFR_LOCATION_MASK ((u32)0x00200000)
#define DBGAFR_NUMBITS_MASK ((u32)0x00100000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : GPIO_DeInit
* Description : Deinitializes the GPIOx peripheral registers to their default
* reset values.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
switch (*(u32*)&GPIOx)
{
case GPIOA_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
break;
case GPIOB_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
break;
case GPIOC_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
break;
case GPIOD_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
break;
case GPIOE_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : GPIO_AFIODeInit
* Description : Deinitializes the Alternate Functions (remap, event control
* and EXTI configuration) registers to their default reset
* values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void GPIO_AFIODeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
}
/*******************************************************************************
* Function Name : GPIO_Init
* Description : Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
u32 tmpreg = 0x00, pinmask = 0x00;
/* Check the parameters */
assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
/*---------------------------- GPIO Mode Configuration -----------------------*/
currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
{
/* Check the parameters */
assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Output mode */
currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
}
/*---------------------------- GPIO CRL Configuration ------------------------*/
/* Configure the eight low port pins */
if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CRL;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((u32)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding low control register bits */
pinmask = ((u32)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((u32)0x01) << pinpos);
}
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((u32)0x01) << pinpos);
}
}
}
GPIOx->CRL = tmpreg;
tmpreg = 0;
}
/*---------------------------- GPIO CRH Configuration ------------------------*/
/* Configure the eight high port pins */
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CRH;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((u32)0x01) << (pinpos + 0x08));
/* Get the port pins position */
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding high control register bits */
pinmask = ((u32)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
}
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CRH = tmpreg;
}
}
/*******************************************************************************
* Function Name : GPIO_StructInit
* Description : Fills each GPIO_InitStruct member with its default value.
* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputDataBit
* Description : Reads the specified input port pin.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* : - GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : The input port pin value.
*******************************************************************************/
u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u8 bitstatus = 0x00;
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)
{
bitstatus = (u8)Bit_SET;
}
else
{
bitstatus = (u8)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputData
* Description : Reads the specified GPIO input data port.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* Output : None
* Return : GPIO input data port value.
*******************************************************************************/
u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
return ((u16)GPIOx->IDR);
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputDataBit
* Description : Reads the specified output data port bit.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* : - GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : The output port pin value.
*******************************************************************************/
u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u8 bitstatus = 0x00;
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)
{
bitstatus = (u8)Bit_SET;
}
else
{
bitstatus = (u8)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputData
* Description : Reads the specified GPIO output data port.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* Output : None
* Return : GPIO output data port value.
*******************************************************************************/
u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
return ((u16)GPIOx->ODR);
}
/**
* @brief Sets the selected data port bits.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
/* Check the parameters */
assert(IS_GPIO_ALL_PERIPH(GPIOx));
assert(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSRR = GPIO_Pin;
}
/**
* @brief Clears the selected data port bits.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
/* Check the parameters */
assert(IS_GPIO_ALL_PERIPH(GPIOx));
assert(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BRR = GPIO_Pin;
}
/*******************************************************************************
* Function Name : GPIO_WriteBit
* Description : Sets or clears the selected data port bit.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bit to be written.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* - BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enum values:
* - Bit_RESET: to clear the port pin
* - Bit_SET: to set the port pin
* Output : None
* Return : None
*******************************************************************************/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
assert(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin;
}
}
/*******************************************************************************
* Function Name : GPIO_Write
* Description : Writes data to the specified GPIO data port.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - PortVal: specifies the value to be written to the port output
* data register.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)
{
GPIOx->ODR = PortVal;
}
/*******************************************************************************
* Function Name : GPIO_PinLockConfig
* Description : Locks GPIO Pins configuration registers.
* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bit to be written.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u32 tmp = 0x00010000;
/* Check the parameters */
assert(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputConfig
* Description : Selects the GPIO pin used as Event output.
* Input : - GPIO_PortSource: selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be
* (A..E).
* - GPIO_PinSource: specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
{
u32 tmpreg = 0x00;
/* Check the parameters */
assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmpreg = AFIO->EVCR;
/* Clear the PORT[6:4] and PIN[3:0] bits */
tmpreg &= EVCR_PORTPINCONFIG_MASK;
tmpreg |= (u32)GPIO_PortSource << 0x04;
tmpreg |= GPIO_PinSource;
AFIO->EVCR = tmpreg;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputCmd
* Description : Enables or disables the Event Output.
* Input : - NewState: new state of the Event output.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EventOutputCmd(FunctionalState NewState)
{
/* Check the parameters */
assert(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) EVCR_EVOE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : GPIO_PinRemapConfig
* Description : Changes the mapping of the specified pin.
* Input : - GPIO_Remap: selects the pin to remap.
* This parameter can be one of the following values:
* - GPIO_Remap_SPI1
* - GPIO_Remap_I2C1
* - GPIO_Remap_USART1
* - GPIO_Remap_USART2
* - GPIO_PartialRemap_USART3
* - GPIO_FullRemap_USART3
* - GPIO_PartialRemap_TIM1
* - GPIO_FullRemap_TIM1
* - GPIO_PartialRemap1_TIM2
* - GPIO_PartialRemap2_TIM2
* - GPIO_FullRemap_TIM2
* - GPIO_PartialRemap_TIM3
* - GPIO_FullRemap_TIM3
* - GPIO_Remap_TIM4
* - GPIO_Remap1_CAN
* - GPIO_Remap2_CAN
* - GPIO_Remap_PD01
* - GPIO_Remap_SWJ_NoJTRST
* - GPIO_Remap_SWJ_JTAGDisable
* - GPIO_Remap_SWJ_Disable
* - NewState: new state of the port pin remapping.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)
{
u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
/* Check the parameters */
assert(IS_GPIO_REMAP(GPIO_Remap));
assert(IS_FUNCTIONAL_STATE(NewState));
tmpreg = AFIO->MAPR;
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
{
tmpreg &= DBGAFR_SWJCFG_MASK;
}
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
{
tmp1 = ((u32)0x03) << tmpmask;
tmpreg &= ~tmp1;
}
else
{
tmpreg &= ~tmp;
}
if (NewState != DISABLE)
{
if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
{
tmpreg |= (tmp << 0x10);
}
else
{
tmpreg |= tmp;
}
}
AFIO->MAPR = tmpreg;
}
/*******************************************************************************
* Function Name : GPIO_EXTILineConfig
* Description : Selects the GPIO pin used as EXTI Line.
* Input : - GPIO_PortSource: selects the GPIO port to be used as
* source for EXTI lines.
* - GPIO_PinSource: specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
{
u32 tmp = 0x00;
/* Check the parameters */
assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_gpio.c | C | oos | 20,583 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_wwdg.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the WWDG firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_wwdg.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* Alias word address of EWIF bit */
#define SR_OFFSET (WWDG_OFFSET + 0x08)
#define EWIF_BitNumber 0x00
#define SR_EWIF_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_WDGA_Set ((u32)0x00000080)
/* CFR register bit mask */
#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)
#define CFR_W_Mask ((u32)0xFFFFFF80)
#define BIT_Mask ((u8)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : WWDG_DeInit
* Description : Deinitializes the WWDG peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/*******************************************************************************
* Function Name : WWDG_SetPrescaler
* Description : Sets the WWDG Prescaler.
* Input : - WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetPrescaler(u32 WWDG_Prescaler)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[8:7] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
/* Set WDGTB[8:7] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_SetWindowValue
* Description : Sets the WWDG window value.
* Input : - WindowValue: specifies the window value to be compared to
* the downcounter.
* This parameter value must be lower than 0x80.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetWindowValue(u8 WindowValue)
{
u32 tmpreg = 0;
/* Check the parameters */
assert(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_Mask;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & BIT_Mask;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_EnableIT
* Description : Enables the WWDG Early Wakeup interrupt(EWI).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_EnableIT(void)
{
*(vu32 *) CFR_EWI_BB = (u32)ENABLE;
}
/*******************************************************************************
* Function Name : WWDG_SetCounter
* Description : Sets the WWDG counter value.
* Input : - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetCounter(u8 Counter)
{
/* Check the parameters */
assert(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_Mask;
}
/*******************************************************************************
* Function Name : WWDG_Enable
* Description : Enables WWDG and load the counter value.
* - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_Enable(u8 Counter)
{
/* Check the parameters */
assert(IS_WWDG_COUNTER(Counter));
WWDG->CR = CR_WDGA_Set | Counter;
}
/*******************************************************************************
* Function Name : WWDG_GetFlagStatus
* Description : Checks whether the Early Wakeup interrupt flag is set or not.
* Input : None
* Output : None
* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)
*******************************************************************************/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(*(vu32 *) SR_EWIF_BB);
}
/*******************************************************************************
* Function Name : WWDG_ClearFlag
* Description : Clears Early Wakeup interrupt flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_ClearFlag(void)
{
WWDG->SR = (u32)RESET;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_wwdg.c | C | oos | 7,816 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_iwdg.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all the IWDG firmware functions.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_iwdg.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- IWDG registers bit mask ------------------------ */
/* KR register bit mask */
#define KR_Reload ((u16)0xAAAA)
#define KR_Enable ((u16)0xCCCC)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : IWDG_WriteAccessCmd
* Description : Enables or disables write access to IWDG_PR and IWDG_RLR
* registers.
* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and
* IWDG_RLR registers.
* This parameter can be one of the following values:
* - IWDG_WriteAccess_Enable: Enable write access to
* IWDG_PR and IWDG_RLR registers
* - IWDG_WriteAccess_Disable: Disable write access to
* IWDG_PR and IWDG_RLR registers
* Output : None
* Return : None
*******************************************************************************/
void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)
{
/* Check the parameters */
assert(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/*******************************************************************************
* Function Name : IWDG_SetPrescaler
* Description : Sets IWDG Prescaler value.
* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* - IWDG_Prescaler_4: IWDG prescaler set to 4
* - IWDG_Prescaler_8: IWDG prescaler set to 8
* - IWDG_Prescaler_16: IWDG prescaler set to 16
* - IWDG_Prescaler_32: IWDG prescaler set to 32
* - IWDG_Prescaler_64: IWDG prescaler set to 64
* - IWDG_Prescaler_128: IWDG prescaler set to 128
* - IWDG_Prescaler_256: IWDG prescaler set to 256
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetPrescaler(u8 IWDG_Prescaler)
{
/* Check the parameters */
assert(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/*******************************************************************************
* Function Name : IWDG_SetReload
* Description : Sets IWDG Reload value.
* Input : - Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetReload(u16 Reload)
{
/* Check the parameters */
assert(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/*******************************************************************************
* Function Name : IWDG_ReloadCounter
* Description : Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_Reload;
}
/*******************************************************************************
* Function Name : IWDG_Enable
* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
* disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_Enable(void)
{
IWDG->KR = KR_Enable;
}
/*******************************************************************************
* Function Name : IWDG_GetFlagStatus
* Description : Checks whether the specified IWDG flag is set or not.
* Input : - IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - IWDG_FLAG_PVU: Prescaler Value Update on going
* - IWDG_FLAG_RVU: Reload Value Update on going
* Output : None
* Return : The new state of IWDG_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_iwdg.c | C | oos | 6,515 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_lib.c
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : This file provides all peripherals pointers initialization.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#define EXT
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
* Function Name : debug
* Description : This function initialize peripherals pointers.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void debug(void)
{
/************************************* ADC ************************************/
#ifdef _ADC1
ADC1 = (ADC_TypeDef *) ADC1_BASE;
#endif /*_ADC1 */
#ifdef _ADC2
ADC2 = (ADC_TypeDef *) ADC2_BASE;
#endif /*_ADC2 */
/************************************* BKP ************************************/
#ifdef _BKP
BKP = (BKP_TypeDef *) BKP_BASE;
#endif /*_BKP */
/************************************* CAN ************************************/
#ifdef _CAN
CAN = (CAN_TypeDef *) CAN_BASE;
#endif /*_CAN */
/************************************* DMA ************************************/
#ifdef _DMA
DMA = (DMA_TypeDef *) DMA_BASE;
#endif /*_DMA */
#ifdef _DMA_Channel1
DMA_Channel1 = (DMA_Channel_TypeDef *) DMA_Channel1_BASE;
#endif /*_DMA_Channel1 */
#ifdef _DMA_Channel2
DMA_Channel2 = (DMA_Channel_TypeDef *) DMA_Channel2_BASE;
#endif /*_DMA_Channel2 */
#ifdef _DMA_Channel3
DMA_Channel3 = (DMA_Channel_TypeDef *) DMA_Channel3_BASE;
#endif /*_DMA_Channel3 */
#ifdef _DMA_Channel4
DMA_Channel4 = (DMA_Channel_TypeDef *) DMA_Channel4_BASE;
#endif /*_DMA_Channel4 */
#ifdef _DMA_Channel5
DMA_Channel5 = (DMA_Channel_TypeDef *) DMA_Channel5_BASE;
#endif /*_DMA_Channel5 */
#ifdef _DMA_Channel6
DMA_Channel6 = (DMA_Channel_TypeDef *) DMA_Channel6_BASE;
#endif /*_DMA_Channel6 */
#ifdef _DMA_Channel7
DMA_Channel7 = (DMA_Channel_TypeDef *) DMA_Channel7_BASE;
#endif /*_DMA_Channel7 */
/************************************* EXTI ***********************************/
#ifdef _EXTI
EXTI = (EXTI_TypeDef *) EXTI_BASE;
#endif /*_EXTI */
/************************************* FLASH and Option Bytes *****************/
#ifdef _FLASH
FLASH = (FLASH_TypeDef *) FLASH_BASE;
OB = (OB_TypeDef *) OB_BASE;
#endif /*_FLASH */
/************************************* GPIO ***********************************/
#ifdef _GPIOA
GPIOA = (GPIO_TypeDef *) GPIOA_BASE;
#endif /*_GPIOA */
#ifdef _GPIOB
GPIOB = (GPIO_TypeDef *) GPIOB_BASE;
#endif /*_GPIOB */
#ifdef _GPIOC
GPIOC = (GPIO_TypeDef *) GPIOC_BASE;
#endif /*_GPIOC */
#ifdef _GPIOD
GPIOD = (GPIO_TypeDef *) GPIOD_BASE;
#endif /*_GPIOD */
#ifdef _GPIOE
GPIOE = (GPIO_TypeDef *) GPIOE_BASE;
#endif /*_GPIOE */
#ifdef _AFIO
AFIO = (AFIO_TypeDef *) AFIO_BASE;
#endif /*_AFIO */
/************************************* I2C ************************************/
#ifdef _I2C1
I2C1 = (I2C_TypeDef *) I2C1_BASE;
#endif /*_I2C1 */
#ifdef _I2C2
I2C2 = (I2C_TypeDef *) I2C2_BASE;
#endif /*_I2C2 */
/************************************* IWDG ***********************************/
#ifdef _IWDG
IWDG = (IWDG_TypeDef *) IWDG_BASE;
#endif /*_IWDG */
/************************************* NVIC ***********************************/
#ifdef _NVIC
NVIC = (NVIC_TypeDef *) NVIC_BASE;
#endif /*_NVIC */
#ifdef _SCB
SCB = (SCB_TypeDef *) SCB_BASE;
#endif /*_SCB */
/************************************* PWR ************************************/
#ifdef _PWR
PWR = (PWR_TypeDef *) PWR_BASE;
#endif /*_PWR */
/************************************* RCC ************************************/
#ifdef _RCC
RCC = (RCC_TypeDef *) RCC_BASE;
#endif /*_RCC */
/************************************* RTC ************************************/
#ifdef _RTC
RTC = (RTC_TypeDef *) RTC_BASE;
#endif /*_RTC */
/************************************* SPI ************************************/
#ifdef _SPI1
SPI1 = (SPI_TypeDef *) SPI1_BASE;
#endif /*_SPI1 */
#ifdef _SPI2
SPI2 = (SPI_TypeDef *) SPI2_BASE;
#endif /*_SPI2 */
/************************************* SysTick ********************************/
#ifdef _SysTick
SysTick = (SysTick_TypeDef *) SysTick_BASE;
#endif /*_SysTick */
/************************************* TIM1 ***********************************/
#ifdef _TIM1
TIM1 = (TIM1_TypeDef *) TIM1_BASE;
#endif /*_TIM1 */
/************************************* TIM ************************************/
#ifdef _TIM2
TIM2 = (TIM_TypeDef *) TIM2_BASE;
#endif /*_TIM2 */
#ifdef _TIM3
TIM3 = (TIM_TypeDef *) TIM3_BASE;
#endif /*_TIM3 */
#ifdef _TIM4
TIM4 = (TIM_TypeDef *) TIM4_BASE;
#endif /*_TIM4 */
/************************************* USART **********************************/
#ifdef _USART1
USART1 = (USART_TypeDef *) USART1_BASE;
#endif /*_USART1 */
#ifdef _USART2
USART2 = (USART_TypeDef *) USART2_BASE;
#endif /*_USART2 */
#ifdef _USART3
USART3 = (USART_TypeDef *) USART3_BASE;
#endif /*_USART3 */
/************************************* WWDG ***********************************/
#ifdef _WWDG
WWDG = (WWDG_TypeDef *) WWDG_BASE;
#endif /*_WWDG */
}
#endif
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/STM32F10xFWLib/src/stm32f10x_lib.c | C | oos | 6,921 |
/*
* Copyright (C) 2011 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <Max3421e.h>
#include <Usb.h>
#include <AndroidAccessory.h>
#include <string.h>
#include "iNEMO_util.h"
#define USB_ACCESSORY_VENDOR_ID 0x18D1
#define USB_ACCESSORY_PRODUCT_ID 0x2D00
#define USB_ACCESSORY_ADB_PRODUCT_ID 0x2D01
#define ACCESSORY_STRING_MANUFACTURER 0
#define ACCESSORY_STRING_MODEL 1
#define ACCESSORY_STRING_DESCRIPTION 2
#define ACCESSORY_STRING_VERSION 3
#define ACCESSORY_STRING_URI 4
#define ACCESSORY_STRING_SERIAL 5
#define ACCESSORY_GET_PROTOCOL 51
#define ACCESSORY_SEND_STRING 52
#define ACCESSORY_START 53
struct AndroidAccessory androidAccessory;
/* Constructor */
void AndroidAccessory(const char *manufacturer,
const char *model,
const char *description,
const char *version,
const char *uri,
const char *serial)
{
androidAccessory.manufacturer = manufacturer;
androidAccessory.model = model;
androidAccessory.description = description;
androidAccessory.version = version;
androidAccessory.uri = uri;
androidAccessory.serial = serial;
/* Also construct max3421e chip and USB stack */
max3421e();
usbUSB();
print("Android Accessory contructed [ok]\r\n");
}
byte androidAccessoryIsAccessoryDevice(USB_DEVICE_DESCRIPTOR *desc)
{
return desc->idVendor == 0x18d1 && (desc->idProduct == 0x2D00 || desc->idProduct == 0x2D01);
}
void androidAccessoryPowerOn(void)
{
max3421ePowerOn();
delay(200);
}
s16 androidAccessoryGetProtocol(byte addr)
{
s16 protocol = 0xaaaa;
usbCtrlReq_NAK_LIMIT(addr, 0,
USB_SETUP_DEVICE_TO_HOST |
USB_SETUP_TYPE_VENDOR |
USB_SETUP_RECIPIENT_DEVICE,
ACCESSORY_GET_PROTOCOL, 0, 0, 0, 2, (char *)&protocol);
return protocol;
}
void androidAccessorySendString(byte addr, int index, const char *str)
{
usbCtrlReq_NAK_LIMIT(addr, 0,
USB_SETUP_HOST_TO_DEVICE |
USB_SETUP_TYPE_VENDOR |
USB_SETUP_RECIPIENT_DEVICE,
ACCESSORY_SEND_STRING, 0, 0, index,
strlen((char*)str) + 1, (char *)str);
}
bool androidAccessorySwitchDevice(byte addr)
{
int protocol = androidAccessoryGetProtocol(addr);
if (protocol == 1) {
print("device supports protcol 1\r\n");
} else {
print("could not read device protocol version\r\n");
return false;
}
androidAccessorySendString(addr, ACCESSORY_STRING_MANUFACTURER, androidAccessory.manufacturer);
androidAccessorySendString(addr, ACCESSORY_STRING_MODEL, androidAccessory.model);
androidAccessorySendString(addr, ACCESSORY_STRING_DESCRIPTION, androidAccessory.description);
androidAccessorySendString(addr, ACCESSORY_STRING_VERSION, androidAccessory.version);
androidAccessorySendString(addr, ACCESSORY_STRING_URI, androidAccessory.uri);
androidAccessorySendString(addr, ACCESSORY_STRING_SERIAL, androidAccessory.serial);
usbCtrlReq_NAK_LIMIT(addr, 0,
USB_SETUP_HOST_TO_DEVICE |
USB_SETUP_TYPE_VENDOR |
USB_SETUP_RECIPIENT_DEVICE,
ACCESSORY_START, 0, 0, 0, 0, NULL);
while (usbGetUsbTaskState() != USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE) {
max3421eTask();
usbTask();
}
return true;
}
// Finds the first bulk IN and bulk OUT endpoints
bool androidAccessoryFindEndpoints(byte addr, EP_RECORD *inEp, EP_RECORD *outEp)
{
u16 len;
byte err;
u8 *p;
err = usbGetConfDescr(addr, 0, 4, 0, (char *)androidAccessory.descBuff);
if (err) {
print("Can't get config descriptor length\r\n");
return false;
}
len = androidAccessory.descBuff[2] | ((u16)androidAccessory.descBuff[3] << 8);
if (len > sizeof(androidAccessory.descBuff)) {
print("config descriptor too large\r\n");
/* might want to truncate here */
return false;
}
err = usbGetConfDescr(addr, 0, len, 0, (char *)androidAccessory.descBuff);
if (err) {
print("Can't get config descriptor\r\n");
return false;
}
p = androidAccessory.descBuff;
inEp->epAddr = 0;
outEp->epAddr = 0;
while (p < (androidAccessory.descBuff + len)){
u8 descLen = p[0];
u8 descType = p[1];
USB_ENDPOINT_DESCRIPTOR *epDesc;
EP_RECORD *ep;
switch (descType) {
case USB_DESCRIPTOR_CONFIGURATION:
print("config desc\r\n");
break;
case USB_DESCRIPTOR_INTERFACE:
print("interface desc\r\n");
break;
case USB_DESCRIPTOR_ENDPOINT:
epDesc = (USB_ENDPOINT_DESCRIPTOR *)p;
if (!inEp->epAddr && (epDesc->bEndpointAddress & 0x80))
ep = inEp;
else if (!outEp->epAddr)
ep = outEp;
else
ep = NULL;
if (ep) {
ep->epAddr = epDesc->bEndpointAddress & 0x7f;
ep->Attr = epDesc->bmAttributes;
ep->MaxPktSize = epDesc->wMaxPacketSize;
ep->sndToggle = bmSNDTOG0;
ep->rcvToggle = bmRCVTOG0;
}
break;
default:
print("unkown desc type \r\n");
//println( descType, HEX);
break;
}
p += descLen;
}
if (!(inEp->epAddr && outEp->epAddr))
print("can't find accessory endpoints\r\n");
return true;
}
bool androidAccessoryConfigureAndroid(void)
{
byte err;
EP_RECORD inEp, outEp;
if (!androidAccessoryFindEndpoints(1, &inEp, &outEp))
return false;
memset(&androidAccessory.epRecord, 0x0, sizeof(androidAccessory.epRecord));
androidAccessory.epRecord[inEp.epAddr] = inEp;
if (outEp.epAddr != inEp.epAddr)
androidAccessory.epRecord[outEp.epAddr] = outEp;
androidAccessory.in = inEp.epAddr;
androidAccessory.out = outEp.epAddr;
print("End points: ");
printHex(inEp.epAddr);
print(" ");
printHex(outEp.epAddr);
print("\r\n");
androidAccessory.epRecord[0] = *(usbGetDevTableEntry(0,0));
usbSetDevTableEntry(1, androidAccessory.epRecord);
err = usbSetConf( 1, 0, 1 );
if (err) {
print("Can't set config to 1\r\n");
return false;
}
usbSetUsbTaskState( USB_STATE_RUNNING );
return true;
}
/* Start from here...*/
bool androidAccessoryIsConnected(void)
{
USB_DEVICE_DESCRIPTOR *devDesc = (USB_DEVICE_DESCRIPTOR *) androidAccessory.descBuff;
byte err;
max3421eTask();
usbTask();
if (!androidAccessory.connected &&
usbGetUsbTaskState() >= USB_STATE_CONFIGURING &&
usbGetUsbTaskState() != USB_STATE_RUNNING) {
print("nDevice addressed... \r\n");
print("Requesting device descriptor.\r\n");
err = usbGetDevDescr(1, 0, 0x12, (char *) devDesc);
if (err) {
print("Device descriptor cannot be retrieved. Trying again\r\n");
return false;
}
if (androidAccessoryIsAccessoryDevice(devDesc)) {
print("found android acessory device\r\n");
androidAccessory.connected = androidAccessoryConfigureAndroid();
} else {
print("found possible device. swithcing to serial mode\r\n");
androidAccessorySwitchDevice(1);
}
} else if (usbGetUsbTaskState() == USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE) {
if (androidAccessory.connected)
print("disconnect\r\n");
androidAccessory.connected = false;
}
return androidAccessory.connected;
}
int androidAccessoryRead(void *buff, int len, unsigned int nakLimit)
{
return usbNewInTransfer(1, androidAccessory.in, len, (char *)buff, nakLimit);
}
int androidAccessoryWrite(void *buff, int len)
{
usbOutTransfer_NAK_LIMIT(1, androidAccessory.out, len, (char *)buff);
return len;
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/AndroidAccessory/AndroidAccessory.c | C | oos | 8,745 |
/*
* Copyright (C) 2011 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __AndroidAccessory_h__
#define __AndroidAccessory_h__
#include <Usb.h>
#include "stm32_types_compat.h"
struct AndroidAccessory{
const char *manufacturer;
const char *model;
const char *description;
const char *version;
const char *uri;
const char *serial;
//MAX3421E max;
//USB usb;
bool connected;
u8 in;
u8 out;
EP_RECORD epRecord[8];
u8 descBuff[256];
};
byte androidAccessoryIsAccessoryDevice(USB_DEVICE_DESCRIPTOR *desc);
s16 androidAccessoryGetProtocol(byte addr);
void androidAccessorySendString(byte addr, int index, const char *str);
bool androidAccessorySwitchDevice(byte addr);
bool androidAccessoryFindEndpoints(byte addr, EP_RECORD *inEp, EP_RECORD *outEp);
bool androidAccessoryConfigureAndroid(void);
void AndroidAccessory(const char *manufacturer,
const char *model,
const char *description,
const char *version,
const char *uri,
const char *serial);
void androidAccessoryPowerOn(void);
bool androidAccessoryIsConnected(void);
int androidAccessoryRead(void *buff, int len, unsigned int nakLimit);
int androidAccessoryWrite(void *buff, int len);
#endif /* __AndroidAccessory_h__ */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/AndroidAccessory/AndroidAccessory.h | C | oos | 1,880 |
lpryxxxal.o: Sensors\LPRYxxxAL\src\LPRYxxxAL.c
lpryxxxal.o: .\Sensors\LPRYxxxAL\inc\LPRYxxxAL.h
lpryxxxal.o: .\STM32F10xFWLib\inc\stm32f10x_type.h
lpryxxxal.o: .\Sensors\LPRYxxxAL\inc\HAL_LPRYxxxAL.h
lpryxxxal.o: .\Sensors\iNEMO_Config\inc\iNEMO_conf.h
lpryxxxal.o: ..\..\Source\include\FreeRTOS.h
lpryxxxal.o: C:\Keil\ARM\RV31\Inc\stddef.h
lpryxxxal.o: ..\..\Source\include\projdefs.h
lpryxxxal.o: .\iNEMO_task\FreeRTOSConfig.h
lpryxxxal.o: ..\..\Source\include\portable.h
lpryxxxal.o: ..\..\Source\include\../../Source/portable/RVDS/ARM_CM3/portmacro.h
lpryxxxal.o: ..\..\Source\include\mpu_wrappers.h
lpryxxxal.o: ..\..\Source\include\task.h
lpryxxxal.o: ..\..\Source\include\list.h
lpryxxxal.o: .\STM32F10xFWLib\inc\stm32f10x_adc.h
lpryxxxal.o: .\STM32F10xFWLib\inc\stm32f10x_map.h
lpryxxxal.o: .\iNEMO_task\stm32f10x_conf.h
lpryxxxal.o: .\STM32F10xFWLib\inc\cortexm3_macro.h
lpryxxxal.o: .\STM32F10xFWLib\inc\stm32f10x_dma.h
lpryxxxal.o: .\STM32F10xFWLib\inc\stm32f10x_gpio.h
lpryxxxal.o: .\STM32F10xFWLib\inc\stm32f10x_rcc.h
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/lpryxxxal.d | Makefile | oos | 1,052 |
/**
* @file iNEMO_lib.h
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief This file includes the sensor and features header files in the user application.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion */
#ifndef __iNEMO_LIB_H
#define __iNEMO_LIB_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes*/
#include "stm32f10x_type.h"
#include "iNEMO_conf.h"
#include "utils.h"
#include "STLM75.h"
#include "LPS001DL_I2C.h"
#include "LPRYxxxAL.h"
#include "LSM303DLH.h"
/**
* @addtogroup iNEMO_Config
* @{
*/
/**
* @defgroup Sensor_Default_Parameter
* @brief Default value coming from datasheet for Gain and Offset
* @{
*/
#define iNEMO_Default_OffAccX 0
#define iNEMO_Default_OffAccY 0
#define iNEMO_Default_OffAccZ 0
#define iNEMO_Default_OffGyroX 0
#define iNEMO_Default_OffGyroY 0
#define iNEMO_Default_OffGyroZ 0
#define iNEMO_Default_OffMagnX 0
#define iNEMO_Default_OffMagnY 0
#define iNEMO_Default_OffMagnZ 0
#define iNEMO_Default_OffPress 0
#define iNEMO_Default_OffTemp 0
#define iNEMO_Default_GainAccX LSM_Acc_Sensitivity_2g
#define iNEMO_Default_GainAccY LSM_Acc_Sensitivity_2g
#define iNEMO_Default_GainAccZ LSM_Acc_Sensitivity_2g
#define iNEMO_Default_GainGyroX Gyro_SensitivityLSB_R_300dps
#define iNEMO_Default_GainGyroY Gyro_SensitivityLSB_P_300dps
#define iNEMO_Default_GainGyroZ Gyro_SensitivityLSB_Y_300dps
#define iNEMO_Default_GainMagnX LSM_Magn_Sensitivity_XY_1_3Ga
#define iNEMO_Default_GainMagnY LSM_Magn_Sensitivity_XY_1_3Ga
#define iNEMO_Default_GainMagnZ LSM_Magn_Sensitivity_Z_1_3Ga
#define iNEMO_Default_GainPress P_Conversion
#define iNEMO_Default_GainTemp T_Resolution
#define iNEMO_Default_AccODR 0x00
#define iNEMO_Default_AccFS 0x00
#define iNEMO_Default_AccHPF 0x00
#define iNEMO_Default_GyroPRFS 0x04
#define iNEMO_Default_GyroYFS 0x00
#define iNEMO_Default_MagnODR 0x05
#define iNEMO_Default_MagnFS 0x02
#define iNEMO_Default_MagnMD 0x00
#define iNEMO_Default_PressODR 0x03
/**
* @}
*/ /*!< end of group Gain_and_Offset_Default_Values */
#ifdef AHRS_MOD
#include "iNEMO_AHRS.h"
#endif
#ifdef _6X
#include "HAL_LSM303DLH.h"
#include "LSM303DLH.h"
#endif //_6X
#ifdef _GYRO_RPY
#include "HAL_LPRYxxxAL.h"
#include "LPRYxxxAL.h"
#endif
#ifdef _ACC
#include "LIS331DLH_SPI.h"
#include "HAL_LIS331DLH.h"
#endif //_ACC
#ifdef _PRESS
#include "HAL_LPS001DL.h"
#include "LPS001DL_I2C.h"
#endif // _PRESS
#ifdef _TEMP
#include "HAL_STLM75.h"
#include "STLM75.h"
#endif //_TEMP
#ifdef _VCOM
#include "virtual_com.h"
#endif /*_VCOM */
#ifdef _SDIO
#include "sdcard.h"
#endif /*_SDIO */
#ifdef _ULED
#include "iNEMO_led.h"
#endif /*_ULED */
#ifdef _PBUTT
#include "iNEMO_button.h"
#endif /*_PBUTT */
/**
* @struct
* @brief sensor data struct
*/
typedef struct
{
s16 sAcc[3];
s16 sGyro[3];
s16 sMag[3];
s16 sTemp;
u16 uPress;
float uGain[11]; /*AccX AccY AccZ - GyroX GyroY GyroZ - MagnX MagnY MagnZ - Press - Temp*/
s16 sOffset[11]; /*AccX AccY AccZ - GyroX GyroY GyroZ - MagnX MagnY MagnZ - Press - Temp*/
#ifdef AHRS_MOD
iNEMO_QUAT m_quat;
iNEMO_SENSORDATA m_sensorData;
iNEMO_EULER_ANGLES m_angle;
#endif
} iNEMO_DATA;
void iNEMO_HW_Config(void);
void iNEMO_Config(void);
void iNEMO_Data_Init(iNEMO_DATA* data);
bool iNEMO_Set_Sensor(iNEMO_DATA * pdata, u8 usensor, u8 uparameter, u8 ulenght, u8* pvalue);
bool iNEMO_Acc_Set_Config( iNEMO_DATA * pdata, u8 parameter, u8 lenght, u8* value);
bool iNEMO_Magn_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue);
bool iNEMO_GyroPR_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue);
bool iNEMO_GyroYaw_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue);
bool iNEMO_Pressure_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue);
bool iNEMO_Temp_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue);
bool iNEMO_Get_Sensor_Param(iNEMO_DATA * pdata, u8 usensor, u8 uparameter, u8* pvalue);
bool iNEMO_Acc_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue);
bool iNEMO_Magn_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue);
bool iNEMO_GyroPR_Get_Config(iNEMO_DATA * pdata, u8 uparameter, u8* pvalue);
bool iNEMO_GyroY_Get_Config(iNEMO_DATA * pdata, u8 uparameter, u8* pvalue);
bool iNEMO_Pressure_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue);
bool iNEMO_Temp_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue);
bool iNEMO_Restore_DefaultParam(iNEMO_DATA * pdata, u8 usensor, u8 uparameter, u8* pvalue);
TestStatus Test_SDIO(void);
/**
* @}
*/ /*!< end of group iNEMO_Config */
#endif /* __iNEMO_LIB_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/iNEMO_Config/inc/iNEMO_lib.h | C | oos | 5,847 |
/**
* @file iNEMO_conf.h
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief Entry point for iNEMO platform configuration.
* Comment the line below to disable the specific sensor and features inclusion
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion */
#ifndef __iNEMO_CONF_H
#define __iNEMO_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @addtogroup iNEMO_Config
* @{
*/
/**
* \brief This defines allows to choose the functions to make
* some functions atomic or enter in critical section.
* In this case we are using the FreeRTOS API
*/
#define FREERTOS
#ifdef FREERTOS
#include "FreeRTOS.h"
#include "task.h"
#endif
#ifdef FREERTOS
#define iNEMO_ENTER_CRITICAL() taskENTER_CRITICAL()
#define iNEMO_EXIT_CRITICAL() taskEXIT_CRITICAL()
#elif defined (USER_SCHEDULER)
#define iNEMO_ENTER_CRITICAL() userENTER_CRITICAL()
#define iNEMO_EXIT_CRITICAL() userEXIT_CRITICAL()
#elif defined (NO_SCHEDULER)
#define iNEMO_ENTER_CRITICAL()
#define iNEMO_EXIT_CRITICAL()
#endif
/* Comment the line below to disable the specific sensor and features inclusion */
/* AHRS Library Available*/
//#define AHRS_MOD
/* TRACE Available*/
//#define TRACE_MOD
/**Enable 6-axis module ACC+MAGNETOMETER */
#define _6X
/**Enable Gyroscope PR and Y */
//#define _GYRO_RPY
/**Enable PRESSURE sensor */
//#define _PRESS
/* Enable PRESSURE sensor interrupt1*/
//#define INT1_PAD_ENABLE
/**Enable TEMPERATURE sensor */
#define _TEMP
/*Enable TEMPERATURE sensor */
//#define OS_INT_ENABLE
/** Virtual_COM */
//#define _VCOM
/** SDIO */
//#define _SDIO
/** USER_LED */
//#define _ULED
/** Push_Button */
//#define _PBUTT
/**
* @}
*/ /* end of group iNEMO_Config */
#endif /*__iNEMO_CONF_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/iNEMO_Config/inc/iNEMO_conf.h | C | oos | 2,726 |
/**
* @file iNEMO_lib.c
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief Sensor Hardware Configuration & Setup & API.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes */
#include "iNEMO_lib.h"
#include "iNEMO_conf.h"
#include "utils.h"
/**
* @addtogroup iNEMO_Config
* @{
*/
/* Private define */
#define BlockSize 512 /*!< Block Size in Bytes */
#define BufferWordsSize (BlockSize >> 2)
#define NumberOfBlocks 2 /*!< For Multi Blocks operation (Read/Write) */
#define MultiBufferWordsSize ((BlockSize * NumberOfBlocks) >> 2)
#define iNEMO_OffAccX(data) (data->sOffset[0])
#define iNEMO_OffAccY(data) (data->sOffset[1])
#define iNEMO_OffAccZ(data) (data->sOffset[2])
#define iNEMO_OffGyroX(data) (data->sOffset[3])
#define iNEMO_OffGyroY(data) (data->sOffset[4])
#define iNEMO_OffGyroZ(data) (data->sOffset[5])
#define iNEMO_OffMagnX(data) (data->sOffset[6])
#define iNEMO_OffMagnY(data) (data->sOffset[7])
#define iNEMO_OffMagnZ(data) (data->sOffset[8])
#define iNEMO_OffPress(data) (data->sOffset[9])
#define iNEMO_OffTemp(data) (data->sOffset[10])
#define iNEMO_GainAccX(data) (data->uGain[0])
#define iNEMO_GainAccY(data) (data->uGain[1])
#define iNEMO_GainAccZ(data) (data->uGain[2])
#define iNEMO_GainGyroX(data) (data->uGain[3])
#define iNEMO_GainGyroY(data) (data->uGain[4])
#define iNEMO_GainGyroZ(data) (data->uGain[5])
#define iNEMO_GainMagnX(data) (data->uGain[6])
#define iNEMO_GainMagnY(data) (data->uGain[7])
#define iNEMO_GainMagnZ(data) (data->uGain[8])
#define iNEMO_GainPress(data) (data->uGain[9])
#define iNEMO_GainTemp(data) (data->uGain[10])
/* Private variables */ /*
volatile TestStatus EraseStatus = FAILED, TransferStatus1 = FAILED, TransferStatus2 = FAILED;
static u32 s_Buffer_Block_Tx[BufferWordsSize];
static u32 s_Buffer_Block_Rx[BufferWordsSize];
static u32 s_Buffer_MultiBlock_Tx[MultiBufferWordsSize];
static u32 s_Buffer_MultiBlock_Rx[MultiBufferWordsSize];
*/
/**
* @addtogroup iNEMO_Config_Function
*@{
*/
/**
* @brief Configure the hardware for the iNEMO platform
* */
void iNEMO_HW_Config(void)
{
#ifdef _ULED
iNEMO_Led_Init(LED1);
#endif //_ULED
#ifdef _VCOM
iNEMO_USB_Disconnet_Pin_Config();
USB_Cable_Config(ENABLE);
Set_USBClock();
USB_Interrupts_Config();
USB_Init();
#endif //_VCOM
#ifdef _PRESS
LPS001DL_I2C_Init();
#ifdef INT1_PAD_ENABLE
LPS001DL_INT1_Config();
#endif //INT1_PAD_ENABLE
#endif //_PRESS
#ifdef _TEMP
STLM75_I2C_Init();
#endif //_TEMP
#ifdef _SDIO
SD_Init();
#endif // _SDIO
#ifdef _PBUTT
iNEMO_Button_Init(BUTTON_KEY, BUTTON_MODE_GPIO);
#endif //_PBUTT
#ifdef _6X
LSM303DLH_I2C_Init();
#endif
#ifdef _GYRO_RPY
LPRYxxxAL_ADC_Init();
LPRYxxxAL_DMA_Init();
LPRYxxxAL_PD_ST_Init();
#endif
}
/**
* @brief Initialize the iNEMO data structur
*/
void iNEMO_Data_Init(iNEMO_DATA* data)
{
iNEMO_OffAccX(data)=iNEMO_Default_OffAccX;
iNEMO_OffAccY(data)=iNEMO_Default_OffAccY;
iNEMO_OffAccZ(data)=iNEMO_Default_OffAccZ;
iNEMO_OffGyroX(data)=iNEMO_Default_OffGyroX;
iNEMO_OffGyroY(data)=iNEMO_Default_OffGyroY;
iNEMO_OffGyroZ(data)=iNEMO_Default_OffGyroZ;
iNEMO_OffMagnX(data)=iNEMO_Default_OffMagnX;
iNEMO_OffMagnY(data)=iNEMO_Default_OffMagnY;
iNEMO_OffMagnZ(data)=iNEMO_Default_OffMagnZ;
iNEMO_OffPress(data)=iNEMO_Default_OffPress;
iNEMO_OffTemp(data)=iNEMO_Default_OffTemp;
iNEMO_GainAccX(data)= iNEMO_Default_GainAccX;
iNEMO_GainAccY(data)= iNEMO_Default_GainAccY;
iNEMO_GainAccZ(data)= iNEMO_Default_GainAccZ;
iNEMO_GainGyroX(data)=iNEMO_Default_GainGyroX;
iNEMO_GainGyroY(data)=iNEMO_Default_GainGyroY;
iNEMO_GainGyroZ(data)=iNEMO_Default_GainGyroZ;
iNEMO_GainMagnX(data)=iNEMO_Default_GainMagnX;
iNEMO_GainMagnY(data)=iNEMO_Default_GainMagnY;
iNEMO_GainMagnZ(data)=iNEMO_Default_GainMagnZ;
iNEMO_GainPress(data)=iNEMO_Default_GainPress;
iNEMO_GainTemp(data)=iNEMO_Default_GainTemp;
}
/**
* @brief Initialize the iNEMO sensor platform
*/
void iNEMO_Config(void)
{
#ifdef _6X
LSM_Acc_ConfigTypeDef LSM_Acc_InitStructure;
LSM_Acc_Filter_ConfigTypeDef LSM_Acc_FilterStructure;
LSM_Magn_ConfigTypeDef LSM_Magn_InitStructure;
#endif
#ifdef _ACC
LIS331DLH_ConfigTypeDef LIS331DLH_InitStructure;
LIS331DLH_Filter_ConfigTypeDef LIS331DLH_FilterStructure;
#endif
#ifdef _MAG
HMC5843_ConfigTypeDef HMC5843_InitStructure;
#endif
#ifdef _PRESS
LPS001DL_ConfigTypeDef LPS001DL_InitStructure;
LPS001DL_InterruptTypeDef LPS001DL_InterruptStructure;
#endif
#ifdef _TEMP
#ifdef OS_INT_ENABLE
STLM75_InterruptTypeDef STLM75_InterruptStructure;
#endif
#endif
#ifdef _GYRO_RPY
LPRYxxxAL_On();
LPRYxxxAL_ST_Off();
#endif
#ifdef _6X
LSM_Acc_InitStructure.Power_Mode = LSM_Acc_Lowpower_NormalMode;
LSM_Acc_InitStructure.ODR = LSM_Acc_ODR_50;
LSM_Acc_InitStructure.Axes_Enable= LSM_Acc_XYZEN;
LSM_Acc_InitStructure.FS = LSM_Acc_FS_2;
LSM_Acc_InitStructure.Data_Update = LSM_Acc_BDU_Continuos;
LSM_Acc_InitStructure.Endianess=LSM_Acc_Big_Endian;
LSM_Acc_FilterStructure.HPF_Enable=LSM_Acc_Filter_Disable;
LSM_Acc_FilterStructure.HPF_Mode=LSM_Acc_FilterMode_Normal;
LSM_Acc_FilterStructure.HPF_Reference=0x00;
LSM_Acc_FilterStructure.HPF_Frequency=LSM_Acc_Filter_HPc16;
LSM303DLH_Acc_Config(&LSM_Acc_InitStructure);
LSM303DLH_Acc_Filter_Config(&LSM_Acc_FilterStructure);
LSM_Magn_InitStructure.M_ODR = LSM_Magn_ODR_30;
LSM_Magn_InitStructure.Meas_Conf = LSM_Magn_MEASCONF_NORMAL;
LSM_Magn_InitStructure.Gain = LSM_Magn_GAIN_1_3;
LSM_Magn_InitStructure.Mode = LSM_Magn_MODE_CONTINUOS ;
LSM303DLH_Magn_Config(&LSM_Magn_InitStructure);
#endif
#ifdef _ACC
LIS331DLH_InitStructure.Power_Mode = LIS331DLH_Lowpower_NormalMode;
LIS331DLH_InitStructure.ODR = LIS331DLH_ODR_50;
LIS331DLH_InitStructure.Axes_Enable= LIS331DLH_XYZEN;
LIS331DLH_InitStructure.FS = LIS331DLH_FS_2;
LIS331DLH_InitStructure.Data_Update = LIS331DLH_BDU_Continuos;
LIS331DLH_InitStructure.Endianess=LIS331DLH_Little_Endian;
LIS331DLH_FilterStructure.HPF_Enable=LIS331DLH_Filter_Disable;
LIS331DLH_FilterStructure.HPF_Mode=LIS331DLH_FilterMode_Normal;
LIS331DLH_FilterStructure.HPF_Reference=0x00;
LIS331DLH_FilterStructure.HPF_Frequency=LIS331DLH_Filter_HPc64;
LIS331DLH_Config(&LIS331DLH_InitStructure);
LIS331DLH_Filter_Config(&LIS331DLH_FilterStructure);
#endif /*_ACC */
#ifdef _MAG
HMC5843_InitStructure.M_ODR = HMC5843_ODR_10;
HMC5843_InitStructure.Meas_Conf = HMC5843_MEASCONF_NORMAL;
HMC5843_InitStructure.Gain = HMC5843_GAIN_1;
HMC5843_InitStructure.Mode = HMC5843_MODE_CONTINUOS ;
HMC5843_Config(&HMC5843_InitStructure);
#endif /*_MAG */
#ifdef _PRESS
/* LPS001DL configuration */
LPS001DL_InitStructure.Lowpower = LPS001DL_Lowpower_Disable;
LPS001DL_InitStructure.Output_Data_Rate = LPS001DL_Output_Data_Rate_12_12;
LPS001DL_InitStructure.Data_Update = LPS001DL_BDU_Continuos; //LPS001DL_BDU_Single;
LPS001DL_InitStructure.Endianess = LPS001DL_Little_Endian;
/* LPS001DL interrupt configuration */
LPS001DL_InterruptStructure.Mode = LPS001DL_Interrupt_Active_High;
LPS001DL_InterruptStructure.PP_OD = LPS001DL_Interrupt_Push_Pull;
LPS001DL_InterruptStructure.Int2_Pad_Mode =LPS001DL_Interrupt_Pressure_Low;
LPS001DL_InterruptStructure.Int1_Pad_Mode = LPS001DL_Interrupt_Pressure_High;
LPS001DL_InterruptStructure.Latch = LPS001DL_Interrupt_Latch_Disable;
LPS001DL_InterruptStructure.Delta_Press_Low = LSP001DL_Interrupt_DPL_Enable;
LPS001DL_InterruptStructure.Delta_Press_High = LSP001DL_Interrupt_DPH_Enable;
LPS001DL_Config(&LPS001DL_InitStructure);
LPS001DL_Interrupt_Config(&LPS001DL_InterruptStructure);
LPS001DL_PowerDown_Cmd(DISABLE);
#endif /*_PRESS */
#ifdef _TEMP
#ifdef OS_INT_ENABLE
STLM75_InterruptTypeDef STLM75_InterruptStructure;
/* STLM75 interrupt configuration */
STLM75_InterruptStructure.Mode = STLM75_Interrupt_Mode; //STLM75_Comparator_Mode;
STLM75_InterruptStructure.Polarity = STLM75_Polarity_Low;
STLM75_InterruptStructure.Fault_Number = Fault_Value_1;
STLM75_InterruptStructure.Over_Limit_Value = 305;
STLM75_InterruptStructure.Hysteresis_Value = 290;
STLM75_Interrupt_Config(&STLM75_InterruptStructure);
#endif //OS_INT_ENABLE
#endif /*_TEMP */
}
/**
* @brief Change a a configuration parameter of a iNEMO sensor
* @param pData : poiter to iNEMO_data structure
* @param usensor : the sensor type (0x00 = Accelerometer; 0x01 = Gyroscope; 0x02 Pitch/Roll Gyro; 0x03 Yaw Gyro; 0x04 = Pressure; 0x05 Temp)
* @ulenght : Lenght of value payload
* @param uparamter : paramenter to change
* @param pvalue : new value to set
*/
bool iNEMO_Set_Sensor(iNEMO_DATA * pdata, u8 usensor, u8 uparameter, u8 ulenght, u8* pvalue)
{
bool isAllowed =FALSE;
switch(usensor)
{
case 0x00 : /*!< Accelerometer */
isAllowed = iNEMO_Acc_Set_Config(pdata, uparameter, ulenght, pvalue);
break;
case 0x01 : /*!< Magnetometer */
isAllowed = iNEMO_Magn_Set_Config(pdata,uparameter,ulenght, pvalue);
break;
case 0x02 : /*!< Roll and Pitch Gyro */
isAllowed = iNEMO_GyroPR_Set_Config(pdata,uparameter,ulenght, pvalue);
break;
case 0x03 : /*!< Yaw Gyro */
isAllowed = iNEMO_GyroYaw_Set_Config(pdata,uparameter,ulenght, pvalue);
break;
#ifdef _PRESS
case 0x04 : /*!< Pressure Sensor*/
isAllowed = iNEMO_Pressure_Set_Config(pdata,uparameter,ulenght, pvalue);
break;
#endif
case 0x05 : /*!< Temperature Sensor*/
isAllowed = iNEMO_Temp_Set_Config(pdata,uparameter,ulenght, pvalue);
break;
}
return isAllowed;
}
/**
* @brief Change a a configuration parameter of a iNEMO sensor
* @param pData : poiter to iNEMO_data structure
* @param parameter : paramenter to change <ul>
* <li>0x00 - Output data rate</li>
* <li>0x01 Full Scale </li>
* <li>0x02 HPF </li>
* <li>0x03 Offset X </li>
* <li>0x04 Offset Y </li>
* <li>0x05 Offset Z </li>
* </ul>
* @ulenght : Lenght of value payload
* @param value : new value to set
*/
bool iNEMO_Acc_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue)
{
bool isAllowed=FALSE;
switch(uparameter)
{
case 0x00: /*!< set ODR */
if(pvalue[0] < 0x04 && ulenght == 2)
{
u8 uCtrl=0;;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl, LSM_A_CTRL_REG1_ADDR, 1);
uCtrl = (uCtrl & 0xE7) + (pvalue[0] << 3);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &uCtrl, LSM_A_CTRL_REG1_ADDR);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl, LSM_A_CTRL_REG1_ADDR, 1);
/* check if the command has been executed */
if(((uCtrl >> 3) & 0x03) == pvalue[0])
/* if yes send ack */
isAllowed=TRUE;
else
/* else send nack */
isAllowed=FALSE;
}
else
{
isAllowed=FALSE;
}
break;
case 0x01: /*!< Set Full scale*/
if(pvalue[0] < 0x04 && pvalue[0] != 0x02 && ulenght == 2 )
{
u8 uCtrl=0;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl, LSM_A_CTRL_REG4_ADDR, 1);
uCtrl =(uCtrl & 0xCF) + ((pvalue[0] & 0x03) << 4);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &uCtrl, LSM_A_CTRL_REG4_ADDR);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl, LSM_A_CTRL_REG4_ADDR, 1);
/* check if the command has been executed */
if(((uCtrl & 0x30) >> 4 ) == pvalue[0])
/* if yes */
{
switch(pvalue[0])
{
/* update Gain Value*/
case 0x00:
iNEMO_GainAccX(pdata)= LSM_Acc_Sensitivity_2g;
iNEMO_GainAccY(pdata)= LSM_Acc_Sensitivity_2g;
iNEMO_GainAccZ(pdata)= LSM_Acc_Sensitivity_2g;
break;
case 0x01:
iNEMO_GainAccX(pdata)= LSM_Acc_Sensitivity_4g;
iNEMO_GainAccY(pdata)= LSM_Acc_Sensitivity_4g;
iNEMO_GainAccZ(pdata)= LSM_Acc_Sensitivity_4g;
break;
case 0x03:
iNEMO_GainAccX(pdata)= LSM_Acc_Sensitivity_8g;
iNEMO_GainAccY(pdata)= LSM_Acc_Sensitivity_8g;
iNEMO_GainAccZ(pdata)= LSM_Acc_Sensitivity_8g;
break;
}
isAllowed=TRUE;
}
else
/* else send nack */
isAllowed=FALSE;
}
else
isAllowed=FALSE;
break;
case 0x02: /* HPF enable*/
if(ulenght == 3)
{
u8 temp=pvalue[0];
/*
pvalue[0] = | RFU |RFU |Filter Enable/Disable |REF ENABLE/DISABLE |HP1 |HP0 | ODR1 |ODR0
*/
if((temp & 0x20) == 0x20) /* check filter ENABLE command */
{
u8 uCtrl1, uCtrl2, temp2, ref;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl1, LSM_A_CTRL_REG1_ADDR, 1);
uCtrl1 = (uCtrl1 & 0xE7) + ((temp & 0x03) << 3); //set ODR
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &uCtrl1, LSM_A_CTRL_REG1_ADDR);/*!<set the ODR value in the ctrl1 register*/
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl1, LSM_A_CTRL_REG1_ADDR, 1);
if((temp & 0x10) == 0x10) /* check if reference is enabled */
{
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &temp2, LSM_A_CTRL_REG2_ADDR, 1);
uCtrl2 = ((temp2 & 0xCC) + ((temp & 0x0C) >> 2) + 0x30); /* !<set cut off frequency and bits to enble filter and enable reference */
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR, 1);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &pvalue[1], LSM_A_REFERENCE_REG_ADDR); /*!<WRITE the refence value in the LSM_A_REFERENCE_REG_ADDR register*/
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &ref, LSM_A_REFERENCE_REG_ADDR,1);
temp2= ((uCtrl2 & 0x03) <<2) + (uCtrl2 & 0x30);
temp2 = (temp2 & 0xFC) + ((uCtrl1 & 0x18) >> 3);
if((temp2 == temp) && (ref==pvalue[1])) /*!< check if the command has been executed && ((uCtrl2 & 0x10) == 0x10)*/
isAllowed=TRUE;
else
isAllowed=FALSE;
}
else
{
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR, 1);
uCtrl2 = ((temp2 & 0xCC) + ((temp & 0x0C) >> 2) + 0x10); /*!< set cut off frequency and set to 1 FDS bit to enble filter */
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR, 1);
uCtrl1 = ((uCtrl1 & 0x18) >> 3);
uCtrl1 = uCtrl1 + ((uCtrl2 & 0x03) <<2) ;
uCtrl1 = uCtrl1 + ((uCtrl2 & 0x10)<<1);
if((uCtrl1 == temp ) && ((uCtrl2 & 0x10) == 0x10)) /*!< check if the command has been executed*/
isAllowed=TRUE;
else
isAllowed=FALSE;
}
}
else /* filter disable*/
{
u8 uCtrl2;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR, 1);
uCtrl2 = (uCtrl2 & 0xCF); /* !< set to 0 FDS bit to disable filter */
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, 0x00, LSM_A_REFERENCE_REG_ADDR);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &uCtrl2, LSM_A_CTRL_REG2_ADDR, 1);
if((uCtrl2 & 0x10) == 0x00)
isAllowed=TRUE;
else
isAllowed=FALSE;
}
}
break;
case 0x03: /* !< set x axis offset*/
if(ulenght == 3 )
{
iNEMO_OffAccX(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
case 0x04: /*!< set y axis offset*/
if(ulenght == 3 )
{
iNEMO_OffAccY(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
case 0x05: /*!< set z axis offset*/
if(ulenght == 3 )
{
iNEMO_OffAccZ(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
}
return isAllowed;
}
/**
* @brief Change a configuration parameter of a iNEMO magnetometer
* @param parameter : paramenter to change <ul>
* <li>0x00 - Output data rate</li>
* <li>0x01 Full Scale </li>
* <li>0x02 MAGN operationg mode </li>
* <li>0x03 Offset X </li>
* <li>0x04 Offset Y </li>
* <li>0x05 Offset Z </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_Magn_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue)
{
bool isAllowed=FALSE;
switch(uparameter)
{
case 0x00: /*!< set ODR */
if(pvalue[0] < 0x07 && ulenght == 2)
{
u8 uCtrl;
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRA_REG_ADDR, 1);
uCtrl = (uCtrl & 0xE3) + (pvalue[0] << 2);
LSM303DLH_I2C_ByteWrite(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRA_REG_ADDR);
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRA_REG_ADDR, 1);
/* check if the command has been executed */
if(((uCtrl >>2) & 0x07) == pvalue[0])
/* if yes send ack */
isAllowed=TRUE;
else
/* else send nack */
isAllowed=FALSE;
}
else
{
isAllowed=FALSE;
}
break;
case 0x01: /*!< Set Full scale*/
if(pvalue[0] < 0x08 && pvalue[0] > 0x00 && ulenght == 2 )
{
u8 uCtrl;
uCtrl =(pvalue[0] << 5) & 0xE0;
LSM303DLH_I2C_ByteWrite(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRB_REG_ADDR);
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRB_REG_ADDR, 1);
/* check if the command has been executed */
if(((uCtrl >>5) & 0x07) == pvalue[0])
{
switch(pvalue[0])
{
case 0x01:
iNEMO_GainMagnX(pdata)= LSM_Magn_Sensitivity_XY_1_3Ga;
iNEMO_GainMagnY(pdata)= LSM_Magn_Sensitivity_XY_1_3Ga;
iNEMO_GainMagnZ(pdata)= LSM_Magn_Sensitivity_XY_1_3Ga;
break;
case 0x02:
iNEMO_GainMagnX(pdata)= LSM_Magn_Sensitivity_XY_1_9Ga;
iNEMO_GainMagnY(pdata)= LSM_Magn_Sensitivity_XY_1_9Ga;
iNEMO_GainMagnZ(pdata)= LSM_Magn_Sensitivity_Z_1_9Ga;
break;
case 0x03:
iNEMO_GainMagnX(pdata)= LSM_Magn_Sensitivity_XY_2_5Ga;
iNEMO_GainMagnY(pdata)= LSM_Magn_Sensitivity_XY_2_5Ga;
iNEMO_GainMagnZ(pdata)= LSM_Magn_Sensitivity_Z_2_5Ga;
break;
case 0x04:
iNEMO_GainMagnX(pdata)= LSM_Magn_Sensitivity_XY_4Ga;
iNEMO_GainMagnY(pdata)= LSM_Magn_Sensitivity_XY_4Ga;
iNEMO_GainMagnZ(pdata)= LSM_Magn_Sensitivity_Z_4Ga;
break;
case 0x05:
iNEMO_GainMagnX(pdata)= LSM_Magn_Sensitivity_XY_4_7Ga;
iNEMO_GainMagnY(pdata)= LSM_Magn_Sensitivity_XY_4_7Ga;
iNEMO_GainMagnZ(pdata)= LSM_Magn_Sensitivity_Z_4_7Ga;
break;
case 0x06:
iNEMO_GainMagnX(pdata)= LSM_Magn_Sensitivity_XY_5_6Ga;
iNEMO_GainMagnY(pdata)= LSM_Magn_Sensitivity_XY_5_6Ga;
iNEMO_GainMagnZ(pdata)= LSM_Magn_Sensitivity_Z_5_6Ga;
break;
case 0x07:
iNEMO_GainMagnX(pdata)= LSM_Magn_Sensitivity_XY_8_1Ga;
iNEMO_GainMagnY(pdata)= LSM_Magn_Sensitivity_XY_8_1Ga;
iNEMO_GainMagnZ(pdata)= LSM_Magn_Sensitivity_Z_8_1Ga;
break;
}
isAllowed=TRUE;
}
else
/* else send nack */
isAllowed=FALSE;
}
else
isAllowed=FALSE;
break;
case 0x02: /*!< Magn operating mode*/
if(pvalue[0] < 0x03 && ulenght == 2)
{
u8 uCtrl;
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRA_REG_ADDR, 1);
uCtrl = (uCtrl & 0xFC) + pvalue[0];
LSM303DLH_I2C_ByteWrite(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRA_REG_ADDR);
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &uCtrl, LSM_M_CRA_REG_ADDR, 1);
/* check if the command has been executed */
if(((uCtrl & 0x03) == pvalue[0]))
/* if yes send ack */
isAllowed=TRUE;
else
/* else send nack */
isAllowed=FALSE;
}
else
{
isAllowed=FALSE;
}
break;
case 0x03: /*!< set x axis offset*/
if(ulenght == 3 )
{
iNEMO_OffMagnX(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
case 0x04: /*!< set y axis offset*/
if(ulenght == 3 )
{
iNEMO_OffMagnY(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
case 0x05: /*!< set z axis offset*/
if(ulenght == 3 )
{
iNEMO_OffMagnZ(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
}
return isAllowed;
}
/**
* @brief Change a configuration parameter of a iNEMO gyro roll-pitch
* @param parameter : paramenter to change <ul>
* <li>0x00 Full Scale </li>
* <li>0x01 Offset X </li>
* <li>0x02 Offset Y </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_GyroPR_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue)
{
bool isAllowed=FALSE;
switch(uparameter)
{
case 0x00: /*!< set FS */
if((pvalue[0]==0x04 || pvalue[0]==0x08) && ulenght == 2)
{
switch(pvalue[0])
{
case 0x04: /*!< 300dps*/
iNEMO_GainGyroX(pdata)= Gyro_SensitivityLSB_R_300dps;
iNEMO_GainGyroY(pdata)= Gyro_SensitivityLSB_P_300dps;
isAllowed=TRUE;
break;
case 0x08: /*!< 1200dps*/
iNEMO_GainGyroX(pdata)= Gyro_SensitivityLSB_R_1200dps;
iNEMO_GainGyroY(pdata)= Gyro_SensitivityLSB_P_1200dps;
isAllowed=TRUE;
break;
}
}
else
isAllowed=FALSE;
break;
case 0x01: /*!< set x axis offset*/
if(ulenght == 3 )
{
iNEMO_OffGyroX(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
case 0x02: /*!< set y axis offset*/
if(ulenght == 3 )
{
iNEMO_OffGyroY(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
}
return isAllowed;
}
/**
* @brief Change a configuration parameter of a iNEMO gyro Yaw
* @param parameter : paramenter to change <ul>
* <li>0x00 Full Scale </li>
* <li>0x01 Offset X </li>
* <li>0x02 Offset Y </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_GyroYaw_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue)
{
bool isAllowed=FALSE;
switch(uparameter)
{
case 0x00: /*!< set FS */
if(pvalue[0] == 0x04 && ulenght == 2)
{
switch(pvalue[0])
{
case 0x04: /* 300dps*/
iNEMO_GainGyroZ(pdata)= Gyro_SensitivityLSB_Y_300dps;
isAllowed=TRUE;
break;
}
}
else
isAllowed=FALSE;
break;
case 0x01: /*!< set z axis offset*/
if(ulenght == 3 )
{
iNEMO_OffGyroZ(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
}
return isAllowed;
}
/**
* @brief Change a configuration parameter of a iNEMO pressure sensor
* @param parameter : paramenter to change <ul>
* <li>0x00 - Output data rate</li>
* <li>0x01 Offset </li>
* </ul>
* @param value : new value to set
*/
#ifdef _PRESS
bool iNEMO_Pressure_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue)
{
bool isAllowed=FALSE;
switch(uparameter)
{
case 0x00: /*!< ODR */
if((pvalue[0] == 0x03 || pvalue[0] == 0x01) && ulenght == 2)
{
u8 uCtrl;
LPS001DL_Read(&uCtrl, LPS001DL_CTRL_REG1_ADDR, 1);
uCtrl = (uCtrl & 0xCF) + ( pvalue[0] << 4);
LPS001DL_Write(&uCtrl, LPS001DL_CTRL_REG1_ADDR, 1);
LPS001DL_Read(&uCtrl, LPS001DL_CTRL_REG1_ADDR, 1);
/* check if the command has been executed */
if(((uCtrl & 0x30)>>4) == pvalue[0])
/* if yes send ack */
isAllowed=TRUE;
else
/* else send nack */
isAllowed=FALSE;
}
else
{
isAllowed=FALSE;
}
break;
case 0x01: /*!< set pressure offset*/
if(ulenght == 3)
{
iNEMO_OffPress(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
}
return isAllowed;
}
#endif
/**
* @brief Change a configuration parameter of a iNEMO temerature sensor
* @param parameter : paramenter to change <ul>
* <li>0x00 Offset </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_Temp_Set_Config( iNEMO_DATA * pdata, u8 uparameter, u8 ulenght, u8* pvalue)
{
bool isAllowed=FALSE;
switch(uparameter)
{
case 0x00: /*!< set temperature offset*/
if(ulenght == 3)
{
iNEMO_OffTemp(pdata)=((s16)pvalue[0] << 8) + pvalue[1];
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
}
return isAllowed;
}
/**
* @brief Get a configuration parameter of a iNEMO sensor
* @param pData : poiter to iNEMO_data structure
* @param usensor : the sensor type (0x00 = Accelerometer; 0x01 = Gyroscope; 0x02 Pitch/Roll Gyro; 0x03 Yaw Gyro; 0x04 = Pressure; 0x05 Temp)
* @param uparamter : paramenter to get
*/
bool iNEMO_Get_Sensor_Param(iNEMO_DATA * pdata, u8 usensor, u8 uparameter, u8* pvalue)
{
bool isAllowed =FALSE;
switch(usensor)
{
case 0x00 : /*!< Accelerometer */
isAllowed = iNEMO_Acc_Get_Config(pdata, uparameter, pvalue);
break;
case 0x01 : /*!< Magnetometer */
isAllowed = iNEMO_Magn_Get_Config(pdata,uparameter, pvalue);
break;
case 0x02 : /*!< Roll and Pitch Gyro */
isAllowed = iNEMO_GyroPR_Get_Config(pdata,uparameter, pvalue);
break;
case 0x03 : /*!< Yaw Gyro */
isAllowed = iNEMO_GyroY_Get_Config(pdata,uparameter, pvalue);
break;
#ifdef _PRESS
case 0x04 : /*!< Pressure Sensor*/
isAllowed = iNEMO_Pressure_Get_Config(pdata,uparameter, pvalue);
break;
#endif
case 0x05 : /*!< Temperature Sensor*/
isAllowed = iNEMO_Temp_Get_Config(pdata,uparameter, pvalue);
break;
}
return isAllowed;
}
/**
* @brief Get a configuration parameter of a iNEMO accelerometer
* @param parameter : paramenter to change <ul>
* <li>0x00 - Output data rate</li>
* <li>0x01 Full Scale </li>
* <li>0x02 HPF </li>
* <li>0x03 Offset X </li>
* <li>0x04 Offset Y </li>
* <li>0x05 Offset Z </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_Acc_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue)
{
bool isAllowed=FALSE;
/* pValue temp[0]=lengh of payload, temp[1]=sensor, temp[2]=parameter, temp[3]=payload1, temp[4]=payload2(if any)*/
pvalue[1]=0x00;
switch(uparameter)
{
case 0x00: /* set ODR */
pvalue[0]=3;
pvalue[2]=0x00;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &pvalue[3], LSM_A_CTRL_REG1_ADDR, 1);
pvalue[3]=((pvalue[3] >> 3) & 0x03);
isAllowed=TRUE;
break;
case 0x01: /* Set Full scale*/
pvalue[0]=3;
pvalue[2]=0x1;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &pvalue[3], LSM_A_CTRL_REG4_ADDR, 1);
pvalue[3]=((pvalue[3] & 0x30) >> 4 );
isAllowed=TRUE;
break;
case 0x02: /* HPF */
/*
return:
temp[0]=payload lenght
temp[1] = | RFU |RFU |Filter Enable/Disable |REF ENABLE/DISABLE |HP1 |HP0 | ODR1 |ODR0
temp[2] = referemce value
*/
{
u8 ctrl, temp=0;
pvalue[0]=4;
pvalue[2]=0x02;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &ctrl, LSM_A_CTRL_REG1_ADDR, 1); // read ODR
temp = (ctrl & 0x18)>> 3 ;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &ctrl, LSM_A_CTRL_REG2_ADDR, 1);
temp = (temp & 0xF3) + ((ctrl & 0x03) << 2);
if((ctrl & 0x60) == 0x20) /* reference enabled*/
temp = temp + 0x10;
if((ctrl & 0x10) == 0x10) /* filter enabled */
temp = temp + 0x20;
pvalue[3]=temp;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &pvalue[4], LSM_A_REFERENCE_REG_ADDR,1); /*!<read the refence value in the LSM_A_REFERENCE_REG_ADDR register*/
isAllowed=TRUE;
break;
}
case 0x03: /* set x axis offset*/
/*
return:
temp[0]=payload lenght
temp[3] = offset MSB
temp[4] = offset LSB
*/
pvalue[0]=4;
pvalue[2]=0x03;
s16_to_u8_buffer(&iNEMO_OffAccX(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
case 0x04: /* set y axis offset*/
/*
return:
temp[0]=payload lenght
temp[3] = offset MSB
temp[4] = offset LSB
*/
pvalue[0]=4;
pvalue[2]=0x04;
s16_to_u8_buffer(&iNEMO_OffAccY(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
case 0x05: /* set z axis offset*/
/*
return:
temp[0]=payload lenght
temp[3] = offset MSB
temp[4] = offset LSB
*/
{ s16 temp=iNEMO_OffAccZ(pdata);
pvalue[0]=4;
pvalue[2]=0x05;
s16_to_u8_buffer(&temp, &pvalue[3]);
isAllowed=TRUE;
}
break;
}
return isAllowed;
}
/**
* @brief Get a configuration parameter of a iNEMO magnetometer
* @param parameter : paramenter to change <ul>
* <li>0x00 Output data rate</li>
* <li>0x01 Full Scale </li>
* <li>0x02 MAGN operationg mode </li>
* <li>0x03 Offset X </li>
* <li>0x04 Offset Y </li>
* <li>0x05 Offset Z </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_Magn_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue)
{
bool isAllowed=FALSE;
/*
return:
temp[0]=payload lenght
temp[1] = sensor
temp[2] = paramter
temp[3] = payload1
temp[4] = payload2
*/
pvalue[1]=0x01;
switch(uparameter)
{
case 0x00: /* Get ODR */
pvalue[0]=3;
pvalue[2]=0x00;
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &pvalue[3], LSM_M_CRA_REG_ADDR, 1);
pvalue[3]=(pvalue[3] >>2) & 0x07;
isAllowed=TRUE;
break;
case 0x01: /* Get Full scale*/
pvalue[0]=3;
pvalue[2]=0x01;
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &pvalue[3], LSM_M_CRB_REG_ADDR, 1);
pvalue[3]=(pvalue[3] >>5) & 0x07;
isAllowed=TRUE;
break;
case 0x02: /* Magn operating mode*/
pvalue[0]=3;
pvalue[2]=0x02;
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &pvalue[3], LSM_M_CRA_REG_ADDR, 1);
pvalue[3]= pvalue[3] & 0x03;
isAllowed=TRUE;
break;
case 0x03: /* set x axis offset*/
pvalue[0]=4;
pvalue[2]=0x03;
s16_to_u8_buffer(&iNEMO_OffMagnX(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
case 0x04: /* set y axis offset*/
pvalue[0]=4;
pvalue[2]=0x04;
s16_to_u8_buffer(&iNEMO_OffMagnY(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
case 0x05: /* set z axis offset*/
pvalue[0]=4;
pvalue[2]=0x05;
s16_to_u8_buffer(&iNEMO_OffMagnZ(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
}
return isAllowed;
}
/**
* @brief Get a configuration parameter of a iNEMO Gyro Pitch and Roll
* @param parameter : paramenter to change <ul>
* <li>0x00 Full Scale </li>
* <li>0x01 Offset X </li>
* <li>0x02 Offset Y </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_GyroPR_Get_Config(iNEMO_DATA * pdata, u8 uparameter, u8* pvalue)
{
bool isAllowed=FALSE;
/*
return:
temp[0] = payload lenght
temp[1] = sensor
temp[2] = parameter
temp[3] = payload1
temp[4] = payload2
*/
pvalue[1]=0x02;
switch(uparameter)
{
case 0x00: /* Full Scale*/
/*
temp[3] = gain --> 0x04 = 300dps ; 0x08 =1200dps
*/
pvalue[0]=3;
pvalue[2]=0x00;
if(iNEMO_GainGyroX(pdata) > (u16)Gyro_SensitivityLSB_R_300dps)
{
pvalue[3]=0x04;
isAllowed=TRUE;
}
else if(iNEMO_GainGyroX(pdata)==Gyro_SensitivityLSB_R_1200dps)
{
pvalue[3]=0x08;
isAllowed=TRUE;
}
else
isAllowed=FALSE;
break;
case 0x01: /* set x axis offset*/
/*
temp[3] = offset MSB
temp[4] = offset LSB
*/
pvalue[0]=4;
pvalue[2]=0x01;
s16_to_u8_buffer(&iNEMO_OffGyroX(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
case 0x02: /* set y axis offset*/
/*
temp[3] = offset MSB
temp[4] = offset LSB
*/
pvalue[0]=4;
pvalue[2]=0x02;
s16_to_u8_buffer(&iNEMO_OffGyroY(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
}
return isAllowed;
}
/**
* @brief Get a configuration parameter of a iNEMO Gyro Pitch and Roll
* @param parameter : paramenter to change <ul>
* <li>0x00 Full Scale </li>
* <li>0x01 Offset X </li>
* <li>0x02 Offset Y </li>
* </ul>
* @param value : new value to set
*/
bool iNEMO_GyroY_Get_Config(iNEMO_DATA * pdata, u8 uparameter, u8* pvalue)
{
bool isAllowed=FALSE;
/*
return:
temp[0]=payload lenght
temp[1] = sensor
temp[2] = parameter
temp[3] = payload1
temp[4] = payload2
*/
pvalue[1]=0x03;
switch(uparameter)
{
case 0x00: /* Full Scale*/
/*
temp[3] = gain --> 0x00 = 300dps
*/
pvalue[0]=3;
pvalue[2]=0x00;
/* if(iNEMO_GainGyroZ(pdata)==(u16)Gyro_SensitivityLSB_Y_300dps) //TODO
{
*/
pvalue[3]= 0x04;
isAllowed=TRUE;
/* }
else
isAllowed=FALSE; */
break;
case 0x01: /* set x axis offset*/
/*
return:
temp[3] = offset MSB
temp[4] = offset LSB
*/
pvalue[0]=4;
pvalue[2]=0x01;
s16_to_u8_buffer(&iNEMO_OffGyroZ(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
}
return isAllowed;
}
/**
* @brief Get a configuration parameter of a iNEMO Pressure Sensor
* @param parameter : paramenter to change <ul>
* <li>0x00 ODR </li>
* <li>0x01 Offset </li>
* </ul>
* @param value : value to get
*/
#ifdef _PRESS
bool iNEMO_Pressure_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue)
{
bool isAllowed=FALSE;
/*
return:
temp[0]=payload lenght
temp[1] = sensor
temp[2] = parameter
temp[3] = payload1
temp[4] = payload2
*/
pvalue[1]=0x04;
switch(uparameter)
{
case 0x00: /*!< ODR */
pvalue[0]=3;
pvalue[2]=0x00;
LPS001DL_Read(&pvalue[3], LPS001DL_CTRL_REG1_ADDR, 1);
pvalue[3]=(pvalue[3] & 0x30)>>4;
isAllowed=TRUE;
break;
case 0x01: /*!< set pressure offset*/
pvalue[0]=4;
pvalue[2]=0x01;
s16_to_u8_buffer(&iNEMO_OffPress(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
}
return isAllowed;
}
#endif
/**
* @brief Get a configuration parameter of a iNEMO Temperature Sensor
* @param parameter : paramenter to change <ul>
* <li>0x01 Offset </li>
* </ul>
* @param value : value to get
*/
bool iNEMO_Temp_Get_Config( iNEMO_DATA * pdata, u8 uparameter, u8* pvalue)
{
bool isAllowed=FALSE;
/*
return:
temp[0]=payload lenght
temp[1] = sensor
temp[2] = paramter
temp[3] = payload1
temp[4] = payload2
*/
pvalue[1]=0x05;
switch(uparameter)
{
case 0x00: /*!< set pressure offset*/
pvalue[0]=4;
pvalue[2]=0x00;
s16_to_u8_buffer(&iNEMO_OffTemp(pdata), &pvalue[3]);
isAllowed=TRUE;
break;
}
return isAllowed;
}
/**
* @brief Change a a configuration parameter of a iNEMO sensor
* @param pData : poiter to iNEMO_data structure
* @param usensor : the sensor type (0x00 = Accelerometer; 0x01 = Gyroscope; 0x02 Pitch/Roll Gyro; 0x03 Yaw Gyro; 0x04 = Pressure; 0x05 Temp)
* @ulenght : Lenght of value payload
* @param uparamter : paramenter to change
* @param pvalue : new value to set
*/
bool iNEMO_Restore_DefaultParam(iNEMO_DATA * pdata, u8 usensor, u8 uparameter, u8* pvalue)
{
bool isAllowed =FALSE;
switch(usensor)
{
case 0x00 : /*!< Accelerometer */
switch(uparameter)
{
case 0x00: /*!< set ODR */
pvalue[0]=3;
pvalue[1]=iNEMO_Default_AccODR;
isAllowed = iNEMO_Acc_Set_Config(pdata, uparameter, 2, &pvalue[1]);
break;
case 0x01: /*!< set FS */
pvalue[0]=3;
pvalue[1]=iNEMO_Default_AccFS;
isAllowed = iNEMO_Acc_Set_Config(pdata, uparameter, 2, &pvalue[1]);
break;
case 0x02: /*!< set HPS */
pvalue[0]=4;
pvalue[1]=iNEMO_Default_AccHPF;
isAllowed = iNEMO_Acc_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x03: /*!< Set x offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffAccX & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffAccX & 0x00FF);
isAllowed = iNEMO_Acc_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x04: /*!< Set y offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffAccY & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffAccY & 0x00FF);
isAllowed = iNEMO_Acc_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x05: /*!< Set z offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffAccZ & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffAccZ & 0x00FF);
isAllowed = iNEMO_Acc_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
}
break;
case 0x01 : /*!< Magnetometer */
switch(uparameter)
{
case 0x00: /*!< set ODR */
pvalue[0]=3;
pvalue[1]=iNEMO_Default_MagnODR;
isAllowed = iNEMO_Magn_Set_Config(pdata, uparameter, 2, &pvalue[1]);
break;
case 0x01: /*!< set ODR */
pvalue[0]=3;
pvalue[1]=iNEMO_Default_MagnFS;
isAllowed = iNEMO_Magn_Set_Config(pdata, uparameter, 2, &pvalue[1]);
break;
case 0x02: /*!< set Mode */
pvalue[0]=4;
pvalue[1]=iNEMO_Default_MagnMD;
isAllowed = iNEMO_Magn_Set_Config(pdata, uparameter, 2, &pvalue[1]);
break;
case 0x03: /*!< Set x offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffMagnX & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffMagnX & 0x00FF);
isAllowed = iNEMO_Magn_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x04: /*!< Set y offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffMagnY & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffMagnY & 0x00FF);
isAllowed = iNEMO_Magn_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x05: /*!< Set z offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffMagnZ & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffMagnZ & 0x00FF);
isAllowed = iNEMO_Magn_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
}
break;
case 0x02 : /*!< Roll and Pitch Gyro */
switch(uparameter)
{
case 0x00: /*!<Full Scal*/
pvalue[0]=3;
pvalue[1]=0x04; /* 300dps*/
isAllowed = iNEMO_GyroPR_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x01: /*!<Set x offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffGyroX & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffGyroX & 0x00FF);
isAllowed = iNEMO_GyroPR_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x02: /*!<Set y offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffGyroY & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffGyroY & 0x00FF);
isAllowed = iNEMO_GyroPR_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
}
break;
case 0x03 : /*!<Yaw Gyro */
switch(uparameter)
{
case 0x00: /*!< Full Scal*/
pvalue[0]=3;
pvalue[1]=0x04; /*!<300dps*/
isAllowed = iNEMO_GyroYaw_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
case 0x01: /*!<Set z offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffGyroZ & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffGyroZ & 0x00FF);
isAllowed = iNEMO_GyroYaw_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
}
break;
#ifdef _PRESS
case 0x04 : /*!< Pressure Sensor*/
switch(uparameter)
{
case 0x00: /*!< set ODR */
pvalue[0]=3;
pvalue[1]=iNEMO_Default_PressODR;
isAllowed = iNEMO_Pressure_Set_Config(pdata,uparameter,2, &pvalue[1]);
break;
case 0x01: /*!< Set z offset*/
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffPress & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffPress & 0x00FF);
isAllowed = iNEMO_Pressure_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
}
break;
#endif
case 0x05 : /*!< Temperature Sensor*/
switch(uparameter)
{
case 0x00: /*!< set ODR */
pvalue[0]=4;
pvalue[1]=(u8)((iNEMO_Default_OffTemp & 0xFF00)>>8);
pvalue[2]=(u8)(iNEMO_Default_OffTemp & 0x00FF);
isAllowed = iNEMO_Temp_Set_Config(pdata, uparameter, 3, &pvalue[1]);
break;
}
break;
}
return isAllowed;
}
/**
* @brief Test SDIO
*/
#ifdef _SDIO
TestStatus Test_SDIO(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
SD_CardInfo SDCardInfo;
SD_Error Status = SD_OK;
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 11;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* SD Init */
Status = SD_Init();
if (Status == SD_OK)
{
/* Read CSD/CID MSD registers */
Status = SD_GetCardInfo(&SDCardInfo);
}
if (Status == SD_OK)
{
/* Select Card -*/
Status = SD_SelectDeselect((u32) (SDCardInfo.RCA << 16));
}
if (Status == SD_OK)
{
Status = SD_EnableWideBusOperation(SDIO_BusWide_4b);
}
/* Block Erase */
if (Status == SD_OK)
{
/* Erase NumberOfBlocks Blocks of WRITE_BL_LEN(512 Bytes) */
Status = SD_Erase(0x00, (BlockSize * NumberOfBlocks));
}
/* Set Device Transfer Mode to DMA */
if (Status == SD_OK)
{
Status = SD_SetDeviceMode(SD_DMA_MODE);
}
if (Status == SD_OK)
{
Status = SD_ReadMultiBlocks(0x00, s_Buffer_MultiBlock_Rx, BlockSize, NumberOfBlocks);
}
if (Status == SD_OK)
{
EraseStatus = eBuffercmp(s_Buffer_MultiBlock_Rx, MultiBufferWordsSize);
}
/* Block Read/Write */
/* Fill the buffer to send */
Fill_Buffer(s_Buffer_Block_Tx, BufferWordsSize, 0xFFFF);
if (Status == SD_OK)
{
/* Write block of 512 bytes on address 0 */
Status = SD_WriteBlock(0x00, s_Buffer_Block_Tx, BlockSize);
}
if (Status == SD_OK)
{
/* Read block of 512 bytes from address 0 */
Status = SD_ReadBlock(0x00, s_Buffer_Block_Rx, BlockSize);
}
if (Status == SD_OK)
{
/* Check the corectness of written dada */
TransferStatus1 = Buffercmp(s_Buffer_Block_Tx, s_Buffer_Block_Rx, BufferWordsSize);
}
/* Multiple Block Read/Write */
/* Fill the buffer to send */
Fill_Buffer(s_Buffer_MultiBlock_Tx, MultiBufferWordsSize, 0x0);
if (Status == SD_OK)
{
/* Write multiple block of many bytes on address 0 */
Status = SD_WriteMultiBlocks(0x00, s_Buffer_MultiBlock_Tx, BlockSize, NumberOfBlocks);
}
if (Status == SD_OK)
{
/* Read block of many bytes from address 0 */
Status = SD_ReadMultiBlocks(0x00, s_Buffer_MultiBlock_Rx, BlockSize, NumberOfBlocks);
}
if (Status == SD_OK)
{
/* Check the corectness of written dada */
TransferStatus2 = Buffercmp(s_Buffer_MultiBlock_Tx, s_Buffer_MultiBlock_Rx, MultiBufferWordsSize);
}
if(EraseStatus==PASSED && TransferStatus1==PASSED && TransferStatus2==PASSED)
return PASSED;
else
return FAILED;
}
#else
/* If the _SDIO macro is not defined in iNEMO_conf.h file, the test simply return FAILED*/
TestStatus Test_SDIO(void) {
return FAILED;
}
#endif
/**
* @}
*/ /* end of group iNEMO_Config_Function */
/**
* @}
*/ /* end of group iNEMO_Config */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/iNEMO_Config/src/iNEMO_lib.c | C | oos | 48,524 |
/**
* @file HAL_LPS001DL.h
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief Hardware Abstraction Layer for LPS001DL.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_LPS001DL_H
#define __HAL_LPS001DL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
#include "iNEMO_conf.h"
/**
* @addtogroup LPS001DL
* @{
*/
/**
* @addtogroup LPS001DL_I2C_Define
* @{
*/
#define PRESS_I2C I2C2
#define PRESS_RCC_Periph_I2C RCC_APB1Periph_I2C2
#define PRESS_I2C_Port GPIOB
#define PRESS_I2C_SCL_Pin GPIO_Pin_10
#define PRESS_I2C_SDA_Pin GPIO_Pin_11
#define PRESS_RCC_Port_I2C RCC_APB2Periph_GPIOB
#define PRESS_I2C_Speed 100000
/**
*@}
*/ /* end of group LPS001DL_I2C_Define */
/**
*@addtogroup LPS001DL_Interrupt_Port_Defines
*@{
*/
#ifdef INT1_PAD_ENABLE
#define LPS001DL_INT1_Port GPIOA
#define LPS001DL_INT1_RCC RCC_APB2Periph_GPIOA
#define LPS001DL_INT1_Pin GPIO_Pin_9
#define LPS001DL_INT1_Port_Source GPIO_PortSourceGPIOA
#define LPS001DL_INT1_Pin_Source GPIO_PinSource9
#define LPS001DL_INT1_EXTI_Line EXTI_Line9
#define LPS001DL_INT1_Edge EXTI_Trigger_Rising /*!<It must be coherent with Mode field of LPS001DL_InterruptTypeDef structure */
#define LPS001DL_INT1_EXTI_IRQCHANNEL EXTI9_5_IRQn
#define LPS001DL_INT1_Preemption_Priority 12
#define LPS001DL_INT1_Sub_Priority 0
#endif /*!<INT1_PAD_ENABLE */
/**
*@}
*/ /* end of group LPS001DL_Interrupt_Port_Defines */
/**
* @}
*/ /* end of group LPS001DL */
#endif /* __HAL_LPS001DL_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/LPS001DL/inc/HAL_LPS001DL.h | C | oos | 2,774 |
/**
* @file HAL_LSM303DLH.h
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief Hardware Abstraction Layer for LSM303DLH.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion*/
#ifndef __HAL_LSM303DLH_H
#define __HAL_LSM303DLH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "stm32f10x_type.h"
/**
* @addtogroup LSM303DLH
* @{
*/
/**
* @addtogroup LSM303DLH_I2C_Define
* @{
*/
#define LSM_I2C I2C1
#define LSM_I2C_RCC_Periph RCC_APB1Periph_I2C1
#define LSM_I2C_Port GPIOB
#define LSM_I2C_SCL_Pin GPIO_Pin_6
#define LSM_I2C_SDA_Pin GPIO_Pin_7
#define LSM_I2C_RCC_Port RCC_APB2Periph_GPIOB
#define LSM_I2C_Speed 100000
/**
*@}
*/ /* end of group LSM303DLH_I2C_Define */
/**
* @addtogroup Magnetometer
* @{
*/
/**
* @addtogroup Magnetometer_I2C_Define
* @{
*/
#define LSM_M_I2C I2C1
#define LSM_M_I2C_RCC_Periph RCC_APB1Periph_I2C1
#define LSM_M_I2C_Port GPIOB
#define LSM_M_I2C_SCL_Pin GPIO_Pin_6
#define LSM_M_I2C_SDA_Pin GPIO_Pin_7
#define LSM_M_I2C_RCC_Port RCC_APB2Periph_GPIOB
#define LSM_M_I2C_Speed 100000
/**
*@}
*/ /* end of group Magnetometer_I2C_Define */
/**
* @addtogroup Magnetometer_Interrupt_Pin_Define
* @{
*/
//#ifdef LSM_M_DRDY_ENABLE
#define LSM_M_DRDY_Pin GPIO_Pin_8
#define LSM_M_DRDY_Port GPIOB
#define LSM_M_DRDY_RCC_Port RCC_APB2Periph_GPIOB
#define LSM_M_DRDY_Port_Source GPIO_PortSourceGPIOB
#define LSM_M_DRDY_Pin_Source GPIO_PinSource8
#define LSM_M_DRDY_EXTI_Line EXTI_Line8
#define LSM_M_DRDY_Edge EXTI_Trigger_Falling
#define LSM_M_DRDY_EXTI_IRQCHANNEL EXTI9_5_IRQChannel
#define LSM_M_DRDY_Preemption_Priority 3
#define LSM_M_DRDY_Sub_Priority 3
//#endif
/**
* @}
*/ /* end of group Magnetometer_Interrupt_Pin_Define */
/**
* @}
*/ /* end of group Magnetometer */
/**
* @addtogroup Accelerometer
* @{
*/
/**
* @addtogroup Accelerometer_Interrupt_Pin_Define
* @{
*/
#ifdef LSM_A_INT1_ENABLE
#define LSM_A_INT1_Pin GPIO_Pin_12
#define LSM_A_INT1_Port GPIOB
#define LSM_A_INT1_RCC_Port RCC_APB2Periph_GPIOB
#endif
#ifdef LSM_A_INT2_ENABLE
#define LSM_A_INT2_Pin GPIO_Pin_13
#define LSM_A_INT2_Port GPIOB
#define LSM_A_INT2_RCC_Port RCC_APB2Periph_GPIOB
#endif
/**
*@}
*/ /* end of group Accelerometer_Interrupt_Pin_Define */
/**
* @addtogroup Accelerometer_I2C_Defines
* @{
*/
#define LSM_A_I2C I2C1
#define LSM_A_I2C_RCC_Periph RCC_APB1Periph_I2C1
#define LSM_A_I2C_Port GPIOB
#define LSM_A_I2C_SCL_Pin GPIO_Pin_6
#define LSM_A_I2C_SDA_Pin GPIO_Pin_7
#define LSM_A_I2C_RCC_Port RCC_APB2Periph_GPIOB
#define LSM_A_I2C_Speed 100000
/**
*@}
*/ /* end of group Accelerometer_I2C_Defines */
/**
* @}
*/ /* end of group Accelerometer */
/**
*@}
*/ /* end of group LSM303DLH */
#endif /* __HAL_LSM303DLH_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/LSM303DLH/inc/HAL_LSM303DLH.h | C | oos | 4,095 |
/**
* @file LSM303DLH.c
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief This file provides a set of functions needed to manage the
* communication between STM32 I2C master and LSM303DLH I2C slave.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Includes */
#include "LSM303DLH.h"
#include "HAL_LSM303DLH.h"
#include "iNEMO_conf.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_rcc.h"
/**
* @defgroup LSM303DLH
* @{
*/
/** @defgroup LSM303DLH_I2C_Function
* @{
*/
/**
* @brief Initializes the I2C peripheral used to drive the LSM303DLH
* @param None
* @retval None
*/
void LSM303DLH_I2C_Init(void)
{
I2C_InitTypeDef I2C_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable I2C and GPIO clocks */
RCC_APB1PeriphClockCmd(LSM_I2C_RCC_Periph, ENABLE);
RCC_APB2PeriphClockCmd(LSM_I2C_RCC_Port, ENABLE);
/* Configure I2C pins: SCL and SDA */
GPIO_InitStructure.GPIO_Pin = LSM_I2C_SCL_Pin | LSM_I2C_SDA_Pin;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
GPIO_Init(LSM_I2C_Port, &GPIO_InitStructure);
/* I2C configuration */
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
I2C_InitStructure.I2C_OwnAddress1 = 0x00;
I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_InitStructure.I2C_ClockSpeed = LSM_I2C_Speed;
/* Apply I2C configuration after enabling it */
I2C_Init(LSM_I2C, &I2C_InitStructure);
/* I2C Peripheral Enable */
I2C_Cmd(LSM_I2C, ENABLE);
}
/**
* @brief Writes one byte to the LSM303DLH.
* @param slAddr : slave address LSM_A_I2C_ADDRESS or LSM_M_I2C_ADDRESS
* @param pBuffer : pointer to the buffer containing the data to be written to the LSM303DLH.
* @param WriteAddr : address of the register in which the data will be written
* @retval None
*/
void LSM303DLH_I2C_ByteWrite(u8 slAddr, u8* pBuffer, u8 WriteAddr)
{
iNEMO_ENTER_CRITICAL();
/* Send START condition */
I2C_GenerateSTART(LSM_I2C, ENABLE);
/* Test on EV5 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_MODE_SELECT));
/* Send LSM303DLH_Magn address for write */
I2C_Send7bitAddress(LSM_I2C, slAddr, I2C_Direction_Transmitter);
/* Test on EV6 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
/* Send the LSM303DLH_Magn's internal address to write to */
I2C_SendData(LSM_I2C, WriteAddr);
/* Test on EV8 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
/* Send the byte to be written */
I2C_SendData(LSM_I2C, *pBuffer);
/* Test on EV8 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
/* Send STOP condition */
I2C_GenerateSTOP(LSM_I2C, ENABLE);
iNEMO_EXIT_CRITICAL();
}
/**
* @brief Reads a block of data from the LSM303DLH.
* @param slAddr : slave address LSM_A_I2C_ADDRESS or LSM_M_I2C_ADDRESS
* @param pBuffer : pointer to the buffer that receives the data read from the LSM303DLH.
* @param ReadAddr : LSM303DLH's internal address to read from.
* @param NumByteToRead : number of bytes to read from the LSM303DLH ( NumByteToRead >1 only for the Mgnetometer readinf).
* @retval None
*/
void LSM303DLH_I2C_BufferRead(u8 slAddr, u8* pBuffer, u8 ReadAddr, u16 NumByteToRead)
{
iNEMO_ENTER_CRITICAL();
/* While the bus is busy */
while(I2C_GetFlagStatus(LSM_I2C, I2C_FLAG_BUSY));
/* Send START condition */
I2C_GenerateSTART(LSM_I2C, ENABLE);
/* Test on EV5 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_MODE_SELECT));
/* Send LSM303DLH_Magn address for write */
I2C_Send7bitAddress(LSM_I2C, slAddr, I2C_Direction_Transmitter);
/* Test on EV6 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
/* Clear EV6 by setting again the PE bit */
I2C_Cmd(LSM_I2C, ENABLE);
/* Send the LSM303DLH_Magn's internal address to write to */
I2C_SendData(LSM_I2C, ReadAddr);
/* Test on EV8 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
/* Send STRAT condition a second time */
I2C_GenerateSTART(LSM_I2C, ENABLE);
/* Test on EV5 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_MODE_SELECT));
/* Send LSM303DLH address for read */
I2C_Send7bitAddress(LSM_I2C, slAddr, I2C_Direction_Receiver);
/* Test on EV6 and clear it */
while(!I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED));
/* While there is data to be read */
while(NumByteToRead)
{
if(NumByteToRead == 1)
{
/* Disable Acknowledgement */
I2C_AcknowledgeConfig(LSM_I2C, DISABLE);
/* Send STOP Condition */
I2C_GenerateSTOP(LSM_I2C, ENABLE);
}
/* Test on EV7 and clear it */
if(I2C_CheckEvent(LSM_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED))
{
/* Read a byte from the LSM303DLH */
*pBuffer = I2C_ReceiveData(LSM_I2C);
/* Point to the next location where the byte read will be saved */
pBuffer++;
/* Decrement the read bytes counter */
NumByteToRead--;
}
}
/* Enable Acknowledgement to be ready for another reception */
I2C_AcknowledgeConfig(LSM_I2C, ENABLE);
iNEMO_EXIT_CRITICAL();
}
/**
* @}
*/ /* end of group LSM303DLH_I2C_Function */
/**
* @addtogroup Accelerometer
* @{
*/
/**
* @defgroup Accelerometer_Function
* @{
*/
/**
* @brief Set configuration of Linear Acceleration measurement of LSM303DLH
* @param LSM_Acc_Config_Struct : pointer to a LSM_Acc_ConfigTypeDef structure that contains the configuration setting for the Accelerometer LSM303DLH.
* @retval None
*/
void LSM303DLH_Acc_Config(LSM_Acc_ConfigTypeDef *LSM_Acc_Config_Struct)
{
u8 CRTL1 = 0x00;
u8 CRTL4 = 0x00;
CRTL1 |= (u8) (LSM_Acc_Config_Struct->Power_Mode | LSM_Acc_Config_Struct->ODR| LSM_Acc_Config_Struct->Axes_Enable);
CRTL4 |= (u8) (LSM_Acc_Config_Struct->FS | LSM_Acc_Config_Struct->Data_Update| LSM_Acc_Config_Struct->Endianess);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &CRTL1, LSM_A_CTRL_REG1_ADDR);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &CRTL4, LSM_A_CTRL_REG4_ADDR);
}
/**
* @brief Set configuration of Internal High Pass Filter of LSM303DLH for the linear acceleration
* @param LSM303DLH_Filter_ConfigTypeDef : pointer to a LSM303DLH_ConfigTypeDef structure that
* contains the configuration setting for the LSM303DLH.
* @retval None
*/
void LSM303DLH_Acc_Filter_Config(LSM_Acc_Filter_ConfigTypeDef *LSM_Acc_Filter_Config_Struct)
{
u8 CRTL2 = 0x00;
u8 REF = 0x00;
CRTL2 |= (u8) (LSM_Acc_Filter_Config_Struct->HPF_Enable | LSM_Acc_Filter_Config_Struct->HPF_Mode| LSM_Acc_Filter_Config_Struct->HPF_Frequency);
REF |= (u8) (LSM_Acc_Filter_Config_Struct->HPF_Reference);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &CRTL2, LSM_A_CTRL_REG2_ADDR);
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS, &REF, LSM_A_REFERENCE_REG_ADDR);
}
/**
* @brief Change the lowpower mode for Accelerometer of LSM303DLH
* @param LowPowerMode : new state for the lowpower mode. This parameter can be: LSM303DLH_Lowpower_x see LSM303DLH_SPI.h file
* @retval None
*/
void LSM303DLH_Acc_Lowpower_Cmd(u8 LowPowerMode)
{
u8 tmpreg;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &tmpreg, LSM_A_CTRL_REG1_ADDR, 1);
tmpreg &= 0x1F;
tmpreg |= LowPowerMode;
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS,&tmpreg, LSM_A_CTRL_REG1_ADDR);
}
/**
* @brief Change the ODR(Output data rate) for Acceleromter of LSM303DLH
* @param DataRateValue : new ODR value. This parameter can be: LSM303DLH_ODR_x see LSM303DLH_SPI.h file
* @retval None
*/
void LSM303DLH_Acc_DataRate_Cmd(u8 DataRateValue)
{
u8 tmpreg;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &tmpreg, LSM_A_CTRL_REG1_ADDR, 1);
tmpreg &= 0xE7;
tmpreg |= DataRateValue;
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS,&tmpreg, LSM_A_CTRL_REG1_ADDR);
}
/**
* @brief Change the Full Scale of LSM303DLH
* @param FS_value : new full scale value. This parameter can be: LSM303DLH_FS_x see LSM303DLH_SPI.h file
* @retval None
*/
void LSM303DLH_Acc_FullScale_Cmd(u8 FS_value)
{
u8 tmpreg;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &tmpreg, LSM_A_CTRL_REG4_ADDR, 1);
tmpreg &= 0xCF;
tmpreg |= FS_value;
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS,&tmpreg, LSM_A_CTRL_REG4_ADDR);
}
/**
* @brief Reboot memory content of LSM303DLH
* @param None
* @retval None
*/
void LSM303DLH_Acc_Reboot_Cmd(void)
{
u8 tmpreg;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &tmpreg, LSM_A_CTRL_REG2_ADDR, 1);
tmpreg |= 0x80;
LSM303DLH_I2C_ByteWrite(LSM_A_I2C_ADDRESS,&tmpreg, LSM_A_CTRL_REG2_ADDR);
}
/**
* @brief Read LSM303DLH linear acceleration output register
* @param out : buffer to store data
* @retval None
*/
void LSM_Acc_Read_OutReg(u8* out)
{
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, out, (LSM_A_OUT_X_L_ADDR | 0x80), 6);
}
/**
* @brief Read LSM303DLH output register, and calculate the raw acceleration [LSB] ACC= (out_h*256+out_l)/16 (12 bit rappresentation)
* @param out : buffer to store data
* @retval None
*/
void LSM303DLH_Acc_Read_RawData(s16* out)
{
u8 buffer[6];
u8 crtl4;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &crtl4, LSM_A_CTRL_REG4_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[0], LSM_A_OUT_X_L_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[1], LSM_A_OUT_X_H_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[2], LSM_A_OUT_Y_L_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[3], LSM_A_OUT_Y_H_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[4], LSM_A_OUT_Z_L_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[5], LSM_A_OUT_Z_H_ADDR, 1);
/* check in the control register4 the data alignment*/
if(!(crtl4 & 0x40))
{
int i = 0;
for(i=0; i<3; i++)
{
out[i]=(s16)(((u16)buffer[2*i+1] << 8) + buffer[2*i]);
}
}
else
{
int i = 0;
for(i=0; i<3; i++)
out[i]=((s16)((u16)buffer[2*i] << 8) + buffer[2*i+1])/16;
}
}
/**
* @brief Read LSM303DLH output register, and calculate the acceleration ACC=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation)
* @param out : buffer to store data
* @retval None
*/
void LSM303DLH_Acc_Read_Acc(s16* out)
{
u8 buffer[6];
u8 crtl4;
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &crtl4, LSM_A_CTRL_REG4_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[0], LSM_A_OUT_X_L_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[1], LSM_A_OUT_X_H_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[2], LSM_A_OUT_Y_L_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[3], LSM_A_OUT_Y_H_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[4], LSM_A_OUT_Z_L_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_A_I2C_ADDRESS, &buffer[5], LSM_A_OUT_Z_H_ADDR, 1);
/* check in the control register4 the data alignment*/
if(!(crtl4 & 0x40))
{
int i = 0;
/* switch the sensitivity value set in the CRTL4*/
switch(crtl4 & 0x30)
{
case 0x00:
for(i=0; i<3; i++)
{
out[i]=(s16)(((u16)buffer[2*i+1] << 8) + buffer[2*i])/LSM_Acc_Sensitivity_2g;
}
break;
case 0x10:
for(i=0; i<3; i++)
out[i]=(s16)(((u16)buffer[2*i+1] << 8) + buffer[2*i])/LSM_Acc_Sensitivity_4g;
break;
case 0x30:
for(i=0; i<3; i++)
out[i]=(s16)(((u16)buffer[2*i+1] << 8) + buffer[2*i])/LSM_Acc_Sensitivity_8g;
}
}
else
{
int i = 0;
switch(crtl4 & 0x30)
{
case 0x00:
for(i=0; i<3; i++)
out[i]=((s16)((u16)buffer[2*i] << 8) + buffer[2*i+1])/(16*LSM_Acc_Sensitivity_2g);
break;
case 0x10:
for(i=0; i<3; i++)
out[i]=((s16)((u16)buffer[2*i] << 8) + buffer[2*i+1])/(16*LSM_Acc_Sensitivity_4g);
break;
case 0x30:
for(i=0; i<3; i++)
out[i]=((s16)((u16)buffer[2*i] << 8) + buffer[2*i+1])/(16*LSM_Acc_Sensitivity_8g);
break;
}
}
}
/**
*@}
*/ /* end of group Accelerometer_Function */
/**
* @}
*/ /* end of group Accelerometer */
/**
* @addtogroup Magnetometer
* @{
*/
/**
* @defgroup Magnetometer_Function
* @{
*/
/**
* @brief Set configuration of Magnetic field measurement of LSM303DLH
* @param LSM_Magn_Config_Struct : pointer to LSM_Magn_ConfigTypeDef structure that
* contains the configuration setting for the LSM303DLH_Magn.
* @retval None
*/
void LSM303DLH_Magn_Config(LSM_Magn_ConfigTypeDef *LSM_Magn_Config_Struct)
{
u8 CRTLA = 0x00;
u8 CRTLB = 0x00;
u8 MODE = 0x00;
CRTLA |= (u8) (LSM_Magn_Config_Struct->M_ODR | LSM_Magn_Config_Struct->Meas_Conf);
CRTLB |= (u8) (LSM_Magn_Config_Struct->Gain);
MODE |= (u8) (LSM_Magn_Config_Struct->Mode);
LSM303DLH_I2C_ByteWrite(LSM_M_I2C_ADDRESS, &CRTLA, LSM_M_CRA_REG_ADDR); //CRTL_REGA
LSM303DLH_I2C_ByteWrite(LSM_M_I2C_ADDRESS, &CRTLB, LSM_M_CRB_REG_ADDR); //CRTL_REGB
LSM303DLH_I2C_ByteWrite(LSM_M_I2C_ADDRESS, &MODE, LSM_M_MR_REG_ADDR); //Mode register
}
#ifdef _MAG_DRDY
/**
* @brief Initializes the MAG_DRDY pin interrupt
* @param None
* @retval None
*/
void LSM303DLH_Magn_DRDY_Config(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable _MAG_DRDY pad GPIO clocks */
RCC_APB2PeriphClockCmd(LSM_M_DRDY_RCC_Port, ENABLE);
/* Configure MAG_DRDY pin as input floating */
GPIO_InitStructure.GPIO_Pin = LSM_M_DRDY_Pin;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(LSM_M_DRDY_Port, &GPIO_InitStructure);
/* Connect MAG_DRDY_EXTI_Line to MAG_DRDY Pin */
GPIO_EXTILineConfig(LSM_M_DRDY_Port_Source, LSM_M_DRDY_Pin_Source);
/* Configure MAG_DRDY_EXTI_Line to generate an interrupt on MAG_DRDY_Edge edge */
EXTI_InitStructure.EXTI_Line = LSM_M_DRDY_EXTI_Line;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = LSM_M_DRDY_Edge;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
/* Enable the MAG_DRDY_EXTI_IRQCHANNEL Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = LSM_M_DRDY_EXTI_IRQCHANNEL;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = LSM_M_DRDY_Preemption_Priority;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = LSM_M_DRDY_Sub_Priority;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
#endif /*_MAG_DRDY*/
/**
* @brief Read LSM303DLH magnetic field output register
* @param out : buffer to store data
* @retval None
*/
void LSM303DLH_Magn_ReadOut(u8* out)
{
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, out, LSM_M_OUT_X_H_ADDR, 6);
}
/**
* @brief Read LSM303DLH output register, and calculate the magnetic field Magn[Ga]=(out_h*256+out_l)*1000/ SENSITIVITY
* @param out : buffer to store data
* @retval None
*/
void LSM303DLH_Magn_Read_Magn(s16* out)
{
int i = 0;
u8 buffer[6];
u8 crtlB;
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, &crtlB, LSM_M_CRB_REG_ADDR, 1);
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, buffer, LSM_M_OUT_X_H_ADDR, 6);
/** switch the sensitivity set in the CRTLB*/
switch(crtlB & 0xE0)
{
case 0x40:
for(i=0; i<2; i++)
out[i]=((s16)((u16)buffer[2*i] << 8) + buffer[2*i+1])*1000/LSM_Magn_Sensitivity_XY_1_3Ga;
out[2]=((s16)((u16)buffer[4] << 8) + buffer[5])*1000/LSM_Magn_Sensitivity_Z_1_3Ga;
break;
case 0x60:
for(i=0; i<2; i++)
out[i]=((s16)((u16)buffer[2*i] << 8) + buffer[2*i+1])*1000/LSM_Magn_Sensitivity_XY_1_9Ga;
out[2]=((s16)((u16)buffer[4] << 8) + buffer[5])*1000/LSM_Magn_Sensitivity_Z_1_9Ga;
break;
case 0x80:
for(i=0; i<2; i++)
out[i]=(s16)(((u16)buffer[2*i] << 8) + buffer[2*i+1])*1000/LSM_Magn_Sensitivity_XY_2_5Ga;
out[2]=((s16)((u16)buffer[4] << 8) + buffer[5])*1000/LSM_Magn_Sensitivity_Z_2_5Ga;
break;
case 0xA0:
for(i=0; i<2; i++)
out[i]=(s16)(((u16)buffer[2*i] << 8) + buffer[2*i+1])*1000/LSM_Magn_Sensitivity_XY_4Ga;
out[2]=((s16)((u16)buffer[4] << 8) + buffer[5])*1000/LSM_Magn_Sensitivity_Z_4Ga;
break;
case 0xB0:
for(i=0; i<2; i++)
out[i]=(s16)(((u16)buffer[2*i] << 8) + buffer[2*i+1])*1000/LSM_Magn_Sensitivity_XY_4_7Ga;
out[2]=((s16)((u16)buffer[4] << 8) + buffer[5])*1000/LSM_Magn_Sensitivity_Z_4_7Ga;
break;
case 0xC0:
for(i=0; i<2; i++)
out[i]=(s16)(((u16)buffer[2*i] << 8) + buffer[2*i+1])*1000/LSM_Magn_Sensitivity_XY_5_6Ga;
out[2]=((s16)((u16)buffer[4] << 8) + buffer[5])*1000/LSM_Magn_Sensitivity_Z_5_6Ga;
break;
case 0xE0:
for(i=0; i<2; i++)
out[i]=(s16)(((u16)buffer[2*i] << 8) + buffer[2*i+1])*1000/LSM_Magn_GAIN_8_1;
out[2]=((s16)((u16)buffer[4] << 8) + buffer[5])*1000/LSM_Magn_Sensitivity_Z_8_1Ga;
break;
}
}
/**
* @brief Read LSM303DLH magnetic field output register and compute the s16 value
* @param out : buffer to store data
* @retval None
*/
void LSM303DLH_Magn_Read_RawData(s16* out)
{
int i = 0;
u8 buffer[6];
LSM303DLH_I2C_BufferRead(LSM_M_I2C_ADDRESS, buffer, LSM_M_OUT_X_H_ADDR, 6);
for(i=0; i<3; i++)
out[i]=((s16)((u16)buffer[2*i] << 8) + buffer[2*i+1]);
}
/**
*@}
*/ /* end of group Magnetometer_Function */
/**
* @}
*/ /* end of group Magnetometer */
/**
*@}
*/ /* end of group LSM303DLH */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/LSM303DLH/src/LSM303DLH.c | C | oos | 18,845 |
/**
* @file utils.h
* @author ART Team IMS-Systems Lab
* @version V2.0.0
* @date 09/20/2010
* @brief Header for utils.c
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/** \def
* Define to prevent recursive inclusion
*/
#ifndef __UTILS_H
#define __UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* \include
* */
#include "stm32f10x_type.h"
/** \addtogroup Utils
* \{
*/
/** @enum TestStatus
*/
typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
/**\def
* Computes the absolute value of its argument \a x.
*/
#define abs(a) ((a)>0?(a):-(a))
/**\def
* Define the UID Address and a pointer to it.
*/
#define U_ID_Base_Register_Address (0x1FFFF7E8)
#define MCU_ID ((const unsigned char *)(U_ID_Base_Register_Address))
/** \addtogroup Utils_Function
* \{
*/
void prvFindFactors(u32 n, u16 *a, u16 *b);
void Delay(vu32 nCount);
void CopyBuffer(unsigned char* pBufferOrigin, unsigned char* pBufferDestination, u8 NBOfBytes);
void s16_to_u8_buffer(s16* refvalue, unsigned char* pBufferDestination);
void u16_to_u8_buffer(u16* refvalue, unsigned char* pBufferDestination);
void Fill_Buffer(u32 *pBuffer, u16 BufferLenght, u32 Offset);
TestStatus Buffercmp(u32* pBuffer1, u32* pBuffer2, u16 BufferLength);
TestStatus eBuffercmp(u32* pBuffer, u16 BufferLength);
void Float_To_Buffer(float t, u8* pBuffer);
void Buffer_To_Float(u8* pBuffer,float t);
/**
* \}
*/ /* end of group Utils_Function */
/**
* \}
*/ /* end of group Utils */
#endif /* __UTILS_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/utils/inc/utils.h | C | oos | 2,387 |
/**
* @file utils.c
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief This file includes some utility functions
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/**
* \include
*/
#include "utils.h"
/**
* \defgroup Utils
* \{
*/
/** \addtogroup Utils_Function
* \{
*/
/**
* \brief Compute two integer value a and b such that n = a * b. It used to
* setup the timer to generate an IRQ whit a specified frequency n.
* \param n : the specified frequency
* \param a : prescaler factor
* \param b : period factor
* \retval None
*/
void prvFindFactors(u32 n, u16 *a, u16 *b)
{
/** This function is copied from the ST STR7 library and is
* copyright STMicroelectronics. Reproduced with permission.
*/
u16 b0;
u16 a0;
long err, err_min=n;
*a = a0 = ((n-1)/0xffff) + 1;
*b = b0 = n / *a;
for (; *a < 0xffff-1; (*a)++)
{
*b = n / *a;
err = (long)*a * (long)*b - (long)n;
if (abs(err) > (*a / 2))
{
(*b)++;
err = (long)*a * (long)*b - (long)n;
}
if (abs(err) < abs(err_min))
{
err_min = err;
a0 = *a;
b0 = *b;
if (err == 0) break;
}
}
*a = a0;
*b = b0;
}
/**
* \brief Inserts a delay time
* \param nCount: specifies the delay time length
* \retval None
*/
void Delay(vu32 nCount)
{
for(; nCount != 0; nCount--);
}
/**
* \brief Copy one buffer to another
* \param pBufferOrigin
* \param pBufferDestination
* \param NBOfBytes : number of bytes to copy
* \retval None
*/
void CopyBuffer(unsigned char* pBufferOrigin, unsigned char* pBufferDestination, u8 NBOfBytes)
{
while(NBOfBytes!=0)
{
NBOfBytes--;
*pBufferDestination=*pBufferOrigin;
pBufferDestination++;
pBufferOrigin++;
}
}
/**
* \brief Put in a buffer as u8 an s16.
* \param refvalue : s16 recipient
* \param pBufferDestination : u8 buffer destination
* \retval None
*/
void s16_to_u8_buffer(s16* refvalue, unsigned char* pBufferDestination)
{
u16 tmp=0x00;
tmp = (u16)(*refvalue);
*pBufferDestination=(u8)(tmp>>8);
pBufferDestination++;
*pBufferDestination=(u8)tmp;
}
/**
* \brief Put in a buffer as u8 an u16.
* \param refvalue : u16 recipient
* \param pBufferDestination : u8 buffer destination
* \retval None
*/
void u16_to_u8_buffer(u16* refvalue, unsigned char* pBufferDestination)
{
u16 tmp=0x00;
tmp = (u16)(*refvalue);
*pBufferDestination=(u8)(tmp>>8);
pBufferDestination++;
*pBufferDestination=(u8)tmp;
}
/**
* \brief Compares two buffers
* \param pBuffer1 : buffers to be compared
* \param pBuffer2 : buffers to be compared
* \retval TestStatus : PASSED if pBuffer1 is identical to pBuffer2; or FAILED if pBuffer1 id differs from pBuffer2
*/
TestStatus Buffercmp(u32* pBuffer1, u32* pBuffer2, u16 BufferLength)
{
while (BufferLength--)
{
if (*pBuffer1 != *pBuffer2)
{
return FAILED;
}
pBuffer1++;
pBuffer2++;
}
return PASSED;
}
/**
* \brief Fills buffer with user predefined data
* \param pBuffer : pointer on the Buffer to fill
* \param BufferLenght : size of the buffer to fill
* \param Offset : first value to fill on the Buffer
* \retval None
*/
void Fill_Buffer(u32 *pBuffer, u16 BufferLenght, u32 Offset)
{
u16 index = 0;
/* Put in global buffer same values */
for (index = 0; index < BufferLenght; index++ )
{
pBuffer[index] = index + Offset;
}
}
/**
* \brief Checks if a buffer has all its values are equal to zero
* \param pBuffer : buffer to be compared.
* \param BufferLenght : buffer's length
* \retval TestStatus : PASSED pBuffer values are zero
* FAILED At least one value from pBuffer buffer is diffrent
* from zero.
*/
TestStatus eBuffercmp(u32* pBuffer, u16 BufferLength)
{
while (BufferLength--)
{
if (*pBuffer != 0x00)
{
return FAILED;
}
pBuffer++;
}
return PASSED;
}
/**
* brief: Copy the four byte of a float, into a buffer starting from a position
* @param pBuffer
* @param t : the float to copy into the buffer
* @retval None
*/
void Float_To_Buffer(float t, u8* pBuffer)
{
char* s;
int i = 0;
s=(char*)(&t);
for(i=3;i>=0;i--)
{
pBuffer[i]=(char) (*s);
s++;
}
}
/**
* brief: Copy four byte of a buffer into a float.
* @param t : the float to copy into the buffer
* @param pBuffer
* @retval None
*/
void Buffer_To_Float(u8* pBuffer, float t)
{
char* s;
int i = 0;
s=(char*)(&t);
for(i=0;i<4;i++)
{
*s=pBuffer[i];
s++;
}
}
/**
* }
*/ /* end of group Utils_Function */
/**
* @}
*/ /* end of group Utils */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/utils/src/utils.c | C | oos | 5,662 |
/**
* @file HAL_LPRYxxxAL.h
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief Hardware Abstraction Layer for LPYRxxxAL gyroscope of iNEMO_v2.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion */
#ifndef __HAL_LPRYxxxAL_H
#define __HAL_LPRYxxxAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
//#include "stm32f10x.h"
//#include "iNEMO_conf.h"
/**
* @addtogroup LPR430AL_LY330ALH
* @{
*/
/** @defgroup Gyro_ADC_Define
* @{
*/
#define GYRO_ADC ADC1
#define GYRO_RCC_Periph_ADC RCC_APB2Periph_ADC1
#define GYRO_ADC_Port GPIOC
#define GYRO_ADC_DR_Address ((u32)0x4001244C)
#define GYRO_RCC_Port RCC_APB2Periph_GPIOC
/**
* @}
*/ /* end of group Gyro_ADC_Define */
/** @defgroup Gyro_DMA_Define
*@{
*/
#define GYRO_DMA DMA1
#define GYRO_RCC_Periph_DMA RCC_AHBPeriph_DMA1
#define GYRO_DMA_Channel DMA_Channel1
#define GYRO_DMA_IRQChannel DMA1_Channel1_IRQChannel
#define GYRO_DMA_FLAG DMA_FLAG_TC1
/**
*@}
*/ /* end of group Gyro_DMA_Define */
/** @defgroup Gyro_GPIO_Define
*@{
*/
#define GYRO_GPIO_Port2 GPIOB /*!< GPIO for ST and PD/SLEEP pin*/
#define GYRO_GPIO_RCC_Port2 RCC_APB2Periph_GPIOB
#define GYRO_LY_PinZ GPIO_Pin_4
#define GYRO_LY_PinREF GPIO_Pin_5
#define GYRO_LY_PinST GPIO_Pin_14 /*!< GPIO port B*/
#define GYRO_LY_PinPD GPIO_Pin_15 /*!< GPIO port B*/
#define GYRO_LPR_PinY GPIO_Pin_1
#define GYRO_LPR_PinX GPIO_Pin_0
#define GYRO_LPR_PinREF GPIO_Pin_2
#define GYRO_LPR_PinST GPIO_Pin_1 /*!< GPIO port B*/
#define GYRO_LPR_PinPD GPIO_Pin_5 /*!< GPIO port B*/
#define GYRO_LY_ACD_ChZ ADC_Channel_14
#define GYRO_LY_ACD_ChREF ADC_Channel_15
#define GYRO_LPR_ACD_ChY ADC_Channel_11
#define GYRO_LPR_ACD_ChX ADC_Channel_10
#define GYRO_LPR_ACD_ChREF ADC_Channel_12
/**
*@}
*/ /* end of group Gyro_GPIO_Define */
/**
* @}
*/ /* end of group LPR430AL_LY330ALH */
#endif /*__HAL_LPRYxxxAL_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/LPRYxxxAL/inc/HAL_LPRYxxxAL.h | C | oos | 3,117 |
/**
* @file LPRYxxxAL.h
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief Header for LPRYxxxAL.c file of iNEMO_v2
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/** Define to prevent recursive inclusion */
#ifndef __LPRYxxxAL_H
#define __LPRYxxx0AL_H
#ifdef __cplusplus
extern "C" {
#endif
/** Includes*/
#include "stm32f10x_type.h"
#include "HAL_LPRYxxxAL.h"
/**
* @defgroup LPR430AL_LY330ALH
* @{
*/
/** @defgroup Gyro_Sensitivity_Define
* @{
*/
#define Gyro_Sensitivity_Y_300dps 3.752 /*!< Yaw axis Sensitivity [ mV/dps ] see LY330ALH datasheet */
#define Gyro_SensitivityLSB_Y_300dps 4.62 /*!< Yaw axis Sensitivity [ LSB/dps] */
#define Gyro_Sensitivity_P_300dps 3.33 /*!<300dps Full Scale Pitch axis Sensitivity [ mV/dps ]see LPR430AL datasheet*/
#define Gyro_SensitivityLSB_P_300dps 4.13 /*!<300dps Full Scale Pitch axis Sensitivity [ LSB/dps ]*/
#define Gyro_Sensitivity_R_300dps 3.33 /*!< 300dps Full Scale Roll axis Sensitivity [ mV/dps ]see LPR430AL datasheet*/
#define Gyro_SensitivityLSB_R_300dps 4.13 /*!< 300dps Full Scale Roll axis Sensitivity [ LSB/dps ]*/
#define Gyro_Sensitivity_R_1200dps 0.83 /*!< 1200 dps full scale Roll axis Sensitivity [ mV/dps ]see LPR430AL datasheet*/
#define Gyro_SensitivityLSB_R_1200dps 1.03 /*!< 1200dps full scale Roll axis Sensitivity [ LSB/dps ]*/
#define Gyro_Sensitivity_P_1200dps 0.83 /*!< 1200 dps full scale Pitch axis Sensitivity [ mV/dps ]see LPR430AL datasheet*/
#define Gyro_SensitivityLSB_P_1200dps 1.03 /*!< 1200 dps full scale Pitch axis Sensitivity [ LSB/dps ]*/
#define BufferSize 5
#define AxisNumber 3
/**
*@}
*/ /* end of group Gyro_Sensitivity_Define */
/** @defgroup Gyro_Functions
* @{
*/
void LPRYxxxAL_ADC_Init(void);
void LPRYxxxAL_DMA_Init(void);
void LPRYxxxAL_PD_ST_Init(void);
void LPRYxxxAL_On(void);
void LPRYxxxAL_Off(void);
void LPRYxxxAL_ST_On(void);
void LPRYxxxAL_ST_Off(void);
void LPRYxxxAL_Read(u16* out);
void LPRYxxxAL_Read_Rate(s16* out);
void LPRYxxxAL_Read_RawRate(s16* out);
/**
* @}
*/ /* end of group Gyro_Functions */
/**
* @}
*/ /* end of group LPR430AL_LY330ALH */
#endif /* __LPRYxxxAL_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/LPRYxxxAL/inc/LPRYxxxAL.h | C | oos | 3,151 |
/**
* @file LPRYxxxAL.c
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief This file provides a set of functions to manage the communication
* between STM32 ADC and LPRYxxxAL analog output using DMA.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
#include "LPRYxxxAL.h"
#include "iNEMO_conf.h"
#include "stm32f10x_adc.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
/**
* @addtogroup LPR430AL_LY330ALH
* @{
*/
/**Buffer to store ADC value*/
u16 ADC_ConvertedValue[BufferSize];
/** @defgroup Gyro_Functions
* @{
*/
/**
* @brief Initializes the ADC peripheral used to drive the LPRYxxxAL
* @param None
* @retval None
*/
void LPRYxxxAL_ADC_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
ADC_InitTypeDef ADC_InitStructure;
/** IMPORTANT :check in Set_System() in main.c if ADCCLK is configured --> (es.) RCC_ADCCLKConfig(RCC_PCLK2_Div6)*/
/* GPIO configuration*/
RCC_APB2PeriphClockCmd( GYRO_RCC_Port | GYRO_RCC_Periph_ADC, ENABLE);
GPIO_InitStructure.GPIO_Pin = GYRO_LPR_PinY | GYRO_LPR_PinX | GYRO_LPR_PinREF | GYRO_LY_PinZ |GYRO_LY_PinREF;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
GPIO_Init(GYRO_ADC_Port, &GPIO_InitStructure);
/* GYRO_ADC configuration*/
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = ENABLE;
ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel =5;
/* GYRO_ADC regular channel configuration */
ADC_RegularChannelConfig(GYRO_ADC, GYRO_LPR_ACD_ChX, 1, ADC_SampleTime_239Cycles5);
ADC_RegularChannelConfig(GYRO_ADC, GYRO_LPR_ACD_ChY, 2,ADC_SampleTime_239Cycles5);
ADC_RegularChannelConfig(GYRO_ADC, GYRO_LPR_ACD_ChREF, 3,ADC_SampleTime_239Cycles5);
ADC_RegularChannelConfig(GYRO_ADC, GYRO_LY_ACD_ChZ, 4, ADC_SampleTime_239Cycles5);
ADC_RegularChannelConfig(GYRO_ADC, GYRO_LY_ACD_ChREF, 5,ADC_SampleTime_239Cycles5);
ADC_Init(GYRO_ADC, &ADC_InitStructure);
/* Enable GYRO_ADC */
ADC_Cmd(GYRO_ADC, ENABLE);
/* Enable GYRO_ADC reset calibration register */
ADC_ResetCalibration(GYRO_ADC);
/* Check the end of GYRO_ADC reset calibration register */
while(ADC_GetResetCalibrationStatus(GYRO_ADC));
/* Start GYRO_ADC calibration */
ADC_StartCalibration(GYRO_ADC);
/* Check the end of GYRO_ADC calibration */
while(ADC_GetCalibrationStatus(GYRO_ADC));
}
/**
* @brief Initializes the DMA peripheral used to drive the LPRYxxxAL
* @param NONE
* @retval NONE
*/
void LPRYxxxAL_DMA_Init()
{
DMA_InitTypeDef DMA_InitStructure;
RCC_AHBPeriphClockCmd(GYRO_RCC_Periph_DMA, ENABLE);
DMA_DeInit(GYRO_DMA_Channel);
DMA_InitStructure.DMA_PeripheralBaseAddr =(u32)GYRO_ADC_DR_Address;
DMA_InitStructure.DMA_MemoryBaseAddr = (u32)ADC_ConvertedValue;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_BufferSize = BufferSize;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(GYRO_DMA_Channel, &DMA_InitStructure);
}
/**
* @brief Initializes the PD(Power Down) ans ST(Self Test) GPIO pins
* @param None
* @retval None
*/
void LPRYxxxAL_PD_ST_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable GPIO clocks */
RCC_APB2PeriphClockCmd(GYRO_GPIO_RCC_Port2, ENABLE);
/* Configure Pins */
GPIO_InitStructure.GPIO_Pin = GYRO_LY_PinST | GYRO_LY_PinPD | GYRO_LPR_PinST |GYRO_LY_PinPD ;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GYRO_GPIO_Port2, &GPIO_InitStructure);
}
/**
* @brief Reset the two PD pins to turn on the two Gyros
* @param None
* @retval None
*/
void LPRYxxxAL_On(void)
{
GPIO_ResetBits(GYRO_GPIO_Port2, GYRO_LY_PinPD);
GPIO_ResetBits(GYRO_GPIO_Port2, GYRO_LPR_PinPD);
}
/**
* @brief Set the two PD pins to turn off the two Gyros
* @param None
* @retval None
*/
void LPRYxxxAL_Off(void)
{
GPIO_SetBits(GYRO_GPIO_Port2, GYRO_LY_PinPD);
GPIO_SetBits(GYRO_GPIO_Port2, GYRO_LPR_PinPD) ;
}
/**
* @brief Set the two PD pins to turn on the Self test funtion of two Gyros
* @param None
* @retval None
*/
void LPRYxxxAL_ST_On(void)
{
GPIO_SetBits(GYRO_GPIO_Port2, GYRO_LY_PinST);
GPIO_SetBits(GYRO_GPIO_Port2, GYRO_LPR_PinST);
}
/**
* @brief Reset the two PD pins to turn off the Self test funtion of two Gyros
* @param None
* @retval None
*/
void LPRYxxxAL_ST_Off(void)
{
GPIO_ResetBits(GYRO_GPIO_Port2, GYRO_LY_PinST);
GPIO_ResetBits(GYRO_GPIO_Port2, GYRO_LPR_PinST);
}
/**
* @brief Read the LPRYxxxAL output
* @param out : u16 buffer to store data
* @retval None
*/
void LPRYxxxAL_Read(u16* out)
{
int i = 0;
iNEMO_ENTER_CRITICAL();
/* Enable GYRO_ADC DMA */
ADC_DMACmd(GYRO_ADC, ENABLE);
ADC_Cmd(GYRO_ADC, ENABLE);
DMA_Cmd(GYRO_DMA_Channel, ENABLE);
ADC_SoftwareStartConvCmd(GYRO_ADC, ENABLE);
while(!(DMA_GetFlagStatus(GYRO_DMA_FLAG)));
ADC_Cmd(GYRO_ADC, DISABLE);
ADC_SoftwareStartConvCmd(GYRO_ADC, DISABLE);
DMA_ClearFlag(GYRO_DMA_FLAG);
for(i=0; i< BufferSize; i++)
{
*out=ADC_ConvertedValue[i];
out++;
}
iNEMO_EXIT_CRITICAL();
}
/**
* @brief Read LPRYxxxAL output, and calculate the angular rate for each axis Rate=(output_axis-output_reference)/Gyro_SensitivityLSB
* angular rates are positive in counterclockwise direction
* @param out : s16 data buffer
* @retval None
*/
void LPRYxxxAL_Read_Rate(s16* out)
{
u16 outADC[BufferSize];
LPRYxxxAL_Read(outADC);
out[0]=(s16)((outADC[0]-outADC[2])/Gyro_SensitivityLSB_R_300dps);
out[1]=(s16)((outADC[1]-outADC[2])/Gyro_SensitivityLSB_P_300dps);
out[2]=(s16)((outADC[3]-outADC[4])/Gyro_SensitivityLSB_Y_300dps);
}
/**
* @brief Read LPRYxxxAL output, and calculate the angular rate for each axis Rate[LSB]=(output_axis-output_reference)
* angular rates are positive in counterclockwise direction
* @param out : s16 data buffer
* @retval None
*/
void LPRYxxxAL_Read_RawRate(s16* out)
{
u16 outADC[BufferSize];
LPRYxxxAL_Read(outADC);
out[0]=(s16)(outADC[0]-outADC[2]);
out[1]=-(s16)(outADC[1]-outADC[2]);
out[2]=(s16)(outADC[3]-outADC[4]);
}
/**
* @}
*/ /* end of group Gyro_Functions */
/**
* @}
*/ /* end of group LPR430AL_LY330ALH */
/* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/LPRYxxxAL/src/LPRYxxxAL.c | C | oos | 7,798 |
/**
* @file HAL_STLM75.h
* @author ART Team IMS-Systems Lab
* @version V2.2
* @date 01/11/2011
* @brief Hardware Abstraction Layer for STLM75.
* @details
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* THIS SOURCE CODE IS PROTECTED BY A LICENSE.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion*/
#ifndef __HAL_STLM75_H
#define __HAL_STLM75_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
//#include "stm32f10x.h"
//#include "iNEMO_conf.h"
/**
* @defgroup STLM75
* @{
*/
/**
* @defgroup STLM75_I2C_Define
* @{
*/
#define TEMP_I2C I2C2
#define TEMP_RCC_Periph_I2C RCC_APB1Periph_I2C2
#define TEMP_I2C_Port GPIOB
#define TEMP_I2C_SCL_Pin GPIO_Pin_10
#define TEMP_I2C_SDA_Pin GPIO_Pin_11
#define TEMP_RCC_Port_I2C RCC_APB2Periph_GPIOB
#define TEMP_I2C_Speed 100000
/**
*@}
*/ /* end of group STLM75_I2C_Define */
/**
* @defgroup STLM75_Interrupt_Pin_Define
* @{
*/
#ifdef OS_INT_ENABLE
#define STLM75_INT_Port GPIOB
#define STLM75_INT_RCC RCC_APB2Periph_GPIOB
#define STLM75_INT_Pin GPIO_Pin_1
#define STLM75_INT_Port_Source GPIO_PortSourceGPIOB
#define STLM75_INT_Pin_Source GPIO_PinSource1
#define STLM75_INT_EXTI_Line EXTI_Line1
#define STLM75_INT_Edge EXTI_Trigger_Falling
#define STLM75_INT_EXTI_IRQCHANNEL EXTI1_IRQn
#define STLM75_INT_Preemption_Priority 12
#define STLM75_INT_Sub_Priority 0
#endif //OS_INT_ENABLE
/**
*@}
*/ /* end of group STLM75_Interrupt_Pin_Define */
/**
*@}
*/ /* end of group STLM75 */
#endif /* __HAL_STLM75_H */
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/Sensors/STLM75/inc/HAL_STLM75.h | C | oos | 2,570 |
/*
* Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com
* MAX3421E USB host controller support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the authors nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "FreeRTOS.h"
#include "stm32f10x_lib.h"
#include "stm32_types_compat.h"
#include "Max3421e_constants.h"
/* Public methods */
void max3421e(void); //constructor
void max3421eRegWr(u8 reg, u8 val);
u8 max3421eRegRd(u8 reg);
char* max3421eBytesWr(u8 reg, u8 nbytes, char* data); // TO BE TESTED!
char* max3421eBytesRd(u8 reg, u8 nbytes, char* data); // TO BE TESTED!
void max3421ePowerOn(void);
u8 max3421eReset(void);
u8 max3421eTask(void);
/* Prvivate methods (as from Max3421e.cpp Arduino code) */
void spi_init(void);
void pinInit(void);
void busprobe(void);
u8 getVbusState(void);
u8 IntHandler(void);
u8 GpxHandler(void);
u8 GpxHandler(void);
u8 readINT(void);
u8 readGPX(void);
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/USB_Host_Shield/Max3421e.h | C | oos | 2,344 |
/*
* Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com
* MAX3421E USB host controller support
*
* Ported to STM32 by David Siorpaes
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the authors nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* USB functions */
#ifndef _usb_h_
#define _usb_h_
#include <Max3421e.h>
#include "ch9.h"
#include "stm32_types_compat.h"
/* Common setup data constant combinations */
#define bmREQ_GET_DESCR USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_DEVICE //get descriptor request type
#define bmREQ_SET USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_DEVICE //set request type for all but 'set feature' and 'set interface'
#define bmREQ_CL_GET_INTF USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE //get interface request type
/* HID requests */
#define bmREQ_HIDOUT USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
#define bmREQ_HIDIN USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
#define bmREQ_HIDREPORT USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_INTERFACE
#define USB_XFER_TIMEOUT 5000 //USB transfer timeout in milliseconds, per section 9.2.6.1 of USB 2.0 spec
#define USB_NAK_LIMIT 32000 //NAK limit for a transfer. o meand NAKs are not counted
#define USB_RETRY_LIMIT 3 //retry limit for a transfer
#define USB_SETTLE_DELAY 200 //settle delay in milliseconds
#define USB_NAK_NOWAIT 1 //used in Richard's PS2/Wiimote code
#define USB_NUMDEVICES 2 //number of USB devices
/* USB state machine states */
#define USB_STATE_MASK 0xf0
#define USB_STATE_DETACHED 0x10
#define USB_DETACHED_SUBSTATE_INITIALIZE 0x11
#define USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE 0x12
#define USB_DETACHED_SUBSTATE_ILLEGAL 0x13
#define USB_ATTACHED_SUBSTATE_SETTLE 0x20
#define USB_ATTACHED_SUBSTATE_RESET_DEVICE 0x30
#define USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE 0x40
#define USB_ATTACHED_SUBSTATE_WAIT_SOF 0x50
#define USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE 0x60
#define USB_STATE_ADDRESSING 0x70
#define USB_STATE_CONFIGURING 0x80
#define USB_STATE_RUNNING 0x90
#define USB_STATE_ERROR 0xa0
// byte usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE
/* USB Setup Packet Structure */
typedef struct {
union { // offset description
byte bmRequestType; // 0 Bit-map of request type
struct {
byte recipient: 5; // Recipient of the request
byte type: 2; // Type of request
byte direction: 1; // Direction of data X-fer
}dummy;
}ReqType_u;
byte bRequest; // 1 Request
union {
u16 wValue; // 2 Depends on bRequest
struct {
byte wValueLo;
byte wValueHi;
}dummy;
}wVal_u;
u16 wIndex; // 4 Depends on bRequest
u16 wLength; // 6 Depends on bRequest
} SETUP_PKT, *PSETUP_PKT;
/* Endpoint information structure */
/* bToggle of endpoint 0 initialized to 0xff */
/* during enumeration bToggle is set to 00 */
typedef struct {
byte epAddr; //copy from endpoint descriptor. Bit 7 indicates direction ( ignored for control endpoints )
byte Attr; // Endpoint transfer type.
u16 MaxPktSize; // Maximum packet size.
byte Interval; // Polling interval in frames.
byte sndToggle; //last toggle value, bitmask for HCTL toggle bits
byte rcvToggle; //last toggle value, bitmask for HCTL toggle bits
/* not sure if both are necessary */
} EP_RECORD;
/* device record structure */
typedef struct {
EP_RECORD* epinfo; //device endpoint information
byte devclass; //device class
} DEV_RECORD;
//class USB : public MAX3421E {
//data structures
/* device table. Filled during enumeration */
/* index corresponds to device address */
/* each entry contains pointer to endpoint structure */
/* and device class to use in various places */
//DEV_RECORD devtable[ USB_NUMDEVICES + 1 ];
//EP_RECORD dev0ep; //Endpoint data structure used during enumeration for uninitialized device
//byte usb_task_state;
void usbUSB( void );
byte usbGetUsbTaskState( void );
void usbSetUsbTaskState( byte state );
EP_RECORD* usbGetDevTableEntry( byte addr, byte ep );
void usbSetDevTableEntry( byte addr, EP_RECORD* eprecord_ptr );
byte usbCtrlReq( byte addr, byte ep, byte bmReqType, byte bRequest, byte wValLo, byte wValHi, u16 wInd, u16 nbytes, char* dataptr, unsigned int nak_limit );
/* Control requests */
byte usbGetDevDescr( byte addr, byte ep, u16 nbytes, char* dataptr);
byte usbGetConfDescr( byte addr, byte ep, u16 nbytes, byte conf, char* dataptr);
byte usbGetStrDescr( byte addr, byte ep, u16 nbytes, byte index, u16 langid, char* dataptr);
byte usbSetAddr( byte oldaddr, byte ep, byte newaddr);
byte usbSetConf( byte addr, byte ep, byte conf_value);
/**/
byte usbSetProto( byte addr, byte ep, byte interface, byte protocol);
byte usbGetProto( byte addr, byte ep, byte interface, char* dataptr);
byte usbGetReportDescr( byte addr, byte ep, u16 nbytes, char* dataptr);
byte usbSetReport( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr);
byte usbGetReport( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr);
byte usbGetIdle( byte addr, byte ep, byte interface, byte reportID, char* dataptr);
byte usbSetIdle( byte addr, byte ep, byte interface, byte reportID, byte duration);
/**/
byte usbCtrlData( byte addr, byte ep, u16 nbytes, char* dataptr, boolean direction, unsigned int nak_limit );
byte usbCtrlStatus( byte ep, boolean direction, unsigned int nak_limit );
byte usbInTransfer( byte addr, byte ep, u16 nbytes, char* data, unsigned int nak_limit );
int usbNewInTransfer( byte addr, byte ep, u16 nbytes, char* data, unsigned int nak_limit );
byte usbOutTransfer( byte addr, byte ep, u16 nbytes, char* data, unsigned int nak_limit );
byte usbDispatchPkt( byte token, byte ep, unsigned int nak_limit );
void usbTask( void );
/* Provate methods */
void usbInit(void);
byte usbCtrlReq_NAK_LIMIT( byte addr, byte ep, byte bmReqType, byte bRequest, byte wValLo, byte wValHi, u16 wInd, u16 nbytes, char* dataptr);
/*
byte usbGetDevDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* dataptr);
byte usbGetConfDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte conf, char* dataptr);
byte usbGetStrDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte index, u16 langid);
byte usbSetAddr_NAK_LIMIT( byte oldaddr, byte ep, byte newaddr);
byte usbSetConf_NAK_LIMIT( byte addr, byte ep, byte conf_value);
byte usbSetProto_NAK_LIMIT( byte addr, byte ep, byte interface, byte protocol);
byte usbGetProto_NAK_LIMIT( byte addr, byte ep, byte interface, char* dataptr);
byte usbGetReportDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* dataptr);
byte usbSetReport_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr);
byte usbGetReport_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr);
byte usbGetIdle_NAK_LIMIT( byte addr, byte ep, byte interface, byte reportID, char* dataptr);
byte usbSetIdle_NAK_LIMIT( byte addr, byte ep, byte interface, byte reportID, byte duration);
*/
byte usbCtrlData_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* dataptr, boolean direction);
byte usbCtrlStatus_NAK_LIMIT( byte ep, boolean direction);
byte usbInTransfer_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* data);
int usbNewInTransfer_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* data);
byte usbOutTransfer_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* data);
byte usbDispatchPkt_NAK_LIMIT( byte token, byte ep);
/* Inline methods below have bee moved to .c file since simpols clashed upon inclusion */
/* */
#endif //_usb_h_
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/USB_Host_Shield/Usb.h | C | oos | 10,142 |
/*
* Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com
* MAX3421E USB host controller support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the authors nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* USB chapter 9 structures */
#ifndef _ch9_h_
#define _ch9_h_
#include "stm32_types_compat.h"
/* Misc.USB constants */
#define DEV_DESCR_LEN 18 //device descriptor length
#define CONF_DESCR_LEN 9 //configuration descriptor length
#define INTR_DESCR_LEN 9 //interface descriptor length
#define EP_DESCR_LEN 7 //endpoint descriptor length
/* Standard Device Requests */
#define USB_REQUEST_GET_STATUS 0 // Standard Device Request - GET STATUS
#define USB_REQUEST_CLEAR_FEATURE 1 // Standard Device Request - CLEAR FEATURE
#define USB_REQUEST_SET_FEATURE 3 // Standard Device Request - SET FEATURE
#define USB_REQUEST_SET_ADDRESS 5 // Standard Device Request - SET ADDRESS
#define USB_REQUEST_GET_DESCRIPTOR 6 // Standard Device Request - GET DESCRIPTOR
#define USB_REQUEST_SET_DESCRIPTOR 7 // Standard Device Request - SET DESCRIPTOR
#define USB_REQUEST_GET_CONFIGURATION 8 // Standard Device Request - GET CONFIGURATION
#define USB_REQUEST_SET_CONFIGURATION 9 // Standard Device Request - SET CONFIGURATION
#define USB_REQUEST_GET_INTERFACE 10 // Standard Device Request - GET INTERFACE
#define USB_REQUEST_SET_INTERFACE 11 // Standard Device Request - SET INTERFACE
#define USB_REQUEST_SYNCH_FRAME 12 // Standard Device Request - SYNCH FRAME
#define USB_FEATURE_ENDPOINT_HALT 0 // CLEAR/SET FEATURE - Endpoint Halt
#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1 // CLEAR/SET FEATURE - Device remote wake-up
#define USB_FEATURE_TEST_MODE 2 // CLEAR/SET FEATURE - Test mode
/* Setup Data Constants */
#define USB_SETUP_HOST_TO_DEVICE 0x00 // Device Request bmRequestType transfer direction - host to device transfer
#define USB_SETUP_DEVICE_TO_HOST 0x80 // Device Request bmRequestType transfer direction - device to host transfer
#define USB_SETUP_TYPE_STANDARD 0x00 // Device Request bmRequestType type - standard
#define USB_SETUP_TYPE_CLASS 0x20 // Device Request bmRequestType type - class
#define USB_SETUP_TYPE_VENDOR 0x40 // Device Request bmRequestType type - vendor
#define USB_SETUP_RECIPIENT_DEVICE 0x00 // Device Request bmRequestType recipient - device
#define USB_SETUP_RECIPIENT_INTERFACE 0x01 // Device Request bmRequestType recipient - interface
#define USB_SETUP_RECIPIENT_ENDPOINT 0x02 // Device Request bmRequestType recipient - endpoint
#define USB_SETUP_RECIPIENT_OTHER 0x03 // Device Request bmRequestType recipient - other
/* USB descriptors */
#define USB_DESCRIPTOR_DEVICE 0x01 // bDescriptorType for a Device Descriptor.
#define USB_DESCRIPTOR_CONFIGURATION 0x02 // bDescriptorType for a Configuration Descriptor.
#define USB_DESCRIPTOR_STRING 0x03 // bDescriptorType for a String Descriptor.
#define USB_DESCRIPTOR_INTERFACE 0x04 // bDescriptorType for an Interface Descriptor.
#define USB_DESCRIPTOR_ENDPOINT 0x05 // bDescriptorType for an Endpoint Descriptor.
#define USB_DESCRIPTOR_DEVICE_QUALIFIER 0x06 // bDescriptorType for a Device Qualifier.
#define USB_DESCRIPTOR_OTHER_SPEED 0x07 // bDescriptorType for a Other Speed Configuration.
#define USB_DESCRIPTOR_INTERFACE_POWER 0x08 // bDescriptorType for Interface Power.
#define USB_DESCRIPTOR_OTG 0x09 // bDescriptorType for an OTG Descriptor.
/* OTG SET FEATURE Constants */
#define OTG_FEATURE_B_HNP_ENABLE 3 // SET FEATURE OTG - Enable B device to perform HNP
#define OTG_FEATURE_A_HNP_SUPPORT 4 // SET FEATURE OTG - A device supports HNP
#define OTG_FEATURE_A_ALT_HNP_SUPPORT 5 // SET FEATURE OTG - Another port on the A device supports HNP
/* USB Endpoint Transfer Types */
#define USB_TRANSFER_TYPE_CONTROL 0x00 // Endpoint is a control endpoint.
#define USB_TRANSFER_TYPE_ISOCHRONOUS 0x01 // Endpoint is an isochronous endpoint.
#define USB_TRANSFER_TYPE_BULK 0x02 // Endpoint is a bulk endpoint.
#define USB_TRANSFER_TYPE_INTERRUPT 0x03 // Endpoint is an interrupt endpoint.
#define bmUSB_TRANSFER_TYPE 0x03 // bit mask to separate transfer type from ISO attributes
/* Standard Feature Selectors for CLEAR_FEATURE Requests */
#define USB_FEATURE_ENDPOINT_STALL 0 // Endpoint recipient
#define USB_FEATURE_DEVICE_REMOTE_WAKEUP 1 // Device recipient
#define USB_FEATURE_TEST_MODE 2 // Device recipient
/* HID constants. Not part of chapter 9 */
/* Class-Specific Requests */
#define HID_REQUEST_GET_REPORT 0x01
#define HID_REQUEST_GET_IDLE 0x02
#define HID_REQUEST_GET_PROTOCOL 0x03
#define HID_REQUEST_SET_REPORT 0x09
#define HID_REQUEST_SET_IDLE 0x0A
#define HID_REQUEST_SET_PROTOCOL 0x0B
/* Class Descriptor Types */
#define HID_DESCRIPTOR_HID 0x21
#define HID_DESCRIPTOR_REPORT 0x22
#define HID_DESRIPTOR_PHY 0x23
/* Protocol Selection */
#define BOOT_PROTOCOL 0x00
#define RPT_PROTOCOL 0x01
/* HID Interface Class Code */
#define HID_INTF 0x03
/* HID Interface Class SubClass Codes */
#define BOOT_INTF_SUBCLASS 0x01
/* HID Interface Class Protocol Codes */
#define HID_PROTOCOL_NONE 0x00
#define HID_PROTOCOL_KEYBOARD 0x01
#define HID_PROTOCOL_MOUSE 0x02
/* descriptor data structures */
/* Device descriptor structure */
typedef struct{
byte bLength; // Length of this descriptor.
byte bDescriptorType; // DEVICE descriptor type (USB_DESCRIPTOR_DEVICE).
u16 bcdUSB; // USB Spec Release Number (BCD).
byte bDeviceClass; // Class code (assigned by the USB-IF). 0xFF-Vendor specific.
byte bDeviceSubClass; // Subclass code (assigned by the USB-IF).
byte bDeviceProtocol; // Protocol code (assigned by the USB-IF). 0xFF-Vendor specific.
byte bMaxPacketSize0; // Maximum packet size for endpoint 0.
u16 idVendor; // Vendor ID (assigned by the USB-IF).
u16 idProduct; // Product ID (assigned by the manufacturer).
u16 bcdDevice; // Device release number (BCD).
byte iManufacturer; // Index of String Descriptor describing the manufacturer.
byte iProduct; // Index of String Descriptor describing the product.
byte iSerialNumber; // Index of String Descriptor with the device's serial number.
byte bNumConfigurations; // Number of possible configurations.
} USB_DEVICE_DESCRIPTOR;
/* Configuration descriptor structure */
typedef struct
{
byte bLength; // Length of this descriptor.
byte bDescriptorType; // CONFIGURATION descriptor type (USB_DESCRIPTOR_CONFIGURATION).
u16 wTotalLength; // Total length of all descriptors for this configuration.
byte bNumInterfaces; // Number of interfaces in this configuration.
byte bConfigurationValue; // Value of this configuration (1 based).
byte iConfiguration; // Index of String Descriptor describing the configuration.
byte bmAttributes; // Configuration characteristics.
byte bMaxPower; // Maximum power consumed by this configuration.
} USB_CONFIGURATION_DESCRIPTOR;
/* Interface descriptor structure */
typedef struct
{
byte bLength; // Length of this descriptor.
byte bDescriptorType; // INTERFACE descriptor type (USB_DESCRIPTOR_INTERFACE).
byte bInterfaceNumber; // Number of this interface (0 based).
byte bAlternateSetting; // Value of this alternate interface setting.
byte bNumEndpoints; // Number of endpoints in this interface.
byte bInterfaceClass; // Class code (assigned by the USB-IF). 0xFF-Vendor specific.
byte bInterfaceSubClass; // Subclass code (assigned by the USB-IF).
byte bInterfaceProtocol; // Protocol code (assigned by the USB-IF). 0xFF-Vendor specific.
byte iInterface; // Index of String Descriptor describing the interface.
} USB_INTERFACE_DESCRIPTOR;
/* Endpoint descriptor structure */
typedef struct
{
byte bLength; // Length of this descriptor.
byte bDescriptorType; // ENDPOINT descriptor type (USB_DESCRIPTOR_ENDPOINT).
byte bEndpointAddress; // Endpoint address. Bit 7 indicates direction (0=OUT, 1=IN).
byte bmAttributes; // Endpoint transfer type.
u16 wMaxPacketSize; // Maximum packet size.
byte bInterval; // Polling interval in frames.
} USB_ENDPOINT_DESCRIPTOR;
/* HID descriptor */
typedef struct {
byte bLength;
byte bDescriptorType;
u16 bcdHID;
byte bCountryCode;
byte bNumDescriptors;
byte bDescrType;
u16 wDescriptorLength;
} USB_HID_DESCRIPTOR;
#endif // _ch9_h_
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/USB_Host_Shield/ch9.h | C | oos | 11,067 |
/*
* Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com
* MAX3421E USB host controller support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the authors nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/** USB shield support library. Ported from Google code base "ADK_release_0512"
*
* Public methods are preceded with "max3421e" prefix.
* Private methods signatures are left unchanged
*/
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "serial.h"
/* Library includes. */
#include "stm32f10x_it.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_spi.h"
#include "Max3421e.h"
#include "Max3421e_constants.h"
#include "iNEMO_util.h"
#include "stm32_types_compat.h"
static u8 vbusState;
/*
* Public methods
*/
void max3421e(void)
{
pinInit();
spi_init();
}
void max3421eRegWr(u8 reg, u8 val)
{
/* Slave select low
* The software SS SPI_SSOutputCmd(SPI1, ENABLE);
* is not working properly, relying on GPIO instead */
GPIO_WriteBit(GPIOC, GPIO_Pin_3, Bit_RESET);
/* Send command: since we are writing set command bit accordingly */
reg |= 0x02;
SPI_SendData(SPI1, reg);
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET){}
/* Dummy read */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE)== RESET){}
SPI_ReceiveData(SPI1);
/* Send value */
SPI_SendData(SPI1, val);
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET){}
/* Dummy read */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE)== RESET){}
SPI_ReceiveData(SPI1);
/* Slave select hi */
GPIO_WriteBit(GPIOC, GPIO_Pin_3, Bit_SET);
}
/* Cfr: LCD_ReadReg */
u8 max3421eRegRd(u8 reg)
{
u8 rddata;
/* Slave select low. According to Maxim spec (p13), we should wait at
* least tl=30ns */
GPIO_WriteBit(GPIOC, GPIO_Pin_3, Bit_RESET);
/* Send command */
SPI_SendData(SPI1, reg);
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET){}
/* Dummy read */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE)== RESET){}
SPI_ReceiveData(SPI1);
/* Dummy write */
SPI_SendData(SPI1, 0xFF);
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET){}
/* Actual read */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE)== RESET){}
rddata = SPI_ReceiveData(SPI1);
/* Slave select hi. Should wait tcsw=300 ns before next transfer */
GPIO_WriteBit(GPIOC, GPIO_Pin_3, Bit_SET);
return rddata;
}
char* max3421eBytesWr(u8 reg, u8 nbytes, char* data )
{
while(nbytes--){
max3421eRegWr(reg, *data);
data++;
}
return( data );
}
char* max3421eBytesRd(u8 reg, u8 nbytes, char* data)
{
while(nbytes--){
*data = max3421eRegRd(reg);
data++;
}
return data;
}
u8 max3421eReset(void)
{
u16 tmp = 0;
max3421eRegWr( rUSBCTL, bmCHIPRES ); //Chip reset. This stops the oscillator
max3421eRegWr( rUSBCTL, 0x00 ); //Remove the reset
while(!(max3421eRegRd( rUSBIRQ ) & bmOSCOKIRQ )) { //wait until the PLL is stable
vTaskDelay(10);
tmp++; //timeout after 100ms
if( tmp == 10 ) {
return( false );
}
}
return( true );
}
void max3421ePowerOn(void)
{
max3421eRegWr( rPINCTL,( bmFDUPSPI + bmINTLEVEL + bmGPXB )); // Full-duplex SPI, level interrupt, GPX
if( max3421eReset() == false ) { // stop/start the oscillator
print("Error: OSCOKIRQ failed to assert\r\n");
panic();
}else{
print("MAX3421e reset [ok]\r\n");
}
/* configure host operation */
max3421eRegWr( rMODE, bmDPPULLDN|bmDMPULLDN|bmHOST|bmSEPIRQ ); // set pull-downs, Host, Separate GPIN IRQ on GPX
max3421eRegWr( rHIEN, bmCONDETIE|bmFRAMEIE ); // connection detection
/* check if device is connected */
max3421eRegWr( rHCTL,bmSAMPLEBUS ); // sample USB bus
while(!(max3421eRegRd( rHCTL ) & bmSAMPLEBUS )); // wait for sample operation to finish
busprobe(); // check if anything is connected
max3421eRegWr( rHIRQ, bmCONDETIRQ ); // clear connection detect interrupt
max3421eRegWr( rCPUCTL, 0x01 ); // enable interrupt pin
print("MAX3421e powered on [ok]\r\n");
}
/* MAX3421 state change task and interrupt handler */
u8 max3421eTask( void )
{
u8 rcode = 0;
u8 pinvalue;
//Serial.print("Vbus state: ");
//Serial.println( vbusState, HEX );
pinvalue = readINT();
if( pinvalue == Bit_RESET ) {
rcode = IntHandler();
}
pinvalue = readGPX();
if( pinvalue == Bit_RESET ) {
GpxHandler();
}
// usbSM(); //USB state machine
return( rcode );
}
/* Private methods
*/
void spi_init(void)
{
SPI_InitTypeDef SPI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable SPI1 clock */
RCC_APB1PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
/* Configure SPI1 pins: NSS, SCK, MISO and MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* SPI1 Config (cfr. Demo/Common/drivers/ST/STM32F10xFWLib/src/lcd.c) */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_Init(SPI1, &SPI_InitStructure);
/* SPI1 enable */
SPI_Cmd(SPI1, ENABLE);
}
void pinInit(void)
{
/* Slave select high */
GPIO_WriteBit(GPIOC, GPIO_Pin_3, Bit_SET);
/* Also Reset line MUST be se high otherwise reset() wont work
* In our setup it is wired to 3.3V
*/
}
/* probe bus to determine device presense and speed and switch host to this speed */
void busprobe(void)
{
u8 bus_sample;
bus_sample = max3421eRegRd( rHRSL ); //Get J,K status
bus_sample &= ( bmJSTATUS|bmKSTATUS ); //zero the rest of the byte
switch( bus_sample ) { //start full-speed or low-speed host
case( bmJSTATUS ):
if(( max3421eRegRd( rMODE ) & bmLOWSPEED ) == 0 ) {
max3421eRegWr( rMODE, MODE_FS_HOST ); //start full-speed host
vbusState = FSHOST;
}
else {
max3421eRegWr( rMODE, MODE_LS_HOST); //start low-speed host
vbusState = LSHOST;
}
break;
case( bmKSTATUS ):
if(( max3421eRegRd( rMODE ) & bmLOWSPEED ) == 0 ) {
max3421eRegWr( rMODE, MODE_LS_HOST ); //start low-speed host
vbusState = LSHOST;
}
else {
max3421eRegWr( rMODE, MODE_FS_HOST ); //start full-speed host
vbusState = FSHOST;
}
break;
case( bmSE1 ): //illegal state
vbusState = SE1;
break;
case( bmSE0 ): //disconnected state
max3421eRegWr( rMODE, bmDPPULLDN|bmDMPULLDN|bmHOST|bmSEPIRQ);
vbusState = SE0;
break;
}//end switch( bus_sample )
}
u8 getVbusState(void)
{
return( vbusState );
}
u8 IntHandler(void)
{
u8 HIRQ;
u8 HIRQ_sendback = 0x00;
HIRQ = max3421eRegRd( rHIRQ ); //determine interrupt source
//if( HIRQ & bmFRAMEIRQ ) { //->1ms SOF interrupt handler
// HIRQ_sendback |= bmFRAMEIRQ;
//}//end FRAMEIRQ handling
if( HIRQ & bmCONDETIRQ ) {
busprobe();
HIRQ_sendback |= bmCONDETIRQ;
}
/* End HIRQ interrupts handling, clear serviced IRQs */
max3421eRegWr( rHIRQ, HIRQ_sendback );
return( HIRQ_sendback );
}
u8 GpxHandler(void)
{
u8 GPINIRQ = max3421eRegRd( rGPINIRQ ); //read GPIN IRQ register
// if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload
// vbusPwr( OFF ); //attempt powercycle
// delay( 1000 );
// vbusPwr( ON );
// regWr( rGPINIRQ, bmGPINIRQ7 );
// }
return( GPINIRQ );
}
u8 readINT(void)
{
return (u8)GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_7);
}
u8 readGPX(void)
{
// return GPX_PIN & _BV(GPX) ? HIGH : LOW;
return (u8)Bit_RESET;
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/USB_Host_Shield/Max3421e.c | C | oos | 10,481 |
/*
* Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com
* MAX3421E USB host controller support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the authors nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* USB functions */
#include <string.h>
#include "Usb.h"
#include "iNEMO_util.h"
static byte usb_error = 0;
static byte usb_task_state;
DEV_RECORD devtable[ USB_NUMDEVICES + 1 ];
EP_RECORD dev0ep; //Endpoint data structure used during enumeration for uninitialized device
/* constructor */
void usbUSB () {
usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE; //set up state machine
usbInit();
print("USB stack initialized [ok]\r\n");
}
/* Initialize data structures */
void usbInit(void)
{
byte i;
for( i = 0; i < ( USB_NUMDEVICES + 1 ); i++ ) {
devtable[ i ].epinfo = NULL; //clear device table
devtable[ i ].devclass = 0;
}
devtable[ 0 ].epinfo = &dev0ep; //set single ep for uninitialized device
// not necessary dev0ep.MaxPktSize = 8; //minimum possible
dev0ep.sndToggle = bmSNDTOG0; //set DATA0/1 toggles to 0
dev0ep.rcvToggle = bmRCVTOG0;
}
byte usbGetUsbTaskState( void )
{
return( usb_task_state );
}
void usbSetUsbTaskState( byte state )
{
usb_task_state = state;
}
EP_RECORD* usbGetDevTableEntry( byte addr, byte ep )
{
EP_RECORD* ptr;
ptr = devtable[ addr ].epinfo;
ptr += ep;
return( ptr );
}
/* set device table entry */
/* each device is different and has different number of endpoints. This function plugs endpoint record structure, defined in application, to devtable */
void usbSetDevTableEntry( byte addr, EP_RECORD* eprecord_ptr )
{
devtable[ addr ].epinfo = eprecord_ptr;
//return();
}
/* Control transfer. Sets address, endpoint, fills control packet with necessary data, dispatches control packet, and initiates bulk IN transfer, */
/* depending on request. Actual requests are defined as inlines */
/* return codes: */
/* 00 = success */
/* 01-0f = non-zero HRSLT */
byte usbCtrlReq( byte addr, byte ep, byte bmReqType, byte bRequest, byte wValLo, byte wValHi, u16 wInd, u16 nbytes, char* dataptr, unsigned int nak_limit)
{
boolean direction = false; //request direction, IN or OUT
byte rcode;
SETUP_PKT setup_pkt;
SETUP_PKT* address = & setup_pkt;
memset(address, 0, sizeof(SETUP_PKT));
max3421eRegWr( rPERADDR, addr ); //set peripheral address
if( bmReqType & 0x80 ) {
direction = true; //determine request direction
}
/* fill in setup packet */
setup_pkt.ReqType_u.bmRequestType = bmReqType;
setup_pkt.bRequest = bRequest;
setup_pkt.wVal_u.dummy.wValueLo = wValLo; //CFR strange stuff in .h definition
setup_pkt.wVal_u.dummy.wValueHi = wValHi;
setup_pkt.wIndex = wInd;
setup_pkt.wLength = nbytes;
max3421eBytesWr( rSUDFIFO, 8, ( char *)&setup_pkt ); //transfer to setup packet FIFO
rcode = usbDispatchPkt( tokSETUP, ep, nak_limit); //dispatch packet
print("Setup packet\r\n"); //DEBUG
if( rcode ) { //return HRSLT if not zero
print("Setup packet error: \r\n");
//print( rcode, HEX );
return( rcode );
}
//Serial.println( direction, HEX );
if( dataptr != NULL ) { //data stage, if present
rcode = usbCtrlData_NAK_LIMIT( addr, ep, nbytes, dataptr, direction );
}
if( rcode ) { //return error
print("Data packet error: \r\n");
//Serial.print( rcode, HEX );
return( rcode );
}
rcode = usbCtrlStatus_NAK_LIMIT( ep, direction ); //status stage
return( rcode );
}
/* Control transfer with status stage and no data stage */
/* Assumed peripheral address is already set */
byte usbCtrlStatus( byte ep, boolean direction, unsigned int nak_limit)
{
byte rcode;
if( direction ) { //GET
rcode = usbDispatchPkt( tokOUTHS, ep, nak_limit );
}
else {
rcode = usbDispatchPkt( tokINHS, ep, nak_limit );
}
return( rcode );
}
/* Control transfer with data stage. Stages 2 and 3 of control transfer. Assumes preipheral address is set and setup packet has been sent */
byte usbCtrlData( byte addr, byte ep, u16 nbytes, char* dataptr, boolean direction, unsigned int nak_limit )
{
byte rcode;
if( direction ) { //IN transfer
devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1;
rcode = usbInTransfer( addr, ep, nbytes, dataptr, nak_limit );
return( rcode );
}
else { //OUT transfer
devtable[ addr ].epinfo[ ep ].sndToggle = bmSNDTOG1;
rcode = usbOutTransfer( addr, ep, nbytes, dataptr, nak_limit );
return( rcode );
}
}
/* IN transfer to arbitrary endpoint. Assumes PERADDR is set. Handles multiple packets if necessary. Transfers 'nbytes' bytes. */
/* Keep sending INs and writes data to memory area pointed by 'data' */
/* rcode 0 if no errors. rcode 01-0f is relayed from dispatchPkt(). Rcode f0 means RCVDAVIRQ error,
fe USB xfer timeout */
byte usbInTransfer( byte addr, byte ep, u16 nbytes, char* data, unsigned int nak_limit)
{
byte rcode;
byte pktsize;
byte maxpktsize = devtable[ addr ].epinfo[ ep ].MaxPktSize;
u16 xfrlen = 0;
max3421eRegWr( rHCTL, devtable[ addr ].epinfo[ ep ].rcvToggle ); //set toggle value
while( 1 ) { // use a 'return' to exit this loop
rcode = usbDispatchPkt( tokIN, ep, nak_limit ); //IN packet to EP-'endpoint'. Function takes care of NAKS.
if( rcode ) {
return( rcode ); //should be 0, indicating ACK. Else return error code.
}
/* check for RCVDAVIRQ and generate error if not present */
/* the only case when absense of RCVDAVIRQ makes sense is when toggle error occured. Need to add handling for that */
if(( max3421eRegRd( rHIRQ ) & bmRCVDAVIRQ ) == 0 ) {
return ( 0xf0 ); //receive error
}
pktsize = max3421eRegRd( rRCVBC ); //number of received bytes
data = max3421eBytesRd( rRCVFIFO, pktsize, data );
max3421eRegWr( rHIRQ, bmRCVDAVIRQ ); // Clear the IRQ & free the buffer
xfrlen += pktsize; // add this packet's byte count to total transfer length
/* The transfer is complete under two conditions: */
/* 1. The device sent a short packet (L.T. maxPacketSize) */
/* 2. 'nbytes' have been transferred. */
if (( pktsize < maxpktsize ) || (xfrlen >= nbytes )) { // have we transferred 'nbytes' bytes?
if( max3421eRegRd( rHRSL ) & bmRCVTOGRD ) { //save toggle value
devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1;
}
else {
devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG0;
}
return( 0 );
}
}//while( 1 )
}
int usbNewInTransfer( byte addr, byte ep, u16 nbytes, char* data, unsigned int nak_limit)
{
byte rcode;
byte pktsize;
byte maxpktsize = devtable[ addr ].epinfo[ ep ].MaxPktSize;
u16 xfrlen = 0;
max3421eRegWr( rHCTL, devtable[ addr ].epinfo[ ep ].rcvToggle ); //set toggle value
while( 1 ) { // use a 'return' to exit this loop
rcode = usbDispatchPkt( tokIN, ep, nak_limit); //IN packet to EP-'endpoint'. Function takes care of NAKS.
if( rcode ) {
return -1; //should be 0, indicating ACK. Else return error code.
}
/* check for RCVDAVIRQ and generate error if not present */
/* the only case when absense of RCVDAVIRQ makes sense is when toggle error occured. Need to add handling for that */
if(( max3421eRegRd( rHIRQ ) & bmRCVDAVIRQ ) == 0 ) {
return -1; //receive error
}
pktsize = max3421eRegRd( rRCVBC ); //number of received bytes
data = max3421eBytesRd( rRCVFIFO, pktsize, data );
max3421eRegWr( rHIRQ, bmRCVDAVIRQ ); // Clear the IRQ & free the buffer
xfrlen += pktsize; // add this packet's byte count to total transfer length
/* The transfer is complete under two conditions: */
/* 1. The device sent a short packet (L.T. maxPacketSize) */
/* 2. 'nbytes' have been transferred. */
if (( pktsize < maxpktsize ) || (xfrlen >= nbytes )) { // have we transferred 'nbytes' bytes?
if( max3421eRegRd( rHRSL ) & bmRCVTOGRD ) { //save toggle value
devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1;
}
else {
devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG0;
}
return xfrlen;
}
}//while( 1 )
}
/* OUT transfer to arbitrary endpoint. Assumes PERADDR is set. Handles multiple packets if necessary. Transfers 'nbytes' bytes. */
/* Handles NAK bug per Maxim Application Note 4000 for single buffer transfer */
/* rcode 0 if no errors. rcode 01-0f is relayed from HRSL */
/* major part of this function borrowed from code shared by Richard Ibbotson */
byte usbOutTransfer( byte addr, byte ep, u16 nbytes, char* data, unsigned int nak_limit)
{
byte rcode, retry_count;
char* data_p = data; //local copy of the data pointer
u16 bytes_tosend, nak_count;
u16 bytes_left = nbytes;
byte maxpktsize = devtable[ addr ].epinfo[ ep ].MaxPktSize;
unsigned long timeout = millis() + USB_XFER_TIMEOUT;
if (!maxpktsize) { //todo: move this check close to epinfo init. Make it 1< pktsize <64
return 0xFE;
}
max3421eRegWr( rHCTL, devtable[ addr ].epinfo[ ep ].sndToggle ); //set toggle value
while( bytes_left ) {
retry_count = 0;
nak_count = 0;
bytes_tosend = ( bytes_left >= maxpktsize ) ? maxpktsize : bytes_left;
max3421eBytesWr( rSNDFIFO, bytes_tosend, data_p ); //filling output FIFO
max3421eRegWr( rSNDBC, bytes_tosend ); //set number of bytes
max3421eRegWr( rHXFR, ( tokOUT | ep )); //dispatch packet
while(!(max3421eRegRd( rHIRQ ) & bmHXFRDNIRQ )); //wait for the completion IRQ
max3421eRegWr( rHIRQ, bmHXFRDNIRQ ); //clear IRQ
rcode = ( max3421eRegRd( rHRSL ) & 0x0f );
while( rcode && ( timeout > millis())) {
switch( rcode ) {
case hrNAK:
nak_count++;
if( nak_limit && ( nak_count == USB_NAK_LIMIT )) {
return( rcode); //return NAK
}
break;
case hrTIMEOUT:
retry_count++;
if( retry_count == USB_RETRY_LIMIT ) {
return( rcode ); //return TIMEOUT
}
break;
default:
return( rcode );
}//switch( rcode...
/* process NAK according to Host out NAK bug */
max3421eRegWr( rSNDBC, 0 );
max3421eRegWr( rSNDFIFO, *data_p );
max3421eRegWr( rSNDBC, bytes_tosend );
max3421eRegWr( rHXFR, ( tokOUT | ep )); //dispatch packet
while(!(max3421eRegRd( rHIRQ ) & bmHXFRDNIRQ )); //wait for the completion IRQ
max3421eRegWr( rHIRQ, bmHXFRDNIRQ ); //clear IRQ
rcode = ( max3421eRegRd( rHRSL ) & 0x0f );
}//while( rcode && ....
bytes_left -= bytes_tosend;
data_p += bytes_tosend;
}//while( bytes_left...
devtable[ addr ].epinfo[ ep ].sndToggle = ( max3421eRegRd( rHRSL ) & bmSNDTOGRD ) ? bmSNDTOG1 : bmSNDTOG0; //update toggle
return( rcode ); //should be 0 in all cases
}
/* dispatch usb packet. Assumes peripheral address is set and relevant buffer is loaded/empty */
/* If NAK, tries to re-send up to nak_limit times */
/* If nak_limit == 0, do not count NAKs, exit after timeout */
/* If bus timeout, re-sends up to USB_RETRY_LIMIT times */
/* return codes 0x00-0x0f are HRSLT( 0x00 being success ), 0xff means timeout */
byte usbDispatchPkt( byte token, byte ep, unsigned int nak_limit)
{
unsigned long timeout = millis() + USB_XFER_TIMEOUT;
byte tmpdata;
byte rcode;
u16 nak_count = 0;
char retry_count = 0;
while( timeout > millis() ) {
max3421eRegWr( rHXFR, ( token|ep )); //launch the transfer
rcode = 0xff;
while( millis() < timeout ) { //wait for transfer completion
tmpdata = max3421eRegRd( rHIRQ );
if( tmpdata & bmHXFRDNIRQ ) {
max3421eRegWr( rHIRQ, bmHXFRDNIRQ ); //clear the interrupt
rcode = 0x00;
break;
}//if( tmpdata & bmHXFRDNIRQ
}//while ( millis() < timeout
if( rcode != 0x00 ) { //exit if timeout
return( rcode );
}
rcode = ( max3421eRegRd( rHRSL ) & 0x0f ); //analyze transfer result
switch( rcode ) {
case hrNAK:
nak_count ++;
if(nak_limit && ( nak_count == nak_limit )) {
return( rcode );
}
break;
case hrTIMEOUT:
retry_count ++;
if( retry_count == USB_RETRY_LIMIT ) {
return( rcode );
}
break;
default:
return( rcode );
}//switch( rcode
}//while( timeout > millis()
return( rcode );
}
/* USB main task. Performs enumeration/cleanup */
void usbTask( void ) //USB state machine
{
byte i;
byte rcode;
byte tmpdata;
static unsigned long delay = 0;
USB_DEVICE_DESCRIPTOR buf;
tmpdata = getVbusState();
/* modify USB task state if Vbus changed */
switch( tmpdata ) {
case SE1: //illegal state
usb_task_state = USB_DETACHED_SUBSTATE_ILLEGAL;
break;
case SE0: //disconnected
if(( usb_task_state & USB_STATE_MASK ) != USB_STATE_DETACHED ) {
usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE;
}
break;
case FSHOST: //attached
case LSHOST:
if(( usb_task_state & USB_STATE_MASK ) == USB_STATE_DETACHED ) {
delay = millis() + USB_SETTLE_DELAY;
usb_task_state = USB_ATTACHED_SUBSTATE_SETTLE;
}
break;
}// switch( tmpdata
//Serial.print("USB task state: ");
//Serial.println( usb_task_state, HEX );
switch( usb_task_state ) {
case USB_DETACHED_SUBSTATE_INITIALIZE:
usbInit();
usb_task_state = USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE;
break;
case USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE: //just sit here
break;
case USB_DETACHED_SUBSTATE_ILLEGAL: //just sit here
break;
case USB_ATTACHED_SUBSTATE_SETTLE: //setlle time for just attached device
if( delay < millis() ) {
usb_task_state = USB_ATTACHED_SUBSTATE_RESET_DEVICE;
}
break;
case USB_ATTACHED_SUBSTATE_RESET_DEVICE:
max3421eRegWr( rHCTL, bmBUSRST ); //issue bus reset
usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE;
break;
case USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE:
if(( max3421eRegRd( rHCTL ) & bmBUSRST ) == 0 ) {
tmpdata = max3421eRegRd( rMODE ) | bmSOFKAENAB; //start SOF generation
max3421eRegWr( rMODE, tmpdata );
// max3421eRegWr( rMODE, bmSOFKAENAB );
usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_SOF;
delay = millis() + 20; //20ms wait after reset per USB spec
}
break;
case USB_ATTACHED_SUBSTATE_WAIT_SOF: //todo: change check order
if( max3421eRegRd( rHIRQ ) & bmFRAMEIRQ ) { //when first SOF received we can continue
if( delay < millis() ) { //20ms passed
usb_task_state = USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE;
}
}
break;
case USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE:
// toggle( BPNT_0 );
devtable[ 0 ].epinfo->MaxPktSize = 8; //set max.packet size to min.allowed
rcode = usbGetDevDescr( 0, 0, 8, ( char* )&buf );
if( rcode == 0 ) {
devtable[ 0 ].epinfo->MaxPktSize = buf.bMaxPacketSize0;
usb_task_state = USB_STATE_ADDRESSING;
}
else {
usb_error = USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE;
usb_task_state = USB_STATE_ERROR;
}
break;
case USB_STATE_ADDRESSING:
for( i = 1; i < USB_NUMDEVICES; i++ ) {
if( devtable[ i ].epinfo == NULL ) {
devtable[ i ].epinfo = devtable[ 0 ].epinfo; //set correct MaxPktSize
//temporary record
//until plugged with real device endpoint structure
rcode = usbSetAddr( 0, 0, i );
if( rcode == 0 ) {
usb_task_state = USB_STATE_CONFIGURING;
}
else {
usb_error = USB_STATE_ADDRESSING; //set address error
usb_task_state = USB_STATE_ERROR;
}
break; //break if address assigned or error occured during address assignment attempt
}
}//for( i = 1; i < USB_NUMDEVICES; i++
if( usb_task_state == USB_STATE_ADDRESSING ) { //no vacant place in devtable
usb_error = 0xfe;
usb_task_state = USB_STATE_ERROR;
}
break;
case USB_STATE_CONFIGURING:
break;
case USB_STATE_RUNNING:
break;
case USB_STATE_ERROR:
break;
}// switch( usb_task_state
}
//get device descriptor
byte usbGetDevDescr( byte addr, byte ep, u16 nbytes, char* dataptr) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, 0x00, USB_DESCRIPTOR_DEVICE, 0x0000, nbytes, dataptr));
}
//get configuration descriptor
byte usbGetConfDescr( byte addr, byte ep, u16 nbytes, byte conf, char* dataptr) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, conf, USB_DESCRIPTOR_CONFIGURATION, 0x0000, nbytes, dataptr ));
}
//get string descriptor
byte usbGetStrDescr( byte addr, byte ep, u16 nbytes, byte index, u16 langid, char* dataptr) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, index, USB_DESCRIPTOR_STRING, langid, nbytes, dataptr));
}
//set address
byte usbSetAddr( byte oldaddr, byte ep, byte newaddr) {
return( usbCtrlReq_NAK_LIMIT( oldaddr, ep, bmREQ_SET, USB_REQUEST_SET_ADDRESS, newaddr, 0x00, 0x0000, 0x0000, NULL));
}
//set configuration
byte usbSetConf( byte addr, byte ep, byte conf_value) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_SET, USB_REQUEST_SET_CONFIGURATION, conf_value, 0x00, 0x0000, 0x0000, NULL));
}
//class requests
byte usbSetProto( byte addr, byte ep, byte interface, byte protocol) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_HIDOUT, HID_REQUEST_SET_PROTOCOL, protocol, 0x00, interface, 0x0000, NULL));
}
byte usbGetProto( byte addr, byte ep, byte interface, char* dataptr) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_PROTOCOL, 0x00, 0x00, interface, 0x0001, dataptr));
}
//get HID report descriptor
byte usbGetReportDescr( byte addr, byte ep, u16 nbytes, char* dataptr) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_HIDREPORT, USB_REQUEST_GET_DESCRIPTOR, 0x00, HID_DESCRIPTOR_REPORT, 0x0000, nbytes, dataptr));
}
byte usbSetReport( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_HIDOUT, HID_REQUEST_SET_REPORT, report_id, report_type, interface, nbytes, dataptr));
}
byte usbGetReport( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr) { // ** RI 04/11/09
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_REPORT, report_id, report_type, interface, nbytes, dataptr));
}
/* returns one byte of data in dataptr */
byte usbGetIdle( byte addr, byte ep, byte interface, byte reportID, char* dataptr) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_IDLE, reportID, 0, interface, 0x0001, dataptr));
}
byte usbSetIdle( byte addr, byte ep, byte interface, byte reportID, byte duration) {
return( usbCtrlReq_NAK_LIMIT( addr, ep, bmREQ_HIDOUT, HID_REQUEST_SET_IDLE, reportID, duration, interface, 0x0000, NULL));
}
byte usbCtrlReq_NAK_LIMIT( byte addr, byte ep, byte bmReqType, byte bRequest, byte wValLo, byte wValHi, u16 wInd, u16 nbytes, char* dataptr){
return usbCtrlReq(addr, ep, bmReqType, bRequest, wValLo, wValHi, wInd, nbytes, dataptr, USB_NAK_LIMIT);
}
/*
byte usbGetDevDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* dataptr){
return usbGetDevDescr(addr, ep, nbytes, dataptr, USB_NAK_LIMIT);
}
byte usbGetConfDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte conf, char* dataptr){
return usbGetConfDescr( addr, ep, nbytes, conf, dataptr, USB_NAK_LIMIT);
}
byte usbGetStrDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte index, u16 langid){
return usbGetStrDescr(addr, ep, nbytes, index, langid, USB_NAK_LIMIT);
}
byte usbSetAddr_NAK_LIMIT( byte oldaddr, byte ep, byte newaddr){
return usbSetAddr(oldaddr, ep, newaddr, USB_NAK_LIMIT);
}
byte usbSetConf_NAK_LIMIT( byte addr, byte ep, byte conf_value){
return usbSetConf(addr, ep, conf_value, USB_NAK_LIMIT);
}
byte usbSetProto_NAK_LIMIT( byte addr, byte ep, byte interface, byte protocol){
return usbSetProto(addr, ep, interface, protocol, USB_NAK_LIMIT);
}
byte usbGetProto_NAK_LIMIT( byte addr, byte ep, byte interface, char* dataptr){
return usbGetProto(addr, ep, interface, dataptr, USB_NAK_LIMIT);
}
byte usbGetReportDescr_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* dataptr){
return usbGetReportDescr(addr, ep, nbytes, dataptr, USB_NAK_LIMIT);
}
byte usbSetReport_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr){
return usbSetReport(addr, ep, nbytes, interface, report_type, report_id, dataptr, USB_NAK_LIMIT);
}
byte usbGetReport_NAK_LIMIT( byte addr, byte ep, u16 nbytes, byte interface, byte report_type, byte report_id, char* dataptr){
return usbGetReport(addr, ep, nbytes, interface, report_type, report_id, dataptr, USB_NAK_LIMIT);
}
byte usbGetIdle_NAK_LIMIT( byte addr, byte ep, byte interface, byte reportID, char* dataptr){
return usbGetIdle(addr, ep, nbytes, interface, reportID, dataptr, USB_NAK_LIMIT);
}
byte usbSetIdle_NAK_LIMIT( byte addr, byte ep, byte interface, byte reportID, byte duration){
return usbSetIdle(addr, ep, nbytes, interface, reportID, duration, USB_NAK_LIMIT);
}
*/
byte usbCtrlData_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* dataptr, boolean direction){
return usbCtrlData(addr, ep, nbytes, dataptr, direction, USB_NAK_LIMIT);
}
byte usbCtrlStatus_NAK_LIMIT( byte ep, boolean direction){
return usbCtrlStatus(ep, direction, USB_NAK_LIMIT);
}
byte usbInTransfer_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* data){
return usbInTransfer(addr, ep, nbytes, data, USB_NAK_LIMIT);
}
int usbNewInTransfer_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* data){
return usbNewInTransfer(addr, ep, nbytes, data, USB_NAK_LIMIT);
}
byte usbOutTransfer_NAK_LIMIT( byte addr, byte ep, u16 nbytes, char* data){
return usbOutTransfer(addr, ep, nbytes, data, USB_NAK_LIMIT);
}
byte usbDispatchPkt_NAK_LIMIT( byte token, byte ep){
return usbDispatchPkt(token, ep, USB_NAK_LIMIT);
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/USB_Host_Shield/Usb.c | C | oos | 26,596 |
/*
* Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com
* MAX3421E USB host controller support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the authors nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* MAX3421E register/bit names and bitmasks */
#ifndef _MAX3421Econstants_h_
#define _MAX3421Econstants_h_
/* SPI pins for diffrent Arduinos */
#if defined(__AVR_ATmega1280__) || (__AVR_ATmega2560__)
#define SCK_PIN 52
#define MISO_PIN 50
#define MOSI_PIN 51
#define SS_PIN 53
#endif
#if defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__)
#define SCK_PIN 13
#define MISO_PIN 12
#define MOSI_PIN 11
#define SS_PIN 10
#endif
#define MAX_SS 53
#define MAX_INT 9
#define MAX_GPX 8
#define MAX_RESET 7
/* "Breakpoint" pins for debugging */
//#define BPNT_0 3
//#define BPNT_1 2
//#define Select_MAX3421E digitalWrite(MAX_SS,LOW)
//#define Deselect_MAX3421E digitalWrite(MAX_SS,HIGH)
/* */
#define ON true
#define OFF false
/* VBUS states */
#define SE0 0
#define SE1 1
#define FSHOST 2
#define LSHOST 3
/* MAX3421E command byte format: rrrrr0wa where 'r' is register number */
//
// MAX3421E Registers in HOST mode.
//
#define rRCVFIFO 0x08 //1<<3
#define rSNDFIFO 0x10 //2<<3
#define rSUDFIFO 0x20 //4<<3
#define rRCVBC 0x30 //6<<3
#define rSNDBC 0x38 //7<<3
#define rUSBIRQ 0x68 //13<<3
/* USBIRQ Bits */
#define bmVBUSIRQ 0x40 //b6
#define bmNOVBUSIRQ 0x20 //b5
#define bmOSCOKIRQ 0x01 //b0
#define rUSBIEN 0x70 //14<<3
/* USBIEN Bits */
#define bmVBUSIE 0x40 //b6
#define bmNOVBUSIE 0x20 //b5
#define bmOSCOKIE 0x01 //b0
#define rUSBCTL 0x78 //15<<3
/* USBCTL Bits */
#define bmCHIPRES 0x20 //b5
#define bmPWRDOWN 0x10 //b4
#define rCPUCTL 0x80 //16<<3
/* CPUCTL Bits */
#define bmPUSLEWID1 0x80 //b7
#define bmPULSEWID0 0x40 //b6
#define bmIE 0x01 //b0
#define rPINCTL 0x88 //17<<3
/* PINCTL Bits */
#define bmFDUPSPI 0x10 //b4
#define bmINTLEVEL 0x08 //b3
#define bmPOSINT 0x04 //b2
#define bmGPXB 0x02 //b1
#define bmGPXA 0x01 //b0
// GPX pin selections
#define GPX_OPERATE 0x00
#define GPX_VBDET 0x01
#define GPX_BUSACT 0x02
#define GPX_SOF 0x03
#define rREVISION 0x90 //18<<3
#define rIOPINS1 0xa0 //20<<3
/* IOPINS1 Bits */
#define bmGPOUT0 0x01
#define bmGPOUT1 0x02
#define bmGPOUT2 0x04
#define bmGPOUT3 0x08
#define bmGPIN0 0x10
#define bmGPIN1 0x20
#define bmGPIN2 0x40
#define bmGPIN3 0x80
#define rIOPINS2 0xa8 //21<<3
/* IOPINS2 Bits */
#define bmGPOUT4 0x01
#define bmGPOUT5 0x02
#define bmGPOUT6 0x04
#define bmGPOUT7 0x08
#define bmGPIN4 0x10
#define bmGPIN5 0x20
#define bmGPIN6 0x40
#define bmGPIN7 0x80
#define rGPINIRQ 0xb0 //22<<3
/* GPINIRQ Bits */
#define bmGPINIRQ0 0x01
#define bmGPINIRQ1 0x02
#define bmGPINIRQ2 0x04
#define bmGPINIRQ3 0x08
#define bmGPINIRQ4 0x10
#define bmGPINIRQ5 0x20
#define bmGPINIRQ6 0x40
#define bmGPINIRQ7 0x80
#define rGPINIEN 0xb8 //23<<3
/* GPINIEN Bits */
#define bmGPINIEN0 0x01
#define bmGPINIEN1 0x02
#define bmGPINIEN2 0x04
#define bmGPINIEN3 0x08
#define bmGPINIEN4 0x10
#define bmGPINIEN5 0x20
#define bmGPINIEN6 0x40
#define bmGPINIEN7 0x80
#define rGPINPOL 0xc0 //24<<3
/* GPINPOL Bits */
#define bmGPINPOL0 0x01
#define bmGPINPOL1 0x02
#define bmGPINPOL2 0x04
#define bmGPINPOL3 0x08
#define bmGPINPOL4 0x10
#define bmGPINPOL5 0x20
#define bmGPINPOL6 0x40
#define bmGPINPOL7 0x80
#define rHIRQ 0xc8 //25<<3
/* HIRQ Bits */
#define bmBUSEVENTIRQ 0x01 // indicates BUS Reset Done or BUS Resume
#define bmRWUIRQ 0x02
#define bmRCVDAVIRQ 0x04
#define bmSNDBAVIRQ 0x08
#define bmSUSDNIRQ 0x10
#define bmCONDETIRQ 0x20
#define bmFRAMEIRQ 0x40
#define bmHXFRDNIRQ 0x80
#define rHIEN 0xd0 //26<<3
/* HIEN Bits */
#define bmBUSEVENTIE 0x01
#define bmRWUIE 0x02
#define bmRCVDAVIE 0x04
#define bmSNDBAVIE 0x08
#define bmSUSDNIE 0x10
#define bmCONDETIE 0x20
#define bmFRAMEIE 0x40
#define bmHXFRDNIE 0x80
#define rMODE 0xd8 //27<<3
/* MODE Bits */
#define bmHOST 0x01
#define bmLOWSPEED 0x02
#define bmHUBPRE 0x04
#define bmSOFKAENAB 0x08
#define bmSEPIRQ 0x10
#define bmDELAYISO 0x20
#define bmDMPULLDN 0x40
#define bmDPPULLDN 0x80
#define rPERADDR 0xe0 //28<<3
#define rHCTL 0xe8 //29<<3
/* HCTL Bits */
#define bmBUSRST 0x01
#define bmFRMRST 0x02
#define bmSAMPLEBUS 0x04
#define bmSIGRSM 0x08
#define bmRCVTOG0 0x10
#define bmRCVTOG1 0x20
#define bmSNDTOG0 0x40
#define bmSNDTOG1 0x80
#define rHXFR 0xf0 //30<<3
/* Host transfer token values for writing the HXFR register (R30) */
/* OR this bit field with the endpoint number in bits 3:0 */
#define tokSETUP 0x10 // HS=0, ISO=0, OUTNIN=0, SETUP=1
#define tokIN 0x00 // HS=0, ISO=0, OUTNIN=0, SETUP=0
#define tokOUT 0x20 // HS=0, ISO=0, OUTNIN=1, SETUP=0
#define tokINHS 0x80 // HS=1, ISO=0, OUTNIN=0, SETUP=0
#define tokOUTHS 0xA0 // HS=1, ISO=0, OUTNIN=1, SETUP=0
#define tokISOIN 0x40 // HS=0, ISO=1, OUTNIN=0, SETUP=0
#define tokISOOUT 0x60 // HS=0, ISO=1, OUTNIN=1, SETUP=0
#define rHRSL 0xf8 //31<<3
/* HRSL Bits */
#define bmRCVTOGRD 0x10
#define bmSNDTOGRD 0x20
#define bmKSTATUS 0x40
#define bmJSTATUS 0x80
#define bmSE0 0x00 //SE0 - disconnect state
#define bmSE1 0xc0 //SE1 - illegal state
/* Host error result codes, the 4 LSB's in the HRSL register */
#define hrSUCCESS 0x00
#define hrBUSY 0x01
#define hrBADREQ 0x02
#define hrUNDEF 0x03
#define hrNAK 0x04
#define hrSTALL 0x05
#define hrTOGERR 0x06
#define hrWRONGPID 0x07
#define hrBADBC 0x08
#define hrPIDERR 0x09
#define hrPKTERR 0x0A
#define hrCRCERR 0x0B
#define hrKERR 0x0C
#define hrJERR 0x0D
#define hrTIMEOUT 0x0E
#define hrBABBLE 0x0F
#define MODE_FS_HOST (bmDPPULLDN|bmDMPULLDN|bmHOST|bmSOFKAENAB)
#define MODE_LS_HOST (bmDPPULLDN|bmDMPULLDN|bmHOST|bmLOWSPEED|bmSOFKAENAB)
#endif //_MAX3421Econstants_h_
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/USB_Host_Shield/Max3421e_constants.h | C | oos | 7,979 |
/** iNEMO utility functions
*/
#ifndef __INEMO_UTIL_H
#define __INEMO_UTIL_H
#define BOARD_IS_INEMOV2 1
/* Task priorities. */
#define IN_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The check task uses the sprintf function so requires a little more stack. */
#define IN_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 200)
void prvSetupHardware(void);
void gpiosInit(void);
int inemoUtilInit(void);
void ledOn(void);
void ledOff(void);
int print(char* string);
void printHex(unsigned int);
unsigned int millis(void);
void delay(int delay);
void panic(void);
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/iNEMO_util.h | C | oos | 602 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 72000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 17 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* This is the raw value as per the Cortex-M3 NVIC. Values can be 255
(lowest) to 0 (1?) (highest). */
#define configKERNEL_INTERRUPT_PRIORITY 255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xb0, or priority 11. */
/* This is the value being used as per the ST library which permits 16
priority values, 0 to 15. This must correspond to the
configKERNEL_INTERRUPT_PRIORITY setting. Here 15 corresponds to the lowest
NVIC value of 255. */
#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15
#endif /* FREERTOS_CONFIG_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/FreeRTOSConfig.h | C | oos | 5,101 |
/** iNEMO ADKPing Accessory firmware
* David Siorpaes (C) STMicroelectronics 2011
*
* Sends a string to Android application and receives back
* data from Android application.
*
* Derived from Android DemoKit.pde Arduino application
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "iNEMO_util.h"
#include <AndroidAccessory.h>
#include "comManager.h"
#include "stm32f10x_tim.h"
#include "STLM75.h"
#include "LSM303DLH.h"
#include "LPS001DL_I2C.h"
#include "LPRYxxxAL.h"
#include <stdio.h>
/**
* Pointer to iNemoData structure. This struct contatins
* the setting values for the sensor parameters of the board.
* (see iNEMO_DATA definition in iNEMO_lib.h)
*
*/
static iNEMO_DATA *s_pSharedData = NULL;
/**
* This resource is used to synchronize the iNemo Command Manager task
* with the Accessory task.
*/
static xQueueHandle s_usbQueue;
/**
* This resource is used to synchronize the TIM2 IRQ and the iNemo data acquisition task.
*/
static xSemaphoreHandle s_timSemaphore;
/* Forward declaration */
static void accessoryTask(void *pvParameters);
static void inCommandTaskFunction(void *pvParameters);
static void inDataTaskFunction(void *pvParameters);
static void Timer_Config(void);
int main( void )
{
int err;
/* Initialize board */
prvSetupHardware();
Timer_Config();
gpiosInit();
/* Create the queue used to synchronize iNemo Command Manager task and the accessory task. */
s_usbQueue = xQueueCreate(1, sizeof(struct receivedMsg));
if (!s_usbQueue) {
// Error in resource creation.
print("Error in resource creation: s_usbQueue\n");
panic();
}
/* Create the semaphore used to synchronize the iNemo data acquisition task and the TIM2 interrupt service routine. */
vSemaphoreCreateBinary(s_timSemaphore);
if (!s_timSemaphore) {
// Error in resource creation.
print("Error in resource creation: s_timSemaphore\n");
panic();
}
xSemaphoreTake(s_timSemaphore, 0);
/* Create Android Accessory task */
if( xTaskCreate(accessoryTask, (signed portCHAR*) "ADK", 512, NULL, IN_TASK_PRIORITY + 1, NULL ) != pdPASS ) {
print("Error in task creation: AccessoryTask\n");
panic();
}
/* Create the iNemo Command task */
if ( xTaskCreate(inCommandTaskFunction, "iNemoCmd", IN_TASK_STACK_SIZE, NULL, IN_TASK_PRIORITY+1, NULL) != pdPASS ) {
// Error in task creation
print("Error in task creation: iNemoCmd\n");
panic();
}
/* Create the iNemo Data stream task */
if ( xTaskCreate(inDataTaskFunction, "iNemoData", IN_TASK_STACK_SIZE, NULL, IN_TASK_PRIORITY, NULL) != pdPASS ) {
// Error in task creation
print("Error in task creation: iNemoData\n");
panic();
}
/* Start the scheduler. */
vTaskStartScheduler();
/* Will only get here if there was not enough heap space to create the idle task. */
panic();
return 0;
}
void accessoryTask(void* pvParameters)
{
/* Initialize iNEMO utility library */
inemoUtilInit();
/* Construct accessory. Vendor, application and version MUST match
* with Android application manifest correspondent entries */
AndroidAccessory("STMicroelectronics", "adkping", "Just pings data", "2.0",
"http://www.st.com", "1234567890123456");
/* Power on accessory */
androidAccessoryPowerOn();
delay(200);
/* Main loop */
while(1){
/* Checks if there is a device connected. If there is
* one, it tries to switch the device in Accesory mode.
* If there is not any device attached, or the device
* does not support ADK (or it simply refuses the connection),
* false is returned. */
if (androidAccessoryIsConnected()) {
int len = 0;
u8 buffer_rx[FRAME_SIZE];
print("Inside acc.isconnected..\r\n");
/* Reads the input stream. If the device sent a message to the board,
* the message is stored in buffer_rx and the number of bytes read
* are stored in len. If no message is present len will be -1. */
len = androidAccessoryRead(buffer_rx, sizeof(buffer_rx), 1);
if(len > 0) {
/* The variable msg will contain the message received from
* the device and its length (in bytes). It is enqueued to
* s_usbQueue in order to be processed by the Command
* Manager Task. */
struct receivedMsg msg;
msg.length = len;
memcpy(msg.msg, buffer_rx, FRAME_SIZE);
xQueueSend(s_usbQueue, &msg, (portTickType) 0);
}
delay(20);
} else{
print("Test loop...\r\n");
delay(20);
ledOn();
delay(20);
ledOff();
}
}
}
/**
* iNemo Command Manager task control function.
* This task waits for a frame coming from the Accessory Task.
*
* pvParameters not used.
*/
void inCommandTaskFunction(void *pvParameters) {
struct receivedMsg msg;
for (;;) {
if ( xQueueReceive(s_usbQueue, &msg, portMAX_DELAY ) == pdTRUE ) {
/* Process the message received from the device. */
ParseCommandFrame(msg.length, msg.msg, s_pSharedData);
}
}
}
/**
* iNemo data acquisition/send task control function.
* This task is synchronized with the Timer2 interrupt. It reads all sensor data, packages the data according to the frame
* format and sends the data to the device over the ADK connection.
*
* pvParameters not used.
*/
void inDataTaskFunction(void *pvParameters)
{
iNEMO_DATA data;
iNEMO_Data_Init(&data);
s_pSharedData = &data;
#ifdef AHRS_MOD
iNEMO_AHRS_Init(&data.m_sensorData, &data.m_angle, &data.m_quat);
#endif
for (;;) {
if ( xSemaphoreTake(s_timSemaphore, portMAX_DELAY) == pdTRUE ) {
DataProcess(GetOutMode(),&data);
}
}
}
/**
* Configures the timer 2
*/
void Timer_Config(void) {
unsigned short a;
unsigned short b;
unsigned long n;
unsigned char frequency = 50; //This value is the frequency interrupts in Hz
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
NVIC_InitTypeDef NVIC_InitStructure;
// Enable timer clocks
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE );
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
TIM_TimeBaseStructInit( &TIM_TimeBaseStructure );
// Time base configuration for timer 2 - which generates the interrupts.
n = configCPU_CLOCK_HZ/frequency;
prvFindFactors( n, &a, &b );
TIM_TimeBaseStructure.TIM_Period = b - 1;
TIM_TimeBaseStructure.TIM_Prescaler = a - 1;
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit( TIM2, &TIM_TimeBaseStructure );
TIM_ARRPreloadConfig( TIM2, ENABLE );
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 13;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init( &NVIC_InitStructure );
}
/**
* This function handles TIM2 global interrupt request by resuming the
* iNemoData task. The timer establishes the sending data rate.
*/
void TIM2_IRQHandler(void) {
if(TIM_GetITStatus(TIM2, TIM_IT_Update)) {
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
xSemaphoreGiveFromISR(s_timSemaphore, &xHigherPriorityTaskWoken);
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
}
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/main.c | C | oos | 7,532 |
#include <string.h>
#include "iNEMO_util.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "serial.h"
/* Library includes. */
#include "stm32f10x_it.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_spi.h"
//#include "STLM75.h"
//#include "LSM303DLH.h"
//#include "LPS001DL_I2C.h"
#include "iNEMO_lib.h"
xComPortHandle uartHandle;
/* Turns iNEMO D3 led on */
void ledOn(void)
{
GPIO_WriteBit(GPIOB, GPIO_Pin_9, Bit_SET);
}
/* Turns iNEMO D3 led off */
void ledOff(void)
{
GPIO_WriteBit(GPIOB, GPIO_Pin_9, Bit_RESET);
}
/* Innitializes UART. MUST be called after FreeRTOS scheduler has started */
int inemoUtilInit(void)
{
uartHandle = xSerialPortInitMinimal(115200, 256);
if(uartHandle != NULL){
print("UART initialized succesfully\n\r");
return 0;
}
return -1;
}
/* Prints on serial line a string */
int print(char* string)
{
int len;
len = strlen(string);
if(uartHandle){
vSerialPutString(uartHandle, (const signed char*)string, len);
return len;
}
else{
return -1;
}
}
/* Prints on serial line hex value */
void printHex(unsigned int val)
{
char string[5];
u8 i;
unsigned int rem;
for(i=0; i<4;i++){
rem = val % 16;
if(rem >= 10)
string[3-i] = 'A' + rem - 10;
else
string[3-i] = '0' + rem;
val /= 16;
}
string[4] = 0;
print(string);
}
/* This mimics the Arduino millis() call: returns the number of milliseconds
* since system reset */
unsigned int millis(void)
{
return xTaskGetTickCount()/portTICK_RATE_MS;
}
/* Arduino adapter: waits for given amount of time (milliseconds) */
void delay(int delay)
{
vTaskDelay(delay);
}
/* Call this when things go awfully wrong */
void panic(void)
{
GPIO_WriteBit(GPIOB, GPIO_Pin_9, Bit_SET);
for(;;);
}
/* Configure clocks, PLL, GPIOs clock gate */
void prvSetupHardware(void)
{
/* Start with the clocks in their expected state. */
RCC_DeInit();
/* Enable HSE (high speed external clock). */
RCC_HSEConfig( RCC_HSE_ON );
/* Wait till HSE is ready. */
while( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) == RESET )
{
}
/* 2 wait states required on the flash. */
*( ( unsigned portLONG * ) 0x40022000 ) = 0x02;
/* HCLK = SYSCLK */
RCC_HCLKConfig( RCC_SYSCLK_Div1 );
/* PCLK2 = HCLK */
RCC_PCLK2Config( RCC_HCLK_Div1 );
/* PCLK1 = HCLK/2 */
#if BOARD_IS_INEMOV2
RCC_PCLK1Config( RCC_HCLK_Div2 ); //STMF103 Max 32MHz
#elif BOARD_IS_DISCOVERY
RCC_PCLK1Config( RCC_HCLK_Div1 ); //STMF100 Max 24MHz
#else
#error "Please define either BOARD_IS_INEMOV2 or BOARD_IS_DISCOVERY"
#endif
/* PLLCLK = 8MHz * 9 = 72 MHz. */
#if BOARD_IS_INEMOV2
RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_9 ); //STMF103 @72MHz
#elif BOARD_IS_DISCOVERY
RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_3 ); //STMF100 @24MHz
#else
#error "Please define either BOARD_IS_INEMOV2 or BOARD_IS_DISCOVERY"
#endif
/* Enable PLL. */
RCC_PLLCmd( ENABLE );
/* Wait till PLL is ready. */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source. */
RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK );
/* Wait till PLL is used as system clock source. */
while( RCC_GetSYSCLKSource() != 0x08 )
{
}
/* Enable GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and AFIO clocks */
RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |RCC_APB2Periph_GPIOC
| RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE );
/* SPI2 Periph clock enable */
RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE );
/* SPI1 Periph clock enable (for Max3421) */
RCC_APB2PeriphClockCmd( RCC_APB2Periph_SPI1, ENABLE );
/* USART2 Periph clock enable (for debug on serial port) */
RCC_APB1PeriphClockCmd( RCC_APB1Periph_USART2, ENABLE );
/* Set the Vector Table base address at 0x08000000 */
NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x0 );
NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );
/* Configure HCLK clock as SysTick clock source. */
SysTick_CLKSourceConfig( SysTick_CLKSource_HCLK );
/* Enable prefetch */
*((unsigned long*)(0x40022000)) = 0x12;
iNEMO_HW_Config();
iNEMO_Config();
}
/* Enables specific GPIOs for application */
void gpiosInit(void)
{
GPIO_InitTypeDef gpioInit;
/* Enable iNemo LED PB9 */
GPIO_StructInit(&gpioInit);
gpioInit.GPIO_Pin = GPIO_Pin_9;
gpioInit.GPIO_Mode = GPIO_Mode_Out_PP;
gpioInit.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_Init(GPIOB, &gpioInit);
/* Enable PB0 for output */
GPIO_StructInit(&gpioInit);
gpioInit.GPIO_Pin = GPIO_Pin_0;
gpioInit.GPIO_Mode = GPIO_Mode_Out_PP;
gpioInit.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_Init(GPIOB, &gpioInit);
/* Enable PC7 for input (Interrupt) */
GPIO_StructInit(&gpioInit);
gpioInit.GPIO_Pin = GPIO_Pin_7;
gpioInit.GPIO_Mode = GPIO_Mode_AIN;
gpioInit.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_Init(GPIOC, &gpioInit);
/* Enable PC3 for output (SPI Slave Select) */
GPIO_StructInit(&gpioInit);
gpioInit.GPIO_Pin = GPIO_Pin_3;
gpioInit.GPIO_Mode = GPIO_Mode_Out_PP;
gpioInit.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_Init(GPIOC, &gpioInit);
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/iNEMO_util.c | C | oos | 5,369 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_conf.h
* Author : MCD Application Team
* Date First Issued : 09/29/2006
* Description : Library configuration file.
********************************************************************************
* History:
* mm/dd/yyyy: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CONF_H
#define __STM32F10x_CONF_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Comment the line below to compile the library in release mode */
//#define DEBUG
/* Comment the line below to disable the specific peripheral inclusion */
/************************************* ADC ************************************/
//#define _ADC
#define _ADC1
//#define _ADC2
/************************************* CAN ************************************/
//#define _CAN
/************************************* DMA ************************************/
#define _DMA
#define _DMA_Channel1
//#define _DMA_Channel2
//#define _DMA_Channel3
//#define _DMA_Channel4
//#define _DMA_Channel5
//#define _DMA_Channel6
//#define _DMA_Channel7
/************************************* EXTI ***********************************/
#define _EXTI
/************************************* GPIO ***********************************/
#define _GPIO
#define _GPIOA
#define _GPIOB
#define _GPIOC
#define _GPIOD
#define _GPIOE
#define _AFIO
/************************************* I2C ************************************/
#define _I2C
#define _I2C1
#define _I2C2
/************************************* IWDG ***********************************/
//#define _IWDG
/************************************* NVIC ***********************************/
#define _NVIC
#define _SCB
/************************************* BKP ************************************/
//#define _BKP
/************************************* PWR ************************************/
//#define _PWR
/************************************* RCC ************************************/
#define _RCC
/************************************* RTC ************************************/
//#define _RTC
/************************************* SPI ************************************/
#define _SPI
#define _SPI1
#define _SPI2
/************************************* SysTick ********************************/
#define _SysTick
/************************************* TIM ************************************/
//#define _TIM
#define _TIM2
#define _TIM3
//#define _TIM4
/************************************* USART **********************************/
#define _USART
#define _USART1
#define _USART2
//#define _USART3
/************************************* WWDG ***********************************/
//#define _WWDG
/* In the following line adjust the value of External High Speed oscillator (HSE)
used in your application */
#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
/* Exported macro ------------------------------------------------------------*/
#undef assert
#ifdef DEBUG
/*******************************************************************************
* Macro Name : assert
* Description : The assert macro is used for function's parameters check.
* It is used only if the library is compiled in DEBUG mode.
* Input : - expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* Return : None
*******************************************************************************/
#define assert(expr) ((expr) ? (void)0 : assert_failed(__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(u8* file, u32 line);
#else
#define assert(expr) ((void)0)
#endif /* DEBUG */
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32F10x_CONF_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/stm32f10x_conf.h | C | oos | 5,193 |
/* STM32/Arduino types compatibility
* Cfr.: stm32f10x_type.h
*/
#ifndef __STM32_TYPES_COMPAT_H
#define __STM32_TYPES_COMPAT_H
typedef u8 boolean;
typedef u8 byte;
#define false FALSE
#define true TRUE
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/stm32_types_compat.h | C | oos | 230 |
#ifndef LCD_MESSAGE_H
#define LCD_MESSAGE_H
/* The structure passed to the LCD when there is text to display. */
typedef struct
{
long xColumn;
signed char *pcMessage;
} xLCDMessage;
/* The bitmap displayed on the LCD when the LCD task starts. */
const unsigned char pcBitmap[] =
{
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0x01, 0xfc, 0x03, 0x9f, 0x3f, 0xfe, 0x0c, 0x80, 0x03, 0xf8, 0x01, 0x70, 0x80, 0xff, 0x0f, 0xf0, 0xf8, 0xc7,
0x3f, 0x00, 0xff, 0xff, 0xff, 0xff, 0x03, 0x78, 0x00, 0xf8, 0xc0, 0xff, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0x01, 0xf8, 0x01, 0x9e, 0x3f, 0xfe, 0x0c, 0x80, 0x03, 0xf0, 0x01, 0x70, 0x00, 0xfe, 0x0f, 0xe0, 0xf9, 0xe7,
0x3f, 0x00, 0xff, 0xff, 0xff, 0xff, 0x03, 0x70, 0x00, 0x78, 0x80, 0x3f, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xf9, 0xf1, 0x78, 0x3c, 0x9f, 0x7c, 0xce, 0xff, 0xf3, 0xe3, 0xf9, 0x7f, 0x7e, 0xfc, 0xcf, 0xc7, 0xf3, 0xf3,
0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xe3, 0xcf, 0x3f, 0x1e, 0x1f, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xf9, 0x73, 0xfe, 0x39, 0x9f, 0x7c, 0xce, 0xff, 0xf3, 0xe7, 0xf9, 0x7f, 0xfe, 0xfc, 0xcf, 0xcf, 0xe3, 0xf1,
0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xe7, 0xcf, 0x9f, 0x7f, 0x9e, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xf9, 0x33, 0xfe, 0x31, 0x9f, 0x7c, 0xce, 0xff, 0xf3, 0xe7, 0xf9, 0x7f, 0xfe, 0xf9, 0xcf, 0xcf, 0xc7, 0xf8,
0x3f, 0xff, 0x13, 0x0f, 0xff, 0xf0, 0xf3, 0xe7, 0xcf, 0x8f, 0x7f, 0x9c, 0xff, 0xff, 0x87, 0x4f, 0x1c, 0xf2, 0xff, 0xff,
0xff, 0xff, 0xf9, 0x33, 0xff, 0x33, 0x9e, 0x3d, 0xce, 0xff, 0xf3, 0xe3, 0xf9, 0x7f, 0xfe, 0xf9, 0xcf, 0xc7, 0xcf, 0xfc,
0x3f, 0xff, 0x03, 0x03, 0x3c, 0xc0, 0xf3, 0xe3, 0xcf, 0xcf, 0xff, 0x1c, 0xff, 0xff, 0x01, 0x0e, 0x0c, 0xf0, 0xff, 0xff,
0xff, 0xff, 0xf9, 0x31, 0xff, 0x73, 0xce, 0x39, 0x0f, 0xc0, 0x03, 0xf0, 0x01, 0x78, 0xfe, 0xf9, 0x0f, 0xe0, 0x1f, 0xfe,
0x3f, 0x80, 0xe3, 0xf3, 0x3c, 0xcf, 0x03, 0xf0, 0xcf, 0xcf, 0xff, 0x3c, 0xf0, 0xff, 0x79, 0x8e, 0xcf, 0xf1, 0xff, 0xff,
0xff, 0xff, 0x01, 0x38, 0xff, 0x73, 0xce, 0x39, 0x0f, 0xc0, 0x03, 0xf8, 0x01, 0x78, 0xfe, 0xf9, 0x0f, 0xe0, 0x1f, 0xfe,
0x3f, 0x80, 0xf3, 0xf9, 0x99, 0x9f, 0x03, 0xf8, 0xcf, 0xcf, 0xff, 0xfc, 0xc0, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff,
0xff, 0xff, 0x01, 0x3c, 0xff, 0x73, 0xce, 0x39, 0xcf, 0xff, 0xf3, 0xfc, 0xf9, 0x7f, 0xfe, 0xf9, 0xcf, 0xcf, 0x3f, 0xff,
0x3f, 0xff, 0xf3, 0x01, 0x18, 0x80, 0xf3, 0xfc, 0xcf, 0xcf, 0xff, 0xfc, 0x8f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff,
0xff, 0xff, 0xf9, 0x3f, 0xff, 0xf3, 0xe4, 0x93, 0xcf, 0xff, 0xf3, 0xf8, 0xf9, 0x7f, 0xfe, 0xf9, 0xcf, 0x9f, 0x3f, 0xff,
0x3f, 0xff, 0xf3, 0x01, 0x18, 0x80, 0xf3, 0xf8, 0xcf, 0xcf, 0xff, 0xfc, 0x3f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff,
0xff, 0xff, 0xf9, 0x3f, 0xfe, 0xf1, 0xe4, 0x93, 0xcf, 0xff, 0xf3, 0xf9, 0xf9, 0x7f, 0xfe, 0xf9, 0xcf, 0x9f, 0x3f, 0xff,
0x3f, 0xff, 0xf3, 0xf9, 0x9f, 0xff, 0xf3, 0xf9, 0xcf, 0x8f, 0x7f, 0xcc, 0x3f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff,
0xff, 0xff, 0xf9, 0x7f, 0xfe, 0xf9, 0xe4, 0x93, 0xcf, 0xff, 0xf3, 0xf1, 0xf9, 0x7f, 0xfe, 0xfc, 0xcf, 0x9f, 0x3f, 0xff,
0x3f, 0xff, 0xf3, 0xf9, 0x9f, 0xff, 0xf3, 0xf1, 0xcf, 0x9f, 0x7f, 0x8e, 0x3f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff,
0xff, 0xff, 0xf9, 0xff, 0x78, 0xfc, 0xe4, 0x93, 0xcf, 0xff, 0xf3, 0xe3, 0xf9, 0x7f, 0x7e, 0xfc, 0xcf, 0x8f, 0x3f, 0xff,
0x3f, 0xff, 0xf3, 0xf3, 0x38, 0x8f, 0xf3, 0xe3, 0xcf, 0x3f, 0x1e, 0x1f, 0x1f, 0xff, 0x79, 0xce, 0xcf, 0xf1, 0xff, 0xff,
0xff, 0xff, 0xf9, 0xff, 0x01, 0xfe, 0xf1, 0xc7, 0x0f, 0x80, 0xf3, 0xe7, 0x01, 0x70, 0x00, 0xfe, 0x0f, 0xc0, 0x3f, 0xff,
0x3f, 0xff, 0xf3, 0x03, 0x3c, 0xc0, 0xf3, 0xe7, 0xcf, 0x7f, 0x80, 0x3f, 0x80, 0xe7, 0x01, 0xce, 0x0f, 0xf0, 0xff, 0xff,
0xff, 0xff, 0xf9, 0xff, 0x03, 0xff, 0xf1, 0xc7, 0x0f, 0x80, 0xf3, 0xc7, 0x01, 0x70, 0x80, 0xff, 0x0f, 0xe0, 0x3f, 0xff,
0x3f, 0xff, 0xf3, 0x0f, 0xfe, 0xe0, 0xf3, 0xc7, 0xcf, 0xff, 0xc0, 0x7f, 0xe0, 0xe7, 0x87, 0xcf, 0x1f, 0xf2, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe7, 0xf1, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0xf8, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0xfc, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0xff, 0xff, 0xff, 0xff, 0x03,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3,
0xe7, 0xcf, 0x9f, 0x7f, 0x9e, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0x3e, 0x7c, 0x1f, 0xbe, 0xcf, 0x3f, 0xff, 0x13, 0x0f, 0xff, 0xf0, 0xf3,
0xe7, 0xcf, 0x8f, 0x7f, 0x9c, 0xff, 0xff, 0x87, 0x4f, 0x1c, 0xf2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x79, 0x3c, 0x3c, 0x1e, 0x1e, 0xcf, 0x3f, 0xff, 0x03, 0x03, 0x3c, 0xc0, 0xf3,
0xe3, 0xcf, 0xcf, 0xff, 0x1c, 0xff, 0xff, 0x01, 0x0e, 0x0c, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xbc, 0x3d, 0xde, 0x1e, 0xef, 0x3f, 0x80, 0xe3, 0xf3, 0x3c, 0xcf, 0x03,
0xf0, 0xcf, 0xcf, 0xff, 0x3c, 0xf0, 0xff, 0x79, 0x8e, 0xcf, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x73, 0x9d, 0xb9, 0xce, 0x5c, 0xe7, 0x3f, 0x80, 0xf3, 0xf9, 0x99, 0x9f, 0x03,
0xf8, 0xcf, 0xcf, 0xff, 0xfc, 0xc0, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x33, 0x99, 0x99, 0xcc, 0x4c, 0xe6, 0x3f, 0xff, 0xf3, 0x01, 0x18, 0x80, 0xf3,
0xfc, 0xcf, 0xcf, 0xff, 0xfc, 0x8f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xc9, 0x93, 0xe4, 0x49, 0xf2, 0x3f, 0xff, 0xf3, 0x01, 0x18, 0x80, 0xf3,
0xf8, 0xcf, 0xcf, 0xff, 0xfc, 0x3f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xc9, 0x93, 0xe4, 0x49, 0xf2, 0x3f, 0xff, 0xf3, 0xf9, 0x9f, 0xff, 0xf3,
0xf9, 0xcf, 0x8f, 0x7f, 0xcc, 0x3f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xeb, 0xd7, 0xf5, 0xeb, 0xfa, 0x3f, 0xff, 0xf3, 0xf9, 0x9f, 0xff, 0xf3,
0xf1, 0xcf, 0x9f, 0x7f, 0x8e, 0x3f, 0xff, 0xfc, 0xcc, 0xe7, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xe3, 0xc7, 0xf1, 0xe3, 0xf8, 0x3f, 0xff, 0xf3, 0xf3, 0x38, 0x8f, 0xf3,
0xe3, 0xcf, 0x3f, 0x1e, 0x1f, 0x1f, 0xff, 0x79, 0xce, 0xcf, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xe3, 0xc7, 0xf1, 0xe3, 0xf8, 0x3c, 0xff, 0xf3, 0x03, 0x3c, 0xc0, 0xf3,
0xe7, 0xcf, 0x7f, 0x80, 0x3f, 0x80, 0xe7, 0x01, 0xce, 0x0f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xf3, 0xcf, 0xf9, 0xe7, 0xfc, 0x3c, 0xff, 0xf3, 0x0f, 0xfe, 0xe0, 0xf3,
0xc7, 0xcf, 0xff, 0xc0, 0x7f, 0xe0, 0xe7, 0x87, 0xcf, 0x1f, 0xf2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe7, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0xf8, 0xff, 0x3f, 0xfc, 0x7f, 0x00,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0xdf, 0x87, 0xef, 0xc3, 0xf7, 0xf9, 0xe7, 0xff, 0x03, 0x07, 0x1e, 0x7e, 0xfe,
0xfc, 0xf9, 0xf1, 0x8f, 0xf3, 0xff, 0xff, 0xf0, 0x87, 0x4f, 0x18, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xfc, 0xf9, 0xf9, 0x9f, 0xe3, 0xff, 0x3f, 0xe0, 0x01, 0x0e, 0x08, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x8f, 0xb7, 0xc7, 0xdb, 0xe3, 0xfd, 0x0f, 0xfc, 0x7c, 0x9e, 0xe7, 0x79, 0x00,
0xfe, 0xf9, 0xf9, 0x9f, 0x07, 0xfe, 0x3f, 0xc7, 0x79, 0x8e, 0xe3, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xf9, 0xf9, 0x9f, 0x1f, 0xf8, 0x9f, 0xcf, 0xfc, 0xcc, 0xf3, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x73, 0xfe, 0x39, 0xff, 0x9c, 0x9f, 0x1f, 0xf8, 0xc1, 0x9c, 0x1f, 0x7c, 0xfe,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x80,
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x80,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x07, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x07, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x00, 0x30, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0xf0, 0xff, 0xff, 0x0f, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0xf0, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x30, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0xf0, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x30, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0xf0, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x30, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0xf0, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x81,
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0xc0, 0xff, 0xff, 0x1f, 0x78, 0x70, 0xc0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
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0xc0, 0xff, 0xff, 0x1f, 0x38, 0x70, 0xc0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
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0xc0, 0xff, 0xff, 0x1f, 0x38, 0x70, 0xc0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0xf0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x81,
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0xc0, 0xff, 0xff, 0x1f, 0x78, 0x30, 0xf0, 0x1f, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0xf0, 0x1f, 0x00, 0x00, 0xf0, 0x3f, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x00, 0xff, 0xff, 0x80, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0x10, 0x00, 0xf0, 0x1f, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x1f, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0xc0, 0xff, 0x03, 0x00, 0xe0, 0xff, 0xff, 0x8f, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0x00, 0x00, 0xf0, 0x1f, 0x00, 0xe0, 0xff, 0x1f, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff, 0x07, 0x00, 0xc0, 0xff, 0x03, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0x00, 0x00, 0xf0, 0x1f, 0x00, 0xe0, 0xff, 0x1f, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff, 0x07, 0x00, 0xc0, 0xff, 0x03, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0x00, 0x00, 0xf0, 0x1f, 0x00, 0xe0, 0xff, 0x3f, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x0f, 0x00, 0x80, 0xff, 0xff, 0x1f, 0x00, 0x80, 0xff, 0x01, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x03, 0x00, 0xe0, 0xff, 0xff, 0x1f, 0x00, 0x80, 0xff, 0x01, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xfc, 0x1f, 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x03, 0x00, 0xe0, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xfe, 0x01, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xfc, 0x1f, 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x03, 0x00, 0xe0, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xfe, 0x01, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x00, 0x00, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf0, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xfe, 0x01, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x07, 0x80, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf0, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xfe, 0x01, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x07, 0x80, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf0, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xfe, 0x01, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf8, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf8, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0x1f, 0x00, 0x80, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x01, 0x00, 0xfc, 0x03, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0x1f, 0x00, 0x80, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x01, 0x00, 0xfc, 0x03, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x07, 0xf8, 0xff, 0x1f, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x80, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x01, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0x01, 0x70, 0xf8, 0x1f, 0x00, 0xc0, 0xff, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x01, 0x00, 0xfc, 0x0f, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x30, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0xfc, 0x1f, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x30, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
0xff, 0xff, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0xfc, 0x1f, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x7f, 0x00, 0x30, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x03, 0x00, 0xf8,
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0xc0, 0xff, 0xff, 0x07, 0x00, 0x00, 0xf0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0x1f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x81,
0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x80,
0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x80,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf0,
0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0xbe,
0x4d, 0x42, 0x00
};
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/other/LCD_Message.h | C | oos | 58,778 |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : spi_flash.c
* Author : MCD Application Team
* Date First Issued : 02/05/2007
* Description : This file provides a set of functions needed to manage the
* communication between SPI peripheral and SPI M25P64 FLASH.
********************************************************************************
* History:
* 04/02/2007: V0.2
* 02/05/2007: V0.1
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "spi_flash.h"
/* Private typedef -----------------------------------------------------------*/
#define SPI_FLASH_PageSize 256
#define WRITE 0x02 /* Write to Memory instruction */
#define WRSR 0x01 /* Write Status Register instruction */
#define WREN 0x06 /* Write enable instruction */
#define READ 0x03 /* Read from Memory instruction */
#define RDSR 0x05 /* Read Status Register instruction */
#define RDID 0x9F /* Read identification */
#define SE 0xD8 /* Sector Erase instruction */
#define BE 0xC7 /* Bulk Erase instruction */
#define WIP_Flag 0x01 /* Write In Progress (WIP) flag */
#define Dummy_Byte 0xA5
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SPI_FLASH_Init
* Description : Initializes the peripherals used by the SPI FLASH driver.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_Init(void)
{
SPI_InitTypeDef SPI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable SPI1 and GPIOA clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1 | RCC_APB2Periph_GPIOA, ENABLE);
/* Configure SPI1 pins: NSS, SCK, MISO and MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Configure PA.4 as Output push-pull, used as Flash Chip select */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
/* SPI1 configuration */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
SPI_Init(SPI1, &SPI_InitStructure);
/* Enable SPI1 */
SPI_Cmd(SPI1, ENABLE);
}
/*******************************************************************************
* Function Name : SPI_FLASH_SectorErase
* Description : Erases the specified FLASH sector.
* Input : SectorAddr: address of the sector to erase.
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_SectorErase(u32 SectorAddr)
{
/* Send write enable instruction */
SPI_FLASH_WriteEnable();
/* Sector Erase */
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send Sector Erase instruction */
SPI_FLASH_SendByte(SE);
/* Send SectorAddr high nibble address byte */
SPI_FLASH_SendByte((SectorAddr & 0xFF0000) >> 16);
/* Send SectorAddr medium nibble address byte */
SPI_FLASH_SendByte((SectorAddr & 0xFF00) >> 8);
/* Send SectorAddr low nibble address byte */
SPI_FLASH_SendByte(SectorAddr & 0xFF);
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
/* Wait the end of Flash writing */
SPI_FLASH_WaitForWriteEnd();
}
/*******************************************************************************
* Function Name : SPI_FLASH_BulkErase
* Description : Erases the entire FLASH.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_BulkErase(void)
{
/* Send write enable instruction */
SPI_FLASH_WriteEnable();
/* Bulk Erase */
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send Bulk Erase instruction */
SPI_FLASH_SendByte(BE);
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
/* Wait the end of Flash writing */
SPI_FLASH_WaitForWriteEnd();
}
/*******************************************************************************
* Function Name : SPI_FLASH_PageWrite
* Description : Writes more than one byte to the FLASH with a single WRITE
* cycle(Page WRITE sequence). The number of byte can't exceed
* the FLASH page size.
* Input : - pBuffer : pointer to the buffer containing the data to be
* written to the FLASH.
* - WriteAddr : FLASH's internal address to write to.
* - NumByteToWrite : number of bytes to write to the FLASH,
* must be equal or less than "SPI_FLASH_PageSize" value.
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite)
{
/* Enable the write access to the FLASH */
SPI_FLASH_WriteEnable();
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send "Write to Memory " instruction */
SPI_FLASH_SendByte(WRITE);
/* Send WriteAddr high nibble address byte to write to */
SPI_FLASH_SendByte((WriteAddr & 0xFF0000) >> 16);
/* Send WriteAddr medium nibble address byte to write to */
SPI_FLASH_SendByte((WriteAddr & 0xFF00) >> 8);
/* Send WriteAddr low nibble address byte to write to */
SPI_FLASH_SendByte(WriteAddr & 0xFF);
/* while there is data to be written on the FLASH */
while(NumByteToWrite--)
{
/* Send the current byte */
SPI_FLASH_SendByte(*pBuffer);
/* Point on the next byte to be written */
pBuffer++;
}
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
/* Wait the end of Flash writing */
SPI_FLASH_WaitForWriteEnd();
}
/*******************************************************************************
* Function Name : SPI_FLASH_BufferWrite
* Description : Writes block of data to the FLASH. In this function, the
* number of WRITE cycles are reduced, using Page WRITE sequence.
* Input : - pBuffer : pointer to the buffer containing the data to be
* written to the FLASH.
* - WriteAddr : FLASH's internal address to write to.
* - NumByteToWrite : number of bytes to write to the FLASH.
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite)
{
u8 NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0;
Addr = WriteAddr % SPI_FLASH_PageSize;
count = SPI_FLASH_PageSize - Addr;
NumOfPage = NumByteToWrite / SPI_FLASH_PageSize;
NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize;
if(Addr == 0) /* WriteAddr is SPI_FLASH_PageSize aligned */
{
if(NumOfPage == 0) /* NumByteToWrite < SPI_FLASH_PageSize */
{
SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite);
}
else /* NumByteToWrite > SPI_FLASH_PageSize */
{
while(NumOfPage--)
{
SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize);
WriteAddr += SPI_FLASH_PageSize;
pBuffer += SPI_FLASH_PageSize;
}
SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle);
}
}
else /* WriteAddr is not SPI_FLASH_PageSize aligned */
{
if(NumOfPage== 0) /* NumByteToWrite < SPI_FLASH_PageSize */
{
if(NumOfSingle > count) /* (NumByteToWrite + WriteAddr) > SPI_FLASH_PageSize */
{
temp = NumOfSingle - count;
SPI_FLASH_PageWrite(pBuffer, WriteAddr, count);
WriteAddr += count;
pBuffer += count;
SPI_FLASH_PageWrite(pBuffer, WriteAddr, temp);
}
else
{
SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite);
}
}
else /* NumByteToWrite > SPI_FLASH_PageSize */
{
NumByteToWrite -= count;
NumOfPage = NumByteToWrite / SPI_FLASH_PageSize;
NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize;
SPI_FLASH_PageWrite(pBuffer, WriteAddr, count);
WriteAddr += count;
pBuffer += count;
while(NumOfPage--)
{
SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize);
WriteAddr += SPI_FLASH_PageSize;
pBuffer += SPI_FLASH_PageSize;
}
if(NumOfSingle != 0)
{
SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle);
}
}
}
}
/*******************************************************************************
* Function Name : SPI_FLASH_BufferRead
* Description : Reads a block of data from the FLASH.
* Input : - pBuffer : pointer to the buffer that receives the data read
* from the FLASH.
* - ReadAddr : FLASH's internal address to read from.
* - NumByteToRead : number of bytes to read from the FLASH.
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead)
{
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send "Read from Memory " instruction */
SPI_FLASH_SendByte(READ);
/* Send ReadAddr high nibble address byte to read from */
SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
/* Send ReadAddr medium nibble address byte to read from */
SPI_FLASH_SendByte((ReadAddr& 0xFF00) >> 8);
/* Send ReadAddr low nibble address byte to read from */
SPI_FLASH_SendByte(ReadAddr & 0xFF);
while(NumByteToRead--) /* while there is data to be read */
{
/* Read a byte from the FLASH */
*pBuffer = SPI_FLASH_SendByte(Dummy_Byte);
/* Point to the next location where the byte read will be saved */
pBuffer++;
}
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
}
/*******************************************************************************
* Function Name : SPI_FLASH_ReadID
* Description : Reads FLASH identification.
* Input : None
* Output : None
* Return : FLASH identification
*******************************************************************************/
u32 SPI_FLASH_ReadID(void)
{
u32 Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0;
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send "RDID " instruction */
SPI_FLASH_SendByte(0x9F);
/* Read a byte from the FLASH */
Temp0 = SPI_FLASH_SendByte(Dummy_Byte);
/* Read a byte from the FLASH */
Temp1 = SPI_FLASH_SendByte(Dummy_Byte);
/* Read a byte from the FLASH */
Temp2 = SPI_FLASH_SendByte(Dummy_Byte);
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2;
return Temp;
}
/*******************************************************************************
* Function Name : SPI_FLASH_StartReadSequence
* Description : Initiates a read data byte (READ) sequence from the Flash.
* This is done by driving the /CS line low to select the device,
* then the READ instruction is transmitted followed by 3 bytes
* address. This function exit and keep the /CS line low, so the
* Flash still being selected. With this technique the whole
* content of the Flash is read with a single READ instruction.
* Input : - ReadAddr : FLASH's internal address to read from.
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_StartReadSequence(u32 ReadAddr)
{
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send "Read from Memory " instruction */
SPI_FLASH_SendByte(READ);
/* Send the 24-bit address of the address to read from -----------------------*/
/* Send ReadAddr high nibble address byte */
SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
/* Send ReadAddr medium nibble address byte */
SPI_FLASH_SendByte((ReadAddr& 0xFF00) >> 8);
/* Send ReadAddr low nibble address byte */
SPI_FLASH_SendByte(ReadAddr & 0xFF);
}
/*******************************************************************************
* Function Name : SPI_FLASH_ReadByte
* Description : Reads a byte from the SPI Flash.
* This function must be used only if the Start_Read_Sequence
* function has been previously called.
* Input : None
* Output : None
* Return : Byte Read from the SPI Flash.
*******************************************************************************/
u8 SPI_FLASH_ReadByte(void)
{
return (SPI_FLASH_SendByte(Dummy_Byte));
}
/*******************************************************************************
* Function Name : SPI_FLASH_ChipSelect
* Description : Selects or deselects the FLASH.
* Input : State : level to be applied on the FLASH's ChipSelect pin.
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_ChipSelect(u8 State)
{
/* Set High or low the chip select line on PA.4 pin */
GPIO_WriteBit(GPIOA, GPIO_Pin_4, (BitAction)State);
}
/*******************************************************************************
* Function Name : SPI_FLASH_SendByte
* Description : Sends a byte through the SPI interface and return the byte
* received from the SPI bus.
* Input : byte : byte to send.
* Output : None
* Return : The value of the received byte.
*******************************************************************************/
u8 SPI_FLASH_SendByte(u8 byte)
{
/* Loop while DR register in not emplty */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET);
/* Send byte through the SPI1 peripheral */
SPI_SendData(SPI1, byte);
/* Wait to receive a byte */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE) == RESET);
/* Return the byte read from the SPI bus */
return SPI_ReceiveData(SPI1);
}
/*******************************************************************************
* Function Name : SPI_FLASH_SendHalfWord
* Description : Sends a Half Word through the SPI interface and return the
* Half Word received from the SPI bus.
* Input : Half Word : Half Word to send.
* Output : None
* Return : The value of the received Half Word.
*******************************************************************************/
u16 SPI_FLASH_SendHalfWord(u16 HalfWord)
{
/* Loop while DR register in not emplty */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET);
/* Send Half Word through the SPI1 peripheral */
SPI_SendData(SPI1, HalfWord);
/* Wait to receive a Half Word */
while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE) == RESET);
/* Return the Half Word read from the SPI bus */
return SPI_ReceiveData(SPI1);
}
/*******************************************************************************
* Function Name : SPI_FLASH_WriteEnable
* Description : Enables the write access to the FLASH.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_WriteEnable(void)
{
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send "Write Enable" instruction */
SPI_FLASH_SendByte(WREN);
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
}
/*******************************************************************************
* Function Name : SPI_FLASH_WaitForWriteEnd
* Description : Polls the status of the Write In Progress (WIP) flag in the
* FLASH's status register and loop until write opertaion
* has completed.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI_FLASH_WaitForWriteEnd(void)
{
u8 FLASH_Status = 0;
/* Select the FLASH: Chip Select low */
SPI_FLASH_ChipSelect(Low);
/* Send "Read Status Register" instruction */
SPI_FLASH_SendByte(RDSR);
/* Loop as long as the memory is busy with a write cycle */
do
{
/* Send a dummy byte to generate the clock needed by the FLASH
and put the value of the status register in FLASH_Status variable */
FLASH_Status = SPI_FLASH_SendByte(Dummy_Byte);
} while((FLASH_Status & WIP_Flag) == SET); /* Write in progress */
/* Deselect the FLASH: Chip Select high */
SPI_FLASH_ChipSelect(High);
}
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/other/spi_flash.c | C | oos | 19,371 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* High speed timer test as described in main.c. */
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Library includes. */
#include "stm32f10x_lib.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_map.h"
/* The set frequency of the interrupt. Deviations from this are measured as
the jitter. */
#define timerINTERRUPT_FREQUENCY ( ( unsigned portSHORT ) 20000 )
/* The expected time between each of the timer interrupts - if the jitter was
zero. */
#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )
/* The highest available interrupt priority. */
#define timerHIGHEST_PRIORITY ( 0 )
/* Misc defines. */
#define timerMAX_32BIT_VALUE ( 0xffffffffUL )
#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )
/* The number of interrupts to pass before we start looking at the jitter. */
#define timerSETTLE_TIME 5
/*-----------------------------------------------------------*/
/*
* Configures the two timers used to perform the test.
*/
void vSetupTimerTest( void );
/* Interrupt handler in which the jitter is measured. */
void vTimer2IntHandler( void );
/* Stores the value of the maximum recorded jitter between interrupts. */
volatile unsigned portSHORT usMaxJitter = 0;
/*-----------------------------------------------------------*/
void vSetupTimerTest( void )
{
unsigned long ulFrequency;
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
NVIC_InitTypeDef NVIC_InitStructure;
/* Enable timer clocks */
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE );
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM3, ENABLE );
/* Initialise data. */
TIM_DeInit( TIM2 );
TIM_DeInit( TIM3 );
TIM_TimeBaseStructInit( &TIM_TimeBaseStructure );
/* Time base configuration for timer 2 - which generates the interrupts. */
ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY;
TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) ( ulFrequency & 0xffffUL );
TIM_TimeBaseStructure.TIM_Prescaler = 0x0;
TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit( TIM2, &TIM_TimeBaseStructure );
TIM_ARRPreloadConfig( TIM2, ENABLE );
/* Configuration for timer 3 which is used as a high resolution time
measurement. */
TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) 0xffff;
TIM_TimeBaseInit( TIM3, &TIM_TimeBaseStructure );
TIM_ARRPreloadConfig( TIM3, ENABLE );
/* Enable TIM2 IT. TIM3 does not generate an interrupt. */
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = timerHIGHEST_PRIORITY;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init( &NVIC_InitStructure );
TIM_ITConfig( TIM2, TIM_IT_Update, ENABLE );
/* Finally, enable both timers. */
TIM_Cmd( TIM2, ENABLE );
TIM_Cmd( TIM3, ENABLE );
}
/*-----------------------------------------------------------*/
void vTimer2IntHandler( void )
{
static unsigned portSHORT usLastCount = 0, usSettleCount = 0, usMaxDifference = 0;
unsigned portSHORT usThisCount, usDifference;
/* Capture the free running timer 3 value as we enter the interrupt. */
usThisCount = TIM3->CNT;
if( usSettleCount >= timerSETTLE_TIME )
{
/* What is the difference between the timer value in this interrupt
and the value from the last interrupt. */
usDifference = usThisCount - usLastCount;
/* Store the difference in the timer values if it is larger than the
currently stored largest value. The difference over and above the
expected difference will give the 'jitter' in the processing of these
interrupts. */
if( usDifference > usMaxDifference )
{
usMaxDifference = usDifference;
usMaxJitter = usMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;
}
}
else
{
/* Don't bother storing any values for the first couple of
interrupts. */
usSettleCount++;
}
/* Remember what the timer value was this time through, so we can calculate
the difference the next time through. */
usLastCount = usThisCount;
TIM_ClearITPendingBit( TIM2, TIM_IT_Update );
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/iNEMO_task/other/timertest.c | C | oos | 7,252 |
#ifndef __COM_MANAGER_H
#define __COM_MANAGER_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32f10x_map.h"
#include "iNEMO_lib.h"
#include "string.h"
#include "FreeRTOS.h"
#include "task.h"
#define FRAME_SIZE 64
/**
* FRAME_CONTROL_DEFINE
*
*/
#define CTRL_type 0x00 /*!< control frame */
#define DATA_type 0x40 /*!< data frame */
#define ACK_type 0x80 /*!< Ack frame */
#define NACK_type 0xC0 /*!< NACK frame */
#define ACK_req 0x20 /*!< Ack required */
#define ACK_NOTreq 0x00 /*!< NACK required */
#define Last_Frag 0x00 /*!< Last Fragment */
#define More_Frag 0x10 /*!< More Fragment */
#define Version_1 0x00 /*!< Frame Version */
#define QoS_Normal 0x00 /*!< Data no Ack Last Fragment */
#define Qos_Medium 0x01 /*!< Data with Ack More Fragment */
#define QoS_High 0x02 /*!< Ack no payload */
#define Ctrl_Check(type,ack,frag,vers,QoS) (type | ack | frag | vers | QoS) /*!< macro to build control byte */
#define CTRL_wACK_LF Ctrl_Check(CTRL_type, ACK_req ,Last_Frag ,Version_1 ,QoS_Normal) /*!< macro to build control frame with ack , last fragment */
#define CTRL_noACK_LF Ctrl_Check(CTRL_type, ACK_NOTreq ,Last_Frag ,Version_1 ,QoS_Normal) /*!< macro to build control frame without ack , last fragment */
#define DATA Ctrl_Check(DATA_type, ACK_NOTreq ,Last_Frag ,Version_1 ,QoS_Normal) /*!< macro to build data frame with ack , last fragment */
#define ACK Ctrl_Check(ACK_type, ACK_NOTreq, Last_Frag ,Version_1 ,QoS_Normal) /*!< macro to build Ack frame */
#define NACK Ctrl_Check(NACK_type, ACK_NOTreq ,Last_Frag ,Version_1 ,QoS_Normal) /*!< macro to build NACK frame with ack */
#define TRACE Ctrl_Check(DATA_type, ACK_NOTreq ,Last_Frag ,Version_1 ,Qos_Medium) /*!< macro to build data frame with ack , last fragment, QOS Medium */
/* end of group FRAME_CONTROL_DEFINE */
/**
* ERROR_CODE
*
*/
#define CmdUnsupported 0x01
#define ValueOutOfRange 0x02
#define NotExecutable 0x03
#define WrongSyntax 0x04
#define iNEMONotConnected 0x05
/* end of group ERROR_CODE */
/**
* MESSAGE_ID
*
*/
/**
* COMMUNICATION_CONTROL_FRAME
*
*/
#define iNEMO_Connect 0x00
#define iNEMO_Disconnect 0x01
#define iNEMO_Reset_Board 0x02
#define iNEMO_Enter_DFU_Mode 0x03
#define iNEMO_Trace 0x07
#define iNEMO_Led 0x08
/* end of group COMMUNICATION_CONTROL_FRAME */
/**
* BOARD_INFO_FRAME
*
*/
#define iNEMO_Get_Device_Mode 0x10
#define iNEMO_Get_MCU_ID 0x12
#define iNEMO_Get_FW_Version 0x13
#define iNEMO_Get_HW_Version 0x14
#define iNEMO_Identify 0x15
#define iNEMO_Get_AHRS_Library 0x17
#define iNEMO_Get_Libraries 0x18
/* end of group BOARD_INFO_FRAME */
/**
* SENSOR_SETTING_FRAME
*
*/
#define iNEMO_Set_Sensor_Parameter 0x20
#define iNEMO_Get_Sensor_Parameter 0x21
#define iNEMO_Restore_Default_Parameter 0x22
/* end of group SENSOR_SETTING_FRAME */
/**
* ACQUISITION_SENSOR_DATA_FRAME
*
*/
#define iNEMO_SetOutMode 0x50
#define iNEMO_GetOutMode 0x51
#define iNEMO_Start_Acquisition 0x52
#define iNEMO_Stop_Acquisition 0x53
/* end of group ACQUISITION_SENSOR_DATA_FRAME */
/* end of group MESSAGE_ID */
// FREQUENCY ACQUISITION VALUES
#define LOW_FREQUENCY 0x00 /*!< 1 HZ frequency acquisition */
#define MEDIUM_FREQUENCY_1 0x01 /*!< 10 HZ frequency acquisition */
#define MEDIUM_FREQUENCY_2 0x02 /*!< 25 HZ frequency acquisition */
#define HIGH_FREQUENCY 0x03 /*!< 50 HZ frequency acquisition */
// FRAME TYPE for PC
/**
* FW_HW_Version
*
*/
#define iNEMO_FIRMWARE_VERSION "iNEMO Firmware_Version_2.2"
#define SIZE_FWversion strlen(iNEMO_FIRMWARE_VERSION)
#define iNEMO_HARDWARE_VERSION "iNEMO V2 Hardware_Version_1"
#define SIZE_HWversion strlen(iNEMO_HARDWARE_VERSION)
/* end of group FW_HW_Version */
/**
* Libraries_Version
*
*/ /*
#ifdef AHRS_MOD
#define iNEMO_AHRS_VERSION "iNEMO AHRS ENABLE V1.2.0"
#define iNEMO_AHRS_LIBRARY 0x01
#else
#define iNEMO_AHRS_VERSION "iNEMO AHRS NOT AVAILABLE"
#define iNEMO_AHRS_LIBRARY 0x00
#endif
#define SIZE_AHRSlibrary strlen(iNEMO_AHRS_VERSION)
#ifdef COMPASS_MOD
#define iNEMO_COMPASS_LIBRARY 0x02
#else
#define iNEMO_COMPASS_LIBRARY 0x00
#endif
#ifdef ALTIMETER_MOD
#define iNEMO_ALTIMETER_LIBRARY 0x04
#else
#define iNEMO_ALTIMETER_LIBRARY 0x00
#endif
#ifdef TRACE_MOD
#define iNEMO_TRACE_LIBRARY 0x08
#else
#define iNEMO_TRACE_LIBRARY 0x00
#endif
#ifdef FAT_MOD
#define iNEMO_FAT_LIBRARY 0x10
#else
#define iNEMO_FAT_LIBRARY 0x00
#endif
#define AVAILABLE_LIBRARIES (iNEMO_AHRS_LIBRARY | iNEMO_COMPASS_LIBRARY | \
iNEMO_ALTIMETER_LIBRARY | iNEMO_TRACE_LIBRARY |\
iNEMO_FAT_LIBRARY)*/ /*!< macro to build available libraries */
/* end of group Libraries_Version */
struct receivedMsg{
int length;
u8 msg[FRAME_SIZE];
};
void Send_Ack(unsigned char frame, u8 length, u8* payload);
void Send_Nack(unsigned char frame, u8 error_code);
void Send_Data(unsigned char frame, u8 length, u8* payload);
void Set_Timer(unsigned char number);
void ParseCommandFrame(u32 nFrameSize, u8* buffer_rx, iNEMO_DATA * pdata);
void DataProcess(u8 outmode, iNEMO_DATA *pData);
void SetAhrs(bool bEnable);
void SetRawData(bool bEnable);
bool GetAhrs();
bool GetRawData();
void SetOutMode(u8 outmode);
u8 GetOutMode();
static void Enable_Timer(FunctionalState command);
#endif /*__COM_MANAGER_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/CommunicationManager/comManager.h | C | oos | 6,021 |
#include "comManager.h"
#include "string.h"
#include "utils.h"
#include "iNEMO_util.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_nvic.h"
#include <AndroidAccessory.h>
/**
* Specifies the incremental counter for the data frames sent to the device.
*/
static u16 s_iC = 0;
/**
* Number of sample to be acquired
*/
static u16 s_nLengthSample = 0;
/**
* Specifies which output data are enabled
* Details: 0 Disable/1 Enable order bit :AHRS | RFU 0 | Cal/Raw | Accelerometer | Gyro | Magnetometer | Pressure | Temperature
* * Cal/Raw 0-> Calibrated data
* 1-> Raw data [lsb]
* 0x1F --> all sensors enabled
* 0x11 --> only temperature and accelerometer sensors enabled
*/
static u8 s_uOutSelect = 0x11;
/**
* Specifies comunicatin frequency and output channel
* Details :RFU 0 | RFU 0 | FQ2 | FQ1 | FQ0 | OT2 | OT1 | OT0
* FQ : 000 (1Hz); 001 (10Hz); 010 (25Hz); 011 (50Hz)
* OT : 000 (USB output)
*/
static u8 s_uOutMode=0;
/**
* Specifies if the iNEMO is connected
*/
static bool s_bConnectState=FALSE;
/**
* Sensor sampling frequency
*/
static u8 s_uTimerFrequence=0x03;
/**
* Specifies if the sensor data have to be filtered using AHRS.
*/
static bool s_bAhrsEnabled = FALSE;
/**
* Specifies if the raw sensor data sending is enabled.
*/
static bool s_bRawDataEnabled = FALSE;
/**
* Process a command coming from the device (through ADK connection). All supported command are:
* iNEMO_Connect - this must be the first command to send to the board. Others command are
* not processed before this one.
* iNEMO_Disconnect
* iNEMO_Reset_Board
* iNEMO_Enter_DFU_Mode
* iNEMO_Led_Control
* iNEMO_Get_Device_Mode
* iNEMO_Get_MCU_ID
* iNEMO_Get_FW_Version
* iNEMO_Get_HW_Version
* iNEMO_Get_Identify
* iNEMO_Get_AHRS_Library
* iNEMO_Get_Libraries
* iNEMO_SetOutMode
* iNEMO_GetOutMode
* iNEMO_Set_Sensor_Parameter
* iNEMO_Get_Sensor_Parameter
* iNEMO_Restore_Default_Parameter
* iNEMO_Start_Acquisition - start the the transmission of sensor data according to the
* parameters specified in frame payload.
* iNEMO_Stop_Acquisition - stop the transmission of sensor data.
* Invalid frame are dropped.
*
* Parameters:
* nFrameSize specifies the size of the received frame.
* buffer_rx is the frame to be processed.
* pdata contains the sensor parameters settings.
*/
void ParseCommandFrame(u32 nFrameSize, u8* buffer_rx, iNEMO_DATA * pdata) {
/** Check if the iNEMO is connect, if it is disconnected the only accepted command is iNEMO_Connect */
if(s_bConnectState == FALSE )
{
/* if the command is iNEMO_Connect Parse the frame */
if(buffer_rx[2]== iNEMO_Connect)
{
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2)
{
/* iNEMO_Connet_Response --> Change iNEMO Stauts to Connceted and Send Ack*/
s_bConnectState=TRUE;
Send_Ack(iNEMO_Connect,1,0x00);
}
else
{
/* wrong syntax */
Send_Nack(iNEMO_Connect,WrongSyntax);
}
}
else /* the command is not iNEMO_Connect */
{
Send_Nack((char)buffer_rx[2], iNEMONotConnected);
}
}
else /* if iNEMO is connected the other command can be executed */
{
/* Switch the command */
switch (buffer_rx[2]){
/* Connection Request*/
case iNEMO_Connect:
/* syntactic check :
Frame Control -> Control frame; Ach required; Last fragment ; version 1; Normal Priority
Lenght -> 1 (No payload)
nFrameSize --> check if the payload lenght is correct
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2)
{
/* iNEMO_Connet_Response --> Change iNEMO Stauts to Connceted and Send Ack*/
s_bConnectState=TRUE;
Send_Ack(iNEMO_Connect,1,0x00);
}
else
{
Send_Nack(iNEMO_Connect,WrongSyntax);
}
break;
/* Disconnect Request*/
case iNEMO_Disconnect:
/* syntactic check :
Frame Control -> Control frame; Ach required; Last fragment ; version 1; Normal Priority
Lenght -> 1 (No payload)
nFrameSize --> check il the payload lenght is correct
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2)
{
/* iNEMO_Connet_Response --> Change iNEMO Stauts to Disconnceted and Send Ack */
s_bConnectState=FALSE;
Send_Ack(iNEMO_Disconnect,1,0x00);
}
else
Send_Nack(iNEMO_Disconnect,WrongSyntax);
break;
/* iNEMO_Get_MCU_ID Request */
case iNEMO_Get_MCU_ID:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> 1
nFrameSize --> check il the payload lenght is correct
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2 )
{
unsigned char mcu_id[12];
int i = 0;
for (i=0; i<12; ++i)
mcu_id[i] = MCU_ID[12-(i+1)];
/* send ack with payload= STM32 Unique indetifier */
Send_Ack(iNEMO_Get_MCU_ID, 13, mcu_id);
}
else
Send_Nack(iNEMO_Get_MCU_ID,WrongSyntax);
break;
/* iNEMO Get FW Version Request */
case iNEMO_Get_FW_Version:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> 1
nFrameSize --> check il the payload lenght is correct
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2 )
{
/* send ack with payload= string FW version*/
Send_Ack(iNEMO_Get_FW_Version, (SIZE_FWversion + 1), iNEMO_FIRMWARE_VERSION);
}
else
Send_Nack(iNEMO_Get_FW_Version,WrongSyntax);
break;
/* iNEMO Get HW Version Request : */
case iNEMO_Get_HW_Version:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> 1
nFrameSize --> check il the payload lenght is correct
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2 )
{
/* send ack with payload= string HW version*/
Send_Ack(iNEMO_Get_HW_Version, (SIZE_HWversion + 1), iNEMO_HARDWARE_VERSION);
}
else
Send_Nack(iNEMO_Get_HW_Version,WrongSyntax);
break;
/*------ Sensor Setting parameter---------- */
/* Set parameter */
case iNEMO_Set_Sensor_Parameter:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> variable
nFrameSize --> check il the payload lenght is correct
buffer_rx[1] --> Payload Lenght +1
buffer_rx[3] --> Sensor Type
buffer_rx[4] --> Sensor Parameter
buffer_rx[5] --> New value to set (if any)
*/
if(buffer_rx[0]==CTRL_wACK_LF && nFrameSize== buffer_rx[1]+2)
{
if(iNEMO_Set_Sensor(pdata, buffer_rx[3], buffer_rx[4], (buffer_rx[1] - 2), &buffer_rx[5]))
{
Send_Ack(iNEMO_Set_Sensor_Parameter, 1, 0x00);
}
else
/* else send nack */
Send_Nack(iNEMO_Set_Sensor_Parameter,NotExecutable);
}
else
Send_Nack(iNEMO_Set_Sensor_Parameter,WrongSyntax);
break;
/* Get parameter */
case iNEMO_Get_Sensor_Parameter:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> variable
nFrameSize --> check il the payload lenght is correct
buffer_rx[1] --> Payload Lenght +1
buffer_rx[3] --> Sensor Type
buffer_rx[4] --> Sensor Parameter
*/
if(buffer_rx[0]==CTRL_wACK_LF && nFrameSize== buffer_rx[1]+2)
{
u8 value[10];
if(iNEMO_Get_Sensor_Param(pdata, buffer_rx[3], buffer_rx[4], value))
Send_Ack(iNEMO_Get_Sensor_Parameter, value[0]+1, &value[1]);
else
/* else send nack */
Send_Nack(iNEMO_Get_Sensor_Parameter,NotExecutable);
}
else
Send_Nack(iNEMO_Get_Sensor_Parameter,WrongSyntax);
break;
/* Restore Default Parameter */
case iNEMO_Restore_Default_Parameter:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> variable
nFrameSize --> check il the payload lenght is correct
buffer_rx[1] --> Payload Lenght +1
buffer_rx[3] --> Sensor Type
buffer_rx[4] --> Sensor Parameter
*/
if(buffer_rx[0]==CTRL_wACK_LF && nFrameSize== buffer_rx[1]+2)
{
u8 value[10];
if(iNEMO_Restore_DefaultParam(pdata, buffer_rx[3], buffer_rx[4], value))
Send_Ack(iNEMO_Restore_Default_Parameter, value[0]+1, &value[1]);
else
/* else send nack */
Send_Nack(iNEMO_Restore_Default_Parameter,NotExecutable);
}
else
Send_Nack(iNEMO_Restore_Default_Parameter,WrongSyntax);
break;
/*-------Acquisition Command--------------- */
/* Configure iNEMO output settings*/
case iNEMO_SetOutMode:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> 5
nFrameSize --> check il the payload lenght is correct
buffer_rx[3] --> Enable setting 1 Enable/0 Disable AHRS |RFU 0 | Cal/Raw | Acc | Gyro | Mag | Press | temp |
buffer_rx[4] --> Acquition Frequency + output type : 00 FQ2 FQ1 FQ0 OT2 OT1 OT0
buffer_rx[5] --> Number of Samples (MSB)
buffer_rx[6] --> Number of Samples (LSB)
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==5 && nFrameSize== buffer_rx[1]+2 && ((buffer_rx[4] & 0xC0)==0x00))
{
#ifndef AHRS_MOD /* The AHRS Library is not available */
if(buffer_rx[3] & 0x80)
Send_Nack(iNEMO_SetOutMode,NotExecutable);
else
{
SetRawData(buffer_rx[3] & 0x20 ? TRUE : FALSE);
s_uOutSelect=buffer_rx[3];
s_uTimerFrequence = (buffer_rx[4] & 0x38) >> 3;
s_uOutMode =(buffer_rx[4] & 0x03);
if((s_uTimerFrequence>6) || (s_uOutMode>0))
{
Send_Nack(iNEMO_SetOutMode,ValueOutOfRange);
}
else
{
/* set timer */
Set_Timer(s_uTimerFrequence);
/* set number of sample or continuos mode (s_nLengthSample=0) */
s_nLengthSample = ((u16)buffer_rx[5] << 8) + buffer_rx[6];
Send_Ack(iNEMO_SetOutMode, 1, 0x00);
}
}
#else /* The AHRS Library is available */
SetAhrs(buffer_rx[3] & 0x80 ? TRUE : FALSE);
SetRawData(buffer_rx[3] & 0x20 ? TRUE : FALSE);
s_uOutSelect=buffer_rx[3];
if(GetAhrs())
s_uTimerFrequence = 0x03;
else
s_uTimerFrequence = (buffer_rx[4] & 0x38) >> 3;
s_uOutMode =(buffer_rx[4] & 0x03);
if((s_uTimerFrequence>7) || (s_uOutMode>0))
{
Send_Nack(iNEMO_SetOutMode,ValueOutOfRange);
}
else
{
/* set timer */
Set_Timer(s_uTimerFrequence);
/* set number of sample or continuos mode (s_nLengthSample=0) */
s_nLengthSample = ((u16)buffer_rx[5] << 8) + buffer_rx[6];
/*Select output destination*/
Send_Ack(iNEMO_SetOutMode, 1, 0x00);
}
#endif /*AHRS_MOD*/
}
else
Send_Nack(iNEMO_SetOutMode,WrongSyntax);
break;
/* Get iNEMO output settings*/
case iNEMO_GetOutMode:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> 1
nFrameSize --> check il the payload lenght is correct
Ack response
buffer_rx[3] --> Enable setting 1 Enable/0 Disable AHRS |RFU 0 | Cal/Raw | Acc | Gyro | Mag | Press | Temp |
buffer_rx[4] --> Acquition Frequency + output type : 00 FQ2 FQ1 FQ0 OT2 OT1 OT0
buffer_rx[5] --> Number of Samples (MSB)
buffer_rx[6] --> Number of Samples (LSB)
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2 )
{
u8 temp[4];
temp[0]=s_uOutSelect;
temp[1]=((s_uTimerFrequence ) << 3) + (s_uOutMode & 0x07);
temp[2]=(u8)(s_nLengthSample >> 8);
temp[3]=(u8)s_nLengthSample;
Send_Ack(iNEMO_GetOutMode, 5, temp);
}
else
Send_Nack(iNEMO_GetOutMode,WrongSyntax);
break;
/* start iNEMO acquisition data*/
case iNEMO_Start_Acquisition:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> 1
nFrameSize --> check il the payload lenght is correct
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2)
{
s_iC=0;
Send_Ack(iNEMO_Start_Acquisition, 1, 0x00);
Enable_Timer(ENABLE);
}
else
Send_Nack(iNEMO_Start_Acquisition,WrongSyntax);
break;
/* start iNEMO acquisition data*/
case iNEMO_Stop_Acquisition:
/* syntactic check :
Frame Control -> Control frame; Ack required; Last fragment ; version 1; Normal Priority
Lenght -> 1
nFrameSize --> check il the payload lenght is correct
*/
if(buffer_rx[0]==CTRL_wACK_LF && buffer_rx[1]==1 && nFrameSize== buffer_rx[1]+2)
{
Enable_Timer(DISABLE);
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
s_iC=0;
Send_Ack(iNEMO_Stop_Acquisition, 1, 0x00);
}
else
Send_Nack(iNEMO_Stop_Acquisition,WrongSyntax);
break;
default:
Send_Nack(buffer_rx[2],CmdUnsupported);
break;
}
}
}
/**
* Send a frame containing all sensor data and orientation data according to the transmission option specified by the CMD_START command.
*/
void DataProcess(u8 outmode, iNEMO_DATA *pData)
{
u8 nByteToSend=0;
u8 databuffer[60]= {0};
if ((s_iC < s_nLengthSample) || (s_nLengthSample ==0))
{
/* if AHRS is ENABLED*/
if (GetAhrs())
{
#ifdef _GYRO_RPY
//float roll, pitch, yaw;
LPRYxxxAL_Read_RawRate(pData->sGyro);
LSM303DLH_Acc_Read_RawData(pData->sAcc);
LSM303DLH_Magn_Read_RawData(pData->sMag);
#endif
/* if accelerometer output is requested */
if(outmode & 0x10)
{
/*if raw data enabled*/
if(GetRawData())
{
s16_to_u8_buffer(&(pData->sAcc[0]), &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&(pData->sAcc[1]), &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&(pData->sAcc[2]), &databuffer[nByteToSend + 6]);
}
/* Calibrated data are requested*/
else
{
s16 acc[3];
acc[0]=(s16)(pData->sAcc[0]/pData->uGain[0]) - pData->sOffset[0];
acc[1]=(s16)(pData->sAcc[1]/pData->uGain[1]) - pData->sOffset[1];
acc[2]=(s16)(pData->sAcc[2]/pData->uGain[2]) - pData->sOffset[2];
s16_to_u8_buffer(&acc[0], &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&acc[1], &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&acc[2], &databuffer[nByteToSend + 6]);
}
nByteToSend+=6;
}/* End of Accelerometer Data*/
#ifdef _GYRO_RPY
/* if gyroscopes output is requested */
if(outmode & 0x08)
{
/*if raw data enabled*/
if(GetRawData())
{
s16_to_u8_buffer(&(pData->sGyro[0]), &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&(pData->sGyro[1]), &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&(pData->sGyro[2]), &databuffer[nByteToSend + 6]);
}
/* Calibrated data are requested*/
else
{
s16 dps[3];
dps[0]=(s16)((pData->sGyro[0]/pData->uGain[3]) - pData->sOffset[3]);
dps[1]=(s16)((pData->sGyro[1]/pData->uGain[4]) - pData->sOffset[4]);
dps[2]=(s16)((pData->sGyro[2]/pData->uGain[5]) - pData->sOffset[5]);
s16_to_u8_buffer(&dps[0], &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&dps[1], &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&dps[2], &databuffer[nByteToSend + 6]);
}
nByteToSend+=6;
}/* End of Gyroscope Data */
/* if magnetometer output is requested */
if(outmode & 0x04)
{
/*if raw data enabled*/
if(GetRawData())
{
s16_to_u8_buffer(&(pData->sMag[0]), &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&(pData->sMag[1]), &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&(pData->sMag[2]), &databuffer[nByteToSend + 6]);
}
/* Calibrated data are requested*/
else
{
s16 gauss[3];
gauss[0]=(s16)(pData->sMag[0]*1000/pData->uGain[6]) - pData->sOffset[6];
gauss[1]=(s16)(pData->sMag[1]*1000/pData->uGain[7]) - pData->sOffset[7];
gauss[2]=(s16)(pData->sMag[2]*1000/pData->uGain[8]) - pData->sOffset[8];
s16_to_u8_buffer(&gauss[0], &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&gauss[1], &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&gauss[2], &databuffer[nByteToSend + 6]);
}
nByteToSend+=6;
} /* End of Magnetometer Data */
#endif
#ifdef _PRESS
/* if pressure output is requested */
if(outmode & 0x02)
{
LPS001DL_Get_Raw_Pressure(&(pData->uPress));
/*if raw data enabled*/
if(GetRawData())
{
u16_to_u8_buffer(&(pData->uPress), &databuffer[nByteToSend + 2]);
}
/* Calibrated data are requested*/
else
{
u16 p;
p=(s16)((pData->uPress/pData->uGain[9]) - pData->sOffset[9]);
u16_to_u8_buffer(&p, &databuffer[nByteToSend + 2]);
}
nByteToSend+=2;
} /* End of Pressure Sensor Data */
#endif
/* if temperature output is requested */
if(outmode & 0x01)
{
/*if raw data enabled*/
if(GetRawData())
{
STLM75_Read_Raw_Data(&(pData->sTemp));
s16_to_u8_buffer(&(pData->sTemp),&databuffer[nByteToSend + 2]);
}
/* Calibrated data are requested*/
else
{
s16 p;
STLM75_Read_Temperature_Signed(&(pData->sTemp));
p=(s16)(pData->sTemp - pData->sOffset[10]);
s16_to_u8_buffer(&p, &databuffer[nByteToSend + 2]);
}
nByteToSend+=2;
} /* End of Temeprature Sensor Data */
#ifdef AHRS_MOD
pData->m_sensorData.m_fAcc[0]=((float)((*pData).sAcc[1]))*9.8/1000.0;
pData->m_sensorData.m_fAcc[1]=((float)((*pData).sAcc[0]))*9.8/1000.0;
pData->m_sensorData.m_fAcc[2]=-((float)((*pData).sAcc[2]))*9.8/1000.0;
/* report gyro data into dps in float format */
pData->m_sensorData.m_fGyro[1]=((float)((*pData).sGyro[0]))*(3.141592/180.0)/Gyro_SensitivityLSB_R_300dps;
pData->m_sensorData.m_fGyro[0]=((float)((*pData).sGyro[1]))*(3.141592/180.0)/Gyro_SensitivityLSB_P_300dps;
pData->m_sensorData.m_fGyro[2]=-((float)((*pData).sGyro[2]))*(3.141592/180.0)/Gyro_SensitivityLSB_Y_300dps;
pData->m_sensorData.m_fMag[1]=((float)((*pData).sMag[0]))/LSM_Magn_Sensitivity_XY_1_3Ga;
pData->m_sensorData.m_fMag[0]=((float)((*pData).sMag[1]))/LSM_Magn_Sensitivity_XY_1_3Ga;
pData->m_sensorData.m_fMag[2]=-((float)((*pData).sMag[2]))/LSM_Magn_Sensitivity_Z_1_3Ga;
iNEMO_AHRS_Update(&(pData->m_sensorData), &(pData->m_angle), &(pData->m_quat));
roll = pData->m_angle.m_fRoll* 180.0f / 3.141592f;
pitch = pData->m_angle.m_fPitch * 180.0f / 3.141592f;
yaw = pData->m_angle.m_fYaw * 180.0f / 3.141592f;
Float_To_Buffer(roll, &databuffer[nByteToSend + 2]);
Float_To_Buffer(pitch, &databuffer[nByteToSend + 6]);
Float_To_Buffer(yaw, &databuffer[nByteToSend +10]);
Float_To_Buffer((pData->m_quat[0]), &databuffer[nByteToSend + 14]);
Float_To_Buffer((pData->m_quat[1]), &databuffer[nByteToSend + 18]);
Float_To_Buffer((pData->m_quat[2]), &databuffer[nByteToSend + 22]);
Float_To_Buffer((pData->m_quat[3]), &databuffer[nByteToSend + 26]);
nByteToSend+=4*sizeof (float) + 3* sizeof (float);// 4*float quaternions + 3*float angles.
#endif
} /* End if AHRS is ENABLED*/
/*AHRS DISABLE*/
else
{
if(outmode & 0x10)
{
LSM303DLH_Acc_Read_RawData(pData->sAcc);
/*if raw data enabled*/
if(GetRawData())
{
s16_to_u8_buffer(&(pData->sAcc[0]), &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&(pData->sAcc[1]), &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&(pData->sAcc[2]), &databuffer[nByteToSend + 6]);
}
/* Calibrated data are requested*/
else
{
s16 acc[3];
acc[0]=(s16)(pData->sAcc[0]/pData->uGain[0]) - pData->sOffset[0];
acc[1]=(s16)(pData->sAcc[1]/pData->uGain[1]) - pData->sOffset[1];
acc[2]=(s16)(pData->sAcc[2]/pData->uGain[2]) - pData->sOffset[2];
s16_to_u8_buffer(&acc[0], &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&acc[1], &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&acc[2], &databuffer[nByteToSend + 6]);
}
nByteToSend+=6;
}/* End of Accelerometer Data*/
/* if gyroscopes output is requested */
#ifdef _GYRO_RPY
if(outmode & 0x08)
{
LPRYxxxAL_Read_RawRate(pData->sGyro);
/*if raw data enabled*/
if(GetRawData())
{
s16_to_u8_buffer(&(pData->sGyro[0]), &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&(pData->sGyro[1]), &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&(pData->sGyro[2]), &databuffer[nByteToSend + 6]);
}
/* Calibrated data are requested*/
else
{
s16 dps[3];
dps[0]=(s16)((pData->sGyro[0]/pData->uGain[3]) - pData->sOffset[3]);
dps[1]=(s16)((pData->sGyro[1]/pData->uGain[4]) - pData->sOffset[4]);
dps[2]=(s16)((pData->sGyro[2]/pData->uGain[5]) - pData->sOffset[5]);
s16_to_u8_buffer(&dps[0], &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&dps[1], &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&dps[2], &databuffer[nByteToSend + 6]);
}
nByteToSend+=6;
}/* End of Gyroscope Data */
/* if magnetometer output is requested */
if(outmode & 0x04)
{
LSM303DLH_Magn_Read_RawData(pData->sMag);
/*if raw data enabled*/
if(GetRawData())
{
s16_to_u8_buffer(&(pData->sMag[0]), &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&(pData->sMag[1]), &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&(pData->sMag[2]), &databuffer[nByteToSend + 6]);
}
/* Calibrated data are requested*/
else
{
s16 gauss[3];
gauss[0]=(s16)(pData->sMag[0]*1000/pData->uGain[6]) - pData->sOffset[6];
gauss[1]=(s16)(pData->sMag[1]*1000/pData->uGain[7]) - pData->sOffset[7];
gauss[2]=(s16)(pData->sMag[2]*1000/pData->uGain[8]) - pData->sOffset[8];
s16_to_u8_buffer(&gauss[0], &databuffer[nByteToSend + 2]);
s16_to_u8_buffer(&gauss[1], &databuffer[nByteToSend + 4]);
s16_to_u8_buffer(&gauss[2], &databuffer[nByteToSend + 6]);
}
nByteToSend+=6;
} /* End of Magnetometer Data */
#endif
#ifdef _PRESS
/* if pressure output is requested */
if(outmode & 0x02)
{
LPS001DL_Get_Raw_Pressure(&(pData->uPress));
/*if raw data enabled*/
if(GetRawData())
{
u16_to_u8_buffer(&(pData->uPress), &databuffer[nByteToSend + 2]);
}
/* Calibrated data are requested*/
else
{
u16 p;
p=(s16)((pData->uPress/pData->uGain[9]) - pData->sOffset[9]);
u16_to_u8_buffer(&p, &databuffer[nByteToSend + 2]);
}
nByteToSend+=2;
} /* End of Pressure Sensor Data */
#endif
/* if temperature output is requested */
if(outmode & 0x01)
{
/*if raw data enabled*/
if(GetRawData())
{
STLM75_Read_Raw_Data(&(pData->sTemp));
s16_to_u8_buffer(&(pData->sTemp),&databuffer[nByteToSend + 2]);
}
/* Calibrated data are requested*/
else
{
s16 p;
STLM75_Read_Temperature_Signed(&(pData->sTemp));
p=(s16)(pData->sTemp - pData->sOffset[10]);
s16_to_u8_buffer(&p, &databuffer[nByteToSend + 2]);
}
nByteToSend+=2;
} /* End of Temperature Sensor Data */
}
s_iC++;
databuffer[0]=(u8)(s_iC>>8);
databuffer[1]=(u8)(s_iC);
nByteToSend+=2; /* 2 byte counter*/
Send_Data(iNEMO_Start_Acquisition, nByteToSend+1, databuffer);
}
else { // end of data acquisition in Sample Mode.
Enable_Timer(DISABLE);
}
}
/**
* Send Acknowledgment without Payload to the device, as correct reception of a frame.
* frame : Frame_Type to acknowledge.
*/
void Send_Ack(unsigned char frame, u8 length, u8* payload)
{
u8 tmp[30];
tmp[0] = ACK;
tmp[1] = length;
tmp[2] = frame;
if(length>1)
CopyBuffer(payload, &tmp[3],length-1);
androidAccessoryWrite(tmp, length + 2);
}
/**
* Send Command w/o payload to the device, as correct reception of a frame.
* frame : Frame_Type to acknowledge.
*/
void Send_Data(unsigned char frame, u8 length, u8* payload)
{
u8 tmp[100];
tmp[0] = DATA;
tmp[1] = length;
tmp[2] = frame;
if(length>1)
CopyBuffer(payload, &tmp[3],length-1);
androidAccessoryWrite(tmp, length + 2);
}
/**
* Send NAcknowledgment without Payload to the device, as correct reception of a frame.
* frame : Frame_Type to acknowledge.
*/
void Send_Nack(unsigned char frame, u8 error_code)
{
u8 tmp[30];
tmp[0] = NACK;
tmp[1] = 2;
tmp[2] = frame;
tmp[3] = error_code;
androidAccessoryWrite(&tmp[0], 4);
}
/**
* Configure the timer in order to generate a recursive interrupt according to the
* number parameter.
* The interrupt is used by the iNemo Data task to send the sensor data at a given frequency.
* LOW_FREQUENCY - specifies a frequency acquisition of 1Hz
* MEDIUM_FREQUENCY_1 - specifies a frequency acquisition of 10Hz
* MEDIUM_FREQUENCY_2 - specifies a frequency acquisition of 25Hz
* HIGH_FREQUENCY - specifies a frequency acquisition of 50Hz. This is the
* default value
*/
void Set_Timer(unsigned char number)
{
unsigned short a;
unsigned short b;
unsigned long n;
int frequency; //This value is the timer frequency expressed in Hz
// table to convert the frequency number to actual frequency value.
const int nFreqEnum2freVal[7] = { 1, 10, 25, 50, 30,100, 400 };
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
NVIC_InitTypeDef NVIC_InitStructure;
frequency = number < 7 ? nFreqEnum2freVal[number] : 400;
TIM_TimeBaseStructInit( &TIM_TimeBaseStructure );
// Time base configuration for timer 2 - which generates the interrupts.
n = 72000000/frequency;
prvFindFactors( n, &a, &b );
TIM_TimeBaseStructure.TIM_Period = b - 1;
TIM_TimeBaseStructure.TIM_Prescaler = a - 1;
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit( TIM2, &TIM_TimeBaseStructure );
TIM_ARRPreloadConfig(TIM2, ENABLE );
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 13;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init( &NVIC_InitStructure );
}
/**
* Start and stop the timer used by the iNemo Data Task.
* command start the timer if ENABLE, stop the timer if DISABLE.
*/
void Enable_Timer(FunctionalState command) {
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
TIM_ITConfig( TIM2, TIM_IT_Update, command );
TIM_Cmd(TIM2, command);
}
/**
* Set Output Mode option
* outmode : 0 Disable/1 Enable order bit :AHRS | RFU 0 | Cal/Raw | Acceleration | Gyro | Magnetometer | Pressure | temperature
* Cal/Raw --> 0-->Calibrated 1-->Raw
* Calibrated data: Sensitivity and offset [mg, dps etc..]
* Raw data: [lsb]
*/
void SetOutMode(u8 outmode) {
s_uOutSelect = outmode;
}
/**
* Return output mode option
*/
u8 GetOutMode() {
return s_uOutSelect;
}
/**
* set a boolean to enable/disable AHRS
* bEnable : TRUE AHRS enable FALSE AHRS disable
*/
void SetAhrs(bool bEnable) {
s_bAhrsEnabled = bEnable;
}
/**
* set a boolean to enable/disable RAW DATA
* bEnable : TRUE RAW enable FALSE RAW disable
*/
void SetRawData(bool bEnable) {
s_bRawDataEnabled = bEnable;
}
/**
* return a boolean to check if AHRS is enabled/disabled
* s_bAhrsEnabled : TRUE Ahrs enable FALSE Ahrs disable
*/
bool GetAhrs()
{
return s_bAhrsEnabled;
}
/**
* return a boolean to check if Raw is enabled/disabled
* s_bAhrsEnabled : TRUE Ahrs enable FALSE Ahrs disable
*/
bool GetRawData()
{
return s_bRawDataEnabled;
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Demo/CORTEX_STM32F103_Keil/CommunicationManager/comManager.c | C | oos | 31,674 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
all the API functions to use the MPU wrappers. That should only be done when
task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "StackMacros.h"
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/*
* Macro to define the amount of stack available to the idle task.
*/
#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE
/*
* Task control block. A task control block (TCB) is allocated to each task,
* and stores the context of the task.
*/
typedef struct tskTaskControlBlock
{
volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */
#if ( portUSING_MPU_WRAPPERS == 1 )
xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE STRUCT. */
#endif
xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */
xListItem xEventListItem; /*< List item used to place the TCB in event lists. */
unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */
portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */
signed char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */
#if ( portSTACK_GROWTH > 0 )
portSTACK_TYPE *pxEndOfStack; /*< Used for stack overflow checking on architectures where the stack grows up from low memory. */
#endif
#if ( portCRITICAL_NESTING_IN_TCB == 1 )
unsigned portBASE_TYPE uxCriticalNesting;
#endif
#if ( configUSE_TRACE_FACILITY == 1 )
unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */
#endif
#if ( configUSE_MUTEXES == 1 )
unsigned portBASE_TYPE uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
#endif
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
pdTASK_HOOK_CODE pxTaskTag;
#endif
#if ( configGENERATE_RUN_TIME_STATS == 1 )
unsigned long ulRunTimeCounter; /*< Used for calculating how much CPU time each task is utilising. */
#endif
} tskTCB;
/*
* Some kernel aware debuggers require data to be viewed to be global, rather
* than file scope.
*/
#ifdef portREMOVE_STATIC_QUALIFIER
#define static
#endif
/*lint -e956 */
PRIVILEGED_DATA tskTCB * volatile pxCurrentTCB = NULL;
/* Lists for ready and blocked tasks. --------------------*/
PRIVILEGED_DATA static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */
PRIVILEGED_DATA static xList xDelayedTaskList1; /*< Delayed tasks. */
PRIVILEGED_DATA static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
PRIVILEGED_DATA static xList * volatile pxDelayedTaskList ; /*< Points to the delayed task list currently being used. */
PRIVILEGED_DATA static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
PRIVILEGED_DATA static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */
#if ( INCLUDE_vTaskDelete == 1 )
PRIVILEGED_DATA static xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */
PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0U;
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
PRIVILEGED_DATA static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */
#endif
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
PRIVILEGED_DATA static xTaskHandle xIdleTaskHandle = NULL;
#endif
/* File private variables. --------------------------------*/
PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0U;
PRIVILEGED_DATA static volatile portTickType xTickCount = ( portTickType ) 0U;
PRIVILEGED_DATA static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY;
PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY;
PRIVILEGED_DATA static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE;
PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE;
PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0U;
PRIVILEGED_DATA static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE;
PRIVILEGED_DATA static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0;
PRIVILEGED_DATA static unsigned portBASE_TYPE uxTaskNumber = ( unsigned portBASE_TYPE ) 0U;
PRIVILEGED_DATA static portTickType xNextTaskUnblockTime = ( portTickType ) portMAX_DELAY;
#if ( configGENERATE_RUN_TIME_STATS == 1 )
PRIVILEGED_DATA static char pcStatsString[ 50 ] ;
PRIVILEGED_DATA static unsigned long ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */
static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime ) PRIVILEGED_FUNCTION;
#endif
/* Debugging and trace facilities private variables and macros. ------------*/
/*
* The value used to fill the stack of a task when the task is created. This
* is used purely for checking the high water mark for tasks.
*/
#define tskSTACK_FILL_BYTE ( 0xa5U )
/*
* Macros used by vListTask to indicate which state a task is in.
*/
#define tskBLOCKED_CHAR ( ( signed char ) 'B' )
#define tskREADY_CHAR ( ( signed char ) 'R' )
#define tskDELETED_CHAR ( ( signed char ) 'D' )
#define tskSUSPENDED_CHAR ( ( signed char ) 'S' )
/*
* Macros and private variables used by the trace facility.
*/
#if ( configUSE_TRACE_FACILITY == 1 )
#define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned long ) ( sizeof( unsigned long ) + sizeof( unsigned long ) ) )
PRIVILEGED_DATA static volatile signed char * volatile pcTraceBuffer;
PRIVILEGED_DATA static signed char *pcTraceBufferStart;
PRIVILEGED_DATA static signed char *pcTraceBufferEnd;
PRIVILEGED_DATA static signed portBASE_TYPE xTracing = pdFALSE;
static unsigned portBASE_TYPE uxPreviousTask = 255U;
PRIVILEGED_DATA static char pcStatusString[ 50 ];
#endif
/*-----------------------------------------------------------*/
/*
* Macro that writes a trace of scheduler activity to a buffer. This trace
* shows which task is running when and is very useful as a debugging tool.
* As this macro is called each context switch it is a good idea to undefine
* it if not using the facility.
*/
#if ( configUSE_TRACE_FACILITY == 1 )
#define vWriteTraceToBuffer() \
{ \
if( xTracing != pdFALSE ) \
{ \
if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \
{ \
if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \
{ \
uxPreviousTask = pxCurrentTCB->uxTCBNumber; \
*( unsigned long * ) pcTraceBuffer = ( unsigned long ) xTickCount; \
pcTraceBuffer += sizeof( unsigned long ); \
*( unsigned long * ) pcTraceBuffer = ( unsigned long ) uxPreviousTask; \
pcTraceBuffer += sizeof( unsigned long ); \
} \
else \
{ \
xTracing = pdFALSE; \
} \
} \
} \
}
#else
#define vWriteTraceToBuffer()
#endif
/*-----------------------------------------------------------*/
/*
* Place the task represented by pxTCB into the appropriate ready queue for
* the task. It is inserted at the end of the list. One quirk of this is
* that if the task being inserted is at the same priority as the currently
* executing task, then it will only be rescheduled after the currently
* executing task has been rescheduled.
*/
#define prvAddTaskToReadyQueue( pxTCB ) \
if( ( pxTCB )->uxPriority > uxTopReadyPriority ) \
{ \
uxTopReadyPriority = ( pxTCB )->uxPriority; \
} \
vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )
/*-----------------------------------------------------------*/
/*
* Macro that looks at the list of tasks that are currently delayed to see if
* any require waking.
*
* Tasks are stored in the queue in the order of their wake time - meaning
* once one tasks has been found whose timer has not expired we need not look
* any further down the list.
*/
#define prvCheckDelayedTasks() \
{ \
portTickType xItemValue; \
\
/* Is the tick count greater than or equal to the wake time of the first \
task referenced from the delayed tasks list? */ \
if( xTickCount >= xNextTaskUnblockTime ) \
{ \
for( ;; ) \
{ \
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) \
{ \
/* The delayed list is empty. Set xNextTaskUnblockTime to the \
maximum possible value so it is extremely unlikely that the \
if( xTickCount >= xNextTaskUnblockTime ) test will pass next \
time through. */ \
xNextTaskUnblockTime = portMAX_DELAY; \
break; \
} \
else \
{ \
/* The delayed list is not empty, get the value of the item at \
the head of the delayed list. This is the time at which the \
task at the head of the delayed list should be removed from \
the Blocked state. */ \
pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); \
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ); \
\
if( xTickCount < xItemValue ) \
{ \
/* It is not time to unblock this item yet, but the item \
value is the time at which the task at the head of the \
blocked list should be removed from the Blocked state - \
so record the item value in xNextTaskUnblockTime. */ \
xNextTaskUnblockTime = xItemValue; \
break; \
} \
\
/* It is time to remove the item from the Blocked state. */ \
vListRemove( &( pxTCB->xGenericListItem ) ); \
\
/* Is the task waiting on an event also? */ \
if( pxTCB->xEventListItem.pvContainer != NULL ) \
{ \
vListRemove( &( pxTCB->xEventListItem ) ); \
} \
prvAddTaskToReadyQueue( pxTCB ); \
} \
} \
} \
}
/*-----------------------------------------------------------*/
/*
* Several functions take an xTaskHandle parameter that can optionally be NULL,
* where NULL is used to indicate that the handle of the currently executing
* task should be used in place of the parameter. This macro simply checks to
* see if the parameter is NULL and returns a pointer to the appropriate TCB.
*/
#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) ( pxHandle ) )
/* Callback function prototypes. --------------------------*/
extern void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName );
extern void vApplicationTickHook( void );
/* File private functions. --------------------------------*/
/*
* Utility to ready a TCB for a given task. Mainly just copies the parameters
* into the TCB structure.
*/
static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth ) PRIVILEGED_FUNCTION;
/*
* Utility to ready all the lists used by the scheduler. This is called
* automatically upon the creation of the first task.
*/
static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
/*
* The idle task, which as all tasks is implemented as a never ending loop.
* The idle task is automatically created and added to the ready lists upon
* creation of the first user task.
*
* The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
* language extensions. The equivalent prototype for this function is:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
/*
* Utility to free all memory allocated by the scheduler to hold a TCB,
* including the stack pointed to by the TCB.
*
* This does not free memory allocated by the task itself (i.e. memory
* allocated by calls to pvPortMalloc from within the tasks application code).
*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( tskTCB *pxTCB ) PRIVILEGED_FUNCTION;
#endif
/*
* Used only by the idle task. This checks to see if anything has been placed
* in the list of tasks waiting to be deleted. If so the task is cleaned up
* and its TCB deleted.
*/
static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
/*
* The currently executing task is entering the Blocked state. Add the task to
* either the current or the overflow delayed task list.
*/
static void prvAddCurrentTaskToDelayedList( portTickType xTimeToWake ) PRIVILEGED_FUNCTION;
/*
* Allocates memory from the heap for a TCB and associated stack. Checks the
* allocation was successful.
*/
static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer ) PRIVILEGED_FUNCTION;
/*
* Called from vTaskList. vListTasks details all the tasks currently under
* control of the scheduler. The tasks may be in one of a number of lists.
* prvListTaskWithinSingleList accepts a list and details the tasks from
* within just that list.
*
* THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
* NORMAL APPLICATION CODE.
*/
#if ( configUSE_TRACE_FACILITY == 1 )
static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus ) PRIVILEGED_FUNCTION;
#endif
/*
* When a task is created, the stack of the task is filled with a known value.
* This function determines the 'high water mark' of the task stack by
* determining how much of the stack remains at the original preset value.
*/
#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte ) PRIVILEGED_FUNCTION;
#endif
/*lint +e956 */
/*-----------------------------------------------------------
* TASK CREATION API documented in task.h
*----------------------------------------------------------*/
signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pxTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )
{
signed portBASE_TYPE xReturn;
tskTCB * pxNewTCB;
configASSERT( pxTaskCode );
configASSERT( ( uxPriority < configMAX_PRIORITIES ) );
/* Allocate the memory required by the TCB and stack for the new task,
checking that the allocation was successful. */
pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );
if( pxNewTCB != NULL )
{
portSTACK_TYPE *pxTopOfStack;
#if( portUSING_MPU_WRAPPERS == 1 )
/* Should the task be created in privileged mode? */
portBASE_TYPE xRunPrivileged;
if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
{
xRunPrivileged = pdTRUE;
}
else
{
xRunPrivileged = pdFALSE;
}
uxPriority &= ~portPRIVILEGE_BIT;
#endif /* portUSING_MPU_WRAPPERS == 1 */
/* Calculate the top of stack address. This depends on whether the
stack grows from high memory to low (as per the 80x86) or visa versa.
portSTACK_GROWTH is used to make the result positive or negative as
required by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( unsigned short ) 1 );
pxTopOfStack = ( portSTACK_TYPE * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK ) );
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( unsigned long ) pxTopOfStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
}
#else
{
pxTopOfStack = pxNewTCB->pxStack;
/* Check the alignment of the stack buffer is correct. */
configASSERT( ( ( ( unsigned long ) pxNewTCB->pxStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
/* If we want to use stack checking on architectures that use
a positive stack growth direction then we also need to store the
other extreme of the stack space. */
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );
}
#endif
/* Setup the newly allocated TCB with the initial state of the task. */
prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );
/* Initialize the TCB stack to look as if the task was already running,
but had been interrupted by the scheduler. The return address is set
to the start of the task function. Once the stack has been initialised
the top of stack variable is updated. */
#if( portUSING_MPU_WRAPPERS == 1 )
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
}
#else
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
}
#endif
/* Check the alignment of the initialised stack. */
configASSERT( ( ( ( unsigned long ) pxNewTCB->pxTopOfStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
if( ( void * ) pxCreatedTask != NULL )
{
/* Pass the TCB out - in an anonymous way. The calling function/
task can use this as a handle to delete the task later if
required.*/
*pxCreatedTask = ( xTaskHandle ) pxNewTCB;
}
/* We are going to manipulate the task queues to add this task to a
ready list, so must make sure no interrupts occur. */
taskENTER_CRITICAL();
{
uxCurrentNumberOfTasks++;
if( pxCurrentTCB == NULL )
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 )
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
}
}
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
{
if( pxCurrentTCB->uxPriority <= uxPriority )
{
pxCurrentTCB = pxNewTCB;
}
}
}
/* Remember the top priority to make context switching faster. Use
the priority in pxNewTCB as this has been capped to a valid value. */
if( pxNewTCB->uxPriority > uxTopUsedPriority )
{
uxTopUsedPriority = pxNewTCB->uxPriority;
}
#if ( configUSE_TRACE_FACILITY == 1 )
{
/* Add a counter into the TCB for tracing only. */
pxNewTCB->uxTCBNumber = uxTaskNumber;
}
#endif
uxTaskNumber++;
prvAddTaskToReadyQueue( pxNewTCB );
xReturn = pdPASS;
traceTASK_CREATE( pxNewTCB );
}
taskEXIT_CRITICAL();
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
traceTASK_CREATE_FAILED();
}
if( xReturn == pdPASS )
{
if( xSchedulerRunning != pdFALSE )
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < uxPriority )
{
portYIELD_WITHIN_API();
}
}
}
return xReturn;
}
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
void vTaskDelete( xTaskHandle pxTaskToDelete )
{
tskTCB *pxTCB;
taskENTER_CRITICAL();
{
/* Ensure a yield is performed if the current task is being
deleted. */
if( pxTaskToDelete == pxCurrentTCB )
{
pxTaskToDelete = NULL;
}
/* If null is passed in here then we are deleting ourselves. */
pxTCB = prvGetTCBFromHandle( pxTaskToDelete );
/* Remove task from the ready list and place in the termination list.
This will stop the task from be scheduled. The idle task will check
the termination list and free up any memory allocated by the
scheduler for the TCB and stack. */
vListRemove( &( pxTCB->xGenericListItem ) );
/* Is the task waiting on an event also? */
if( pxTCB->xEventListItem.pvContainer != NULL )
{
vListRemove( &( pxTCB->xEventListItem ) );
}
vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );
/* Increment the ucTasksDeleted variable so the idle task knows
there is a task that has been deleted and that it should therefore
check the xTasksWaitingTermination list. */
++uxTasksDeleted;
/* Increment the uxTaskNumberVariable also so kernel aware debuggers
can detect that the task lists need re-generating. */
uxTaskNumber++;
traceTASK_DELETE( pxTCB );
}
taskEXIT_CRITICAL();
/* Force a reschedule if we have just deleted the current task. */
if( xSchedulerRunning != pdFALSE )
{
if( ( void * ) pxTaskToDelete == NULL )
{
portYIELD_WITHIN_API();
}
}
}
#endif
/*-----------------------------------------------------------
* TASK CONTROL API documented in task.h
*----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelayUntil == 1 )
void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )
{
portTickType xTimeToWake;
portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE;
configASSERT( pxPreviousWakeTime );
configASSERT( ( xTimeIncrement > 0U ) );
vTaskSuspendAll();
{
/* Generate the tick time at which the task wants to wake. */
xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
if( xTickCount < *pxPreviousWakeTime )
{
/* The tick count has overflowed since this function was
lasted called. In this case the only time we should ever
actually delay is if the wake time has also overflowed,
and the wake time is greater than the tick time. When this
is the case it is as if neither time had overflowed. */
if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) )
{
xShouldDelay = pdTRUE;
}
}
else
{
/* The tick time has not overflowed. In this case we will
delay if either the wake time has overflowed, and/or the
tick time is less than the wake time. */
if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) )
{
xShouldDelay = pdTRUE;
}
}
/* Update the wake time ready for the next call. */
*pxPreviousWakeTime = xTimeToWake;
if( xShouldDelay != pdFALSE )
{
traceTASK_DELAY_UNTIL();
/* We must remove ourselves from the ready list before adding
ourselves to the blocked list as the same list item is used for
both lists. */
vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
prvAddCurrentTaskToDelayedList( xTimeToWake );
}
}
xAlreadyYielded = xTaskResumeAll();
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
{
portYIELD_WITHIN_API();
}
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( portTickType xTicksToDelay )
{
portTickType xTimeToWake;
signed portBASE_TYPE xAlreadyYielded = pdFALSE;
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( portTickType ) 0U )
{
vTaskSuspendAll();
{
traceTASK_DELAY();
/* A task that is removed from the event list while the
scheduler is suspended will not get placed in the ready
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
/* Calculate the time to wake - this may overflow but this is
not a problem. */
xTimeToWake = xTickCount + xTicksToDelay;
/* We must remove ourselves from the ready list before adding
ourselves to the blocked list as the same list item is used for
both lists. */
vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
prvAddCurrentTaskToDelayedList( xTimeToWake );
}
xAlreadyYielded = xTaskResumeAll();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
{
portYIELD_WITHIN_API();
}
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_uxTaskPriorityGet == 1 )
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask )
{
tskTCB *pxTCB;
unsigned portBASE_TYPE uxReturn;
taskENTER_CRITICAL();
{
/* If null is passed in here then we are changing the
priority of the calling function. */
pxTCB = prvGetTCBFromHandle( pxTask );
uxReturn = pxTCB->uxPriority;
}
taskEXIT_CRITICAL();
return uxReturn;
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskPrioritySet == 1 )
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )
{
tskTCB *pxTCB;
unsigned portBASE_TYPE uxCurrentPriority;
portBASE_TYPE xYieldRequired = pdFALSE;
configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
/* Ensure the new priority is valid. */
if( uxNewPriority >= configMAX_PRIORITIES )
{
uxNewPriority = configMAX_PRIORITIES - ( unsigned portBASE_TYPE ) 1U;
}
taskENTER_CRITICAL();
{
if( pxTask == pxCurrentTCB )
{
pxTask = NULL;
}
/* If null is passed in here then we are changing the
priority of the calling function. */
pxTCB = prvGetTCBFromHandle( pxTask );
traceTASK_PRIORITY_SET( pxTask, uxNewPriority );
#if ( configUSE_MUTEXES == 1 )
{
uxCurrentPriority = pxTCB->uxBasePriority;
}
#else
{
uxCurrentPriority = pxTCB->uxPriority;
}
#endif
if( uxCurrentPriority != uxNewPriority )
{
/* The priority change may have readied a task of higher
priority than the calling task. */
if( uxNewPriority > uxCurrentPriority )
{
if( pxTask != NULL )
{
/* The priority of another task is being raised. If we
were raising the priority of the currently running task
there would be no need to switch as it must have already
been the highest priority task. */
xYieldRequired = pdTRUE;
}
}
else if( pxTask == NULL )
{
/* Setting our own priority down means there may now be another
task of higher priority that is ready to execute. */
xYieldRequired = pdTRUE;
}
#if ( configUSE_MUTEXES == 1 )
{
/* Only change the priority being used if the task is not
currently using an inherited priority. */
if( pxTCB->uxBasePriority == pxTCB->uxPriority )
{
pxTCB->uxPriority = uxNewPriority;
}
/* The base priority gets set whatever. */
pxTCB->uxBasePriority = uxNewPriority;
}
#else
{
pxTCB->uxPriority = uxNewPriority;
}
#endif
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( configMAX_PRIORITIES - ( portTickType ) uxNewPriority ) );
/* If the task is in the blocked or suspended list we need do
nothing more than change it's priority variable. However, if
the task is in a ready list it needs to be removed and placed
in the queue appropriate to its new priority. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) )
{
/* The task is currently in its ready list - remove before adding
it to it's new ready list. As we are in a critical section we
can do this even if the scheduler is suspended. */
vListRemove( &( pxTCB->xGenericListItem ) );
prvAddTaskToReadyQueue( pxTCB );
}
if( xYieldRequired == pdTRUE )
{
portYIELD_WITHIN_API();
}
}
}
taskEXIT_CRITICAL();
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskSuspend == 1 )
void vTaskSuspend( xTaskHandle pxTaskToSuspend )
{
tskTCB *pxTCB;
taskENTER_CRITICAL();
{
/* Ensure a yield is performed if the current task is being
suspended. */
if( pxTaskToSuspend == pxCurrentTCB )
{
pxTaskToSuspend = NULL;
}
/* If null is passed in here then we are suspending ourselves. */
pxTCB = prvGetTCBFromHandle( pxTaskToSuspend );
traceTASK_SUSPEND( pxTCB );
/* Remove task from the ready/delayed list and place in the suspended list. */
vListRemove( &( pxTCB->xGenericListItem ) );
/* Is the task waiting on an event also? */
if( pxTCB->xEventListItem.pvContainer != NULL )
{
vListRemove( &( pxTCB->xEventListItem ) );
}
vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );
}
taskEXIT_CRITICAL();
if( ( void * ) pxTaskToSuspend == NULL )
{
if( xSchedulerRunning != pdFALSE )
{
/* We have just suspended the current task. */
portYIELD_WITHIN_API();
}
else
{
/* The scheduler is not running, but the task that was pointed
to by pxCurrentTCB has just been suspended and pxCurrentTCB
must be adjusted to point to a different task. */
if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
{
/* No other tasks are ready, so set pxCurrentTCB back to
NULL so when the next task is created pxCurrentTCB will
be set to point to it no matter what its relative priority
is. */
pxCurrentTCB = NULL;
}
else
{
vTaskSwitchContext();
}
}
}
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskSuspend == 1 )
signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask )
{
portBASE_TYPE xReturn = pdFALSE;
const tskTCB * const pxTCB = ( tskTCB * ) xTask;
/* It does not make sense to check if the calling task is suspended. */
configASSERT( xTask );
/* Is the task we are attempting to resume actually in the
suspended list? */
if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )
{
/* Has the task already been resumed from within an ISR? */
if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE )
{
/* Is it in the suspended list because it is in the
Suspended state? It is possible to be in the suspended
list because it is blocked on a task with no timeout
specified. */
if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) == pdTRUE )
{
xReturn = pdTRUE;
}
}
}
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskSuspend == 1 )
void vTaskResume( xTaskHandle pxTaskToResume )
{
tskTCB *pxTCB;
/* It does not make sense to resume the calling task. */
configASSERT( pxTaskToResume );
/* Remove the task from whichever list it is currently in, and place
it in the ready list. */
pxTCB = ( tskTCB * ) pxTaskToResume;
/* The parameter cannot be NULL as it is impossible to resume the
currently executing task. */
if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
{
taskENTER_CRITICAL();
{
if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE )
{
traceTASK_RESUME( pxTCB );
/* As we are in a critical section we can access the ready
lists even if the scheduler is suspended. */
vListRemove( &( pxTCB->xGenericListItem ) );
prvAddTaskToReadyQueue( pxTCB );
/* We may have just resumed a higher priority task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
{
/* This yield may not cause the task just resumed to run, but
will leave the lists in the correct state for the next yield. */
portYIELD_WITHIN_API();
}
}
}
taskEXIT_CRITICAL();
}
}
#endif
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume )
{
portBASE_TYPE xYieldRequired = pdFALSE;
tskTCB *pxTCB;
configASSERT( pxTaskToResume );
pxTCB = ( tskTCB * ) pxTaskToResume;
if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE )
{
traceTASK_RESUME_FROM_ISR( pxTCB );
if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
{
xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority );
vListRemove( &( pxTCB->xGenericListItem ) );
prvAddTaskToReadyQueue( pxTCB );
}
else
{
/* We cannot access the delayed or ready lists, so will hold this
task pending until the scheduler is resumed, at which point a
yield will be performed if necessary. */
vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
}
}
return xYieldRequired;
}
#endif
/*-----------------------------------------------------------
* PUBLIC SCHEDULER CONTROL documented in task.h
*----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
portBASE_TYPE xReturn;
/* Add the idle task at the lowest priority. */
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
{
/* Create the idle task, storing its handle in xIdleTaskHandle so it can
be returned by the xTaskGetIdleTaskHandle() function. */
xReturn = xTaskCreate( prvIdleTask, ( signed char * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle );
}
#else
{
/* Create the idle task without storing its handle. */
xReturn = xTaskCreate( prvIdleTask, ( signed char * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL );
}
#endif
#if ( configUSE_TIMERS == 1 )
{
if( xReturn == pdPASS )
{
xReturn = xTimerCreateTimerTask();
}
}
#endif
if( xReturn == pdPASS )
{
/* Interrupts are turned off here, to ensure a tick does not occur
before or during the call to xPortStartScheduler(). The stacks of
the created tasks contain a status word with interrupts switched on
so interrupts will automatically get re-enabled when the first task
starts to run.
STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE
DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */
portDISABLE_INTERRUPTS();
xSchedulerRunning = pdTRUE;
xTickCount = ( portTickType ) 0U;
/* If configGENERATE_RUN_TIME_STATS is defined then the following
macro must be defined to configure the timer/counter used to generate
the run time counter time base. */
portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
{
/* Should not reach here as if the scheduler is running the
function will not return. */
}
else
{
/* Should only reach here if a task calls xTaskEndScheduler(). */
}
}
/* This line will only be reached if the kernel could not be started. */
configASSERT( xReturn );
}
/*-----------------------------------------------------------*/
void vTaskEndScheduler( void )
{
/* Stop the scheduler interrupts and call the portable scheduler end
routine so the original ISRs can be restored if necessary. The port
layer must ensure interrupts enable bit is left in the correct state. */
portDISABLE_INTERRUPTS();
xSchedulerRunning = pdFALSE;
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
/* A critical section is not required as the variable is of type
portBASE_TYPE. */
++uxSchedulerSuspended;
}
/*----------------------------------------------------------*/
signed portBASE_TYPE xTaskResumeAll( void )
{
register tskTCB *pxTCB;
signed portBASE_TYPE xAlreadyYielded = pdFALSE;
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
{
--uxSchedulerSuspended;
if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
{
if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0U )
{
portBASE_TYPE xYieldRequired = pdFALSE;
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( ( xList * ) &xPendingReadyList ) == pdFALSE )
{
pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) );
vListRemove( &( pxTCB->xEventListItem ) );
vListRemove( &( pxTCB->xGenericListItem ) );
prvAddTaskToReadyQueue( pxTCB );
/* If we have moved a task that has a priority higher than
the current task then we should yield. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
{
xYieldRequired = pdTRUE;
}
}
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does not
slip, and that any delayed tasks are resumed at the correct time. */
if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0U )
{
while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0U )
{
vTaskIncrementTick();
--uxMissedTicks;
}
/* As we have processed some ticks it is appropriate to yield
to ensure the highest priority task that is ready to run is
the task actually running. */
#if configUSE_PREEMPTION == 1
{
xYieldRequired = pdTRUE;
}
#endif
}
if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) )
{
xAlreadyYielded = pdTRUE;
xMissedYield = pdFALSE;
portYIELD_WITHIN_API();
}
}
}
}
taskEXIT_CRITICAL();
return xAlreadyYielded;
}
/*-----------------------------------------------------------
* PUBLIC TASK UTILITIES documented in task.h
*----------------------------------------------------------*/
portTickType xTaskGetTickCount( void )
{
portTickType xTicks;
/* Critical section required if running on a 16 bit processor. */
taskENTER_CRITICAL();
{
xTicks = xTickCount;
}
taskEXIT_CRITICAL();
return xTicks;
}
/*-----------------------------------------------------------*/
portTickType xTaskGetTickCountFromISR( void )
{
portTickType xReturn;
unsigned portBASE_TYPE uxSavedInterruptStatus;
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
xReturn = xTickCount;
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
/*-----------------------------------------------------------*/
unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void )
{
/* A critical section is not required because the variables are of type
portBASE_TYPE. */
return uxCurrentNumberOfTasks;
}
/*-----------------------------------------------------------*/
#if ( INCLUDE_pcTaskGetTaskName == 1 )
signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery )
{
tskTCB *pxTCB;
/* If null is passed in here then the name of the calling task is being queried. */
pxTCB = prvGetTCBFromHandle( xTaskToQuery );
configASSERT( pxTCB );
return &( pxTCB->pcTaskName[ 0 ] );
}
#endif
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
void vTaskList( signed char *pcWriteBuffer )
{
unsigned portBASE_TYPE uxQueue;
/* This is a VERY costly function that should be used for debug only.
It leaves interrupts disabled for a LONG time. */
vTaskSuspendAll();
{
/* Run through all the lists that could potentially contain a TCB and
report the task name, state and stack high water mark. */
*pcWriteBuffer = ( signed char ) 0x00;
strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" );
uxQueue = uxTopUsedPriority + ( unsigned portBASE_TYPE ) 1U;
do
{
uxQueue--;
if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) == pdFALSE )
{
prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR );
}
}while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY );
if( listLIST_IS_EMPTY( pxDelayedTaskList ) == pdFALSE )
{
prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR );
}
if( listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) == pdFALSE )
{
prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR );
}
#if( INCLUDE_vTaskDelete == 1 )
{
if( listLIST_IS_EMPTY( &xTasksWaitingTermination ) == pdFALSE )
{
prvListTaskWithinSingleList( pcWriteBuffer, &xTasksWaitingTermination, tskDELETED_CHAR );
}
}
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( listLIST_IS_EMPTY( &xSuspendedTaskList ) == pdFALSE )
{
prvListTaskWithinSingleList( pcWriteBuffer, &xSuspendedTaskList, tskSUSPENDED_CHAR );
}
}
#endif
}
xTaskResumeAll();
}
#endif
/*----------------------------------------------------------*/
#if ( configGENERATE_RUN_TIME_STATS == 1 )
void vTaskGetRunTimeStats( signed char *pcWriteBuffer )
{
unsigned portBASE_TYPE uxQueue;
unsigned long ulTotalRunTime;
/* This is a VERY costly function that should be used for debug only.
It leaves interrupts disabled for a LONG time. */
vTaskSuspendAll();
{
#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
#else
ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
#endif
/* Divide ulTotalRunTime by 100 to make the percentage caluclations
simpler in the prvGenerateRunTimeStatsForTasksInList() function. */
ulTotalRunTime /= 100UL;
/* Run through all the lists that could potentially contain a TCB,
generating a table of run timer percentages in the provided
buffer. */
*pcWriteBuffer = ( signed char ) 0x00;
strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" );
uxQueue = uxTopUsedPriority + ( unsigned portBASE_TYPE ) 1U;
do
{
uxQueue--;
if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) == pdFALSE )
{
prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), ulTotalRunTime );
}
}while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY );
if( listLIST_IS_EMPTY( pxDelayedTaskList ) == pdFALSE )
{
prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, ulTotalRunTime );
}
if( listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) == pdFALSE )
{
prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, ulTotalRunTime );
}
#if ( INCLUDE_vTaskDelete == 1 )
{
if( listLIST_IS_EMPTY( &xTasksWaitingTermination ) == pdFALSE )
{
prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, &xTasksWaitingTermination, ulTotalRunTime );
}
}
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( listLIST_IS_EMPTY( &xSuspendedTaskList ) == pdFALSE )
{
prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, &xSuspendedTaskList, ulTotalRunTime );
}
}
#endif
}
xTaskResumeAll();
}
#endif
/*----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
void vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize )
{
configASSERT( pcBuffer );
configASSERT( ulBufferSize );
taskENTER_CRITICAL();
{
pcTraceBuffer = ( signed char * )pcBuffer;
pcTraceBufferStart = pcBuffer;
pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE );
xTracing = pdTRUE;
}
taskEXIT_CRITICAL();
}
#endif
/*----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
unsigned long ulTaskEndTrace( void )
{
unsigned long ulBufferLength;
taskENTER_CRITICAL();
xTracing = pdFALSE;
taskEXIT_CRITICAL();
ulBufferLength = ( unsigned long ) ( pcTraceBuffer - pcTraceBufferStart );
return ulBufferLength;
}
#endif
/*----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
xTaskHandle xTaskGetIdleTaskHandle( void )
{
/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
started, then xIdleTaskHandle will be NULL. */
configASSERT( ( xIdleTaskHandle != NULL ) );
return xIdleTaskHandle;
}
#endif
/*-----------------------------------------------------------
* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
* documented in task.h
*----------------------------------------------------------*/
void vTaskIncrementTick( void )
{
tskTCB * pxTCB;
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
{
++xTickCount;
if( xTickCount == ( portTickType ) 0U )
{
xList *pxTemp;
/* Tick count has overflowed so we need to swap the delay lists.
If there are any items in pxDelayedTaskList here then there is
an error! */
configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );
pxTemp = pxDelayedTaskList;
pxDelayedTaskList = pxOverflowDelayedTaskList;
pxOverflowDelayedTaskList = pxTemp;
xNumOfOverflows++;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
{
/* The new current delayed list is empty. Set
xNextTaskUnblockTime to the maximum possible value so it is
extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
}
else
{
/* The new current delayed list is not empty, get the value of
the item at the head of the delayed list. This is the time at
which the task at the head of the delayed list should be removed
from the Blocked state. */
pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );
}
}
/* See if this tick has made a timeout expire. */
prvCheckDelayedTasks();
}
else
{
++uxMissedTicks;
/* The tick hook gets called at regular intervals, even if the
scheduler is locked. */
#if ( configUSE_TICK_HOOK == 1 )
{
vApplicationTickHook();
}
#endif
}
#if ( configUSE_TICK_HOOK == 1 )
{
/* Guard against the tick hook being called when the missed tick
count is being unwound (when the scheduler is being unlocked. */
if( uxMissedTicks == ( unsigned portBASE_TYPE ) 0U )
{
vApplicationTickHook();
}
}
#endif
traceTASK_INCREMENT_TICK( xTickCount );
}
/*-----------------------------------------------------------*/
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction )
{
tskTCB *xTCB;
/* If xTask is NULL then we are setting our own task hook. */
if( xTask == NULL )
{
xTCB = ( tskTCB * ) pxCurrentTCB;
}
else
{
xTCB = ( tskTCB * ) xTask;
}
/* Save the hook function in the TCB. A critical section is required as
the value can be accessed from an interrupt. */
taskENTER_CRITICAL();
xTCB->pxTaskTag = pxHookFunction;
taskEXIT_CRITICAL();
}
#endif
/*-----------------------------------------------------------*/
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask )
{
tskTCB *xTCB;
pdTASK_HOOK_CODE xReturn;
/* If xTask is NULL then we are setting our own task hook. */
if( xTask == NULL )
{
xTCB = ( tskTCB * ) pxCurrentTCB;
}
else
{
xTCB = ( tskTCB * ) xTask;
}
/* Save the hook function in the TCB. A critical section is required as
the value can be accessed from an interrupt. */
taskENTER_CRITICAL();
xReturn = xTCB->pxTaskTag;
taskEXIT_CRITICAL();
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )
{
tskTCB *xTCB;
portBASE_TYPE xReturn;
/* If xTask is NULL then we are calling our own task hook. */
if( xTask == NULL )
{
xTCB = ( tskTCB * ) pxCurrentTCB;
}
else
{
xTCB = ( tskTCB * ) xTask;
}
if( xTCB->pxTaskTag != NULL )
{
xReturn = xTCB->pxTaskTag( pvParameter );
}
else
{
xReturn = pdFAIL;
}
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE )
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xMissedYield = pdTRUE;
}
else
{
traceTASK_SWITCHED_OUT();
#if ( configGENERATE_RUN_TIME_STATS == 1 )
{
unsigned long ulTempCounter;
#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
portALT_GET_RUN_TIME_COUNTER_VALUE( ulTempCounter );
#else
ulTempCounter = portGET_RUN_TIME_COUNTER_VALUE();
#endif
/* Add the amount of time the task has been running to the accumulated
time so far. The time the task started running was stored in
ulTaskSwitchedInTime. Note that there is no overflow protection here
so count values are only valid until the timer overflows. Generally
this will be about 1 hour assuming a 1uS timer increment. */
pxCurrentTCB->ulRunTimeCounter += ( ulTempCounter - ulTaskSwitchedInTime );
ulTaskSwitchedInTime = ulTempCounter;
}
#endif
taskFIRST_CHECK_FOR_STACK_OVERFLOW();
taskSECOND_CHECK_FOR_STACK_OVERFLOW();
/* Find the highest priority queue that contains ready tasks. */
while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) )
{
configASSERT( uxTopReadyPriority );
--uxTopReadyPriority;
}
/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the
same priority get an equal share of the processor time. */
listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) );
traceTASK_SWITCHED_IN();
vWriteTraceToBuffer();
}
}
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait )
{
portTickType xTimeToWake;
configASSERT( pxEventList );
/* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE
SCHEDULER SUSPENDED. */
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. */
vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );
/* We must remove ourselves from the ready list before adding ourselves
to the blocked list as the same list item is used for both lists. We have
exclusive access to the ready lists as the scheduler is locked. */
vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( xTicksToWait == portMAX_DELAY )
{
/* Add ourselves to the suspended task list instead of a delayed task
list to ensure we are not woken by a timing event. We will block
indefinitely. */
vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
}
else
{
/* Calculate the time at which the task should be woken if the event does
not occur. This may overflow but this doesn't matter. */
xTimeToWake = xTickCount + xTicksToWait;
prvAddCurrentTaskToDelayedList( xTimeToWake );
}
}
#else
{
/* Calculate the time at which the task should be woken if the event does
not occur. This may overflow but this doesn't matter. */
xTimeToWake = xTickCount + xTicksToWait;
prvAddCurrentTaskToDelayedList( xTimeToWake );
}
#endif
}
/*-----------------------------------------------------------*/
#if configUSE_TIMERS == 1
void vTaskPlaceOnEventListRestricted( const xList * const pxEventList, portTickType xTicksToWait )
{
portTickType xTimeToWake;
configASSERT( pxEventList );
/* This function should not be called by application code hence the
'Restricted' in its name. It is not part of the public API. It is
designed for use by kernel code, and has special calling requirements -
it should be called from a critical section. */
/* Place the event list item of the TCB in the appropriate event list.
In this case it is assume that this is the only task that is going to
be waiting on this event list, so the faster vListInsertEnd() function
can be used in place of vListInsert. */
vListInsertEnd( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );
/* We must remove this task from the ready list before adding it to the
blocked list as the same list item is used for both lists. This
function is called form a critical section. */
vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
/* Calculate the time at which the task should be woken if the event does
not occur. This may overflow but this doesn't matter. */
xTimeToWake = xTickCount + xTicksToWait;
prvAddCurrentTaskToDelayedList( xTimeToWake );
}
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList )
{
tskTCB *pxUnblockedTCB;
portBASE_TYPE xReturn;
/* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE
SCHEDULER SUSPENDED. It can also be called from within an ISR. */
/* The event list is sorted in priority order, so we can remove the
first in the list, remove the TCB from the delayed list, and add
it to the ready list.
If an event is for a queue that is locked then this function will never
get called - the lock count on the queue will get modified instead. This
means we can always expect exclusive access to the event list here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
configASSERT( pxUnblockedTCB );
vListRemove( &( pxUnblockedTCB->xEventListItem ) );
if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
{
vListRemove( &( pxUnblockedTCB->xGenericListItem ) );
prvAddTaskToReadyQueue( pxUnblockedTCB );
}
else
{
/* We cannot access the delayed or ready lists, so will hold this
task pending until the scheduler is resumed. */
vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
}
if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority )
{
/* Return true if the task removed from the event list has
a higher priority than the calling task. This allows
the calling task to know if it should force a context
switch now. */
xReturn = pdTRUE;
}
else
{
xReturn = pdFALSE;
}
return xReturn;
}
/*-----------------------------------------------------------*/
void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut )
{
configASSERT( pxTimeOut );
pxTimeOut->xOverflowCount = xNumOfOverflows;
pxTimeOut->xTimeOnEntering = xTickCount;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait )
{
portBASE_TYPE xReturn;
configASSERT( pxTimeOut );
configASSERT( pxTicksToWait );
taskENTER_CRITICAL();
{
#if ( INCLUDE_vTaskSuspend == 1 )
/* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is
the maximum block time then the task should block indefinitely, and
therefore never time out. */
if( *pxTicksToWait == portMAX_DELAY )
{
xReturn = pdFALSE;
}
else /* We are not blocking indefinitely, perform the checks below. */
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( ( portTickType ) xTickCount >= ( portTickType ) pxTimeOut->xTimeOnEntering ) )
{
/* The tick count is greater than the time at which vTaskSetTimeout()
was called, but has also overflowed since vTaskSetTimeOut() was called.
It must have wrapped all the way around and gone past us again. This
passed since vTaskSetTimeout() was called. */
xReturn = pdTRUE;
}
else if( ( ( portTickType ) ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering ) ) < ( portTickType ) *pxTicksToWait )
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering );
vTaskSetTimeOutState( pxTimeOut );
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
}
taskEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
xMissedYield = pdTRUE;
}
/*
* -----------------------------------------------------------
* The Idle task.
* ----------------------------------------------------------
*
* The portTASK_FUNCTION() macro is used to allow port/compiler specific
* language extensions. The equivalent prototype for this function is:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
/* Stop warnings. */
( void ) pvParameters;
for( ;; )
{
/* See if any tasks have been deleted. */
prvCheckTasksWaitingTermination();
#if ( configUSE_PREEMPTION == 0 )
{
/* If we are not using preemption we keep forcing a task switch to
see if any other task has become available. If we are using
preemption we don't need to do this as any task becoming available
will automatically get the processor anyway. */
taskYIELD();
}
#endif
#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
{
/* When using preemption tasks of equal priority will be
timesliced. If a task that is sharing the idle priority is ready
to run then the idle task should yield before the end of the
timeslice.
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 )
{
taskYIELD();
}
}
#endif
#if ( configUSE_IDLE_HOOK == 1 )
{
extern void vApplicationIdleHook( void );
/* Call the user defined function from within the idle task. This
allows the application designer to add background functionality
without the overhead of a separate task.
NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
CALL A FUNCTION THAT MIGHT BLOCK. */
vApplicationIdleHook();
}
#endif
}
} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */
/*-----------------------------------------------------------
* File private functions documented at the top of the file.
*----------------------------------------------------------*/
static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth )
{
/* Store the function name in the TCB. */
#if configMAX_TASK_NAME_LEN > 1
{
/* Don't bring strncpy into the build unnecessarily. */
strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned short ) configMAX_TASK_NAME_LEN );
}
#endif
pxTCB->pcTaskName[ ( unsigned short ) configMAX_TASK_NAME_LEN - ( unsigned short ) 1 ] = ( signed char ) '\0';
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= configMAX_PRIORITIES )
{
uxPriority = configMAX_PRIORITIES - ( unsigned portBASE_TYPE ) 1U;
}
pxTCB->uxPriority = uxPriority;
#if ( configUSE_MUTEXES == 1 )
{
pxTCB->uxBasePriority = uxPriority;
}
#endif
vListInitialiseItem( &( pxTCB->xGenericListItem ) );
vListInitialiseItem( &( pxTCB->xEventListItem ) );
/* Set the pxTCB as a link back from the xListItem. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );
listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );
#if ( portCRITICAL_NESTING_IN_TCB == 1 )
{
pxTCB->uxCriticalNesting = ( unsigned portBASE_TYPE ) 0U;
}
#endif
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
{
pxTCB->pxTaskTag = NULL;
}
#endif
#if ( configGENERATE_RUN_TIME_STATS == 1 )
{
pxTCB->ulRunTimeCounter = 0UL;
}
#endif
#if ( portUSING_MPU_WRAPPERS == 1 )
{
vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );
}
#else
{
( void ) xRegions;
( void ) usStackDepth;
}
#endif
}
/*-----------------------------------------------------------*/
#if ( portUSING_MPU_WRAPPERS == 1 )
void vTaskAllocateMPURegions( xTaskHandle xTaskToModify, const xMemoryRegion * const xRegions )
{
tskTCB *pxTCB;
if( xTaskToModify == pxCurrentTCB )
{
xTaskToModify = NULL;
}
/* If null is passed in here then we are deleting ourselves. */
pxTCB = prvGetTCBFromHandle( xTaskToModify );
vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
}
/*-----------------------------------------------------------*/
#endif
static void prvInitialiseTaskLists( void )
{
unsigned portBASE_TYPE uxPriority;
for( uxPriority = ( unsigned portBASE_TYPE ) 0U; uxPriority < configMAX_PRIORITIES; uxPriority++ )
{
vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) );
}
vListInitialise( ( xList * ) &xDelayedTaskList1 );
vListInitialise( ( xList * ) &xDelayedTaskList2 );
vListInitialise( ( xList * ) &xPendingReadyList );
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( ( xList * ) &xTasksWaitingTermination );
}
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( ( xList * ) &xSuspendedTaskList );
}
#endif
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
pxOverflowDelayedTaskList = &xDelayedTaskList2;
}
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
#if ( INCLUDE_vTaskDelete == 1 )
{
portBASE_TYPE xListIsEmpty;
/* ucTasksDeleted is used to prevent vTaskSuspendAll() being called
too often in the idle task. */
if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0U )
{
vTaskSuspendAll();
xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );
xTaskResumeAll();
if( xListIsEmpty == pdFALSE )
{
tskTCB *pxTCB;
taskENTER_CRITICAL();
{
pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) );
vListRemove( &( pxTCB->xGenericListItem ) );
--uxCurrentNumberOfTasks;
--uxTasksDeleted;
}
taskEXIT_CRITICAL();
prvDeleteTCB( pxTCB );
}
}
}
#endif
}
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( portTickType xTimeToWake )
{
/* The list item will be inserted in wake time order. */
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );
if( xTimeToWake < xTickCount )
{
/* Wake time has overflowed. Place this item in the overflow list. */
vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
}
else
{
/* The wake time has not overflowed, so we can use the current block list. */
vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
/* If the task entering the blocked state was placed at the head of the
list of blocked tasks then xNextTaskUnblockTime needs to be updated
too. */
if( xTimeToWake < xNextTaskUnblockTime )
{
xNextTaskUnblockTime = xTimeToWake;
}
}
}
/*-----------------------------------------------------------*/
static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer )
{
tskTCB *pxNewTCB;
/* Allocate space for the TCB. Where the memory comes from depends on
the implementation of the port malloc function. */
pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) );
if( pxNewTCB != NULL )
{
/* Allocate space for the stack used by the task being created.
The base of the stack memory stored in the TCB so the task can
be deleted later if required. */
pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMallocAligned( ( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ), puxStackBuffer );
if( pxNewTCB->pxStack == NULL )
{
/* Could not allocate the stack. Delete the allocated TCB. */
vPortFree( pxNewTCB );
pxNewTCB = NULL;
}
else
{
/* Just to help debugging. */
memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( portSTACK_TYPE ) );
}
}
return pxNewTCB;
}
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus )
{
volatile tskTCB *pxNextTCB, *pxFirstTCB;
unsigned short usStackRemaining;
/* Write the details of all the TCB's in pxList into the buffer. */
listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
do
{
listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
#if ( portSTACK_GROWTH > 0 )
{
usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned char * ) pxNextTCB->pxEndOfStack );
}
#else
{
usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned char * ) pxNextTCB->pxStack );
}
#endif
sprintf( pcStatusString, ( char * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber );
strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatusString );
} while( pxNextTCB != pxFirstTCB );
}
#endif
/*-----------------------------------------------------------*/
#if ( configGENERATE_RUN_TIME_STATS == 1 )
static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime )
{
volatile tskTCB *pxNextTCB, *pxFirstTCB;
unsigned long ulStatsAsPercentage;
/* Write the run time stats of all the TCB's in pxList into the buffer. */
listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
do
{
/* Get next TCB in from the list. */
listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
/* Divide by zero check. */
if( ulTotalRunTime > 0UL )
{
/* Has the task run at all? */
if( pxNextTCB->ulRunTimeCounter == 0UL )
{
/* The task has used no CPU time at all. */
sprintf( pcStatsString, ( char * ) "%s\t\t0\t\t0%%\r\n", pxNextTCB->pcTaskName );
}
else
{
/* What percentage of the total run time has the task used?
This will always be rounded down to the nearest integer.
ulTotalRunTime has already been divided by 100. */
ulStatsAsPercentage = pxNextTCB->ulRunTimeCounter / ulTotalRunTime;
if( ulStatsAsPercentage > 0UL )
{
#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
{
sprintf( pcStatsString, ( char * ) "%s\t\t%lu\t\t%lu%%\r\n", pxNextTCB->pcTaskName, pxNextTCB->ulRunTimeCounter, ulStatsAsPercentage );
}
#else
{
/* sizeof( int ) == sizeof( long ) so a smaller
printf() library can be used. */
sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t%u%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
}
#endif
}
else
{
/* If the percentage is zero here then the task has
consumed less than 1% of the total run time. */
#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
{
sprintf( pcStatsString, ( char * ) "%s\t\t%lu\t\t<1%%\r\n", pxNextTCB->pcTaskName, pxNextTCB->ulRunTimeCounter );
}
#else
{
/* sizeof( int ) == sizeof( long ) so a smaller
printf() library can be used. */
sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t<1%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter );
}
#endif
}
}
strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatsString );
}
} while( pxNextTCB != pxFirstTCB );
}
#endif
/*-----------------------------------------------------------*/
#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte )
{
register unsigned short usCount = 0U;
while( *pucStackByte == tskSTACK_FILL_BYTE )
{
pucStackByte -= portSTACK_GROWTH;
usCount++;
}
usCount /= sizeof( portSTACK_TYPE );
return usCount;
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask )
{
tskTCB *pxTCB;
unsigned char *pcEndOfStack;
unsigned portBASE_TYPE uxReturn;
pxTCB = prvGetTCBFromHandle( xTask );
#if portSTACK_GROWTH < 0
{
pcEndOfStack = ( unsigned char * ) pxTCB->pxStack;
}
#else
{
pcEndOfStack = ( unsigned char * ) pxTCB->pxEndOfStack;
}
#endif
uxReturn = ( unsigned portBASE_TYPE ) usTaskCheckFreeStackSpace( pcEndOfStack );
return uxReturn;
}
#endif
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( tskTCB *pxTCB )
{
/* Free up the memory allocated by the scheduler for the task. It is up to
the task to free any memory allocated at the application level. */
vPortFreeAligned( pxTCB->pxStack );
vPortFree( pxTCB );
}
#endif
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
xTaskHandle xTaskGetCurrentTaskHandle( void )
{
xTaskHandle xReturn;
/* A critical section is not required as this is not called from
an interrupt and the current TCB will always be the same for any
individual execution thread. */
xReturn = pxCurrentTCB;
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
portBASE_TYPE xTaskGetSchedulerState( void )
{
portBASE_TYPE xReturn;
if( xSchedulerRunning == pdFALSE )
{
xReturn = taskSCHEDULER_NOT_STARTED;
}
else
{
if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
{
xReturn = taskSCHEDULER_RUNNING;
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
}
}
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder )
{
tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder;
configASSERT( pxMutexHolder );
if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )
{
/* Adjust the mutex holder state to account for its new priority. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxCurrentTCB->uxPriority );
/* If the task being modified is in the ready state it will need to
be moved in to a new list. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )
{
vListRemove( &( pxTCB->xGenericListItem ) );
/* Inherit the priority before being moved into the new list. */
pxTCB->uxPriority = pxCurrentTCB->uxPriority;
prvAddTaskToReadyQueue( pxTCB );
}
else
{
/* Just inherit the priority. */
pxTCB->uxPriority = pxCurrentTCB->uxPriority;
}
}
}
#endif
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder )
{
tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder;
if( pxMutexHolder != NULL )
{
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
{
/* We must be the running task to be able to give the mutex back.
Remove ourselves from the ready list we currently appear in. */
vListRemove( &( pxTCB->xGenericListItem ) );
/* Disinherit the priority before adding ourselves into the new
ready list. */
pxTCB->uxPriority = pxTCB->uxBasePriority;
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxTCB->uxPriority );
prvAddTaskToReadyQueue( pxTCB );
}
}
}
#endif
/*-----------------------------------------------------------*/
#if ( portCRITICAL_NESTING_IN_TCB == 1 )
void vTaskEnterCritical( void )
{
portDISABLE_INTERRUPTS();
if( xSchedulerRunning != pdFALSE )
{
( pxCurrentTCB->uxCriticalNesting )++;
}
}
#endif
/*-----------------------------------------------------------*/
#if ( portCRITICAL_NESTING_IN_TCB == 1 )
void vTaskExitCritical( void )
{
if( xSchedulerRunning != pdFALSE )
{
if( pxCurrentTCB->uxCriticalNesting > 0U )
{
( pxCurrentTCB->uxCriticalNesting )--;
if( pxCurrentTCB->uxCriticalNesting == 0U )
{
portENABLE_INTERRUPTS();
}
}
}
}
#endif
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/tasks.c | C | oos | 80,950 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include <stdlib.h>
#include "FreeRTOS.h"
#include "list.h"
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( xList *pxList )
{
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd );
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd );
pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd );
pxList->uxNumberOfItems = ( unsigned portBASE_TYPE ) 0U;
}
/*-----------------------------------------------------------*/
void vListInitialiseItem( xListItem *pxItem )
{
/* Make sure the list item is not recorded as being on a list. */
pxItem->pvContainer = NULL;
}
/*-----------------------------------------------------------*/
void vListInsertEnd( xList *pxList, xListItem *pxNewListItem )
{
volatile xListItem * pxIndex;
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by
the pxIndex member. */
pxIndex = pxList->pxIndex;
pxNewListItem->pxNext = pxIndex->pxNext;
pxNewListItem->pxPrevious = pxList->pxIndex;
pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;
pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem;
pxList->pxIndex = ( volatile xListItem * ) pxNewListItem;
/* Remember which list the item is in. */
pxNewListItem->pvContainer = ( void * ) pxList;
( pxList->uxNumberOfItems )++;
}
/*-----------------------------------------------------------*/
void vListInsert( xList *pxList, xListItem *pxNewListItem )
{
volatile xListItem *pxIterator;
portTickType xValueOfInsertion;
/* Insert the new list item into the list, sorted in ulListItem order. */
xValueOfInsertion = pxNewListItem->xItemValue;
/* If the list already contains a list item with the same item value then
the new list item should be placed after it. This ensures that TCB's which
are stored in ready lists (all of which have the same ulListItem value)
get an equal share of the CPU. However, if the xItemValue is the same as
the back marker the iteration loop below will not end. This means we need
to guard against this by checking the value first and modifying the
algorithm slightly if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
{
pxIterator = pxList->xListEnd.pxPrevious;
}
else
{
/* *** NOTE ***********************************************************
If you find your application is crashing here then likely causes are:
1) Stack overflow -
see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
2) Incorrect interrupt priority assignment, especially on Cortex-M3
parts where numerically high priority values denote low actual
interrupt priories, which can seem counter intuitive. See
configMAX_SYSCALL_INTERRUPT_PRIORITY on http://www.freertos.org/a00110.html
3) Calling an API function from within a critical section or when
the scheduler is suspended.
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
See http://www.freertos.org/FAQHelp.html for more tips.
**********************************************************************/
for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
{
/* There is nothing to do here, we are just iterating to the
wanted insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;
pxNewListItem->pxPrevious = pxIterator;
pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem;
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pvContainer = ( void * ) pxList;
( pxList->uxNumberOfItems )++;
}
/*-----------------------------------------------------------*/
void vListRemove( xListItem *pxItemToRemove )
{
xList * pxList;
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
/* The list item knows which list it is in. Obtain the list from the list
item. */
pxList = ( xList * ) pxItemToRemove->pvContainer;
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
}
pxItemToRemove->pvContainer = NULL;
( pxList->uxNumberOfItems )--;
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/list.c | C | oos | 8,296 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
all the API functions to use the MPU wrappers. That should only be done when
task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/* This entire source file will be skipped if the application is not configured
to include software timer functionality. This #if is closed at the very bottom
of this file. If you want to include software timer functionality then ensure
configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
#if ( configUSE_TIMERS == 1 )
/* Misc definitions. */
#define tmrNO_DELAY ( portTickType ) 0U
/* The definition of the timers themselves. */
typedef struct tmrTimerControl
{
const signed char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */
xListItem xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */
portTickType xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
unsigned portBASE_TYPE uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one shot timer. */
void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */
tmrTIMER_CALLBACK pxCallbackFunction; /*<< The function that will be called when the timer expires. */
} xTIMER;
/* The definition of messages that can be sent and received on the timer
queue. */
typedef struct tmrTimerQueueMessage
{
portBASE_TYPE xMessageID; /*<< The command being sent to the timer service task. */
portTickType xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
xTIMER * pxTimer; /*<< The timer to which the command will be applied. */
} xTIMER_MESSAGE;
/* The list in which active timers are stored. Timers are referenced in expire
time order, with the nearest expiry time at the front of the list. Only the
timer service task is allowed to access xActiveTimerList. */
PRIVILEGED_DATA static xList xActiveTimerList1;
PRIVILEGED_DATA static xList xActiveTimerList2;
PRIVILEGED_DATA static xList *pxCurrentTimerList;
PRIVILEGED_DATA static xList *pxOverflowTimerList;
/* A queue that is used to send commands to the timer service task. */
PRIVILEGED_DATA static xQueueHandle xTimerQueue = NULL;
#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
PRIVILEGED_DATA static xTaskHandle xTimerTaskHandle = NULL;
#endif
/*-----------------------------------------------------------*/
/*
* Initialise the infrastructure used by the timer service task if it has not
* been initialised already.
*/
static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
/*
* The timer service task (daemon). Timer functionality is controlled by this
* task. Other tasks communicate with the timer service task using the
* xTimerQueue queue.
*/
static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
/*
* Called by the timer service task to interpret and process a command it
* received on the timer queue.
*/
static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
/*
* Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
* depending on if the expire time causes a timer counter overflow.
*/
static portBASE_TYPE prvInsertTimerInActiveList( xTIMER *pxTimer, portTickType xNextExpiryTime, portTickType xTimeNow, portTickType xCommandTime ) PRIVILEGED_FUNCTION;
/*
* An active timer has reached its expire time. Reload the timer if it is an
* auto reload timer, then call its callback.
*/
static void prvProcessExpiredTimer( portTickType xNextExpireTime, portTickType xTimeNow ) PRIVILEGED_FUNCTION;
/*
* The tick count has overflowed. Switch the timer lists after ensuring the
* current timer list does not still reference some timers.
*/
static void prvSwitchTimerLists( portTickType xLastTime ) PRIVILEGED_FUNCTION;
/*
* Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
* if a tick count overflow occurred since prvSampleTimeNow() was last called.
*/
static portTickType prvSampleTimeNow( portBASE_TYPE *pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
/*
* If the timer list contains any active timers then return the expire time of
* the timer that will expire first and set *pxListWasEmpty to false. If the
* timer list does not contain any timers then return 0 and set *pxListWasEmpty
* to pdTRUE.
*/
static portTickType prvGetNextExpireTime( portBASE_TYPE *pxListWasEmpty ) PRIVILEGED_FUNCTION;
/*
* If a timer has expired, process it. Otherwise, block the timer service task
* until either a timer does expire or a command is received.
*/
static void prvProcessTimerOrBlockTask( portTickType xNextExpireTime, portBASE_TYPE xListWasEmpty ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
portBASE_TYPE xTimerCreateTimerTask( void )
{
portBASE_TYPE xReturn = pdFAIL;
/* This function is called when the scheduler is started if
configUSE_TIMERS is set to 1. Check that the infrastructure used by the
timer service task has been created/initialised. If timers have already
been created then the initialisation will already have been performed. */
prvCheckForValidListAndQueue();
if( xTimerQueue != NULL )
{
#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
{
/* Create the timer task, storing its handle in xTimerTaskHandle so
it can be returned by the xTimerGetTimerDaemonTaskHandle() function. */
xReturn = xTaskCreate( prvTimerTask, ( const signed char * ) "Tmr Svc", ( unsigned short ) configTIMER_TASK_STACK_DEPTH, NULL, ( unsigned portBASE_TYPE ) configTIMER_TASK_PRIORITY, &xTimerTaskHandle );
}
#else
{
/* Create the timer task without storing its handle. */
xReturn = xTaskCreate( prvTimerTask, ( const signed char * ) "Tmr Svc", ( unsigned short ) configTIMER_TASK_STACK_DEPTH, NULL, ( unsigned portBASE_TYPE ) configTIMER_TASK_PRIORITY, NULL);
}
#endif
}
configASSERT( xReturn );
return xReturn;
}
/*-----------------------------------------------------------*/
xTimerHandle xTimerCreate( const signed char *pcTimerName, portTickType xTimerPeriodInTicks, unsigned portBASE_TYPE uxAutoReload, void *pvTimerID, tmrTIMER_CALLBACK pxCallbackFunction )
{
xTIMER *pxNewTimer;
/* Allocate the timer structure. */
if( xTimerPeriodInTicks == ( portTickType ) 0U )
{
pxNewTimer = NULL;
configASSERT( ( xTimerPeriodInTicks > 0 ) );
}
else
{
pxNewTimer = ( xTIMER * ) pvPortMalloc( sizeof( xTIMER ) );
if( pxNewTimer != NULL )
{
/* Ensure the infrastructure used by the timer service task has been
created/initialised. */
prvCheckForValidListAndQueue();
/* Initialise the timer structure members using the function parameters. */
pxNewTimer->pcTimerName = pcTimerName;
pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
pxNewTimer->uxAutoReload = uxAutoReload;
pxNewTimer->pvTimerID = pvTimerID;
pxNewTimer->pxCallbackFunction = pxCallbackFunction;
vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
traceTIMER_CREATE( pxNewTimer );
}
else
{
traceTIMER_CREATE_FAILED();
}
}
return ( xTimerHandle ) pxNewTimer;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xTimerGenericCommand( xTimerHandle xTimer, portBASE_TYPE xCommandID, portTickType xOptionalValue, portBASE_TYPE *pxHigherPriorityTaskWoken, portTickType xBlockTime )
{
portBASE_TYPE xReturn = pdFAIL;
xTIMER_MESSAGE xMessage;
/* Send a message to the timer service task to perform a particular action
on a particular timer definition. */
if( xTimerQueue != NULL )
{
/* Send a command to the timer service task to start the xTimer timer. */
xMessage.xMessageID = xCommandID;
xMessage.xMessageValue = xOptionalValue;
xMessage.pxTimer = ( xTIMER * ) xTimer;
if( pxHigherPriorityTaskWoken == NULL )
{
if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xBlockTime );
}
else
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
}
}
else
{
xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
}
traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
}
return xReturn;
}
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
xTaskHandle xTimerGetTimerDaemonTaskHandle( void )
{
/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
started, then xTimerTaskHandle will be NULL. */
configASSERT( ( xTimerTaskHandle != NULL ) );
return xTimerTaskHandle;
}
#endif
/*-----------------------------------------------------------*/
static void prvProcessExpiredTimer( portTickType xNextExpireTime, portTickType xTimeNow )
{
xTIMER *pxTimer;
portBASE_TYPE xResult;
/* Remove the timer from the list of active timers. A check has already
been performed to ensure the list is not empty. */
pxTimer = ( xTIMER * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
vListRemove( &( pxTimer->xTimerListItem ) );
traceTIMER_EXPIRED( pxTimer );
/* If the timer is an auto reload timer then calculate the next
expiry time and re-insert the timer in the list of active timers. */
if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )
{
/* This is the only time a timer is inserted into a list using
a time relative to anything other than the current time. It
will therefore be inserted into the correct list relative to
the time this task thinks it is now, even if a command to
switch lists due to a tick count overflow is already waiting in
the timer queue. */
if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )
{
/* The timer expired before it was added to the active timer
list. Reload it now. */
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xNextExpireTime, NULL, tmrNO_DELAY );
configASSERT( xResult );
( void ) xResult;
}
}
/* Call the timer callback. */
pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );
}
/*-----------------------------------------------------------*/
static void prvTimerTask( void *pvParameters )
{
portTickType xNextExpireTime;
portBASE_TYPE xListWasEmpty;
/* Just to avoid compiler warnings. */
( void ) pvParameters;
for( ;; )
{
/* Query the timers list to see if it contains any timers, and if so,
obtain the time at which the next timer will expire. */
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
/* If a timer has expired, process it. Otherwise, block this task
until either a timer does expire, or a command is received. */
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
/* Empty the command queue. */
prvProcessReceivedCommands();
}
}
/*-----------------------------------------------------------*/
static void prvProcessTimerOrBlockTask( portTickType xNextExpireTime, portBASE_TYPE xListWasEmpty )
{
portTickType xTimeNow;
portBASE_TYPE xTimerListsWereSwitched;
vTaskSuspendAll();
{
/* Obtain the time now to make an assessment as to whether the timer
has expired or not. If obtaining the time causes the lists to switch
then don't process this timer as any timers that remained in the list
when the lists were switched will have been processed within the
prvSampelTimeNow() function. */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
if( xTimerListsWereSwitched == pdFALSE )
{
/* The tick count has not overflowed, has the timer expired? */
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
{
xTaskResumeAll();
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
}
else
{
/* The tick count has not overflowed, and the next expire
time has not been reached yet. This task should therefore
block to wait for the next expire time or a command to be
received - whichever comes first. The following line cannot
be reached unless xNextExpireTime > xTimeNow, except in the
case when the current timer list is empty. */
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ) );
if( xTaskResumeAll() == pdFALSE )
{
/* Yield to wait for either a command to arrive, or the block time
to expire. If a command arrived between the critical section being
exited and this yield then the yield will not cause the task
to block. */
portYIELD_WITHIN_API();
}
}
}
else
{
xTaskResumeAll();
}
}
}
/*-----------------------------------------------------------*/
static portTickType prvGetNextExpireTime( portBASE_TYPE *pxListWasEmpty )
{
portTickType xNextExpireTime;
/* Timers are listed in expiry time order, with the head of the list
referencing the task that will expire first. Obtain the time at which
the timer with the nearest expiry time will expire. If there are no
active timers then just set the next expire time to 0. That will cause
this task to unblock when the tick count overflows, at which point the
timer lists will be switched and the next expiry time can be
re-assessed. */
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
if( *pxListWasEmpty == pdFALSE )
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
}
else
{
/* Ensure the task unblocks when the tick count rolls over. */
xNextExpireTime = ( portTickType ) 0U;
}
return xNextExpireTime;
}
/*-----------------------------------------------------------*/
static portTickType prvSampleTimeNow( portBASE_TYPE *pxTimerListsWereSwitched )
{
portTickType xTimeNow;
static portTickType xLastTime = ( portTickType ) 0U;
xTimeNow = xTaskGetTickCount();
if( xTimeNow < xLastTime )
{
prvSwitchTimerLists( xLastTime );
*pxTimerListsWereSwitched = pdTRUE;
}
else
{
*pxTimerListsWereSwitched = pdFALSE;
}
xLastTime = xTimeNow;
return xTimeNow;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvInsertTimerInActiveList( xTIMER *pxTimer, portTickType xNextExpiryTime, portTickType xTimeNow, portTickType xCommandTime )
{
portBASE_TYPE xProcessTimerNow = pdFALSE;
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
if( xNextExpiryTime <= xTimeNow )
{
/* Has the expiry time elapsed between the command to start/reset a
timer was issued, and the time the command was processed? */
if( ( ( portTickType ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks )
{
/* The time between a command being issued and the command being
processed actually exceeds the timers period. */
xProcessTimerNow = pdTRUE;
}
else
{
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
}
}
else
{
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
{
/* If, since the command was issued, the tick count has overflowed
but the expiry time has not, then the timer must have already passed
its expiry time and should be processed immediately. */
xProcessTimerNow = pdTRUE;
}
else
{
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
}
}
return xProcessTimerNow;
}
/*-----------------------------------------------------------*/
static void prvProcessReceivedCommands( void )
{
xTIMER_MESSAGE xMessage;
xTIMER *pxTimer;
portBASE_TYPE xTimerListsWereSwitched, xResult;
portTickType xTimeNow;
/* In this case the xTimerListsWereSwitched parameter is not used, but it
must be present in the function call. */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL )
{
pxTimer = xMessage.pxTimer;
/* Is the timer already in a list of active timers? When the command
is trmCOMMAND_PROCESS_TIMER_OVERFLOW, the timer will be NULL as the
command is to the task rather than to an individual timer. */
if( pxTimer != NULL )
{
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
{
/* The timer is in a list, remove it. */
vListRemove( &( pxTimer->xTimerListItem ) );
}
}
traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.xMessageValue );
switch( xMessage.xMessageID )
{
case tmrCOMMAND_START :
/* Start or restart a timer. */
if( prvInsertTimerInActiveList( pxTimer, xMessage.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.xMessageValue ) == pdTRUE )
{
/* The timer expired before it was added to the active timer
list. Process it now. */
pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );
if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xMessage.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
configASSERT( xResult );
( void ) xResult;
}
}
break;
case tmrCOMMAND_STOP :
/* The timer has already been removed from the active list.
There is nothing to do here. */
break;
case tmrCOMMAND_CHANGE_PERIOD :
pxTimer->xTimerPeriodInTicks = xMessage.xMessageValue;
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
break;
case tmrCOMMAND_DELETE :
/* The timer has already been removed from the active list,
just free up the memory. */
vPortFree( pxTimer );
break;
default :
/* Don't expect to get here. */
break;
}
}
}
/*-----------------------------------------------------------*/
static void prvSwitchTimerLists( portTickType xLastTime )
{
portTickType xNextExpireTime, xReloadTime;
xList *pxTemp;
xTIMER *pxTimer;
portBASE_TYPE xResult;
/* Remove compiler warnings if configASSERT() is not defined. */
( void ) xLastTime;
/* The tick count has overflowed. The timer lists must be switched.
If there are any timers still referenced from the current timer list
then they must have expired and should be processed before the lists
are switched. */
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
/* Remove the timer from the list. */
pxTimer = ( xTIMER * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
vListRemove( &( pxTimer->xTimerListItem ) );
/* Execute its callback, then send a command to restart the timer if
it is an auto-reload timer. It cannot be restarted here as the lists
have not yet been switched. */
pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );
if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )
{
/* Calculate the reload value, and if the reload value results in
the timer going into the same timer list then it has already expired
and the timer should be re-inserted into the current list so it is
processed again within this loop. Otherwise a command should be sent
to restart the timer to ensure it is only inserted into a list after
the lists have been swapped. */
xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
if( xReloadTime > xNextExpireTime )
{
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
}
else
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xNextExpireTime, NULL, tmrNO_DELAY );
configASSERT( xResult );
( void ) xResult;
}
}
}
pxTemp = pxCurrentTimerList;
pxCurrentTimerList = pxOverflowTimerList;
pxOverflowTimerList = pxTemp;
}
/*-----------------------------------------------------------*/
static void prvCheckForValidListAndQueue( void )
{
/* Check that the list from which active timers are referenced, and the
queue used to communicate with the timer service, have been
initialised. */
taskENTER_CRITICAL();
{
if( xTimerQueue == NULL )
{
vListInitialise( &xActiveTimerList1 );
vListInitialise( &xActiveTimerList2 );
pxCurrentTimerList = &xActiveTimerList1;
pxOverflowTimerList = &xActiveTimerList2;
xTimerQueue = xQueueCreate( ( unsigned portBASE_TYPE ) configTIMER_QUEUE_LENGTH, sizeof( xTIMER_MESSAGE ) );
}
}
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer )
{
portBASE_TYPE xTimerIsInActiveList;
xTIMER *pxTimer = ( xTIMER * ) xTimer;
/* Is the timer in the list of active timers? */
taskENTER_CRITICAL();
{
/* Checking to see if it is in the NULL list in effect checks to see if
it is referenced from either the current or the overflow timer lists in
one go, but the logic has to be reversed, hence the '!'. */
xTimerIsInActiveList = !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );
}
taskEXIT_CRITICAL();
return xTimerIsInActiveList;
}
/*-----------------------------------------------------------*/
void *pvTimerGetTimerID( xTimerHandle xTimer )
{
xTIMER *pxTimer = ( xTIMER * ) xTimer;
return pxTimer->pvTimerID;
}
/*-----------------------------------------------------------*/
/* This entire source file will be skipped if the application is not configured
to include software timer functionality. If you want to include software timer
functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
#endif /* configUSE_TIMERS == 1 */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/timers.c | C | oos | 25,659 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include <stdlib.h>
#include <string.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
all the API functions to use the MPU wrappers. That should only be done when
task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
#include "FreeRTOS.h"
#include "task.h"
#if ( configUSE_CO_ROUTINES == 1 )
#include "croutine.h"
#endif
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
/* Constants used with the cRxLock and cTxLock structure members. */
#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 )
#define queueLOCKED_UNMODIFIED ( ( signed portBASE_TYPE ) 0 )
#define queueERRONEOUS_UNBLOCK ( -1 )
/* For internal use only. */
#define queueSEND_TO_BACK ( 0 )
#define queueSEND_TO_FRONT ( 1 )
/* Effectively make a union out of the xQUEUE structure. */
#define pxMutexHolder pcTail
#define uxQueueType pcHead
#define uxRecursiveCallCount pcReadFrom
#define queueQUEUE_IS_MUTEX NULL
/* Semaphores do not actually store or copy data, so have an items size of
zero. */
#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portBASE_TYPE ) 0 )
#define queueDONT_BLOCK ( ( portTickType ) 0U )
#define queueMUTEX_GIVE_BLOCK_TIME ( ( portTickType ) 0U )
/*
* Definition of the queue used by the scheduler.
* Items are queued by copy, not reference.
*/
typedef struct QueueDefinition
{
signed char *pcHead; /*< Points to the beginning of the queue storage area. */
signed char *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
signed char *pcWriteTo; /*< Points to the free next place in the storage area. */
signed char *pcReadFrom; /*< Points to the last place that a queued item was read from. */
xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */
xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */
volatile unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */
unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */
signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
} xQUEUE;
/*-----------------------------------------------------------*/
/*
* Inside this file xQueueHandle is a pointer to a xQUEUE structure.
* To keep the definition private the API header file defines it as a
* pointer to void.
*/
typedef xQUEUE * xQueueHandle;
/*
* Prototypes for public functions are included here so we don't have to
* include the API header file (as it defines xQueueHandle differently). These
* functions are documented in the API header file.
*/
xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;
unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;
void vQueueDelete( xQueueHandle xQueue ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ) PRIVILEGED_FUNCTION;
xQueueHandle xQueueCreateMutex( void ) PRIVILEGED_FUNCTION;
xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) PRIVILEGED_FUNCTION;
portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ) PRIVILEGED_FUNCTION;
portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle xMutex ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;
unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;
void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;
/*
* Co-routine queue functions differ from task queue functions. Co-routines are
* an optional component.
*/
#if configUSE_CO_ROUTINES == 1
signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;
signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;
#endif
/*
* The queue registry is just a means for kernel aware debuggers to locate
* queue structures. It has no other purpose so is an optional component.
*/
#if configQUEUE_REGISTRY_SIZE > 0
/* The type stored within the queue registry array. This allows a name
to be assigned to each queue making kernel aware debugging a little
more user friendly. */
typedef struct QUEUE_REGISTRY_ITEM
{
signed char *pcQueueName;
xQueueHandle xHandle;
} xQueueRegistryItem;
/* The queue registry is simply an array of xQueueRegistryItem structures.
The pcQueueName member of a structure being NULL is indicative of the
array position being vacant. */
xQueueRegistryItem xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
/* Removes a queue from the registry by simply setting the pcQueueName
member to NULL. */
static void vQueueUnregisterQueue( xQueueHandle xQueue ) PRIVILEGED_FUNCTION;
void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName ) PRIVILEGED_FUNCTION;
#endif
/*
* Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not
* prevent an ISR from adding or removing items to the queue, but does prevent
* an ISR from removing tasks from the queue event lists. If an ISR finds a
* queue is locked it will instead increment the appropriate queue lock count
* to indicate that a task may require unblocking. When the queue in unlocked
* these lock counts are inspected, and the appropriate action taken.
*/
static void prvUnlockQueue( xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;
/*
* Uses a critical section to determine if there is any data in a queue.
*
* @return pdTRUE if the queue contains no items, otherwise pdFALSE.
*/
static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;
/*
* Uses a critical section to determine if there is any space in a queue.
*
* @return pdTRUE if there is no space, otherwise pdFALSE;
*/
static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;
/*
* Copies an item into the queue, either at the front of the queue or the
* back of the queue.
*/
static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition ) PRIVILEGED_FUNCTION;
/*
* Copies an item out of a queue.
*/
static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
/*
* Macro to mark a queue as locked. Locking a queue prevents an ISR from
* accessing the queue event lists.
*/
#define prvLockQueue( pxQueue ) \
taskENTER_CRITICAL(); \
{ \
if( ( pxQueue )->xRxLock == queueUNLOCKED ) \
{ \
( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED; \
} \
if( ( pxQueue )->xTxLock == queueUNLOCKED ) \
{ \
( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED; \
} \
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------
* PUBLIC QUEUE MANAGEMENT API documented in queue.h
*----------------------------------------------------------*/
xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize )
{
xQUEUE *pxNewQueue;
size_t xQueueSizeInBytes;
xQueueHandle xReturn = NULL;
/* Allocate the new queue structure. */
if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 )
{
pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );
if( pxNewQueue != NULL )
{
/* Create the list of pointers to queue items. The queue is one byte
longer than asked for to make wrap checking easier/faster. */
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1;
pxNewQueue->pcHead = ( signed char * ) pvPortMalloc( xQueueSizeInBytes );
if( pxNewQueue->pcHead != NULL )
{
/* Initialise the queue members as described above where the
queue type is defined. */
pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize );
pxNewQueue->uxMessagesWaiting = ( unsigned portBASE_TYPE ) 0U;
pxNewQueue->pcWriteTo = pxNewQueue->pcHead;
pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - ( unsigned portBASE_TYPE ) 1U ) * uxItemSize );
pxNewQueue->uxLength = uxQueueLength;
pxNewQueue->uxItemSize = uxItemSize;
pxNewQueue->xRxLock = queueUNLOCKED;
pxNewQueue->xTxLock = queueUNLOCKED;
/* Likewise ensure the event queues start with the correct state. */
vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );
vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );
traceQUEUE_CREATE( pxNewQueue );
xReturn = pxNewQueue;
}
else
{
traceQUEUE_CREATE_FAILED();
vPortFree( pxNewQueue );
}
}
}
configASSERT( xReturn );
return xReturn;
}
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
xQueueHandle xQueueCreateMutex( void )
{
xQUEUE *pxNewQueue;
/* Allocate the new queue structure. */
pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );
if( pxNewQueue != NULL )
{
/* Information required for priority inheritance. */
pxNewQueue->pxMutexHolder = NULL;
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
/* Queues used as a mutex no data is actually copied into or out
of the queue. */
pxNewQueue->pcWriteTo = NULL;
pxNewQueue->pcReadFrom = NULL;
/* Each mutex has a length of 1 (like a binary semaphore) and
an item size of 0 as nothing is actually copied into or out
of the mutex. */
pxNewQueue->uxMessagesWaiting = ( unsigned portBASE_TYPE ) 0U;
pxNewQueue->uxLength = ( unsigned portBASE_TYPE ) 1U;
pxNewQueue->uxItemSize = ( unsigned portBASE_TYPE ) 0U;
pxNewQueue->xRxLock = queueUNLOCKED;
pxNewQueue->xTxLock = queueUNLOCKED;
/* Ensure the event queues start with the correct state. */
vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );
vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );
/* Start with the semaphore in the expected state. */
xQueueGenericSend( pxNewQueue, NULL, ( portTickType ) 0U, queueSEND_TO_BACK );
traceCREATE_MUTEX( pxNewQueue );
}
else
{
traceCREATE_MUTEX_FAILED();
}
configASSERT( pxNewQueue );
return pxNewQueue;
}
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
#if configUSE_RECURSIVE_MUTEXES == 1
portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex )
{
portBASE_TYPE xReturn;
configASSERT( pxMutex );
/* If this is the task that holds the mutex then pxMutexHolder will not
change outside of this task. If this task does not hold the mutex then
pxMutexHolder can never coincidentally equal the tasks handle, and as
this is the only condition we are interested in it does not matter if
pxMutexHolder is accessed simultaneously by another task. Therefore no
mutual exclusion is required to test the pxMutexHolder variable. */
if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() )
{
traceGIVE_MUTEX_RECURSIVE( pxMutex );
/* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
the task handle, therefore no underflow check is required. Also,
uxRecursiveCallCount is only modified by the mutex holder, and as
there can only be one, no mutual exclusion is required to modify the
uxRecursiveCallCount member. */
( pxMutex->uxRecursiveCallCount )--;
/* Have we unwound the call count? */
if( pxMutex->uxRecursiveCallCount == 0 )
{
/* Return the mutex. This will automatically unblock any other
task that might be waiting to access the mutex. */
xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
}
xReturn = pdPASS;
}
else
{
/* We cannot give the mutex because we are not the holder. */
xReturn = pdFAIL;
traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
}
return xReturn;
}
#endif /* configUSE_RECURSIVE_MUTEXES */
/*-----------------------------------------------------------*/
#if configUSE_RECURSIVE_MUTEXES == 1
portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime )
{
portBASE_TYPE xReturn;
configASSERT( pxMutex );
/* Comments regarding mutual exclusion as per those within
xQueueGiveMutexRecursive(). */
traceTAKE_MUTEX_RECURSIVE( pxMutex );
if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() )
{
( pxMutex->uxRecursiveCallCount )++;
xReturn = pdPASS;
}
else
{
xReturn = xQueueGenericReceive( pxMutex, NULL, xBlockTime, pdFALSE );
/* pdPASS will only be returned if we successfully obtained the mutex,
we may have blocked to reach here. */
if( xReturn == pdPASS )
{
( pxMutex->uxRecursiveCallCount )++;
}
else
{
traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
}
}
return xReturn;
}
#endif /* configUSE_RECURSIVE_MUTEXES */
/*-----------------------------------------------------------*/
#if configUSE_COUNTING_SEMAPHORES == 1
xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )
{
xQueueHandle pxHandle;
pxHandle = xQueueCreate( ( unsigned portBASE_TYPE ) uxCountValue, queueSEMAPHORE_QUEUE_ITEM_LENGTH );
if( pxHandle != NULL )
{
pxHandle->uxMessagesWaiting = uxInitialCount;
traceCREATE_COUNTING_SEMAPHORE();
}
else
{
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
configASSERT( pxHandle );
return pxHandle;
}
#endif /* configUSE_COUNTING_SEMAPHORES */
/*-----------------------------------------------------------*/
signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )
{
signed portBASE_TYPE xEntryTimeSet = pdFALSE;
xTimeOutType xTimeOut;
configASSERT( pxQueue );
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );
/* This function relaxes the coding standard somewhat to allow return
statements within the function itself. This is done in the interest
of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
{
/* Is there room on the queue now? To be running we must be
the highest priority task wanting to access the queue. */
if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
{
traceQUEUE_SEND( pxQueue );
prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
portYIELD_WITHIN_API();
}
}
taskEXIT_CRITICAL();
/* Return to the original privilege level before exiting the
function. */
return pdPASS;
}
else
{
if( xTicksToWait == ( portTickType ) 0 )
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
}
else if( xEntryTimeSet == pdFALSE )
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskSetTimeOutState( &xTimeOut );
xEntryTimeSet = pdTRUE;
}
}
}
taskEXIT_CRITICAL();
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
prvLockQueue( pxQueue );
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
{
portYIELD_WITHIN_API();
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
( void ) xTaskResumeAll();
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
( void ) xTaskResumeAll();
/* Return to the original privilege level before exiting the
function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
}
}
}
/*-----------------------------------------------------------*/
#if configUSE_ALTERNATIVE_API == 1
signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )
{
signed portBASE_TYPE xEntryTimeSet = pdFALSE;
xTimeOutType xTimeOut;
configASSERT( pxQueue );
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );
for( ;; )
{
taskENTER_CRITICAL();
{
/* Is there room on the queue now? To be running we must be
the highest priority task wanting to access the queue. */
if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
{
traceQUEUE_SEND( pxQueue );
prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
{
/* The unblocked task has a priority higher than
our own so yield immediately. */
portYIELD_WITHIN_API();
}
}
taskEXIT_CRITICAL();
return pdPASS;
}
else
{
if( xTicksToWait == ( portTickType ) 0 )
{
taskEXIT_CRITICAL();
return errQUEUE_FULL;
}
else if( xEntryTimeSet == pdFALSE )
{
vTaskSetTimeOutState( &xTimeOut );
xEntryTimeSet = pdTRUE;
}
}
}
taskEXIT_CRITICAL();
taskENTER_CRITICAL();
{
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
portYIELD_WITHIN_API();
}
}
else
{
taskEXIT_CRITICAL();
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
}
}
taskEXIT_CRITICAL();
}
}
#endif /* configUSE_ALTERNATIVE_API */
/*-----------------------------------------------------------*/
#if configUSE_ALTERNATIVE_API == 1
signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )
{
signed portBASE_TYPE xEntryTimeSet = pdFALSE;
xTimeOutType xTimeOut;
signed char *pcOriginalReadPosition;
configASSERT( pxQueue );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );
for( ;; )
{
taskENTER_CRITICAL();
{
if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
{
/* Remember our read position in case we are just peeking. */
pcOriginalReadPosition = pxQueue->pcReadFrom;
prvCopyDataFromQueue( pxQueue, pvBuffer );
if( xJustPeeking == pdFALSE )
{
traceQUEUE_RECEIVE( pxQueue );
/* We are actually removing data. */
--( pxQueue->uxMessagesWaiting );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
/* Record the information required to implement
priority inheritance should it become necessary. */
pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle();
}
}
#endif
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
{
portYIELD_WITHIN_API();
}
}
}
else
{
traceQUEUE_PEEK( pxQueue );
/* We are not removing the data, so reset our read
pointer. */
pxQueue->pcReadFrom = pcOriginalReadPosition;
/* The data is being left in the queue, so see if there are
any other tasks waiting for the data. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority than this task. */
portYIELD_WITHIN_API();
}
}
}
taskEXIT_CRITICAL();
return pdPASS;
}
else
{
if( xTicksToWait == ( portTickType ) 0 )
{
taskEXIT_CRITICAL();
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
}
else if( xEntryTimeSet == pdFALSE )
{
vTaskSetTimeOutState( &xTimeOut );
xEntryTimeSet = pdTRUE;
}
}
}
taskEXIT_CRITICAL();
taskENTER_CRITICAL();
{
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
{
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
portENTER_CRITICAL();
vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
portEXIT_CRITICAL();
}
}
#endif
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
portYIELD_WITHIN_API();
}
}
else
{
taskEXIT_CRITICAL();
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
}
}
taskEXIT_CRITICAL();
}
}
#endif /* configUSE_ALTERNATIVE_API */
/*-----------------------------------------------------------*/
signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition )
{
signed portBASE_TYPE xReturn;
unsigned portBASE_TYPE uxSavedInterruptStatus;
configASSERT( pxQueue );
configASSERT( pxHigherPriorityTaskWoken );
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );
/* Similar to xQueueGenericSend, except we don't block if there is no room
in the queue. Also we don't directly wake a task that was blocked on a
queue read, instead we return a flag to say whether a context switch is
required or not (i.e. has a task with a higher priority than us been woken
by this post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
{
traceQUEUE_SEND_FROM_ISR( pxQueue );
prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
/* If the queue is locked we do not alter the event list. This will
be done when the queue is unlocked later. */
if( pxQueue->xTxLock == queueUNLOCKED )
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
*pxHigherPriorityTaskWoken = pdTRUE;
}
}
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
++( pxQueue->xTxLock );
}
xReturn = pdPASS;
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )
{
signed portBASE_TYPE xEntryTimeSet = pdFALSE;
xTimeOutType xTimeOut;
signed char *pcOriginalReadPosition;
configASSERT( pxQueue );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );
/* This function relaxes the coding standard somewhat to allow return
statements within the function itself. This is done in the interest
of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
{
/* Is there data in the queue now? To be running we must be
the highest priority task wanting to access the queue. */
if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
{
/* Remember our read position in case we are just peeking. */
pcOriginalReadPosition = pxQueue->pcReadFrom;
prvCopyDataFromQueue( pxQueue, pvBuffer );
if( xJustPeeking == pdFALSE )
{
traceQUEUE_RECEIVE( pxQueue );
/* We are actually removing data. */
--( pxQueue->uxMessagesWaiting );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
/* Record the information required to implement
priority inheritance should it become necessary. */
pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle();
}
}
#endif
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
{
portYIELD_WITHIN_API();
}
}
}
else
{
traceQUEUE_PEEK( pxQueue );
/* We are not removing the data, so reset our read
pointer. */
pxQueue->pcReadFrom = pcOriginalReadPosition;
/* The data is being left in the queue, so see if there are
any other tasks waiting for the data. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority than this task. */
portYIELD_WITHIN_API();
}
}
}
taskEXIT_CRITICAL();
return pdPASS;
}
else
{
if( xTicksToWait == ( portTickType ) 0 )
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
}
else if( xEntryTimeSet == pdFALSE )
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskSetTimeOutState( &xTimeOut );
xEntryTimeSet = pdTRUE;
}
}
}
taskEXIT_CRITICAL();
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
prvLockQueue( pxQueue );
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
{
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
portENTER_CRITICAL();
{
vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
}
portEXIT_CRITICAL();
}
}
#endif
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
prvUnlockQueue( pxQueue );
if( xTaskResumeAll() == pdFALSE )
{
portYIELD_WITHIN_API();
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
( void ) xTaskResumeAll();
}
}
else
{
prvUnlockQueue( pxQueue );
( void ) xTaskResumeAll();
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
}
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken )
{
signed portBASE_TYPE xReturn;
unsigned portBASE_TYPE uxSavedInterruptStatus;
configASSERT( pxQueue );
configASSERT( pxTaskWoken );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
/* We cannot block from an ISR, so check there is data available. */
if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
{
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
prvCopyDataFromQueue( pxQueue, pvBuffer );
--( pxQueue->uxMessagesWaiting );
/* If the queue is locked we will not modify the event list. Instead
we update the lock count so the task that unlocks the queue will know
that an ISR has removed data while the queue was locked. */
if( pxQueue->xRxLock == queueUNLOCKED )
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
{
/* The task waiting has a higher priority than us so
force a context switch. */
*pxTaskWoken = pdTRUE;
}
}
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was removed while it was locked. */
++( pxQueue->xRxLock );
}
xReturn = pdPASS;
}
else
{
xReturn = pdFAIL;
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
}
/*-----------------------------------------------------------*/
unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue )
{
unsigned portBASE_TYPE uxReturn;
configASSERT( pxQueue );
taskENTER_CRITICAL();
uxReturn = pxQueue->uxMessagesWaiting;
taskEXIT_CRITICAL();
return uxReturn;
}
/*-----------------------------------------------------------*/
unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue )
{
unsigned portBASE_TYPE uxReturn;
configASSERT( pxQueue );
uxReturn = pxQueue->uxMessagesWaiting;
return uxReturn;
}
/*-----------------------------------------------------------*/
void vQueueDelete( xQueueHandle pxQueue )
{
configASSERT( pxQueue );
traceQUEUE_DELETE( pxQueue );
vQueueUnregisterQueue( pxQueue );
vPortFree( pxQueue->pcHead );
vPortFree( pxQueue );
}
/*-----------------------------------------------------------*/
static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition )
{
if( pxQueue->uxItemSize == ( unsigned portBASE_TYPE ) 0 )
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
/* The mutex is no longer being held. */
vTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
pxQueue->pxMutexHolder = NULL;
}
}
#endif
}
else if( xPosition == queueSEND_TO_BACK )
{
memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize );
pxQueue->pcWriteTo += pxQueue->uxItemSize;
if( pxQueue->pcWriteTo >= pxQueue->pcTail )
{
pxQueue->pcWriteTo = pxQueue->pcHead;
}
}
else
{
memcpy( ( void * ) pxQueue->pcReadFrom, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize );
pxQueue->pcReadFrom -= pxQueue->uxItemSize;
if( pxQueue->pcReadFrom < pxQueue->pcHead )
{
pxQueue->pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
}
}
++( pxQueue->uxMessagesWaiting );
}
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer )
{
if( pxQueue->uxQueueType != queueQUEUE_IS_MUTEX )
{
pxQueue->pcReadFrom += pxQueue->uxItemSize;
if( pxQueue->pcReadFrom >= pxQueue->pcTail )
{
pxQueue->pcReadFrom = pxQueue->pcHead;
}
memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
}
}
/*-----------------------------------------------------------*/
static void prvUnlockQueue( xQueueHandle pxQueue )
{
/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
{
/* See if data was added to the queue while it was locked. */
while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )
{
/* Data was posted while the queue was locked. Are any tasks
blocked waiting for data to become available? */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The task waiting has a higher priority so record that a
context switch is required. */
vTaskMissedYield();
}
--( pxQueue->xTxLock );
}
else
{
break;
}
}
pxQueue->xTxLock = queueUNLOCKED;
}
taskEXIT_CRITICAL();
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
{
while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
{
vTaskMissedYield();
}
--( pxQueue->xRxLock );
}
else
{
break;
}
}
pxQueue->xRxLock = queueUNLOCKED;
}
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue )
{
signed portBASE_TYPE xReturn;
taskENTER_CRITICAL();
xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );
taskEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue )
{
signed portBASE_TYPE xReturn;
configASSERT( pxQueue );
xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );
return xReturn;
}
/*-----------------------------------------------------------*/
static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue )
{
signed portBASE_TYPE xReturn;
taskENTER_CRITICAL();
xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );
taskEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue )
{
signed portBASE_TYPE xReturn;
configASSERT( pxQueue );
xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );
return xReturn;
}
/*-----------------------------------------------------------*/
#if configUSE_CO_ROUTINES == 1
signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )
{
signed portBASE_TYPE xReturn;
/* If the queue is already full we may have to block. A critical section
is required to prevent an interrupt removing something from the queue
between the check to see if the queue is full and blocking on the queue. */
portDISABLE_INTERRUPTS();
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
{
/* The queue is full - do we want to block or just leave without
posting? */
if( xTicksToWait > ( portTickType ) 0 )
{
/* As this is called from a coroutine we cannot block directly, but
return indicating that we need to block. */
vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
portENABLE_INTERRUPTS();
return errQUEUE_BLOCKED;
}
else
{
portENABLE_INTERRUPTS();
return errQUEUE_FULL;
}
}
}
portENABLE_INTERRUPTS();
portNOP();
portDISABLE_INTERRUPTS();
{
if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
{
/* There is room in the queue, copy the data into the queue. */
prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
xReturn = pdPASS;
/* Were any co-routines waiting for data to become available? */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
/* In this instance the co-routine could be placed directly
into the ready list as we are within a critical section.
Instead the same pending ready list mechanism is used as if
the event were caused from within an interrupt. */
if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The co-routine waiting has a higher priority so record
that a yield might be appropriate. */
xReturn = errQUEUE_YIELD;
}
}
}
else
{
xReturn = errQUEUE_FULL;
}
}
portENABLE_INTERRUPTS();
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
#if configUSE_CO_ROUTINES == 1
signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )
{
signed portBASE_TYPE xReturn;
/* If the queue is already empty we may have to block. A critical section
is required to prevent an interrupt adding something to the queue
between the check to see if the queue is empty and blocking on the queue. */
portDISABLE_INTERRUPTS();
{
if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 )
{
/* There are no messages in the queue, do we want to block or just
leave with nothing? */
if( xTicksToWait > ( portTickType ) 0 )
{
/* As this is a co-routine we cannot block directly, but return
indicating that we need to block. */
vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
portENABLE_INTERRUPTS();
return errQUEUE_BLOCKED;
}
else
{
portENABLE_INTERRUPTS();
return errQUEUE_FULL;
}
}
}
portENABLE_INTERRUPTS();
portNOP();
portDISABLE_INTERRUPTS();
{
if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
{
/* Data is available from the queue. */
pxQueue->pcReadFrom += pxQueue->uxItemSize;
if( pxQueue->pcReadFrom >= pxQueue->pcTail )
{
pxQueue->pcReadFrom = pxQueue->pcHead;
}
--( pxQueue->uxMessagesWaiting );
memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
xReturn = pdPASS;
/* Were any co-routines waiting for space to become available? */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
/* In this instance the co-routine could be placed directly
into the ready list as we are within a critical section.
Instead the same pending ready list mechanism is used as if
the event were caused from within an interrupt. */
if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
{
xReturn = errQUEUE_YIELD;
}
}
}
else
{
xReturn = pdFAIL;
}
}
portENABLE_INTERRUPTS();
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
#if configUSE_CO_ROUTINES == 1
signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken )
{
/* Cannot block within an ISR so if there is no space on the queue then
exit without doing anything. */
if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
{
prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
/* We only want to wake one co-routine per ISR, so check that a
co-routine has not already been woken. */
if( xCoRoutinePreviouslyWoken == pdFALSE )
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
return pdTRUE;
}
}
}
}
return xCoRoutinePreviouslyWoken;
}
#endif
/*-----------------------------------------------------------*/
#if configUSE_CO_ROUTINES == 1
signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken )
{
signed portBASE_TYPE xReturn;
/* We cannot block from an ISR, so check there is data available. If
not then just leave without doing anything. */
if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
{
/* Copy the data from the queue. */
pxQueue->pcReadFrom += pxQueue->uxItemSize;
if( pxQueue->pcReadFrom >= pxQueue->pcTail )
{
pxQueue->pcReadFrom = pxQueue->pcHead;
}
--( pxQueue->uxMessagesWaiting );
memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
if( ( *pxCoRoutineWoken ) == pdFALSE )
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
{
if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
{
*pxCoRoutineWoken = pdTRUE;
}
}
}
xReturn = pdPASS;
}
else
{
xReturn = pdFAIL;
}
return xReturn;
}
#endif
/*-----------------------------------------------------------*/
#if configQUEUE_REGISTRY_SIZE > 0
void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName )
{
unsigned portBASE_TYPE ux;
/* See if there is an empty space in the registry. A NULL name denotes
a free slot. */
for( ux = ( unsigned portBASE_TYPE ) 0U; ux < ( unsigned portBASE_TYPE ) configQUEUE_REGISTRY_SIZE; ux++ )
{
if( xQueueRegistry[ ux ].pcQueueName == NULL )
{
/* Store the information on this queue. */
xQueueRegistry[ ux ].pcQueueName = pcQueueName;
xQueueRegistry[ ux ].xHandle = xQueue;
break;
}
}
}
#endif
/*-----------------------------------------------------------*/
#if configQUEUE_REGISTRY_SIZE > 0
static void vQueueUnregisterQueue( xQueueHandle xQueue )
{
unsigned portBASE_TYPE ux;
/* See if the handle of the queue being unregistered in actually in the
registry. */
for( ux = ( unsigned portBASE_TYPE ) 0U; ux < ( unsigned portBASE_TYPE ) configQUEUE_REGISTRY_SIZE; ux++ )
{
if( xQueueRegistry[ ux ].xHandle == xQueue )
{
/* Set the name to NULL to show that this slot if free again. */
xQueueRegistry[ ux ].pcQueueName = NULL;
break;
}
}
}
#endif
/*-----------------------------------------------------------*/
#if configUSE_TIMERS == 1
void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait )
{
/* This function should not be called by application code hence the
'Restricted' in its name. It is not part of the public API. It is
designed for use by kernel code, and has special calling requirements.
It can result in vListInsert() being called on a list that can only
possibly ever have one item in it, so the list will be fast, but even
so it should be called with the scheduler locked and not from a critical
section. */
/* Only do anything if there are no messages in the queue. This function
will not actually cause the task to block, just place it on a blocked
list. It will not block until the scheduler is unlocked - at which
time a yield will be performed. If an item is added to the queue while
the queue is locked, and the calling task blocks on the queue, then the
calling task will be immediately unblocked when the queue is unlocked. */
prvLockQueue( pxQueue );
if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0U )
{
/* There is nothing in the queue, block for the specified period. */
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
}
prvUnlockQueue( pxQueue );
}
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/queue.c | C | oos | 51,545 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned short
#define portBASE_TYPE short
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 2
#define portSTACK_GROWTH 1
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portINTERRUPT_BITS ( ( unsigned portSHORT ) configKERNEL_INTERRUPT_PRIORITY << ( unsigned portSHORT ) 5 )
#define portDISABLE_INTERRUPTS() SR |= portINTERRUPT_BITS
#define portENABLE_INTERRUPTS() SR &= ~portINTERRUPT_BITS
/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter
what their value was prior to entering the critical section. */
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
extern void vPortYield( void );
#define portYIELD() asm volatile ( "CALL _vPortYield \n" \
"NOP " );
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/* Required by the kernel aware debugger. */
#ifdef __DEBUG
#define portREMOVE_STATIC_QUALIFIER
#endif
#define portNOP() asm volatile ( "NOP" )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h | C | oos | 5,582 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
.global _vPortYield
.extern _vTaskSwitchContext
.extern uxCriticalNesting
_vPortYield:
PUSH SR /* Save the SR used by the task.... */
PUSH W0 /* ....then disable interrupts. */
MOV #32, W0
MOV W0, SR
PUSH W1 /* Save registers to the stack. */
PUSH.D W2
PUSH.D W4
PUSH.D W6
PUSH.D W8
PUSH.D W10
PUSH.D W12
PUSH W14
PUSH RCOUNT
PUSH TBLPAG
PUSH CORCON
PUSH PSVPAG
MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */
PUSH W0
MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */
MOV W15, [W0]
call _vTaskSwitchContext
MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */
MOV [W0], W15
POP W0 /* Restore the critical nesting counter for the task. */
MOV W0, _uxCriticalNesting
POP PSVPAG
POP CORCON
POP TBLPAG
POP RCOUNT /* Restore the registers from the stack. */
POP W14
POP.D W12
POP.D W10
POP.D W8
POP.D W6
POP.D W4
POP.D W2
POP.D W0
POP SR
return
.end
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S | Unix Assembly | oos | 4,111 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
Changes from V4.2.1
+ Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the PIC24 port.
*----------------------------------------------------------*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Hardware specifics. */
#define portBIT_SET 1
#define portTIMER_PRESCALE 8
#define portINITIAL_SR 0
/* Defined for backward compatability with project created prior to
FreeRTOS.org V4.3.0. */
#ifndef configKERNEL_INTERRUPT_PRIORITY
#define configKERNEL_INTERRUPT_PRIORITY 1
#endif
/* The program counter is only 23 bits. */
#define portUNUSED_PR_BITS 0x7f
/* Records the nesting depth of calls to portENTER_CRITICAL(). */
unsigned portBASE_TYPE uxCriticalNesting = 0xef;
#if configKERNEL_INTERRUPT_PRIORITY != 1
#error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
#endif
#ifdef MPLAB_PIC24_PORT
#define portRESTORE_CONTEXT() \
asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
"MOV [W0], W15 \n" \
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
"MOV W0, _uxCriticalNesting \n" \
"POP PSVPAG \n" \
"POP CORCON \n" \
"POP TBLPAG \n" \
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
"POP W14 \n" \
"POP.D W12 \n" \
"POP.D W10 \n" \
"POP.D W8 \n" \
"POP.D W6 \n" \
"POP.D W4 \n" \
"POP.D W2 \n" \
"POP.D W0 \n" \
"POP SR " );
#endif /* MPLAB_PIC24_PORT */
#ifdef MPLAB_DSPIC_PORT
#define portRESTORE_CONTEXT() \
asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
"MOV [W0], W15 \n" \
"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
"MOV W0, _uxCriticalNesting \n" \
"POP PSVPAG \n" \
"POP CORCON \n" \
"POP DOENDH \n" \
"POP DOENDL \n" \
"POP DOSTARTH \n" \
"POP DOSTARTL \n" \
"POP DCOUNT \n" \
"POP ACCBU \n" \
"POP ACCBH \n" \
"POP ACCBL \n" \
"POP ACCAU \n" \
"POP ACCAH \n" \
"POP ACCAL \n" \
"POP TBLPAG \n" \
"POP RCOUNT \n" /* Restore the registers from the stack. */ \
"POP W14 \n" \
"POP.D W12 \n" \
"POP.D W10 \n" \
"POP.D W8 \n" \
"POP.D W6 \n" \
"POP.D W4 \n" \
"POP.D W2 \n" \
"POP.D W0 \n" \
"POP SR " );
#endif /* MPLAB_DSPIC_PORT */
/*
* Setup the timer used to generate the tick interrupt.
*/
static void prvSetupTimerInterrupt( void );
/*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
unsigned short usCode;
portBASE_TYPE i;
const portSTACK_TYPE xInitialStack[] =
{
0x1111, /* W1 */
0x2222, /* W2 */
0x3333, /* W3 */
0x4444, /* W4 */
0x5555, /* W5 */
0x6666, /* W6 */
0x7777, /* W7 */
0x8888, /* W8 */
0x9999, /* W9 */
0xaaaa, /* W10 */
0xbbbb, /* W11 */
0xcccc, /* W12 */
0xdddd, /* W13 */
0xeeee, /* W14 */
0xcdce, /* RCOUNT */
0xabac, /* TBLPAG */
/* dsPIC specific registers. */
#ifdef MPLAB_DSPIC_PORT
0x0202, /* ACCAL */
0x0303, /* ACCAH */
0x0404, /* ACCAU */
0x0505, /* ACCBL */
0x0606, /* ACCBH */
0x0707, /* ACCBU */
0x0808, /* DCOUNT */
0x090a, /* DOSTARTL */
0x1010, /* DOSTARTH */
0x1110, /* DOENDL */
0x1212, /* DOENDH */
#endif
};
/* Setup the stack as if a yield had occurred.
Save the low bytes of the program counter. */
usCode = ( unsigned short ) pxCode;
*pxTopOfStack = ( portSTACK_TYPE ) usCode;
pxTopOfStack++;
/* Save the high byte of the program counter. This will always be zero
here as it is passed in a 16bit pointer. If the address is greater than
16 bits then the pointer will point to a jump table. */
*pxTopOfStack = ( portSTACK_TYPE ) 0;
pxTopOfStack++;
/* Status register with interrupts enabled. */
*pxTopOfStack = portINITIAL_SR;
pxTopOfStack++;
/* Parameters are passed in W0. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
pxTopOfStack++;
for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( portSTACK_TYPE ) ); i++ )
{
*pxTopOfStack = xInitialStack[ i ];
pxTopOfStack++;
}
*pxTopOfStack = CORCON;
pxTopOfStack++;
*pxTopOfStack = PSVPAG;
pxTopOfStack++;
/* Finally the critical nesting depth. */
*pxTopOfStack = 0x00;
pxTopOfStack++;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
/* Setup a timer for the tick ISR. */
prvSetupTimerInterrupt();
/* Restore the context of the first task to run. */
portRESTORE_CONTEXT();
/* Simulate the end of the yield function. */
asm volatile ( "return" );
/* Should not reach here. */
return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the scheduler for the PIC port will get stopped
once running. If required disable the tick interrupt here, then return
to xPortStartScheduler(). */
}
/*-----------------------------------------------------------*/
/*
* Setup a timer for a regular tick.
*/
static void prvSetupTimerInterrupt( void )
{
const unsigned long ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
/* Prescale of 8. */
T1CON = 0;
TMR1 = 0;
PR1 = ( unsigned short ) ulCompareMatch;
/* Setup timer 1 interrupt priority. */
IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
/* Clear the interrupt as a starting condition. */
IFS0bits.T1IF = 0;
/* Enable the interrupt. */
IEC0bits.T1IE = 1;
/* Setup the prescale value. */
T1CONbits.TCKPS0 = 1;
T1CONbits.TCKPS1 = 0;
/* Start the timer. */
T1CONbits.TON = 1;
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
}
/*-----------------------------------------------------------*/
void __attribute__((__interrupt__, auto_psv)) _T1Interrupt( void )
{
/* Clear the timer interrupt. */
IFS0bits.T1IF = 0;
vTaskIncrementTick();
#if configUSE_PREEMPTION == 1
portYIELD();
#endif
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC24_dsPIC/port.c | C | oos | 10,614 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
.global _vPortYield
.extern _vTaskSwitchContext
.extern uxCriticalNesting
_vPortYield:
PUSH SR /* Save the SR used by the task.... */
PUSH W0 /* ....then disable interrupts. */
MOV #32, W0
MOV W0, SR
PUSH W1 /* Save registers to the stack. */
PUSH.D W2
PUSH.D W4
PUSH.D W6
PUSH.D W8
PUSH.D W10
PUSH.D W12
PUSH W14
PUSH RCOUNT
PUSH TBLPAG
PUSH ACCAL
PUSH ACCAH
PUSH ACCAU
PUSH ACCBL
PUSH ACCBH
PUSH ACCBU
PUSH DCOUNT
PUSH DOSTARTL
PUSH DOSTARTH
PUSH DOENDL
PUSH DOENDH
PUSH CORCON
PUSH PSVPAG
MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */
PUSH W0
MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */
MOV W15, [W0]
call _vTaskSwitchContext
MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */
MOV [W0], W15
POP W0 /* Restore the critical nesting counter for the task. */
MOV W0, _uxCriticalNesting
POP PSVPAG
POP CORCON
POP DOENDH
POP DOENDL
POP DOSTARTH
POP DOSTARTL
POP DCOUNT
POP ACCBU
POP ACCBH
POP ACCBL
POP ACCAU
POP ACCAH
POP ACCAL
POP TBLPAG
POP RCOUNT /* Restore the registers from the stack. */
POP W14
POP.D W12
POP.D W10
POP.D W8
POP.D W6
POP.D W4
POP.D W2
POP.D W0
POP SR
return
.end
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S | Unix Assembly | oos | 4,441 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include <p32xxxx.h>
#include <sys/asm.h>
#include "ISR_Support.h"
.set nomips16
.set noreorder
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vPortIncrementTick
.extern xISRStackTop
.global vPortStartFirstTask
.global vPortYieldISR
.global vT1InterruptHandler
/******************************************************************/
.set noreorder
.set noat
.ent vT1InterruptHandler
vT1InterruptHandler:
portSAVE_CONTEXT
jal vPortIncrementTick
nop
portRESTORE_CONTEXT
.end vT1InterruptHandler
/******************************************************************/
.set noreorder
.set noat
.ent xPortStartScheduler
vPortStartFirstTask:
/* Simply restore the context of the highest priority task that has been
created so far. */
portRESTORE_CONTEXT
.end xPortStartScheduler
/*******************************************************************/
.set noreorder
.set noat
.ent vPortYieldISR
vPortYieldISR:
/* Make room for the context. First save the current status so we can
manipulate it, and the cause and EPC registers so we capture their
original values in case of interrupt nesting. */
mfc0 k0, _CP0_CAUSE
addiu sp, sp, -portCONTEXT_SIZE
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so we can use them during this interrupt. Any
nesting interrupts should maintain the values of these registers
across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Enable interrupts above the current priority. */
srl k0, k0, 0xa
ins k1, k0, 10, 6
ins k1, zero, 1, 4
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Swap to the system stack. This is not conditional on the nesting
count as this interrupt is always the lowest priority and therefore
the nesting is always 0. */
la sp, xISRStackTop
lw sp, (sp)
/* Set the nesting count. */
la k0, uxInterruptNesting
addiu s6, zero, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved with the rest of the context
after interrupts are enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s7, 48(s5)
sw s6, portEPC_STACK_LOCATION(s5)
/* s5 and s6 has already been saved. */
sw s4, 36(s5)
sw s3, 32(s5)
sw s2, 28(s5)
sw s1, 24(s5)
sw s0, 20(s5)
sw $1, 16(s5)
/* s7 is used as a scratch register as this should always be saved across
nesting interrupts. */
mfhi s7
sw s7, 12(s5)
mflo s7
sw s7, 8(s5)
/* Save the stack pointer to the task. */
la s7, pxCurrentTCB
lw s7, (s7)
sw s5, (s7)
/* Set the interrupt mask to the max priority that can use the API. The
yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
raise the IPL value and never lower it. */
di
mfc0 s7, _CP0_STATUS
ins s7, $0, 10, 6
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
/* This mtc0 re-enables interrupts, but only above
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 s6, _CP0_STATUS
/* Clear the software interrupt in the core. */
mfc0 s6, _CP0_CAUSE
addiu s4,zero,-257
and s6, s6, s4
mtc0 s6, _CP0_CAUSE
/* Clear the interrupt in the interrupt controller. */
la s6, IFS0CLR
addiu s4, zero, 2
sw s4, (s6)
jal vTaskSwitchContext
nop
/* Clear the interrupt mask again. The saved status value is still in s7. */
mtc0 s7, _CP0_STATUS
/* Restore the stack pointer from the TCB. */
la s0, pxCurrentTCB
lw s0, (s0)
lw s5, (s0)
/* Restore the rest of the context. */
lw s0, 8(s5)
mtlo s0
lw s0, 12(s5)
mthi s0
lw $1, 16(s5)
lw s0, 20(s5)
lw s1, 24(s5)
lw s2, 28(s5)
lw s3, 32(s5)
lw s4, 36(s5)
/* s5 is loaded later. */
lw s6, 44(s5)
lw s7, 48(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
/* Set nesting back to zero. As the lowest priority interrupt this
interrupt cannot have nested. */
la k0, uxInterruptNesting
sw zero, 0(k0)
/* Switch back to use the real stack pointer. */
add sp, zero, s5
/* Restore the real s5 value. */
lw s5, 40(sp)
/* Pop the status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
/* Remove stack frame. */
addiu sp, sp, portCONTEXT_SIZE
mtc0 k1, _CP0_STATUS
mtc0 k0, _CP0_EPC
ehb
eret
nop
.end vPortYieldISR
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC32MX/port_asm.S | Motorola 68K Assembly | oos | 8,379 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* System include files */
#include <plib.h>
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned long
#define portBASE_TYPE long
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned long portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 8
#define portSTACK_GROWTH -1
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portIPL_SHIFT ( 10UL )
#define portALL_IPL_BITS ( 0x3fUL << portIPL_SHIFT )
#define portSW0_BIT ( 0x01 << 8 )
/* This clears the IPL bits, then sets them to
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
from an interrupt, so therefore will not be called with an IPL setting
above configMAX_SYSCALL_INTERRUPT_PRIORITY. Therefore, when used correctly, the
instructions in this macro can only result in the IPL being raised, and
therefore never lowered. */
#define portDISABLE_INTERRUPTS() \
{ \
unsigned long ulStatus; \
\
/* Mask interrupts at and below the kernel interrupt priority. */ \
ulStatus = _CP0_GET_STATUS(); \
ulStatus &= ~portALL_IPL_BITS; \
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
}
#define portENABLE_INTERRUPTS() \
{ \
unsigned long ulStatus; \
\
/* Unmask all interrupts. */ \
ulStatus = _CP0_GET_STATUS(); \
ulStatus &= ~portALL_IPL_BITS; \
_CP0_SET_STATUS( ulStatus ); \
}
extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void );
#define portCRITICAL_NESTING_IN_TCB 1
#define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical()
extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR();
extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE );
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portYIELD() \
{ \
unsigned long ulStatus; \
\
/* Trigger software interrupt. */ \
ulStatus = _CP0_GET_CAUSE(); \
ulStatus |= portSW0_BIT; \
_CP0_SET_CAUSE( ulStatus ); \
}
#define portNOP() asm volatile ( "nop" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
{ \
portYIELD(); \
}
/* Required by the kernel aware debugger. */
#ifdef __DEBUG
#define portREMOVE_STATIC_QUALIFIER
#endif
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC32MX/portmacro.h | C | oos | 7,095 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include "FreeRTOSConfig.h"
#define portCONTEXT_SIZE 132
#define portEPC_STACK_LOCATION 124
#define portSTATUS_STACK_LOCATION 128
/******************************************************************/
.macro portSAVE_CONTEXT
/* Make room for the context. First save the current status so we can
manipulate it, and the cause and EPC registers so we capture their
original values in case of interrupt nesting. */
mfc0 k0, _CP0_CAUSE
addiu sp, sp, -portCONTEXT_SIZE
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so we can use them during this interrupt. Any
nesting interrupts should maintain the values of these registers
across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Enable interrupts above the current priority. */
srl k0, k0, 0xa
ins k1, k0, 10, 6
ins k1, zero, 1, 4
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Check the nesting count value. */
la k0, uxInterruptNesting
lw s6, (k0)
/* If the nesting count is 0 then swap to the the system stack, otherwise
the system stack is already being used. */
bne s6, zero, .+20
nop
/* Swap to the system stack. */
la sp, xISRStackTop
lw sp, (sp)
/* Increment and save the nesting count. */
addiu s6, s6, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. No other s registers need be
saved. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s6, portEPC_STACK_LOCATION(s5)
sw $1, 16(s5)
/* s6 is used as a scratch register. */
mfhi s6
sw s6, 12(s5)
mflo s6
sw s6, 8(s5)
/* Update the task stack pointer value if nesting is zero. */
la s6, uxInterruptNesting
lw s6, (s6)
addiu s6, s6, -1
bne s6, zero, .+20
nop
/* Save the stack pointer. */
la s6, uxSavedTaskStackPointer
sw s5, (s6)
.endm
/******************************************************************/
.macro portRESTORE_CONTEXT
/* Restore the stack pointer from the TCB. This is only done if the
nesting count is 1. */
la s6, uxInterruptNesting
lw s6, (s6)
addiu s6, s6, -1
bne s6, zero, .+20
nop
la s6, uxSavedTaskStackPointer
lw s5, (s6)
/* Restore the context. */
lw s6, 8(s5)
mtlo s6
lw s6, 12(s5)
mthi s6
lw $1, 16(s5)
/* s6 is loaded as it was used as a scratch register and therefore saved
as part of the interrupt context. */
lw s6, 44(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
/* Decrement the nesting count. */
la k0, uxInterruptNesting
lw k1, (k0)
addiu k1, k1, -1
sw k1, 0(k0)
lw k0, portSTATUS_STACK_LOCATION(s5)
lw k1, portEPC_STACK_LOCATION(s5)
/* Leave the stack how we found it. First load sp from s5, then restore
s5 from the stack. */
add sp, zero, s5
lw s5, 40(sp)
addiu sp, sp, portCONTEXT_SIZE
mtc0 k0, _CP0_STATUS
mtc0 k1, _CP0_EPC
ehb
eret
nop
.endm
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC32MX/ISR_Support.h | C | oos | 6,794 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the PIC32MX port.
*----------------------------------------------------------*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Hardware specifics. */
#define portTIMER_PRESCALE 8
/* Bits within various registers. */
#define portIE_BIT ( 0x00000001 )
#define portEXL_BIT ( 0x00000002 )
/* The EXL bit is set to ensure interrupts do not occur while the context of
the first task is being restored. */
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
/* Records the interrupt nesting depth. This starts at one as it will be
decremented to 0 when the first task starts. */
volatile unsigned portBASE_TYPE uxInterruptNesting = 0x01;
/* Stores the task stack pointer when a switch is made to use the system stack. */
unsigned portBASE_TYPE uxSavedTaskStackPointer = 0;
/* The stack used by interrupt service routines that cause a context switch. */
portSTACK_TYPE xISRStack[ configISR_STACK_SIZE ] = { 0 };
/* The top of stack value ensures there is enough space to store 6 registers on
the callers stack, as some functions seem to want to do this. */
const portSTACK_TYPE * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
/*
* Place the prototype here to ensure the interrupt vector is correctly installed.
* Note that because the interrupt is written in assembly, the IPL setting in the
* following line of code has no effect. The interrupt priority is set by the
* call to ConfigIntTimer1() in prvSetupTimerInterrupt().
*/
extern void __attribute__( (interrupt(ipl1), vector(_TIMER_1_VECTOR))) vT1InterruptHandler( void );
/*
* The software interrupt handler that performs the yield. Note that, because
* the interrupt is written in assembly, the IPL setting in the following line of
* code has no effect. The interrupt priority is set by the call to
* mConfigIntCoreSW0() in xPortStartScheduler().
*/
void __attribute__( (interrupt(ipl1), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
/* Ensure byte alignment is maintained when leaving this function. */
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) 0xDEADBEEF;
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) _CP0_GET_CAUSE();
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) portINITIAL_SR; /* CP0_STATUS */
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) pxCode; /* CP0_EPC */
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) NULL; /* ra */
pxTopOfStack -= 15;
*pxTopOfStack = (portSTACK_TYPE) pvParameters; /* Parameters to pass in */
pxTopOfStack -= 14;
*pxTopOfStack = (portSTACK_TYPE) 0x00000000; /* critical nesting level - no longer used. */
pxTopOfStack--;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
/*
* Setup a timer for a regular tick.
*/
void prvSetupTimerInterrupt( void )
{
const unsigned long ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
OpenTimer1( ( T1_ON | T1_PS_1_8 | T1_SOURCE_INT ), ulCompareMatch );
ConfigIntTimer1( T1_INT_ON | configKERNEL_INTERRUPT_PRIORITY );
}
/*-----------------------------------------------------------*/
void vPortEndScheduler(void)
{
/* It is unlikely that the scheduler for the PIC port will get stopped
once running. If required disable the tick interrupt here, then return
to xPortStartScheduler(). */
for( ;; );
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
extern void *pxCurrentTCB;
/* Setup the software interrupt. */
mConfigIntCoreSW0( CSW_INT_ON | configKERNEL_INTERRUPT_PRIORITY | CSW_INT_SUB_PRIOR_0 );
/* Setup the timer to generate the tick. Interrupts will have been
disabled by the time we get here. */
prvSetupTimerInterrupt();
/* Kick off the highest priority task that has been created so far.
Its stack location is loaded into uxSavedTaskStackPointer. */
uxSavedTaskStackPointer = *( unsigned portBASE_TYPE * ) pxCurrentTCB;
vPortStartFirstTask();
/* Should never get here as the tasks will now be executing. */
return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortIncrementTick( void )
{
unsigned portBASE_TYPE uxSavedStatus;
uxSavedStatus = uxPortSetInterruptMaskFromISR();
vTaskIncrementTick();
vPortClearInterruptMaskFromISR( uxSavedStatus );
/* If we are using the preemptive scheduler then we might want to select
a different task to execute. */
#if configUSE_PREEMPTION == 1
SetCoreSW0();
#endif /* configUSE_PREEMPTION */
/* Clear timer 0 interrupt. */
mT1ClearIntFlag();
}
/*-----------------------------------------------------------*/
unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void )
{
unsigned portBASE_TYPE uxSavedStatusRegister;
asm volatile ( "di" );
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
/* This clears the IPL bits, then sets them to
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
from an interrupt that has a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
can only result in the IPL being unchanged or raised, and therefore never
lowered. */
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
return uxSavedStatusRegister;
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE uxSavedStatusRegister )
{
_CP0_SET_STATUS( uxSavedStatusRegister );
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC32MX/port.c | C | oos | 9,276 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT int
#define portSTACK_TYPE unsigned char
#define portBASE_TYPE char
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 1
#define portGLOBAL_INT_ENABLE_BIT 0x80
#define portSTACK_GROWTH 1
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0;
#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1;
/* Push the INTCON register onto the stack, then disable interrupts. */
#define portENTER_CRITICAL() POSTINC1 = INTCON; \
INTCONbits.GIEH = 0;
/* Retrieve the INTCON register from the stack, and enable interrupts
if they were saved as being enabled. Don't modify any other bits
within the INTCON register as these may have lagitimately have been
modified within the critical region. */
#define portEXIT_CRITICAL() _asm \
MOVF POSTDEC1, 1, 0 \
_endasm \
if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
{ \
portENABLE_INTERRUPTS(); \
}
/*-----------------------------------------------------------*/
/* Task utilities. */
extern void vPortYield( void );
#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
/* Required by the kernel aware debugger. */
#ifdef __DEBUG
#define portREMOVE_STATIC_QUALIFIER
#endif
#define portNOP() _asm \
NOP \
_endasm
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC18F/portmacro.h | C | oos | 5,673 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
Changes between V1.2.4 and V1.2.5
+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
interrupt flag setting. Using the two bits defined within
portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
before the test was performed.
Changes from V1.2.5
+ Set the interrupt vector address to 0x08. Previously it was at the
incorrect address for compatibility mode of 0x18.
Changes from V2.1.1
+ PCLATU and PCLATH are now saved as part of the context. This allows
function pointers to be used within tasks. Thanks to Javier Espeche
for the enhancement.
Changes from V2.3.1
+ TABLAT is now saved as part of the task context.
Changes from V3.2.0
+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
value and does not write to the register.
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* MPLAB library include file. */
#include "timers.h"
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the PIC port.
*----------------------------------------------------------*/
/* Hardware setup for tick. */
#define portTIMER_FOSC_SCALE ( ( unsigned long ) 4 )
/* Initial interrupt enable state for newly created tasks. This value is
copied into INTCON when a task switches in for the first time. */
#define portINITAL_INTERRUPT_STATE 0xc0
/* Just the bit within INTCON for the global interrupt flag. */
#define portGLOBAL_INTERRUPT_FLAG 0x80
/* Constant used for context switch macro when we require the interrupt
enable state to be unchanged when the interrupted task is switched back in. */
#define portINTERRUPTS_UNCHANGED 0x00
/* Some memory areas get saved as part of the task context. These memory
area's get used by the compiler for temporary storage, especially when
performing mathematical operations, or when using 32bit data types. This
constant defines the size of memory area which must be saved. */
#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned char ) 0x13 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
typedef void tskTCB;
extern volatile tskTCB * volatile pxCurrentTCB;
/* IO port constants. */
#define portBIT_SET ( ( unsigned char ) 1 )
#define portBIT_CLEAR ( ( unsigned char ) 0 )
/*
* The serial port ISR's are defined in serial.c, but are called from portable
* as they use the same vector as the tick ISR.
*/
void vSerialTxISR( void );
void vSerialRxISR( void );
/*
* Perform hardware setup to enable ticks.
*/
static void prvSetupTimerInterrupt( void );
/*
* ISR to maintain the tick, and perform tick context switches if the
* preemptive scheduler is being used.
*/
static void prvTickISR( void );
/*
* ISR placed on the low priority vector. This calls the appropriate ISR for
* the actual interrupt.
*/
static void prvLowInterrupt( void );
/*
* Macro that pushes all the registers that make up the context of a task onto
* the stack, then saves the new top of stack into the TCB.
*
* If this is called from an ISR then the interrupt enable bits must have been
* set for the ISR to ever get called. Therefore we want to save the INTCON
* register with the enable bits forced to be set - and ucForcedInterruptFlags
* must contain these bit settings. This means the interrupts will again be
* enabled when the interrupted task is switched back in.
*
* If this is called from a manual context switch (i.e. from a call to yield),
* then we want to save the INTCON so it is restored with its current state,
* and ucForcedInterruptFlags must be 0. This allows a yield from within
* a critical section.
*
* The compiler uses some locations at the bottom of the memory for temporary
* storage during math and other computations. This is especially true if
* 32bit data types are utilised (as they are by the scheduler). The .tmpdata
* and MATH_DATA sections have to be stored in there entirety as part of a task
* context. This macro stores from data address 0x00 to
* portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
* applications but you should check the map file for your project to ensure
* this is sufficient for your needs. It is not clear whether this size is
* fixed for all compilations or has the potential to be program specific.
*/
#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
{ \
_asm \
/* Save the status and WREG registers first, as these will get modified \
by the operations below. */ \
MOVFF WREG, PREINC1 \
MOVFF STATUS, PREINC1 \
/* Save the INTCON register with the appropriate bits forced if \
necessary - as described above. */ \
MOVFF INTCON, WREG \
IORLW ucForcedInterruptFlags \
MOVFF WREG, PREINC1 \
_endasm \
\
portDISABLE_INTERRUPTS(); \
\
_asm \
/* Store the necessary registers to the stack. */ \
MOVFF BSR, PREINC1 \
MOVFF FSR2L, PREINC1 \
MOVFF FSR2H, PREINC1 \
MOVFF FSR0L, PREINC1 \
MOVFF FSR0H, PREINC1 \
MOVFF TABLAT, PREINC1 \
MOVFF TBLPTRU, PREINC1 \
MOVFF TBLPTRH, PREINC1 \
MOVFF TBLPTRL, PREINC1 \
MOVFF PRODH, PREINC1 \
MOVFF PRODL, PREINC1 \
MOVFF PCLATU, PREINC1 \
MOVFF PCLATH, PREINC1 \
/* Store the .tempdata and MATH_DATA areas as described above. */ \
CLRF FSR0L, 0 \
CLRF FSR0H, 0 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF POSTINC0, PREINC1 \
MOVFF INDF0, PREINC1 \
MOVFF FSR0L, PREINC1 \
MOVFF FSR0H, PREINC1 \
/* Store the hardware stack pointer in a temp register before we \
modify it. */ \
MOVFF STKPTR, FSR0L \
_endasm \
\
/* Store each address from the hardware stack. */ \
while( STKPTR > ( unsigned char ) 0 ) \
{ \
_asm \
MOVFF TOSL, PREINC1 \
MOVFF TOSH, PREINC1 \
MOVFF TOSU, PREINC1 \
POP \
_endasm \
} \
\
_asm \
/* Store the number of addresses on the hardware stack (from the \
temporary register). */ \
MOVFF FSR0L, PREINC1 \
MOVF PREINC1, 1, 0 \
_endasm \
\
/* Save the new top of the software stack in the TCB. */ \
_asm \
MOVFF pxCurrentTCB, FSR0L \
MOVFF pxCurrentTCB + 1, FSR0H \
MOVFF FSR1L, POSTINC0 \
MOVFF FSR1H, POSTINC0 \
_endasm \
}
/*-----------------------------------------------------------*/
/*
* This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
* details.
*/
#define portRESTORE_CONTEXT() \
{ \
_asm \
/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
MOVFF pxCurrentTCB, FSR0L \
MOVFF pxCurrentTCB + 1, FSR0H \
\
/* De-reference FSR0 to set the address it holds into FSR1. \
(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
MOVFF POSTINC0, FSR1L \
MOVFF POSTINC0, FSR1H \
\
/* How many return addresses are there on the hardware stack? Discard \
the first byte as we are pointing to the next free space. */ \
MOVFF POSTDEC1, FSR0L \
MOVFF POSTDEC1, FSR0L \
_endasm \
\
/* Fill the hardware stack from our software stack. */ \
STKPTR = 0; \
\
while( STKPTR < FSR0L ) \
{ \
_asm \
PUSH \
MOVF POSTDEC1, 0, 0 \
MOVWF TOSU, 0 \
MOVF POSTDEC1, 0, 0 \
MOVWF TOSH, 0 \
MOVF POSTDEC1, 0, 0 \
MOVWF TOSL, 0 \
_endasm \
} \
\
_asm \
/* Restore the .tmpdata and MATH_DATA memory. */ \
MOVFF POSTDEC1, FSR0H \
MOVFF POSTDEC1, FSR0L \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, POSTDEC0 \
MOVFF POSTDEC1, INDF0 \
/* Restore the other registers forming the tasks context. */ \
MOVFF POSTDEC1, PCLATH \
MOVFF POSTDEC1, PCLATU \
MOVFF POSTDEC1, PRODL \
MOVFF POSTDEC1, PRODH \
MOVFF POSTDEC1, TBLPTRL \
MOVFF POSTDEC1, TBLPTRH \
MOVFF POSTDEC1, TBLPTRU \
MOVFF POSTDEC1, TABLAT \
MOVFF POSTDEC1, FSR0H \
MOVFF POSTDEC1, FSR0L \
MOVFF POSTDEC1, FSR2H \
MOVFF POSTDEC1, FSR2L \
MOVFF POSTDEC1, BSR \
/* The next byte is the INTCON register. Read this into WREG as some \
manipulation is required. */ \
MOVFF POSTDEC1, WREG \
_endasm \
\
/* From the INTCON register, only the interrupt enable bits form part \
of the tasks context. It is perfectly legitimate for another task to \
have modified any other bits. We therefore only restore the top two bits. \
*/ \
if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
{ \
_asm \
MOVFF POSTDEC1, STATUS \
MOVFF POSTDEC1, WREG \
/* Return enabling interrupts. */ \
RETFIE 0 \
_endasm \
} \
else \
{ \
_asm \
MOVFF POSTDEC1, STATUS \
MOVFF POSTDEC1, WREG \
/* Return without effecting interrupts. The context may have \
been saved from a critical region. */ \
RETURN 0 \
_endasm \
} \
}
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
unsigned long ulAddress;
unsigned char ucBlock;
/* Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging. */
*pxTopOfStack = 0x11;
pxTopOfStack++;
*pxTopOfStack = 0x22;
pxTopOfStack++;
*pxTopOfStack = 0x33;
pxTopOfStack++;
/* Simulate how the stack would look after a call to vPortYield() generated
by the compiler.
First store the function parameters. This is where the task will expect to
find them when it starts running. */
ulAddress = ( unsigned long ) pvParameters;
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
pxTopOfStack++;
ulAddress >>= 8;
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
pxTopOfStack++;
/* Next we just leave a space. When a context is saved the stack pointer
is incremented before it is used so as not to corrupt whatever the stack
pointer is actually pointing to. This is especially necessary during
function epilogue code generated by the compiler. */
*pxTopOfStack = 0x44;
pxTopOfStack++;
/* Next are all the registers that form part of the task context. */
*pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */
pxTopOfStack++;
/* INTCON is saved with interrupts enabled. */
*pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */
pxTopOfStack++;
/* Next the .tmpdata and MATH_DATA sections. */
for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
{
*pxTopOfStack = ( portSTACK_TYPE ) ucBlock;
*pxTopOfStack++;
}
/* Store the top of the global data section. */
*pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
pxTopOfStack++;
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */
pxTopOfStack++;
/* The only function return address so far is the address of the
task. */
ulAddress = ( unsigned long ) pxCode;
/* TOS low. */
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
pxTopOfStack++;
ulAddress >>= 8;
/* TOS high. */
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
pxTopOfStack++;
ulAddress >>= 8;
/* TOS even higher. */
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
pxTopOfStack++;
/* Store the number of return addresses on the hardware stack - so far only
the address of the task entry point. */
*pxTopOfStack = ( portSTACK_TYPE ) 1;
pxTopOfStack++;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
/* Setup a timer for the tick ISR is using the preemptive scheduler. */
prvSetupTimerInterrupt();
/* Restore the context of the first task to run. */
portRESTORE_CONTEXT();
/* Should not get here. Use the function name to stop compiler warnings. */
( void ) prvLowInterrupt;
( void ) prvTickISR;
return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the scheduler for the PIC port will get stopped
once running. If required disable the tick interrupt here, then return
to xPortStartScheduler(). */
}
/*-----------------------------------------------------------*/
/*
* Manual context switch. This is similar to the tick context switch,
* but does not increment the tick count. It must be identical to the
* tick context switch in how it stores the stack of a task.
*/
void vPortYield( void )
{
/* This can get called with interrupts either enabled or disabled. We
will save the INTCON register with the interrupt enable bits unmodified. */
portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
/* Switch to the highest priority task that is ready to run. */
vTaskSwitchContext();
/* Start executing the task we have just switched to. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
* Vector for ISR. Nothing here must alter any registers!
*/
#pragma code high_vector=0x08
static void prvLowInterrupt( void )
{
/* Was the interrupt the tick? */
if( PIR1bits.CCP1IF )
{
_asm
goto prvTickISR
_endasm
}
/* Was the interrupt a byte being received? */
if( PIR1bits.RCIF )
{
_asm
goto vSerialRxISR
_endasm
}
/* Was the interrupt the Tx register becoming empty? */
if( PIR1bits.TXIF )
{
if( PIE1bits.TXIE )
{
_asm
goto vSerialTxISR
_endasm
}
}
}
#pragma code
/*-----------------------------------------------------------*/
/*
* ISR for the tick.
* This increments the tick count and, if using the preemptive scheduler,
* performs a context switch. This must be identical to the manual
* context switch in how it stores the context of a task.
*/
static void prvTickISR( void )
{
/* Interrupts must have been enabled for the ISR to fire, so we have to
save the context with interrupts enabled. */
portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
PIR1bits.CCP1IF = 0;
/* Maintain the tick count. */
vTaskIncrementTick();
#if configUSE_PREEMPTION == 1
{
/* Switch to the highest priority task that is ready to run. */
vTaskSwitchContext();
}
#endif
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
* Setup a timer for a regular tick.
*/
static void prvSetupTimerInterrupt( void )
{
const unsigned long ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
unsigned long ulCompareValue;
unsigned char ucByte;
/* Interrupts are disabled when this function is called.
Setup CCP1 to provide the tick interrupt using a compare match on timer
1.
Clear the time count then setup timer. */
TMR1H = ( unsigned char ) 0x00;
TMR1L = ( unsigned char ) 0x00;
/* Set the compare match value. */
ulCompareValue = ulConstCompareValue;
CCPR1L = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
ulCompareValue >>= ( unsigned long ) 8;
CCPR1H = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
/* We are only going to use the global interrupt bit, so set the peripheral
bit to true. */
INTCONbits.GIEL = portBIT_SET;
/* Provided library function for setting up the timer that will produce the
tick. */
OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/MPLAB/PIC18F/port.c | C | oos | 23,151 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned long
#define portBASE_TYPE long
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 4
#define portSTACK_GROWTH -1
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
unsigned portLONG ulPortSetIPL( unsigned portLONG );
#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void );
extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE );
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portNOP() asm volatile ( "nop" )
/* Context switches are requested using the force register. */
#define portYIELD() INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
{ \
portYIELD(); \
}
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h | C | oos | 5,791 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
* supplied source files.
*/
.global ulPortSetIPL
.global _ulPortSetIPL
.global mcf5xxx_wr_cacrx
.global _mcf5xxx_wr_cacrx
.global vPortYieldISR
.global _vPortYieldISR
.global vPortStartFirstTask
.global _vPortStartFirstTask
.extern _pxCurrentTCB
.extern _vPortYieldHandler
.text
.macro portSAVE_CONTEXT
lea.l (-60, sp), sp
movem.l d0-a6, (sp)
move.l _pxCurrentTCB, a0
move.l sp, (a0)
.endm
.macro portRESTORE_CONTEXT
move.l _pxCurrentTCB, a0
move.l (a0), sp
movem.l (sp), d0-a6
lea.l (60, sp), sp
rte
.endm
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
ulPortSetIPL:
_ulPortSetIPL:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D6 /* prepare return value */
andi.l #0x0700,D6 /* mask out IPL */
lsr.l #8,D6 /* IPL */
andi.l #0x07,D0 /* least significant three bits */
lsl.l #8,D0 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D0,D7 /* place new IPL in sr */
move.w D7,SR
move.l D6, D0 /* Return value in D0. */
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
mcf5xxx_wr_cacrx:
_mcf5xxx_wr_cacrx:
move.l 4(sp),d0
.long 0x4e7b0002 /* movec d0,cacr */
nop
rts
/********************************************************************/
/* Yield interrupt. */
_vPortYieldISR:
vPortYieldISR:
portSAVE_CONTEXT
jsr _vPortYieldHandler
portRESTORE_CONTEXT
/********************************************************************/
vPortStartFirstTask:
_vPortStartFirstTask:
portRESTORE_CONTEXT
.end
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/ColdFire_V1/portasm.S | Motorola 68K Assembly | oos | 5,360 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#define portINITIAL_FORMAT_VECTOR ( ( portSTACK_TYPE ) 0x4000 )
/* Supervisor mode set. */
#define portINITIAL_STATUS_REGISTER ( ( portSTACK_TYPE ) 0x2000)
/* The clock prescale into the timer peripheral. */
#define portPRESCALE_VALUE ( ( unsigned char ) 10 )
/* The clock frequency into the RTC. */
#define portRTC_CLOCK_HZ ( ( unsigned long ) 1000 )
asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
static void prvSetupTimerInterrupt( void );
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
will be set to 0 prior to the first task being started. */
static unsigned long ulCriticalNesting = 0x9999UL;
/*-----------------------------------------------------------*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
unsigned long ulOriginalA5;
__asm{ MOVE.L A5, ulOriginalA5 };
*pxTopOfStack = (portSTACK_TYPE) 0xDEADBEEF;
pxTopOfStack--;
/* Exception stack frame starts with the return address. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode;
pxTopOfStack--;
*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x0; /*FP*/
pxTopOfStack -= 14; /* A5 to D0. */
/* Parameter in A0. */
*( pxTopOfStack + 8 ) = ( portSTACK_TYPE ) pvParameters;
/* A5 must be maintained as it is resurved by the compiler. */
*( pxTopOfStack + 13 ) = ulOriginalA5;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
ulCriticalNesting = 0UL;
/* Configure a timer to generate the tick interrupt. */
prvSetupTimerInterrupt();
/* Start the first task executing. */
vPortStartFirstTask();
return pdFALSE;
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
/* Prescale by 1 - ie no prescale. */
RTCSC |= 8;
/* Compare match value. */
RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
/* Enable the RTC to generate interrupts - interrupts are already disabled
when this code executes. */
RTCSC_RTIE = 1;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* Not implemented as there is nothing to return to. */
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( INTC_FRC == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
}
/*-----------------------------------------------------------*/
void vPortYieldHandler( void )
{
unsigned long ulSavedInterruptMask;
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
{
/* Note this will clear all forced interrupts - this is done for speed. */
INTC_CFRC = 0x3E;
vTaskSwitchContext();
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
/*-----------------------------------------------------------*/
void interrupt VectorNumber_Vrtc vPortTickISR( void )
{
unsigned long ulSavedInterruptMask;
/* Clear the interrupt. */
RTCSC |= RTCSC_RTIF_MASK;
/* Increment the RTOS tick. */
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
{
vTaskIncrementTick();
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
/* If we are using the pre-emptive scheduler then also request a
context switch as incrementing the tick could have unblocked a task. */
#if configUSE_PREEMPTION == 1
{
taskYIELD();
}
#endif
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/ColdFire_V1/port.c | C | oos | 7,137 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portCHAR
#define portBASE_TYPE char
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 1
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portYIELD() __asm( "swi" );
#define portNOP() __asm( "nop" );
/*-----------------------------------------------------------*/
/* Critical section handling. */
#define portENABLE_INTERRUPTS() __asm( "cli" )
#define portDISABLE_INTERRUPTS() __asm( "sei" )
/*
* Disable interrupts before incrementing the count of critical section nesting.
* The nesting count is maintained so we know when interrupts should be
* re-enabled. Once interrupts are disabled the nesting count can be accessed
* directly. Each task maintains its own nesting count.
*/
#define portENTER_CRITICAL() \
{ \
extern volatile unsigned portBASE_TYPE uxCriticalNesting; \
\
portDISABLE_INTERRUPTS(); \
uxCriticalNesting++; \
}
/*
* Interrupts are disabled so we can access the nesting count directly. If the
* nesting is found to be 0 (no nesting) then we are leaving the critical
* section and interrupts can be re-enabled.
*/
#define portEXIT_CRITICAL() \
{ \
extern volatile unsigned portBASE_TYPE uxCriticalNesting; \
\
uxCriticalNesting--; \
if( uxCriticalNesting == 0 ) \
{ \
portENABLE_INTERRUPTS(); \
} \
}
/*-----------------------------------------------------------*/
/* Task utilities. */
/*
* These macros are very simple as the processor automatically saves and
* restores its registers as interrupts are entered and exited. In
* addition to the (automatically stacked) registers we also stack the
* critical nesting count. Each task maintains its own critical nesting
* count as it is legitimate for a task to yield from within a critical
* section. If the banked memory model is being used then the PPAGE
* register is also stored as part of the tasks context.
*/
#ifdef BANKED_MODEL
/*
* Load the stack pointer for the task, then pull the critical nesting
* count and PPAGE register from the stack. The remains of the
* context are restored by the RTI instruction.
*/
#define portRESTORE_CONTEXT() \
{ \
extern volatile void * pxCurrentTCB; \
extern volatile unsigned portBASE_TYPE uxCriticalNesting; \
\
__asm( "ldx pxCurrentTCB" ); \
__asm( "lds 0, x" ); \
__asm( "pula" ); \
__asm( "staa uxCriticalNesting" ); \
__asm( "pula" ); \
__asm( "staa 0x30" ); /* 0x30 = PPAGE */ \
}
/*
* By the time this macro is called the processor has already stacked the
* registers. Simply stack the nesting count and PPAGE value, then save
* the task stack pointer.
*/
#define portSAVE_CONTEXT() \
{ \
extern volatile void * pxCurrentTCB; \
extern volatile unsigned portBASE_TYPE uxCriticalNesting; \
\
__asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \
__asm( "psha" ); \
__asm( "ldaa uxCriticalNesting" ); \
__asm( "psha" ); \
__asm( "ldx pxCurrentTCB" ); \
__asm( "sts 0, x" ); \
}
#else
/*
* These macros are as per the BANKED versions above, but without saving
* and restoring the PPAGE register.
*/
#define portRESTORE_CONTEXT() \
{ \
extern volatile void * pxCurrentTCB; \
extern volatile unsigned portBASE_TYPE uxCriticalNesting; \
\
__asm( "ldx pxCurrentTCB" ); \
__asm( "lds 0, x" ); \
__asm( "pula" ); \
__asm( "staa uxCriticalNesting" ); \
}
#define portSAVE_CONTEXT() \
{ \
extern volatile void * pxCurrentTCB; \
extern volatile unsigned portBASE_TYPE uxCriticalNesting; \
\
__asm( "ldaa uxCriticalNesting" ); \
__asm( "psha" ); \
__asm( "ldx pxCurrentTCB" ); \
__asm( "sts 0, x" ); \
}
#endif
/*
* Utility macro to call macros above in correct order in order to perform a
* task switch from within a standard ISR. This macro can only be used if
* the ISR does not use any local (stack) variables. If the ISR uses stack
* variables portYIELD() should be used in it's place.
*/
#define portTASK_SWITCH_FROM_ISR() \
portSAVE_CONTEXT(); \
vTaskSwitchContext(); \
portRESTORE_CONTEXT();
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/HCS12/portmacro.h | C | oos | 8,799 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the HCS12 port.
*----------------------------------------------------------*/
/*
* Configure a timer to generate the RTOS tick at the frequency specified
* within FreeRTOSConfig.h.
*/
static void prvSetupTimerInterrupt( void );
/* Interrupt service routines have to be in non-banked memory - as does the
scheduler startup function. */
#pragma CODE_SEG __NEAR_SEG NON_BANKED
/* Manual context switch function. This is the SWI ISR. */
void interrupt vPortYield( void );
/* Tick context switch function. This is the timer ISR. */
void interrupt vPortTickInterrupt( void );
/* Simply called by xPortStartScheduler(). xPortStartScheduler() does not
start the scheduler directly because the header file containing the
xPortStartScheduler() prototype is part of the common kernel code, and
therefore cannot use the CODE_SEG pragma. */
static portBASE_TYPE xBankedStartScheduler( void );
#pragma CODE_SEG DEFAULT
/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
critical section should not be left (i.e. interrupts should not be re-enabled)
until the nesting depth reaches 0. This variable simply tracks the nesting
depth. Each task maintains it's own critical nesting depth variable so
uxCriticalNesting is saved and restored from the task stack during a context
switch. */
volatile unsigned portBASE_TYPE uxCriticalNesting = 0xff;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
/*
Place a few bytes of known values on the bottom of the stack.
This can be uncommented to provide useful stack markers when debugging.
*pxTopOfStack = ( portSTACK_TYPE ) 0x11;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x22;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x33;
pxTopOfStack--;
*/
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. In this case the stack as
expected by the HCS12 RTI instruction. */
/* The address of the task function is placed in the stack byte at a time. */
*pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 );
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 );
pxTopOfStack--;
/* Next are all the registers that form part of the task context. */
/* Y register */
*pxTopOfStack = ( portSTACK_TYPE ) 0xff;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xee;
pxTopOfStack--;
/* X register */
*pxTopOfStack = ( portSTACK_TYPE ) 0xdd;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xcc;
pxTopOfStack--;
/* A register contains parameter high byte. */
*pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 );
pxTopOfStack--;
/* B register contains parameter low byte. */
*pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 );
pxTopOfStack--;
/* CCR: Note that when the task starts interrupts will be enabled since
"I" bit of CCR is cleared */
*pxTopOfStack = ( portSTACK_TYPE ) 0x00;
pxTopOfStack--;
#ifdef BANKED_MODEL
/* The page of the task. */
*pxTopOfStack = ( portSTACK_TYPE ) ( ( int ) pxCode );
pxTopOfStack--;
#endif
/* Finally the critical nesting depth is initialised with 0 (not within
a critical section). */
*pxTopOfStack = ( portSTACK_TYPE ) 0x00;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the HCS12 port will get stopped. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
TickTimer_SetFreqHz( configTICK_RATE_HZ );
TickTimer_Enable();
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
/* xPortStartScheduler() does not start the scheduler directly because
the header file containing the xPortStartScheduler() prototype is part
of the common kernel code, and therefore cannot use the CODE_SEG pragma.
Instead it simply calls the locally defined xBankedStartScheduler() -
which does use the CODE_SEG pragma. */
return xBankedStartScheduler();
}
/*-----------------------------------------------------------*/
#pragma CODE_SEG __NEAR_SEG NON_BANKED
static portBASE_TYPE xBankedStartScheduler( void )
{
/* Configure the timer that will generate the RTOS tick. Interrupts are
disabled when this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task. */
portRESTORE_CONTEXT();
/* Simulate the end of an interrupt to start the scheduler off. */
__asm( "rti" );
/* Should not get here! */
return pdFALSE;
}
/*-----------------------------------------------------------*/
/*
* Context switch functions. These are both interrupt service routines.
*/
/*
* Manual context switch forced by calling portYIELD(). This is the SWI
* handler.
*/
void interrupt vPortYield( void )
{
portSAVE_CONTEXT();
vTaskSwitchContext();
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
/*
* RTOS tick interrupt service routine. If the cooperative scheduler is
* being used then this simply increments the tick count. If the
* preemptive scheduler is being used a context switch can occur.
*/
void interrupt vPortTickInterrupt( void )
{
#if configUSE_PREEMPTION == 1
{
/* A context switch might happen so save the context. */
portSAVE_CONTEXT();
/* Increment the tick ... */
vTaskIncrementTick();
/* ... then see if the new tick value has necessitated a
context switch. */
vTaskSwitchContext();
TFLG1 = 1;
/* Restore the context of a task - which may be a different task
to that interrupted. */
portRESTORE_CONTEXT();
}
#else
{
vTaskIncrementTick();
TFLG1 = 1;
}
#endif
}
#pragma CODE_SEG DEFAULT
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/HCS12/port.c | C | oos | 9,375 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned long
#define portBASE_TYPE long
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 4
#define portSTACK_GROWTH -1
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
unsigned portLONG ulPortSetIPL( unsigned portLONG );
#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 )
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void );
extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE );
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portNOP() asm volatile ( "nop" )
/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) \
{ \
portYIELD(); \
}
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h | C | oos | 5,900 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
* supplied source files.
*/
.global ulPortSetIPL
.global _ulPortSetIPL
.global mcf5xxx_wr_cacrx
.global _mcf5xxx_wr_cacrx
.global vPortYieldISR
.global _vPortYieldISR
.global vPortStartFirstTask
.global _vPortStartFirstTask
.extern _pxCurrentTCB
.extern _vPortYieldHandler
.text
.macro portSAVE_CONTEXT
lea.l (-60, sp), sp
movem.l d0-a6, (sp)
move.l _pxCurrentTCB, a0
move.l sp, (a0)
.endm
.macro portRESTORE_CONTEXT
move.l _pxCurrentTCB, a0
move.l (a0), sp
movem.l (sp), d0-a6
lea.l (60, sp), sp
rte
.endm
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
ulPortSetIPL:
_ulPortSetIPL:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D0 /* prepare return value */
andi.l #0x0700,D0 /* mask out IPL */
lsr.l #8,D0 /* IPL */
move.l 8(A6),D6 /* get argument */
andi.l #0x07,D6 /* least significant three bits */
lsl.l #8,D6 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D6,D7 /* place new IPL in sr */
move.w D7,SR
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
mcf5xxx_wr_cacrx:
_mcf5xxx_wr_cacrx:
move.l 4(sp),d0
.long 0x4e7b0002 /* movec d0,cacr */
nop
rts
/********************************************************************/
/* Yield interrupt. */
_vPortYieldISR:
vPortYieldISR:
portSAVE_CONTEXT
jsr _vPortYieldHandler
portRESTORE_CONTEXT
/********************************************************************/
vPortStartFirstTask:
_vPortStartFirstTask:
portRESTORE_CONTEXT
.end
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/ColdFire_V2/portasm.S | Motorola 68K Assembly | oos | 5,362 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#define portINITIAL_FORMAT_VECTOR ( ( portSTACK_TYPE ) 0x4000 )
/* Supervisor mode set. */
#define portINITIAL_STATUS_REGISTER ( ( portSTACK_TYPE ) 0x2000)
/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This
will be set to 0 prior to the first task being started. */
static unsigned long ulCriticalNesting = 0x9999UL;
#define portSAVE_CONTEXT() \
lea.l (-60, %sp), %sp; \
movem.l %d0-%fp, (%sp); \
move.l pxCurrentTCB, %a0; \
move.l %sp, (%a0);
#define portRESTORE_CONTEXT() \
move.l pxCurrentTCB, %a0; \
move.l (%a0), %sp; \
movem.l (%sp), %d0-%fp; \
lea.l %sp@(60), %sp; \
rte
/*-----------------------------------------------------------*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE) 0xDEADBEEF;
pxTopOfStack--;
/* Exception stack frame starts with the return address. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode;
pxTopOfStack--;
*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x0; /*FP*/
pxTopOfStack -= 14; /* A5 to D0. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
ulCriticalNesting = 0UL;
/* Configure the interrupts used by this port. */
vApplicationSetupInterrupts();
/* Start the first task executing. */
vPortStartFirstTask();
return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* Not implemented as there is nothing to return to. */
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
if( ulCriticalNesting == 0UL )
{
/* Guard against context switches being pended simultaneously with a
critical section being entered. */
do
{
portDISABLE_INTERRUPTS();
if( MCF_INTC0_INTFRCH == 0UL )
{
break;
}
portENABLE_INTERRUPTS();
} while( 1 );
}
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
ulCriticalNesting--;
if( ulCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
}
/*-----------------------------------------------------------*/
void vPortYieldHandler( void )
{
unsigned long ulSavedInterruptMask;
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
/* Note this will clear all forced interrupts - this is done for speed. */
MCF_INTC0_INTFRCL = 0;
vTaskSwitchContext();
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/CodeWarrior/ColdFire_V2/port.c | C | oos | 6,002 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned int
#define portBASE_TYPE int
#if (configUSE_16_BIT_TICKS==1)
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
#define portDISABLE_INTERRUPTS() __asm ( "DI" )
#define portENABLE_INTERRUPTS() __asm ( "EI" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portBASE_TYPE ) 0 )
#define portENTER_CRITICAL() \
{ \
extern volatile /*unsigned portSHORT*/ portSTACK_TYPE usCriticalNesting; \
\
portDISABLE_INTERRUPTS(); \
\
/* Now interrupts are disabled ulCriticalNesting can be accessed */ \
/* directly. Increment ulCriticalNesting to keep a count of how many */ \
/* times portENTER_CRITICAL() has been called. */ \
usCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
extern volatile /*unsigned portSHORT*/ portSTACK_TYPE usCriticalNesting; \
\
if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
{ \
/* Decrement the nesting count as we are leaving a critical section. */ \
usCriticalNesting--; \
\
/* If the nesting level has reached zero then interrupts should be */ \
/* re-enabled. */ \
if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
{ \
portENABLE_INTERRUPTS(); \
} \
} \
}
/*-----------------------------------------------------------*/
/* Task utilities. */
extern void vPortYield( void );
extern void vPortStart( void );
extern void portSAVE_CONTEXT( void );
extern void portRESTORE_CONTEXT( void );
#define portYIELD() __asm ( "trap 0" )
#define portNOP() __asm ( "NOP" )
extern void vTaskSwitchContext( void );
#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
#define portBYTE_ALIGNMENT 4
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/V850ES/portmacro.h | C | oos | 6,525 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
EXTERN pxCurrentTCB
EXTERN usCriticalNesting
#include "FreeRTOSConfig.h"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Context save and restore macro definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
add -0x0C,sp ; prepare stack to save necessary values
st.w lp,8[sp] ; store LP to stack
stsr 0,r31
st.w lp,4[sp] ; store EIPC to stack
stsr 1,lp
st.w lp,0[sp] ; store EIPSW to stack
#if configDATA_MODE == 1 ; Using the Tiny data model
prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
sst.w r19,72[ep]
sst.w r18,68[ep]
sst.w r17,64[ep]
sst.w r16,60[ep]
sst.w r15,56[ep]
sst.w r14,52[ep]
sst.w r13,48[ep]
sst.w r12,44[ep]
sst.w r11,40[ep]
sst.w r10,36[ep]
sst.w r9,32[ep]
sst.w r8,28[ep]
sst.w r7,24[ep]
sst.w r6,20[ep]
sst.w r5,16[ep]
sst.w r4,12[ep]
#else ; Using the Small/Large data model
prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers
sst.w r19,68[ep]
sst.w r18,64[ep]
sst.w r17,60[ep]
sst.w r16,56[ep]
sst.w r15,52[ep]
sst.w r14,48[ep]
sst.w r13,44[ep]
sst.w r12,40[ep]
sst.w r11,36[ep]
sst.w r10,32[ep]
sst.w r9,28[ep]
sst.w r8,24[ep]
sst.w r7,20[ep]
sst.w r6,16[ep]
sst.w r5,12[ep]
#endif /* configDATA_MODE */
sst.w r2,8[ep]
sst.w r1,4[ep]
MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack
ld.w lw1(usCriticalNesting)[r1],r2
sst.w r2,0[ep]
MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB
ld.w lw1(pxCurrentTCB)[r1],r2
st.w sp,0[r2]
ENDM
portRESTORE_CONTEXT MACRO
MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address
ld.w lw1(pxCurrentTCB)[r1],sp
MOV sp,r1
ld.w 0[r1],sp ; load stackpointer
MOV sp,ep ; set stack pointer to element pointer
sld.w 0[ep],r1 ; load usCriticalNesting value from stack
MOVHI hi1(usCriticalNesting),r0,r2
st.w r1,lw1(usCriticalNesting)[r2]
sld.w 4[ep],r1 ; restore general purpose registers
sld.w 8[ep],r2
#if configDATA_MODE == 1 ; Using Tiny data model
sld.w 12[ep],r4
sld.w 16[ep],r5
sld.w 20[ep],r6
sld.w 24[ep],r7
sld.w 28[ep],r8
sld.w 32[ep],r9
sld.w 36[ep],r10
sld.w 40[ep],r11
sld.w 44[ep],r12
sld.w 48[ep],r13
sld.w 52[ep],r14
sld.w 56[ep],r15
sld.w 60[ep],r16
sld.w 64[ep],r17
sld.w 68[ep],r18
sld.w 72[ep],r19
dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
#else ; Using Small/Large data model
sld.w 12[ep],r5
sld.w 16[ep],r6
sld.w 20[ep],r7
sld.w 24[ep],r8
sld.w 28[ep],r9
sld.w 32[ep],r10
sld.w 36[ep],r11
sld.w 40[ep],r12
sld.w 44[ep],r13
sld.w 48[ep],r14
sld.w 52[ep],r15
sld.w 56[ep],r16
sld.w 60[ep],r17
sld.w 64[ep],r18
sld.w 68[ep],r19
dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
#endif /* configDATA_MODE */
ld.w 0[sp],lp ; restore EIPSW from stack
ldsr lp,1
ld.w 4[sp],lp ; restore EIPC from stack
ldsr lp,0
ld.w 8[sp],lp ; restore LP from stack
add 0x0C,sp ; set SP to right position
RETI
ENDM
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/V850ES/ISR_Support.h | C | oos | 6,770 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Critical nesting should be initialised to a non zero value so interrupts don't
accidentally get enabled before the scheduler is started. */
#define portINITIAL_CRITICAL_NESTING (( portSTACK_TYPE ) 10)
/* The PSW value assigned to tasks when they start to run for the first time. */
#define portPSW (( portSTACK_TYPE ) 0x00000000)
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
typedef void tskTCB;
extern volatile tskTCB * volatile pxCurrentTCB;
/* Keeps track of the nesting level of critical sections. */
volatile portSTACK_TYPE usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
/* Sets up the timer to generate the tick interrupt. */
static void prvSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* Task function start address */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* Task function start address */
pxTopOfStack--;
*pxTopOfStack = portPSW; /* Initial PSW value */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x20202020; /* Initial Value of R20 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x21212121; /* Initial Value of R21 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; /* Initial Value of R22 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x23232323; /* Initial Value of R23 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x24242424; /* Initial Value of R24 */
pxTopOfStack--;
#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1)
*pxTopOfStack = ( portSTACK_TYPE ) 0x25252525; /* Initial Value of R25 */
pxTopOfStack--;
#endif /* configDATA_MODE */
*pxTopOfStack = ( portSTACK_TYPE ) 0x26262626; /* Initial Value of R26 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x27272727; /* Initial Value of R27 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x28282828; /* Initial Value of R28 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x29292929; /* Initial Value of R29 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x30303030; /* Initial Value of R30 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x19191919; /* Initial Value of R19 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x18181818; /* Initial Value of R18 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x17171717; /* Initial Value of R17 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x16161616; /* Initial Value of R16 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x15151515; /* Initial Value of R15 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x14141414; /* Initial Value of R14 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x13131313; /* Initial Value of R13 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* Initial Value of R12 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* Initial Value of R11 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* Initial Value of R10 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x99999999; /* Initial Value of R09 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x88888888; /* Initial Value of R08 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x77777777; /* Initial Value of R07 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x66666666; /* Initial Value of R06 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x55555555; /* Initial Value of R05 */
pxTopOfStack--;
#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
*pxTopOfStack = ( portSTACK_TYPE ) 0x44444444; /* Initial Value of R04 */
pxTopOfStack--;
#endif /* configDATA_MODE */
*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; /* Initial Value of R02 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 is expected to hold the function parameter*/
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING;
/*
* Return a pointer to the top of the stack we have generated so this can
* be stored in the task control block for the task.
*/
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. Interrupts are disabled when
this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task that is going to run. */
vPortStart();
/* Should not get here as the tasks are now running! */
return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply
disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
/*
* Hardware initialisation to generate the RTOS tick. This uses
*/
static void prvSetupTimerInterrupt( void )
{
TM0CE = 0; /* TMM0 operation disable */
TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
#ifdef __IAR_V850ES_Fx3__
{
TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
}
#else
{
TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
}
#endif
TM0EQIC0 &= 0xF8;
TM0CTL0 = 0x00;
TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
TM0CE = 1; /* TMM0 operation enable */
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/V850ES/port.c | C | oos | 9,206 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
#include <intrinsics.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portLONG
#define portBASE_TYPE portLONG
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portYIELD() asm ( "SWI 0" )
#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
__arm __interwork void vPortEnterCritical( void );
__arm __interwork void vPortExitCritical( void );
#define portDISABLE_INTERRUPTS() __disable_interrupt()
#define portENABLE_INTERRUPTS() __enable_interrupt()
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern void vTaskSwitchContext( void ); \
\
if( xSwitchRequired ) \
{ \
vTaskSwitchContext(); \
} \
}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR75x/portmacro.h | C | oos | 5,322 |
;/*
; FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
;
;
; ***************************************************************************
; * *
; * FreeRTOS tutorial books are available in pdf and paperback. *
; * Complete, revised, and edited pdf reference manuals are also *
; * available. *
; * *
; * Purchasing FreeRTOS documentation will not only help you, by *
; * ensuring you get running as quickly as possible and with an *
; * in-depth knowledge of how to use FreeRTOS, it will also help *
; * the FreeRTOS project to continue with its mission of providing *
; * professional grade, cross platform, de facto standard solutions *
; * for microcontrollers - completely free of charge! *
; * *
; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
; * *
; * Thank you for using FreeRTOS, and thank you for your support! *
; * *
; ***************************************************************************
;
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
; >>>NOTE<<< The modification to the GPL is included to allow you to
; distribute a combined work that includes FreeRTOS without being obliged to
; provide the source code for proprietary components outside of the FreeRTOS
; kernel. FreeRTOS is distributed in the hope that it will be useful, but
; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
; more details. You should have received a copy of the GNU General Public
; License and the FreeRTOS license exception along with FreeRTOS; if not it
; can be viewed here: http://www.freertos.org/a00114.html and also obtained
; by writing to Richard Barry, contact details for whom are available on the
; FreeRTOS WEB site.
;
; 1 tab == 4 spaces!
;
; http://www.FreeRTOS.org - Documentation, latest information, license and
; contact details.
;
; http://www.SafeRTOS.com - A version that is certified for use in safety
; critical systems.
;
; http://www.OpenRTOS.com - Commercial support, development, porting,
; licensing and training services.
;*/
EXTERN pxCurrentTCB
EXTERN ulCriticalNesting
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Context save and restore macro definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
; Push R0 as we are going to use the register.
STMDB SP!, {R0}
; Set R0 to point to the task stack pointer.
STMDB SP, {SP}^
NOP
SUB SP, SP, #4
LDMIA SP!, {R0}
; Push the return address onto the stack.
STMDB R0!, {LR}
; Now we have saved LR we can use it instead of R0.
MOV LR, R0
; Pop R0 so we can save it onto the system mode stack.
LDMIA SP!, {R0}
; Push all the system mode registers onto the task stack.
STMDB LR, {R0-LR}^
NOP
SUB LR, LR, #60
; Push the SPSR onto the task stack.
MRS R0, SPSR
STMDB LR!, {R0}
LDR R0, =ulCriticalNesting
LDR R0, [R0]
STMDB LR!, {R0}
; Store the new top of stack for the task.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
STR LR, [R0]
ENDM
portRESTORE_CONTEXT MACRO
; Set the LR to the task stack.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
LDR LR, [R0]
; The critical nesting depth is the first item on the stack.
; Load it into the ulCriticalNesting variable.
LDR R0, =ulCriticalNesting
LDMFD LR!, {R1}
STR R1, [R0]
; Get the SPSR from the stack.
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
; Restore all system mode registers for the task.
LDMFD LR, {R0-R14}^
NOP
; Restore the return address.
LDR LR, [LR, #+60]
; And return - correcting the offset in the LR to obtain the
; correct address.
SUBS PC, LR, #4
ENDM
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR75x/ISR_Support.h | C | oos | 4,789 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the ST STR75x ARM7
* port.
*----------------------------------------------------------*/
/* Library includes. */
#include "75x_tb.h"
#include "75x_eic.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Constants required to setup the initial stack. */
#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
/* Constants required to handle critical sections. */
#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
/* Prescale used on the timer clock when calculating the tick period. */
#define portPRESCALE 20
/*-----------------------------------------------------------*/
/* Setup the TB to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
cannot be initialised to 0 as this will cause interrupts to be enabled
during the kernel initialisation process. */
unsigned long ulCriticalNesting = ( unsigned long ) 9999;
/* Tick interrupt routines for preemptive operation. */
__arm void vPortPreemptiveTick( void );
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
portSTACK_TYPE *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
pxTopOfStack--;
/* The status register is set for system mode, with interrupts enabled. */
*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
pxTopOfStack--;
/* Interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
vPortStartFirstTask();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
}
/*-----------------------------------------------------------*/
__arm void vPortPreemptiveTick( void )
{
/* Increment the tick counter. */
vTaskIncrementTick();
/* The new tick value might unblock a task. Ensure the highest task that
is ready to execute is the task that will execute when the tick ISR
exits. */
#if configUSE_PREEMPTION == 1
vTaskSwitchContext();
#endif
TB_ClearITPendingBit( TB_IT_Update );
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
EIC_IRQInitTypeDef EIC_IRQInitStructure;
TB_InitTypeDef TB_InitStructure;
/* Setup the EIC for the TB. */
EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
EIC_IRQInit(&EIC_IRQInitStructure);
/* Setup the TB for the generation of the tick interrupt. */
TB_InitStructure.TB_Mode = TB_Mode_Timing;
TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
TB_Init(&TB_InitStructure);
/* Enable TB Update interrupt */
TB_ITConfig(TB_IT_Update, ENABLE);
/* Clear TB Update interrupt pending bit */
TB_ClearITPendingBit(TB_IT_Update);
/* Enable TB */
TB_Cmd(ENABLE);
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortEnterCritical( void )
{
/* Disable interrupts first! */
__disable_interrupt();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortExitCritical( void )
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as we are leaving a critical section. */
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
__enable_interrupt();
}
}
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR75x/port.c | C | oos | 9,830 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#include <intrinsics.h>
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portLONG
#define portBASE_TYPE portLONG
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portYIELD() asm ( "SWI 0" )
#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
__arm __interwork void vPortDisableInterruptsFromThumb( void );
__arm __interwork void vPortEnableInterruptsFromThumb( void );
__arm __interwork void vPortEnterCritical( void );
__arm __interwork void vPortExitCritical( void );
#define portDISABLE_INTERRUPTS() __disable_irq()
#define portENABLE_INTERRUPTS() __enable_irq()
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern void vTaskSwitchContext( void ); \
\
if( xSwitchRequired ) \
{ \
vTaskSwitchContext(); \
} \
}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM9XE/portmacro.h | C | oos | 5,439 |
EXTERN pxCurrentTCB
EXTERN ulCriticalNesting
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Context save and restore macro definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
; Push R0 as we are going to use the register.
STMDB SP!, {R0}
; Set R0 to point to the task stack pointer.
STMDB SP, {SP}^
NOP
SUB SP, SP, #4
LDMIA SP!, {R0}
; Push the return address onto the stack.
STMDB R0!, {LR}
; Now we have saved LR we can use it instead of R0.
MOV LR, R0
; Pop R0 so we can save it onto the system mode stack.
LDMIA SP!, {R0}
; Push all the system mode registers onto the task stack.
STMDB LR, {R0-LR}^
NOP
SUB LR, LR, #60
; Push the SPSR onto the task stack.
MRS R0, SPSR
STMDB LR!, {R0}
LDR R0, =ulCriticalNesting
LDR R0, [R0]
STMDB LR!, {R0}
; Store the new top of stack for the task.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
STR LR, [R0]
ENDM
portRESTORE_CONTEXT MACRO
; Set the LR to the task stack.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
LDR LR, [R0]
; The critical nesting depth is the first item on the stack.
; Load it into the ulCriticalNesting variable.
LDR R0, =ulCriticalNesting
LDMFD LR!, {R1}
STR R1, [R0]
; Get the SPSR from the stack.
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
; Restore all system mode registers for the task.
LDMFD LR, {R0-R14}^
NOP
; Restore the return address.
LDR LR, [LR, #+60]
; And return - correcting the offset in the LR to obtain the
; correct address.
SUBS PC, LR, #4
ENDM
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h | C | oos | 1,770 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the Atmel ARM7 port.
*----------------------------------------------------------*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Hardware includes. */
#include <board.h>
#include <pio/pio.h>
#include <pio/pio_it.h>
#include <pit/pit.h>
#include <aic/aic.h>
#include <tc/tc.h>
#include <utility/led.h>
#include <utility/trace.h>
/*-----------------------------------------------------------*/
/* Constants required to setup the initial stack. */
#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
/* Constants required to setup the PIT. */
#define port1MHz_IN_Hz ( 1000000ul )
#define port1SECOND_IN_uS ( 1000000.0 )
/* Constants required to handle critical sections. */
#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
#define portINT_LEVEL_SENSITIVE 0
#define portPIT_ENABLE ( ( unsigned short ) 0x1 << 24 )
#define portPIT_INT_ENABLE ( ( unsigned short ) 0x1 << 25 )
/*-----------------------------------------------------------*/
/* Setup the PIT to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
/* The PIT interrupt handler - the RTOS tick. */
static void vPortTickISR( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
cannot be initialised to 0 as this will cause interrupts to be enabled
during the kernel initialisation process. */
unsigned long ulCriticalNesting = ( unsigned long ) 9999;
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
portSTACK_TYPE *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
pxTopOfStack--;
/* The status register is set for system mode, with interrupts enabled. */
*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
#ifdef THUMB_INTERWORK
{
/* We want the task to start in thumb mode. */
*pxTopOfStack |= portTHUMB_MODE_BIT;
}
#endif
pxTopOfStack--;
/* Interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
vPortStartFirstTask();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
}
/*-----------------------------------------------------------*/
static __arm void vPortTickISR( void )
{
volatile unsigned long ulDummy;
/* Increment the tick count - which may wake some tasks but as the
preemptive scheduler is not being used any woken task is not given
processor time no matter what its priority. */
vTaskIncrementTick();
#if configUSE_PREEMPTION == 1
vTaskSwitchContext();
#endif
/* Clear the PIT interrupt. */
ulDummy = AT91C_BASE_PITC->PITC_PIVR;
/* To remove compiler warning. */
( void ) ulDummy;
/* The AIC is cleared in the asm wrapper, outside of this function. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
const unsigned long ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
/* Setup the PIT for the required frequency. */
PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz );
/* Setup the PIT interrupt. */
AIC_DisableIT( AT91C_ID_SYS );
AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR );
AIC_EnableIT( AT91C_ID_SYS );
PIT_EnableIT();
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
/* Disable interrupts first! */
__disable_irq();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as we are leaving a critical section. */
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
__enable_irq();
}
}
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM9XE/port.c | C | oos | 10,152 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
#include <intrinsics.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portLONG
#define portBASE_TYPE portLONG
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portYIELD() asm ( "SWI 0" )
#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
__arm __interwork void vPortEnterCritical( void );
__arm __interwork void vPortExitCritical( void );
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
#define portDISABLE_INTERRUPTS() __disable_interrupt()
#define portENABLE_INTERRUPTS() __enable_interrupt()
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern void vTaskSwitchContext( void ); \
\
if( xSwitchRequired ) \
{ \
vTaskSwitchContext(); \
} \
}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR91x/portmacro.h | C | oos | 5,331 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
EXTERN pxCurrentTCB
EXTERN ulCriticalNesting
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Context save and restore macro definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
; Push R0 as we are going to use the register.
STMDB SP!, {R0}
; Set R0 to point to the task stack pointer.
STMDB SP, {SP}^
NOP
SUB SP, SP, #4
LDMIA SP!, {R0}
; Push the return address onto the stack.
STMDB R0!, {LR}
; Now we have saved LR we can use it instead of R0.
MOV LR, R0
; Pop R0 so we can save it onto the system mode stack.
LDMIA SP!, {R0}
; Push all the system mode registers onto the task stack.
STMDB LR, {R0-LR}^
NOP
SUB LR, LR, #60
; Push the SPSR onto the task stack.
MRS R0, SPSR
STMDB LR!, {R0}
LDR R0, =ulCriticalNesting
LDR R0, [R0]
STMDB LR!, {R0}
; Store the new top of stack for the task.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
STR LR, [R0]
ENDM
portRESTORE_CONTEXT MACRO
; Set the LR to the task stack.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
LDR LR, [R0]
; The critical nesting depth is the first item on the stack.
; Load it into the ulCriticalNesting variable.
LDR R0, =ulCriticalNesting
LDMFD LR!, {R1}
STR R1, [R0]
; Get the SPSR from the stack.
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
; Restore all system mode registers for the task.
LDMFD LR, {R0-R14}^
NOP
; Restore the return address.
LDR LR, [LR, #+60]
; And return - correcting the offset in the LR to obtain the
; correct address.
SUBS PC, LR, #4
ENDM
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR91x/ISR_Support.h | C | oos | 4,737 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the ST STR91x ARM9
* port.
*----------------------------------------------------------*/
/* Library includes. */
#include "91x_lib.h"
/* Standard includes. */
#include <stdlib.h>
#include <assert.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#ifndef configUSE_WATCHDOG_TICK
#error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
#endif
/* Constants required to setup the initial stack. */
#ifndef _RUN_TASK_IN_ARM_MODE_
#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
#else
#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
#endif
#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
/* Constants required to handle critical sections. */
#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
#ifndef abs
#define abs(x) ((x)>0 ? (x) : -(x))
#endif
/**
* Toggle a led using the following algorithm:
* if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
* {
* GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
* }
* else
* {
* GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
* }
*
*/
#define TOGGLE_LED(port,pin) \
if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \
{ \
(port)->DR[(pin) <<2] = 0x00; \
} \
else \
{ \
(port)->DR[(pin) <<2] = (pin); \
}
/*-----------------------------------------------------------*/
/* Setup the watchdog to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
cannot be initialised to 0 as this will cause interrupts to be enabled
during the kernel initialisation process. */
unsigned long ulCriticalNesting = ( unsigned long ) 9999;
/* Tick interrupt routines for cooperative and preemptive operation
respectively. The preemptive version is not defined as __irq as it is called
from an asm wrapper function. */
void WDG_IRQHandler( void );
/* VIC interrupt default handler. */
static void prvDefaultHandler( void );
#if configUSE_WATCHDOG_TICK == 0
/* Used to update the OCR timer register */
static u16 s_nPulseLength;
#endif
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
portSTACK_TYPE *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
pxTopOfStack--;
/* The status register is set for system mode, with interrupts enabled. */
*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
pxTopOfStack--;
/* Interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
vPortStartFirstTask();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* This function is called from an asm wrapper, so does not require the __irq
keyword. */
#if configUSE_WATCHDOG_TICK == 1
static void prvFindFactors(u32 n, u16 *a, u32 *b)
{
/* This function is copied from the ST STR7 library and is
copyright STMicroelectronics. Reproduced with permission. */
u32 b0;
u16 a0;
long err, err_min=n;
*a = a0 = ((n-1)/65536ul) + 1;
*b = b0 = n / *a;
for (; *a <= 256; (*a)++)
{
*b = n / *a;
err = (long)*a * (long)*b - (long)n;
if (abs(err) > (*a / 2))
{
(*b)++;
err = (long)*a * (long)*b - (long)n;
}
if (abs(err) < abs(err_min))
{
err_min = err;
a0 = *a;
b0 = *b;
if (err == 0) break;
}
}
*a = a0;
*b = b0;
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
WDG_InitTypeDef xWdg;
unsigned short a;
unsigned long n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
/* Configure the watchdog as a free running timer that generates a
periodic interrupt. */
SCU_APBPeriphClockConfig( __WDG, ENABLE );
WDG_DeInit();
WDG_StructInit(&xWdg);
prvFindFactors( n, &a, &b );
xWdg.WDG_Prescaler = a - 1;
xWdg.WDG_Preload = b - 1;
WDG_Init( &xWdg );
WDG_ITConfig(ENABLE);
/* Configure the VIC for the WDG interrupt. */
VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
VIC_ITCmd( WDG_ITLine, ENABLE );
/* Install the default handlers for both VIC's. */
VIC0->DVAR = ( unsigned long ) prvDefaultHandler;
VIC1->DVAR = ( unsigned long ) prvDefaultHandler;
WDG_Cmd(ENABLE);
}
/*-----------------------------------------------------------*/
void WDG_IRQHandler( void )
{
{
/* Increment the tick counter. */
vTaskIncrementTick();
#if configUSE_PREEMPTION == 1
{
/* The new tick value might unblock a task. Ensure the highest task that
is ready to execute is the task that will execute when the tick ISR
exits. */
vTaskSwitchContext();
}
#endif /* configUSE_PREEMPTION. */
/* Clear the interrupt in the watchdog. */
WDG->SR &= ~0x0001;
}
}
#else
static void prvFindFactors(u32 n, u8 *a, u16 *b)
{
/* This function is copied from the ST STR7 library and is
copyright STMicroelectronics. Reproduced with permission. */
u16 b0;
u8 a0;
long err, err_min=n;
*a = a0 = ((n-1)/256) + 1;
*b = b0 = n / *a;
for (; *a <= 256; (*a)++)
{
*b = n / *a;
err = (long)*a * (long)*b - (long)n;
if (abs(err) > (*a / 2))
{
(*b)++;
err = (long)*a * (long)*b - (long)n;
}
if (abs(err) < abs(err_min))
{
err_min = err;
a0 = *a;
b0 = *b;
if (err == 0) break;
}
}
*a = a0;
*b = b0;
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
unsigned char a;
unsigned short b;
unsigned long n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
TIM_InitTypeDef timer;
SCU_APBPeriphClockConfig( __TIM23, ENABLE );
TIM_DeInit(TIM2);
TIM_StructInit(&timer);
prvFindFactors( n, &a, &b );
timer.TIM_Mode = TIM_OCM_CHANNEL_1;
timer.TIM_OC1_Modes = TIM_TIMING;
timer.TIM_Clock_Source = TIM_CLK_APB;
timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
timer.TIM_Prescaler = a-1;
timer.TIM_Pulse_Level_1 = TIM_HIGH;
timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1;
TIM_Init (TIM2, &timer);
TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
/* Configure the VIC for the WDG interrupt. */
VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
VIC_ITCmd( TIM2_ITLine, ENABLE );
/* Install the default handlers for both VIC's. */
VIC0->DVAR = ( unsigned long ) prvDefaultHandler;
VIC1->DVAR = ( unsigned long ) prvDefaultHandler;
TIM_CounterCmd(TIM2, TIM_CLEAR);
TIM_CounterCmd(TIM2, TIM_START);
}
/*-----------------------------------------------------------*/
void TIM2_IRQHandler( void )
{
/* Reset the timer counter to avioid overflow. */
TIM2->OC1R += s_nPulseLength;
/* Increment the tick counter. */
vTaskIncrementTick();
#if configUSE_PREEMPTION == 1
{
/* The new tick value might unblock a task. Ensure the highest task that
is ready to execute is the task that will execute when the tick ISR
exits. */
vTaskSwitchContext();
}
#endif
/* Clear the interrupt in the watchdog. */
TIM2->SR &= ~TIM_FLAG_OC1;
}
#endif /* USE_WATCHDOG_TICK */
/*-----------------------------------------------------------*/
__arm __interwork void vPortEnterCritical( void )
{
/* Disable interrupts first! */
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortExitCritical( void )
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as we are leaving a critical section. */
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
portENABLE_INTERRUPTS();
}
}
}
/*-----------------------------------------------------------*/
static void prvDefaultHandler( void )
{
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR91x/port.c | C | oos | 14,347 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include "PriorityDefinitions.h"
PUBLIC _prvStartFirstTask
PUBLIC ___interrupt_27
EXTERN _pxCurrentTCB
EXTERN _vTaskSwitchContext
RSEG CODE:CODE(4)
_prvStartFirstTask:
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
SETPSW U
/* Obtain the location of the stack associated with which ever task
pxCurrentTCB is currently pointing to. */
MOV.L #_pxCurrentTCB, R15
MOV.L [R15], R15
MOV.L [R15], R0
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15
POP R15
/* Floating point status word. */
MVTC R15, FPSW
/* R1 to R15 - R0 is not included as it is the SP. */
POPM R1-R15
/* This pops the remaining registers. */
RTE
NOP
NOP
/*-----------------------------------------------------------*/
/* The software interrupt - overwrite the default 'weak' definition. */
___interrupt_27:
/* Re-enable interrupts. */
SETPSW I
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
PUSH.L R15
/* Read the user stack pointer. */
MVFC USP, R15
/* Move the address down to the data being moved. */
SUB #12, R15
MVTC R15, USP
/* Copy the data across, R15, then PC, then PSW. */
MOV.L [ R0 ], [ R15 ]
MOV.L 4[ R0 ], 4[ R15 ]
MOV.L 8[ R0 ], 8[ R15 ]
/* Move the interrupt stack pointer to its new correct position. */
ADD #12, R0
/* All the rest of the registers are saved directly to the user stack. */
SETPSW U
/* Save the rest of the general registers (R15 has been saved already). */
PUSHM R1-R14
/* Save the FPSW and accumulator. */
MVFC FPSW, R15
PUSH.L R15
MVFACHI R15
PUSH.L R15
/* Middle word. */
MVFACMI R15
/* Shifted left as it is restored to the low order word. */
SHLL #16, R15
PUSH.L R15
/* Save the stack pointer to the TCB. */
MOV.L #_pxCurrentTCB, R15
MOV.L [ R15 ], R15
MOV.L R0, [ R15 ]
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
/* Select the next task to run. */
BSR.A _vTaskSwitchContext
/* Reset the interrupt mask as no more data structure access is required. */
MVTIPL #configKERNEL_INTERRUPT_PRIORITY
/* Load the stack pointer of the task that is now selected as the Running
state task from its TCB. */
MOV.L #_pxCurrentTCB,R15
MOV.L [ R15 ], R15
MOV.L [ R15 ], R0
/* Restore the context of the new task. The PSW (Program Status Word) and
PC will be popped by the RTE instruction. */
POP R15
MVTACLO R15
POP R15
MVTACHI R15
POP R15
MVTC R15, FPSW
POPM R1-R15
RTE
NOP
NOP
/*-----------------------------------------------------------*/
END
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/RX600/port_asm.s | Motorola 68K Assembly | oos | 6,232 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#include <intrinsics.h>
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions - these are a bit legacy and not really used now, other than
portSTACK_TYPE and portBASE_TYPE. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portLONG
#define portBASE_TYPE long
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
#define portSTACK_GROWTH -1
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portNOP() __no_operation()
/* The location of the software interrupt register. Software interrupts use
vector 27. */
#define portITU_SWINTR ( ( unsigned char * ) 0x000872E0 )
#define portYIELD() *portITU_SWINTR = ( unsigned char ) 0x01; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD()
/*
* These macros should be called directly, but through the taskENTER_CRITICAL()
* and taskEXIT_CRITICAL() macros.
*/
#define portENABLE_INTERRUPTS() __set_interrupt_level( ( unsigned char ) 0 )
#define portDISABLE_INTERRUPTS() __set_interrupt_level( ( unsigned char ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
/* Critical nesting counts are stored in the TCB. */
#define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */
extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void );
#define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */
unsigned long ulPortGetIPL( void );
void vPortSetIPL( unsigned long ulNewIPL );
#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( unsigned char ) ( uxSavedInterruptStatus ) )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/RX600/portmacro.h | C | oos | 6,038 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the SH2A port.
*----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Library includes. */
#include "string.h"
/* Hardware specifics. */
#include <iorx62n.h>
/*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )
#define portINITIAL_FPSW ( ( portSTACK_TYPE ) 0x00000100 )
/*-----------------------------------------------------------*/
/*
* Function to start the first task executing - written in asm code as direct
* access to registers is required.
*/
extern void prvStartFirstTask( void );
/*
* The tick ISR handler. The peripheral used is configured by the application
* via a hook/callback function.
*/
__interrupt void vTickISR( void );
/*-----------------------------------------------------------*/
extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
/* R0 is not included as it is the stack pointer. */
*pxTopOfStack = 0xdeadbeef;
pxTopOfStack--;
*pxTopOfStack = portINITIAL_PSW;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pxCode;
/* When debugging it can be useful if every register is set to a known
value. Otherwise code space can be saved by just setting the registers
that need to be set. */
#ifdef USE_FULL_REGISTER_INITIALISATION
{
pxTopOfStack--;
*pxTopOfStack = 0xffffffff; /* r15. */
pxTopOfStack--;
*pxTopOfStack = 0xeeeeeeee;
pxTopOfStack--;
*pxTopOfStack = 0xdddddddd;
pxTopOfStack--;
*pxTopOfStack = 0xcccccccc;
pxTopOfStack--;
*pxTopOfStack = 0xbbbbbbbb;
pxTopOfStack--;
*pxTopOfStack = 0xaaaaaaaa;
pxTopOfStack--;
*pxTopOfStack = 0x99999999;
pxTopOfStack--;
*pxTopOfStack = 0x88888888;
pxTopOfStack--;
*pxTopOfStack = 0x77777777;
pxTopOfStack--;
*pxTopOfStack = 0x66666666;
pxTopOfStack--;
*pxTopOfStack = 0x55555555;
pxTopOfStack--;
*pxTopOfStack = 0x44444444;
pxTopOfStack--;
*pxTopOfStack = 0x33333333;
pxTopOfStack--;
*pxTopOfStack = 0x22222222;
pxTopOfStack--;
}
#else
{
pxTopOfStack -= 15;
}
#endif
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */
pxTopOfStack--;
*pxTopOfStack = portINITIAL_FPSW;
pxTopOfStack--;
*pxTopOfStack = 0x12345678; /* Accumulator. */
pxTopOfStack--;
*pxTopOfStack = 0x87654321; /* Accumulator. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vApplicationSetupTimerInterrupt( void );
/* Use pxCurrentTCB just so it does not get optimised away. */
if( pxCurrentTCB != NULL )
{
/* Call an application function to set up the timer that will generate the
tick interrupt. This way the application can decide which peripheral to
use. A demo application is provided to show a suitable example. */
vApplicationSetupTimerInterrupt();
/* Enable the software interrupt. */
_IEN( _ICU_SWINT ) = 1;
/* Ensure the software interrupt is clear. */
_IR( _ICU_SWINT ) = 0;
/* Ensure the software interrupt is set to the kernel priority. */
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the first task. */
prvStartFirstTask();
}
/* Should not get here. */
return pdFAIL;
}
/*-----------------------------------------------------------*/
#pragma vector = configTICK_VECTOR
__interrupt void vTickISR( void )
{
/* Re-enable interrupts. */
__enable_interrupt();
/* Increment the tick, and perform any processing the new tick value
necessitates. */
__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
{
vTaskIncrementTick();
}
__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
/* Only select a new task if the preemptive scheduler is being used. */
#if( configUSE_PREEMPTION == 1 )
taskYIELD();
#endif
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* Not implemented as there is nothing to return to. */
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/RX600/port.c | C | oos | 7,618 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
#warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
#endif
#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
#warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
#endif
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned short
#define portBASE_TYPE short
#if __DATA_MODEL__ == __DATA_MODEL_FAR__
#define portPOINTER_SIZE_TYPE unsigned long
#else
#define portPOINTER_SIZE_TYPE unsigned short
#endif
#if ( configUSE_16_BIT_TICKS == 1 )
typedef unsigned int portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned long portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
#define portDISABLE_INTERRUPTS() __asm ( "DI" )
#define portENABLE_INTERRUPTS() __asm ( "EI" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )
#define portENTER_CRITICAL() \
{ \
extern volatile unsigned short usCriticalNesting; \
\
portDISABLE_INTERRUPTS(); \
\
/* Now interrupts are disabled ulCriticalNesting can be accessed */ \
/* directly. Increment ulCriticalNesting to keep a count of how many */ \
/* times portENTER_CRITICAL() has been called. */ \
usCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
extern volatile unsigned short usCriticalNesting; \
\
if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
{ \
/* Decrement the nesting count as we are leaving a critical section. */ \
usCriticalNesting--; \
\
/* If the nesting level has reached zero then interrupts should be */ \
/* re-enabled. */ \
if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
{ \
portENABLE_INTERRUPTS(); \
} \
} \
}
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portYIELD() __asm( "BRK" )
#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
#define portNOP() __asm( "NOP" )
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
#define portBYTE_ALIGNMENT 2
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* --------------------------------------------------------------------------*/
/* Option-bytes and security ID */
/* --------------------------------------------------------------------------*/
#define OPT_BYTES_SIZE 4
#define SECU_ID_SIZE 10
#define WATCHDOG_DISABLED 0x00
#define LVI_ENABLED 0xFE
#define LVI_DISABLED 0xFF
#define RESERVED_FF 0xFF
#define OCD_DISABLED 0x04
#define OCD_ENABLED 0x81
#define OCD_ENABLED_ERASE 0x80
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/RL78/portmacro.h | C | oos | 7,473 |
;/*
; FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
;
;
; ***************************************************************************
; * *
; * FreeRTOS tutorial books are available in pdf and paperback. *
; * Complete, revised, and edited pdf reference manuals are also *
; * available. *
; * *
; * Purchasing FreeRTOS documentation will not only help you, by *
; * ensuring you get running as quickly as possible and with an *
; * in-depth knowledge of how to use FreeRTOS, it will also help *
; * the FreeRTOS project to continue with its mission of providing *
; * professional grade, cross platform, de facto standard solutions *
; * for microcontrollers - completely free of charge! *
; * *
; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
; * *
; * Thank you for using FreeRTOS, and thank you for your support! *
; * *
; ***************************************************************************
;
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
; >>>NOTE<<< The modification to the GPL is included to allow you to
; distribute a combined work that includes FreeRTOS without being obliged to
; provide the source code for proprietary components outside of the FreeRTOS
; kernel. FreeRTOS is distributed in the hope that it will be useful, but
; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
; more details. You should have received a copy of the GNU General Public
; License and the FreeRTOS license exception along with FreeRTOS; if not it
; can be viewed here: http://www.freertos.org/a00114.html and also obtained
; by writing to Richard Barry, contact details for whom are available on the
; FreeRTOS WEB site.
;
; 1 tab == 4 spaces!
;
; http://www.FreeRTOS.org - Documentation, latest information, license and
; contact details.
;
; http://www.SafeRTOS.com - A version that is certified for use in safety
; critical systems.
;
; http://www.OpenRTOS.com - Commercial support, development, porting,
; licensing and training services.
;*/
#include "FreeRTOSConfig.h"
; Variables used by scheduler
;------------------------------------------------------------------------------
EXTERN pxCurrentTCB
EXTERN usCriticalNesting
;------------------------------------------------------------------------------
; portSAVE_CONTEXT MACRO
; Saves the context of the general purpose registers, CS and ES (only in far
; memory mode) registers the usCriticalNesting Value and the Stack Pointer
; of the active Task onto the task stack
;------------------------------------------------------------------------------
portSAVE_CONTEXT MACRO
PUSH AX ; Save AX Register to stack.
PUSH HL
#if __DATA_MODEL__ == __DATA_MODEL_FAR__
MOV A, CS ; Save CS register.
XCH A, X
MOV A, ES ; Save ES register.
PUSH AX
#else
MOV A, CS ; Save CS register.
PUSH AX
#endif
PUSH DE ; Save the remaining general purpose registers.
PUSH BC
MOVW AX, usCriticalNesting ; Save the usCriticalNesting value.
PUSH AX
MOVW AX, pxCurrentTCB ; Save the Stack pointer.
MOVW HL, AX
MOVW AX, SP
MOVW [HL], AX
ENDM
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; portRESTORE_CONTEXT MACRO
; Restores the task Stack Pointer then use this to restore usCriticalNesting,
; general purpose registers and the CS and ES (only in far memory mode)
; of the selected task from the task stack
;------------------------------------------------------------------------------
portRESTORE_CONTEXT MACRO
MOVW AX, pxCurrentTCB ; Restore the Stack pointer.
MOVW HL, AX
MOVW AX, [HL]
MOVW SP, AX
POP AX ; Restore usCriticalNesting value.
MOVW usCriticalNesting, AX
POP BC ; Restore the necessary general purpose registers.
POP DE
#if __DATA_MODEL__ == __DATA_MODEL_FAR__
POP AX ; Restore the ES register.
MOV ES, A
XCH A, X ; Restore the CS register.
MOV CS, A
#else
POP AX
MOV CS, A ; Restore CS register.
#endif
POP HL ; Restore general purpose register HL.
POP AX ; Restore AX.
ENDM
;------------------------------------------------------------------------------
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/RL78/ISR_Support.h | C | oos | 5,628 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* The critical nesting value is initialised to a non zero value to ensure
interrupts don't accidentally become enabled before the scheduler is started. */
#define portINITIAL_CRITICAL_NESTING ( ( unsigned short ) 10 )
/* Initial PSW value allocated to a newly created task.
* 1100011000000000
* ||||||||-------------- Fill byte
* |||||||--------------- Carry Flag cleared
* |||||----------------- In-service priority Flags set to low level
* ||||------------------ Register bank Select 0 Flag cleared
* |||------------------- Auxiliary Carry Flag cleared
* ||-------------------- Register bank Select 1 Flag cleared
* |--------------------- Zero Flag set
* ---------------------- Global Interrupt Flag set (enabled)
*/
#define portPSW ( 0xc6UL )
/* The address of the pxCurrentTCB variable, but don't know or need to know its
type. */
typedef void tskTCB;
extern volatile tskTCB * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each time
a critical section is entered the count is incremented. Each time a critical
section is exited the count is decremented - with interrupts only being
re-enabled if the count is zero.
usCriticalNesting will get set to zero when the scheduler starts, but must
not be initialised to zero as that could cause problems during the startup
sequence. */
volatile unsigned short usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
/*
* Sets up the periodic ISR used for the RTOS tick.
*/
static void prvSetupTimerInterrupt( void );
/*
* Defined in portasm.s87, this function starts the scheduler by loading the
* context of the first task to run.
*/
extern void vPortStartFirstTask( void );
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See the header file portable.h.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
unsigned long *pulLocal;
#if __DATA_MODEL__ == __DATA_MODEL_FAR__
{
/* Parameters are passed in on the stack, and written using a 32bit value
hence a space is left for the second two bytes. */
pxTopOfStack--;
/* Write in the parameter value. */
pulLocal = ( unsigned long * ) pxTopOfStack;
*pulLocal = ( unsigned long ) pvParameters;
pxTopOfStack--;
/* These values are just spacers. The return address of the function
would normally be written here. */
*pxTopOfStack = ( portSTACK_TYPE ) 0xcdcd;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xcdcd;
pxTopOfStack--;
/* The start address / PSW value is also written in as a 32bit value,
so leave a space for the second two bytes. */
pxTopOfStack--;
/* Task function start address combined with the PSW. */
pulLocal = ( unsigned long * ) pxTopOfStack;
*pulLocal = ( ( ( unsigned long ) pxCode ) | ( portPSW << 24UL ) );
pxTopOfStack--;
/* An initial value for the AX register. */
*pxTopOfStack = ( portSTACK_TYPE ) 0x1111;
pxTopOfStack--;
}
#else
{
/* Task function address is written to the stack first. As it is
written as a 32bit value a space is left on the stack for the second
two bytes. */
pxTopOfStack--;
/* Task function start address combined with the PSW. */
pulLocal = ( unsigned long * ) pxTopOfStack;
*pulLocal = ( ( ( unsigned long ) pxCode ) | ( portPSW << 24UL ) );
pxTopOfStack--;
/* The parameter is passed in AX. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
pxTopOfStack--;
}
#endif
/* An initial value for the HL register. */
*pxTopOfStack = ( portSTACK_TYPE ) 0x2222;
pxTopOfStack--;
/* CS and ES registers. */
*pxTopOfStack = ( portSTACK_TYPE ) 0x0F00;
pxTopOfStack--;
/* Finally the remaining general purpose registers DE and BC */
*pxTopOfStack = ( portSTACK_TYPE ) 0xDEDE;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xBCBC;
pxTopOfStack--;
/* Finally the critical section nesting count is set to zero when the task
first starts. */
*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING;
/* Return a pointer to the top of the stack that has beene generated so it
can be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
/* Setup the hardware to generate the tick. Interrupts are disabled when
this function is called. */
prvSetupTimerInterrupt();
/* Restore the context of the first task that is going to run. */
vPortStartFirstTask();
/* Execution should not reach here as the tasks are now running! */
return pdTRUE;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the RL78/G13 port will get stopped. If required simply
disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
const unsigned short usClockHz = 15000UL; /* Internal clock. */
const unsigned short usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
/* Use the internal 15K clock. */
OSMC = 0x16U;
/* Supply the RTC clock. */
RTCEN = 1U;
/* Disable ITMC operation. */
ITMC = 0x0000;
/* Disable INTIT interrupt. */
ITMK = 1U;
/* Set INTIT high priority */
ITPR1 = 1U;
ITPR0 = 1U;
/* Set interval. */
ITMC = usCompareMatch;
/* Clear INIT interrupt. */
ITIF = 0U;
/* Enable INTIT interrupt. */
ITMK = 0U;
/* Enable IT operation. */
ITMC |= 0x8000;
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/RL78/port.c | C | oos | 8,971 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
#include <intrinsics.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portLONG
#define portBASE_TYPE portLONG
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portYIELD() asm ( "SWI 0" )
#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
__arm __interwork void vPortDisableInterruptsFromThumb( void );
__arm __interwork void vPortEnableInterruptsFromThumb( void );
__arm __interwork void vPortEnterCritical( void );
__arm __interwork void vPortExitCritical( void );
#define portDISABLE_INTERRUPTS() __disable_interrupt()
#define portENABLE_INTERRUPTS() __enable_interrupt()
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern void vTaskSwitchContext( void ); \
\
if( xSwitchRequired ) \
{ \
vTaskSwitchContext(); \
} \
}
/*-----------------------------------------------------------*/
/* EIC utilities. */
#define portEIC_CICR_ADDR *( ( unsigned portLONG * ) 0xFFFFF804 )
#define portEIC_IPR_ADDR *( ( unsigned portLONG * ) 0xFFFFF840 )
#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR71x/portmacro.h | C | oos | 5,750 |
EXTERN pxCurrentTCB
EXTERN ulCriticalNesting
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Context save and restore macro definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
; Push R0 as we are going to use the register.
STMDB SP!, {R0}
; Set R0 to point to the task stack pointer.
STMDB SP, {SP}^
NOP
SUB SP, SP, #4
LDMIA SP!, {R0}
; Push the return address onto the stack.
STMDB R0!, {LR}
; Now we have saved LR we can use it instead of R0.
MOV LR, R0
; Pop R0 so we can save it onto the system mode stack.
LDMIA SP!, {R0}
; Push all the system mode registers onto the task stack.
STMDB LR, {R0-LR}^
NOP
SUB LR, LR, #60
; Push the SPSR onto the task stack.
MRS R0, SPSR
STMDB LR!, {R0}
LDR R0, =ulCriticalNesting
LDR R0, [R0]
STMDB LR!, {R0}
; Store the new top of stack for the task.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
STR LR, [R0]
ENDM
portRESTORE_CONTEXT MACRO
; Set the LR to the task stack.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
LDR LR, [R0]
; The critical nesting depth is the first item on the stack.
; Load it into the ulCriticalNesting variable.
LDR R0, =ulCriticalNesting
LDMFD LR!, {R1}
STR R1, [R0]
; Get the SPSR from the stack.
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
; Restore all system mode registers for the task.
LDMFD LR, {R0-R14}^
NOP
; Restore the return address.
LDR LR, [LR, #+60]
; And return - correcting the offset in the LR to obtain the
; correct address.
SUBS PC, LR, #4
ENDM
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR71x/ISR_Support.h | C | oos | 1,770 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the ST STR71x ARM7
* port.
*----------------------------------------------------------*/
/* Library includes. */
#include "wdg.h"
#include "eic.h"
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Constants required to setup the initial stack. */
#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
/* Constants required to handle critical sections. */
#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
#define portMICROS_PER_SECOND 1000000
/*-----------------------------------------------------------*/
/* Setup the watchdog to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
cannot be initialised to 0 as this will cause interrupts to be enabled
during the kernel initialisation process. */
unsigned long ulCriticalNesting = ( unsigned long ) 9999;
/* Tick interrupt routines for cooperative and preemptive operation
respectively. The preemptive version is not defined as __irq as it is called
from an asm wrapper function. */
__arm __irq void vPortNonPreemptiveTick( void );
void vPortPreemptiveTick( void );
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
portSTACK_TYPE *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
pxTopOfStack--;
/* The status register is set for system mode, with interrupts enabled. */
*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00UL )
{
/* We want the task to start in thumb mode. */
*pxTopOfStack |= portTHUMB_MODE_BIT;
}
pxTopOfStack--;
/* Interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
vPortStartFirstTask();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
}
/*-----------------------------------------------------------*/
/* The cooperative scheduler requires a normal IRQ service routine to
simply increment the system tick. */
__arm __irq void vPortNonPreemptiveTick( void )
{
/* Increment the tick count - which may wake some tasks but as the
preemptive scheduler is not being used any woken task is not given
processor time no matter what its priority. */
vTaskIncrementTick();
/* Clear the interrupt in the watchdog and EIC. */
WDG->SR = 0x0000;
portCLEAR_EIC();
}
/*-----------------------------------------------------------*/
/* This function is called from an asm wrapper, so does not require the __irq
keyword. */
void vPortPreemptiveTick( void )
{
/* Increment the tick counter. */
vTaskIncrementTick();
/* The new tick value might unblock a task. Ensure the highest task that
is ready to execute is the task that will execute when the tick ISR
exits. */
vTaskSwitchContext();
/* Clear the interrupt in the watchdog and EIC. */
WDG->SR = 0x0000;
portCLEAR_EIC();
}
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
/* Set the watchdog up to generate a periodic tick. */
WDG_ECITConfig( DISABLE );
WDG_CntOnOffConfig( DISABLE );
WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ );
/* Setup the tick interrupt in the EIC. */
EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );
EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );
EIC_IRQConfig( ENABLE );
WDG_ECITConfig( ENABLE );
/* Start the timer - interrupts are actually disabled at this point so
it is safe to do this here. */
WDG_CntOnOffConfig( ENABLE );
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortEnterCritical( void )
{
/* Disable interrupts first! */
__disable_interrupt();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
__arm __interwork void vPortExitCritical( void )
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as we are leaving a critical section. */
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
__enable_interrupt();
}
}
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/STR71x/port.c | C | oos | 10,514 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Hardware includes. */
#include "msp430.h"
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT int
#define portBASE_TYPE portSHORT
/* The stack type changes depending on the data model. */
#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
#define portSTACK_TYPE unsigned short
#else
#define portSTACK_TYPE unsigned long
#endif
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
#define portDISABLE_INTERRUPTS() _DINT()
#define portENABLE_INTERRUPTS() _EINT()
/*-----------------------------------------------------------*/
/* Critical section control macros. */
#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )
#define portENTER_CRITICAL() \
{ \
extern volatile unsigned short usCriticalNesting; \
\
portDISABLE_INTERRUPTS(); \
\
/* Now interrupts are disabled usCriticalNesting can be accessed */ \
/* directly. Increment ulCriticalNesting to keep a count of how many */ \
/* times portENTER_CRITICAL() has been called. */ \
usCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
extern volatile unsigned short usCriticalNesting; \
\
if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
{ \
/* Decrement the nesting count as we are leaving a critical section. */ \
usCriticalNesting--; \
\
/* If the nesting level has reached zero then interrupts should be */ \
/* re-enabled. */ \
if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
{ \
portENABLE_INTERRUPTS(); \
} \
} \
}
/*-----------------------------------------------------------*/
/* Task utilities. */
/*
* Manual context switch called by portYIELD or taskYIELD.
*/
extern void vPortYield( void );
#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 2
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portNOP() __no_operation()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
extern void vTaskSwitchContext( void );
#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
void vApplicationSetupTimerInterrupt( void );
/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
run time stats information is to be displayed. */
#define portLU_PRINTF_SPECIFIER_REQUIRED
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/MSP430X/portmacro.h | C | oos | 6,688 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef DATA_MODEL_H
#define DATA_MODEL_H
#ifdef __DATA_MODEL_SMALL__
#define pushm_x pushm.w
#define popm_x popm.w
#define push_x push.w
#define pop_x pop.w
#define mov_x mov.w
#define cmp_x cmp.w
#endif
#ifdef __DATA_MODEL_MEDIUM__
#define pushm_x pushm.a
#define popm_x popm.a
#define push_x pushx.a
#define pop_x popx.a
#define mov_x mov.w
#define cmp_x cmp.w
#endif
#ifdef __DATA_MODEL_LARGE__
#define pushm_x pushm.a
#define popm_x popm.a
#define push_x pushx.a
#define pop_x popx.a
#define mov_x movx.a
#define cmp_x cmpx.a
#endif
#ifndef pushm_x
#error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__
#endif
#endif /* DATA_MODEL_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/MSP430X/data_model.h | C | oos | 3,755 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the MSP430X port.
*----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
not the MCLK. */
#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 )
#define portINITIAL_CRITICAL_NESTING ( ( unsigned short ) 10 )
#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
typedef void tskTCB;
extern volatile tskTCB * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each
time a critical section is entered the count is incremented. Each time a
critical section is exited the count is decremented - with interrupts only
being re-enabled if the count is zero.
usCriticalNesting will get set to zero when the scheduler starts, but must
not be initialised to zero as this will cause problems during the startup
sequence. */
volatile unsigned short usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
/*
* Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
* could have alternatively used the watchdog timer or timer 1.
*/
void vPortSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See the header file portable.h.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
unsigned short *pusTopOfStack;
unsigned long *pulTopOfStack;
/*
Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging and can be included if required.
*pxTopOfStack = ( portSTACK_TYPE ) 0x1111;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x2222;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x3333;
*/
/* portSTACK_TYPE is either 16 bits or 32 bits depending on the data model.
Some stacked items do not change size depending on the data model so have
to be explicitly cast to the correct size so this function will work
whichever data model is being used. */
if( sizeof( portSTACK_TYPE ) == sizeof( unsigned short ) )
{
/* Make room for a 20 bit value stored as a 32 bit value. */
pusTopOfStack = ( unsigned short * ) pxTopOfStack;
pusTopOfStack--;
pulTopOfStack = ( unsigned long * ) pusTopOfStack;
}
else
{
pulTopOfStack = ( unsigned long * ) pxTopOfStack;
}
*pulTopOfStack = ( unsigned long ) pxCode;
pusTopOfStack = ( unsigned short * ) pulTopOfStack;
pusTopOfStack--;
*pusTopOfStack = portFLAGS_INT_ENABLED;
pusTopOfStack -= ( sizeof( portSTACK_TYPE ) / 2 );
/* From here on the size of stacked items depends on the memory model. */
pxTopOfStack = ( portSTACK_TYPE * ) pusTopOfStack;
/* Next the general purpose registers. */
#ifdef PRELOAD_REGISTER_VALUES
*pxTopOfStack = ( portSTACK_TYPE ) 0xffff;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xeeee;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xdddd;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x9999;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x8888;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x5555;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x6666;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x5555;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x4444;
pxTopOfStack--;
#else
pxTopOfStack -= 3;
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
pxTopOfStack -= 9;
#endif
/* A variable is used to keep track of the critical section nesting.
This variable has to be stored as part of the task context and is
initially set to zero. */
*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING;
/* Return a pointer to the top of the stack we have generated so this can
be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the MSP430 port will get stopped. If required simply
disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
/*
* Hardware initialisation to generate the RTOS tick.
*/
void vPortSetupTimerInterrupt( void )
{
vApplicationSetupTimerInterrupt();
}
/*-----------------------------------------------------------*/
#pragma vector=configTICK_VECTOR
__interrupt __raw void vTickISREntry( void )
{
extern void vPortTickISR( void );
vPortTickISR();
}
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/MSP430X/port.c | C | oos | 8,173 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT int
#define portSTACK_TYPE unsigned portSHORT
#define portBASE_TYPE portSHORT
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
#define portDISABLE_INTERRUPTS() _DINT();
#define portENABLE_INTERRUPTS() _EINT();
/*-----------------------------------------------------------*/
/* Critical section control macros. */
#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )
#define portENTER_CRITICAL() \
{ \
extern volatile unsigned portSHORT usCriticalNesting; \
\
portDISABLE_INTERRUPTS(); \
\
/* Now interrupts are disabled usCriticalNesting can be accessed */ \
/* directly. Increment ulCriticalNesting to keep a count of how many */ \
/* times portENTER_CRITICAL() has been called. */ \
usCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
extern volatile unsigned portSHORT usCriticalNesting; \
\
if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
{ \
/* Decrement the nesting count as we are leaving a critical section. */ \
usCriticalNesting--; \
\
/* If the nesting level has reached zero then interrupts should be */ \
/* re-enabled. */ \
if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
{ \
portENABLE_INTERRUPTS(); \
} \
} \
}
/*-----------------------------------------------------------*/
/* Task utilities. */
/*
* Manual context switch called by portYIELD or taskYIELD.
*/
extern void vPortYield( void );
#define portYIELD() vPortYield()
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 2
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portNOP()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#if configINTERRUPT_EXAMPLE_METHOD == 2
extern void vTaskSwitchContext( void );
#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/MSP430/portmacro.h | C | oos | 6,307 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTASM_H
#define PORTASM_H
portSAVE_CONTEXT macro
IMPORT pxCurrentTCB
IMPORT usCriticalNesting
/* Save the remaining registers. */
push r4
push r5
push r6
push r7
push r8
push r9
push r10
push r11
push r12
push r13
push r14
push r15
mov.w &usCriticalNesting, r14
push r14
mov.w &pxCurrentTCB, r12
mov.w r1, 0(r12)
endm
/*-----------------------------------------------------------*/
portRESTORE_CONTEXT macro
mov.w &pxCurrentTCB, r12
mov.w @r12, r1
pop r15
mov.w r15, &usCriticalNesting
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop r8
pop r7
pop r6
pop r5
pop r4
/* The last thing on the stack will be the status register.
Ensure the power down bits are clear ready for the next
time this power down register is popped from the stack. */
bic.w #0xf0,0(SP)
reti
endm
/*-----------------------------------------------------------*/
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/MSP430/portasm.h | C | oos | 4,005 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the MSP430 port.
*----------------------------------------------------------*/
/* Constants required for hardware setup. The tick ISR runs off the ACLK,
not the MCLK. */
#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 )
#define portINITIAL_CRITICAL_NESTING ( ( unsigned short ) 10 )
#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 )
/* We require the address of the pxCurrentTCB variable, but don't want to know
any details of its type. */
typedef void tskTCB;
extern volatile tskTCB * volatile pxCurrentTCB;
/* Each task maintains a count of the critical section nesting depth. Each
time a critical section is entered the count is incremented. Each time a
critical section is exited the count is decremented - with interrupts only
being re-enabled if the count is zero.
usCriticalNesting will get set to zero when the scheduler starts, but must
not be initialised to zero as this will cause problems during the startup
sequence. */
volatile unsigned short usCriticalNesting = portINITIAL_CRITICAL_NESTING;
/*-----------------------------------------------------------*/
/*
* Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
* could have alternatively used the watchdog timer or timer 1.
*/
void vPortSetupTimerInterrupt( void );
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See the header file portable.h.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
/*
Place a few bytes of known values on the bottom of the stack.
This is just useful for debugging and can be included if required.
*pxTopOfStack = ( portSTACK_TYPE ) 0x1111;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x2222;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x3333;
pxTopOfStack--;
*/
/* The msp430 automatically pushes the PC then SR onto the stack before
executing an ISR. We want the stack to look just as if this has happened
so place a pointer to the start of the task on the stack first - followed
by the flags we want the task to use when it starts up. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode;
pxTopOfStack--;
*pxTopOfStack = portFLAGS_INT_ENABLED;
pxTopOfStack--;
/* Next the general purpose registers. */
*pxTopOfStack = ( portSTACK_TYPE ) 0x4444;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x5555;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x6666;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x7777;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x8888;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x9999;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb;
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R15. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xdddd;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xeeee;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xffff;
pxTopOfStack--;
/* A variable is used to keep track of the critical section nesting.
This variable has to be stored as part of the task context and is
initially set to zero. */
*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING;
/* Return a pointer to the top of the stack we have generated so this can
be stored in the task control block for the task. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the MSP430 port will get stopped. If required simply
disable the tick interrupt here. */
}
/*-----------------------------------------------------------*/
/*
* Hardware initialisation to generate the RTOS tick. This uses timer 0
* but could alternatively use the watchdog timer or timer 1.
*/
void vPortSetupTimerInterrupt( void )
{
/* Ensure the timer is stopped. */
TACTL = 0;
/* Run the timer of the ACLK. */
TACTL = TASSEL_1;
/* Clear everything to start with. */
TACTL |= TACLR;
/* Set the compare match value according to the tick rate we want. */
TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
/* Enable the interrupts. */
TACCTL0 = CCIE;
/* Start up clean. */
TACTL |= TACLR;
/* Up mode. */
TACTL |= MC_1;
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/MSP430/port.c | C | oos | 7,841 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name : AT91SAM7S64.h
// Object : AT91SAM7S64 definitions
// Generated : AT91 SW Application Group 07/16/2004 (07:43:09)
//
// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002//
// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002//
// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003//
// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
// ----------------------------------------------------------------------------
// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
// *** Register offset in AT91S_SYSC structure ***
#define SYSC_AIC_SMR ( 0) // Source Mode Register
#define SYSC_AIC_SVR (128) // Source Vector Register
#define SYSC_AIC_IVR (256) // IRQ Vector Register
#define SYSC_AIC_FVR (260) // FIQ Vector Register
#define SYSC_AIC_ISR (264) // Interrupt Status Register
#define SYSC_AIC_IPR (268) // Interrupt Pending Register
#define SYSC_AIC_IMR (272) // Interrupt Mask Register
#define SYSC_AIC_CISR (276) // Core Interrupt Status Register
#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register
#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register
#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register
#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register
#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register
#define SYSC_AIC_SPU (308) // Spurious Vector Register
#define SYSC_AIC_DCR (312) // Debug Control Register (Protect)
#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register
#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register
#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register
#define SYSC_DBGU_CR (512) // Control Register
#define SYSC_DBGU_MR (516) // Mode Register
#define SYSC_DBGU_IER (520) // Interrupt Enable Register
#define SYSC_DBGU_IDR (524) // Interrupt Disable Register
#define SYSC_DBGU_IMR (528) // Interrupt Mask Register
#define SYSC_DBGU_CSR (532) // Channel Status Register
#define SYSC_DBGU_RHR (536) // Receiver Holding Register
#define SYSC_DBGU_THR (540) // Transmitter Holding Register
#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register
#define SYSC_DBGU_C1R (576) // Chip ID1 Register
#define SYSC_DBGU_C2R (580) // Chip ID2 Register
#define SYSC_DBGU_FNTR (584) // Force NTRST Register
#define SYSC_DBGU_RPR (768) // Receive Pointer Register
#define SYSC_DBGU_RCR (772) // Receive Counter Register
#define SYSC_DBGU_TPR (776) // Transmit Pointer Register
#define SYSC_DBGU_TCR (780) // Transmit Counter Register
#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register
#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register
#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register
#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register
#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register
#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register
#define SYSC_PIOA_PER (1024) // PIO Enable Register
#define SYSC_PIOA_PDR (1028) // PIO Disable Register
#define SYSC_PIOA_PSR (1032) // PIO Status Register
#define SYSC_PIOA_OER (1040) // Output Enable Register
#define SYSC_PIOA_ODR (1044) // Output Disable Registerr
#define SYSC_PIOA_OSR (1048) // Output Status Register
#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register
#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register
#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register
#define SYSC_PIOA_SODR (1072) // Set Output Data Register
#define SYSC_PIOA_CODR (1076) // Clear Output Data Register
#define SYSC_PIOA_ODSR (1080) // Output Data Status Register
#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register
#define SYSC_PIOA_IER (1088) // Interrupt Enable Register
#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register
#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register
#define SYSC_PIOA_ISR (1100) // Interrupt Status Register
#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register
#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register
#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register
#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
#define SYSC_PIOA_ASR (1136) // Select A Register
#define SYSC_PIOA_BSR (1140) // Select B Register
#define SYSC_PIOA_ABSR (1144) // AB Select Status Register
#define SYSC_PIOA_OWER (1184) // Output Write Enable Register
#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register
#define SYSC_PIOA_OWSR (1192) // Output Write Status Register
#define SYSC_PMC_SCER (3072) // System Clock Enable Register
#define SYSC_PMC_SCDR (3076) // System Clock Disable Register
#define SYSC_PMC_SCSR (3080) // System Clock Status Register
#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register
#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register
#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register
#define SYSC_PMC_MOR (3104) // Main Oscillator Register
#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register
#define SYSC_PMC_PLLR (3116) // PLL Register
#define SYSC_PMC_MCKR (3120) // Master Clock Register
#define SYSC_PMC_PCKR (3136) // Programmable Clock Register
#define SYSC_PMC_IER (3168) // Interrupt Enable Register
#define SYSC_PMC_IDR (3172) // Interrupt Disable Register
#define SYSC_PMC_SR (3176) // Status Register
#define SYSC_PMC_IMR (3180) // Interrupt Mask Register
#define SYSC_RSTC_RCR (3328) // Reset Control Register
#define SYSC_RSTC_RSR (3332) // Reset Status Register
#define SYSC_RSTC_RMR (3336) // Reset Mode Register
#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register
#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register
#define SYSC_RTTC_RTVR (3368) // Real-time Value Register
#define SYSC_RTTC_RTSR (3372) // Real-time Status Register
#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register
#define SYSC_PITC_PISR (3380) // Period Interval Status Register
#define SYSC_PITC_PIVR (3384) // Period Interval Value Register
#define SYSC_PITC_PIIR (3388) // Period Interval Image Register
#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register
#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register
#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register
#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register
// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register --------
#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR ( 0) // Source Mode Register
#define AIC_SVR (128) // Source Vector Register
#define AIC_IVR (256) // IRQ Vector Register
#define AIC_FVR (260) // FIQ Vector Register
#define AIC_ISR (264) // Interrupt Status Register
#define AIC_IPR (268) // Interrupt Pending Register
#define AIC_IMR (272) // Interrupt Mask Register
#define AIC_CISR (276) // Core Interrupt Status Register
#define AIC_IECR (288) // Interrupt Enable Command Register
#define AIC_IDCR (292) // Interrupt Disable Command Register
#define AIC_ICCR (296) // Interrupt Clear Command Register
#define AIC_ISCR (300) // Interrupt Set Command Register
#define AIC_EOICR (304) // End of Interrupt Command Register
#define AIC_SPU (308) // Spurious Vector Register
#define AIC_DCR (312) // Debug Control Register (Protect)
#define AIC_FFER (320) // Fast Forcing Enable Register
#define AIC_FFDR (324) // Fast Forcing Disable Register
#define AIC_FFSR (328) // Fast Forcing Status Register
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
// *** Register offset in AT91S_DBGU structure ***
#define DBGU_CR ( 0) // Control Register
#define DBGU_MR ( 4) // Mode Register
#define DBGU_IER ( 8) // Interrupt Enable Register
#define DBGU_IDR (12) // Interrupt Disable Register
#define DBGU_IMR (16) // Interrupt Mask Register
#define DBGU_CSR (20) // Channel Status Register
#define DBGU_RHR (24) // Receiver Holding Register
#define DBGU_THR (28) // Transmitter Holding Register
#define DBGU_BRGR (32) // Baud Rate Generator Register
#define DBGU_C1R (64) // Chip ID1 Register
#define DBGU_C2R (68) // Chip ID2 Register
#define DBGU_FNTR (72) // Force NTRST Register
#define DBGU_RPR (256) // Receive Pointer Register
#define DBGU_RCR (260) // Receive Counter Register
#define DBGU_TPR (264) // Transmit Pointer Register
#define DBGU_TCR (268) // Transmit Counter Register
#define DBGU_RNPR (272) // Receive Next Pointer Register
#define DBGU_RNCR (276) // Receive Next Counter Register
#define DBGU_TNPR (280) // Transmit Next Pointer Register
#define DBGU_TNCR (284) // Transmit Next Counter Register
#define DBGU_PTCR (288) // PDC Transfer Control Register
#define DBGU_PTSR (292) // PDC Transfer Status Register
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral Data Controller
// *****************************************************************************
// *** Register offset in AT91S_PDC structure ***
#define PDC_RPR ( 0) // Receive Pointer Register
#define PDC_RCR ( 4) // Receive Counter Register
#define PDC_TPR ( 8) // Transmit Pointer Register
#define PDC_TCR (12) // Transmit Counter Register
#define PDC_RNPR (16) // Receive Next Pointer Register
#define PDC_RNCR (20) // Receive Next Counter Register
#define PDC_TNPR (24) // Transmit Next Pointer Register
#define PDC_TNCR (28) // Transmit Next Counter Register
#define PDC_PTCR (32) // PDC Transfer Control Register
#define PDC_PTSR (36) // PDC Transfer Status Register
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
// *** Register offset in AT91S_PIO structure ***
#define PIO_PER ( 0) // PIO Enable Register
#define PIO_PDR ( 4) // PIO Disable Register
#define PIO_PSR ( 8) // PIO Status Register
#define PIO_OER (16) // Output Enable Register
#define PIO_ODR (20) // Output Disable Registerr
#define PIO_OSR (24) // Output Status Register
#define PIO_IFER (32) // Input Filter Enable Register
#define PIO_IFDR (36) // Input Filter Disable Register
#define PIO_IFSR (40) // Input Filter Status Register
#define PIO_SODR (48) // Set Output Data Register
#define PIO_CODR (52) // Clear Output Data Register
#define PIO_ODSR (56) // Output Data Status Register
#define PIO_PDSR (60) // Pin Data Status Register
#define PIO_IER (64) // Interrupt Enable Register
#define PIO_IDR (68) // Interrupt Disable Register
#define PIO_IMR (72) // Interrupt Mask Register
#define PIO_ISR (76) // Interrupt Status Register
#define PIO_MDER (80) // Multi-driver Enable Register
#define PIO_MDDR (84) // Multi-driver Disable Register
#define PIO_MDSR (88) // Multi-driver Status Register
#define PIO_PPUDR (96) // Pull-up Disable Register
#define PIO_PPUER (100) // Pull-up Enable Register
#define PIO_PPUSR (104) // Pad Pull-up Status Register
#define PIO_ASR (112) // Select A Register
#define PIO_BSR (116) // Select B Register
#define PIO_ABSR (120) // AB Select Status Register
#define PIO_OWER (160) // Output Write Enable Register
#define PIO_OWDR (164) // Output Write Disable Register
#define PIO_OWSR (168) // Output Write Status Register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
// *** Register offset in AT91S_CKGR structure ***
#define CKGR_MOR ( 0) // Main Oscillator Register
#define CKGR_MCFR ( 4) // Main Clock Frequency Register
#define CKGR_PLLR (12) // PLL Register
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
// *** Register offset in AT91S_PMC structure ***
#define PMC_SCER ( 0) // System Clock Enable Register
#define PMC_SCDR ( 4) // System Clock Disable Register
#define PMC_SCSR ( 8) // System Clock Status Register
#define PMC_PCER (16) // Peripheral Clock Enable Register
#define PMC_PCDR (20) // Peripheral Clock Disable Register
#define PMC_PCSR (24) // Peripheral Clock Status Register
#define PMC_MOR (32) // Main Oscillator Register
#define PMC_MCFR (36) // Main Clock Frequency Register
#define PMC_PLLR (44) // PLL Register
#define PMC_MCKR (48) // Master Clock Register
#define PMC_PCKR (64) // Programmable Clock Register
#define PMC_IER (96) // Interrupt Enable Register
#define PMC_IDR (100) // Interrupt Disable Register
#define PMC_SR (104) // Status Register
#define PMC_IMR (108) // Interrupt Mask Register
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RSTC structure ***
#define RSTC_RCR ( 0) // Reset Control Register
#define RSTC_RSR ( 4) // Reset Status Register
#define RSTC_RMR ( 8) // Reset Mode Register
// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password
// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status
#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset.
#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RTTC structure ***
#define RTTC_RTMR ( 0) // Real-time Mode Register
#define RTTC_RTAR ( 4) // Real-time Alarm Register
#define RTTC_RTVR ( 8) // Real-time Value Register
#define RTTC_RTSR (12) // Real-time Status Register
// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PITC structure ***
#define PITC_PIMR ( 0) // Period Interval Mode Register
#define PITC_PISR ( 4) // Period Interval Status Register
#define PITC_PIVR ( 8) // Period Interval Value Register
#define PITC_PIIR (12) // Period Interval Image Register
// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_WDTC structure ***
#define WDTC_WDCR ( 0) // Watchdog Control Register
#define WDTC_WDMR ( 4) // Watchdog Mode Register
#define WDTC_WDSR ( 8) // Watchdog Status Register
// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_MC structure ***
#define MC_RCR ( 0) // MC Remap Control Register
#define MC_ASR ( 4) // MC Abort Status Register
#define MC_AASR ( 8) // MC Abort Address Status Register
#define MC_FMR (96) // MC Flash Mode Register
#define MC_FCR (100) // MC Flash Command Register
#define MC_FSR (104) // MC Flash Status Register
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
// *** Register offset in AT91S_SPI structure ***
#define SPI_CR ( 0) // Control Register
#define SPI_MR ( 4) // Mode Register
#define SPI_RDR ( 8) // Receive Data Register
#define SPI_TDR (12) // Transmit Data Register
#define SPI_SR (16) // Status Register
#define SPI_IER (20) // Interrupt Enable Register
#define SPI_IDR (24) // Interrupt Disable Register
#define SPI_IMR (28) // Interrupt Mask Register
#define SPI_CSR (48) // Chip Select Register
#define SPI_RPR (256) // Receive Pointer Register
#define SPI_RCR (260) // Receive Counter Register
#define SPI_TPR (264) // Transmit Pointer Register
#define SPI_TCR (268) // Transmit Counter Register
#define SPI_RNPR (272) // Receive Next Pointer Register
#define SPI_RNCR (276) // Receive Next Counter Register
#define SPI_TNPR (280) // Transmit Next Pointer Register
#define SPI_TNCR (284) // Transmit Next Counter Register
#define SPI_PTCR (288) // PDC Transfer Control Register
#define SPI_PTSR (292) // PDC Transfer Status Register
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
// *** Register offset in AT91S_ADC structure ***
#define ADC_CR ( 0) // ADC Control Register
#define ADC_MR ( 4) // ADC Mode Register
#define ADC_CHER (16) // ADC Channel Enable Register
#define ADC_CHDR (20) // ADC Channel Disable Register
#define ADC_CHSR (24) // ADC Channel Status Register
#define ADC_SR (28) // ADC Status Register
#define ADC_LCDR (32) // ADC Last Converted Data Register
#define ADC_IER (36) // ADC Interrupt Enable Register
#define ADC_IDR (40) // ADC Interrupt Disable Register
#define ADC_IMR (44) // ADC Interrupt Mask Register
#define ADC_CDR0 (48) // ADC Channel Data Register 0
#define ADC_CDR1 (52) // ADC Channel Data Register 1
#define ADC_CDR2 (56) // ADC Channel Data Register 2
#define ADC_CDR3 (60) // ADC Channel Data Register 3
#define ADC_CDR4 (64) // ADC Channel Data Register 4
#define ADC_CDR5 (68) // ADC Channel Data Register 5
#define ADC_CDR6 (72) // ADC Channel Data Register 6
#define ADC_CDR7 (76) // ADC Channel Data Register 7
#define ADC_RPR (256) // Receive Pointer Register
#define ADC_RCR (260) // Receive Counter Register
#define ADC_TPR (264) // Transmit Pointer Register
#define ADC_TCR (268) // Transmit Counter Register
#define ADC_RNPR (272) // Receive Next Pointer Register
#define ADC_RNCR (276) // Receive Next Counter Register
#define ADC_TNPR (280) // Transmit Next Pointer Register
#define ADC_TNCR (284) // Transmit Next Counter Register
#define ADC_PTCR (288) // PDC Transfer Control Register
#define ADC_PTSR (292) // PDC Transfer Status Register
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_SSC structure ***
#define SSC_CR ( 0) // Control Register
#define SSC_CMR ( 4) // Clock Mode Register
#define SSC_RCMR (16) // Receive Clock ModeRegister
#define SSC_RFMR (20) // Receive Frame Mode Register
#define SSC_TCMR (24) // Transmit Clock Mode Register
#define SSC_TFMR (28) // Transmit Frame Mode Register
#define SSC_RHR (32) // Receive Holding Register
#define SSC_THR (36) // Transmit Holding Register
#define SSC_RSHR (48) // Receive Sync Holding Register
#define SSC_TSHR (52) // Transmit Sync Holding Register
#define SSC_RC0R (56) // Receive Compare 0 Register
#define SSC_RC1R (60) // Receive Compare 1 Register
#define SSC_SR (64) // Status Register
#define SSC_IER (68) // Interrupt Enable Register
#define SSC_IDR (72) // Interrupt Disable Register
#define SSC_IMR (76) // Interrupt Mask Register
#define SSC_RPR (256) // Receive Pointer Register
#define SSC_RCR (260) // Receive Counter Register
#define SSC_TPR (264) // Transmit Pointer Register
#define SSC_TCR (268) // Transmit Counter Register
#define SSC_RNPR (272) // Receive Next Pointer Register
#define SSC_RNCR (276) // Receive Next Counter Register
#define SSC_TNPR (280) // Transmit Next Pointer Register
#define SSC_TNCR (284) // Transmit Next Counter Register
#define SSC_PTCR (288) // PDC Transfer Control Register
#define SSC_PTSR (292) // PDC Transfer Status Register
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
// *** Register offset in AT91S_USART structure ***
#define US_CR ( 0) // Control Register
#define US_MR ( 4) // Mode Register
#define US_IER ( 8) // Interrupt Enable Register
#define US_IDR (12) // Interrupt Disable Register
#define US_IMR (16) // Interrupt Mask Register
#define US_CSR (20) // Channel Status Register
#define US_RHR (24) // Receiver Holding Register
#define US_THR (28) // Transmitter Holding Register
#define US_BRGR (32) // Baud Rate Generator Register
#define US_RTOR (36) // Receiver Time-out Register
#define US_TTGR (40) // Transmitter Time-guard Register
#define US_FIDI (64) // FI_DI_Ratio Register
#define US_NER (68) // Nb Errors Register
#define US_XXR (72) // XON_XOFF Register
#define US_IF (76) // IRDA_FILTER Register
#define US_RPR (256) // Receive Pointer Register
#define US_RCR (260) // Receive Counter Register
#define US_TPR (264) // Transmit Pointer Register
#define US_TCR (268) // Transmit Counter Register
#define US_RNPR (272) // Receive Next Pointer Register
#define US_RNCR (276) // Receive Next Counter Register
#define US_TNPR (280) // Transmit Next Pointer Register
#define US_TNCR (284) // Transmit Next Counter Register
#define US_PTCR (288) // PDC Transfer Control Register
#define US_PTSR (292) // PDC Transfer Status Register
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits
#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
// *** Register offset in AT91S_TWI structure ***
#define TWI_CR ( 0) // Control Register
#define TWI_MMR ( 4) // Master Mode Register
#define TWI_SMR ( 8) // Slave Mode Register
#define TWI_IADR (12) // Internal Address Register
#define TWI_CWGR (16) // Clock Waveform Generator Register
#define TWI_SR (32) // Status Register
#define TWI_IER (36) // Interrupt Enable Register
#define TWI_IDR (40) // Interrupt Disable Register
#define TWI_IMR (44) // Interrupt Mask Register
#define TWI_RHR (48) // Receive Holding Register
#define TWI_THR (52) // Transmit Holding Register
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled
#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled
#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read
#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access
#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access
#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_TC structure ***
#define TC_CCR ( 0) // Channel Control Register
#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
#define TC_CV (16) // Counter Value
#define TC_RA (20) // Register A
#define TC_RB (24) // Register B
#define TC_RC (28) // Register C
#define TC_SR (32) // Status Register
#define TC_IER (36) // Interrupt Enable Register
#define TC_IDR (40) // Interrupt Disable Register
#define TC_IMR (44) // Interrupt Mask Register
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE (0x1 << 15) // (TC)
#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger
#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
// *** Register offset in AT91S_TCB structure ***
#define TCB_TC0 ( 0) // TC Channel 0
#define TCB_TC1 (64) // TC Channel 1
#define TCB_TC2 (128) // TC Channel 2
#define TCB_BCR (192) // TC Block Control Register
#define TCB_BMR (196) // TC Block Mode Register
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR PWMC Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_PWMC_CH structure ***
#define PWMC_CMR ( 0) // Channel Mode Register
#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
#define PWMC_CPRDR ( 8) // Channel Period Register
#define PWMC_CCNTR (12) // Channel Counter Register
#define PWMC_CUPDR (16) // Channel Update Register
#define PWMC_Reserved (20) // Reserved
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PWMC structure ***
#define PWMC_MR ( 0) // PWMC Mode Register
#define PWMC_ENA ( 4) // PWMC Enable Register
#define PWMC_DIS ( 8) // PWMC Disable Register
#define PWMC_SR (12) // PWMC Status Register
#define PWMC_IER (16) // PWMC Interrupt Enable Register
#define PWMC_IDR (20) // PWMC Interrupt Disable Register
#define PWMC_IMR (24) // PWMC Interrupt Mask Register
#define PWMC_ISR (28) // PWMC Interrupt Status Register
#define PWMC_VR (252) // PWMC Version Register
#define PWMC_CH (512) // PWMC Channel 0
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4
#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5
#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6
#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7
// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
// *** Register offset in AT91S_UDP structure ***
#define UDP_NUM ( 0) // Frame Number Register
#define UDP_GLBSTATE ( 4) // Global State Register
#define UDP_FADDR ( 8) // Function Address Register
#define UDP_IER (16) // Interrupt Enable Register
#define UDP_IDR (20) // Interrupt Disable Register
#define UDP_IMR (24) // Interrupt Mask Register
#define UDP_ISR (28) // Interrupt Status Register
#define UDP_ICR (32) // Interrupt Clear Register
#define UDP_RSTEP (40) // Reset Endpoint Register
#define UDP_CSR (48) // Endpoint Control and Status Register
#define UDP_FDR (80) // Endpoint FIFO Data Register
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable
#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt
#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt
#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6
#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
// *****************************************************************************
// ========== Register definition for SYSC peripheral ==========
#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register
#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register
#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
// ========== Register definition for MC peripheral ==========
#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
// ========== Register definition for PDC_SPI peripheral ==========
#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register
// ========== Register definition for SPI peripheral ==========
#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register
#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register
#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register
#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register
#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register
#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register
#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register
#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register
#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
// ========== Register definition for PDC_SSC peripheral ==========
#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
// ========== Register definition for SSC peripheral ==========
#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register
#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register
#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register
#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register
#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
// ========== Register definition for TWI peripheral ==========
#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register
#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
// ========== Register definition for TCB peripheral ==========
#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
// ========== Register definition for PWMC_CH3 peripheral ==========
#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH2 peripheral ==========
#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH1 peripheral ==========
#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH0 peripheral ==========
#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
// ========== Register definition for PWMC peripheral ==========
#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ( 1) // System Peripheral
#define AT91C_ID_PIOA ( 2) // Parallel IO Controller
#define AT91C_ID_3_Reserved ( 3) // Reserved
#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
#define AT91C_ID_US0 ( 6) // USART 0
#define AT91C_ID_US1 ( 7) // USART 1
#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
#define AT91C_ID_TWI ( 9) // Two-Wire Interface
#define AT91C_ID_PWMC (10) // PWM Controller
#define AT91C_ID_UDP (11) // USB Device Port
#define AT91C_ID_TC0 (12) // Timer Counter 0
#define AT91C_ID_TC1 (13) // Timer Counter 1
#define AT91C_ID_TC2 (14) // Timer Counter 2
#define AT91C_ID_15_Reserved (15) // Reserved
#define AT91C_ID_16_Reserved (16) // Reserved
#define AT91C_ID_17_Reserved (17) // Reserved
#define AT91C_ID_18_Reserved (18) // Reserved
#define AT91C_ID_19_Reserved (19) // Reserved
#define AT91C_ID_20_Reserved (20) // Reserved
#define AT91C_ID_21_Reserved (21) // Reserved
#define AT91C_ID_22_Reserved (22) // Reserved
#define AT91C_ID_23_Reserved (23) // Reserved
#define AT91C_ID_24_Reserved (24) // Reserved
#define AT91C_ID_25_Reserved (25) // Reserved
#define AT91C_ID_26_Reserved (26) // Reserved
#define AT91C_ID_27_Reserved (27) // Reserved
#define AT91C_ID_28_Reserved (28) // Reserved
#define AT91C_ID_29_Reserved (29) // Reserved
#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address
#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address
#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address
#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte)
#define AT91C_IFLASH (0x00100000) // Internal ROM base address
#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte)
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h | C | oos | 135,971 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portLONG
#define portBASE_TYPE portLONG
#if( configUSE_16_BIT_TICKS == 1 )
typedef unsigned portSHORT portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned portLONG portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portYIELD() asm ( "SWI 0" )
#define portNOP() asm ( "NOP" )
/*-----------------------------------------------------------*/
/* Critical section handling. */
__arm __interwork void vPortDisableInterruptsFromThumb( void );
__arm __interwork void vPortEnableInterruptsFromThumb( void );
__arm __interwork void vPortEnterCritical( void );
__arm __interwork void vPortExitCritical( void );
#define portDISABLE_INTERRUPTS() __disable_interrupt()
#define portENABLE_INTERRUPTS() __enable_interrupt()
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern void vTaskSwitchContext( void ); \
\
if( xSwitchRequired ) \
{ \
vTaskSwitchContext(); \
} \
}
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/portmacro.h | C | oos | 5,424 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM7X128.h
// Object : AT91SAM7X128 definitions
// Generated : AT91 SW Application Group 05/20/2005 (16:22:23)
//
// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
// ----------------------------------------------------------------------------
// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR ( 0) // Source Mode Register
#define AIC_SVR (128) // Source Vector Register
#define AIC_IVR (256) // IRQ Vector Register
#define AIC_FVR (260) // FIQ Vector Register
#define AIC_ISR (264) // Interrupt Status Register
#define AIC_IPR (268) // Interrupt Pending Register
#define AIC_IMR (272) // Interrupt Mask Register
#define AIC_CISR (276) // Core Interrupt Status Register
#define AIC_IECR (288) // Interrupt Enable Command Register
#define AIC_IDCR (292) // Interrupt Disable Command Register
#define AIC_ICCR (296) // Interrupt Clear Command Register
#define AIC_ISCR (300) // Interrupt Set Command Register
#define AIC_EOICR (304) // End of Interrupt Command Register
#define AIC_SPU (308) // Spurious Vector Register
#define AIC_DCR (312) // Debug Control Register (Protect)
#define AIC_FFER (320) // Fast Forcing Enable Register
#define AIC_FFDR (324) // Fast Forcing Disable Register
#define AIC_FFSR (328) // Fast Forcing Status Register
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
// *** Register offset in AT91S_PDC structure ***
#define PDC_RPR ( 0) // Receive Pointer Register
#define PDC_RCR ( 4) // Receive Counter Register
#define PDC_TPR ( 8) // Transmit Pointer Register
#define PDC_TCR (12) // Transmit Counter Register
#define PDC_RNPR (16) // Receive Next Pointer Register
#define PDC_RNCR (20) // Receive Next Counter Register
#define PDC_TNPR (24) // Transmit Next Pointer Register
#define PDC_TNCR (28) // Transmit Next Counter Register
#define PDC_PTCR (32) // PDC Transfer Control Register
#define PDC_PTSR (36) // PDC Transfer Status Register
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
// *** Register offset in AT91S_DBGU structure ***
#define DBGU_CR ( 0) // Control Register
#define DBGU_MR ( 4) // Mode Register
#define DBGU_IER ( 8) // Interrupt Enable Register
#define DBGU_IDR (12) // Interrupt Disable Register
#define DBGU_IMR (16) // Interrupt Mask Register
#define DBGU_CSR (20) // Channel Status Register
#define DBGU_RHR (24) // Receiver Holding Register
#define DBGU_THR (28) // Transmitter Holding Register
#define DBGU_BRGR (32) // Baud Rate Generator Register
#define DBGU_CIDR (64) // Chip ID Register
#define DBGU_EXID (68) // Chip ID Extension Register
#define DBGU_FNTR (72) // Force NTRST Register
#define DBGU_RPR (256) // Receive Pointer Register
#define DBGU_RCR (260) // Receive Counter Register
#define DBGU_TPR (264) // Transmit Pointer Register
#define DBGU_TCR (268) // Transmit Counter Register
#define DBGU_RNPR (272) // Receive Next Pointer Register
#define DBGU_RNCR (276) // Receive Next Counter Register
#define DBGU_TNPR (280) // Transmit Next Pointer Register
#define DBGU_TNCR (284) // Transmit Next Counter Register
#define DBGU_PTCR (288) // PDC Transfer Control Register
#define DBGU_PTSR (292) // PDC Transfer Status Register
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
// *** Register offset in AT91S_PIO structure ***
#define PIO_PER ( 0) // PIO Enable Register
#define PIO_PDR ( 4) // PIO Disable Register
#define PIO_PSR ( 8) // PIO Status Register
#define PIO_OER (16) // Output Enable Register
#define PIO_ODR (20) // Output Disable Registerr
#define PIO_OSR (24) // Output Status Register
#define PIO_IFER (32) // Input Filter Enable Register
#define PIO_IFDR (36) // Input Filter Disable Register
#define PIO_IFSR (40) // Input Filter Status Register
#define PIO_SODR (48) // Set Output Data Register
#define PIO_CODR (52) // Clear Output Data Register
#define PIO_ODSR (56) // Output Data Status Register
#define PIO_PDSR (60) // Pin Data Status Register
#define PIO_IER (64) // Interrupt Enable Register
#define PIO_IDR (68) // Interrupt Disable Register
#define PIO_IMR (72) // Interrupt Mask Register
#define PIO_ISR (76) // Interrupt Status Register
#define PIO_MDER (80) // Multi-driver Enable Register
#define PIO_MDDR (84) // Multi-driver Disable Register
#define PIO_MDSR (88) // Multi-driver Status Register
#define PIO_PPUDR (96) // Pull-up Disable Register
#define PIO_PPUER (100) // Pull-up Enable Register
#define PIO_PPUSR (104) // Pull-up Status Register
#define PIO_ASR (112) // Select A Register
#define PIO_BSR (116) // Select B Register
#define PIO_ABSR (120) // AB Select Status Register
#define PIO_OWER (160) // Output Write Enable Register
#define PIO_OWDR (164) // Output Write Disable Register
#define PIO_OWSR (168) // Output Write Status Register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
// *** Register offset in AT91S_CKGR structure ***
#define CKGR_MOR ( 0) // Main Oscillator Register
#define CKGR_MCFR ( 4) // Main Clock Frequency Register
#define CKGR_PLLR (12) // PLL Register
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
// *** Register offset in AT91S_PMC structure ***
#define PMC_SCER ( 0) // System Clock Enable Register
#define PMC_SCDR ( 4) // System Clock Disable Register
#define PMC_SCSR ( 8) // System Clock Status Register
#define PMC_PCER (16) // Peripheral Clock Enable Register
#define PMC_PCDR (20) // Peripheral Clock Disable Register
#define PMC_PCSR (24) // Peripheral Clock Status Register
#define PMC_MOR (32) // Main Oscillator Register
#define PMC_MCFR (36) // Main Clock Frequency Register
#define PMC_PLLR (44) // PLL Register
#define PMC_MCKR (48) // Master Clock Register
#define PMC_PCKR (64) // Programmable Clock Register
#define PMC_IER (96) // Interrupt Enable Register
#define PMC_IDR (100) // Interrupt Disable Register
#define PMC_SR (104) // Status Register
#define PMC_IMR (108) // Interrupt Mask Register
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RSTC structure ***
#define RSTC_RCR ( 0) // Reset Control Register
#define RSTC_RSR ( 4) // Reset Status Register
#define RSTC_RMR ( 8) // Reset Mode Register
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RTTC structure ***
#define RTTC_RTMR ( 0) // Real-time Mode Register
#define RTTC_RTAR ( 4) // Real-time Alarm Register
#define RTTC_RTVR ( 8) // Real-time Value Register
#define RTTC_RTSR (12) // Real-time Status Register
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PITC structure ***
#define PITC_PIMR ( 0) // Period Interval Mode Register
#define PITC_PISR ( 4) // Period Interval Status Register
#define PITC_PIVR ( 8) // Period Interval Value Register
#define PITC_PIIR (12) // Period Interval Image Register
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_WDTC structure ***
#define WDTC_WDCR ( 0) // Watchdog Control Register
#define WDTC_WDMR ( 4) // Watchdog Mode Register
#define WDTC_WDSR ( 8) // Watchdog Status Register
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_VREG structure ***
#define VREG_MR ( 0) // Voltage Regulator Mode Register
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_MC structure ***
#define MC_RCR ( 0) // MC Remap Control Register
#define MC_ASR ( 4) // MC Abort Status Register
#define MC_AASR ( 8) // MC Abort Address Status Register
#define MC_FMR (96) // MC Flash Mode Register
#define MC_FCR (100) // MC Flash Command Register
#define MC_FSR (104) // MC Flash Status Register
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
// *** Register offset in AT91S_SPI structure ***
#define SPI_CR ( 0) // Control Register
#define SPI_MR ( 4) // Mode Register
#define SPI_RDR ( 8) // Receive Data Register
#define SPI_TDR (12) // Transmit Data Register
#define SPI_SR (16) // Status Register
#define SPI_IER (20) // Interrupt Enable Register
#define SPI_IDR (24) // Interrupt Disable Register
#define SPI_IMR (28) // Interrupt Mask Register
#define SPI_CSR (48) // Chip Select Register
#define SPI_RPR (256) // Receive Pointer Register
#define SPI_RCR (260) // Receive Counter Register
#define SPI_TPR (264) // Transmit Pointer Register
#define SPI_TCR (268) // Transmit Counter Register
#define SPI_RNPR (272) // Receive Next Pointer Register
#define SPI_RNCR (276) // Receive Next Counter Register
#define SPI_TNPR (280) // Transmit Next Pointer Register
#define SPI_TNCR (284) // Transmit Next Counter Register
#define SPI_PTCR (288) // PDC Transfer Control Register
#define SPI_PTSR (292) // PDC Transfer Status Register
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
// *** Register offset in AT91S_USART structure ***
#define US_CR ( 0) // Control Register
#define US_MR ( 4) // Mode Register
#define US_IER ( 8) // Interrupt Enable Register
#define US_IDR (12) // Interrupt Disable Register
#define US_IMR (16) // Interrupt Mask Register
#define US_CSR (20) // Channel Status Register
#define US_RHR (24) // Receiver Holding Register
#define US_THR (28) // Transmitter Holding Register
#define US_BRGR (32) // Baud Rate Generator Register
#define US_RTOR (36) // Receiver Time-out Register
#define US_TTGR (40) // Transmitter Time-guard Register
#define US_FIDI (64) // FI_DI_Ratio Register
#define US_NER (68) // Nb Errors Register
#define US_IF (76) // IRDA_FILTER Register
#define US_RPR (256) // Receive Pointer Register
#define US_RCR (260) // Receive Counter Register
#define US_TPR (264) // Transmit Pointer Register
#define US_TCR (268) // Transmit Counter Register
#define US_RNPR (272) // Receive Next Pointer Register
#define US_RNCR (276) // Receive Next Counter Register
#define US_TNPR (280) // Transmit Next Pointer Register
#define US_TNCR (284) // Transmit Next Counter Register
#define US_PTCR (288) // PDC Transfer Control Register
#define US_PTSR (292) // PDC Transfer Status Register
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_SSC structure ***
#define SSC_CR ( 0) // Control Register
#define SSC_CMR ( 4) // Clock Mode Register
#define SSC_RCMR (16) // Receive Clock ModeRegister
#define SSC_RFMR (20) // Receive Frame Mode Register
#define SSC_TCMR (24) // Transmit Clock Mode Register
#define SSC_TFMR (28) // Transmit Frame Mode Register
#define SSC_RHR (32) // Receive Holding Register
#define SSC_THR (36) // Transmit Holding Register
#define SSC_RSHR (48) // Receive Sync Holding Register
#define SSC_TSHR (52) // Transmit Sync Holding Register
#define SSC_SR (64) // Status Register
#define SSC_IER (68) // Interrupt Enable Register
#define SSC_IDR (72) // Interrupt Disable Register
#define SSC_IMR (76) // Interrupt Mask Register
#define SSC_RPR (256) // Receive Pointer Register
#define SSC_RCR (260) // Receive Counter Register
#define SSC_TPR (264) // Transmit Pointer Register
#define SSC_TCR (268) // Transmit Counter Register
#define SSC_RNPR (272) // Receive Next Pointer Register
#define SSC_RNCR (276) // Receive Next Counter Register
#define SSC_TNPR (280) // Transmit Next Pointer Register
#define SSC_TNCR (284) // Transmit Next Counter Register
#define SSC_PTCR (288) // PDC Transfer Control Register
#define SSC_PTSR (292) // PDC Transfer Status Register
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
// *** Register offset in AT91S_TWI structure ***
#define TWI_CR ( 0) // Control Register
#define TWI_MMR ( 4) // Master Mode Register
#define TWI_IADR (12) // Internal Address Register
#define TWI_CWGR (16) // Clock Waveform Generator Register
#define TWI_SR (32) // Status Register
#define TWI_IER (36) // Interrupt Enable Register
#define TWI_IDR (40) // Interrupt Disable Register
#define TWI_IMR (44) // Interrupt Mask Register
#define TWI_RHR (48) // Receive Holding Register
#define TWI_THR (52) // Transmit Holding Register
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR PWMC Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_PWMC_CH structure ***
#define PWMC_CMR ( 0) // Channel Mode Register
#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
#define PWMC_CPRDR ( 8) // Channel Period Register
#define PWMC_CCNTR (12) // Channel Counter Register
#define PWMC_CUPDR (16) // Channel Update Register
#define PWMC_Reserved (20) // Reserved
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PWMC structure ***
#define PWMC_MR ( 0) // PWMC Mode Register
#define PWMC_ENA ( 4) // PWMC Enable Register
#define PWMC_DIS ( 8) // PWMC Disable Register
#define PWMC_SR (12) // PWMC Status Register
#define PWMC_IER (16) // PWMC Interrupt Enable Register
#define PWMC_IDR (20) // PWMC Interrupt Disable Register
#define PWMC_IMR (24) // PWMC Interrupt Mask Register
#define PWMC_ISR (28) // PWMC Interrupt Status Register
#define PWMC_VR (252) // PWMC Version Register
#define PWMC_CH (512) // PWMC Channel
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
// *** Register offset in AT91S_UDP structure ***
#define UDP_NUM ( 0) // Frame Number Register
#define UDP_GLBSTATE ( 4) // Global State Register
#define UDP_FADDR ( 8) // Function Address Register
#define UDP_IER (16) // Interrupt Enable Register
#define UDP_IDR (20) // Interrupt Disable Register
#define UDP_IMR (24) // Interrupt Mask Register
#define UDP_ISR (28) // Interrupt Status Register
#define UDP_ICR (32) // Interrupt Clear Register
#define UDP_RSTEP (40) // Reset Endpoint Register
#define UDP_CSR (48) // Endpoint Control and Status Register
#define UDP_FDR (80) // Endpoint FIFO Data Register
#define UDP_TXVC (116) // Transceiver Control Register
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_TC structure ***
#define TC_CCR ( 0) // Channel Control Register
#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
#define TC_CV (16) // Counter Value
#define TC_RA (20) // Register A
#define TC_RB (24) // Register B
#define TC_RC (28) // Register C
#define TC_SR (32) // Status Register
#define TC_IER (36) // Interrupt Enable Register
#define TC_IDR (40) // Interrupt Disable Register
#define TC_IMR (44) // Interrupt Mask Register
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE (0x1 << 15) // (TC)
#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
// *** Register offset in AT91S_TCB structure ***
#define TCB_TC0 ( 0) // TC Channel 0
#define TCB_TC1 (64) // TC Channel 1
#define TCB_TC2 (128) // TC Channel 2
#define TCB_BCR (192) // TC Block Control Register
#define TCB_BMR (196) // TC Block Mode Register
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
// *****************************************************************************
// *** Register offset in AT91S_CAN_MB structure ***
#define CAN_MB_MMR ( 0) // MailBox Mode Register
#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register
#define CAN_MB_MID ( 8) // MailBox ID Register
#define CAN_MB_MFID (12) // MailBox Family ID Register
#define CAN_MB_MSR (16) // MailBox Status Register
#define CAN_MB_MDL (20) // MailBox Data Low Register
#define CAN_MB_MDH (24) // MailBox Data High Register
#define CAN_MB_MCR (28) // MailBox Control Register
// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network Interface
// *****************************************************************************
// *** Register offset in AT91S_CAN structure ***
#define CAN_MR ( 0) // Mode Register
#define CAN_IER ( 4) // Interrupt Enable Register
#define CAN_IDR ( 8) // Interrupt Disable Register
#define CAN_IMR (12) // Interrupt Mask Register
#define CAN_SR (16) // Status Register
#define CAN_BR (20) // Baudrate Register
#define CAN_TIM (24) // Timer Register
#define CAN_TIMESTP (28) // Time Stamp Register
#define CAN_ECR (32) // Error Counter Register
#define CAN_TCR (36) // Transfer Command Register
#define CAN_ACR (40) // Abort Command Register
#define CAN_VR (252) // Version Register
#define CAN_MB0 (512) // CAN Mailbox 0
#define CAN_MB1 (544) // CAN Mailbox 1
#define CAN_MB2 (576) // CAN Mailbox 2
#define CAN_MB3 (608) // CAN Mailbox 3
#define CAN_MB4 (640) // CAN Mailbox 4
#define CAN_MB5 (672) // CAN Mailbox 5
#define CAN_MB6 (704) // CAN Mailbox 6
#define CAN_MB7 (736) // CAN Mailbox 7
#define CAN_MB8 (768) // CAN Mailbox 8
#define CAN_MB9 (800) // CAN Mailbox 9
#define CAN_MB10 (832) // CAN Mailbox 10
#define CAN_MB11 (864) // CAN Mailbox 11
#define CAN_MB12 (896) // CAN Mailbox 12
#define CAN_MB13 (928) // CAN Mailbox 13
#define CAN_MB14 (960) // CAN Mailbox 14
#define CAN_MB15 (992) // CAN Mailbox 15
// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
// *****************************************************************************
// *** Register offset in AT91S_EMAC structure ***
#define EMAC_NCR ( 0) // Network Control Register
#define EMAC_NCFGR ( 4) // Network Configuration Register
#define EMAC_NSR ( 8) // Network Status Register
#define EMAC_TSR (20) // Transmit Status Register
#define EMAC_RBQP (24) // Receive Buffer Queue Pointer
#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer
#define EMAC_RSR (32) // Receive Status Register
#define EMAC_ISR (36) // Interrupt Status Register
#define EMAC_IER (40) // Interrupt Enable Register
#define EMAC_IDR (44) // Interrupt Disable Register
#define EMAC_IMR (48) // Interrupt Mask Register
#define EMAC_MAN (52) // PHY Maintenance Register
#define EMAC_PTR (56) // Pause Time Register
#define EMAC_PFR (60) // Pause Frames received Register
#define EMAC_FTO (64) // Frames Transmitted OK Register
#define EMAC_SCF (68) // Single Collision Frame Register
#define EMAC_MCF (72) // Multiple Collision Frame Register
#define EMAC_FRO (76) // Frames Received OK Register
#define EMAC_FCSE (80) // Frame Check Sequence Error Register
#define EMAC_ALE (84) // Alignment Error Register
#define EMAC_DTF (88) // Deferred Transmission Frame Register
#define EMAC_LCOL (92) // Late Collision Register
#define EMAC_ECOL (96) // Excessive Collision Register
#define EMAC_TUND (100) // Transmit Underrun Error Register
#define EMAC_CSE (104) // Carrier Sense Error Register
#define EMAC_RRE (108) // Receive Ressource Error Register
#define EMAC_ROV (112) // Receive Overrun Errors Register
#define EMAC_RSE (116) // Receive Symbol Errors Register
#define EMAC_ELE (120) // Excessive Length Errors Register
#define EMAC_RJA (124) // Receive Jabbers Register
#define EMAC_USF (128) // Undersize Frames Register
#define EMAC_STE (132) // SQE Test Error Register
#define EMAC_RLE (136) // Receive Length Field Mismatch Register
#define EMAC_TPF (140) // Transmitted Pause Frames Register
#define EMAC_HRB (144) // Hash Address Bottom[31:0]
#define EMAC_HRT (148) // Hash Address Top[63:32]
#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes
#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes
#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes
#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes
#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes
#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes
#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes
#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes
#define EMAC_TID (184) // Type ID Checking Register
#define EMAC_TPQ (188) // Transmit Pause Quantum Register
#define EMAC_USRIO (192) // USER Input/Output Register
#define EMAC_WOL (196) // Wake On LAN Register
#define EMAC_REV (252) // Revision Register
// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
// *** Register offset in AT91S_ADC structure ***
#define ADC_CR ( 0) // ADC Control Register
#define ADC_MR ( 4) // ADC Mode Register
#define ADC_CHER (16) // ADC Channel Enable Register
#define ADC_CHDR (20) // ADC Channel Disable Register
#define ADC_CHSR (24) // ADC Channel Status Register
#define ADC_SR (28) // ADC Status Register
#define ADC_LCDR (32) // ADC Last Converted Data Register
#define ADC_IER (36) // ADC Interrupt Enable Register
#define ADC_IDR (40) // ADC Interrupt Disable Register
#define ADC_IMR (44) // ADC Interrupt Mask Register
#define ADC_CDR0 (48) // ADC Channel Data Register 0
#define ADC_CDR1 (52) // ADC Channel Data Register 1
#define ADC_CDR2 (56) // ADC Channel Data Register 2
#define ADC_CDR3 (60) // ADC Channel Data Register 3
#define ADC_CDR4 (64) // ADC Channel Data Register 4
#define ADC_CDR5 (68) // ADC Channel Data Register 5
#define ADC_CDR6 (72) // ADC Channel Data Register 6
#define ADC_CDR7 (76) // ADC Channel Data Register 7
#define ADC_RPR (256) // Receive Pointer Register
#define ADC_RCR (260) // Receive Counter Register
#define ADC_TPR (264) // Transmit Pointer Register
#define ADC_TCR (268) // Transmit Counter Register
#define ADC_RNPR (272) // Receive Next Pointer Register
#define ADC_RNCR (276) // Receive Next Counter Register
#define ADC_TNPR (280) // Transmit Next Pointer Register
#define ADC_TNCR (284) // Transmit Next Counter Register
#define ADC_PTCR (288) // PDC Transfer Control Register
#define ADC_PTSR (292) // PDC Transfer Status Register
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
// *****************************************************************************
// *** Register offset in AT91S_AES structure ***
#define AES_CR ( 0) // Control Register
#define AES_MR ( 4) // Mode Register
#define AES_IER (16) // Interrupt Enable Register
#define AES_IDR (20) // Interrupt Disable Register
#define AES_IMR (24) // Interrupt Mask Register
#define AES_ISR (28) // Interrupt Status Register
#define AES_KEYWxR (32) // Key Word x Register
#define AES_IDATAxR (64) // Input Data x Register
#define AES_ODATAxR (80) // Output Data x Register
#define AES_IVxR (96) // Initialization Vector x Register
#define AES_VR (252) // AES Version Register
#define AES_RPR (256) // Receive Pointer Register
#define AES_RCR (260) // Receive Counter Register
#define AES_TPR (264) // Transmit Pointer Register
#define AES_TCR (268) // Transmit Counter Register
#define AES_RNPR (272) // Receive Next Pointer Register
#define AES_RNCR (276) // Receive Next Counter Register
#define AES_TNPR (280) // Transmit Next Pointer Register
#define AES_TNCR (284) // Transmit Next Counter Register
#define AES_PTCR (288) // PDC Transfer Control Register
#define AES_PTSR (292) // PDC Transfer Status Register
// -------- AES_CR : (AES Offset: 0x0) Control Register --------
#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing
#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset
#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading
// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode
#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay
#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode
#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet).
#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode
#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode.
#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode.
#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode.
#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode
#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size
#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit.
#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit.
#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit.
#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit.
#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit.
#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key
#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type
#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY
#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End
#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End
#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full
#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty
#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection
// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status
#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access.
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
// *****************************************************************************
// *** Register offset in AT91S_TDES structure ***
#define TDES_CR ( 0) // Control Register
#define TDES_MR ( 4) // Mode Register
#define TDES_IER (16) // Interrupt Enable Register
#define TDES_IDR (20) // Interrupt Disable Register
#define TDES_IMR (24) // Interrupt Mask Register
#define TDES_ISR (28) // Interrupt Status Register
#define TDES_KEY1WxR (32) // Key 1 Word x Register
#define TDES_KEY2WxR (40) // Key 2 Word x Register
#define TDES_KEY3WxR (48) // Key 3 Word x Register
#define TDES_IDATAxR (64) // Input Data x Register
#define TDES_ODATAxR (80) // Output Data x Register
#define TDES_IVxR (96) // Initialization Vector x Register
#define TDES_VR (252) // TDES Version Register
#define TDES_RPR (256) // Receive Pointer Register
#define TDES_RCR (260) // Receive Counter Register
#define TDES_TPR (264) // Transmit Pointer Register
#define TDES_TCR (268) // Transmit Counter Register
#define TDES_RNPR (272) // Receive Next Pointer Register
#define TDES_RNCR (276) // Receive Next Counter Register
#define TDES_TNPR (280) // Transmit Next Pointer Register
#define TDES_TNCR (284) // Transmit Next Counter Register
#define TDES_PTCR (288) // PDC Transfer Control Register
#define TDES_PTSR (292) // PDC Transfer Status Register
// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing
#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset
// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode
#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode
#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode
#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode
#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet).
#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode
#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode.
#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode
#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size
#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit.
#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit.
#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit.
#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit.
// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY
#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End
#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End
#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full
#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty
#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection
// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status
#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access.
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
// *****************************************************************************
// ========== Register definition for SYS peripheral ==========
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register
#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register
#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register
#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register
#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register
#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register
#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register
#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register
#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register
#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register
#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register
#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr
#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register
#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register
#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register
#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register
#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register
#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register
#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
// ========== Register definition for VREG peripheral ==========
#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
// ========== Register definition for MC peripheral ==========
#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
// ========== Register definition for PDC_SPI1 peripheral ==========
#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
// ========== Register definition for SPI1 peripheral ==========
#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register
#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register
#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register
#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register
#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register
#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register
#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register
#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register
#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register
// ========== Register definition for PDC_SPI0 peripheral ==========
#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
// ========== Register definition for SPI0 peripheral ==========
#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register
#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register
#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register
#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register
#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register
#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register
#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register
#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register
#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
// ========== Register definition for PDC_SSC peripheral ==========
#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
// ========== Register definition for SSC peripheral ==========
#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
// ========== Register definition for TWI peripheral ==========
#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
// ========== Register definition for PWMC_CH3 peripheral ==========
#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
// ========== Register definition for PWMC_CH2 peripheral ==========
#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH1 peripheral ==========
#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
// ========== Register definition for PWMC_CH0 peripheral ==========
#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
// ========== Register definition for PWMC peripheral ==========
#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register
#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TCB peripheral ==========
#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
// ========== Register definition for CAN_MB0 peripheral ==========
#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register
#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register
#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register
#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
// ========== Register definition for CAN_MB1 peripheral ==========
#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register
#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register
#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register
#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
// ========== Register definition for CAN_MB2 peripheral ==========
#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register
#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register
#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register
// ========== Register definition for CAN_MB3 peripheral ==========
#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register
#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register
#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register
#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
// ========== Register definition for CAN_MB4 peripheral ==========
#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register
#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register
#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register
#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB5 peripheral ==========
#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB6 peripheral ==========
#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
// ========== Register definition for CAN_MB7 peripheral ==========
#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
// ========== Register definition for CAN peripheral ==========
#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register
#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register
#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register
#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register
#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register
#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register
#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register
#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register
#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register
#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register
#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register
#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register
// ========== Register definition for EMAC peripheral ==========
#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register
#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register
#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register
#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register
#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register
#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register
#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register
#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register
#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register
#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register
#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register
#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register
#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register
#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register
#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register
#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register
#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register
#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register
#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register
#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register
#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register
#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register
#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register
#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register
#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register
#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
// ========== Register definition for PDC_AES peripheral ==========
#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register
#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register
#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register
#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
// ========== Register definition for AES peripheral ==========
#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register
#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register
#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register
#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register
#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register
#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register
#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register
#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register
#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register
#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register
#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register
// ========== Register definition for PDC_TDES peripheral ==========
#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register
#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
// ========== Register definition for TDES peripheral ==========
#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register
#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register
#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register
#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register
#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register
#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register
#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register
#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register
#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register
#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register
#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register
#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register
#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave
#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave
#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock
#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock
#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave
#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave
#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ( 1) // System Peripheral
#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
#define AT91C_ID_US0 ( 6) // USART 0
#define AT91C_ID_US1 ( 7) // USART 1
#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
#define AT91C_ID_TWI ( 9) // Two-Wire Interface
#define AT91C_ID_PWMC (10) // PWM Controller
#define AT91C_ID_UDP (11) // USB Device Port
#define AT91C_ID_TC0 (12) // Timer Counter 0
#define AT91C_ID_TC1 (13) // Timer Counter 1
#define AT91C_ID_TC2 (14) // Timer Counter 2
#define AT91C_ID_CAN (15) // Control Area Network Controller
#define AT91C_ID_EMAC (16) // Ethernet MAC
#define AT91C_ID_ADC (17) // Analog-to-Digital Converter
#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit
#define AT91C_ID_TDES (19) // Triple Data Encryption Standard
#define AT91C_ID_20_Reserved (20) // Reserved
#define AT91C_ID_21_Reserved (21) // Reserved
#define AT91C_ID_22_Reserved (22) // Reserved
#define AT91C_ID_23_Reserved (23) // Reserved
#define AT91C_ID_24_Reserved (24) // Reserved
#define AT91C_ID_25_Reserved (25) // Reserved
#define AT91C_ID_26_Reserved (26) // Reserved
#define AT91C_ID_27_Reserved (27) // Reserved
#define AT91C_ID_28_Reserved (28) // Reserved
#define AT91C_ID_29_Reserved (29) // Reserved
#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address
#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address
#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address
#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address
#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address
#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address
#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address
#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address
#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address
#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address
#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address
#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address
#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address
#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address
#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address
#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address
#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address
#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address
#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address
#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address
#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte)
#define AT91C_IFLASH (0x00100000) // Internal ROM base address
#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte)
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h | C | oos | 186,248 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM7X256.h
// Object : AT91SAM7X256 definitions
// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
//
// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM7X256_H
#define AT91SAM7X256_H
typedef volatile unsigned int AT91_REG;// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
typedef struct _AT91S_SYS {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved2[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved3[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved4[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved5[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved6[1]; //
AT91_REG PIOA_OER; // Output Enable Register
AT91_REG PIOA_ODR; // Output Disable Registerr
AT91_REG PIOA_OSR; // Output Status Register
AT91_REG Reserved7[1]; //
AT91_REG PIOA_IFER; // Input Filter Enable Register
AT91_REG PIOA_IFDR; // Input Filter Disable Register
AT91_REG PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved8[1]; //
AT91_REG PIOA_SODR; // Set Output Data Register
AT91_REG PIOA_CODR; // Clear Output Data Register
AT91_REG PIOA_ODSR; // Output Data Status Register
AT91_REG PIOA_PDSR; // Pin Data Status Register
AT91_REG PIOA_IER; // Interrupt Enable Register
AT91_REG PIOA_IDR; // Interrupt Disable Register
AT91_REG PIOA_IMR; // Interrupt Mask Register
AT91_REG PIOA_ISR; // Interrupt Status Register
AT91_REG PIOA_MDER; // Multi-driver Enable Register
AT91_REG PIOA_MDDR; // Multi-driver Disable Register
AT91_REG PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved9[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved10[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved11[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved12[85]; //
AT91_REG PIOB_PER; // PIO Enable Register
AT91_REG PIOB_PDR; // PIO Disable Register
AT91_REG PIOB_PSR; // PIO Status Register
AT91_REG Reserved13[1]; //
AT91_REG PIOB_OER; // Output Enable Register
AT91_REG PIOB_ODR; // Output Disable Registerr
AT91_REG PIOB_OSR; // Output Status Register
AT91_REG Reserved14[1]; //
AT91_REG PIOB_IFER; // Input Filter Enable Register
AT91_REG PIOB_IFDR; // Input Filter Disable Register
AT91_REG PIOB_IFSR; // Input Filter Status Register
AT91_REG Reserved15[1]; //
AT91_REG PIOB_SODR; // Set Output Data Register
AT91_REG PIOB_CODR; // Clear Output Data Register
AT91_REG PIOB_ODSR; // Output Data Status Register
AT91_REG PIOB_PDSR; // Pin Data Status Register
AT91_REG PIOB_IER; // Interrupt Enable Register
AT91_REG PIOB_IDR; // Interrupt Disable Register
AT91_REG PIOB_IMR; // Interrupt Mask Register
AT91_REG PIOB_ISR; // Interrupt Status Register
AT91_REG PIOB_MDER; // Multi-driver Enable Register
AT91_REG PIOB_MDDR; // Multi-driver Disable Register
AT91_REG PIOB_MDSR; // Multi-driver Status Register
AT91_REG Reserved16[1]; //
AT91_REG PIOB_PPUDR; // Pull-up Disable Register
AT91_REG PIOB_PPUER; // Pull-up Enable Register
AT91_REG PIOB_PPUSR; // Pull-up Status Register
AT91_REG Reserved17[1]; //
AT91_REG PIOB_ASR; // Select A Register
AT91_REG PIOB_BSR; // Select B Register
AT91_REG PIOB_ABSR; // AB Select Status Register
AT91_REG Reserved18[9]; //
AT91_REG PIOB_OWER; // Output Write Enable Register
AT91_REG PIOB_OWDR; // Output Write Disable Register
AT91_REG PIOB_OWSR; // Output Write Status Register
AT91_REG Reserved19[341]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved20[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved21[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved22[1]; //
AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved23[3]; //
AT91_REG PMC_PCKR[4]; // Programmable Clock Register
AT91_REG Reserved24[4]; //
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved25[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved26[5]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved27[5]; //
AT91_REG VREG_MR; // Voltage Regulator Mode Register
} AT91S_SYS, *AT91PS_SYS;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG Reserved0[1]; //
AT91_REG CKGR_PLLR; // PLL Register
} AT91S_CKGR, *AT91PS_CKGR;
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved2[1]; //
AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved3[3]; //
AT91_REG PMC_PCKR[4]; // Programmable Clock Register
AT91_REG Reserved4[4]; //
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
// *****************************************************************************
typedef struct _AT91S_VREG {
AT91_REG VREG_MR; // Voltage Regulator Mode Register
} AT91S_VREG, *AT91PS_VREG;
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved0[21]; //
AT91_REG MC_FMR; // MC Flash Mode Register
AT91_REG MC_FCR; // MC Flash Command Register
AT91_REG MC_FSR; // MC Flash Status Register
} AT91S_MC, *AT91PS_MC;
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[5]; //
AT91_REG US_FIDI; // FI_DI_Ratio Register
AT91_REG US_NER; // Nb Errors Register
AT91_REG Reserved1[1]; //
AT91_REG US_IF; // IRDA_FILTER Register
AT91_REG Reserved2[44]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
AT91_REG US_RNPR; // Receive Next Pointer Register
AT91_REG US_RNCR; // Receive Next Counter Register
AT91_REG US_TNPR; // Transmit Next Pointer Register
AT91_REG US_TNCR; // Transmit Next Counter Register
AT91_REG US_PTCR; // PDC Transfer Control Register
AT91_REG US_PTSR; // PDC Transfer Status Register
} AT91S_USART, *AT91PS_USART;
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
typedef struct _AT91S_SSC {
AT91_REG SSC_CR; // Control Register
AT91_REG SSC_CMR; // Clock Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SSC_RCMR; // Receive Clock ModeRegister
AT91_REG SSC_RFMR; // Receive Frame Mode Register
AT91_REG SSC_TCMR; // Transmit Clock Mode Register
AT91_REG SSC_TFMR; // Transmit Frame Mode Register
AT91_REG SSC_RHR; // Receive Holding Register
AT91_REG SSC_THR; // Transmit Holding Register
AT91_REG Reserved1[2]; //
AT91_REG SSC_RSHR; // Receive Sync Holding Register
AT91_REG SSC_TSHR; // Transmit Sync Holding Register
AT91_REG Reserved2[2]; //
AT91_REG SSC_SR; // Status Register
AT91_REG SSC_IER; // Interrupt Enable Register
AT91_REG SSC_IDR; // Interrupt Disable Register
AT91_REG SSC_IMR; // Interrupt Mask Register
AT91_REG Reserved3[44]; //
AT91_REG SSC_RPR; // Receive Pointer Register
AT91_REG SSC_RCR; // Receive Counter Register
AT91_REG SSC_TPR; // Transmit Pointer Register
AT91_REG SSC_TCR; // Transmit Counter Register
AT91_REG SSC_RNPR; // Receive Next Pointer Register
AT91_REG SSC_RNCR; // Receive Next Counter Register
AT91_REG SSC_TNPR; // Transmit Next Pointer Register
AT91_REG SSC_TNCR; // Transmit Next Counter Register
AT91_REG SSC_PTCR; // PDC Transfer Control Register
AT91_REG SSC_PTSR; // PDC Transfer Status Register
} AT91S_SSC, *AT91PS_SSC;
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; // Control Register
AT91_REG TWI_MMR; // Master Mode Register
AT91_REG Reserved0[1]; //
AT91_REG TWI_IADR; // Internal Address Register
AT91_REG TWI_CWGR; // Clock Waveform Generator Register
AT91_REG Reserved1[3]; //
AT91_REG TWI_SR; // Status Register
AT91_REG TWI_IER; // Interrupt Enable Register
AT91_REG TWI_IDR; // Interrupt Disable Register
AT91_REG TWI_IMR; // Interrupt Mask Register
AT91_REG TWI_RHR; // Receive Holding Register
AT91_REG TWI_THR; // Transmit Holding Register
} AT91S_TWI, *AT91PS_TWI;
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR PWMC Channel Interface
// *****************************************************************************
typedef struct _AT91S_PWMC_CH {
AT91_REG PWMC_CMR; // Channel Mode Register
AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
AT91_REG PWMC_CPRDR; // Channel Period Register
AT91_REG PWMC_CCNTR; // Channel Counter Register
AT91_REG PWMC_CUPDR; // Channel Update Register
AT91_REG PWMC_Reserved[3]; // Reserved
} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
// *****************************************************************************
typedef struct _AT91S_PWMC {
AT91_REG PWMC_MR; // PWMC Mode Register
AT91_REG PWMC_ENA; // PWMC Enable Register
AT91_REG PWMC_DIS; // PWMC Disable Register
AT91_REG PWMC_SR; // PWMC Status Register
AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
AT91_REG Reserved0[55]; //
AT91_REG PWMC_VR; // PWMC Version Register
AT91_REG Reserved1[64]; //
AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
} AT91S_PWMC, *AT91PS_PWMC;
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
typedef struct _AT91S_UDP {
AT91_REG UDP_NUM; // Frame Number Register
AT91_REG UDP_GLBSTATE; // Global State Register
AT91_REG UDP_FADDR; // Function Address Register
AT91_REG Reserved0[1]; //
AT91_REG UDP_IER; // Interrupt Enable Register
AT91_REG UDP_IDR; // Interrupt Disable Register
AT91_REG UDP_IMR; // Interrupt Mask Register
AT91_REG UDP_ISR; // Interrupt Status Register
AT91_REG UDP_ICR; // Interrupt Clear Register
AT91_REG Reserved1[1]; //
AT91_REG UDP_RSTEP; // Reset Endpoint Register
AT91_REG Reserved2[1]; //
AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
AT91_REG Reserved3[2]; //
AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
AT91_REG Reserved4[3]; //
AT91_REG UDP_TXVC; // Transceiver Control Register
} AT91S_UDP, *AT91PS_UDP;
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
// *****************************************************************************
typedef struct _AT91S_CAN_MB {
AT91_REG CAN_MB_MMR; // MailBox Mode Register
AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
AT91_REG CAN_MB_MID; // MailBox ID Register
AT91_REG CAN_MB_MFID; // MailBox Family ID Register
AT91_REG CAN_MB_MSR; // MailBox Status Register
AT91_REG CAN_MB_MDL; // MailBox Data Low Register
AT91_REG CAN_MB_MDH; // MailBox Data High Register
AT91_REG CAN_MB_MCR; // MailBox Control Register
} AT91S_CAN_MB, *AT91PS_CAN_MB;
// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network Interface
// *****************************************************************************
typedef struct _AT91S_CAN {
AT91_REG CAN_MR; // Mode Register
AT91_REG CAN_IER; // Interrupt Enable Register
AT91_REG CAN_IDR; // Interrupt Disable Register
AT91_REG CAN_IMR; // Interrupt Mask Register
AT91_REG CAN_SR; // Status Register
AT91_REG CAN_BR; // Baudrate Register
AT91_REG CAN_TIM; // Timer Register
AT91_REG CAN_TIMESTP; // Time Stamp Register
AT91_REG CAN_ECR; // Error Counter Register
AT91_REG CAN_TCR; // Transfer Command Register
AT91_REG CAN_ACR; // Abort Command Register
AT91_REG Reserved0[52]; //
AT91_REG CAN_VR; // Version Register
AT91_REG Reserved1[64]; //
AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
} AT91S_CAN, *AT91PS_CAN;
// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
// *****************************************************************************
typedef struct _AT91S_EMAC {
AT91_REG EMAC_NCR; // Network Control Register
AT91_REG EMAC_NCFGR; // Network Configuration Register
AT91_REG EMAC_NSR; // Network Status Register
AT91_REG Reserved0[2]; //
AT91_REG EMAC_TSR; // Transmit Status Register
AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
AT91_REG EMAC_RSR; // Receive Status Register
AT91_REG EMAC_ISR; // Interrupt Status Register
AT91_REG EMAC_IER; // Interrupt Enable Register
AT91_REG EMAC_IDR; // Interrupt Disable Register
AT91_REG EMAC_IMR; // Interrupt Mask Register
AT91_REG EMAC_MAN; // PHY Maintenance Register
AT91_REG EMAC_PTR; // Pause Time Register
AT91_REG EMAC_PFR; // Pause Frames received Register
AT91_REG EMAC_FTO; // Frames Transmitted OK Register
AT91_REG EMAC_SCF; // Single Collision Frame Register
AT91_REG EMAC_MCF; // Multiple Collision Frame Register
AT91_REG EMAC_FRO; // Frames Received OK Register
AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
AT91_REG EMAC_ALE; // Alignment Error Register
AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
AT91_REG EMAC_LCOL; // Late Collision Register
AT91_REG EMAC_ECOL; // Excessive Collision Register
AT91_REG EMAC_TUND; // Transmit Underrun Error Register
AT91_REG EMAC_CSE; // Carrier Sense Error Register
AT91_REG EMAC_RRE; // Receive Ressource Error Register
AT91_REG EMAC_ROV; // Receive Overrun Errors Register
AT91_REG EMAC_RSE; // Receive Symbol Errors Register
AT91_REG EMAC_ELE; // Excessive Length Errors Register
AT91_REG EMAC_RJA; // Receive Jabbers Register
AT91_REG EMAC_USF; // Undersize Frames Register
AT91_REG EMAC_STE; // SQE Test Error Register
AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
AT91_REG EMAC_HRT; // Hash Address Top[63:32]
AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
AT91_REG EMAC_TID; // Type ID Checking Register
AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
AT91_REG EMAC_USRIO; // USER Input/Output Register
AT91_REG EMAC_WOL; // Wake On LAN Register
AT91_REG Reserved1[13]; //
AT91_REG EMAC_REV; // Revision Register
} AT91S_EMAC, *AT91PS_EMAC;
// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // ADC Control Register
AT91_REG ADC_MR; // ADC Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // ADC Channel Enable Register
AT91_REG ADC_CHDR; // ADC Channel Disable Register
AT91_REG ADC_CHSR; // ADC Channel Status Register
AT91_REG ADC_SR; // ADC Status Register
AT91_REG ADC_LCDR; // ADC Last Converted Data Register
AT91_REG ADC_IER; // ADC Interrupt Enable Register
AT91_REG ADC_IDR; // ADC Interrupt Disable Register
AT91_REG ADC_IMR; // ADC Interrupt Mask Register
AT91_REG ADC_CDR0; // ADC Channel Data Register 0
AT91_REG ADC_CDR1; // ADC Channel Data Register 1
AT91_REG ADC_CDR2; // ADC Channel Data Register 2
AT91_REG ADC_CDR3; // ADC Channel Data Register 3
AT91_REG ADC_CDR4; // ADC Channel Data Register 4
AT91_REG ADC_CDR5; // ADC Channel Data Register 5
AT91_REG ADC_CDR6; // ADC Channel Data Register 6
AT91_REG ADC_CDR7; // ADC Channel Data Register 7
AT91_REG Reserved1[44]; //
AT91_REG ADC_RPR; // Receive Pointer Register
AT91_REG ADC_RCR; // Receive Counter Register
AT91_REG ADC_TPR; // Transmit Pointer Register
AT91_REG ADC_TCR; // Transmit Counter Register
AT91_REG ADC_RNPR; // Receive Next Pointer Register
AT91_REG ADC_RNCR; // Receive Next Counter Register
AT91_REG ADC_TNPR; // Transmit Next Pointer Register
AT91_REG ADC_TNCR; // Transmit Next Counter Register
AT91_REG ADC_PTCR; // PDC Transfer Control Register
AT91_REG ADC_PTSR; // PDC Transfer Status Register
} AT91S_ADC, *AT91PS_ADC;
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
// *****************************************************************************
typedef struct _AT91S_AES {
AT91_REG AES_CR; // Control Register
AT91_REG AES_MR; // Mode Register
AT91_REG Reserved0[2]; //
AT91_REG AES_IER; // Interrupt Enable Register
AT91_REG AES_IDR; // Interrupt Disable Register
AT91_REG AES_IMR; // Interrupt Mask Register
AT91_REG AES_ISR; // Interrupt Status Register
AT91_REG AES_KEYWxR[4]; // Key Word x Register
AT91_REG Reserved1[4]; //
AT91_REG AES_IDATAxR[4]; // Input Data x Register
AT91_REG AES_ODATAxR[4]; // Output Data x Register
AT91_REG AES_IVxR[4]; // Initialization Vector x Register
AT91_REG Reserved2[35]; //
AT91_REG AES_VR; // AES Version Register
AT91_REG AES_RPR; // Receive Pointer Register
AT91_REG AES_RCR; // Receive Counter Register
AT91_REG AES_TPR; // Transmit Pointer Register
AT91_REG AES_TCR; // Transmit Counter Register
AT91_REG AES_RNPR; // Receive Next Pointer Register
AT91_REG AES_RNCR; // Receive Next Counter Register
AT91_REG AES_TNPR; // Transmit Next Pointer Register
AT91_REG AES_TNCR; // Transmit Next Counter Register
AT91_REG AES_PTCR; // PDC Transfer Control Register
AT91_REG AES_PTSR; // PDC Transfer Status Register
} AT91S_AES, *AT91PS_AES;
// -------- AES_CR : (AES Offset: 0x0) Control Register --------
#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
// *****************************************************************************
typedef struct _AT91S_TDES {
AT91_REG TDES_CR; // Control Register
AT91_REG TDES_MR; // Mode Register
AT91_REG Reserved0[2]; //
AT91_REG TDES_IER; // Interrupt Enable Register
AT91_REG TDES_IDR; // Interrupt Disable Register
AT91_REG TDES_IMR; // Interrupt Mask Register
AT91_REG TDES_ISR; // Interrupt Status Register
AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
AT91_REG Reserved1[2]; //
AT91_REG TDES_IDATAxR[2]; // Input Data x Register
AT91_REG Reserved2[2]; //
AT91_REG TDES_ODATAxR[2]; // Output Data x Register
AT91_REG Reserved3[2]; //
AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
AT91_REG Reserved4[37]; //
AT91_REG TDES_VR; // TDES Version Register
AT91_REG TDES_RPR; // Receive Pointer Register
AT91_REG TDES_RCR; // Receive Counter Register
AT91_REG TDES_TPR; // Transmit Pointer Register
AT91_REG TDES_TCR; // Transmit Counter Register
AT91_REG TDES_RNPR; // Receive Next Pointer Register
AT91_REG TDES_RNCR; // Receive Next Counter Register
AT91_REG TDES_TNPR; // Transmit Next Pointer Register
AT91_REG TDES_TNCR; // Transmit Next Counter Register
AT91_REG TDES_PTCR; // PDC Transfer Control Register
AT91_REG TDES_PTSR; // PDC Transfer Status Register
} AT91S_TDES, *AT91PS_TDES;
// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
// *****************************************************************************
// ========== Register definition for SYS peripheral ==========
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
// ========== Register definition for VREG peripheral ==========
#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
// ========== Register definition for MC peripheral ==========
#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
// ========== Register definition for PDC_SPI1 peripheral ==========
#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
// ========== Register definition for SPI1 peripheral ==========
#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
// ========== Register definition for PDC_SPI0 peripheral ==========
#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
// ========== Register definition for SPI0 peripheral ==========
#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
// ========== Register definition for PDC_SSC peripheral ==========
#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
// ========== Register definition for SSC peripheral ==========
#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
// ========== Register definition for TWI peripheral ==========
#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
// ========== Register definition for PWMC_CH3 peripheral ==========
#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
// ========== Register definition for PWMC_CH2 peripheral ==========
#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH1 peripheral ==========
#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
// ========== Register definition for PWMC_CH0 peripheral ==========
#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
// ========== Register definition for PWMC peripheral ==========
#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TCB peripheral ==========
#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
// ========== Register definition for CAN_MB0 peripheral ==========
#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
// ========== Register definition for CAN_MB1 peripheral ==========
#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
// ========== Register definition for CAN_MB2 peripheral ==========
#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
// ========== Register definition for CAN_MB3 peripheral ==========
#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
// ========== Register definition for CAN_MB4 peripheral ==========
#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB5 peripheral ==========
#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB6 peripheral ==========
#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
// ========== Register definition for CAN_MB7 peripheral ==========
#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
// ========== Register definition for CAN peripheral ==========
#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
// ========== Register definition for EMAC peripheral ==========
#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
// ========== Register definition for PDC_AES peripheral ==========
#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
// ========== Register definition for AES peripheral ==========
#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
// ========== Register definition for PDC_TDES peripheral ==========
#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
// ========== Register definition for TDES peripheral ==========
#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h | C | oos | 207,994 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM7X256.h
// Object : AT91SAM7X256 definitions
// Generated : AT91 SW Application Group 05/20/2005 (16:22:29)
//
// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
// ----------------------------------------------------------------------------
// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR ( 0) // Source Mode Register
#define AIC_SVR (128) // Source Vector Register
#define AIC_IVR (256) // IRQ Vector Register
#define AIC_FVR (260) // FIQ Vector Register
#define AIC_ISR (264) // Interrupt Status Register
#define AIC_IPR (268) // Interrupt Pending Register
#define AIC_IMR (272) // Interrupt Mask Register
#define AIC_CISR (276) // Core Interrupt Status Register
#define AIC_IECR (288) // Interrupt Enable Command Register
#define AIC_IDCR (292) // Interrupt Disable Command Register
#define AIC_ICCR (296) // Interrupt Clear Command Register
#define AIC_ISCR (300) // Interrupt Set Command Register
#define AIC_EOICR (304) // End of Interrupt Command Register
#define AIC_SPU (308) // Spurious Vector Register
#define AIC_DCR (312) // Debug Control Register (Protect)
#define AIC_FFER (320) // Fast Forcing Enable Register
#define AIC_FFDR (324) // Fast Forcing Disable Register
#define AIC_FFSR (328) // Fast Forcing Status Register
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
// *** Register offset in AT91S_PDC structure ***
#define PDC_RPR ( 0) // Receive Pointer Register
#define PDC_RCR ( 4) // Receive Counter Register
#define PDC_TPR ( 8) // Transmit Pointer Register
#define PDC_TCR (12) // Transmit Counter Register
#define PDC_RNPR (16) // Receive Next Pointer Register
#define PDC_RNCR (20) // Receive Next Counter Register
#define PDC_TNPR (24) // Transmit Next Pointer Register
#define PDC_TNCR (28) // Transmit Next Counter Register
#define PDC_PTCR (32) // PDC Transfer Control Register
#define PDC_PTSR (36) // PDC Transfer Status Register
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
// *** Register offset in AT91S_DBGU structure ***
#define DBGU_CR ( 0) // Control Register
#define DBGU_MR ( 4) // Mode Register
#define DBGU_IER ( 8) // Interrupt Enable Register
#define DBGU_IDR (12) // Interrupt Disable Register
#define DBGU_IMR (16) // Interrupt Mask Register
#define DBGU_CSR (20) // Channel Status Register
#define DBGU_RHR (24) // Receiver Holding Register
#define DBGU_THR (28) // Transmitter Holding Register
#define DBGU_BRGR (32) // Baud Rate Generator Register
#define DBGU_CIDR (64) // Chip ID Register
#define DBGU_EXID (68) // Chip ID Extension Register
#define DBGU_FNTR (72) // Force NTRST Register
#define DBGU_RPR (256) // Receive Pointer Register
#define DBGU_RCR (260) // Receive Counter Register
#define DBGU_TPR (264) // Transmit Pointer Register
#define DBGU_TCR (268) // Transmit Counter Register
#define DBGU_RNPR (272) // Receive Next Pointer Register
#define DBGU_RNCR (276) // Receive Next Counter Register
#define DBGU_TNPR (280) // Transmit Next Pointer Register
#define DBGU_TNCR (284) // Transmit Next Counter Register
#define DBGU_PTCR (288) // PDC Transfer Control Register
#define DBGU_PTSR (292) // PDC Transfer Status Register
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
// *** Register offset in AT91S_PIO structure ***
#define PIO_PER ( 0) // PIO Enable Register
#define PIO_PDR ( 4) // PIO Disable Register
#define PIO_PSR ( 8) // PIO Status Register
#define PIO_OER (16) // Output Enable Register
#define PIO_ODR (20) // Output Disable Registerr
#define PIO_OSR (24) // Output Status Register
#define PIO_IFER (32) // Input Filter Enable Register
#define PIO_IFDR (36) // Input Filter Disable Register
#define PIO_IFSR (40) // Input Filter Status Register
#define PIO_SODR (48) // Set Output Data Register
#define PIO_CODR (52) // Clear Output Data Register
#define PIO_ODSR (56) // Output Data Status Register
#define PIO_PDSR (60) // Pin Data Status Register
#define PIO_IER (64) // Interrupt Enable Register
#define PIO_IDR (68) // Interrupt Disable Register
#define PIO_IMR (72) // Interrupt Mask Register
#define PIO_ISR (76) // Interrupt Status Register
#define PIO_MDER (80) // Multi-driver Enable Register
#define PIO_MDDR (84) // Multi-driver Disable Register
#define PIO_MDSR (88) // Multi-driver Status Register
#define PIO_PPUDR (96) // Pull-up Disable Register
#define PIO_PPUER (100) // Pull-up Enable Register
#define PIO_PPUSR (104) // Pull-up Status Register
#define PIO_ASR (112) // Select A Register
#define PIO_BSR (116) // Select B Register
#define PIO_ABSR (120) // AB Select Status Register
#define PIO_OWER (160) // Output Write Enable Register
#define PIO_OWDR (164) // Output Write Disable Register
#define PIO_OWSR (168) // Output Write Status Register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
// *** Register offset in AT91S_CKGR structure ***
#define CKGR_MOR ( 0) // Main Oscillator Register
#define CKGR_MCFR ( 4) // Main Clock Frequency Register
#define CKGR_PLLR (12) // PLL Register
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
// *** Register offset in AT91S_PMC structure ***
#define PMC_SCER ( 0) // System Clock Enable Register
#define PMC_SCDR ( 4) // System Clock Disable Register
#define PMC_SCSR ( 8) // System Clock Status Register
#define PMC_PCER (16) // Peripheral Clock Enable Register
#define PMC_PCDR (20) // Peripheral Clock Disable Register
#define PMC_PCSR (24) // Peripheral Clock Status Register
#define PMC_MOR (32) // Main Oscillator Register
#define PMC_MCFR (36) // Main Clock Frequency Register
#define PMC_PLLR (44) // PLL Register
#define PMC_MCKR (48) // Master Clock Register
#define PMC_PCKR (64) // Programmable Clock Register
#define PMC_IER (96) // Interrupt Enable Register
#define PMC_IDR (100) // Interrupt Disable Register
#define PMC_SR (104) // Status Register
#define PMC_IMR (108) // Interrupt Mask Register
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RSTC structure ***
#define RSTC_RCR ( 0) // Reset Control Register
#define RSTC_RSR ( 4) // Reset Status Register
#define RSTC_RMR ( 8) // Reset Mode Register
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RTTC structure ***
#define RTTC_RTMR ( 0) // Real-time Mode Register
#define RTTC_RTAR ( 4) // Real-time Alarm Register
#define RTTC_RTVR ( 8) // Real-time Value Register
#define RTTC_RTSR (12) // Real-time Status Register
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PITC structure ***
#define PITC_PIMR ( 0) // Period Interval Mode Register
#define PITC_PISR ( 4) // Period Interval Status Register
#define PITC_PIVR ( 8) // Period Interval Value Register
#define PITC_PIIR (12) // Period Interval Image Register
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_WDTC structure ***
#define WDTC_WDCR ( 0) // Watchdog Control Register
#define WDTC_WDMR ( 4) // Watchdog Mode Register
#define WDTC_WDSR ( 8) // Watchdog Status Register
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_VREG structure ***
#define VREG_MR ( 0) // Voltage Regulator Mode Register
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_MC structure ***
#define MC_RCR ( 0) // MC Remap Control Register
#define MC_ASR ( 4) // MC Abort Status Register
#define MC_AASR ( 8) // MC Abort Address Status Register
#define MC_FMR (96) // MC Flash Mode Register
#define MC_FCR (100) // MC Flash Command Register
#define MC_FSR (104) // MC Flash Status Register
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
// *** Register offset in AT91S_SPI structure ***
#define SPI_CR ( 0) // Control Register
#define SPI_MR ( 4) // Mode Register
#define SPI_RDR ( 8) // Receive Data Register
#define SPI_TDR (12) // Transmit Data Register
#define SPI_SR (16) // Status Register
#define SPI_IER (20) // Interrupt Enable Register
#define SPI_IDR (24) // Interrupt Disable Register
#define SPI_IMR (28) // Interrupt Mask Register
#define SPI_CSR (48) // Chip Select Register
#define SPI_RPR (256) // Receive Pointer Register
#define SPI_RCR (260) // Receive Counter Register
#define SPI_TPR (264) // Transmit Pointer Register
#define SPI_TCR (268) // Transmit Counter Register
#define SPI_RNPR (272) // Receive Next Pointer Register
#define SPI_RNCR (276) // Receive Next Counter Register
#define SPI_TNPR (280) // Transmit Next Pointer Register
#define SPI_TNCR (284) // Transmit Next Counter Register
#define SPI_PTCR (288) // PDC Transfer Control Register
#define SPI_PTSR (292) // PDC Transfer Status Register
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
// *** Register offset in AT91S_USART structure ***
#define US_CR ( 0) // Control Register
#define US_MR ( 4) // Mode Register
#define US_IER ( 8) // Interrupt Enable Register
#define US_IDR (12) // Interrupt Disable Register
#define US_IMR (16) // Interrupt Mask Register
#define US_CSR (20) // Channel Status Register
#define US_RHR (24) // Receiver Holding Register
#define US_THR (28) // Transmitter Holding Register
#define US_BRGR (32) // Baud Rate Generator Register
#define US_RTOR (36) // Receiver Time-out Register
#define US_TTGR (40) // Transmitter Time-guard Register
#define US_FIDI (64) // FI_DI_Ratio Register
#define US_NER (68) // Nb Errors Register
#define US_IF (76) // IRDA_FILTER Register
#define US_RPR (256) // Receive Pointer Register
#define US_RCR (260) // Receive Counter Register
#define US_TPR (264) // Transmit Pointer Register
#define US_TCR (268) // Transmit Counter Register
#define US_RNPR (272) // Receive Next Pointer Register
#define US_RNCR (276) // Receive Next Counter Register
#define US_TNPR (280) // Transmit Next Pointer Register
#define US_TNCR (284) // Transmit Next Counter Register
#define US_PTCR (288) // PDC Transfer Control Register
#define US_PTSR (292) // PDC Transfer Status Register
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_SSC structure ***
#define SSC_CR ( 0) // Control Register
#define SSC_CMR ( 4) // Clock Mode Register
#define SSC_RCMR (16) // Receive Clock ModeRegister
#define SSC_RFMR (20) // Receive Frame Mode Register
#define SSC_TCMR (24) // Transmit Clock Mode Register
#define SSC_TFMR (28) // Transmit Frame Mode Register
#define SSC_RHR (32) // Receive Holding Register
#define SSC_THR (36) // Transmit Holding Register
#define SSC_RSHR (48) // Receive Sync Holding Register
#define SSC_TSHR (52) // Transmit Sync Holding Register
#define SSC_SR (64) // Status Register
#define SSC_IER (68) // Interrupt Enable Register
#define SSC_IDR (72) // Interrupt Disable Register
#define SSC_IMR (76) // Interrupt Mask Register
#define SSC_RPR (256) // Receive Pointer Register
#define SSC_RCR (260) // Receive Counter Register
#define SSC_TPR (264) // Transmit Pointer Register
#define SSC_TCR (268) // Transmit Counter Register
#define SSC_RNPR (272) // Receive Next Pointer Register
#define SSC_RNCR (276) // Receive Next Counter Register
#define SSC_TNPR (280) // Transmit Next Pointer Register
#define SSC_TNCR (284) // Transmit Next Counter Register
#define SSC_PTCR (288) // PDC Transfer Control Register
#define SSC_PTSR (292) // PDC Transfer Status Register
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
// *** Register offset in AT91S_TWI structure ***
#define TWI_CR ( 0) // Control Register
#define TWI_MMR ( 4) // Master Mode Register
#define TWI_IADR (12) // Internal Address Register
#define TWI_CWGR (16) // Clock Waveform Generator Register
#define TWI_SR (32) // Status Register
#define TWI_IER (36) // Interrupt Enable Register
#define TWI_IDR (40) // Interrupt Disable Register
#define TWI_IMR (44) // Interrupt Mask Register
#define TWI_RHR (48) // Receive Holding Register
#define TWI_THR (52) // Transmit Holding Register
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR PWMC Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_PWMC_CH structure ***
#define PWMC_CMR ( 0) // Channel Mode Register
#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
#define PWMC_CPRDR ( 8) // Channel Period Register
#define PWMC_CCNTR (12) // Channel Counter Register
#define PWMC_CUPDR (16) // Channel Update Register
#define PWMC_Reserved (20) // Reserved
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PWMC structure ***
#define PWMC_MR ( 0) // PWMC Mode Register
#define PWMC_ENA ( 4) // PWMC Enable Register
#define PWMC_DIS ( 8) // PWMC Disable Register
#define PWMC_SR (12) // PWMC Status Register
#define PWMC_IER (16) // PWMC Interrupt Enable Register
#define PWMC_IDR (20) // PWMC Interrupt Disable Register
#define PWMC_IMR (24) // PWMC Interrupt Mask Register
#define PWMC_ISR (28) // PWMC Interrupt Status Register
#define PWMC_VR (252) // PWMC Version Register
#define PWMC_CH (512) // PWMC Channel
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
// *** Register offset in AT91S_UDP structure ***
#define UDP_NUM ( 0) // Frame Number Register
#define UDP_GLBSTATE ( 4) // Global State Register
#define UDP_FADDR ( 8) // Function Address Register
#define UDP_IER (16) // Interrupt Enable Register
#define UDP_IDR (20) // Interrupt Disable Register
#define UDP_IMR (24) // Interrupt Mask Register
#define UDP_ISR (28) // Interrupt Status Register
#define UDP_ICR (32) // Interrupt Clear Register
#define UDP_RSTEP (40) // Reset Endpoint Register
#define UDP_CSR (48) // Endpoint Control and Status Register
#define UDP_FDR (80) // Endpoint FIFO Data Register
#define UDP_TXVC (116) // Transceiver Control Register
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_TC structure ***
#define TC_CCR ( 0) // Channel Control Register
#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
#define TC_CV (16) // Counter Value
#define TC_RA (20) // Register A
#define TC_RB (24) // Register B
#define TC_RC (28) // Register C
#define TC_SR (32) // Status Register
#define TC_IER (36) // Interrupt Enable Register
#define TC_IDR (40) // Interrupt Disable Register
#define TC_IMR (44) // Interrupt Mask Register
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE (0x1 << 15) // (TC)
#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
// *** Register offset in AT91S_TCB structure ***
#define TCB_TC0 ( 0) // TC Channel 0
#define TCB_TC1 (64) // TC Channel 1
#define TCB_TC2 (128) // TC Channel 2
#define TCB_BCR (192) // TC Block Control Register
#define TCB_BMR (196) // TC Block Mode Register
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
// *****************************************************************************
// *** Register offset in AT91S_CAN_MB structure ***
#define CAN_MB_MMR ( 0) // MailBox Mode Register
#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register
#define CAN_MB_MID ( 8) // MailBox ID Register
#define CAN_MB_MFID (12) // MailBox Family ID Register
#define CAN_MB_MSR (16) // MailBox Status Register
#define CAN_MB_MDL (20) // MailBox Data Low Register
#define CAN_MB_MDH (24) // MailBox Data High Register
#define CAN_MB_MCR (28) // MailBox Control Register
// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network Interface
// *****************************************************************************
// *** Register offset in AT91S_CAN structure ***
#define CAN_MR ( 0) // Mode Register
#define CAN_IER ( 4) // Interrupt Enable Register
#define CAN_IDR ( 8) // Interrupt Disable Register
#define CAN_IMR (12) // Interrupt Mask Register
#define CAN_SR (16) // Status Register
#define CAN_BR (20) // Baudrate Register
#define CAN_TIM (24) // Timer Register
#define CAN_TIMESTP (28) // Time Stamp Register
#define CAN_ECR (32) // Error Counter Register
#define CAN_TCR (36) // Transfer Command Register
#define CAN_ACR (40) // Abort Command Register
#define CAN_VR (252) // Version Register
#define CAN_MB0 (512) // CAN Mailbox 0
#define CAN_MB1 (544) // CAN Mailbox 1
#define CAN_MB2 (576) // CAN Mailbox 2
#define CAN_MB3 (608) // CAN Mailbox 3
#define CAN_MB4 (640) // CAN Mailbox 4
#define CAN_MB5 (672) // CAN Mailbox 5
#define CAN_MB6 (704) // CAN Mailbox 6
#define CAN_MB7 (736) // CAN Mailbox 7
#define CAN_MB8 (768) // CAN Mailbox 8
#define CAN_MB9 (800) // CAN Mailbox 9
#define CAN_MB10 (832) // CAN Mailbox 10
#define CAN_MB11 (864) // CAN Mailbox 11
#define CAN_MB12 (896) // CAN Mailbox 12
#define CAN_MB13 (928) // CAN Mailbox 13
#define CAN_MB14 (960) // CAN Mailbox 14
#define CAN_MB15 (992) // CAN Mailbox 15
// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
// *****************************************************************************
// *** Register offset in AT91S_EMAC structure ***
#define EMAC_NCR ( 0) // Network Control Register
#define EMAC_NCFGR ( 4) // Network Configuration Register
#define EMAC_NSR ( 8) // Network Status Register
#define EMAC_TSR (20) // Transmit Status Register
#define EMAC_RBQP (24) // Receive Buffer Queue Pointer
#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer
#define EMAC_RSR (32) // Receive Status Register
#define EMAC_ISR (36) // Interrupt Status Register
#define EMAC_IER (40) // Interrupt Enable Register
#define EMAC_IDR (44) // Interrupt Disable Register
#define EMAC_IMR (48) // Interrupt Mask Register
#define EMAC_MAN (52) // PHY Maintenance Register
#define EMAC_PTR (56) // Pause Time Register
#define EMAC_PFR (60) // Pause Frames received Register
#define EMAC_FTO (64) // Frames Transmitted OK Register
#define EMAC_SCF (68) // Single Collision Frame Register
#define EMAC_MCF (72) // Multiple Collision Frame Register
#define EMAC_FRO (76) // Frames Received OK Register
#define EMAC_FCSE (80) // Frame Check Sequence Error Register
#define EMAC_ALE (84) // Alignment Error Register
#define EMAC_DTF (88) // Deferred Transmission Frame Register
#define EMAC_LCOL (92) // Late Collision Register
#define EMAC_ECOL (96) // Excessive Collision Register
#define EMAC_TUND (100) // Transmit Underrun Error Register
#define EMAC_CSE (104) // Carrier Sense Error Register
#define EMAC_RRE (108) // Receive Ressource Error Register
#define EMAC_ROV (112) // Receive Overrun Errors Register
#define EMAC_RSE (116) // Receive Symbol Errors Register
#define EMAC_ELE (120) // Excessive Length Errors Register
#define EMAC_RJA (124) // Receive Jabbers Register
#define EMAC_USF (128) // Undersize Frames Register
#define EMAC_STE (132) // SQE Test Error Register
#define EMAC_RLE (136) // Receive Length Field Mismatch Register
#define EMAC_TPF (140) // Transmitted Pause Frames Register
#define EMAC_HRB (144) // Hash Address Bottom[31:0]
#define EMAC_HRT (148) // Hash Address Top[63:32]
#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes
#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes
#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes
#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes
#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes
#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes
#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes
#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes
#define EMAC_TID (184) // Type ID Checking Register
#define EMAC_TPQ (188) // Transmit Pause Quantum Register
#define EMAC_USRIO (192) // USER Input/Output Register
#define EMAC_WOL (196) // Wake On LAN Register
#define EMAC_REV (252) // Revision Register
// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
// *** Register offset in AT91S_ADC structure ***
#define ADC_CR ( 0) // ADC Control Register
#define ADC_MR ( 4) // ADC Mode Register
#define ADC_CHER (16) // ADC Channel Enable Register
#define ADC_CHDR (20) // ADC Channel Disable Register
#define ADC_CHSR (24) // ADC Channel Status Register
#define ADC_SR (28) // ADC Status Register
#define ADC_LCDR (32) // ADC Last Converted Data Register
#define ADC_IER (36) // ADC Interrupt Enable Register
#define ADC_IDR (40) // ADC Interrupt Disable Register
#define ADC_IMR (44) // ADC Interrupt Mask Register
#define ADC_CDR0 (48) // ADC Channel Data Register 0
#define ADC_CDR1 (52) // ADC Channel Data Register 1
#define ADC_CDR2 (56) // ADC Channel Data Register 2
#define ADC_CDR3 (60) // ADC Channel Data Register 3
#define ADC_CDR4 (64) // ADC Channel Data Register 4
#define ADC_CDR5 (68) // ADC Channel Data Register 5
#define ADC_CDR6 (72) // ADC Channel Data Register 6
#define ADC_CDR7 (76) // ADC Channel Data Register 7
#define ADC_RPR (256) // Receive Pointer Register
#define ADC_RCR (260) // Receive Counter Register
#define ADC_TPR (264) // Transmit Pointer Register
#define ADC_TCR (268) // Transmit Counter Register
#define ADC_RNPR (272) // Receive Next Pointer Register
#define ADC_RNCR (276) // Receive Next Counter Register
#define ADC_TNPR (280) // Transmit Next Pointer Register
#define ADC_TNCR (284) // Transmit Next Counter Register
#define ADC_PTCR (288) // PDC Transfer Control Register
#define ADC_PTSR (292) // PDC Transfer Status Register
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
// *****************************************************************************
// *** Register offset in AT91S_AES structure ***
#define AES_CR ( 0) // Control Register
#define AES_MR ( 4) // Mode Register
#define AES_IER (16) // Interrupt Enable Register
#define AES_IDR (20) // Interrupt Disable Register
#define AES_IMR (24) // Interrupt Mask Register
#define AES_ISR (28) // Interrupt Status Register
#define AES_KEYWxR (32) // Key Word x Register
#define AES_IDATAxR (64) // Input Data x Register
#define AES_ODATAxR (80) // Output Data x Register
#define AES_IVxR (96) // Initialization Vector x Register
#define AES_VR (252) // AES Version Register
#define AES_RPR (256) // Receive Pointer Register
#define AES_RCR (260) // Receive Counter Register
#define AES_TPR (264) // Transmit Pointer Register
#define AES_TCR (268) // Transmit Counter Register
#define AES_RNPR (272) // Receive Next Pointer Register
#define AES_RNCR (276) // Receive Next Counter Register
#define AES_TNPR (280) // Transmit Next Pointer Register
#define AES_TNCR (284) // Transmit Next Counter Register
#define AES_PTCR (288) // PDC Transfer Control Register
#define AES_PTSR (292) // PDC Transfer Status Register
// -------- AES_CR : (AES Offset: 0x0) Control Register --------
#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing
#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset
#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading
// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode
#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay
#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode
#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet).
#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode
#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode.
#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode.
#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode.
#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode
#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size
#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit.
#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit.
#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit.
#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit.
#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit.
#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key
#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type
#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY
#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End
#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End
#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full
#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty
#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection
// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status
#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access.
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
// *****************************************************************************
// *** Register offset in AT91S_TDES structure ***
#define TDES_CR ( 0) // Control Register
#define TDES_MR ( 4) // Mode Register
#define TDES_IER (16) // Interrupt Enable Register
#define TDES_IDR (20) // Interrupt Disable Register
#define TDES_IMR (24) // Interrupt Mask Register
#define TDES_ISR (28) // Interrupt Status Register
#define TDES_KEY1WxR (32) // Key 1 Word x Register
#define TDES_KEY2WxR (40) // Key 2 Word x Register
#define TDES_KEY3WxR (48) // Key 3 Word x Register
#define TDES_IDATAxR (64) // Input Data x Register
#define TDES_ODATAxR (80) // Output Data x Register
#define TDES_IVxR (96) // Initialization Vector x Register
#define TDES_VR (252) // TDES Version Register
#define TDES_RPR (256) // Receive Pointer Register
#define TDES_RCR (260) // Receive Counter Register
#define TDES_TPR (264) // Transmit Pointer Register
#define TDES_TCR (268) // Transmit Counter Register
#define TDES_RNPR (272) // Receive Next Pointer Register
#define TDES_RNCR (276) // Receive Next Counter Register
#define TDES_TNPR (280) // Transmit Next Pointer Register
#define TDES_TNCR (284) // Transmit Next Counter Register
#define TDES_PTCR (288) // PDC Transfer Control Register
#define TDES_PTSR (292) // PDC Transfer Status Register
// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing
#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset
// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode
#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode
#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode
#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode
#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet).
#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode
#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode.
#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode
#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size
#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit.
#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit.
#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit.
#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit.
// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY
#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End
#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End
#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full
#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty
#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection
// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status
#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access.
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
// *****************************************************************************
// ========== Register definition for SYS peripheral ==========
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register
#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register
#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register
#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register
#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register
#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register
#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register
#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register
#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register
#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register
#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register
#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr
#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register
#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register
#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register
#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register
#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register
#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register
#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
// ========== Register definition for VREG peripheral ==========
#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
// ========== Register definition for MC peripheral ==========
#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
// ========== Register definition for PDC_SPI1 peripheral ==========
#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
// ========== Register definition for SPI1 peripheral ==========
#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register
#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register
#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register
#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register
#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register
#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register
#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register
#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register
#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register
// ========== Register definition for PDC_SPI0 peripheral ==========
#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
// ========== Register definition for SPI0 peripheral ==========
#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register
#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register
#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register
#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register
#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register
#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register
#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register
#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register
#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
// ========== Register definition for PDC_SSC peripheral ==========
#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
// ========== Register definition for SSC peripheral ==========
#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
// ========== Register definition for TWI peripheral ==========
#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
// ========== Register definition for PWMC_CH3 peripheral ==========
#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
// ========== Register definition for PWMC_CH2 peripheral ==========
#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH1 peripheral ==========
#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
// ========== Register definition for PWMC_CH0 peripheral ==========
#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
// ========== Register definition for PWMC peripheral ==========
#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register
#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TCB peripheral ==========
#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
// ========== Register definition for CAN_MB0 peripheral ==========
#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register
#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register
#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register
#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
// ========== Register definition for CAN_MB1 peripheral ==========
#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register
#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register
#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register
#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
// ========== Register definition for CAN_MB2 peripheral ==========
#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register
#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register
#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register
// ========== Register definition for CAN_MB3 peripheral ==========
#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register
#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register
#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register
#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
// ========== Register definition for CAN_MB4 peripheral ==========
#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register
#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register
#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register
#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB5 peripheral ==========
#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB6 peripheral ==========
#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
// ========== Register definition for CAN_MB7 peripheral ==========
#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
// ========== Register definition for CAN peripheral ==========
#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register
#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register
#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register
#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register
#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register
#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register
#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register
#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register
#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register
#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register
#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register
#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register
// ========== Register definition for EMAC peripheral ==========
#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register
#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register
#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register
#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register
#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register
#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register
#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register
#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register
#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register
#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register
#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register
#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register
#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register
#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register
#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register
#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register
#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register
#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register
#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register
#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register
#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register
#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register
#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register
#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register
#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register
#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
// ========== Register definition for PDC_AES peripheral ==========
#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register
#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register
#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register
#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
// ========== Register definition for AES peripheral ==========
#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register
#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register
#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register
#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register
#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register
#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register
#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register
#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register
#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register
#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register
#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register
// ========== Register definition for PDC_TDES peripheral ==========
#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register
#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
// ========== Register definition for TDES peripheral ==========
#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register
#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register
#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register
#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register
#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register
#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register
#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register
#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register
#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register
#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register
#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register
#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register
#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave
#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave
#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock
#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock
#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave
#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave
#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ( 1) // System Peripheral
#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
#define AT91C_ID_US0 ( 6) // USART 0
#define AT91C_ID_US1 ( 7) // USART 1
#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
#define AT91C_ID_TWI ( 9) // Two-Wire Interface
#define AT91C_ID_PWMC (10) // PWM Controller
#define AT91C_ID_UDP (11) // USB Device Port
#define AT91C_ID_TC0 (12) // Timer Counter 0
#define AT91C_ID_TC1 (13) // Timer Counter 1
#define AT91C_ID_TC2 (14) // Timer Counter 2
#define AT91C_ID_CAN (15) // Control Area Network Controller
#define AT91C_ID_EMAC (16) // Ethernet MAC
#define AT91C_ID_ADC (17) // Analog-to-Digital Converter
#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit
#define AT91C_ID_TDES (19) // Triple Data Encryption Standard
#define AT91C_ID_20_Reserved (20) // Reserved
#define AT91C_ID_21_Reserved (21) // Reserved
#define AT91C_ID_22_Reserved (22) // Reserved
#define AT91C_ID_23_Reserved (23) // Reserved
#define AT91C_ID_24_Reserved (24) // Reserved
#define AT91C_ID_25_Reserved (25) // Reserved
#define AT91C_ID_26_Reserved (26) // Reserved
#define AT91C_ID_27_Reserved (27) // Reserved
#define AT91C_ID_28_Reserved (28) // Reserved
#define AT91C_ID_29_Reserved (29) // Reserved
#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address
#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address
#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address
#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address
#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address
#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address
#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address
#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address
#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address
#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address
#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address
#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address
#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address
#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address
#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address
#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address
#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address
#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address
#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address
#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address
#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
// *****************************************************************************
#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte)
#define AT91C_IFLASH (0x00100000) // Internal ROM base address
#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte)
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h | C | oos | 186,248 |
EXTERN pxCurrentTCB
EXTERN ulCriticalNesting
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Context save and restore macro definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
portSAVE_CONTEXT MACRO
; Push R0 as we are going to use the register.
STMDB SP!, {R0}
; Set R0 to point to the task stack pointer.
STMDB SP, {SP}^
NOP
SUB SP, SP, #4
LDMIA SP!, {R0}
; Push the return address onto the stack.
STMDB R0!, {LR}
; Now we have saved LR we can use it instead of R0.
MOV LR, R0
; Pop R0 so we can save it onto the system mode stack.
LDMIA SP!, {R0}
; Push all the system mode registers onto the task stack.
STMDB LR, {R0-LR}^
NOP
SUB LR, LR, #60
; Push the SPSR onto the task stack.
MRS R0, SPSR
STMDB LR!, {R0}
LDR R0, =ulCriticalNesting
LDR R0, [R0]
STMDB LR!, {R0}
; Store the new top of stack for the task.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
STR LR, [R0]
ENDM
portRESTORE_CONTEXT MACRO
; Set the LR to the task stack.
LDR R1, =pxCurrentTCB
LDR R0, [R1]
LDR LR, [R0]
; The critical nesting depth is the first item on the stack.
; Load it into the ulCriticalNesting variable.
LDR R0, =ulCriticalNesting
LDMFD LR!, {R1}
STR R1, [R0]
; Get the SPSR from the stack.
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
; Restore all system mode registers for the task.
LDMFD LR, {R0-R14}^
NOP
; Restore the return address.
LDR LR, [LR, #+60]
; And return - correcting the offset in the LR to obtain the
; correct address.
SUBS PC, LR, #4
ENDM
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h | C | oos | 1,770 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM7X128.h
// Object : AT91SAM7X128 definitions
// Generated : AT91 SW Application Group 05/20/2005 (16:22:23)
//
// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005//
// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005//
// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005//
// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM7X128_H
#define AT91SAM7X128_H
typedef volatile unsigned int AT91_REG;// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
typedef struct _AT91S_SYS {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved2[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved3[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved4[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved5[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved6[1]; //
AT91_REG PIOA_OER; // Output Enable Register
AT91_REG PIOA_ODR; // Output Disable Registerr
AT91_REG PIOA_OSR; // Output Status Register
AT91_REG Reserved7[1]; //
AT91_REG PIOA_IFER; // Input Filter Enable Register
AT91_REG PIOA_IFDR; // Input Filter Disable Register
AT91_REG PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved8[1]; //
AT91_REG PIOA_SODR; // Set Output Data Register
AT91_REG PIOA_CODR; // Clear Output Data Register
AT91_REG PIOA_ODSR; // Output Data Status Register
AT91_REG PIOA_PDSR; // Pin Data Status Register
AT91_REG PIOA_IER; // Interrupt Enable Register
AT91_REG PIOA_IDR; // Interrupt Disable Register
AT91_REG PIOA_IMR; // Interrupt Mask Register
AT91_REG PIOA_ISR; // Interrupt Status Register
AT91_REG PIOA_MDER; // Multi-driver Enable Register
AT91_REG PIOA_MDDR; // Multi-driver Disable Register
AT91_REG PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved9[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved10[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved11[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved12[85]; //
AT91_REG PIOB_PER; // PIO Enable Register
AT91_REG PIOB_PDR; // PIO Disable Register
AT91_REG PIOB_PSR; // PIO Status Register
AT91_REG Reserved13[1]; //
AT91_REG PIOB_OER; // Output Enable Register
AT91_REG PIOB_ODR; // Output Disable Registerr
AT91_REG PIOB_OSR; // Output Status Register
AT91_REG Reserved14[1]; //
AT91_REG PIOB_IFER; // Input Filter Enable Register
AT91_REG PIOB_IFDR; // Input Filter Disable Register
AT91_REG PIOB_IFSR; // Input Filter Status Register
AT91_REG Reserved15[1]; //
AT91_REG PIOB_SODR; // Set Output Data Register
AT91_REG PIOB_CODR; // Clear Output Data Register
AT91_REG PIOB_ODSR; // Output Data Status Register
AT91_REG PIOB_PDSR; // Pin Data Status Register
AT91_REG PIOB_IER; // Interrupt Enable Register
AT91_REG PIOB_IDR; // Interrupt Disable Register
AT91_REG PIOB_IMR; // Interrupt Mask Register
AT91_REG PIOB_ISR; // Interrupt Status Register
AT91_REG PIOB_MDER; // Multi-driver Enable Register
AT91_REG PIOB_MDDR; // Multi-driver Disable Register
AT91_REG PIOB_MDSR; // Multi-driver Status Register
AT91_REG Reserved16[1]; //
AT91_REG PIOB_PPUDR; // Pull-up Disable Register
AT91_REG PIOB_PPUER; // Pull-up Enable Register
AT91_REG PIOB_PPUSR; // Pull-up Status Register
AT91_REG Reserved17[1]; //
AT91_REG PIOB_ASR; // Select A Register
AT91_REG PIOB_BSR; // Select B Register
AT91_REG PIOB_ABSR; // AB Select Status Register
AT91_REG Reserved18[9]; //
AT91_REG PIOB_OWER; // Output Write Enable Register
AT91_REG PIOB_OWDR; // Output Write Disable Register
AT91_REG PIOB_OWSR; // Output Write Status Register
AT91_REG Reserved19[341]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved20[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved21[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved22[1]; //
AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved23[3]; //
AT91_REG PMC_PCKR[4]; // Programmable Clock Register
AT91_REG Reserved24[4]; //
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved25[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved26[5]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved27[5]; //
AT91_REG VREG_MR; // Voltage Regulator Mode Register
} AT91S_SYS, *AT91PS_SYS;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
// *****************************************************************************
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG Reserved0[1]; //
AT91_REG CKGR_PLLR; // PLL Register
} AT91S_CKGR, *AT91PS_CKGR;
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved2[1]; //
AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved3[3]; //
AT91_REG PMC_PCKR[4]; // Programmable Clock Register
AT91_REG Reserved4[4]; //
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
// *****************************************************************************
typedef struct _AT91S_VREG {
AT91_REG VREG_MR; // Voltage Regulator Mode Register
} AT91S_VREG, *AT91PS_VREG;
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved0[21]; //
AT91_REG MC_FMR; // MC Flash Mode Register
AT91_REG MC_FCR; // MC Flash Command Register
AT91_REG MC_FSR; // MC Flash Status Register
} AT91S_MC, *AT91PS_MC;
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[5]; //
AT91_REG US_FIDI; // FI_DI_Ratio Register
AT91_REG US_NER; // Nb Errors Register
AT91_REG Reserved1[1]; //
AT91_REG US_IF; // IRDA_FILTER Register
AT91_REG Reserved2[44]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
AT91_REG US_RNPR; // Receive Next Pointer Register
AT91_REG US_RNCR; // Receive Next Counter Register
AT91_REG US_TNPR; // Transmit Next Pointer Register
AT91_REG US_TNCR; // Transmit Next Counter Register
AT91_REG US_PTCR; // PDC Transfer Control Register
AT91_REG US_PTSR; // PDC Transfer Status Register
} AT91S_USART, *AT91PS_USART;
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
typedef struct _AT91S_SSC {
AT91_REG SSC_CR; // Control Register
AT91_REG SSC_CMR; // Clock Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SSC_RCMR; // Receive Clock ModeRegister
AT91_REG SSC_RFMR; // Receive Frame Mode Register
AT91_REG SSC_TCMR; // Transmit Clock Mode Register
AT91_REG SSC_TFMR; // Transmit Frame Mode Register
AT91_REG SSC_RHR; // Receive Holding Register
AT91_REG SSC_THR; // Transmit Holding Register
AT91_REG Reserved1[2]; //
AT91_REG SSC_RSHR; // Receive Sync Holding Register
AT91_REG SSC_TSHR; // Transmit Sync Holding Register
AT91_REG Reserved2[2]; //
AT91_REG SSC_SR; // Status Register
AT91_REG SSC_IER; // Interrupt Enable Register
AT91_REG SSC_IDR; // Interrupt Disable Register
AT91_REG SSC_IMR; // Interrupt Mask Register
AT91_REG Reserved3[44]; //
AT91_REG SSC_RPR; // Receive Pointer Register
AT91_REG SSC_RCR; // Receive Counter Register
AT91_REG SSC_TPR; // Transmit Pointer Register
AT91_REG SSC_TCR; // Transmit Counter Register
AT91_REG SSC_RNPR; // Receive Next Pointer Register
AT91_REG SSC_RNCR; // Receive Next Counter Register
AT91_REG SSC_TNPR; // Transmit Next Pointer Register
AT91_REG SSC_TNCR; // Transmit Next Counter Register
AT91_REG SSC_PTCR; // PDC Transfer Control Register
AT91_REG SSC_PTSR; // PDC Transfer Status Register
} AT91S_SSC, *AT91PS_SSC;
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; // Control Register
AT91_REG TWI_MMR; // Master Mode Register
AT91_REG Reserved0[1]; //
AT91_REG TWI_IADR; // Internal Address Register
AT91_REG TWI_CWGR; // Clock Waveform Generator Register
AT91_REG Reserved1[3]; //
AT91_REG TWI_SR; // Status Register
AT91_REG TWI_IER; // Interrupt Enable Register
AT91_REG TWI_IDR; // Interrupt Disable Register
AT91_REG TWI_IMR; // Interrupt Mask Register
AT91_REG TWI_RHR; // Receive Holding Register
AT91_REG TWI_THR; // Transmit Holding Register
} AT91S_TWI, *AT91PS_TWI;
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR PWMC Channel Interface
// *****************************************************************************
typedef struct _AT91S_PWMC_CH {
AT91_REG PWMC_CMR; // Channel Mode Register
AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
AT91_REG PWMC_CPRDR; // Channel Period Register
AT91_REG PWMC_CCNTR; // Channel Counter Register
AT91_REG PWMC_CUPDR; // Channel Update Register
AT91_REG PWMC_Reserved[3]; // Reserved
} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
// *****************************************************************************
typedef struct _AT91S_PWMC {
AT91_REG PWMC_MR; // PWMC Mode Register
AT91_REG PWMC_ENA; // PWMC Enable Register
AT91_REG PWMC_DIS; // PWMC Disable Register
AT91_REG PWMC_SR; // PWMC Status Register
AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
AT91_REG Reserved0[55]; //
AT91_REG PWMC_VR; // PWMC Version Register
AT91_REG Reserved1[64]; //
AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
} AT91S_PWMC, *AT91PS_PWMC;
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
typedef struct _AT91S_UDP {
AT91_REG UDP_NUM; // Frame Number Register
AT91_REG UDP_GLBSTATE; // Global State Register
AT91_REG UDP_FADDR; // Function Address Register
AT91_REG Reserved0[1]; //
AT91_REG UDP_IER; // Interrupt Enable Register
AT91_REG UDP_IDR; // Interrupt Disable Register
AT91_REG UDP_IMR; // Interrupt Mask Register
AT91_REG UDP_ISR; // Interrupt Status Register
AT91_REG UDP_ICR; // Interrupt Clear Register
AT91_REG Reserved1[1]; //
AT91_REG UDP_RSTEP; // Reset Endpoint Register
AT91_REG Reserved2[1]; //
AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
AT91_REG Reserved3[2]; //
AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
AT91_REG Reserved4[3]; //
AT91_REG UDP_TXVC; // Transceiver Control Register
} AT91S_UDP, *AT91PS_UDP;
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
// *****************************************************************************
typedef struct _AT91S_CAN_MB {
AT91_REG CAN_MB_MMR; // MailBox Mode Register
AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
AT91_REG CAN_MB_MID; // MailBox ID Register
AT91_REG CAN_MB_MFID; // MailBox Family ID Register
AT91_REG CAN_MB_MSR; // MailBox Status Register
AT91_REG CAN_MB_MDL; // MailBox Data Low Register
AT91_REG CAN_MB_MDH; // MailBox Data High Register
AT91_REG CAN_MB_MCR; // MailBox Control Register
} AT91S_CAN_MB, *AT91PS_CAN_MB;
// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network Interface
// *****************************************************************************
typedef struct _AT91S_CAN {
AT91_REG CAN_MR; // Mode Register
AT91_REG CAN_IER; // Interrupt Enable Register
AT91_REG CAN_IDR; // Interrupt Disable Register
AT91_REG CAN_IMR; // Interrupt Mask Register
AT91_REG CAN_SR; // Status Register
AT91_REG CAN_BR; // Baudrate Register
AT91_REG CAN_TIM; // Timer Register
AT91_REG CAN_TIMESTP; // Time Stamp Register
AT91_REG CAN_ECR; // Error Counter Register
AT91_REG CAN_TCR; // Transfer Command Register
AT91_REG CAN_ACR; // Abort Command Register
AT91_REG Reserved0[52]; //
AT91_REG CAN_VR; // Version Register
AT91_REG Reserved1[64]; //
AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
} AT91S_CAN, *AT91PS_CAN;
// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
// *****************************************************************************
typedef struct _AT91S_EMAC {
AT91_REG EMAC_NCR; // Network Control Register
AT91_REG EMAC_NCFGR; // Network Configuration Register
AT91_REG EMAC_NSR; // Network Status Register
AT91_REG Reserved0[2]; //
AT91_REG EMAC_TSR; // Transmit Status Register
AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
AT91_REG EMAC_RSR; // Receive Status Register
AT91_REG EMAC_ISR; // Interrupt Status Register
AT91_REG EMAC_IER; // Interrupt Enable Register
AT91_REG EMAC_IDR; // Interrupt Disable Register
AT91_REG EMAC_IMR; // Interrupt Mask Register
AT91_REG EMAC_MAN; // PHY Maintenance Register
AT91_REG EMAC_PTR; // Pause Time Register
AT91_REG EMAC_PFR; // Pause Frames received Register
AT91_REG EMAC_FTO; // Frames Transmitted OK Register
AT91_REG EMAC_SCF; // Single Collision Frame Register
AT91_REG EMAC_MCF; // Multiple Collision Frame Register
AT91_REG EMAC_FRO; // Frames Received OK Register
AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
AT91_REG EMAC_ALE; // Alignment Error Register
AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
AT91_REG EMAC_LCOL; // Late Collision Register
AT91_REG EMAC_ECOL; // Excessive Collision Register
AT91_REG EMAC_TUND; // Transmit Underrun Error Register
AT91_REG EMAC_CSE; // Carrier Sense Error Register
AT91_REG EMAC_RRE; // Receive Ressource Error Register
AT91_REG EMAC_ROV; // Receive Overrun Errors Register
AT91_REG EMAC_RSE; // Receive Symbol Errors Register
AT91_REG EMAC_ELE; // Excessive Length Errors Register
AT91_REG EMAC_RJA; // Receive Jabbers Register
AT91_REG EMAC_USF; // Undersize Frames Register
AT91_REG EMAC_STE; // SQE Test Error Register
AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
AT91_REG EMAC_HRT; // Hash Address Top[63:32]
AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
AT91_REG EMAC_TID; // Type ID Checking Register
AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
AT91_REG EMAC_USRIO; // USER Input/Output Register
AT91_REG EMAC_WOL; // Wake On LAN Register
AT91_REG Reserved1[13]; //
AT91_REG EMAC_REV; // Revision Register
} AT91S_EMAC, *AT91PS_EMAC;
// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // ADC Control Register
AT91_REG ADC_MR; // ADC Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // ADC Channel Enable Register
AT91_REG ADC_CHDR; // ADC Channel Disable Register
AT91_REG ADC_CHSR; // ADC Channel Status Register
AT91_REG ADC_SR; // ADC Status Register
AT91_REG ADC_LCDR; // ADC Last Converted Data Register
AT91_REG ADC_IER; // ADC Interrupt Enable Register
AT91_REG ADC_IDR; // ADC Interrupt Disable Register
AT91_REG ADC_IMR; // ADC Interrupt Mask Register
AT91_REG ADC_CDR0; // ADC Channel Data Register 0
AT91_REG ADC_CDR1; // ADC Channel Data Register 1
AT91_REG ADC_CDR2; // ADC Channel Data Register 2
AT91_REG ADC_CDR3; // ADC Channel Data Register 3
AT91_REG ADC_CDR4; // ADC Channel Data Register 4
AT91_REG ADC_CDR5; // ADC Channel Data Register 5
AT91_REG ADC_CDR6; // ADC Channel Data Register 6
AT91_REG ADC_CDR7; // ADC Channel Data Register 7
AT91_REG Reserved1[44]; //
AT91_REG ADC_RPR; // Receive Pointer Register
AT91_REG ADC_RCR; // Receive Counter Register
AT91_REG ADC_TPR; // Transmit Pointer Register
AT91_REG ADC_TCR; // Transmit Counter Register
AT91_REG ADC_RNPR; // Receive Next Pointer Register
AT91_REG ADC_RNCR; // Receive Next Counter Register
AT91_REG ADC_TNPR; // Transmit Next Pointer Register
AT91_REG ADC_TNCR; // Transmit Next Counter Register
AT91_REG ADC_PTCR; // PDC Transfer Control Register
AT91_REG ADC_PTSR; // PDC Transfer Status Register
} AT91S_ADC, *AT91PS_ADC;
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Encryption Standard
// *****************************************************************************
typedef struct _AT91S_AES {
AT91_REG AES_CR; // Control Register
AT91_REG AES_MR; // Mode Register
AT91_REG Reserved0[2]; //
AT91_REG AES_IER; // Interrupt Enable Register
AT91_REG AES_IDR; // Interrupt Disable Register
AT91_REG AES_IMR; // Interrupt Mask Register
AT91_REG AES_ISR; // Interrupt Status Register
AT91_REG AES_KEYWxR[4]; // Key Word x Register
AT91_REG Reserved1[4]; //
AT91_REG AES_IDATAxR[4]; // Input Data x Register
AT91_REG AES_ODATAxR[4]; // Output Data x Register
AT91_REG AES_IVxR[4]; // Initialization Vector x Register
AT91_REG Reserved2[35]; //
AT91_REG AES_VR; // AES Version Register
AT91_REG AES_RPR; // Receive Pointer Register
AT91_REG AES_RCR; // Receive Counter Register
AT91_REG AES_TPR; // Transmit Pointer Register
AT91_REG AES_TCR; // Transmit Counter Register
AT91_REG AES_RNPR; // Receive Next Pointer Register
AT91_REG AES_RNCR; // Receive Next Counter Register
AT91_REG AES_TNPR; // Transmit Next Pointer Register
AT91_REG AES_TNCR; // Transmit Next Counter Register
AT91_REG AES_PTCR; // PDC Transfer Control Register
AT91_REG AES_PTSR; // PDC Transfer Status Register
} AT91S_AES, *AT91PS_AES;
// -------- AES_CR : (AES Offset: 0x0) Control Register --------
#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
// *****************************************************************************
typedef struct _AT91S_TDES {
AT91_REG TDES_CR; // Control Register
AT91_REG TDES_MR; // Mode Register
AT91_REG Reserved0[2]; //
AT91_REG TDES_IER; // Interrupt Enable Register
AT91_REG TDES_IDR; // Interrupt Disable Register
AT91_REG TDES_IMR; // Interrupt Mask Register
AT91_REG TDES_ISR; // Interrupt Status Register
AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
AT91_REG Reserved1[2]; //
AT91_REG TDES_IDATAxR[2]; // Input Data x Register
AT91_REG Reserved2[2]; //
AT91_REG TDES_ODATAxR[2]; // Output Data x Register
AT91_REG Reserved3[2]; //
AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
AT91_REG Reserved4[37]; //
AT91_REG TDES_VR; // TDES Version Register
AT91_REG TDES_RPR; // Receive Pointer Register
AT91_REG TDES_RCR; // Receive Counter Register
AT91_REG TDES_TPR; // Transmit Pointer Register
AT91_REG TDES_TCR; // Transmit Counter Register
AT91_REG TDES_RNPR; // Receive Next Pointer Register
AT91_REG TDES_RNCR; // Receive Next Counter Register
AT91_REG TDES_TNPR; // Transmit Next Pointer Register
AT91_REG TDES_TNCR; // Transmit Next Counter Register
AT91_REG TDES_PTCR; // PDC Transfer Control Register
AT91_REG TDES_PTSR; // PDC Transfer Status Register
} AT91S_TDES, *AT91PS_TDES;
// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
// *****************************************************************************
// ========== Register definition for SYS peripheral ==========
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
// ========== Register definition for VREG peripheral ==========
#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
// ========== Register definition for MC peripheral ==========
#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
// ========== Register definition for PDC_SPI1 peripheral ==========
#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
// ========== Register definition for SPI1 peripheral ==========
#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
// ========== Register definition for PDC_SPI0 peripheral ==========
#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
// ========== Register definition for SPI0 peripheral ==========
#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
// ========== Register definition for PDC_SSC peripheral ==========
#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
// ========== Register definition for SSC peripheral ==========
#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
// ========== Register definition for TWI peripheral ==========
#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
// ========== Register definition for PWMC_CH3 peripheral ==========
#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
// ========== Register definition for PWMC_CH2 peripheral ==========
#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH1 peripheral ==========
#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
// ========== Register definition for PWMC_CH0 peripheral ==========
#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
// ========== Register definition for PWMC peripheral ==========
#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// ========== Register definition for TCB peripheral ==========
#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
// ========== Register definition for CAN_MB0 peripheral ==========
#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
// ========== Register definition for CAN_MB1 peripheral ==========
#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
// ========== Register definition for CAN_MB2 peripheral ==========
#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
// ========== Register definition for CAN_MB3 peripheral ==========
#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
// ========== Register definition for CAN_MB4 peripheral ==========
#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB5 peripheral ==========
#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
// ========== Register definition for CAN_MB6 peripheral ==========
#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
// ========== Register definition for CAN_MB7 peripheral ==========
#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
// ========== Register definition for CAN peripheral ==========
#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
// ========== Register definition for EMAC peripheral ==========
#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
// ========== Register definition for PDC_AES peripheral ==========
#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
// ========== Register definition for AES peripheral ==========
#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
// ========== Register definition for PDC_TDES peripheral ==========
#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
// ========== Register definition for TDES peripheral ==========
#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
// *****************************************************************************
#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h | C | oos | 207,994 |
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name : AT91SAM7S64.h
// Object : AT91SAM7S64 definitions
// Generated : AT91 SW Application Group 07/16/2004 (07:43:08)
//
// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002//
// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002//
// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003//
// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
// ----------------------------------------------------------------------------
#ifndef AT91SAM7S64_H
#define AT91SAM7S64_H
typedef volatile unsigned int AT91_REG;// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
typedef struct _AT91S_SYSC {
AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register
AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register
AT91_REG SYSC_AIC_IVR; // IRQ Vector Register
AT91_REG SYSC_AIC_FVR; // FIQ Vector Register
AT91_REG SYSC_AIC_ISR; // Interrupt Status Register
AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register
AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register
AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register
AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register
AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register
AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register
AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register
AT91_REG SYSC_AIC_SPU; // Spurious Vector Register
AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register
AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register
AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved2[45]; //
AT91_REG SYSC_DBGU_CR; // Control Register
AT91_REG SYSC_DBGU_MR; // Mode Register
AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register
AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register
AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register
AT91_REG SYSC_DBGU_CSR; // Channel Status Register
AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register
AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register
AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved3[7]; //
AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register
AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register
AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved4[45]; //
AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register
AT91_REG SYSC_DBGU_RCR; // Receive Counter Register
AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register
AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register
AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register
AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register
AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register
AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register
AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved5[54]; //
AT91_REG SYSC_PIOA_PER; // PIO Enable Register
AT91_REG SYSC_PIOA_PDR; // PIO Disable Register
AT91_REG SYSC_PIOA_PSR; // PIO Status Register
AT91_REG Reserved6[1]; //
AT91_REG SYSC_PIOA_OER; // Output Enable Register
AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr
AT91_REG SYSC_PIOA_OSR; // Output Status Register
AT91_REG Reserved7[1]; //
AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register
AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register
AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved8[1]; //
AT91_REG SYSC_PIOA_SODR; // Set Output Data Register
AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register
AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register
AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register
AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register
AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register
AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register
AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register
AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register
AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register
AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved9[1]; //
AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register
AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register
AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register
AT91_REG Reserved10[1]; //
AT91_REG SYSC_PIOA_ASR; // Select A Register
AT91_REG SYSC_PIOA_BSR; // Select B Register
AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved11[9]; //
AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register
AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register
AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved12[469]; //
AT91_REG SYSC_PMC_SCER; // System Clock Enable Register
AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register
AT91_REG SYSC_PMC_SCSR; // System Clock Status Register
AT91_REG Reserved13[1]; //
AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register
AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved14[1]; //
AT91_REG SYSC_PMC_MOR; // Main Oscillator Register
AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved15[1]; //
AT91_REG SYSC_PMC_PLLR; // PLL Register
AT91_REG SYSC_PMC_MCKR; // Master Clock Register
AT91_REG Reserved16[3]; //
AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register
AT91_REG SYSC_PMC_IER; // Interrupt Enable Register
AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register
AT91_REG SYSC_PMC_SR; // Status Register
AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved17[36]; //
AT91_REG SYSC_RSTC_RCR; // Reset Control Register
AT91_REG SYSC_RSTC_RSR; // Reset Status Register
AT91_REG SYSC_RSTC_RMR; // Reset Mode Register
AT91_REG Reserved18[5]; //
AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register
AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register
AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register
AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register
AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register
AT91_REG SYSC_PITC_PISR; // Period Interval Status Register
AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register
AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register
AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register
AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register
AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved19[5]; //
AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register
} AT91S_SYSC, *AT91PS_SYSC;
// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register --------
#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_C1R; // Chip ID1 Register
AT91_REG DBGU_C2R; // Chip ID2 Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral Data Controller
// *****************************************************************************
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
AT91_REG PDC_RNPR; // Receive Next Pointer Register
AT91_REG PDC_RNCR; // Receive Next Counter Register
AT91_REG PDC_TNPR; // Transmit Next Pointer Register
AT91_REG PDC_TNCR; // Transmit Next Counter Register
AT91_REG PDC_PTCR; // PDC Transfer Control Register
AT91_REG PDC_PTSR; // PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pad Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG Reserved0[1]; //
AT91_REG CKGR_PLLR; // PLL Register
} AT91S_CKGR, *AT91PS_CKGR;
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG Reserved2[1]; //
AT91_REG PMC_PLLR; // PLL Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved3[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
typedef struct _AT91S_RSTC {
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;
// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset
#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status
#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset.
#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved0[21]; //
AT91_REG MC_FMR; // MC Flash Mode Register
AT91_REG MC_FCR; // MC Flash Command Register
AT91_REG MC_FSR; // MC Flash Status Register
} AT91S_MC, *AT91PS_MC;
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
// *****************************************************************************
typedef struct _AT91S_SPI {
AT91_REG SPI_CR; // Control Register
AT91_REG SPI_MR; // Mode Register
AT91_REG SPI_RDR; // Receive Data Register
AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG Reserved0[4]; //
AT91_REG SPI_CSR[4]; // Chip Select Register
AT91_REG Reserved1[48]; //
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_RNPR; // Receive Next Pointer Register
AT91_REG SPI_RNCR; // Receive Next Counter Register
AT91_REG SPI_TNPR; // Transmit Next Pointer Register
AT91_REG SPI_TNCR; // Transmit Next Counter Register
AT91_REG SPI_PTCR; // PDC Transfer Control Register
AT91_REG SPI_PTSR; // PDC Transfer Status Register
} AT91S_SPI, *AT91PS_SPI;
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer
#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // ADC Control Register
AT91_REG ADC_MR; // ADC Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // ADC Channel Enable Register
AT91_REG ADC_CHDR; // ADC Channel Disable Register
AT91_REG ADC_CHSR; // ADC Channel Status Register
AT91_REG ADC_SR; // ADC Status Register
AT91_REG ADC_LCDR; // ADC Last Converted Data Register
AT91_REG ADC_IER; // ADC Interrupt Enable Register
AT91_REG ADC_IDR; // ADC Interrupt Disable Register
AT91_REG ADC_IMR; // ADC Interrupt Mask Register
AT91_REG ADC_CDR0; // ADC Channel Data Register 0
AT91_REG ADC_CDR1; // ADC Channel Data Register 1
AT91_REG ADC_CDR2; // ADC Channel Data Register 2
AT91_REG ADC_CDR3; // ADC Channel Data Register 3
AT91_REG ADC_CDR4; // ADC Channel Data Register 4
AT91_REG ADC_CDR5; // ADC Channel Data Register 5
AT91_REG ADC_CDR6; // ADC Channel Data Register 6
AT91_REG ADC_CDR7; // ADC Channel Data Register 7
AT91_REG Reserved1[44]; //
AT91_REG ADC_RPR; // Receive Pointer Register
AT91_REG ADC_RCR; // Receive Counter Register
AT91_REG ADC_TPR; // Transmit Pointer Register
AT91_REG ADC_TCR; // Transmit Counter Register
AT91_REG ADC_RNPR; // Receive Next Pointer Register
AT91_REG ADC_RNCR; // Receive Next Counter Register
AT91_REG ADC_TNPR; // Transmit Next Pointer Register
AT91_REG ADC_TNCR; // Transmit Next Counter Register
AT91_REG ADC_PTCR; // PDC Transfer Control Register
AT91_REG ADC_PTSR; // PDC Transfer Status Register
} AT91S_ADC, *AT91PS_ADC;
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
// *****************************************************************************
typedef struct _AT91S_SSC {
AT91_REG SSC_CR; // Control Register
AT91_REG SSC_CMR; // Clock Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SSC_RCMR; // Receive Clock ModeRegister
AT91_REG SSC_RFMR; // Receive Frame Mode Register
AT91_REG SSC_TCMR; // Transmit Clock Mode Register
AT91_REG SSC_TFMR; // Transmit Frame Mode Register
AT91_REG SSC_RHR; // Receive Holding Register
AT91_REG SSC_THR; // Transmit Holding Register
AT91_REG Reserved1[2]; //
AT91_REG SSC_RSHR; // Receive Sync Holding Register
AT91_REG SSC_TSHR; // Transmit Sync Holding Register
AT91_REG SSC_RC0R; // Receive Compare 0 Register
AT91_REG SSC_RC1R; // Receive Compare 1 Register
AT91_REG SSC_SR; // Status Register
AT91_REG SSC_IER; // Interrupt Enable Register
AT91_REG SSC_IDR; // Interrupt Disable Register
AT91_REG SSC_IMR; // Interrupt Mask Register
AT91_REG Reserved2[44]; //
AT91_REG SSC_RPR; // Receive Pointer Register
AT91_REG SSC_RCR; // Receive Counter Register
AT91_REG SSC_TPR; // Transmit Pointer Register
AT91_REG SSC_TCR; // Transmit Counter Register
AT91_REG SSC_RNPR; // Receive Next Pointer Register
AT91_REG SSC_RNCR; // Receive Next Counter Register
AT91_REG SSC_TNPR; // Transmit Next Pointer Register
AT91_REG SSC_TNCR; // Transmit Next Counter Register
AT91_REG SSC_PTCR; // PDC Transfer Control Register
AT91_REG SSC_PTSR; // PDC Transfer Status Register
} AT91S_SSC, *AT91PS_SSC;
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[5]; //
AT91_REG US_FIDI; // FI_DI_Ratio Register
AT91_REG US_NER; // Nb Errors Register
AT91_REG US_XXR; // XON_XOFF Register
AT91_REG US_IF; // IRDA_FILTER Register
AT91_REG Reserved1[44]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
AT91_REG US_RNPR; // Receive Next Pointer Register
AT91_REG US_RNCR; // Receive Next Counter Register
AT91_REG US_TNPR; // Transmit Next Pointer Register
AT91_REG US_TNCR; // Transmit Next Counter Register
AT91_REG US_PTCR; // PDC Transfer Control Register
AT91_REG US_PTSR; // PDC Transfer Status Register
} AT91S_USART, *AT91PS_USART;
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; // Control Register
AT91_REG TWI_MMR; // Master Mode Register
AT91_REG TWI_SMR; // Slave Mode Register
AT91_REG TWI_IADR; // Internal Address Register
AT91_REG TWI_CWGR; // Clock Waveform Generator Register
AT91_REG Reserved0[3]; //
AT91_REG TWI_SR; // Status Register
AT91_REG TWI_IER; // Interrupt Enable Register
AT91_REG TWI_IDR; // Interrupt Disable Register
AT91_REG TWI_IMR; // Interrupt Mask Register
AT91_REG TWI_RHR; // Receive Holding Register
AT91_REG TWI_THR; // Transmit Holding Register
} AT91S_TWI, *AT91PS_TWI;
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled
#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled
#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read
#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access
#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access
#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger
#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR PWMC Channel Interface
// *****************************************************************************
typedef struct _AT91S_PWMC_CH {
AT91_REG PWMC_CMR; // Channel Mode Register
AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
AT91_REG PWMC_CPRDR; // Channel Period Register
AT91_REG PWMC_CCNTR; // Channel Counter Register
AT91_REG PWMC_CUPDR; // Channel Update Register
AT91_REG PWMC_Reserved[3]; // Reserved
} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
// *****************************************************************************
typedef struct _AT91S_PWMC {
AT91_REG PWMC_MR; // PWMC Mode Register
AT91_REG PWMC_ENA; // PWMC Enable Register
AT91_REG PWMC_DIS; // PWMC Disable Register
AT91_REG PWMC_SR; // PWMC Status Register
AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
AT91_REG Reserved0[55]; //
AT91_REG PWMC_VR; // PWMC Version Register
AT91_REG Reserved1[64]; //
AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0
} AT91S_PWMC, *AT91PS_PWMC;
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4
#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5
#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6
#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7
// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR USB Device Interface
// *****************************************************************************
typedef struct _AT91S_UDP {
AT91_REG UDP_NUM; // Frame Number Register
AT91_REG UDP_GLBSTATE; // Global State Register
AT91_REG UDP_FADDR; // Function Address Register
AT91_REG Reserved0[1]; //
AT91_REG UDP_IER; // Interrupt Enable Register
AT91_REG UDP_IDR; // Interrupt Disable Register
AT91_REG UDP_IMR; // Interrupt Mask Register
AT91_REG UDP_ISR; // Interrupt Status Register
AT91_REG UDP_ICR; // Interrupt Clear Register
AT91_REG Reserved1[1]; //
AT91_REG UDP_RSTEP; // Reset Endpoint Register
AT91_REG Reserved2[1]; //
AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register
AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register
} AT91S_UDP, *AT91PS_UDP;
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable
#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt
#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt
#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6
#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
// *****************************************************************************
// ========== Register definition for SYSC peripheral ==========
#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
// ========== Register definition for DBGU peripheral ==========
#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register
#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register
#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register
#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
// ========== Register definition for CKGR peripheral ==========
#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
// ========== Register definition for PMC peripheral ==========
#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
// ========== Register definition for RSTC peripheral ==========
#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
// ========== Register definition for RTTC peripheral ==========
#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
// ========== Register definition for PITC peripheral ==========
#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
// ========== Register definition for MC peripheral ==========
#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
// ========== Register definition for PDC_SPI peripheral ==========
#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
// ========== Register definition for SPI peripheral ==========
#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
// ========== Register definition for PDC_ADC peripheral ==========
#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
// ========== Register definition for ADC peripheral ==========
#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
// ========== Register definition for PDC_SSC peripheral ==========
#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
// ========== Register definition for SSC peripheral ==========
#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register
#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register
#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register
#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register
#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
// ========== Register definition for TWI peripheral ==========
#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register
#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
// ========== Register definition for TCB peripheral ==========
#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
// ========== Register definition for PWMC_CH3 peripheral ==========
#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH2 peripheral ==========
#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH1 peripheral ==========
#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH0 peripheral ==========
#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
// ========== Register definition for PWMC peripheral ==========
#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
// ========== Register definition for UDP peripheral ==========
#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0
#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1
#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data
#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0
#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave
#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1
#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave
#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2
#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock
#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3
#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync
#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock
#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data
#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data
#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock
#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input
#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2
#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync
#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0
#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data
#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1
#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data
#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock
#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0
#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send
#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1
#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send
#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2
#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect
#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready
#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready
#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input
#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator
#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input
#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data
#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1
#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31
#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2
#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock
#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input
#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data
#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data
#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send
#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3
#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send
#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger
#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data
#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller
#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved
#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter
#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface
#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
// *****************************************************************************
#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
#endif
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h | C | oos | 146,215 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the Atmel ARM7 port.
*----------------------------------------------------------*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Constants required to setup the initial stack. */
#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
/* Constants required to setup the PIT. */
#define portPIT_CLOCK_DIVISOR ( ( unsigned long ) 16 )
#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )
/* Constants required to handle critical sections. */
#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
#define portINT_LEVEL_SENSITIVE 0
#define portPIT_ENABLE ( ( unsigned short ) 0x1 << 24 )
#define portPIT_INT_ENABLE ( ( unsigned short ) 0x1 << 25 )
/*-----------------------------------------------------------*/
/* Setup the PIT to generate the tick interrupts. */
static void prvSetupTimerInterrupt( void );
/* ulCriticalNesting will get set to zero when the first task starts. It
cannot be initialised to 0 as this will cause interrupts to be enabled
during the kernel initialisation process. */
unsigned long ulCriticalNesting = ( unsigned long ) 9999;
/*-----------------------------------------------------------*/
/*
* Initialise the stack of a task to look exactly as if a call to
* portSAVE_CONTEXT had been called.
*
* See header file for description.
*/
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
portSTACK_TYPE *pxOriginalTOS;
pxOriginalTOS = pxTopOfStack;
/* To ensure asserts in tasks.c don't fail, although in this case the assert
is not really required. */
pxTopOfStack--;
/* Setup the initial stack of the task. The stack is set exactly as
expected by the portRESTORE_CONTEXT() macro. */
/* First on the stack is the return address - which in this case is the
start of the task. The offset is added to make the return address appear
as it would within an IRQ ISR. */
*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
pxTopOfStack--;
/* When the task starts is will expect to find the function parameter in
R0. */
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
pxTopOfStack--;
/* The status register is set for system mode, with interrupts enabled. */
*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00UL )
{
/* We want the task to start in thumb mode. */
*pxTopOfStack |= portTHUMB_MODE_BIT;
}
pxTopOfStack--;
/* Interrupt flags cannot always be stored on the stack and will
instead be stored in a variable, which is then saved as part of the
tasks context. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
prvSetupTimerInterrupt();
/* Start the first task. */
vPortStartFirstTask();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* It is unlikely that the ARM port will require this function as there
is nothing to return to. */
}
/*-----------------------------------------------------------*/
#if configUSE_PREEMPTION == 0
/* The cooperative scheduler requires a normal IRQ service routine to
simply increment the system tick. */
static __arm __irq void vPortNonPreemptiveTick( void );
static __arm __irq void vPortNonPreemptiveTick( void )
{
unsigned long ulDummy;
/* Increment the tick count - which may wake some tasks but as the
preemptive scheduler is not being used any woken task is not given
processor time no matter what its priority. */
vTaskIncrementTick();
/* Clear the PIT interrupt. */
ulDummy = AT91C_BASE_PITC->PITC_PIVR;
/* End the interrupt in the AIC. */
AT91C_BASE_AIC->AIC_EOICR = ulDummy;
}
#else
/* Currently the IAR port requires the preemptive tick function to be
defined in an asm file. */
#endif
/*-----------------------------------------------------------*/
static void prvSetupTimerInterrupt( void )
{
AT91PS_PITC pxPIT = AT91C_BASE_PITC;
/* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
on whether the preemptive or cooperative scheduler is being used. */
#if configUSE_PREEMPTION == 0
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );
#else
extern void ( vPortPreemptiveTick )( void );
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );
#endif
/* Configure the PIT period. */
pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
/* Enable the interrupt. Global interrupts are disables at this point so
this is safe. */
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
/* Disable interrupts first! */
__disable_interrupt();
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as we are leaving a critical section. */
ulCriticalNesting--;
/* If the nesting level has reached zero then interrupts should be
re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
__enable_interrupt();
}
}
}
/*-----------------------------------------------------------*/
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/port.c | C | oos | 10,595 |
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : lib_AT91SAM7S64.h
//* Object : AT91SAM7S64 inlined functions
//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09)
//*
//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//
//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//
//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//
//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//
//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//
//*----------------------------------------------------------------------------
#ifndef lib_AT91SAM7S64_H
#define lib_AT91SAM7S64_H
/* *****************************************************************************
SOFTWARE API FOR MC
***************************************************************************** */
#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_Remap
//* \brief Make Remap
//*----------------------------------------------------------------------------
__inline void AT91F_MC_Remap (void) //
{
AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
pMC->MC_RCR = AT91C_MC_RCB;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_EFC_CfgModeReg
//* \brief Configure the EFC Mode Register of the MC controller
//*----------------------------------------------------------------------------
__inline void AT91F_MC_EFC_CfgModeReg (
AT91PS_MC pMC, // pointer to a MC controller
unsigned int mode) // mode register
{
// Write to the FMR register
pMC->MC_FMR = mode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_EFC_GetModeReg
//* \brief Return MC EFC Mode Regsiter
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_MC_EFC_GetModeReg(
AT91PS_MC pMC) // pointer to a MC controller
{
return pMC->MC_FMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_EFC_ComputeFMCN
//* \brief Return MC EFC Mode Regsiter
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
int master_clock) // master clock in Hz
{
return (master_clock/1000000 +2);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_EFC_PerformCmd
//* \brief Perform EFC Command
//*----------------------------------------------------------------------------
__inline void AT91F_MC_EFC_PerformCmd (
AT91PS_MC pMC, // pointer to a MC controller
unsigned int transfer_cmd)
{
pMC->MC_FCR = transfer_cmd;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_EFC_GetStatus
//* \brief Return MC EFC Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_MC_EFC_GetStatus(
AT91PS_MC pMC) // pointer to a MC controller
{
return pMC->MC_FSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_EFC_IsInterruptMasked
//* \brief Test if EFC MC Interrupt is Masked
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
AT91PS_MC pMC, // \arg pointer to a MC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_EFC_IsInterruptSet
//* \brief Test if EFC MC Interrupt is Set
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
AT91PS_MC pMC, // \arg pointer to a MC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_MC_EFC_GetStatus(pMC) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR PDC
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_SetNextRx
//* \brief Set the next receive transfer descriptor
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_SetNextRx (
AT91PS_PDC pPDC, // \arg pointer to a PDC controller
char *address, // \arg address to the next bloc to be received
unsigned int bytes) // \arg number of bytes to be received
{
pPDC->PDC_RNPR = (unsigned int) address;
pPDC->PDC_RNCR = bytes;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_SetNextTx
//* \brief Set the next transmit transfer descriptor
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_SetNextTx (
AT91PS_PDC pPDC, // \arg pointer to a PDC controller
char *address, // \arg address to the next bloc to be transmitted
unsigned int bytes) // \arg number of bytes to be transmitted
{
pPDC->PDC_TNPR = (unsigned int) address;
pPDC->PDC_TNCR = bytes;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_SetRx
//* \brief Set the receive transfer descriptor
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_SetRx (
AT91PS_PDC pPDC, // \arg pointer to a PDC controller
char *address, // \arg address to the next bloc to be received
unsigned int bytes) // \arg number of bytes to be received
{
pPDC->PDC_RPR = (unsigned int) address;
pPDC->PDC_RCR = bytes;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_SetTx
//* \brief Set the transmit transfer descriptor
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_SetTx (
AT91PS_PDC pPDC, // \arg pointer to a PDC controller
char *address, // \arg address to the next bloc to be transmitted
unsigned int bytes) // \arg number of bytes to be transmitted
{
pPDC->PDC_TPR = (unsigned int) address;
pPDC->PDC_TCR = bytes;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_EnableTx
//* \brief Enable transmit
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_EnableTx (
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_EnableRx
//* \brief Enable receive
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_EnableRx (
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_DisableTx
//* \brief Disable transmit
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_DisableTx (
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_DisableRx
//* \brief Disable receive
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_DisableRx (
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_IsTxEmpty
//* \brief Test if the current transfer descriptor has been sent
//*----------------------------------------------------------------------------
__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
return !(pPDC->PDC_TCR);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_IsNextTxEmpty
//* \brief Test if the next transfer descriptor has been moved to the current td
//*----------------------------------------------------------------------------
__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
return !(pPDC->PDC_TNCR);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_IsRxEmpty
//* \brief Test if the current transfer descriptor has been filled
//*----------------------------------------------------------------------------
__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
return !(pPDC->PDC_RCR);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_IsNextRxEmpty
//* \brief Test if the next transfer descriptor has been moved to the current td
//*----------------------------------------------------------------------------
__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
{
return !(pPDC->PDC_RNCR);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_Open
//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_Open (
AT91PS_PDC pPDC) // \arg pointer to a PDC controller
{
//* Disable the RX and TX PDC transfer requests
AT91F_PDC_DisableRx(pPDC);
AT91F_PDC_DisableTx(pPDC);
//* Reset all Counter register Next buffer first
AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
//* Enable the RX and TX PDC transfer requests
AT91F_PDC_EnableRx(pPDC);
AT91F_PDC_EnableTx(pPDC);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_Close
//* \brief Close PDC: disable TX and RX reset transfer descriptors
//*----------------------------------------------------------------------------
__inline void AT91F_PDC_Close (
AT91PS_PDC pPDC) // \arg pointer to a PDC controller
{
//* Disable the RX and TX PDC transfer requests
AT91F_PDC_DisableRx(pPDC);
AT91F_PDC_DisableTx(pPDC);
//* Reset all Counter register Next buffer first
AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_SendFrame
//* \brief Close PDC: disable TX and RX reset transfer descriptors
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PDC_SendFrame(
AT91PS_PDC pPDC,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
if (AT91F_PDC_IsTxEmpty(pPDC)) {
//* Buffer and next buffer can be initialized
AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
return 2;
}
else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
//* Only one buffer can be initialized
AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
return 1;
}
else {
//* All buffer are in use...
return 0;
}
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PDC_ReceiveFrame
//* \brief Close PDC: disable TX and RX reset transfer descriptors
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PDC_ReceiveFrame (
AT91PS_PDC pPDC,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
if (AT91F_PDC_IsRxEmpty(pPDC)) {
//* Buffer and next buffer can be initialized
AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
return 2;
}
else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
//* Only one buffer can be initialized
AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
return 1;
}
else {
//* All buffer are in use...
return 0;
}
}
/* *****************************************************************************
SOFTWARE API FOR DBGU
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_InterruptEnable
//* \brief Enable DBGU Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_DBGU_InterruptEnable(
AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
unsigned int flag) // \arg dbgu interrupt to be enabled
{
pDbgu->DBGU_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_InterruptDisable
//* \brief Disable DBGU Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_DBGU_InterruptDisable(
AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
unsigned int flag) // \arg dbgu interrupt to be disabled
{
pDbgu->DBGU_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_GetInterruptMaskStatus
//* \brief Return DBGU Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
{
return pDbgu->DBGU_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_IsInterruptMasked
//* \brief Test if DBGU Interrupt is Masked
//*----------------------------------------------------------------------------
__inline int AT91F_DBGU_IsInterruptMasked(
AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR SSC
***************************************************************************** */
//* Define the standard I2S mode configuration
//* Configuration to set in the SSC Transmit Clock Mode Register
//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
//* nb_slot_by_frame : number of channels
#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
AT91C_SSC_CKS_DIV +\
AT91C_SSC_CKO_CONTINOUS +\
AT91C_SSC_CKG_NONE +\
AT91C_SSC_START_FALL_RF +\
AT91C_SSC_STTOUT +\
((1<<16) & AT91C_SSC_STTDLY) +\
((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
//* Configuration to set in the SSC Transmit Frame Mode Register
//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
//* nb_slot_by_frame : number of channels
#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
(nb_bit_by_slot-1) +\
AT91C_SSC_MSBF +\
(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
AT91C_SSC_FSOS_NEGATIVE)
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_SetBaudrate
//* \brief Set the baudrate according to the CPU clock
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_SetBaudrate (
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
unsigned int mainClock, // \arg peripheral clock
unsigned int speed) // \arg SSC baudrate
{
unsigned int baud_value;
//* Define the baud rate divisor register
if (speed == 0)
baud_value = 0;
else
{
baud_value = (unsigned int) (mainClock * 10)/(2*speed);
if ((baud_value % 10) >= 5)
baud_value = (baud_value / 10) + 1;
else
baud_value /= 10;
}
pSSC->SSC_CMR = baud_value;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_Configure
//* \brief Configure SSC
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_Configure (
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
unsigned int syst_clock, // \arg System Clock Frequency
unsigned int baud_rate, // \arg Expected Baud Rate Frequency
unsigned int clock_rx, // \arg Receiver Clock Parameters
unsigned int mode_rx, // \arg mode Register to be programmed
unsigned int clock_tx, // \arg Transmitter Clock Parameters
unsigned int mode_tx) // \arg mode Register to be programmed
{
//* Disable interrupts
pSSC->SSC_IDR = (unsigned int) -1;
//* Reset receiver and transmitter
pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
//* Define the Clock Mode Register
AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
//* Write the Receive Clock Mode Register
pSSC->SSC_RCMR = clock_rx;
//* Write the Transmit Clock Mode Register
pSSC->SSC_TCMR = clock_tx;
//* Write the Receive Frame Mode Register
pSSC->SSC_RFMR = mode_rx;
//* Write the Transmit Frame Mode Register
pSSC->SSC_TFMR = mode_tx;
//* Clear Transmit and Receive Counters
AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_EnableRx
//* \brief Enable receiving datas
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_EnableRx (
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
//* Enable receiver
pSSC->SSC_CR = AT91C_SSC_RXEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_DisableRx
//* \brief Disable receiving datas
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_DisableRx (
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
//* Disable receiver
pSSC->SSC_CR = AT91C_SSC_RXDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_EnableTx
//* \brief Enable sending datas
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_EnableTx (
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
//* Enable transmitter
pSSC->SSC_CR = AT91C_SSC_TXEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_DisableTx
//* \brief Disable sending datas
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_DisableTx (
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
{
//* Disable transmitter
pSSC->SSC_CR = AT91C_SSC_TXDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_EnableIt
//* \brief Enable SSC IT
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_EnableIt (
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
unsigned int flag) // \arg IT to be enabled
{
//* Write to the IER register
pSSC->SSC_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_DisableIt
//* \brief Disable SSC IT
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_DisableIt (
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
unsigned int flag) // \arg IT to be disabled
{
//* Write to the IDR register
pSSC->SSC_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_ReceiveFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_SSC_ReceiveFrame (
AT91PS_SSC pSSC,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
return AT91F_PDC_ReceiveFrame(
(AT91PS_PDC) &(pSSC->SSC_RPR),
pBuffer,
szBuffer,
pNextBuffer,
szNextBuffer);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_SendFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_SSC_SendFrame(
AT91PS_SSC pSSC,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
return AT91F_PDC_SendFrame(
(AT91PS_PDC) &(pSSC->SSC_RPR),
pBuffer,
szBuffer,
pNextBuffer,
szNextBuffer);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_GetInterruptMaskStatus
//* \brief Return SSC Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
AT91PS_SSC pSsc) // \arg pointer to a SSC controller
{
return pSsc->SSC_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_IsInterruptMasked
//* \brief Test if SSC Interrupt is Masked
//*----------------------------------------------------------------------------
__inline int AT91F_SSC_IsInterruptMasked(
AT91PS_SSC pSsc, // \arg pointer to a SSC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR SPI
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_Open
//* \brief Open a SPI Port
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_SPI_Open (
const unsigned int null) // \arg
{
/* NOT DEFINED AT THIS MOMENT */
return ( 0 );
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_CfgCs
//* \brief Configure SPI chip select register
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_CfgCs (
AT91PS_SPI pSPI, // pointer to a SPI controller
int cs, // SPI cs number (0 to 3)
int val) // chip select register
{
//* Write to the CSR register
*(pSPI->SPI_CSR + cs) = val;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_EnableIt
//* \brief Enable SPI interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_EnableIt (
AT91PS_SPI pSPI, // pointer to a SPI controller
unsigned int flag) // IT to be enabled
{
//* Write to the IER register
pSPI->SPI_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_DisableIt
//* \brief Disable SPI interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_DisableIt (
AT91PS_SPI pSPI, // pointer to a SPI controller
unsigned int flag) // IT to be disabled
{
//* Write to the IDR register
pSPI->SPI_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_Reset
//* \brief Reset the SPI controller
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_Reset (
AT91PS_SPI pSPI // pointer to a SPI controller
)
{
//* Write to the CR register
pSPI->SPI_CR = AT91C_SPI_SWRST;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_Enable
//* \brief Enable the SPI controller
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_Enable (
AT91PS_SPI pSPI // pointer to a SPI controller
)
{
//* Write to the CR register
pSPI->SPI_CR = AT91C_SPI_SPIEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_Disable
//* \brief Disable the SPI controller
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_Disable (
AT91PS_SPI pSPI // pointer to a SPI controller
)
{
//* Write to the CR register
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_CfgMode
//* \brief Enable the SPI controller
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_CfgMode (
AT91PS_SPI pSPI, // pointer to a SPI controller
int mode) // mode register
{
//* Write to the MR register
pSPI->SPI_MR = mode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_CfgPCS
//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_CfgPCS (
AT91PS_SPI pSPI, // pointer to a SPI controller
char PCS_Device) // PCS of the Device
{
//* Write to the MR register
pSPI->SPI_MR &= 0xFFF0FFFF;
pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_ReceiveFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_SPI_ReceiveFrame (
AT91PS_SPI pSPI,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
return AT91F_PDC_ReceiveFrame(
(AT91PS_PDC) &(pSPI->SPI_RPR),
pBuffer,
szBuffer,
pNextBuffer,
szNextBuffer);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_SendFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_SPI_SendFrame(
AT91PS_SPI pSPI,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
return AT91F_PDC_SendFrame(
(AT91PS_PDC) &(pSPI->SPI_RPR),
pBuffer,
szBuffer,
pNextBuffer,
szNextBuffer);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_Close
//* \brief Close SPI: disable IT disable transfert, close PDC
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_Close (
AT91PS_SPI pSPI) // \arg pointer to a SPI controller
{
//* Reset all the Chip Select register
pSPI->SPI_CSR[0] = 0 ;
pSPI->SPI_CSR[1] = 0 ;
pSPI->SPI_CSR[2] = 0 ;
pSPI->SPI_CSR[3] = 0 ;
//* Reset the SPI mode
pSPI->SPI_MR = 0 ;
//* Disable all interrupts
pSPI->SPI_IDR = 0xFFFFFFFF ;
//* Abort the Peripheral Data Transfers
AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
//* Disable receiver and transmitter and stop any activity immediately
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_PutChar
//* \brief Send a character,does not check if ready to send
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_PutChar (
AT91PS_SPI pSPI,
unsigned int character,
unsigned int cs_number )
{
unsigned int value_for_cs;
value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_GetChar
//* \brief Receive a character,does not check if a character is available
//*----------------------------------------------------------------------------
__inline int AT91F_SPI_GetChar (
const AT91PS_SPI pSPI)
{
return((pSPI->SPI_RDR) & 0xFFFF);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_GetInterruptMaskStatus
//* \brief Return SPI Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
AT91PS_SPI pSpi) // \arg pointer to a SPI controller
{
return pSpi->SPI_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_IsInterruptMasked
//* \brief Test if SPI Interrupt is Masked
//*----------------------------------------------------------------------------
__inline int AT91F_SPI_IsInterruptMasked(
AT91PS_SPI pSpi, // \arg pointer to a SPI controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR PWMC
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_GetStatus
//* \brief Return PWM Interrupt Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
AT91PS_PWMC pPWM) // pointer to a PWM controller
{
return pPWM->PWMC_SR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_InterruptEnable
//* \brief Enable PWM Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_InterruptEnable(
AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
unsigned int flag) // \arg PWM interrupt to be enabled
{
pPwm->PWMC_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_InterruptDisable
//* \brief Disable PWM Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_InterruptDisable(
AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
unsigned int flag) // \arg PWM interrupt to be disabled
{
pPwm->PWMC_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_GetInterruptMaskStatus
//* \brief Return PWM Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
{
return pPwm->PWMC_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_IsInterruptMasked
//* \brief Test if PWM Interrupt is Masked
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PWMC_IsInterruptMasked(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_IsStatusSet
//* \brief Test if PWM Interrupt is Set
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PWMC_IsStatusSet(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PWMC_GetStatus(pPWM) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_CfgChannel
//* \brief Test if PWM Interrupt is Set
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_CfgChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int channelId, // \arg PWM channel ID
unsigned int mode, // \arg PWM mode
unsigned int period, // \arg PWM period
unsigned int duty) // \arg PWM duty cycle
{
pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_StartChannel
//* \brief Enable channel
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_StartChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg Channels IDs to be enabled
{
pPWM->PWMC_ENA = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_StopChannel
//* \brief Disable channel
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_StopChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int flag) // \arg Channels IDs to be enabled
{
pPWM->PWMC_DIS = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWM_UpdateChannel
//* \brief Update Period or Duty Cycle
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_UpdateChannel(
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
unsigned int channelId, // \arg PWM channel ID
unsigned int update) // \arg Channels IDs to be enabled
{
pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
}
/* *****************************************************************************
SOFTWARE API FOR TC
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_TC_InterruptEnable
//* \brief Enable TC Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_TC_InterruptEnable(
AT91PS_TC pTc, // \arg pointer to a TC controller
unsigned int flag) // \arg TC interrupt to be enabled
{
pTc->TC_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC_InterruptDisable
//* \brief Disable TC Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_TC_InterruptDisable(
AT91PS_TC pTc, // \arg pointer to a TC controller
unsigned int flag) // \arg TC interrupt to be disabled
{
pTc->TC_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC_GetInterruptMaskStatus
//* \brief Return TC Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
AT91PS_TC pTc) // \arg pointer to a TC controller
{
return pTc->TC_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC_IsInterruptMasked
//* \brief Test if TC Interrupt is Masked
//*----------------------------------------------------------------------------
__inline int AT91F_TC_IsInterruptMasked(
AT91PS_TC pTc, // \arg pointer to a TC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR PMC
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_CfgSysClkEnableReg
//* \brief Configure the System Clock Enable Register of the PMC controller
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgSysClkEnableReg (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int mode)
{
//* Write to the SCER register
pPMC->PMC_SCER = mode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_CfgSysClkDisableReg
//* \brief Configure the System Clock Disable Register of the PMC controller
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgSysClkDisableReg (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int mode)
{
//* Write to the SCDR register
pPMC->PMC_SCDR = mode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_GetSysClkStatusReg
//* \brief Return the System Clock Status Register of the PMC controller
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
AT91PS_PMC pPMC // pointer to a CAN controller
)
{
return pPMC->PMC_SCSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_EnablePeriphClock
//* \brief Enable peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_EnablePeriphClock (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int periphIds) // \arg IDs of peripherals to enable
{
pPMC->PMC_PCER = periphIds;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_DisablePeriphClock
//* \brief Disable peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_DisablePeriphClock (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int periphIds) // \arg IDs of peripherals to enable
{
pPMC->PMC_PCDR = periphIds;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_GetPeriphClock
//* \brief Get peripheral clock status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetPeriphClock (
AT91PS_PMC pPMC) // \arg pointer to PMC controller
{
return pPMC->PMC_PCSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_CKGR_CfgMainOscillatorReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgMainOscillatorReg (
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
unsigned int mode)
{
pCKGR->CKGR_MOR = mode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_CKGR_GetMainOscillatorReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
return pCKGR->CKGR_MOR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_CKGR_EnableMainOscillator
//* \brief Enable the main oscillator
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_EnableMainOscillator(
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_CKGR_DisableMainOscillator
//* \brief Disable the main oscillator
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_DisableMainOscillator (
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_CKGR_CfgMainOscStartUpTime
//* \brief Cfg MOR Register according to the main osc startup time
//*----------------------------------------------------------------------------
__inline void AT91F_CKGR_CfgMainOscStartUpTime (
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
unsigned int startup_time, // \arg main osc startup time in microsecond (us)
unsigned int slowClock) // \arg slowClock in Hz
{
pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_CKGR_GetMainClockFreqReg
//* \brief Cfg the main oscillator
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
{
return pCKGR->CKGR_MCFR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_CKGR_GetMainClock
//* \brief Return Main clock in Hz
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_CKGR_GetMainClock (
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
unsigned int slowClock) // \arg slowClock in Hz
{
return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_CfgMCKReg
//* \brief Cfg Master Clock Register
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgMCKReg (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int mode)
{
pPMC->PMC_MCKR = mode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_GetMCKReg
//* \brief Return Master Clock Register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetMCKReg(
AT91PS_PMC pPMC) // \arg pointer to PMC controller
{
return pPMC->PMC_MCKR;
}
//*------------------------------------------------------------------------------
//* \fn AT91F_PMC_GetMasterClock
//* \brief Return master clock in Hz which correponds to processor clock for ARM7
//*------------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetMasterClock (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
unsigned int slowClock) // \arg slowClock in Hz
{
unsigned int reg = pPMC->PMC_MCKR;
unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
unsigned int pllDivider, pllMultiplier;
switch (reg & AT91C_PMC_CSS) {
case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
return slowClock / prescaler;
case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
reg = pCKGR->CKGR_PLLR;
pllDivider = (reg & AT91C_CKGR_DIV);
pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
}
return 0;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_EnablePCK
//* \brief Enable peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_EnablePCK (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
unsigned int mode)
{
pPMC->PMC_PCKR[pck] = mode;
pPMC->PMC_SCER = (1 << pck) << 8;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_DisablePCK
//* \brief Enable peripheral clock
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_DisablePCK (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
{
pPMC->PMC_SCDR = (1 << pck) << 8;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_EnableIt
//* \brief Enable PMC interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_EnableIt (
AT91PS_PMC pPMC, // pointer to a PMC controller
unsigned int flag) // IT to be enabled
{
//* Write to the IER register
pPMC->PMC_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_DisableIt
//* \brief Disable PMC interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_DisableIt (
AT91PS_PMC pPMC, // pointer to a PMC controller
unsigned int flag) // IT to be disabled
{
//* Write to the IDR register
pPMC->PMC_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_GetStatus
//* \brief Return PMC Interrupt Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
AT91PS_PMC pPMC) // pointer to a PMC controller
{
return pPMC->PMC_SR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_GetInterruptMaskStatus
//* \brief Return PMC Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
AT91PS_PMC pPMC) // pointer to a PMC controller
{
return pPMC->PMC_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_IsInterruptMasked
//* \brief Test if PMC Interrupt is Masked
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_IsInterruptMasked(
AT91PS_PMC pPMC, // \arg pointer to a PMC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_IsStatusSet
//* \brief Test if PMC Status is Set
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PMC_IsStatusSet(
AT91PS_PMC pPMC, // \arg pointer to a PMC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PMC_GetStatus(pPMC) & flag);
}/* *****************************************************************************
SOFTWARE API FOR ADC
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_EnableIt
//* \brief Enable ADC interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_EnableIt (
AT91PS_ADC pADC, // pointer to a ADC controller
unsigned int flag) // IT to be enabled
{
//* Write to the IER register
pADC->ADC_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_DisableIt
//* \brief Disable ADC interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_DisableIt (
AT91PS_ADC pADC, // pointer to a ADC controller
unsigned int flag) // IT to be disabled
{
//* Write to the IDR register
pADC->ADC_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetStatus
//* \brief Return ADC Interrupt Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
AT91PS_ADC pADC) // pointer to a ADC controller
{
return pADC->ADC_SR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetInterruptMaskStatus
//* \brief Return ADC Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
AT91PS_ADC pADC) // pointer to a ADC controller
{
return pADC->ADC_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_IsInterruptMasked
//* \brief Test if ADC Interrupt is Masked
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_IsInterruptMasked(
AT91PS_ADC pADC, // \arg pointer to a ADC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_IsStatusSet
//* \brief Test if ADC Status is Set
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_IsStatusSet(
AT91PS_ADC pADC, // \arg pointer to a ADC controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_ADC_GetStatus(pADC) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_CfgModeReg
//* \brief Configure the Mode Register of the ADC controller
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_CfgModeReg (
AT91PS_ADC pADC, // pointer to a ADC controller
unsigned int mode) // mode register
{
//* Write to the MR register
pADC->ADC_MR = mode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetModeReg
//* \brief Return the Mode Register of the ADC controller value
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetModeReg (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_MR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_CfgTimings
//* \brief Configure the different necessary timings of the ADC controller
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_CfgTimings (
AT91PS_ADC pADC, // pointer to a ADC controller
unsigned int mck_clock, // in MHz
unsigned int adc_clock, // in MHz
unsigned int startup_time, // in us
unsigned int sample_and_hold_time) // in ns
{
unsigned int prescal,startup,shtim;
prescal = mck_clock/(2*adc_clock) - 1;
startup = adc_clock*startup_time/8 - 1;
shtim = adc_clock*sample_and_hold_time/1000 - 1;
//* Write to the MR register
pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_EnableChannel
//* \brief Return ADC Timer Register Value
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_EnableChannel (
AT91PS_ADC pADC, // pointer to a ADC controller
unsigned int channel) // mode register
{
//* Write to the CHER register
pADC->ADC_CHER = channel;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_DisableChannel
//* \brief Return ADC Timer Register Value
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_DisableChannel (
AT91PS_ADC pADC, // pointer to a ADC controller
unsigned int channel) // mode register
{
//* Write to the CHDR register
pADC->ADC_CHDR = channel;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetChannelStatus
//* \brief Return ADC Timer Register Value
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetChannelStatus (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CHSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_StartConversion
//* \brief Software request for a analog to digital conversion
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_StartConversion (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
pADC->ADC_CR = AT91C_ADC_START;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_SoftReset
//* \brief Software reset
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_SoftReset (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
pADC->ADC_CR = AT91C_ADC_SWRST;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetLastConvertedData
//* \brief Return the Last Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetLastConvertedData (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_LCDR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH0
//* \brief Return the Channel 0 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR0;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH1
//* \brief Return the Channel 1 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR1;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH2
//* \brief Return the Channel 2 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR2;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH3
//* \brief Return the Channel 3 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR3;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH4
//* \brief Return the Channel 4 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR4;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH5
//* \brief Return the Channel 5 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR5;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH6
//* \brief Return the Channel 6 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR6;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_GetConvertedDataCH7
//* \brief Return the Channel 7 Converted Data
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
AT91PS_ADC pADC // pointer to a ADC controller
)
{
return pADC->ADC_CDR7;
}
/* *****************************************************************************
SOFTWARE API FOR PIO
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgPeriph
//* \brief Enable pins to be drived by peripheral
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgPeriph(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int periphAEnable, // \arg PERIPH A to enable
unsigned int periphBEnable) // \arg PERIPH B to enable
{
pPio->PIO_ASR = periphAEnable;
pPio->PIO_BSR = periphBEnable;
pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgOutput
//* \brief Enable PIO in output mode
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int pioEnable) // \arg PIO to be enabled
{
pPio->PIO_PER = pioEnable; // Set in PIO mode
pPio->PIO_OER = pioEnable; // Configure in Output
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgInput
//* \brief Enable PIO in input mode
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgInput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int inputEnable) // \arg PIO to be enabled
{
// Disable output
pPio->PIO_ODR = inputEnable;
pPio->PIO_PER = inputEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgOpendrain
//* \brief Configure PIO in open drain
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgOpendrain(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int multiDrvEnable) // \arg pio to be configured in open drain
{
// Configure the multi-drive option
pPio->PIO_MDDR = ~multiDrvEnable;
pPio->PIO_MDER = multiDrvEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgPullup
//* \brief Enable pullup on PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgPullup(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int pullupEnable) // \arg enable pullup on PIO
{
// Connect or not Pullup
pPio->PIO_PPUDR = ~pullupEnable;
pPio->PIO_PPUER = pullupEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgDirectDrive
//* \brief Enable direct drive on PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgDirectDrive(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int directDrive) // \arg PIO to be configured with direct drive
{
// Configure the Direct Drive
pPio->PIO_OWDR = ~directDrive;
pPio->PIO_OWER = directDrive;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgInputFilter
//* \brief Enable input filter on input PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgInputFilter(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int inputFilter) // \arg PIO to be configured with input filter
{
// Configure the Direct Drive
pPio->PIO_IFDR = ~inputFilter;
pPio->PIO_IFER = inputFilter;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetInput
//* \brief Return PIO input value
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_PDSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsInputSet
//* \brief Test if PIO is input flag is active
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsInputSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetInput(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_SetOutput
//* \brief Set to 1 output PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_SetOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg output to be set
{
pPio->PIO_SODR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_ClearOutput
//* \brief Set to 0 output PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_ClearOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg output to be cleared
{
pPio->PIO_CODR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_ForceOutput
//* \brief Force output when Direct drive option is enabled
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_ForceOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg output to be forced
{
pPio->PIO_ODSR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_Enable
//* \brief Enable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_Enable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio to be enabled
{
pPio->PIO_PER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_Disable
//* \brief Disable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_Disable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio to be disabled
{
pPio->PIO_PDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetStatus
//* \brief Return PIO Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_PSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsSet
//* \brief Test if PIO is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_OutputEnable
//* \brief Output Enable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_OutputEnable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio output to be enabled
{
pPio->PIO_OER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_OutputDisable
//* \brief Output Enable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_OutputDisable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio output to be disabled
{
pPio->PIO_ODR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetOutputStatus
//* \brief Return PIO Output Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_OSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsOuputSet
//* \brief Test if PIO Output is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsOutputSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetOutputStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_InputFilterEnable
//* \brief Input Filter Enable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_InputFilterEnable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio input filter to be enabled
{
pPio->PIO_IFER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_InputFilterDisable
//* \brief Input Filter Disable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_InputFilterDisable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio input filter to be disabled
{
pPio->PIO_IFDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetInputFilterStatus
//* \brief Return PIO Input Filter Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_IFSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsInputFilterSet
//* \brief Test if PIO Input filter is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsInputFilterSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetOutputDataStatus
//* \brief Return PIO Output Data Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_ODSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_InterruptEnable
//* \brief Enable PIO Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_InterruptEnable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio interrupt to be enabled
{
pPio->PIO_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_InterruptDisable
//* \brief Disable PIO Interrupt
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_InterruptDisable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio interrupt to be disabled
{
pPio->PIO_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetInterruptMaskStatus
//* \brief Return PIO Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetInterruptStatus
//* \brief Return PIO Interrupt Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_ISR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsInterruptMasked
//* \brief Test if PIO Interrupt is Masked
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsInterruptMasked(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsInterruptSet
//* \brief Test if PIO Interrupt is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsInterruptSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_MultiDriverEnable
//* \brief Multi Driver Enable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_MultiDriverEnable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio to be enabled
{
pPio->PIO_MDER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_MultiDriverDisable
//* \brief Multi Driver Disable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_MultiDriverDisable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio to be disabled
{
pPio->PIO_MDDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetMultiDriverStatus
//* \brief Return PIO Multi Driver Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_MDSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsMultiDriverSet
//* \brief Test if PIO MultiDriver is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsMultiDriverSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_A_RegisterSelection
//* \brief PIO A Register Selection
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_A_RegisterSelection(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio A register selection
{
pPio->PIO_ASR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_B_RegisterSelection
//* \brief PIO B Register Selection
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_B_RegisterSelection(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio B register selection
{
pPio->PIO_BSR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_Get_AB_RegisterStatus
//* \brief Return PIO Interrupt Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_ABSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsAB_RegisterSet
//* \brief Test if PIO AB Register is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsAB_RegisterSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_OutputWriteEnable
//* \brief Output Write Enable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_OutputWriteEnable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio output write to be enabled
{
pPio->PIO_OWER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_OutputWriteDisable
//* \brief Output Write Disable PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_OutputWriteDisable(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg pio output write to be disabled
{
pPio->PIO_OWDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetOutputWriteStatus
//* \brief Return PIO Output Write Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_OWSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsOutputWriteSet
//* \brief Test if PIO OutputWrite is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsOutputWriteSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetCfgPullup
//* \brief Return PIO Configuration Pullup
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_PPUSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsOutputDataStatusSet
//* \brief Test if PIO Output Data Status is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsOutputDataStatusSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsCfgPullupStatusSet
//* \brief Test if PIO Configuration Pullup Status is Set
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsCfgPullupStatusSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR TWI
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_EnableIt
//* \brief Enable TWI IT
//*----------------------------------------------------------------------------
__inline void AT91F_TWI_EnableIt (
AT91PS_TWI pTWI, // \arg pointer to a TWI controller
unsigned int flag) // \arg IT to be enabled
{
//* Write to the IER register
pTWI->TWI_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_DisableIt
//* \brief Disable TWI IT
//*----------------------------------------------------------------------------
__inline void AT91F_TWI_DisableIt (
AT91PS_TWI pTWI, // \arg pointer to a TWI controller
unsigned int flag) // \arg IT to be disabled
{
//* Write to the IDR register
pTWI->TWI_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_Configure
//* \brief Configure TWI in master mode
//*----------------------------------------------------------------------------
__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
{
//* Disable interrupts
pTWI->TWI_IDR = (unsigned int) -1;
//* Reset peripheral
pTWI->TWI_CR = AT91C_TWI_SWRST;
//* Set Master mode
pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_GetInterruptMaskStatus
//* \brief Return TWI Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
AT91PS_TWI pTwi) // \arg pointer to a TWI controller
{
return pTwi->TWI_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_IsInterruptMasked
//* \brief Test if TWI Interrupt is Masked
//*----------------------------------------------------------------------------
__inline int AT91F_TWI_IsInterruptMasked(
AT91PS_TWI pTwi, // \arg pointer to a TWI controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR USART
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_US_Baudrate
//* \brief Calculate the baudrate
//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
AT91C_US_NBSTOP_1_BIT + \
AT91C_US_PAR_NONE + \
AT91C_US_CHRL_8_BITS + \
AT91C_US_CLKS_CLOCK )
//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
AT91C_US_NBSTOP_1_BIT + \
AT91C_US_PAR_NONE + \
AT91C_US_CHRL_8_BITS + \
AT91C_US_CLKS_EXT )
//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
AT91C_US_USMODE_NORMAL + \
AT91C_US_NBSTOP_1_BIT + \
AT91C_US_PAR_NONE + \
AT91C_US_CHRL_8_BITS + \
AT91C_US_CLKS_CLOCK )
//* SCK used Label
#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
AT91C_US_CLKS_CLOCK +\
AT91C_US_NBSTOP_1_BIT + \
AT91C_US_PAR_EVEN + \
AT91C_US_CHRL_8_BITS + \
AT91C_US_CKLO +\
AT91C_US_OVER)
//* Standard IRDA mode
#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
AT91C_US_NBSTOP_1_BIT + \
AT91C_US_PAR_NONE + \
AT91C_US_CHRL_8_BITS + \
AT91C_US_CLKS_CLOCK )
//*----------------------------------------------------------------------------
//* \fn AT91F_US_Baudrate
//* \brief Caluculate baud_value according to the main clock and the baud rate
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_Baudrate (
const unsigned int main_clock, // \arg peripheral clock
const unsigned int baud_rate) // \arg UART baudrate
{
unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
if ((baud_value % 10) >= 5)
baud_value = (baud_value / 10) + 1;
else
baud_value /= 10;
return baud_value;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_SetBaudrate
//* \brief Set the baudrate according to the CPU clock
//*----------------------------------------------------------------------------
__inline void AT91F_US_SetBaudrate (
AT91PS_USART pUSART, // \arg pointer to a USART controller
unsigned int mainClock, // \arg peripheral clock
unsigned int speed) // \arg UART baudrate
{
//* Define the baud rate divisor register
pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_SetTimeguard
//* \brief Set USART timeguard
//*----------------------------------------------------------------------------
__inline void AT91F_US_SetTimeguard (
AT91PS_USART pUSART, // \arg pointer to a USART controller
unsigned int timeguard) // \arg timeguard value
{
//* Write the Timeguard Register
pUSART->US_TTGR = timeguard ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_EnableIt
//* \brief Enable USART IT
//*----------------------------------------------------------------------------
__inline void AT91F_US_EnableIt (
AT91PS_USART pUSART, // \arg pointer to a USART controller
unsigned int flag) // \arg IT to be enabled
{
//* Write to the IER register
pUSART->US_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_DisableIt
//* \brief Disable USART IT
//*----------------------------------------------------------------------------
__inline void AT91F_US_DisableIt (
AT91PS_USART pUSART, // \arg pointer to a USART controller
unsigned int flag) // \arg IT to be disabled
{
//* Write to the IER register
pUSART->US_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_Configure
//* \brief Configure USART
//*----------------------------------------------------------------------------
__inline void AT91F_US_Configure (
AT91PS_USART pUSART, // \arg pointer to a USART controller
unsigned int mainClock, // \arg peripheral clock
unsigned int mode , // \arg mode Register to be programmed
unsigned int baudRate , // \arg baudrate to be programmed
unsigned int timeguard ) // \arg timeguard to be programmed
{
//* Disable interrupts
pUSART->US_IDR = (unsigned int) -1;
//* Reset receiver and transmitter
pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
//* Define the baud rate divisor register
AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
//* Write the Timeguard Register
AT91F_US_SetTimeguard(pUSART, timeguard);
//* Clear Transmit and Receive Counters
AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
//* Define the USART mode
pUSART->US_MR = mode ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_EnableRx
//* \brief Enable receiving characters
//*----------------------------------------------------------------------------
__inline void AT91F_US_EnableRx (
AT91PS_USART pUSART) // \arg pointer to a USART controller
{
//* Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_EnableTx
//* \brief Enable sending characters
//*----------------------------------------------------------------------------
__inline void AT91F_US_EnableTx (
AT91PS_USART pUSART) // \arg pointer to a USART controller
{
//* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_ResetRx
//* \brief Reset Receiver and re-enable it
//*----------------------------------------------------------------------------
__inline void AT91F_US_ResetRx (
AT91PS_USART pUSART) // \arg pointer to a USART controller
{
//* Reset receiver
pUSART->US_CR = AT91C_US_RSTRX;
//* Re-Enable receiver
pUSART->US_CR = AT91C_US_RXEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_ResetTx
//* \brief Reset Transmitter and re-enable it
//*----------------------------------------------------------------------------
__inline void AT91F_US_ResetTx (
AT91PS_USART pUSART) // \arg pointer to a USART controller
{
//* Reset transmitter
pUSART->US_CR = AT91C_US_RSTTX;
//* Enable transmitter
pUSART->US_CR = AT91C_US_TXEN;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_DisableRx
//* \brief Disable Receiver
//*----------------------------------------------------------------------------
__inline void AT91F_US_DisableRx (
AT91PS_USART pUSART) // \arg pointer to a USART controller
{
//* Disable receiver
pUSART->US_CR = AT91C_US_RXDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_DisableTx
//* \brief Disable Transmitter
//*----------------------------------------------------------------------------
__inline void AT91F_US_DisableTx (
AT91PS_USART pUSART) // \arg pointer to a USART controller
{
//* Disable transmitter
pUSART->US_CR = AT91C_US_TXDIS;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_Close
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
//*----------------------------------------------------------------------------
__inline void AT91F_US_Close (
AT91PS_USART pUSART) // \arg pointer to a USART controller
{
//* Reset the baud rate divisor register
pUSART->US_BRGR = 0 ;
//* Reset the USART mode
pUSART->US_MR = 0 ;
//* Reset the Timeguard Register
pUSART->US_TTGR = 0;
//* Disable all interrupts
pUSART->US_IDR = 0xFFFFFFFF ;
//* Abort the Peripheral Data Transfers
AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
//* Disable receiver and transmitter and stop any activity immediately
pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_TxReady
//* \brief Return 1 if a character can be written in US_THR
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_TxReady (
AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
return (pUSART->US_CSR & AT91C_US_TXRDY);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_RxReady
//* \brief Return 1 if a character can be read in US_RHR
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_RxReady (
AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
return (pUSART->US_CSR & AT91C_US_RXRDY);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_Error
//* \brief Return the error flag
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_Error (
AT91PS_USART pUSART ) // \arg pointer to a USART controller
{
return (pUSART->US_CSR &
(AT91C_US_OVRE | // Overrun error
AT91C_US_FRAME | // Framing error
AT91C_US_PARE)); // Parity error
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_PutChar
//* \brief Send a character,does not check if ready to send
//*----------------------------------------------------------------------------
__inline void AT91F_US_PutChar (
AT91PS_USART pUSART,
int character )
{
pUSART->US_THR = (character & 0x1FF);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_GetChar
//* \brief Receive a character,does not check if a character is available
//*----------------------------------------------------------------------------
__inline int AT91F_US_GetChar (
const AT91PS_USART pUSART)
{
return((pUSART->US_RHR) & 0x1FF);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_SendFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_SendFrame(
AT91PS_USART pUSART,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
return AT91F_PDC_SendFrame(
(AT91PS_PDC) &(pUSART->US_RPR),
pBuffer,
szBuffer,
pNextBuffer,
szNextBuffer);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_ReceiveFrame
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_ReceiveFrame (
AT91PS_USART pUSART,
char *pBuffer,
unsigned int szBuffer,
char *pNextBuffer,
unsigned int szNextBuffer )
{
return AT91F_PDC_ReceiveFrame(
(AT91PS_PDC) &(pUSART->US_RPR),
pBuffer,
szBuffer,
pNextBuffer,
szNextBuffer);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_SetIrdaFilter
//* \brief Set the value of IrDa filter tregister
//*----------------------------------------------------------------------------
__inline void AT91F_US_SetIrdaFilter (
AT91PS_USART pUSART,
unsigned char value
)
{
pUSART->US_IF = value;
}
/* *****************************************************************************
SOFTWARE API FOR UDP
***************************************************************************** */
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EnableIt
//* \brief Enable UDP IT
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_EnableIt (
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned int flag) // \arg IT to be enabled
{
//* Write to the IER register
pUDP->UDP_IER = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_DisableIt
//* \brief Disable UDP IT
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_DisableIt (
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned int flag) // \arg IT to be disabled
{
//* Write to the IDR register
pUDP->UDP_IDR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_SetAddress
//* \brief Set UDP functional address
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_SetAddress (
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char address) // \arg new UDP address
{
pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EnableEp
//* \brief Enable Endpoint
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_EnableEp (
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned int flag) // \arg endpoints to be enabled
{
pUDP->UDP_GLBSTATE |= flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_DisableEp
//* \brief Enable Endpoint
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_DisableEp (
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned int flag) // \arg endpoints to be enabled
{
pUDP->UDP_GLBSTATE &= ~(flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_SetState
//* \brief Set UDP Device state
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_SetState (
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned int flag) // \arg new UDP address
{
pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
pUDP->UDP_GLBSTATE |= flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_GetState
//* \brief return UDP Device state
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
AT91PS_UDP pUDP) // \arg pointer to a UDP controller
{
return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_ResetEp
//* \brief Reset UDP endpoint
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned int flag) // \arg Endpoints to be reset
{
pUDP->UDP_RSTEP = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EpStall
//* \brief Endpoint will STALL requests
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_EpStall(
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char endpoint) // \arg endpoint number
{
pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EpWrite
//* \brief Write value in the DPR
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_EpWrite(
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char endpoint, // \arg endpoint number
unsigned char value) // \arg value to be written in the DPR
{
pUDP->UDP_FDR[endpoint] = value;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EpRead
//* \brief Return value from the DPR
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_UDP_EpRead(
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char endpoint) // \arg endpoint number
{
return pUDP->UDP_FDR[endpoint];
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EpEndOfWr
//* \brief Notify the UDP that values in DPR are ready to be sent
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_EpEndOfWr(
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char endpoint) // \arg endpoint number
{
pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EpClear
//* \brief Clear flag in the endpoint CSR register
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_EpClear(
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char endpoint, // \arg endpoint number
unsigned int flag) // \arg flag to be cleared
{
pUDP->UDP_CSR[endpoint] &= ~(flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EpSet
//* \brief Set flag in the endpoint CSR register
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_EpSet(
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char endpoint, // \arg endpoint number
unsigned int flag) // \arg flag to be cleared
{
pUDP->UDP_CSR[endpoint] |= flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_EpStatus
//* \brief Return the endpoint CSR register
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_UDP_EpStatus(
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
unsigned char endpoint) // \arg endpoint number
{
return pUDP->UDP_CSR[endpoint];
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_GetInterruptMaskStatus
//* \brief Return UDP Interrupt Mask Status
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
AT91PS_UDP pUdp) // \arg pointer to a UDP controller
{
return pUdp->UDP_IMR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_IsInterruptMasked
//* \brief Test if UDP Interrupt is Masked
//*----------------------------------------------------------------------------
__inline int AT91F_UDP_IsInterruptMasked(
AT91PS_UDP pUdp, // \arg pointer to a UDP controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
}
/* *****************************************************************************
SOFTWARE API FOR AIC
***************************************************************************** */
#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_ConfigureIt
//* \brief Interrupt Handler Initialization
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_ConfigureIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id, // \arg interrupt number to initialize
unsigned int priority, // \arg priority to give to the interrupt
unsigned int src_type, // \arg activation and sense of activation
void (*newHandler) (void) ) // \arg address of the interrupt handler
{
unsigned int oldHandler;
unsigned int mask ;
oldHandler = pAic->AIC_SVR[irq_id];
mask = 0x1 << irq_id ;
//* Disable the interrupt on the interrupt controller
pAic->AIC_IDCR = mask ;
//* Save the interrupt handler routine pointer and the interrupt priority
pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
//* Store the Source Mode Register
pAic->AIC_SMR[irq_id] = src_type | priority ;
//* Clear the interrupt on the interrupt controller
pAic->AIC_ICCR = mask ;
return oldHandler;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_EnableIt
//* \brief Enable corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_EnableIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id ) // \arg interrupt number to initialize
{
//* Enable the interrupt on the interrupt controller
pAic->AIC_IECR = 0x1 << irq_id ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_DisableIt
//* \brief Disable corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_DisableIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id ) // \arg interrupt number to initialize
{
unsigned int mask = 0x1 << irq_id;
//* Disable the interrupt on the interrupt controller
pAic->AIC_IDCR = mask ;
//* Clear the interrupt on the Interrupt Controller ( if one is pending )
pAic->AIC_ICCR = mask ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_ClearIt
//* \brief Clear corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_ClearIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg interrupt number to initialize
{
//* Clear the interrupt on the Interrupt Controller ( if one is pending )
pAic->AIC_ICCR = (0x1 << irq_id);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_AcknowledgeIt
//* \brief Acknowledge corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_AcknowledgeIt (
AT91PS_AIC pAic) // \arg pointer to the AIC registers
{
pAic->AIC_EOICR = pAic->AIC_EOICR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_SetExceptionVector
//* \brief Configure vector handler
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_SetExceptionVector (
unsigned int *pVector, // \arg pointer to the AIC registers
void (*Handler) () ) // \arg Interrupt Handler
{
unsigned int oldVector = *pVector;
if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
else
*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
return oldVector;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_Trig
//* \brief Trig an IT
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_Trig (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg interrupt number
{
pAic->AIC_ISCR = (0x1 << irq_id) ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_IsActive
//* \brief Test if an IT is active
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_IsActive (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg Interrupt Number
{
return (pAic->AIC_ISR & (0x1 << irq_id));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_IsPending
//* \brief Test if an IT is pending
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_IsPending (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg Interrupt Number
{
return (pAic->AIC_IPR & (0x1 << irq_id));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_Open
//* \brief Set exception vectors and AIC registers to default values
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_Open(
AT91PS_AIC pAic, // \arg pointer to the AIC registers
void (*IrqHandler) (), // \arg Default IRQ vector exception
void (*FiqHandler) (), // \arg Default FIQ vector exception
void (*DefaultHandler) (), // \arg Default Handler set in ISR
void (*SpuriousHandler) (), // \arg Default Spurious Handler
unsigned int protectMode) // \arg Debug Control Register
{
int i;
// Disable all interrupts and set IVR to the default handler
for (i = 0; i < 32; ++i) {
AT91F_AIC_DisableIt(pAic, i);
AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
}
// Set the IRQ exception vector
AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
// Set the Fast Interrupt exception vector
AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
pAic->AIC_SPU = (unsigned int) SpuriousHandler;
pAic->AIC_DCR = protectMode;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_MC_CfgPMC
//* \brief Enable Peripheral clock in PMC for MC
//*----------------------------------------------------------------------------
__inline void AT91F_MC_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SYS));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_CfgPMC
//* \brief Enable Peripheral clock in PMC for DBGU
//*----------------------------------------------------------------------------
__inline void AT91F_DBGU_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SYS));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_DBGU_CfgPIO
//* \brief Configure PIO controllers to drive DBGU signals
//*----------------------------------------------------------------------------
__inline void AT91F_DBGU_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA10_DTXD ) |
((unsigned int) AT91C_PA9_DRXD ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWMC_CH3_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH3 signals
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_CH3_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PA14_PWM3 ) |
((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWMC_CH2_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH2 signals
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_CH2_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A
((unsigned int) AT91C_PA25_PWM2 ) |
((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWMC_CH1_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_CH1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A
((unsigned int) AT91C_PA24_PWM1 ) |
((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWMC_CH0_CfgPIO
//* \brief Configure PIO controllers to drive PWMC_CH0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_CH0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A
((unsigned int) AT91C_PA23_PWM0 ) |
((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_CfgPMC
//* \brief Enable Peripheral clock in PMC for SSC
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SSC));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SSC_CfgPIO
//* \brief Configure PIO controllers to drive SSC signals
//*----------------------------------------------------------------------------
__inline void AT91F_SSC_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA17_TD ) |
((unsigned int) AT91C_PA15_TF ) |
((unsigned int) AT91C_PA19_RK ) |
((unsigned int) AT91C_PA18_RD ) |
((unsigned int) AT91C_PA20_RF ) |
((unsigned int) AT91C_PA16_TK ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_CfgPMC
//* \brief Enable Peripheral clock in PMC for SPI
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SPI));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_CfgPIO
//* \brief Configure PIO controllers to drive SPI signals
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA11_NPCS0 ) |
((unsigned int) AT91C_PA13_MOSI ) |
((unsigned int) AT91C_PA31_NPCS1 ) |
((unsigned int) AT91C_PA12_MISO ) |
((unsigned int) AT91C_PA14_SPCK ), // Peripheral A
((unsigned int) AT91C_PA9_NPCS1 ) |
((unsigned int) AT91C_PA30_NPCS2 ) |
((unsigned int) AT91C_PA10_NPCS2 ) |
((unsigned int) AT91C_PA22_NPCS3 ) |
((unsigned int) AT91C_PA3_NPCS3 ) |
((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PWMC_CfgPMC
//* \brief Enable Peripheral clock in PMC for PWMC
//*----------------------------------------------------------------------------
__inline void AT91F_PWMC_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_PWMC));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC2_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC2
//*----------------------------------------------------------------------------
__inline void AT91F_TC2_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC2));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC2_CfgPIO
//* \brief Configure PIO controllers to drive TC2 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC2_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PA26_TIOA2 ) |
((unsigned int) AT91C_PA27_TIOB2 ) |
((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC1_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC1
//*----------------------------------------------------------------------------
__inline void AT91F_TC1_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC1_CfgPIO
//* \brief Configure PIO controllers to drive TC1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PA15_TIOA1 ) |
((unsigned int) AT91C_PA16_TIOB1 ) |
((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC0_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC0
//*----------------------------------------------------------------------------
__inline void AT91F_TC0_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC0_CfgPIO
//* \brief Configure PIO controllers to drive TC0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PA0_TIOA0 ) |
((unsigned int) AT91C_PA1_TIOB0 ) |
((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_CfgPMC
//* \brief Enable Peripheral clock in PMC for PMC
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SYS));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PMC_CfgPIO
//* \brief Configure PIO controllers to drive PMC signals
//*----------------------------------------------------------------------------
__inline void AT91F_PMC_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PA17_PCK1 ) |
((unsigned int) AT91C_PA21_PCK1 ) |
((unsigned int) AT91C_PA31_PCK2 ) |
((unsigned int) AT91C_PA18_PCK2 ) |
((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_CfgPMC
//* \brief Enable Peripheral clock in PMC for ADC
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_ADC));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ADC_CfgPIO
//* \brief Configure PIO controllers to drive ADC signals
//*----------------------------------------------------------------------------
__inline void AT91F_ADC_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIOA_CfgPMC
//* \brief Enable Peripheral clock in PMC for PIOA
//*----------------------------------------------------------------------------
__inline void AT91F_PIOA_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_PIOA));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_CfgPMC
//* \brief Enable Peripheral clock in PMC for TWI
//*----------------------------------------------------------------------------
__inline void AT91F_TWI_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TWI));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_CfgPIO
//* \brief Configure PIO controllers to drive TWI signals
//*----------------------------------------------------------------------------
__inline void AT91F_TWI_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA3_TWD ) |
((unsigned int) AT91C_PA4_TWCK ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgPMC
//* \brief Enable Peripheral clock in PMC for US1
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgPIO
//* \brief Configure PIO controllers to drive US1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA21_RXD1 ) |
((unsigned int) AT91C_PA27_DTR1 ) |
((unsigned int) AT91C_PA26_DCD1 ) |
((unsigned int) AT91C_PA22_TXD1 ) |
((unsigned int) AT91C_PA24_RTS1 ) |
((unsigned int) AT91C_PA23_SCK1 ) |
((unsigned int) AT91C_PA28_DSR1 ) |
((unsigned int) AT91C_PA29_RI1 ) |
((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgPMC
//* \brief Enable Peripheral clock in PMC for US0
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgPIO
//* \brief Configure PIO controllers to drive US0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA5_RXD0 ) |
((unsigned int) AT91C_PA6_TXD0 ) |
((unsigned int) AT91C_PA7_RTS0 ) |
((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A
((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_CfgPMC
//* \brief Enable Peripheral clock in PMC for UDP
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_UDP));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgPMC
//* \brief Enable Peripheral clock in PMC for AIC
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_IRQ0) |
((unsigned int) 1 << AT91C_ID_FIQ) |
((unsigned int) 1 << AT91C_ID_IRQ1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgPIO
//* \brief Configure PIO controllers to drive AIC signals
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A
((unsigned int) AT91C_PA20_IRQ0 ) |
((unsigned int) AT91C_PA19_FIQ )); // Peripheral B
}
#endif // lib_AT91SAM7S64_H
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h | C | oos | 129,193 |
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned short
#define portBASE_TYPE short
#if (configUSE_16_BIT_TICKS==1)
typedef unsigned int portTickType;
#define portMAX_DELAY ( portTickType ) 0xffff
#else
typedef unsigned long portTickType;
#define portMAX_DELAY ( portTickType ) 0xffffffff
#endif
/*-----------------------------------------------------------*/
/* Interrupt control macros. */
#define portDISABLE_INTERRUPTS() __asm ( "DI" )
#define portENABLE_INTERRUPTS() __asm ( "EI" )
/*-----------------------------------------------------------*/
/* Critical section control macros. */
#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 )
#define portENTER_CRITICAL() \
{ \
extern volatile unsigned portSHORT usCriticalNesting; \
\
portDISABLE_INTERRUPTS(); \
\
/* Now interrupts are disabled ulCriticalNesting can be accessed */ \
/* directly. Increment ulCriticalNesting to keep a count of how many */ \
/* times portENTER_CRITICAL() has been called. */ \
usCriticalNesting++; \
}
#define portEXIT_CRITICAL() \
{ \
extern volatile unsigned portSHORT usCriticalNesting; \
\
if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
{ \
/* Decrement the nesting count as we are leaving a critical section. */ \
usCriticalNesting--; \
\
/* If the nesting level has reached zero then interrupts should be */ \
/* re-enabled. */ \
if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
{ \
portENABLE_INTERRUPTS(); \
} \
} \
}
/*-----------------------------------------------------------*/
/* Task utilities. */
extern void vPortStart( void );
#define portYIELD() __asm( "BRK" )
#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
#define portNOP() __asm( "NOP" )
/*-----------------------------------------------------------*/
/* Hardwware specifics. */
#define portBYTE_ALIGNMENT 2
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
static __interrupt void P0_isr (void);
/* --------------------------------------------------------------------------*/
/* Option-bytes and security ID */
/* --------------------------------------------------------------------------*/
#define OPT_BYTES_SIZE 4
#define SECU_ID_SIZE 10
#define WATCHDOG_DISABLED 0x00
#define LVI_ENABLED 0xFE
#define LVI_DISABLED 0xFF
#define RESERVED_FF 0xFF
#define OCD_DISABLED 0x04
#define OCD_ENABLED 0x81
#define OCD_ENABLED_ERASE 0x80
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
| zz314326255--adkping | iNEMO-accessory/firmware/FreeRTOSv7.0.2/Source/portable/IAR/78K0R/portmacro.h | C | oos | 6,880 |