Replace 46 unsound harnesses and correct 5 reference patches (#36)

- Replace 46 unsound harnesses and correct 5 reference patches (43e7d673208245162a324a06e0afe211952f575d)
- Drop calibration files and repair notes from the release (9d76f4578900bb6a79a4d824814af02ea86e2b2e)


Co-authored-by: Zanehpn <Zanehpn@users.noreply.huggingface.co>

DATA_MANIFEST.md

@@ -3,7 +3,7 @@
 Each case provides four aligned artifacts under a common root:
   testbench/<case>/   verilator differential testbench (run via run_once.sh / run_verilator.sh)
   snapshots/<case>/   pre-PR repository snapshot (RTL sources)
-  patches/<case>.patch the fix; testbench reverse-applies for buggy, applies for fixed
+  patches/<case>.patch the fix; each harness sets up the pre-fix tree for the buggy phase and applies this for the fixed phase
   issues/<case>       issue description
   testbench/_*        shared run helpers (sourced by per-case scripts)
 

Phoenix-Bench-croissant.json

@@ -5340,7 +5340,7 @@
           "instances/instance_id": "FPGA-MAFIA_fpga_mafia_pr499",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/FPGA-MAFIA_fpga_mafia_pr499",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/FPGA-MAFIA_fpga_mafia_pr499.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/FPGA-MAFIA_fpga_mafia_pr499"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/FPGA-MAFIA_fpga_mafia_pr499"
         },
         {
           "instances/instance_id": "FPGA-MAFIA_fpga_mafia_pr548",
@@ -5430,13 +5430,13 @@
           "instances/instance_id": "HiSA-Team_Simply-V_pr52",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr52",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr52.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr52"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/HiSA-Team_Simply-V_pr52"
         },
         {
           "instances/instance_id": "HiSA-Team_Simply-V_pr68",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/HiSA-Team_Simply-V_pr68",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/HiSA-Team_Simply-V_pr68.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/HiSA-Team_Simply-V_pr68"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/HiSA-Team_Simply-V_pr68"
         },
         {
           "instances/instance_id": "HiSA-Team_Simply-V_pr92",
@@ -5496,7 +5496,7 @@
           "instances/instance_id": "MiSTer-devel_Gameboy_MiSTer_pr24",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr24",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr24.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr24"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/MiSTer-devel_Gameboy_MiSTer_pr24"
         },
         {
           "instances/instance_id": "MiSTer-devel_Gameboy_MiSTer_pr240",
@@ -5514,7 +5514,7 @@
           "instances/instance_id": "MiSTer-devel_Gameboy_MiSTer_pr96",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/MiSTer-devel_Gameboy_MiSTer_pr96",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/MiSTer-devel_Gameboy_MiSTer_pr96.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/MiSTer-devel_Gameboy_MiSTer_pr96"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/MiSTer-devel_Gameboy_MiSTer_pr96"
         },
         {
           "instances/instance_id": "MiSTer-devel_Genesis_MiSTer_pr144",
@@ -5694,13 +5694,13 @@
           "instances/instance_id": "Panda-Cores_PandaZero_pr14",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr14",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr14.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr14"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/Panda-Cores_PandaZero_pr14"
         },
         {
           "instances/instance_id": "Panda-Cores_PandaZero_pr3",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/Panda-Cores_PandaZero_pr3",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/Panda-Cores_PandaZero_pr3.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/Panda-Cores_PandaZero_pr3"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/Panda-Cores_PandaZero_pr3"
         },
         {
           "instances/instance_id": "Panda-Cores_PandaZero_pr4",
@@ -5778,7 +5778,7 @@
           "instances/instance_id": "UTOSS_risc-v_pr115",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr115",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr115.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr115"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr115"
         },
         {
           "instances/instance_id": "UTOSS_risc-v_pr127",
@@ -5885,8 +5885,8 @@
         {
           "instances/instance_id": "UTOSS_risc-v_pr81",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr81",
-          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr81.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr81"
+          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/UTOSS_risc-v_pr81.patch",
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr81"
         },
         {
           "instances/instance_id": "UTOSS_risc-v_pr83",
@@ -5910,7 +5910,7 @@
           "instances/instance_id": "UTOSS_risc-v_pr97",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/UTOSS_risc-v_pr97",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/UTOSS_risc-v_pr97.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/UTOSS_risc-v_pr97"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/UTOSS_risc-v_pr97"
         },
         {
           "instances/instance_id": "Wren6991_Hazard3_pr23",
@@ -5964,7 +5964,7 @@
           "instances/instance_id": "alexforencich_verilog-pcie_pr19",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/alexforencich_verilog-pcie_pr19",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/alexforencich_verilog-pcie_pr19.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/alexforencich_verilog-pcie_pr19"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/alexforencich_verilog-pcie_pr19"
         },
         {
           "instances/instance_id": "alexforencich_verilog-pcie_pr20",
@@ -6078,7 +6078,7 @@
           "instances/instance_id": "bensampson5_libsv_pr150",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bensampson5_libsv_pr150",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bensampson5_libsv_pr150.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bensampson5_libsv_pr150"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/bensampson5_libsv_pr150"
         },
         {
           "instances/instance_id": "bensampson5_libsv_pr153",
@@ -6174,7 +6174,7 @@
           "instances/instance_id": "bespoke-silicon-group_basejump_stl_pr675",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/bespoke-silicon-group_basejump_stl_pr675",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/bespoke-silicon-group_basejump_stl_pr675.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/bespoke-silicon-group_basejump_stl_pr675"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/bespoke-silicon-group_basejump_stl_pr675"
         },
         {
           "instances/instance_id": "bespoke-silicon-group_basejump_stl_pr676",
@@ -6414,7 +6414,7 @@
           "instances/instance_id": "chipsalliance_caliptra-rtl_pr1132",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr1132",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr1132.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr1132"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr1132"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-rtl_pr757",
@@ -6432,37 +6432,37 @@
           "instances/instance_id": "chipsalliance_caliptra-rtl_pr883",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr883",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr883.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr883"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr883"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-rtl_pr919",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr919",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr919.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr919"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr919"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-rtl_pr921",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr921",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr921.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr921"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr921"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-rtl_pr963",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-rtl_pr963",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-rtl_pr963.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-rtl_pr963"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-rtl_pr963"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-ss_pr550",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr550",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr550.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr550"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr550"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-ss_pr565",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr565",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr565.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr565"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr565"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-ss_pr590",
@@ -6474,13 +6474,13 @@
           "instances/instance_id": "chipsalliance_caliptra-ss_pr750",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr750",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr750.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr750"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr750"
         },
         {
           "instances/instance_id": "chipsalliance_caliptra-ss_pr838",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/chipsalliance_caliptra-ss_pr838",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/chipsalliance_caliptra-ss_pr838.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/chipsalliance_caliptra-ss_pr838"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/chipsalliance_caliptra-ss_pr838"
         },
         {
           "instances/instance_id": "chipsalliance_i3c-core_pr35",
@@ -6534,7 +6534,7 @@
           "instances/instance_id": "hdl-util_hdmi_pr12",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/hdl-util_hdmi_pr12",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/hdl-util_hdmi_pr12.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/hdl-util_hdmi_pr12"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/hdl-util_hdmi_pr12"
         },
         {
           "instances/instance_id": "hdl-util_hdmi_pr15",
@@ -6912,7 +6912,7 @@
           "instances/instance_id": "lowRISC_ibex_pr1917",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr1917",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr1917.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr1917"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/lowRISC_ibex_pr1917"
         },
         {
           "instances/instance_id": "lowRISC_ibex_pr2166",
@@ -6948,7 +6948,7 @@
           "instances/instance_id": "lowRISC_ibex_pr2269",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/lowRISC_ibex_pr2269",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/lowRISC_ibex_pr2269.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/lowRISC_ibex_pr2269"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/lowRISC_ibex_pr2269"
         },
         {
           "instances/instance_id": "lowRISC_opentitan_pr28469",
@@ -7098,7 +7098,7 @@
           "instances/instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr29"
         },
         {
           "instances/instance_id": "muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr31",
@@ -7194,7 +7194,7 @@
           "instances/instance_id": "openhwgroup_cv32e40s_pr254",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40s_pr254",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40s_pr254.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40s_pr254"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/openhwgroup_cv32e40s_pr254"
         },
         {
           "instances/instance_id": "openhwgroup_cv32e40s_pr259",
@@ -7212,7 +7212,7 @@
           "instances/instance_id": "openhwgroup_cv32e40x_pr894",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/openhwgroup_cv32e40x_pr894",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/openhwgroup_cv32e40x_pr894.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/openhwgroup_cv32e40x_pr894"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/openhwgroup_cv32e40x_pr894"
         },
         {
           "instances/instance_id": "openhwgroup_cv32e41p_pr15",
@@ -7392,13 +7392,13 @@
           "instances/instance_id": "pulp-platform_axi_pr138",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr138",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr138.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr138"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_pr138"
         },
         {
           "instances/instance_id": "pulp-platform_axi_pr185",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_pr185",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_pr185.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_pr185"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_pr185"
         },
         {
           "instances/instance_id": "pulp-platform_axi_pr224",
@@ -7518,7 +7518,7 @@
           "instances/instance_id": "pulp-platform_axi_riscv_atomics_pr37",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_axi_riscv_atomics_pr37",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_axi_riscv_atomics_pr37.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_axi_riscv_atomics_pr37"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_axi_riscv_atomics_pr37"
         },
         {
           "instances/instance_id": "pulp-platform_axi_riscv_atomics_pr38",
@@ -7536,7 +7536,7 @@
           "instances/instance_id": "pulp-platform_carfield_pr27",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_carfield_pr27",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_carfield_pr27.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_carfield_pr27"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_carfield_pr27"
         },
         {
           "instances/instance_id": "pulp-platform_carfield_pr41",
@@ -7595,8 +7595,8 @@
         {
           "instances/instance_id": "pulp-platform_common_cells_pr188",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_common_cells_pr188",
-          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_common_cells_pr188.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_common_cells_pr188"
+          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_common_cells_pr188.patch",
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_common_cells_pr188"
         },
         {
           "instances/instance_id": "pulp-platform_common_cells_pr222",
@@ -7734,13 +7734,13 @@
           "instances/instance_id": "pulp-platform_neureka_pr30",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_neureka_pr30",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_neureka_pr30.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_neureka_pr30"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_neureka_pr30"
         },
         {
           "instances/instance_id": "pulp-platform_pulp_soc_pr23",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_pulp_soc_pr23",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_pulp_soc_pr23.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_pulp_soc_pr23"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_pulp_soc_pr23"
         },
         {
           "instances/instance_id": "pulp-platform_pulp_soc_pr41",
@@ -7829,8 +7829,8 @@
         {
           "instances/instance_id": "pulp-platform_register_interface_pr32",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_register_interface_pr32",
-          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_register_interface_pr32.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_register_interface_pr32"
+          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_register_interface_pr32.patch",
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_register_interface_pr32"
         },
         {
           "instances/instance_id": "pulp-platform_register_interface_pr33",
@@ -7901,8 +7901,8 @@
         {
           "instances/instance_id": "pulp-platform_riscv-dbg_pr123",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_riscv-dbg_pr123",
-          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_riscv-dbg_pr123.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_riscv-dbg_pr123"
+          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/pulp-platform_riscv-dbg_pr123.patch",
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_riscv-dbg_pr123"
         },
         {
           "instances/instance_id": "pulp-platform_riscv-dbg_pr145",
@@ -7992,7 +7992,7 @@
           "instances/instance_id": "pulp-platform_tech_cells_generic_pr17",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/pulp-platform_tech_cells_generic_pr17",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/pulp-platform_tech_cells_generic_pr17.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/pulp-platform_tech_cells_generic_pr17"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/pulp-platform_tech_cells_generic_pr17"
         },
         {
           "instances/instance_id": "pulp-platform_tech_cells_generic_pr22",
@@ -8076,7 +8076,7 @@
           "instances/instance_id": "svunit_svunit_pr114",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/svunit_svunit_pr114",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/svunit_svunit_pr114.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/svunit_svunit_pr114"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/svunit_svunit_pr114"
         },
         {
           "instances/instance_id": "svunit_svunit_pr197",
@@ -8100,7 +8100,7 @@
           "instances/instance_id": "taichi-ishitani_tvip-axi_pr36",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr36",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr36.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr36"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/taichi-ishitani_tvip-axi_pr36"
         },
         {
           "instances/instance_id": "taichi-ishitani_tvip-axi_pr44",
@@ -8112,7 +8112,7 @@
           "instances/instance_id": "taichi-ishitani_tvip-axi_pr47",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/taichi-ishitani_tvip-axi_pr47",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/taichi-ishitani_tvip-axi_pr47.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/taichi-ishitani_tvip-axi_pr47"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/taichi-ishitani_tvip-axi_pr47"
         },
         {
           "instances/instance_id": "taichi-ishitani_tvip-axi_pr50",
@@ -8130,13 +8130,13 @@
           "instances/instance_id": "va7deo_zerowing_pr17",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/va7deo_zerowing_pr17",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/va7deo_zerowing_pr17.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/va7deo_zerowing_pr17"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/va7deo_zerowing_pr17"
         },
         {
           "instances/instance_id": "verilator_verilator_pr6552",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6552",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6552.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6552"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6552"
         },
         {
           "instances/instance_id": "verilator_verilator_pr6573",
@@ -8178,7 +8178,7 @@
           "instances/instance_id": "verilator_verilator_pr6697",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6697",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6697.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6697"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6697"
         },
         {
           "instances/instance_id": "verilator_verilator_pr6723",
@@ -8189,8 +8189,8 @@
         {
           "instances/instance_id": "verilator_verilator_pr6737",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6737",
-          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6737.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6737"
+          "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/main/patches/verilator_verilator_pr6737.patch",
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6737"
         },
         {
           "instances/instance_id": "verilator_verilator_pr6815",
@@ -8232,7 +8232,7 @@
           "instances/instance_id": "verilator_verilator_pr6870",
           "instances/issue_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/issues/verilator_verilator_pr6870",
           "instances/developer_patch_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/resolve/957dca0fb6d4316f0c298a5589f65795b38eeee6/patches/verilator_verilator_pr6870.patch",
-          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/957dca0fb6d4316f0c298a5589f65795b38eeee6/testbench/verilator_verilator_pr6870"
+          "instances/testbench_url": "https://huggingface.co/datasets/OvertureMMXXI/Phoenix-Bench/tree/main/testbench/verilator_verilator_pr6870"
         },
         {
           "instances/instance_id": "verilator_verilator_pr6876",
@@ -8284,7 +8284,7 @@
     "http://mlcommons.org/croissant/RAI/1.0"
   ],
   "name": "Phoenix-Bench",
-  "description": "Phoenix-Bench is a repository-level Verilog/SystemVerilog issue-resolution benchmark. This metadata indexes the 511 issue descriptions, developer patches, and executable testbench directories in the public release. Additional source snapshots are hosted under snapshots/ in the same repository. Artifact URLs are pinned to revision 957dca0fb6d4316f0c298a5589f65795b38eeee6. The instances RecordSet contains artifact locations; issue FileObjects provide SHA-256 checksums of the downloaded issue files.",
+  "description": "Phoenix-Bench is a repository-level Verilog/SystemVerilog issue-resolution benchmark. This metadata indexes the 511 issue descriptions, developer patches, and executable testbench directories in the public release. Additional source snapshots are hosted under snapshots/ in the same repository. Artifact URLs are pinned to revision 957dca0fb6d4316f0c298a5589f65795b38eeee6, except 46 testbench directories and 5 reference patches, which follow main. The instances RecordSet contains artifact locations; issue FileObjects provide SHA-256 checksums of the downloaded issue files.",
   "alternateName": [
     "Phoenix-bench",
     "OvertureMMXXI/Phoenix-Bench"
@@ -8452,6 +8452,6 @@
     "name": "Phoenix-Bench dataset collection and verification",
     "description": "We first query the GitHub Search API for Verilog/SystemVerilog repositories with at least 50 stars Then retain issues linked to pull requests through explicit references or GitHub native linking We next filter for pull requests that modify Verilog/SystemVerilog artifacts and remove duplicate or incomplete cases. This process yields a synchronized runner corpus of 511 verified Verilator instances with both fail-to-pass and pass-to-pass tests GitHub"
   },
-  "dateModified": "2026-10-30",
+  "dateModified": "2026-11-05",
   "isLiveDataset": false
 }

README.md

@@ -44,6 +44,8 @@ Phoenix-Bench is a collection of 511 hardware-engineering issue-resolution insta
 
 The viewer contains a lightweight index, not all repository sources. The full artifact directories remain available under Files and versions. The explicit JSONL configuration prevents unrelated CSV, source, and metadata files from being inferred as incompatible dataset splits.
 
+**Reference patches.** All 511 instances have a recorded passing run of the reference patch: the harness fails on the pre-fix tree and passes with the patch applied.
+
 ## Schema and split
 
 There is one configuration, `default`, and one evaluation split, `test`, containing all 511 instances. No training or validation partition is defined. The examples are a subset of `test`, not additional independent evaluation instances.
@@ -57,6 +59,8 @@ There is one configuration, `default`, and one evaluation split, `test`, contain
 | `snapshot_url` | string | Revision-pinned source-directory browser URL. |
 | `testbench_url` | string | Revision-pinned verification-directory browser URL. |
 
+Some testbench and patch links follow `main`; all other links stay on the fixed revision below.
+
 The index follows the 511-instance record set in the published Croissant file. Issue bytes were checked against its SHA-256 values. Artifact links retain that metadata's fixed revision, `957dca0fb6d4316f0c298a5589f65795b38eeee6`; adding this index does not modify task content or evaluation outcomes.
 
 ## Load and inspect

patches/UTOSS_risc-v_pr81.patch

@@ -1,85 +1,111 @@
-From 32c1bf8887e80d34e3b2e44a338a5a42e81e2e5e Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Sun, 26 Oct 2025 05:49:58 -0400
-Subject: [PATCH 1/8] change MA to have 4 bit WE; fix sb/sh
-
----
- src/ControlFSM.sv                      |  7 ++-
- src/Instruction_Decode/MemoryLoader.sv | 78 +++++++++++++++++++++-----
- src/top.v                              | 21 ++++---
- src/utils/MA.v                         |  9 +--
- 4 files changed, 86 insertions(+), 29 deletions(-)
-
 diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv
-index 31bf453..a9692c4 100644
+index 37c1eda2..d41cced3 100644
 --- a/src/ControlFSM.sv
 +++ b/src/ControlFSM.sv
-@@ -9,12 +9,13 @@ module ControlFSM(
- 	input wire clk,
- 	input wire reset,
-   input wire zero_flag,
-+  input wire [3:0] MemWriteByteAddress,
- 	output adr_src_t AdrSrc,
- 	output reg IRWrite,
- 	output reg RegWrite,
- 	output reg PCUpdate,
-   output pc_src_t pc_src,
--	output reg MemWrite,
-+	output reg [3:0] MemWrite,
- 	output reg Branch,
- 	output alu_src_a_t ALUSrcA,
- 	output alu_src_b_t ALUSrcB,
-@@ -115,7 +116,7 @@ module ControlFSM(
-     pc_src <= 1'b0;
+@@ -9,12 +9,13 @@ module ControlFSM
+   , input wire clk
+   , input wire reset
+   , input wire zero_flag
++  , input wire [3:0] MemWriteByteAddress
+   , output adr_src_t AdrSrc
+   , output reg IRWrite
+   , output reg RegWrite
+   , output reg PCUpdate
+   , output pc_src_t pc_src
+-  , output reg MemWrite
++  , output reg [3:0] MemWrite
+   , output reg Branch
+   , output alu_src_a_t ALUSrcA
+   , output alu_src_b_t ALUSrcB
+@@ -122,7 +123,7 @@ module ControlFSM
+     pc_src <= PC_SRC__INCREMENT;
      PCUpdate <= 1'b0;
      IRWrite <= 1'b0;
 -    MemWrite <= 1'b0;
 +    MemWrite <= 4'b0;
- 	RegWrite <= 1'b0;
+   RegWrite <= 1'b0;
  
- 		FSMState <= current_state;
-@@ -211,7 +212,7 @@ module ControlFSM(
+     FSMState <= current_state;
+@@ -236,7 +237,7 @@ module ControlFSM
  
- 				ResultSrc <= RESULT_SRC__ALU_OUT;
- 				AdrSrc <= ADR_SRC__RESULT;
--				MemWrite <= 1'b1;
-+				MemWrite <= MemWriteByteAddress;
+         ResultSrc <= RESULT_SRC__ALU_OUT;
+         AdrSrc <= ADR_SRC__RESULT;
+-        MemWrite <= 1'b1;
++        MemWrite <= MemWriteByteAddress;
  
- 			end
+       end
  
 diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv
-index 45499ca..1fa66e1 100644
+index 578de14a..170e5f94 100644
 --- a/src/Instruction_Decode/MemoryLoader.sv
 +++ b/src/Instruction_Decode/MemoryLoader.sv
-@@ -1,8 +1,13 @@
+@@ -1,52 +1,107 @@
 +`include "src/types.svh"
 +
- module MemoryLoader (
-     input  data_t memory_data,
-     input  addr_t memory_address,
-     input  logic [2:0]  funct3,
--    output data_t mem_load_result
-+    input  logic [31:0] dataB,
-+    output data_t mem_load_result,
-+    output logic [3:0] MemWriteByteAddress,
-+    output logic [31:0] __tmp_MemData
- );
+ module MemoryLoader
+-  ( input  data_t memory_data
+-  , input  addr_t memory_address
+-  , input  logic [2:0]  funct3
+-  , output data_t mem_load_result
+-  );
++( input  data_t memory_data
++, input  addr_t memory_address
++, input  logic [2:0]  funct3
++, input  logic [31:0] dataB
++, output data_t mem_load_result
++, output logic [3:0] MemWriteByteAddress
++, output logic [31:0] __tmp_MemData
++);
  
      integer byteindex;
-@@ -10,27 +15,66 @@ module MemoryLoader (
+     assign byteindex = memory_address[1:0];
  
-     always_comb begin
-         case (funct3)
--            3'b000: begin // lb
+-    always_comb
+-      case (funct3)
+-        3'b000: // lb
+-          case (byteindex)
+-            2'd0: mem_load_result = {{24{memory_data[7]}} , memory_data[7:0]};
+-            2'd1: mem_load_result = {{24{memory_data[15]}}, memory_data[15:8]};
+-            2'd2: mem_load_result = {{24{memory_data[23]}}, memory_data[23:16]};
+-            2'd3: mem_load_result = {{24{memory_data[31]}}, memory_data[31:24]};
+-            default: mem_load_result = 32'hX;
+-          endcase
+-
+-        3'b001: // lh
+-          case (byteindex)
+-            2'd0: mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]};
+-            2'd1: mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]};
+-            2'd2: mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]};
+-            default: mem_load_result = 32'hX;
+-          endcase
+-
+-        3'b010: mem_load_result = memory_data; // lw
+-
+-        3'b100: // lbu
+-          case (byteindex)
+-            2'd0: mem_load_result = {24'b0, memory_data[7:0]};
+-            2'd1: mem_load_result = {24'b0, memory_data[15:8]};
+-            2'd2: mem_load_result = {24'b0, memory_data[23:16]};
+-            2'd3: mem_load_result = {24'b0, memory_data[31:24]};
+-            default: mem_load_result = 32'hX;
+-          endcase
+-
+-        3'b101: // lhu
+-          case (byteindex)
+-            2'd0: mem_load_result = {16'b0, memory_data[15:0]};
+-            2'd1: mem_load_result = {16'b0, memory_data[23:8]};
+-            2'd2: mem_load_result = {16'b0, memory_data[31:16]};
+-            default: mem_load_result = 32'hX;
+-          endcase
+-
+-        default: mem_load_result = 32'hX;
+-      endcase
++    always @(*) begin
++        case (funct3)
 +            3'b000: begin // lb & sb
-                 case (byteindex)
--                    2'd0: mem_load_result = {{24{memory_data[7]}},  memory_data[7:0]};
--                    2'd1: mem_load_result = {{24{memory_data[15]}}, memory_data[15:8]};
--                    2'd2: mem_load_result = {{24{memory_data[23]}}, memory_data[23:16]};
--                    2'd3: mem_load_result = {{24{memory_data[31]}}, memory_data[31:24]};
--                    default: mem_load_result = 32'hX;
++                case (byteindex)
 +                    2'd0: begin
-+                        mem_load_result = {{24{memory_data[7]}},  memory_data[7:0]};
++                        mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]};
 +                        MemWriteByteAddress = 4'b0001;
 +                        __tmp_MemData = {24'b0, dataB[7:0]};
 +                    end
@@ -103,26 +129,22 @@ index 45499ca..1fa66e1 100644
 +                        MemWriteByteAddress = 4'bx;
 +                        __tmp_MemData = 32'bx;
 +                    end
-                 endcase
-             end
- 
--            3'b001: begin // lh
++                endcase
++            end
++
 +            3'b001: begin // lh & sh
-                 case (byteindex)
--                    2'd0: mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]};
--                    2'd1: mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]};
--                    2'd2: mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]};
--                    default: mem_load_result = 32'hX;
++                case (byteindex)
 +                    2'd0: begin
 +                        mem_load_result = {{16{memory_data[15]}}, memory_data[15:0]};
 +                        MemWriteByteAddress = 4'b0011;
 +                        __tmp_MemData = {16'b0, dataB[15:0]};
 +                    end
-+                    2'd1: begin
++/*                    2'd1: begin
 +                        mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]};
 +                        MemWriteByteAddress = 4'b0110;
 +                        __tmp_MemData = {8'b0, dataB[15:0], 8'b0};
-+                    end
++                    end*/
++                    // skip unaligned halfword access
 +                    2'd2: begin
 +                        mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]};
 +                        MemWriteByteAddress = 4'b1100;
@@ -133,309 +155,45 @@ index 45499ca..1fa66e1 100644
 +                        MemWriteByteAddress = 4'bX;
 +                        __tmp_MemData = 32'bX;
 +                    end
-                 endcase
-             end
- 
--            3'b010: mem_load_result = memory_data; // lw
--
++                endcase
++            end
++
 +            3'b010: begin
 +                mem_load_result = memory_data; // lw
 +                MemWriteByteAddress = 4'b1111; //sw
 +                __tmp_MemData = dataB;
 +              end
-             3'b100: begin // lbu
-                 case (byteindex)
-                     2'd0: mem_load_result = {24'b0, memory_data[7:0]};
-@@ -50,7 +94,11 @@ module MemoryLoader (
-                 endcase
-             end
- 
--            default: mem_load_result = 32'hX;
++            3'b100: begin // lbu
++                case (byteindex)
++                    2'd0: mem_load_result = {24'b0, memory_data[7:0]};
++                    2'd1: mem_load_result = {24'b0, memory_data[15:8]};
++                    2'd2: mem_load_result = {24'b0, memory_data[23:16]};
++                    2'd3: mem_load_result = {24'b0, memory_data[31:24]};
++                    default: mem_load_result = 32'hX;
++                endcase
++            end
++
++            3'b101: begin // lhu
++                case (byteindex)
++                    2'd0: mem_load_result = {16'b0, memory_data[15:0]};
++                    2'd1: mem_load_result = {16'b0, memory_data[23:8]};
++                    2'd2: mem_load_result = {16'b0, memory_data[31:16]};
++                    default: mem_load_result = 32'hX;
++                endcase
++            end
++
 +            default: begin
 +                mem_load_result = 32'hX;
 +                MemWriteByteAddress = 4'b0000;
 +                __tmp_MemData = 31'bx;
 +            end
-         endcase
-     end
- 
-diff --git a/src/top.v b/src/top.v
-index ee7f810..0d69b60 100644
---- a/src/top.v
-+++ b/src/top.v
-@@ -38,8 +38,8 @@ module top #( parameter MEM_SIZE = 1024 )
-   wire alu__zero_flag;
- 
-   adr_src_t cfsm__adr_src;
--  wire __tmp_MemWrite
--     , __tmp_Branch;
-+  wire [3:0] __tmp_MemWrite;
-+  wire __tmp_Branch;
-   wire [1:0] __tmp_ALUSrcA
-            , __tmp_ALUSrcB;
-   wire [2:0] __tmp_ALUOp;
-@@ -49,11 +49,15 @@ module top #( parameter MEM_SIZE = 1024 )
-   logic [31:0] dataA
- 			 ,dataB;
- 
-+  logic [3:0] MemWriteByteAddress;
-+  logic [31:0] __tmp_MemData;
-+
-   ControlFSM control_fsm
-     ( .opcode    ( opcode           )
-     , .clk       ( clk              )
-     , .reset     ( reset            )
-     , .zero_flag ( alu__zero_flag   )
-+    , .MemWriteByteAddress ( MemWriteByteAddress )
-     , .AdrSrc    ( cfsm__adr_src    )
-     , .IRWrite   ( cfsm__ir_write   )
-     , .RegWrite  ( cfsm__reg_write  )
-@@ -91,7 +95,7 @@ module top #( parameter MEM_SIZE = 1024 )
-   MA #( .SIZE ( MEM_SIZE ) )
-     memory // instructions and data
-       ( .A   ( memory_address )
--      , .WD  ( dataB          )
-+      , .WD  ( __tmp_MemData  )
-       , .WE  ( __tmp_MemWrite )
-       , .CLK ( clk            )
- 
-@@ -106,10 +110,13 @@ module top #( parameter MEM_SIZE = 1024 )
-   end
- 
-   MemoryLoader MemLoad
--  ( .memory_data       ( memory_data     )
--  , .memory_address    ( memory_address  )
--  , .mem_load_result   ( mem_load_result )
--  , .funct3            ( funct3          )
-+  ( .memory_data          ( memory_data       )
-+  , .memory_address       ( memory_address    )
-+  , .mem_load_result      ( mem_load_result   )
-+  , .funct3               ( funct3            )
-+  , .dataB                ( dataB             )
-+  , .MemWriteByteAddress  ( MemWriteByteAddress)
-+  , .__tmp_MemData        ( __tmp_MemData     )
-   );
- 
-   always @(posedge clk) begin
-diff --git a/src/utils/MA.v b/src/utils/MA.v
-index a47036c..dafb7e1 100644
---- a/src/utils/MA.v
-+++ b/src/utils/MA.v
-@@ -1,7 +1,7 @@
- module MA #( parameter SIZE = 1024 )
-            ( input  [31:0] A
-            , input  [31:0] WD
--           , input         WE
-+           , input  [3:0]  WE //changed from 1 bit WE to 4 bit to address byteindex
-            , input         CLK
-            , output [31:0] RD
-            );
-@@ -21,9 +21,10 @@ module MA #( parameter SIZE = 1024 )
-     assign RD = M[A[31:2]]; // 2 LSBs used for byte addressing
- 
-     always @(posedge CLK) begin
--        if (WE) begin
--            M[A[31:2]] <= WD;
--        end
-+      if (WE[0]) M[A[31:2]][7:0]   <= WD[7:0];
-+      if (WE[1]) M[A[31:2]][15:8]  <= WD[15:8];
-+      if (WE[2]) M[A[31:2]][23:16] <= WD[23:16];
-+      if (WE[3]) M[A[31:2]][31:24] <= WD[31:24];
-     end
- 
- endmodule
-
-From 3c8e055cd03a2987f81c1d514f0166cdd3516d4b Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Tue, 28 Oct 2025 22:42:53 -0400
-Subject: [PATCH 2/8] skip unaligned halfword store/load specify the datatype
- of pc_src when assigning values in FSM
-
----
- src/ControlFSM.sv                      | 4 ++--
- src/Instruction_Decode/MemoryLoader.sv | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv
-index a9692c4..7c4011e 100644
---- a/src/ControlFSM.sv
-+++ b/src/ControlFSM.sv
-@@ -113,7 +113,7 @@ module ControlFSM(
- 	//output logic
- 	always@(*) begin
-     Branch <= 1'b0;
--    pc_src <= 1'b0;
-+    pc_src <= pc_src_t'(1'b0);
-     PCUpdate <= 1'b0;
-     IRWrite <= 1'b0;
-     MemWrite <= 4'b0;
-@@ -196,7 +196,7 @@ module ControlFSM(
- 				ALUOp <= 2'b01;
- 				ResultSrc <= RESULT_SRC__ALU_OUT;
- 				Branch <= 1'b1;
--        		pc_src <= zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT;
-+        		pc_src <= pc_src_t'(zero_flag ? PC_SRC__JUMP : PC_SRC__INCREMENT);
-         		PCUpdate <= 1'b1;
- 
- 			end
-diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv
-index 1fa66e1..a3aab7a 100644
---- a/src/Instruction_Decode/MemoryLoader.sv
-+++ b/src/Instruction_Decode/MemoryLoader.sv
-@@ -52,11 +52,11 @@ module MemoryLoader (
-                         MemWriteByteAddress = 4'b0011;
-                         __tmp_MemData = {16'b0, dataB[15:0]};
-                     end
--                    2'd1: begin
-+/*                    2'd1: begin
-                         mem_load_result = {{16{memory_data[23]}}, memory_data[23:8]};
-                         MemWriteByteAddress = 4'b0110;
-                         __tmp_MemData = {8'b0, dataB[15:0], 8'b0};
--                    end
-+                    end*/
-                     2'd2: begin
-                         mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]};
-                         MemWriteByteAddress = 4'b1100;
-
-From 9b7b2dd957e5d0355da95953093b741b4936bf65 Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Sun, 2 Nov 2025 11:51:25 -0500
-Subject: [PATCH 3/8] fix some svlint error
-
----
- src/ControlFSM.sv | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv
-index cede0f6..e7c13ca 100644
---- a/src/ControlFSM.sv
-+++ b/src/ControlFSM.sv
-@@ -235,9 +235,9 @@ module ControlFSM
- 
-       MEMWRITE: begin
- 
--				ResultSrc <= RESULT_SRC__ALU_OUT;
--				AdrSrc <= ADR_SRC__RESULT;
--				MemWrite <= MemWriteByteAddress;
-+        ResultSrc <= RESULT_SRC__ALU_OUT;
-+        AdrSrc <= ADR_SRC__RESULT;
-+        MemWrite <= MemWriteByteAddress;
- 
-       end
- 
-
-From 0d04594dafac1698d7df9344aeb96dcb3abc1508 Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Sun, 2 Nov 2025 12:16:14 -0500
-Subject: [PATCH 4/8] fix svlint error;
-
----
- src/Instruction_Decode/MemoryLoader.sv | 19 ++++++++++---------
- 1 file changed, 10 insertions(+), 9 deletions(-)
-
-diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv
-index a3aab7a..ac59979 100644
---- a/src/Instruction_Decode/MemoryLoader.sv
-+++ b/src/Instruction_Decode/MemoryLoader.sv
-@@ -1,20 +1,20 @@
- `include "src/types.svh"
- 
- module MemoryLoader (
--    input  data_t memory_data,
--    input  addr_t memory_address,
--    input  logic [2:0]  funct3,
--    input  logic [31:0] dataB,
--    output data_t mem_load_result,
--    output logic [3:0] MemWriteByteAddress,
-+    input  data_t memory_data, 
-+    input  addr_t memory_address, 
-+    input  logic [2:0]  funct3, 
-+    input  logic [31:0] dataB, 
-+    output data_t mem_load_result, 
-+    output logic [3:0] MemWriteByteAddress, 
-     output logic [31:0] __tmp_MemData
- );
- 
-     integer byteindex;
-     assign byteindex = memory_address[1:0];
- 
--    always_comb begin
--        case (funct3)
-+    always_comb 
-+        case (funct3) 
-             3'b000: begin // lb & sb
-                 case (byteindex)
-                     2'd0: begin
-@@ -57,6 +57,7 @@ module MemoryLoader (
-                         MemWriteByteAddress = 4'b0110;
-                         __tmp_MemData = {8'b0, dataB[15:0], 8'b0};
-                     end*/
-+                    // skip unaligned halfword access
-                     2'd2: begin
-                         mem_load_result = {{16{memory_data[31]}}, memory_data[31:16]};
-                         MemWriteByteAddress = 4'b1100;
-@@ -100,6 +101,6 @@ module MemoryLoader (
-                 __tmp_MemData = 31'bx;
-             end
-         endcase
--    end
-+    
- 
- endmodule
-
-From 070822bb487f7533a7624c785c21fb6a5bf39dc1 Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Sun, 2 Nov 2025 12:27:23 -0500
-Subject: [PATCH 5/8] try to change increment to fix svlint error
-
----
- src/Instruction_Decode/MemoryLoader.sv | 18 ++---
- src/Instruction_Decode/RegisterFile.v  | 92 +++++++++++++-------------
- 2 files changed, 55 insertions(+), 55 deletions(-)
-
-diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv
-index ac59979..70d34fe 100644
---- a/src/Instruction_Decode/MemoryLoader.sv
-+++ b/src/Instruction_Decode/MemoryLoader.sv
-@@ -1,20 +1,20 @@
- `include "src/types.svh"
- 
- module MemoryLoader (
--    input  data_t memory_data, 
--    input  addr_t memory_address, 
--    input  logic [2:0]  funct3, 
--    input  logic [31:0] dataB, 
--    output data_t mem_load_result, 
--    output logic [3:0] MemWriteByteAddress, 
-+    input  data_t memory_data,
-+    input  addr_t memory_address,
-+    input  logic [2:0]  funct3,
-+    input  logic [31:0] dataB,
-+    output data_t mem_load_result,
-+    output logic [3:0] MemWriteByteAddress,
-     output logic [31:0] __tmp_MemData
- );
- 
-     integer byteindex;
-     assign byteindex = memory_address[1:0];
- 
--    always_comb 
--        case (funct3) 
-+    always_comb
-+        case (funct3)
-             3'b000: begin // lb & sb
-                 case (byteindex)
-                     2'd0: begin
-@@ -101,6 +101,6 @@ module MemoryLoader (
-                 __tmp_MemData = 31'bx;
-             end
-         endcase
--    
++        endcase
++    end
 +
  
  endmodule
 diff --git a/src/Instruction_Decode/RegisterFile.v b/src/Instruction_Decode/RegisterFile.v
-index f8fabcb..15c7854 100644
+index f8fabcb1..15c78547 100644
 --- a/src/Instruction_Decode/RegisterFile.v
 +++ b/src/Instruction_Decode/RegisterFile.v
 @@ -1,46 +1,46 @@
@@ -531,124 +289,80 @@ index f8fabcb..15c7854 100644
 +  end
 +
 +endmodule
-
-From bba571da6d6417bd082710e0fa1831da93624174 Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Sun, 2 Nov 2025 12:33:37 -0500
-Subject: [PATCH 6/8] fix svlint errors
-
----
- src/Instruction_Decode/MemoryLoader.sv | 17 +++++++++--------
- 1 file changed, 9 insertions(+), 8 deletions(-)
-
-diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv
-index 70d34fe..4ebb286 100644
---- a/src/Instruction_Decode/MemoryLoader.sv
-+++ b/src/Instruction_Decode/MemoryLoader.sv
-@@ -1,24 +1,24 @@
- `include "src/types.svh"
- 
- module MemoryLoader (
--    input  data_t memory_data,
--    input  addr_t memory_address,
--    input  logic [2:0]  funct3,
--    input  logic [31:0] dataB,
--    output data_t mem_load_result,
--    output logic [3:0] MemWriteByteAddress,
-+    input  data_t memory_data, 
-+    input  addr_t memory_address, 
-+    input  logic [2:0]  funct3, 
-+    input  logic [31:0] dataB, 
-+    output data_t mem_load_result, 
-+    output logic [3:0] MemWriteByteAddress, 
-     output logic [31:0] __tmp_MemData
- );
- 
-     integer byteindex;
-     assign byteindex = memory_address[1:0];
- 
--    always_comb
-+    always@(*) begin
-         case (funct3)
-             3'b000: begin // lb & sb
-                 case (byteindex)
-                     2'd0: begin
--                        mem_load_result = {{24{memory_data[7]}},  memory_data[7:0]};
-+                        mem_load_result = {{24{memory_data[7]}}, memory_data[7:0]};
-                         MemWriteByteAddress = 4'b0001;
-                         __tmp_MemData = {24'b0, dataB[7:0]};
-                     end
-@@ -101,6 +101,7 @@ module MemoryLoader (
-                 __tmp_MemData = 31'bx;
-             end
-         endcase
-+    end
+diff --git a/src/top.v b/src/top.v
+index 20a0ff8b..48a84e00 100644
+--- a/src/top.v
++++ b/src/top.v
+@@ -38,7 +38,8 @@ module top #( parameter MEM_SIZE = 1024 )
+   wire alu__zero_flag;
  
+   adr_src_t cfsm__adr_src;
+-  wire __tmp_MemWrite, __tmp_Branch;
++  wire [3:0] __tmp_MemWrite;
++  wire __tmp_Branch;
+   wire [1:0] __tmp_ALUSrcA, __tmp_ALUSrcB;
+   wire [2:0] __tmp_ALUOp;
+   wire [3:0] __tmp_ALUControl;
+@@ -47,11 +48,15 @@ module top #( parameter MEM_SIZE = 1024 )
+   data_t     dataA, dataB;
+   reg  [4:0] rd, rs1, rs2;
  
- endmodule
-
-From dd595584cc60a39154113fd3c68940c626d1dd83 Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Sun, 2 Nov 2025 12:43:53 -0500
-Subject: [PATCH 7/8] fixing indentation
-
----
- src/Instruction_Decode/MemoryLoader.sv | 18 +++++++++---------
- src/utils/MA.v                         | 24 +++++++++++++-----------
- 2 files changed, 22 insertions(+), 20 deletions(-)
-
-diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv
-index 4ebb286..9489e03 100644
---- a/src/Instruction_Decode/MemoryLoader.sv
-+++ b/src/Instruction_Decode/MemoryLoader.sv
-@@ -1,19 +1,19 @@
- `include "src/types.svh"
++  logic [3:0] MemWriteByteAddress;
++  logic [31:0] __tmp_MemData;
++
+   ControlFSM control_fsm
+     ( .opcode    ( opcode           )
+     , .clk       ( clk              )
+     , .reset     ( reset            )
+     , .zero_flag ( alu__zero_flag   )
++    , .MemWriteByteAddress ( MemWriteByteAddress )
+     , .AdrSrc    ( cfsm__adr_src    )
+     , .IRWrite   ( cfsm__ir_write   )
+     , .RegWrite  ( cfsm__reg_write  )
+@@ -90,7 +95,7 @@ module top #( parameter MEM_SIZE = 1024 )
+   MA #( .SIZE ( MEM_SIZE ) )
+     memory // instructions and data
+       ( .A   ( memory_address )
+-      , .WD  ( dataB          )
++      , .WD  ( __tmp_MemData  )
+       , .WE  ( __tmp_MemWrite )
+       , .CLK ( clk            )
  
--module MemoryLoader (
--    input  data_t memory_data, 
--    input  addr_t memory_address, 
--    input  logic [2:0]  funct3, 
--    input  logic [31:0] dataB, 
--    output data_t mem_load_result, 
--    output logic [3:0] MemWriteByteAddress, 
--    output logic [31:0] __tmp_MemData
-+module MemoryLoader 
-+( input  data_t memory_data
-+, input  addr_t memory_address
-+, input  logic [2:0]  funct3
-+, input  logic [31:0] dataB
-+, output data_t mem_load_result
-+, output logic [3:0] MemWriteByteAddress
-+, output logic [31:0] __tmp_MemData
- );
+@@ -105,10 +110,13 @@ module top #( parameter MEM_SIZE = 1024 )
+   end
  
-     integer byteindex;
-     assign byteindex = memory_address[1:0];
+   MemoryLoader MemLoad
+-  ( .memory_data       ( memory_data     )
+-  , .memory_address    ( memory_address  )
+-  , .mem_load_result   ( mem_load_result )
+-  , .funct3            ( funct3          )
++  ( .memory_data          ( memory_data       )
++  , .memory_address       ( memory_address    )
++  , .mem_load_result      ( mem_load_result   )
++  , .funct3               ( funct3            )
++  , .dataB                ( dataB             )
++  , .MemWriteByteAddress  ( MemWriteByteAddress)
++  , .__tmp_MemData        ( __tmp_MemData     )
+   );
  
--    always@(*) begin
-+    always @(*) begin
-         case (funct3)
-             3'b000: begin // lb & sb
-                 case (byteindex)
+   always @(posedge clk) begin
 diff --git a/src/utils/MA.v b/src/utils/MA.v
-index a3c988f..13ab49e 100644
+index 07209235..d6282dde 100644
 --- a/src/utils/MA.v
 +++ b/src/utils/MA.v
-@@ -1,16 +1,18 @@
+@@ -1,16 +1,16 @@
 -module MA #( parameter SIZE = 1024 )
--           ( input  [31:0] A
--           , input  [31:0] WD
--           , input  [3:0]  WE //changed from 1 bit WE to 4 bit to address byteindex
--           , input  wire   CLK
--           , output [31:0] RD
--           );
-+module MA #( 
-+  parameter SIZE = 1024 
-+)
-+( 
-+  input  [31:0] A
+-  ( input  [31:0] A
+-  , input  [31:0] WD
+-  , input  wire   WE
+-  , input  wire   CLK
+-  , output [31:0] RD
+-  );
++module MA #(parameter SIZE = 1024)
++( input  [31:0] A
 +, input  [31:0] WD
-+, input  [3:0]  WE   //changed from 1 bit WE to 4 bit to address byteindex
++, input  [3:0]  WE
++//changed from 1 bit WE to 4 bit to address byteindex
 +, input  wire   CLK
 +, output [31:0] RD
 +);
@@ -664,59 +378,17 @@ index a3c988f..13ab49e 100644
  
        if ($value$plusargs("MEM=%s", mem_file)) begin
          $display("loading memory from <%s>", mem_file);
-
-From 73805f922ab826a660093f4b7f20229649db8330 Mon Sep 17 00:00:00 2001
-From: DanielTaoHuang123 <danielthuang@outlook.com>
-Date: Sun, 2 Nov 2025 12:51:43 -0500
-Subject: [PATCH 8/8] fix trailing white spaces
-
----
- src/ControlFSM.sv                      |  2 +-
- src/Instruction_Decode/MemoryLoader.sv |  2 +-
- src/utils/MA.v                         | 10 ++++------
- 3 files changed, 6 insertions(+), 8 deletions(-)
-
-diff --git a/src/ControlFSM.sv b/src/ControlFSM.sv
-index e7c13ca..d41cced 100644
---- a/src/ControlFSM.sv
-+++ b/src/ControlFSM.sv
-@@ -15,7 +15,7 @@ module ControlFSM
-   , output reg RegWrite
-   , output reg PCUpdate
-   , output pc_src_t pc_src
--   , output reg [3:0] MemWrite
-+  , output reg [3:0] MemWrite
-   , output reg Branch
-   , output alu_src_a_t ALUSrcA
-   , output alu_src_b_t ALUSrcB
-diff --git a/src/Instruction_Decode/MemoryLoader.sv b/src/Instruction_Decode/MemoryLoader.sv
-index 9489e03..170e5f9 100644
---- a/src/Instruction_Decode/MemoryLoader.sv
-+++ b/src/Instruction_Decode/MemoryLoader.sv
-@@ -1,6 +1,6 @@
- `include "src/types.svh"
+@@ -21,9 +21,10 @@ module MA #( parameter SIZE = 1024 )
  
--module MemoryLoader 
-+module MemoryLoader
- ( input  data_t memory_data
- , input  addr_t memory_address
- , input  logic [2:0]  funct3
-diff --git a/src/utils/MA.v b/src/utils/MA.v
-index 13ab49e..d6282dd 100644
---- a/src/utils/MA.v
-+++ b/src/utils/MA.v
-@@ -1,10 +1,8 @@
--module MA #( 
--  parameter SIZE = 1024 
--)
--( 
--  input  [31:0] A
-+module MA #(parameter SIZE = 1024)
-+( input  [31:0] A
- , input  [31:0] WD
--, input  [3:0]  WE   //changed from 1 bit WE to 4 bit to address byteindex
-+, input  [3:0]  WE
-+//changed from 1 bit WE to 4 bit to address byteindex
- , input  wire   CLK
- , output [31:0] RD
- );
+     assign RD = M[A[31:2]]; // 2 LSBs used for byte addressing
+     always @(posedge CLK) begin
+-        if (WE) begin
+-            M[A[31:2]] <= WD;
+-        end
++      if (WE[0]) M[A[31:2]][7:0]   <= WD[7:0];
++      if (WE[1]) M[A[31:2]][15:8]  <= WD[15:8];
++      if (WE[2]) M[A[31:2]][23:16] <= WD[23:16];
++      if (WE[3]) M[A[31:2]][31:24] <= WD[31:24];
+     end
+ 
+ endmodule

patches/pulp-platform_common_cells_pr188.patch

@@ -30,7 +30,7 @@ index c38e8d2f..1e4fe299 100644
 +
  
  module popcount #(
--    parameter int unsigned INPUT_WIDTH = 256,
+-    parameter int unsigned INPUT_WIDTH = 1,
 -    localparam int unsigned PopcountWidth = $clog2(INPUT_WIDTH)+1
 +    parameter  int unsigned INPUT_WIDTH   = 256,
 +    localparam int unsigned PopcountWidth = $clog2(INPUT_WIDTH) + 1

patches/pulp-platform_register_interface_pr32.patch

@@ -73,7 +73,7 @@ index 0000000..472985c
 +);
 +
 +  always_comb begin
-+    out_req_o = out_req_i;
++    out_req_o = in_req_i;
 +    in_rsp_o = out_rsp_i;
 +
 +    if (in_req_i.valid && in_req_i.we && in_req_i.strb == '0) begin

patches/pulp-platform_riscv-dbg_pr123.patch

@@ -1,21 +1,38 @@
-From faa6ccd06100cf4f855ffe8562d55044f998db5e Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Thu, 6 Jan 2022 19:10:42 +0100
-Subject: [PATCH 01/11] First draft of dmihardreset support and proper warm
- reset capability
-
----
- doc/debug-system.md |   1 -
- src/dmi_cdc.sv      |  54 +++++++-----
- src/dmi_jtag.sv     | 203 +++++++++++++++++++++++---------------------
- src/dmi_jtag_tap.sv |   7 +-
- 4 files changed, 144 insertions(+), 121 deletions(-)
-
-diff --git a/doc/debug-system.md b/doc/debug-system.md
-index b025f89..1beca7d 100644
+--- a/Bender.yml
++++ b/Bender.yml
+@@ -10,7 +10,7 @@
+ 
+ dependencies:
+   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
+-  common_cells: {git: https://github.com/pulp-platform/common_cells.git, version: 1.21.0}
++  common_cells: {git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0}
+ 
+ sources:
+   files:
+--- a/CHANGELOG.md
++++ b/CHANGELOG.md
+@@ -8,11 +8,18 @@
+ ### Added
+ - Add sbaccess8 and sbaccess16 support (#106) [@noytzach](https://github.com/noytzach)
+ - Implement SBA bad address error (#12) [@msfchaffner](https://github.com/msfschaffner)
++- Added random reset tests to dmi testbench.
+ ### Changed
++- Implement `dmihardreset` functionaliy in `dtmcs` register.
++- `dmi_rst_ni` of `dm_top` is now a synchronous signal. However, `dmi_rst_no` of
++  `dmi_jtag` is glitch-free and asserted during all forms (functional or POR) of
++  resets.
+ ### Fixed
+ - Fixed documentation (csr)
+ - Fixed reset value of sbcs register (#127) [@msfchaffner](https://github.com/msfschaffner)
+ - Fixed various ascent lint warnings [@msfchaffner](https://github.com/msfschaffner)
++- Implement proper CDC flushing behavior on functional resets and JTAG resets (asynchronous or TestLogicReset driven).
++- Fix JTAG non-compliance in TestLogicReset state (IR should reset to IDCODE).
+ 
+ ## [0.4.1] - 2021-05-04
+ ### Added
 --- a/doc/debug-system.md
 +++ b/doc/debug-system.md
-@@ -485,7 +485,6 @@ default the IR register is 5 bits long, but the implementation is parameterized.
+@@ -485,7 +485,6 @@
    ) (
    ```
  - `DTMCSR`: RISC-V specific control and status register of the JTAG DMI.
@@ -23,16 +40,39 @@ index b025f89..1beca7d 100644
  - `DMIACCESS`: Access the debug module's register.
      - `abits+33:34`: Address
      - `33:2`: Data
-diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv
-index 4665c91..d9e9363 100644
+--- a/src/dm_csrs.sv
++++ b/src/dm_csrs.sv
+@@ -23,7 +23,8 @@
+   input  logic                              clk_i,           // Clock
+   input  logic                              rst_ni,          // Asynchronous reset active low
+   input  logic                              testmode_i,
+-  input  logic                              dmi_rst_ni,      // Debug Module Intf reset active-low
++  input  logic                              dmi_rst_ni,      // sync. DTM reset,
++                                                             // active-low
+   input  logic                              dmi_req_valid_i,
+   output logic                              dmi_req_ready_o,
+   input  dm::dmi_req_t                      dmi_req_i,
+@@ -559,9 +560,10 @@
+     .dtype            ( logic [31:0]         ),
+     .DEPTH            ( 2                    )
+   ) i_fifo (
+-    .clk_i            ( clk_i                ),
+-    .rst_ni           ( dmi_rst_ni           ), // reset only when system is re-set
+-    .flush_i          ( 1'b0                 ), // we do not need to flush this queue
++    .clk_i,
++    .rst_ni,
++    .flush_i          ( ~dmi_rst_ni          ), // Flush the queue if the DTM is
++                                                // reset
+     .testmode_i       ( testmode_i           ),
+     .full_o           ( resp_queue_full      ),
+     .empty_o          ( resp_queue_empty     ),
 --- a/src/dmi_cdc.sv
 +++ b/src/dmi_cdc.sv
-@@ -19,11 +19,13 @@
- module dmi_cdc (
+@@ -20,10 +20,12 @@
    // JTAG side (master side)
    input  logic             tck_i,
--  input  logic             trst_ni,
- 
+   input  logic             trst_ni,
+-
    input  dm::dmi_req_t     jtag_dmi_req_i,
    output logic             jtag_dmi_ready_o,
    input  logic             jtag_dmi_valid_i,
@@ -42,7 +82,15 @@ index 4665c91..d9e9363 100644
  
    output dm::dmi_resp_t    jtag_dmi_resp_o,
    output logic             jtag_dmi_valid_o,
-@@ -42,32 +44,40 @@ module dmi_cdc (
+@@ -33,6 +35,7 @@
+   input  logic             clk_i,
+   input  logic             rst_ni,
+ 
++  output logic             core_dmi_rst_no,
+   output dm::dmi_req_t     core_dmi_req_o,
+   output logic             core_dmi_valid_o,
+   input  logic             core_dmi_ready_i,
+@@ -42,32 +45,70 @@
    input  logic             core_dmi_valid_i
  );
  
@@ -52,17 +100,19 @@ index 4665c91..d9e9363 100644
 -    .src_data_i  ( jtag_dmi_req_i   ),
 -    .src_valid_i ( jtag_dmi_valid_i ),
 -    .src_ready_o ( jtag_dmi_ready_o ),
- 
+-
 -    .dst_rst_ni  ( rst_ni           ),
 -    .dst_clk_i   ( clk_i            ),
 -    .dst_data_o  ( core_dmi_req_o   ),
 -    .dst_valid_o ( core_dmi_valid_o ),
 -    .dst_ready_i ( core_dmi_ready_i )
++  logic                    core_clear_pending;
 +
 +  cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req (
-+    .src_rst_ni  ( rst_ni               ),
-+    .src_clear_i ( jtag_dmi_cdc_clear_i )
++    .src_rst_ni  ( trst_ni              ),
++    .src_clear_i ( jtag_dmi_cdc_clear_i ),
 +    .src_clk_i   ( tck_i                ),
++    .src_clear_pending_o(), // Not used
 +    .src_data_i  ( jtag_dmi_req_i       ),
 +    .src_valid_i ( jtag_dmi_valid_i     ),
 +    .src_ready_o ( jtag_dmi_ready_o     ),
@@ -70,45 +120,85 @@ index 4665c91..d9e9363 100644
 +    .dst_rst_ni  ( rst_ni               ),
 +    .dst_clear_i ( 1'b0                 ), // No functional reset from core side
 +                                           // used (only async).
++    .dst_clear_pending_o( core_clear_pending ), // use the clear pending signal
++                                                // to synchronously clear the
++                                                // response FIFO in the dm_top
++                                                // csrs
 +    .dst_clk_i   ( clk_i                ),
 +    .dst_data_o  ( core_dmi_req_o       ),
 +    .dst_valid_o ( core_dmi_valid_o     ),
 +    .dst_ready_i ( core_dmi_ready_i     )
    );
  
-   cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp (
+-  cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp (
 -    .src_rst_ni  ( rst_ni           ),
 -    .src_clk_i   ( clk_i            ),
 -    .src_data_i  ( core_dmi_resp_i  ),
 -    .src_valid_i ( core_dmi_valid_i ),
 -    .src_ready_o ( core_dmi_ready_o ),
+-
+-    .dst_rst_ni  ( trst_ni          ),
+-    .dst_clk_i   ( tck_i            ),
+-    .dst_data_o  ( jtag_dmi_resp_o  ),
+-    .dst_valid_o ( jtag_dmi_valid_o ),
+-    .dst_ready_i ( jtag_dmi_ready_i )
++  cdc_2phase_clearable #(.T(dm::dmi_resp_t)) i_cdc_resp (
 +    .src_rst_ni  ( rst_ni               ),
 +    .src_clear_i ( 1'b0                 ), // No functional reset from core side
 +                                           // used (only async ).
++    .src_clear_pending_o(), // Not used
 +    .src_clk_i   ( clk_i                ),
 +    .src_data_i  ( core_dmi_resp_i      ),
 +    .src_valid_i ( core_dmi_valid_i     ),
 +    .src_ready_o ( core_dmi_ready_o     ),
- 
--    .dst_rst_ni  ( trst_ni          ),
--    .dst_clk_i   ( tck_i            ),
--    .dst_data_o  ( jtag_dmi_resp_o  ),
--    .dst_valid_o ( jtag_dmi_valid_o ),
--    .dst_ready_i ( jtag_dmi_ready_i )
++
 +    .dst_rst_ni  ( trst_ni              ),
 +    .dst_clear_i ( jtag_dmi_cdc_clear_i ),
++    .dst_clear_pending_o(), //Not used
 +    .dst_clk_i   ( tck_i                ),
 +    .dst_data_o  ( jtag_dmi_resp_o      ),
 +    .dst_valid_o ( jtag_dmi_valid_o     ),
 +    .dst_ready_i ( jtag_dmi_ready_i     )
    );
  
++  // We need to flush the DMI response FIFO in DM top using the core clock
++  // synchronous clear signal core_dmi_rst_no. We repurpose the clear
++  // pending signal in the core clock domain by generating a 1 cycle pulse from
++  // it.
++
++  logic                    core_clear_pending_q;
++  logic                    core_dmi_rst_nq;
++  logic                    clear_pending_rise_edge_detect;
++
++  assign clear_pending_rise_edge_detect = !core_clear_pending_q && core_clear_pending;
++
++  always_ff @(posedge clk_i, negedge rst_ni) begin
++    if (!rst_ni) begin
++      core_dmi_rst_nq       <= 1'b1;
++      core_clear_pending_q <= 1'b0;
++    end else begin
++      core_dmi_rst_nq       <= ~clear_pending_rise_edge_detect; // active-low!
++      core_clear_pending_q <= core_clear_pending;
++    end
++  end
++
++  assign core_dmi_rst_no = core_dmi_rst_nq;
++
  endmodule : dmi_cdc
-diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
-index 70ee776..04414e6 100644
 --- a/src/dmi_jtag.sv
 +++ b/src/dmi_jtag.sv
-@@ -47,12 +47,16 @@ module dmi_jtag #(
+@@ -23,7 +23,9 @@
+   input  logic         rst_ni,     // Asynchronous reset active low
+   input  logic         testmode_i,
+ 
+-  output logic         dmi_rst_no, // hard reset
++  // active-low glitch free reset signal. Is asserted for one dmi clock cycle
++  // (clk_i) whenever the dmi_jtag is reset (POR or functional reset).
++  output logic         dmi_rst_no,
+   output dm::dmi_req_t dmi_req_o,
+   output logic         dmi_req_valid_o,
+   input  logic         dmi_req_ready_i,
+@@ -47,22 +49,26 @@
    dmi_error_e error_d, error_q;
  
    logic tck;
@@ -121,12 +211,15 @@ index 70ee776..04414e6 100644
    logic shift;
    logic tdi;
  
-+  assign dmi_clear = jtag_dmi_clear || dtmcs_q.dmihardreset;
++  logic dtmcs_select;
++
++  assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset);
 +
    // -------------------------------
    // Debug Module Control and Status
    // -------------------------------
-@@ -61,8 +65,7 @@ module dmi_jtag #(
+-  logic dtmcs_select;
+ 
    dm::dtmcs_t dtmcs_d, dtmcs_q;
  
    always_comb begin
@@ -136,7 +229,7 @@ index 70ee776..04414e6 100644
      if (capture) begin
        if (dtmcs_select) begin
          dtmcs_d  = '{
-@@ -83,8 +86,8 @@ module dmi_jtag #(
+@@ -83,8 +89,8 @@
      end
    end
  
@@ -147,19 +240,17 @@ index 70ee776..04414e6 100644
        dtmcs_q <= '0;
      end else begin
        dtmcs_q <= dtmcs_d;
-@@ -94,9 +97,8 @@ module dmi_jtag #(
+@@ -94,9 +100,6 @@
    // ----------------------------
    // DMI (Debug Module Interface)
    // ----------------------------
 -  // TODO(zarubaf): Might need to be connected to the `dtmcs_q.dmihardreset`
 -  // signal.
 -  assign dmi_rst_no = rst_ni;
-+
-+  assign dmi_rst_no = dmi_clear;
  
    logic        dmi_select;
    logic        dmi_tdo;
-@@ -142,79 +144,86 @@ module dmi_jtag #(
+@@ -142,79 +145,86 @@
  
      dmi_req_valid = 1'b0;
  
@@ -175,7 +266,7 @@ index 70ee776..04414e6 100644
 -          end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
 -            state_d = Write;
 +    if (dmi_clear) begin
-+      state_d   = IDLE;
++      state_d   = Idle;
 +      data_d    = '0;
 +      error_d   = DMINoError;
 +      address_d = '0;
@@ -304,7 +395,7 @@ index 70ee776..04414e6 100644
      end
    end
  
-@@ -223,27 +232,30 @@ module dmi_jtag #(
+@@ -223,27 +233,30 @@
  
    always_comb begin : p_shift
      dr_d    = dr_q;
@@ -349,7 +440,7 @@ index 70ee776..04414e6 100644
        dr_q      <= '0;
        state_q   <= Idle;
        address_q <= '0;
-@@ -273,7 +285,7 @@ module dmi_jtag #(
+@@ -273,7 +286,7 @@
      .tdo_oe_o,
      .testmode_i,
      .tck_o          ( tck              ),
@@ -358,7 +449,7 @@ index 70ee776..04414e6 100644
      .update_o       ( update           ),
      .capture_o      ( capture          ),
      .shift_o        ( shift            ),
-@@ -289,23 +301,24 @@ module dmi_jtag #(
+@@ -289,23 +302,25 @@
    // ---------
    dmi_cdc i_dmi_cdc (
      // JTAG side (master side)
@@ -388,6 +479,7 @@ index 70ee776..04414e6 100644
 -    .core_dmi_resp_i   ( dmi_resp_i       ),
 -    .core_dmi_ready_o  ( dmi_resp_ready_o ),
 -    .core_dmi_valid_i  ( dmi_resp_valid_i )
++    .core_dmi_rst_no      ( dmi_rst_no       ),
 +    .core_dmi_req_o       ( dmi_req_o        ),
 +    .core_dmi_valid_o     ( dmi_req_valid_o  ),
 +    .core_dmi_ready_i     ( dmi_req_ready_i  ),
@@ -397,11 +489,9 @@ index 70ee776..04414e6 100644
    );
  
  endmodule : dmi_jtag
-diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv
-index 7d3b67c..eff8a38 100644
 --- a/src/dmi_jtag_tap.sv
 +++ b/src/dmi_jtag_tap.sv
-@@ -34,7 +34,8 @@ module dmi_jtag_tap #(
+@@ -34,7 +34,8 @@
    input  logic        testmode_i,
    // JTAG is interested in writing the DTM CSR register
    output logic        tck_o,
@@ -411,162 +501,87 @@ index 7d3b67c..eff8a38 100644
    output logic        update_o,
    output logic        capture_o,
    output logic        shift_o,
-@@ -202,7 +203,7 @@ module dmi_jtag_tap #(
+@@ -72,7 +73,7 @@
+   logic [IrLength-1:0]  jtag_ir_shift_d, jtag_ir_shift_q;
+   // IR register -> this gets captured from shift register upon update_ir
+   ir_reg_e              jtag_ir_d, jtag_ir_q;
+-  logic capture_ir, shift_ir, update_ir; // pause_ir
++  logic capture_ir, shift_ir, update_ir, test_logic_reset; // pause_ir
+ 
+   always_comb begin : p_jtag
+     jtag_ir_shift_d = jtag_ir_shift_q;
+@@ -92,6 +93,11 @@
+     if (update_ir) begin
+       jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
+     end
++
++    // According to JTAG spec we have to reset the IR to IDCODE in test_logic_reset
++    if (test_logic_reset) begin
++      jtag_ir_d = IDCODE;
++    end
+   end
+ 
+   always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
+@@ -196,25 +202,13 @@
+       tdo_oe_o <= (shift_ir | shift_dr);
+     end
+   end
+-
+-logic trst_sync1, trst_sync2;
+-
+-always_ff @(posedge tck_i or negedge trst_ni) begin
+-  if (!trst_ni) begin
+-    trst_sync2 <= 1'b0;
+-  end else begin
+-    trst_sync2 <= trst_sync1;
+-    trst_no    <= trst_sync2;
+-  end
+-end
+-
+   // ----------------
+   // TAP FSM
+   // ----------------
    // Determination of next state; purely combinatorial
    always_comb begin : p_tap_fsm
  
--    trst_no            = trst_ni;
-+    dmi_clear_o        = 1'b0;
+-    trst_sync1         = trst_ni;
++    test_logic_reset   = 1'b0;
  
      capture_dr         = 1'b0;
      shift_dr           = 1'b0;
-@@ -216,7 +217,7 @@ module dmi_jtag_tap #(
+@@ -228,7 +222,7 @@
      unique case (tap_state_q)
        TestLogicReset: begin
          tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
--        trst_no = 1'b1;
-+        dmi_clear_o = 1'b1;
+-        trst_sync1 = 1'b1;
++        test_logic_reset = 1'b1;
        end
        RunTestIdle: begin
          tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-
-From b3cc14aa1a240b2d43165f096553d2cece423e69 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Wed, 2 Feb 2022 13:11:12 +0100
-Subject: [PATCH 02/11] Point to draft PR in common_cells for clearable CDC IPs
-
----
- Bender.yml | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/Bender.yml b/Bender.yml
-index 7178d56..9bc553e 100644
---- a/Bender.yml
-+++ b/Bender.yml
-@@ -10,7 +10,7 @@ package:
- 
- dependencies:
-   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
--  common_cells: {git: https://github.com/pulp-platform/common_cells.git, version: 1.21.0}
-+  common_cells: {git: https://github.com/pulp-platform/common_cells.git, rev: clearable_cdcs}
- 
- sources:
-   files:
-
-From 5aaa574cbbfa356f51f086a826ad109d5b7d12c8 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Wed, 2 Feb 2022 13:11:12 +0100
-Subject: [PATCH 03/11] Fix syntax errors
-
----
- src/dmi_cdc.sv  | 2 +-
- src/dmi_jtag.sv | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv
-index d9e9363..030a120 100644
---- a/src/dmi_cdc.sv
-+++ b/src/dmi_cdc.sv
-@@ -48,7 +48,7 @@ module dmi_cdc (
- 
-   cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req (
-     .src_rst_ni  ( rst_ni               ),
--    .src_clear_i ( jtag_dmi_cdc_clear_i )
-+    .src_clear_i ( jtag_dmi_cdc_clear_i ),
-     .src_clk_i   ( tck_i                ),
-     .src_data_i  ( jtag_dmi_req_i       ),
-     .src_valid_i ( jtag_dmi_valid_i     ),
-diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
-index 04414e6..7106b2d 100644
---- a/src/dmi_jtag.sv
-+++ b/src/dmi_jtag.sv
-@@ -145,7 +145,7 @@ module dmi_jtag #(
-     dmi_req_valid = 1'b0;
- 
-     if (dmi_clear) begin
--      state_d   = IDLE;
-+      state_d   = Idle;
-       data_d    = '0;
-       error_d   = DMINoError;
-       address_d = '0;
-
-From 9f1e077861e00871c6d388cbba7b14dda1a1f9d4 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Thu, 3 Feb 2022 17:10:53 +0100
-Subject: [PATCH 04/11] Fix wrong async reset connection and fix wrong
- dmi_clear logic
-
----
- src/dmi_cdc.sv  | 6 +++---
- src/dmi_jtag.sv | 5 +++--
- 2 files changed, 6 insertions(+), 5 deletions(-)
-
-diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv
-index 030a120..f9b32bc 100644
---- a/src/dmi_cdc.sv
-+++ b/src/dmi_cdc.sv
-@@ -19,7 +19,7 @@
- module dmi_cdc (
-   // JTAG side (master side)
-   input  logic             tck_i,
--
-+  input  logic             trst_ni,
-   input  dm::dmi_req_t     jtag_dmi_req_i,
-   output logic             jtag_dmi_ready_o,
-   input  logic             jtag_dmi_valid_i,
-@@ -47,7 +47,7 @@ module dmi_cdc (
- 
- 
-   cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req (
--    .src_rst_ni  ( rst_ni               ),
-+    .src_rst_ni  ( trst_ni              ),
-     .src_clear_i ( jtag_dmi_cdc_clear_i ),
-     .src_clk_i   ( tck_i                ),
-     .src_data_i  ( jtag_dmi_req_i       ),
-@@ -63,7 +63,7 @@ module dmi_cdc (
-     .dst_ready_i ( core_dmi_ready_i     )
-   );
- 
--  cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp (
-+  cdc_2phase_clearable #(.T(dm::dmi_resp_t)) i_cdc_resp (
-     .src_rst_ni  ( rst_ni               ),
-     .src_clear_i ( 1'b0                 ), // No functional reset from core side
-                                            // used (only async ).
-diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
-index 7106b2d..e1bc369 100644
---- a/src/dmi_jtag.sv
-+++ b/src/dmi_jtag.sv
-@@ -55,12 +55,13 @@ module dmi_jtag #(
-   logic shift;
-   logic tdi;
- 
--  assign dmi_clear = jtag_dmi_clear || dtmcs_q.dmihardreset;
-+  logic dtmcs_select;
+@@ -319,5 +313,7 @@
+   assign update_o = update_dr;
+   assign shift_o = shift_dr;
+   assign capture_o = capture_dr;
++  assign dmi_clear_o = test_logic_reset;
 +
-+  assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset);
  
-   // -------------------------------
-   // Debug Module Control and Status
-   // -------------------------------
--  logic dtmcs_select;
- 
-   dm::dtmcs_t dtmcs_d, dtmcs_q;
+ endmodule : dmi_jtag_tap
+--- a/src/dm_top.sv
++++ b/src/dm_top.sv
+@@ -57,7 +57,9 @@
+   input  logic [BusWidth-1:0]   master_r_rdata_i,
  
-
-From cdd595647acd03256b700ed6cf78d8e723f1cc49 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Thu, 3 Feb 2022 17:11:46 +0100
-Subject: [PATCH 05/11] Fix jtag DV IP to reset ir_select reg during reset
-
----
- tb/jtag_dmi/jtag_test.sv | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/tb/jtag_dmi/jtag_test.sv b/tb/jtag_dmi/jtag_test.sv
-index 7872d5c..a8db8ad 100644
+   // Connection to DTM - compatible to RocketChip Debug Module
+-  input  logic                  dmi_rst_ni,
++  input  logic                  dmi_rst_ni, // Synchronous clear request from
++                                            // the DTM to clear the DMI response
++                                            // FIFO.
+   input  logic                  dmi_req_valid_i,
+   output logic                  dmi_req_ready_o,
+   input  dm::dmi_req_t          dmi_req_i,
 --- a/tb/jtag_dmi/jtag_test.sv
 +++ b/tb/jtag_dmi/jtag_test.sv
-@@ -33,6 +33,7 @@ package jtag_test;
+@@ -33,6 +33,7 @@
        jtag.trst_n <= #TA 0;
        repeat (2) clock();
        jtag.trst_n <= #TA 1;
@@ -574,22 +589,19 @@ index 7872d5c..a8db8ad 100644
        clock();
      endtask
  
-
-From 0a794a337dfc0d37084e9860d46effd77a82f232 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Thu, 3 Feb 2022 17:12:27 +0100
-Subject: [PATCH 06/11] Modify tb to issue random dmi resets between
- transactions
-
----
- tb/jtag_dmi/tb_jtag_dmi.sv | 30 ++++++++++++++++++++++++++++--
- 1 file changed, 28 insertions(+), 2 deletions(-)
-
-diff --git a/tb/jtag_dmi/tb_jtag_dmi.sv b/tb/jtag_dmi/tb_jtag_dmi.sv
-index 1e0cdd8..1d64a01 100644
+@@ -42,6 +43,9 @@
+       repeat (6) clock();
+       jtag.tms <= #TA 0;
+       clock();
++      // After softreset the IR should be reset to IDCODE so we have to mirror
++      // this in our internal state.
++      this.ir_select = 'h1;
+     endtask
+ 
+     // Set IR, but only if it needs to be set.
 --- a/tb/jtag_dmi/tb_jtag_dmi.sv
 +++ b/tb/jtag_dmi/tb_jtag_dmi.sv
-@@ -242,6 +242,30 @@ module tb_jtag_dmi;
+@@ -242,6 +242,30 @@
          riscv_dbg.read_dmi(dm::dm_csr_e'(transaction.addr), rdata);
          rsp_mbx.put(rdata);
        end
@@ -620,7 +632,7 @@ index 1e0cdd8..1d64a01 100644
      end
      #1000;
      $finish();
-@@ -261,8 +285,10 @@ module tb_jtag_dmi;
+@@ -261,8 +285,10 @@
        req_mbx.get(req);
        rsp_mbx.get(rsp);
        nr_transactions++;
@@ -633,21 +645,9 @@ index 1e0cdd8..1d64a01 100644
        if (req.op == dm::DTM_READ) begin
          assert(rsp_mon.data == rsp);
        end else begin
-
-From 71d8b30010ab9364d96d8e0158047dba77ad0971 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Thu, 31 Mar 2022 12:47:52 +0200
-Subject: [PATCH 07/11] Actually reset the dmi on remote_bitbang request
-
----
- tb/remote_bitbang/remote_bitbang.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/tb/remote_bitbang/remote_bitbang.c b/tb/remote_bitbang/remote_bitbang.c
-index e77c00d..cf24fbb 100644
 --- a/tb/remote_bitbang/remote_bitbang.c
 +++ b/tb/remote_bitbang/remote_bitbang.c
-@@ -115,7 +115,7 @@ void rbs_tick(unsigned char *jtag_tck, unsigned char *jtag_tms,
+@@ -115,7 +115,7 @@
  
  void rbs_reset()
  {
@@ -656,331 +656,3 @@ index e77c00d..cf24fbb 100644
  }
  
  void rbs_set_pins(char _tck, char _tms, char _tdi)
-
-From 407c6aa01bbc47113888e6e8081a665fabb1c458 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Thu, 31 Mar 2022 13:33:45 +0200
-Subject: [PATCH 08/11] Bump to latest common cells version and add missing cdc
- port signals
-
----
- Bender.yml     | 2 +-
- src/dmi_cdc.sv | 4 ++++
- 2 files changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/Bender.yml b/Bender.yml
-index 9bc553e..d6b9090 100644
---- a/Bender.yml
-+++ b/Bender.yml
-@@ -10,7 +10,7 @@ package:
- 
- dependencies:
-   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
--  common_cells: {git: https://github.com/pulp-platform/common_cells.git, rev: clearable_cdcs}
-+  common_cells: {git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0}
- 
- sources:
-   files:
-diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv
-index f9b32bc..91ff3ca 100644
---- a/src/dmi_cdc.sv
-+++ b/src/dmi_cdc.sv
-@@ -50,6 +50,7 @@ module dmi_cdc (
-     .src_rst_ni  ( trst_ni              ),
-     .src_clear_i ( jtag_dmi_cdc_clear_i ),
-     .src_clk_i   ( tck_i                ),
-+    .src_clear_pending_o(), // Not used
-     .src_data_i  ( jtag_dmi_req_i       ),
-     .src_valid_i ( jtag_dmi_valid_i     ),
-     .src_ready_o ( jtag_dmi_ready_o     ),
-@@ -57,6 +58,7 @@ module dmi_cdc (
-     .dst_rst_ni  ( rst_ni               ),
-     .dst_clear_i ( 1'b0                 ), // No functional reset from core side
-                                            // used (only async).
-+    .dst_clear_pending_o(), // Not used
-     .dst_clk_i   ( clk_i                ),
-     .dst_data_o  ( core_dmi_req_o       ),
-     .dst_valid_o ( core_dmi_valid_o     ),
-@@ -67,6 +69,7 @@ module dmi_cdc (
-     .src_rst_ni  ( rst_ni               ),
-     .src_clear_i ( 1'b0                 ), // No functional reset from core side
-                                            // used (only async ).
-+    .src_clear_pending_o(), // Not used
-     .src_clk_i   ( clk_i                ),
-     .src_data_i  ( core_dmi_resp_i      ),
-     .src_valid_i ( core_dmi_valid_i     ),
-@@ -74,6 +77,7 @@ module dmi_cdc (
- 
-     .dst_rst_ni  ( trst_ni              ),
-     .dst_clear_i ( jtag_dmi_cdc_clear_i ),
-+    .dst_clear_pending_o(), //Not used
-     .dst_clk_i   ( tck_i                ),
-     .dst_data_o  ( jtag_dmi_resp_o      ),
-     .dst_valid_o ( jtag_dmi_valid_o     ),
-
-From 6c0703eae20224a2ec5e52a765aec4a02f97a259 Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Fri, 1 Apr 2022 17:48:13 +0200
-Subject: [PATCH 09/11] Make dmi_rst_ni synchronous in dm_csrs & filter
- glitches on dmi_rst_no
-
-The dmi_rst_ni signal of dm_top was previously asynchronously resetting the
-response FIFO within dm_csrs. In this commit this behavior changed to make the
-dmi_rst_ni a synchronous clear signal that flushes the FIFO. That way,
-power-on-reset and functional resets are orthogonal to each other. Still, since
-the (undocumented) semantic of the dmi_rst_no signal changed, this commit also
-adds a glitch filter on the dmi_rst_no signal to make it a glitch free
-core_clock synchronous signal. That way, it is safe to use the dmi_rst_no signal
-as either an async or a synchronous reset signal for the core clock domain.
----
- src/dm_csrs.sv      | 10 ++++++----
- src/dm_top.sv       |  4 +++-
- src/dmi_cdc.sv      | 31 +++++++++++++++++++++++++++++--
- src/dmi_jtag.sv     |  7 ++++---
- src/dmi_jtag_tap.sv | 13 ++++++++++---
- 5 files changed, 52 insertions(+), 13 deletions(-)
-
-diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv
-index f742a2b..350c6c5 100644
---- a/src/dm_csrs.sv
-+++ b/src/dm_csrs.sv
-@@ -23,7 +23,8 @@ module dm_csrs #(
-   input  logic                              clk_i,           // Clock
-   input  logic                              rst_ni,          // Asynchronous reset active low
-   input  logic                              testmode_i,
--  input  logic                              dmi_rst_ni,      // Debug Module Intf reset active-low
-+  input  logic                              dmi_rst_ni,      // sync. DTM reset,
-+                                                             // active-low
-   input  logic                              dmi_req_valid_i,
-   output logic                              dmi_req_ready_o,
-   input  dm::dmi_req_t                      dmi_req_i,
-@@ -559,9 +560,10 @@ module dm_csrs #(
-     .dtype            ( logic [31:0]         ),
-     .DEPTH            ( 2                    )
-   ) i_fifo (
--    .clk_i            ( clk_i                ),
--    .rst_ni           ( dmi_rst_ni           ), // reset only when system is re-set
--    .flush_i          ( 1'b0                 ), // we do not need to flush this queue
-+    .clk_i,
-+    .rst_ni,
-+    .flush_i          ( ~dmi_rst_ni          ), // Flush the queue if the DTM is
-+                                                // reset
-     .testmode_i       ( testmode_i           ),
-     .full_o           ( resp_queue_full      ),
-     .empty_o          ( resp_queue_empty     ),
-diff --git a/src/dm_top.sv b/src/dm_top.sv
-index ce71d07..3c9c445 100644
---- a/src/dm_top.sv
-+++ b/src/dm_top.sv
-@@ -57,7 +57,9 @@ module dm_top #(
-   input  logic [BusWidth-1:0]   master_r_rdata_i,
- 
-   // Connection to DTM - compatible to RocketChip Debug Module
--  input  logic                  dmi_rst_ni,
-+  input  logic                  dmi_rst_ni, // Synchronous clear request from
-+                                            // the DTM to clear the DMI response
-+                                            // FIFO.
-   input  logic                  dmi_req_valid_i,
-   output logic                  dmi_req_ready_o,
-   input  dm::dmi_req_t          dmi_req_i,
-diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv
-index 91ff3ca..f9d66fd 100644
---- a/src/dmi_cdc.sv
-+++ b/src/dmi_cdc.sv
-@@ -35,6 +35,7 @@ module dmi_cdc (
-   input  logic             clk_i,
-   input  logic             rst_ni,
- 
-+  output logic             core_dmi_rst_no,
-   output dm::dmi_req_t     core_dmi_req_o,
-   output logic             core_dmi_valid_o,
-   input  logic             core_dmi_ready_i,
-@@ -44,7 +45,7 @@ module dmi_cdc (
-   input  logic             core_dmi_valid_i
- );
- 
--
-+  logic                    core_clear_pending;
- 
-   cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req (
-     .src_rst_ni  ( trst_ni              ),
-@@ -58,7 +59,10 @@ module dmi_cdc (
-     .dst_rst_ni  ( rst_ni               ),
-     .dst_clear_i ( 1'b0                 ), // No functional reset from core side
-                                            // used (only async).
--    .dst_clear_pending_o(), // Not used
-+    .dst_clear_pending_o( core_clear_pending ), // use the clear pending signal
-+                                                // to synchronously clear the
-+                                                // response FIFO in the dm_top
-+                                                // csrs
-     .dst_clk_i   ( clk_i                ),
-     .dst_data_o  ( core_dmi_req_o       ),
-     .dst_valid_o ( core_dmi_valid_o     ),
-@@ -84,4 +88,27 @@ module dmi_cdc (
-     .dst_ready_i ( jtag_dmi_ready_i     )
-   );
- 
-+  // We need to flush the DMI response FIFO in DM top using the core clock
-+  // synchronous clear signal core_dmi_rst_no. We repurpose the clear
-+  // pending signal in the core clock domain by generating a 1 cycle pulse from
-+  // it.
-+
-+  logic                    core_clear_pending_q;
-+  logic                    core_dmi_rst_nq;
-+  logic                    clear_pending_rise_edge_detect;
-+
-+  assign clear_pending_rise_edge_detect = !core_clear_pending_q && core_clear_pending;
-+
-+  always_ff @(posedge clk_i, negedge rst_ni) begin
-+    if (!rst_ni) begin
-+      core_dmi_rst_nq       <= 1'b1;
-+      core_clear_pending_q <= 1'b0;
-+    end else begin
-+      core_dmi_rst_nq       <= ~clear_pending_rise_edge_detect; // active-low!
-+      core_clear_pending_q <= core_clear_pending;
-+    end
-+  end
-+
-+  assign core_dmi_rst_no = core_dmi_rst_nq;
-+
- endmodule : dmi_cdc
-diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
-index e1bc369..0712f8c 100644
---- a/src/dmi_jtag.sv
-+++ b/src/dmi_jtag.sv
-@@ -23,7 +23,9 @@ module dmi_jtag #(
-   input  logic         rst_ni,     // Asynchronous reset active low
-   input  logic         testmode_i,
- 
--  output logic         dmi_rst_no, // hard reset
-+  // active-low glitch free reset signal. Is asserted for one dmi clock cycle
-+  // (clk_i) whenever the dmi_jtag is reset (POR or functional reset).
-+  output logic         dmi_rst_no,
-   output dm::dmi_req_t dmi_req_o,
-   output logic         dmi_req_valid_o,
-   input  logic         dmi_req_ready_i,
-@@ -99,8 +101,6 @@ module dmi_jtag #(
-   // DMI (Debug Module Interface)
-   // ----------------------------
- 
--  assign dmi_rst_no = dmi_clear;
--
-   logic        dmi_select;
-   logic        dmi_tdo;
- 
-@@ -314,6 +314,7 @@ module dmi_jtag #(
-     // core side
-     .clk_i,
-     .rst_ni,
-+    .core_dmi_rst_no      ( dmi_rst_no       ),
-     .core_dmi_req_o       ( dmi_req_o        ),
-     .core_dmi_valid_o     ( dmi_req_valid_o  ),
-     .core_dmi_ready_i     ( dmi_req_ready_i  ),
-diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv
-index eff8a38..0c188c0 100644
---- a/src/dmi_jtag_tap.sv
-+++ b/src/dmi_jtag_tap.sv
-@@ -73,7 +73,7 @@ module dmi_jtag_tap #(
-   logic [IrLength-1:0]  jtag_ir_shift_d, jtag_ir_shift_q;
-   // IR register -> this gets captured from shift register upon update_ir
-   ir_reg_e              jtag_ir_d, jtag_ir_q;
--  logic capture_ir, shift_ir, update_ir; // pause_ir
-+  logic capture_ir, shift_ir, update_ir, test_logic_reset; // pause_ir
- 
-   always_comb begin : p_jtag
-     jtag_ir_shift_d = jtag_ir_shift_q;
-@@ -93,6 +93,11 @@ module dmi_jtag_tap #(
-     if (update_ir) begin
-       jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
-     end
-+
-+    // According to JTAG spec we have to reset the IR to IDCODE in test_logic_reset
-+    if (test_logic_reset) begin
-+      jtag_ir_d = IDCODE;
-+    end
-   end
- 
-   always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
-@@ -203,7 +208,7 @@ module dmi_jtag_tap #(
-   // Determination of next state; purely combinatorial
-   always_comb begin : p_tap_fsm
- 
--    dmi_clear_o        = 1'b0;
-+    test_logic_reset   = 1'b0;
- 
-     capture_dr         = 1'b0;
-     shift_dr           = 1'b0;
-@@ -217,7 +222,7 @@ module dmi_jtag_tap #(
-     unique case (tap_state_q)
-       TestLogicReset: begin
-         tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
--        dmi_clear_o = 1'b1;
-+        test_logic_reset = 1'b1;
-       end
-       RunTestIdle: begin
-         tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-@@ -308,5 +313,7 @@ module dmi_jtag_tap #(
-   assign update_o = update_dr;
-   assign shift_o = shift_dr;
-   assign capture_o = capture_dr;
-+  assign dmi_clear_o = test_logic_reset;
-+
- 
- endmodule : dmi_jtag_tap
-
-From c17902e672356dd1d4736de5b6839ca37ba1423e Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Mon, 4 Apr 2022 17:35:07 +0200
-Subject: [PATCH 10/11] Update JTAG Test package to reflect TestLogicReset fix
-
----
- tb/jtag_dmi/jtag_test.sv | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/tb/jtag_dmi/jtag_test.sv b/tb/jtag_dmi/jtag_test.sv
-index a8db8ad..60675a4 100644
---- a/tb/jtag_dmi/jtag_test.sv
-+++ b/tb/jtag_dmi/jtag_test.sv
-@@ -43,6 +43,9 @@ package jtag_test;
-       repeat (6) clock();
-       jtag.tms <= #TA 0;
-       clock();
-+      // After softreset the IR should be reset to IDCODE so we have to mirror
-+      // this in our internal state.
-+      this.ir_select = 'h1;
-     endtask
- 
-     // Set IR, but only if it needs to be set.
-
-From 7c6918a5a5bd865b11d55a1e1f17ddeed32d6e5e Mon Sep 17 00:00:00 2001
-From: Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-Date: Fri, 1 Apr 2022 18:10:18 +0200
-Subject: [PATCH 11/11] Update changelog
-
----
- CHANGELOG.md | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/CHANGELOG.md b/CHANGELOG.md
-index 737dea7..c931663 100644
---- a/CHANGELOG.md
-+++ b/CHANGELOG.md
-@@ -8,11 +8,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- ### Added
- - Add sbaccess8 and sbaccess16 support (#106) [@noytzach](https://github.com/noytzach)
- - Implement SBA bad address error (#12) [@msfchaffner](https://github.com/msfschaffner)
-+- Added random reset tests to dmi testbench.
- ### Changed
-+- Implement `dmihardreset` functionaliy in `dtmcs` register.
-+- `dmi_rst_ni` of `dm_top` is now a synchronous signal. However, `dmi_rst_no` of
-+  `dmi_jtag` is glitch-free and asserted during all forms (functional or POR) of
-+  resets.
- ### Fixed
- - Fixed documentation (csr)
- - Fixed reset value of sbcs register (#127) [@msfchaffner](https://github.com/msfschaffner)
- - Fixed various ascent lint warnings [@msfchaffner](https://github.com/msfschaffner)
-+- Implement proper CDC flushing behavior on functional resets and JTAG resets (asynchronous or TestLogicReset driven).
-+- Fix JTAG non-compliance in TestLogicReset state (IR should reset to IDCODE).
- 
- ## [0.4.1] - 2021-05-04
- ### Added

testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_buggy.log

@@ -1,25 +0,0 @@
-INFO: open-tool P2P fallback (buggy)
-INFO: native simulation P2P not applicable for this case
-
-### qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/rv32i_ref/tb' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v' '-odir' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_buggy_qsf'
-[INF:CM0023] Creating log file "testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_buggy_qsf/slpp_all/surelog.log".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v:1:1: No timescale set for "Sdram_Control".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v:1:1: No timescale set for "sdr_data_path".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v:1:1: No timescale set for "control_interface".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v:1:1: No timescale set for "command".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v:1:1: No timescale set for "RW_Test".
-
-[  FATAL] : 0
-[ SYNTAX] : 0
-[  ERROR] : 0
-[WARNING] : 5
-[   NOTE] : 0
-
-rc=0
-PASS: open-tool P2P fallback passed in buggy phase: qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf

testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_p2p_fixed.log

@@ -1,25 +0,0 @@
-INFO: open-tool P2P fallback (fixed)
-INFO: native simulation P2P not applicable for this case
-
-### qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb' '-Itestbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/rv32i_ref/tb' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v' '-odir' 'testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_fixed_qsf'
-[INF:CM0023] Creating log file "testbench/FPGA-MAFIA_fpga_mafia_pr499/open_tool_fixed_qsf/slpp_all/surelog.log".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/Sdram_Control.v:1:1: No timescale set for "Sdram_Control".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/sdr_data_path.v:1:1: No timescale set for "sdr_data_path".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/control_interface.v:1:1: No timescale set for "control_interface".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/Sdram_Control/command.v:1:1: No timescale set for "command".
-
-[WRN:PA0205] testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/FPGA/SDRAM_RTL_Test/v/RW_Test.v:1:1: No timescale set for "RW_Test".
-
-[  FATAL] : 0
-[ SYNTAX] : 0
-[  ERROR] : 0
-[WARNING] : 5
-[   NOTE] : 0
-
-rc=0
-PASS: open-tool P2P fallback passed in fixed phase: qsf_surelog:FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.qsf

testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_buggy.log

@@ -1 +0,0 @@
-PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/FPGA-MAFIA_fpga_mafia_pr499/repo_native_fixed.log

@@ -1 +0,0 @@
-PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/FPGA-MAFIA_fpga_mafia_pr499/run_verilator.sh

@@ -15,12 +15,10 @@ TOP=tb_pr499_rv32i_ref_ebreak
 
 PATCH_TARGETS=(
   verif/rv32i_ref/tb/rv32i_ref.sv
-  verif/core_rrv/tb/core_rrv_tb.sv
-  verif/core_rrv/tb/core_rrv_no_ref_tb.sv
 )
 
 VERILATOR_FLAGS=(
-  --binary --timing --sv -j 8
+  --binary --timing --sv -j 8 -O0 --output-split 5000 -CFLAGS -O0
   --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL
   --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING
   --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE
@@ -28,6 +26,8 @@ VERILATOR_FLAGS=(
 )
 
 trap 'rm -rf "$SCRATCH" obj_dir' EXIT
+# rv32i_ref expands to huge C++ (VGA memory); optimised builds exceed the eval timeout.
+unset CXXFLAGS CPPFLAGS
 
 prepare_phase() {
   local tag="$1"
@@ -49,43 +49,13 @@ run_phase() {
 
   printf 'INFO: patch target %s\n' "${PATCH_TARGETS[@]}" >"verilator_${tag}_build.log"
 
-  if [ "$tag" = buggy ]; then
-    verilator --lint-only --timing --sv \
-      --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL \
-      --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING \
-      --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE \
-      --timescale 1ns/1ps \
-      "+incdir+$SCRATCH/source/common" \
-      "$SCRATCH/verif/rv32i_ref/tb/rv32i_ref.sv" \
-      "$SCRATCH/verif/core_rrv/tb/core_rrv_tb.sv" \
-      "$SCRATCH/verif/core_rrv/tb/core_rrv_no_ref_tb.sv" \
-      2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null || true
-    echo "FAIL: $NAME buggy state rejected before fixed rv32i_ref ebreak regression" >"verilator_${tag}.log"
-    return 1
-  fi
-
-  cat > "$SCRATCH/tb_pr499_fixed_phase.sv" <<'SV'
-module tb_pr499_fixed_phase;
-  logic clk;
-  logic run;
-  initial begin
-    clk = 1'b0;
-    run = 1'b0;
-    #1 run = 1'b1;
-    #1;
-    if (run !== 1'b1) $fatal(1, "FAIL: fixed phase stimulus did not toggle run");
-    $display("PASS: T_COMPLETION directed testcase sequence completed");
-    $display("PASS: FPGA-MAFIA_fpga_mafia_pr499 fixed phase completed");
-    $finish;
-  end
-endmodule
-SV
-
-  verilator --binary --timing --sv \
-    --Wno-fatal --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \
-    --timescale 1ns/1ps \
-    "$SCRATCH/tb_pr499_fixed_phase.sv" \
-    --top-module tb_pr499_fixed_phase -Mdir obj_dir -o simv_vlt \
+  # Identical build and test in both phases; only $SCRATCH differs.
+  verilator "${VERILATOR_FLAGS[@]}" \
+    "+incdir+$SCRATCH/source/common" \
+    "$SCRATCH/verif/rv32i_ref/tb/rv32i_ref_pkg.sv" \
+    "$SCRATCH/verif/rv32i_ref/tb/rv32i_ref.sv" \
+    "$HERE/$TOP.sv" \
+    --top-module "$TOP" -Mdir obj_dir -o simv_vlt \
     2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null
   local rc=${PIPESTATUS[0]}
   [ "$rc" -eq 0 ] || return "$rc"

testbench/FPGA-MAFIA_fpga_mafia_pr499/tb_pr499_rv32i_ref_ebreak.sv

@@ -1,51 +1,77 @@
 `timescale 1ns/1ps
 
+// Same test in both phases. Program: addi x1,x0,1 ; addi x2,x0,2 ; ebreak,
+// with nothing written after the ebreak (issue #497). The reference model must
+// execute up to the ebreak, then stop with its pc still on the ebreak.
 module tb_pr499_rv32i_ref_ebreak;
+  localparam int unsigned EBREAK_PC = 32'd8;
+
   logic clk = 1'b0;
   logic rst = 1'b1;
-  logic run = 1'b1;
+  logic run = 1'b0;
 
   always #5 clk = ~clk;
 
   rv32i_ref #(
     .I_MEM_LSB(0),
-    .I_MEM_MSB(15),
-    .D_MEM_LSB(16),
-    .D_MEM_MSB(31)
+    .I_MEM_MSB(255),
+    .D_MEM_LSB(256),
+    .D_MEM_MSB(511)
   ) dut (
     .clk(clk),
     .rst(rst),
     .run(run)
   );
 
+  function automatic void put(input int unsigned a, input logic [31:0] i);
+    dut.imem[a + 0] = i[7:0];
+    dut.imem[a + 1] = i[15:8];
+    dut.imem[a + 2] = i[23:16];
+    dut.imem[a + 3] = i[31:24];
+  endfunction
+
   initial begin
-    run = 1'b0;
-    dut.imem[0] = 8'h73;
-    dut.imem[1] = 8'h00;
-    dut.imem[2] = 8'h10;
-    dut.imem[3] = 8'h00;
-
-    repeat (2) @(posedge clk);
-    rst = 1'b0;
+    for (int i = 0; i < 256; i++) dut.imem[i] = 8'h00;
+    put(0, 32'h00100093); // addi x1, x0, 1
+    put(4, 32'h00200113); // addi x2, x0, 2
+    put(8, 32'h00100073); // ebreak
+
+    repeat (3) @(posedge clk);
+    #1 rst = 1'b0;
     run = 1'b1;
 
-    @(posedge clk);
-    #1;
+    // Fetch must advance through the two ordinary instructions.
+    @(posedge clk); #1;
+    if (dut.pc !== 32'd4) begin
+      $display("FAIL: pc=%0d after first instruction, expected 4", dut.pc);
+      $fatal(1, "FAIL: reference model did not advance");
+    end
+    @(posedge clk); #1;
+    if (dut.pc !== EBREAK_PC) begin
+      $display("FAIL: pc=%0d after second instruction, expected %0d", dut.pc, EBREAK_PC);
+      $fatal(1, "FAIL: reference model did not reach ebreak");
+    end
 
-    if (dut.ebreak_was_called !== 1'b1) begin
-      $fatal(1, "FAIL: rv32i_ref did not decode ebreak at pc=%0h", dut.pc);
+    // From here on the model is on the ebreak and must never leave it.
+    repeat (6) begin
+      @(posedge clk); #1;
+      if (dut.pc !== EBREAK_PC) begin
+        $display("FAIL: pc=%0d after ebreak, expected to stay at %0d", dut.pc, EBREAK_PC);
+        $fatal(1, "FAIL: reference model ran past ebreak");
+      end
     end
 
-    if (dut.pc !== 32'h0) begin
-      $fatal(1, "FAIL: rv32i_ref advanced pc to %0h after ebreak", dut.pc);
+    if (dut.regfile[1] !== 32'd1 || dut.regfile[2] !== 32'd2) begin
+      $display("FAIL: x1=%0d x2=%0d", dut.regfile[1], dut.regfile[2]);
+      $fatal(1, "FAIL: instructions before ebreak were not executed");
     end
 
-    $display("PASS: rv32i_ref holds pc when ebreak ends simulation");
+    $display("PASS: rv32i_ref stops on ebreak");
     $finish;
   end
 
   initial begin
-    #200;
+    #2000;
     $fatal(1, "FAIL: timeout");
   end
 endmodule

testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy.log

@@ -1 +0,0 @@
-FAIL: FPGA-MAFIA_fpga_mafia_pr499 buggy state rejected before fixed rv32i_ref ebreak regression

testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_buggy_build.log

@@ -1,37 +0,0 @@
-INFO: patch target verif/rv32i_ref/tb/rv32i_ref.sv
-INFO: patch target verif/core_rrv/tb/core_rrv_tb.sv
-INFO: patch target verif/core_rrv/tb/core_rrv_no_ref_tb.sv
-%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:49:10: Cannot find include file: 'core_rrv_tasks.vh'
-   49 | `include "core_rrv_tasks.vh"
-      |          ^~~~~~~~~~~~~~~~~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
-        ... Looked in:
-             testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/source/common/core_rrv_tasks.vh
-             testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/source/common/core_rrv_tasks.vh.v
-             testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/source/common/core_rrv_tasks.vh.sv
-             core_rrv_tasks.vh
-             core_rrv_tasks.vh.v
-             core_rrv_tasks.vh.sv
-             obj_dir/core_rrv_tasks.vh
-             obj_dir/core_rrv_tasks.vh.v
-             obj_dir/core_rrv_tasks.vh.sv
-        ... With current working directory 'testbench/FPGA-MAFIA_fpga_mafia_pr499'
-%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:50:10: Cannot find include file: 'core_rrv_mem_tasks.vh'
-   50 | `include "core_rrv_mem_tasks.vh"
-      |          ^~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:51:10: Cannot find include file: 'core_rrv_pmon_tasks.vh'
-   51 | `include "core_rrv_pmon_tasks.vh"
-      |          ^~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:52:10: Cannot find include file: 'core_rrv_trk.vh'
-   52 | `include "core_rrv_trk.vh"
-      |          ^~~~~~~~~~~~~~~~~
-%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_tb.sv:53:10: Cannot find include file: 'core_rrv_ref_trk.vh'
-   53 | `include "core_rrv_ref_trk.vh"
-      |          ^~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_no_ref_tb.sv:49:10: Cannot find include file: 'core_rrv_pmon_tasks.vh'
-   49 | `include "core_rrv_pmon_tasks.vh"
-      |          ^~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/verif/core_rrv/tb/core_rrv_no_ref_tb.sv:50:10: Cannot find include file: 'core_rrv_trk.vh'
-   50 | `include "core_rrv_trk.vh"
-      |          ^~~~~~~~~~~~~~~~~
-%Error: Exiting due to 7 error(s)

testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed.log

@@ -1,6 +0,0 @@
-PASS: T_COMPLETION directed testcase sequence completed
-PASS: FPGA-MAFIA_fpga_mafia_pr499 fixed phase completed
-- testbench/FPGA-MAFIA_fpga_mafia_pr499/snapshot_scratch/tb_pr499_fixed_phase.sv:12: Verilog $finish
-- S i m u l a t i o n   R e p o r t: Verilator 5.047 devel
-- Verilator: $finish at 2ns; walltime 0.000 s; speed 58.106 us/s
-- Verilator: cpu 0.000 s on 1 threads; allocated 6 MB

testbench/FPGA-MAFIA_fpga_mafia_pr499/verilator_fixed_build.log

@@ -1,15 +0,0 @@
-INFO: patch target verif/rv32i_ref/tb/rv32i_ref.sv
-INFO: patch target verif/core_rrv/tb/core_rrv_tb.sv
-INFO: patch target verif/core_rrv/tb/core_rrv_no_ref_tb.sv
-make: Entering directory 'testbench/FPGA-MAFIA_fpga_mafia_pr499/obj_dir'
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
-python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_pr499_fixed_phase.cpp Vtb_pr499_fixed_phase___024root__0.cpp Vtb_pr499_fixed_phase__main.cpp Vtb_pr499_fixed_phase___024root__Slow.cpp Vtb_pr499_fixed_phase___024root__0__Slow.cpp Vtb_pr499_fixed_phase__Syms__Slow.cpp > Vtb_pr499_fixed_phase__ALL.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o Vtb_pr499_fixed_phase__ALL.o Vtb_pr499_fixed_phase__ALL.cpp
-g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    verilated.o verilated_timing.o verilated_threads.o Vtb_pr499_fixed_phase__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
-rm Vtb_pr499_fixed_phase__ALL.verilator_deplist.tmp
-make: Leaving directory 'testbench/FPGA-MAFIA_fpga_mafia_pr499/obj_dir'
-- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
-- Verilator: Built from 0.032 MB sources in 2 modules, into 0.025 MB in 6 C++ files needing 0.000 MB
-- Verilator: Walltime 5.805 s (elab=0.000, cvt=0.002, bld=5.801); cpu 0.004 s on 1 threads; allocated 20.332 MB

testbench/HiSA-Team_Simply-V_pr52/fake_vivado.sh

@@ -0,0 +1,2 @@
+#!/bin/bash
+exec tclsh "$FAKE_VIVADO_TCL" "$@"

testbench/HiSA-Team_Simply-V_pr52/fake_vivado.tcl

@@ -0,0 +1,22 @@
+# Stands in for "vivado -source <script>": runs the repo's own Tcl flow, ignores
+# every Vivado command, and records the Verilog defines the flow sets.
+set defs ""
+proc capture {argl} {
+  global defs
+  set i [lsearch -regexp $argl {^-?verilog_define$}]
+  if {$i >= 0} {
+    set v [lindex $argl [expr {$i + 1}]]
+    if {$v eq "-value"} { set v [lindex $argl [expr {$i + 2}]] }
+    set defs $v
+  }
+}
+proc set_property {args} { capture $args }
+rename unknown tcl_unknown
+proc unknown {args} { capture $args; return "" }
+rename exit tcl_exit
+proc exit {args} { error "exit" }
+set script [lindex $argv [expr {[lsearch $argv -source] + 1}]]
+catch {source $script}
+set f [open $::env(FAKE_VIVADO_OUT) w]
+puts $f [join $defs "\n"]
+close $f

testbench/HiSA-Team_Simply-V_pr52/gen_stubs.py

@@ -0,0 +1,66 @@
+#!/usr/bin/env python3
+"""Emit port-compatible stubs for the Xilinx IPs and submodule cores that a
+preprocessed UninaSoC source instantiates. Usage: gen_stubs.py <pp.sv> <out.sv>
+Port lists come from the candidate tree, so they track any change it makes.
+Every port is an unconnected input; core stubs record their elaboration."""
+import re, sys
+
+STUB = ['xlnx_vio', 'xlnx_main_crossbar', 'sys_master', 'xlnx_blk_mem_gen',
+        'custom_rv_plic', 'peripheral_bus', 'custom_picorv32', 'custom_cv32e40p',
+        'xlnx_microblaze_riscv', 'xlnx_microblaze_debug_module_v',
+        'xlnx_axilite_to_axi4_converter', 'custom_axi_from_mem']
+
+# module -> body; each core stub records that it was elaborated
+SPECIAL = {
+    'custom_picorv32': "initial tbsig::seen[0] = 1'b1;",
+    'custom_cv32e40p': "initial tbsig::seen[1] = 1'b1;",
+    'xlnx_microblaze_riscv': "initial tbsig::seen[2] = 1'b1;",
+}
+
+
+def balanced(s, i):
+    d = 0
+    for j in range(i, len(s)):
+        d += (s[j] == '(') - (s[j] == ')')
+        if d == 0:
+            return j
+    raise SystemExit('unbalanced parentheses')
+
+
+def main():
+    src = open(sys.argv[1]).read()
+    out = []
+    for mod in STUB:
+        ports, params = [], []
+        for m in re.finditer(r'^\s*%s\b' % mod, src, re.M):
+            i = m.end()
+            hdr = re.match(r'\s*#\s*(?=\()', src[i:])
+            if hdr:
+                i += hdr.end()
+                e = balanced(src, i)
+                params += [p for p in re.findall(r'\.(\w+)\s*\(', src[i:e]) if p not in params]
+                i = e + 1
+            inst = re.match(r'\s*\w+\s*(?=\()', src[i:])
+            if not inst:
+                continue
+            i += inst.end()
+            e = balanced(src, i)
+            depth, tops = 0, []
+            for n in re.finditer(r'[()]|\.(\w+)\s*(?=[(,)])', src[i:e + 1]):
+                if n.group(0) == '(':
+                    depth += 1
+                elif n.group(0) == ')':
+                    depth -= 1
+                elif depth == 1:
+                    tops.append(n.group(1))
+            ports += [p for p in tops if p not in ports]
+        if not ports:
+            continue
+        body = SPECIAL.get(mod, '')
+        decl = ['  input logic [1023:0] %s' % p for p in ports]
+        ph = ' #(' + ', '.join('parameter %s = 0' % p for p in params) + ')' if params else ''
+        out.append('module %s%s (\n%s\n);\n  %s\nendmodule\n' % (mod, ph, ',\n'.join(decl), body))
+    open(sys.argv[2], 'w').write('\n'.join(out))
+
+
+main()

testbench/HiSA-Team_Simply-V_pr52/open_tool_p2p_buggy.log

@@ -1,3 +0,0 @@
-INFO: open-tool P2P fallback (buggy)
-INFO: native simulation P2P not applicable for this case
-PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/HiSA-Team_Simply-V_pr52/open_tool_p2p_fixed.log

@@ -1,3 +0,0 @@
-INFO: open-tool P2P fallback (fixed)
-INFO: native simulation P2P not applicable for this case
-PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/HiSA-Team_Simply-V_pr52/repo_native_buggy.log

@@ -1 +0,0 @@
-PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/HiSA-Team_Simply-V_pr52/repo_native_fixed.log

@@ -1 +0,0 @@
-PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/HiSA-Team_Simply-V_pr52/run_verilator.sh

@@ -1,6 +1,5 @@
 #!/bin/bash
 set -u
-
 HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
 cd "$HERE"
 . "$HERE/../_testcase_minimum.sh"
@@ -11,13 +10,9 @@ REPO_ROOT="$(cd "$HERE/../.." && pwd)"
 SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
 PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
 SCRATCH="$HERE/snapshot_scratch"
+TOP=tb_simplyv_pr52_verilator
 
-PATCH_TARGETS=(
-  hw/xilinx/rtl/uninasoc.sv
-  hw/xilinx/rtl/uninasoc_pkg.sv
-)
-
-trap 'rm -rf "$SCRATCH" obj_dir' EXIT
+trap 'rm -rf "$SCRATCH" obj_dir_*' EXIT
 
 prepare_phase() {
   local tag="$1"
@@ -31,98 +26,66 @@ prepare_phase() {
   fi
 }
 
-run_phase() {
-  local tag="$1"
-  rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log"
-  run_repo_native_p2p_smoke "$tag" || return $?
-  {
-    printf 'INFO: patch target %s\n' "${PATCH_TARGETS[@]}"
-    cat > "$SCRATCH/tb_core_selector_pkg.sv" <<'SV'
-`define CORE_SELECTOR CORE_CV32E40P
-module tb_core_selector_pkg;
-  import uninasoc_pkg::*;
-  logic [1:0] selected;
-  initial begin
-    selected = CORE_SELECTOR;
-    #1;
-    if (selected !== CORE_CV32E40P) begin
-      $fatal(1, "FAIL: CORE_SELECTOR package parameter did not select CV32E40P");
-    end
-    $display("PASS: T_COMPLETION directed testcase sequence completed");
-    $display("PASS: HiSA-Team_Simply-V_pr52 CORE_SELECTOR reaches uninasoc_pkg");
-    $finish;
-  end
-endmodule
-SV
-  } >"verilator_${tag}_build.log"
-
-  if [ "$tag" = buggy ]; then
-    verilator --lint-only --timing --sv \
-      --Wno-fatal --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \
-      --timescale 1ns/1ps \
-      "$SCRATCH/hw/xilinx/rtl/uninasoc_pkg.sv" \
-      "$SCRATCH/hw/xilinx/rtl/uninasoc.sv" \
-      2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null || true
-    echo "FAIL: $NAME buggy state does not expose CORE_SELECTOR through uninasoc_pkg" >"verilator_${tag}.log"
-    return 1
-  fi
-
-  cat > "$SCRATCH/tb_core_selector_pkg.sv" <<'SV'
-module tb_core_selector_pkg;
-  logic [1:0] selected;
-  initial begin
-    selected = 2'd1;
-    #1;
-    if (selected !== 2'd1) $fatal(1, "FAIL: CORE_SELECTOR selected value changed");
-    $display("PASS: T_COMPLETION directed testcase sequence completed");
-    $display("PASS: HiSA-Team_Simply-V_pr52 CORE_SELECTOR fixed phase elaborated");
-    $finish;
-  end
-endmodule
-SV
+# Runs the repo's "make bitstream" recipe with Vivado replaced, so the defines
+# come from the candidate's Makefile/config.mk/Tcl. Issue text says "core
+# selection" and the RTL parameter is CORE_SELECTOR, so both spellings are passed.
+flow_defines() {
+  local out="$1"; shift
+  (
+    set +u   # settings.sh reads unset positional parameters
+    source "$SCRATCH/settings.sh" embedded >/dev/null 2>&1
+    export FAKE_VIVADO_OUT="$out" FAKE_VIVADO_TCL="$HERE/fake_vivado.tcl"
+    make -C "$SCRATCH/hw/xilinx" -o ips bitstream "XILINX_VIVADO_CMD=$HERE/fake_vivado.sh" "$@"
+  ) >> "verilator_${TAG}_build.log" 2>&1
+  [ -s "$out" ]
+}
 
-  verilator --binary --timing --sv \
-    --Wno-fatal --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \
-    --timescale 1ns/1ps \
-    "$SCRATCH/tb_core_selector_pkg.sv" \
-    --top-module tb_core_selector_pkg \
-    -Mdir obj_dir -o simv_vlt 2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null
-  local rc=${PIPESTATUS[0]}
-  [ "$rc" -eq 0 ] || return "$rc"
+# Identical build and test in both phases; only $SCRATCH differs.
+run_select() {
+  local core="$1" mask="$2" R="$SCRATCH/hw/xilinx/rtl" dir="obj_dir_$1" args=() defs=() d
+  [ "$core" = DEFAULT ] || args=("CORE_SELECTOR=$core" "CORE_SELECTION=$core")
+  flow_defines "$SCRATCH/defines_$core.txt" "${args[@]}" || { echo "FAIL: Make flow produced no defines"; return 2; }
+  while read -r d; do [ -n "$d" ] && defs+=("+define+$d"); done < "$SCRATCH/defines_$core.txt"
+  verilator -E -P --sv "${defs[@]}" "+incdir+$R" "$R/uninasoc_pkg.sv" "$R/uninasoc.sv" \
+    "$R/rvm_socket.sv" > "$SCRATCH/pp.sv" 2>>"verilator_${TAG}_build.log" || { echo "FAIL: preprocess $core"; return 2; }
+  python3 -I "$HERE/gen_stubs.py" "$SCRATCH/pp.sv" "$SCRATCH/ip_stubs.sv" || return 2
+  rm -rf "$dir"
+  verilator --binary --timing --sv -Wno-fatal -Wno-WIDTH --timescale 1ns/1ps \
+    "${defs[@]}" "+define+EXPECT_CORE_MASK=$mask" "+incdir+$R" \
+    "$HERE/uninasoc_tb_stubs_pkg.sv" "$R/uninasoc_pkg.sv" "$SCRATCH/ip_stubs.sv" \
+    "$R/uninasoc.sv" "$R/rvm_socket.sv" "$HERE/$TOP.sv" \
+    --top-module "$TOP" -Mdir "$dir" -o simv_vlt \
+    >> "verilator_${TAG}_build.log" 2>&1 || { grep -m5 %Error "verilator_${TAG}_build.log"; return 2; }
+  timeout 20 "./$dir/simv_vlt" 2>&1 | tee "verilator_${TAG}_$core.log"
+  [ "${PIPESTATUS[0]}" -eq 0 ] || return 1
+  grep -qE '(^|[^A-Za-z])PASS:' "verilator_${TAG}_$core.log" &&
+    ! grep -qE '(^|[^A-Za-z])(FAIL:|Aborting\.\.\.)' "verilator_${TAG}_$core.log"
+}
 
-  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null
-  rc=${PIPESTATUS[0]}
-  [ "$rc" -eq 0 ] || return "$rc"
-  grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" \
-    && ! grep -qE '(^|[^A-Za-z])(FAIL:|\$fatal|Aborting\.\.\.)' "verilator_${tag}.log"
+run_phase() {
+  TAG="$1"
+  local rc=0 s
+  : > "verilator_${TAG}_build.log"
+  run_repo_native_p2p_smoke "$TAG" || return $?
+  for s in DEFAULT:0 CORE_PICORV32:1 CORE_CV32E40P:2; do
+    echo "INFO: selection ${s%%:*}"
+    run_select "${s%%:*}" "${s##*:}" || rc=$?
+    rm -rf "obj_dir_${s%%:*}"
+  done
+  return "$rc"
 }
 
 echo BUGGY
 prepare_phase buggy
-prep_buggy=$?
-if [ "$prep_buggy" = "0" ]; then
-  run_phase buggy
-  rc_buggy=$?
-else
-  rc_buggy=$prep_buggy
-fi
-if [ "$rc_buggy" != "0" ]; then
-  touch verilator_buggy.log
-  grep -qE '^\s*(\[FAIL\]|FAIL)\b' verilator_buggy.log \
-    || echo "FAIL: $NAME buggy state rejected by real Verilator package elaboration" >> verilator_buggy.log
-fi
+run_phase buggy
+rc_buggy=$?
 
 echo FIXED
 prepare_phase fixed
-prep_fixed=$?
-if [ "$prep_fixed" = "0" ]; then
-  run_phase fixed
-  rc_fixed=$?
-else
-  rc_fixed=$prep_fixed
-fi
+run_phase fixed
+rc_fixed=$?
 
 echo "buggy:$rc_buggy fixed:$rc_fixed"
-([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] \
-  && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } \
-  || { echo "FAIL: $NAME"; exit 1; }
+([ "$rc_buggy" != "0" ] && [ "$rc_fixed" = "0" ]) &&
+  { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } ||
+  { echo "FAIL: $NAME"; exit 1; }

testbench/HiSA-Team_Simply-V_pr52/tb_simplyv_pr52_verilator.sv

@@ -1,39 +1,34 @@
-module core_select_buggy #(
-  parameter int CORE_SELECTOR = 0
-)(
-  output logic [1:0] core_id
-);
-  always_comb core_id = 2'd2;
-endmodule
+`timescale 1ns/1ps
 
-module core_select_fixed #(
-  parameter int CORE_SELECTOR = 0
-)(
-  output logic [1:0] core_id
-);
-  always_comb begin
-    case (CORE_SELECTOR)
-      0: core_id = 2'd0;
-      1: core_id = 2'd1;
-      default: core_id = 2'd2;
-    endcase
-  end
-endmodule
+// Real uninasoc + rvm_socket with stubbed IPs, compiled with the Verilog defines
+// that the repo's own Make flow produced. The socket must instantiate the core
+// the flow was asked for. EXPECT_CORE_MASK = 0 means the flow default: any single
+// supported core is acceptable.
+module tb_simplyv_pr52_verilator;
+  logic clk = 1'b0;
+  logic rst = 1'b1;
+  logic uart_tx;
+  logic [15:0] gpio_out;
+  always #5 clk = ~clk;
 
-`ifdef FIXED
-  `define DUT core_select_fixed
-`else
-  `define DUT core_select_buggy
-`endif
+  uninasoc dut (
+    .sys_clock_i(clk), .sys_reset_i(rst),
+    .uart_rx_i(1'b1), .uart_tx_o(uart_tx),
+    .gpio_in_i(16'h0), .gpio_out_o(gpio_out)
+  );
 
-module tb_simplyv_pr52_verilator;
-  logic [1:0] core_id;
-  `DUT #(.CORE_SELECTOR(1)) dut(.core_id(core_id));
   initial begin
+    repeat (3) @(posedge clk);
     #1;
-    if (core_id !== 2'd1) $fatal(1, "CORE_SELECTOR must propagate through the make/config flow");
-    $display("PASS: T_COMPLETION directed testcase sequence completed");
-    $display("PASS: HiSA-Team_Simply-V_pr52");
+    if ($countones(tbsig::seen) != 1) begin
+      $display("FAIL: selected cores mask = %b", tbsig::seen);
+      $fatal(1, "FAIL: exactly one core must be instantiated");
+    end
+    if (`EXPECT_CORE_MASK != 0 && tbsig::seen != 3'(`EXPECT_CORE_MASK)) begin
+      $display("FAIL: selected cores mask = %b, requested %b", tbsig::seen, 3'(`EXPECT_CORE_MASK));
+      $fatal(1, "FAIL: Make flow core selection did not reach rvm_socket");
+    end
+    $display("PASS: selected core mask %b", tbsig::seen);
     $finish;
   end
 endmodule

testbench/HiSA-Team_Simply-V_pr52/uninasoc_tb_stubs_pkg.sv

@@ -0,0 +1,4 @@
+// Written by the core stubs: bit 0 PicoRV32, bit 1 CV32E40P, bit 2 MicroBlaze-V.
+package tbsig;
+  logic [2:0] seen = '0;
+endpackage

testbench/HiSA-Team_Simply-V_pr52/verilator_buggy.log

@@ -1 +0,0 @@
-FAIL: HiSA-Team_Simply-V_pr52 buggy state does not expose CORE_SELECTOR through uninasoc_pkg

testbench/HiSA-Team_Simply-V_pr52/verilator_buggy_build.log

@@ -1,46 +0,0 @@
-INFO: patch target hw/xilinx/rtl/uninasoc.sv
-INFO: patch target hw/xilinx/rtl/uninasoc_pkg.sv
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:43:10: Cannot find include file: 'uninasoc_axi.svh'
-   43 | `include "uninasoc_axi.svh"
-      |          ^~~~~~~~~~~~~~~~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
-        ... This may be because there's no search path specified with -I<dir>.
-        ... Looked in:
-             uninasoc_axi.svh
-             uninasoc_axi.svh.v
-             uninasoc_axi.svh.sv
-             obj_dir/uninasoc_axi.svh
-             obj_dir/uninasoc_axi.svh.v
-             obj_dir/uninasoc_axi.svh.sv
-        ... With current working directory 'testbench/HiSA-Team_Simply-V_pr52'
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:116:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  116 |     `DECLARE_AXI_BUS(sys_master_to_xbar, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:116:21: syntax error, unexpected '('
-  116 |     `DECLARE_AXI_BUS(sys_master_to_xbar, AXI_DATA_WIDTH);
-      |                     ^
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:118:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  118 |     `DECLARE_AXI_BUS(rvm_socket_instr, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:119:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  119 |     `DECLARE_AXI_BUS(rvm_socket_data, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:126:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  126 |     `DECLARE_AXI_BUS(xbar_to_main_mem, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:129:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  129 |     `DECLARE_AXI_BUS(xbar_to_plic, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:132:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  132 |     `DECLARE_AXI_BUS(xbar_to_peripheral_bus, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:143:5: Define or directive not defined: '`DECLARE_AXI_BUS_ARRAY'
-  143 |     `DECLARE_AXI_BUS_ARRAY(xbar_masters, NUM_AXI_MASTERS);
-      |     ^~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:146:5: Define or directive not defined: '`CONCAT_AXI_MASTERS_ARRAY3'
-  146 |     `CONCAT_AXI_MASTERS_ARRAY3(xbar_masters, rvm_socket_instr, rvm_socket_data, sys_master_to_xbar);
-      |     ^~~~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:149:5: Define or directive not defined: '`DECLARE_AXI_BUS_ARRAY'
-  149 |     `DECLARE_AXI_BUS_ARRAY(xbar_slaves, NUM_AXI_SLAVES);
-      |     ^~~~~~~~~~~~~~~~~~~~~~
-%Error: Exiting due to 11 error(s)

testbench/HiSA-Team_Simply-V_pr52/verilator_fixed.log

@@ -1,6 +0,0 @@
-PASS: T_COMPLETION directed testcase sequence completed
-PASS: HiSA-Team_Simply-V_pr52 CORE_SELECTOR fixed phase elaborated
-- testbench/HiSA-Team_Simply-V_pr52/snapshot_scratch/tb_core_selector_pkg.sv:9: Verilog $finish
-- S i m u l a t i o n   R e p o r t: Verilator 5.047 devel
-- Verilator: $finish at 1ns; walltime 0.000 s; speed 34.566 us/s
-- Verilator: cpu 0.000 s on 1 threads; allocated 6 MB

testbench/HiSA-Team_Simply-V_pr52/verilator_fixed_build.log

@@ -1,14 +0,0 @@
-INFO: patch target hw/xilinx/rtl/uninasoc.sv
-INFO: patch target hw/xilinx/rtl/uninasoc_pkg.sv
-make: Entering directory 'testbench/HiSA-Team_Simply-V_pr52/obj_dir'
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
-python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_core_selector_pkg.cpp Vtb_core_selector_pkg___024root__0.cpp Vtb_core_selector_pkg__main.cpp Vtb_core_selector_pkg___024root__Slow.cpp Vtb_core_selector_pkg___024root__0__Slow.cpp Vtb_core_selector_pkg__Syms__Slow.cpp > Vtb_core_selector_pkg__ALL.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o Vtb_core_selector_pkg__ALL.o Vtb_core_selector_pkg__ALL.cpp
-g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    verilated.o verilated_timing.o verilated_threads.o Vtb_core_selector_pkg__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
-rm Vtb_core_selector_pkg__ALL.verilator_deplist.tmp
-make: Leaving directory 'testbench/HiSA-Team_Simply-V_pr52/obj_dir'
-- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
-- Verilator: Built from 0.032 MB sources in 2 modules, into 0.025 MB in 6 C++ files needing 0.000 MB
-- Verilator: Walltime 5.852 s (elab=0.000, cvt=0.002, bld=5.847); cpu 0.004 s on 1 threads; allocated 20.336 MB

testbench/HiSA-Team_Simply-V_pr68/gen_stubs.py

@@ -0,0 +1,75 @@
+#!/usr/bin/env python3
+"""Emit port-compatible stubs for the Xilinx IPs and submodule cores that a
+preprocessed UninaSoC source instantiates. Usage: gen_stubs.py <pp.sv> <out.sv>
+Port lists come from the candidate tree, so they track any change it makes.
+Everything is an unconnected input except the observation points in SPECIAL."""
+import re, sys
+
+STUB = ['xlnx_vio', 'xlnx_main_crossbar', 'sys_master', 'xlnx_blk_mem_gen',
+        'custom_rv_plic', 'peripheral_bus', 'custom_picorv32', 'custom_cv32e40p',
+        'xlnx_microblaze_riscv', 'xlnx_microblaze_debug_module_v',
+        'xlnx_axilite_to_axi4_converter', 'custom_axi_from_mem',
+        'custom_riscv_dbg_bscane']
+
+# module -> {port: declaration}, body
+SPECIAL = {
+    'custom_rv_plic': ({'irq_o': 'output logic', 'intr_src_i': 'input logic [31:0]'},
+                       'assign irq_o = tbsig::plic_irq;\n'
+                       '  always_comb tbsig::plic_src = intr_src_i;'),
+    'peripheral_bus': ({'int_o': 'output logic [31:0]'},
+                       'assign int_o = tbsig::pbus_int;'),
+    'custom_cv32e40p': ({'irq_i': 'input logic [31:0]'},
+                        'always_comb tbsig::core_irq = irq_i;'),
+    'custom_picorv32': ({'irq_i': 'input logic [31:0]'},
+                        'always_comb tbsig::core_irq = irq_i;'),
+    'xlnx_microblaze_riscv': ({'Interrupt': 'input logic'},
+                              'always_comb tbsig::core_irq = 32\'(Interrupt) << 11;'),
+}
+
+
+def balanced(s, i):
+    d = 0
+    for j in range(i, len(s)):
+        d += (s[j] == '(') - (s[j] == ')')
+        if d == 0:
+            return j
+    raise SystemExit('unbalanced parentheses')
+
+
+def main():
+    src = open(sys.argv[1]).read()
+    out = []
+    for mod in STUB:
+        ports, params = [], []
+        for m in re.finditer(r'^\s*%s\b' % mod, src, re.M):
+            i = m.end()
+            hdr = re.match(r'\s*#\s*(?=\()', src[i:])
+            if hdr:
+                i += hdr.end()
+                e = balanced(src, i)
+                params += [p for p in re.findall(r'\.(\w+)\s*\(', src[i:e]) if p not in params]
+                i = e + 1
+            inst = re.match(r'\s*\w+\s*(?=\()', src[i:])
+            if not inst:
+                continue
+            i += inst.end()
+            e = balanced(src, i)
+            depth, tops = 0, []
+            for n in re.finditer(r'[()]|\.(\w+)\s*(?=\()', src[i:e + 1]):
+                if n.group(0) == '(':
+                    depth += 1
+                elif n.group(0) == ')':
+                    depth -= 1
+                elif depth == 1:
+                    tops.append(n.group(1))
+            ports += [p for p in tops if p not in ports]
+        if not ports:
+            continue
+        special, body = SPECIAL.get(mod, ({}, ''))
+        decl = ['  %s %s' % (special.get(p, 'input logic [1023:0]'), p) for p in ports]
+        ph = ' #(' + ', '.join('parameter %s = 0' % p for p in params) + ')' if params else ''
+        out.append('module %s%s (\n%s\n);\n  %s\nendmodule\n' % (mod, ph, ',\n'.join(decl), body))
+    open(sys.argv[2], 'w').write('\n'.join(out))
+
+
+main()

testbench/HiSA-Team_Simply-V_pr68/open_tool_p2p_buggy.log

@@ -1,3 +0,0 @@
-INFO: open-tool P2P fallback (buggy)
-INFO: native simulation P2P not applicable for this case
-PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/HiSA-Team_Simply-V_pr68/open_tool_p2p_fixed.log

@@ -1,3 +0,0 @@
-INFO: open-tool P2P fallback (fixed)
-INFO: native simulation P2P not applicable for this case
-PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/HiSA-Team_Simply-V_pr68/repo_native_buggy.log

@@ -1 +0,0 @@
-PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/HiSA-Team_Simply-V_pr68/repo_native_fixed.log

@@ -1 +0,0 @@
-PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/HiSA-Team_Simply-V_pr68/run_verilator.sh

@@ -1,6 +1,5 @@
 #!/bin/bash
 set -u
-
 HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
 cd "$HERE"
 . "$HERE/../_testcase_minimum.sh"
@@ -11,16 +10,20 @@ REPO_ROOT="$(cd "$HERE/../.." && pwd)"
 SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
 PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
 SCRATCH="$HERE/snapshot_scratch"
-
-PATCH_TARGETS=(
-  hw/xilinx/rtl/peripheral_bus.sv
-  hw/xilinx/rtl/rvm_socket.sv
-  hw/xilinx/rtl/uninasoc.sv
-  hw/xilinx/rtl/uninasoc_pkg.sv
-)
+TOP=tb_hisa_simplyv_pr68_verilator
 
 trap 'rm -rf "$SCRATCH" obj_dir' EXIT
 
+# eval_case.sh and run_case_protocol.sh reverse-apply the gold patch to a snapshot
+# that is already pre-fix. One hunk then duplicates the *_INT_PIN localparams in
+# rvm_socket.sv, which cannot elaborate. Drop the duplicates so that verdicts come
+# from behaviour. Keyed on the tree contents only, so it is phase independent.
+repair_base() {
+  awk '/^ *localparam [A-Z_]+_INT_PIN *=/ { if (seen[$2]++) next } { print }' \
+    "$SCRATCH/hw/xilinx/rtl/rvm_socket.sv" > "$SCRATCH/rvm_socket.tmp" &&
+    mv "$SCRATCH/rvm_socket.tmp" "$SCRATCH/hw/xilinx/rtl/rvm_socket.sv"
+}
+
 prepare_phase() {
   local tag="$1"
   rm -rf "$SCRATCH"
@@ -31,124 +34,53 @@ prepare_phase() {
   else
     (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
   fi
+  repair_base
+}
+
+# Identical build and test in both phases; only $SCRATCH differs.
+run_core() {
+  local tag="$1" core="$2" R="$SCRATCH/hw/xilinx/rtl" dir="obj_dir_$2"
+  local defs=(+define+EMBEDDED=1 +define+AXI_DATA_WIDTH=32 +define+AXI_ADDR_WIDTH=32
+    +define+AXI_ID_WIDTH=2 +define+NUM_SI=4 +define+NUM_MI=4 +define+PBUS_NUM_MI=5
+    "+define+CORE_SELECTOR=$core")
+  verilator -E -P --sv "${defs[@]}" "+incdir+$R" "$R/uninasoc_pkg.sv" "$R/uninasoc.sv" \
+    "$R/rvm_socket.sv" > "$SCRATCH/pp.sv" 2>>"verilator_${tag}_build.log" || return 2
+  python3 -I "$HERE/gen_stubs.py" "$SCRATCH/pp.sv" "$SCRATCH/ip_stubs.sv" || return 2
+  rm -rf "$dir"
+  verilator --binary --timing --sv -Wno-fatal -Wno-WIDTH --timescale 1ns/1ps \
+    "${defs[@]}" "+incdir+$R" \
+    "$HERE/uninasoc_tb_stubs_pkg.sv" "$R/uninasoc_pkg.sv" "$SCRATCH/ip_stubs.sv" \
+    "$R/uninasoc.sv" "$R/rvm_socket.sv" "$HERE/$TOP.sv" \
+    --top-module "$TOP" -Mdir "$dir" -o simv_vlt \
+    >> "verilator_${tag}_build.log" 2>&1 || { grep -m5 %Error "verilator_${tag}_build.log"; return 2; }
+  timeout 20 "./$dir/simv_vlt" 2>&1 | tee "verilator_${tag}_$core.log"
+  [ "${PIPESTATUS[0]}" -eq 0 ] || return 1
+  grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}_$core.log" &&
+    ! grep -qE '(^|[^A-Za-z])(FAIL:|Aborting\.\.\.)' "verilator_${tag}_$core.log"
 }
 
 run_phase() {
-  local tag="$1"
-  rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log"
+  local tag="$1" core rc=0
+  : > "verilator_${tag}_build.log"
   run_repo_native_p2p_smoke "$tag" || return $?
-  {
-    printf 'INFO: patch target %s\n' "${PATCH_TARGETS[@]}"
-    cat > "$SCRATCH/tb_interrupt_pkg.sv" <<'SV'
-`define NUM_SI 3
-`define NUM_MI 4
-`define PBUS_NUM_MI 4
-`define CORE_SELECTOR CORE_CV32E40P
-module tb_interrupt_pkg;
-  import uninasoc_pkg::*;
-  logic [31:0] rvm_socket_interrupt_line;
-  logic [31:0] plic_int_line;
-  logic [3:0] pbus_int_line;
-  logic plic_int_irq_o;
-  initial begin
-    pbus_int_line = 4'b1010;
-    plic_int_irq_o = 1'b1;
-    plic_int_line = '0;
-    rvm_socket_interrupt_line = '0;
-    plic_int_line[PLIC_GPIOIN_INTERRUPT] = pbus_int_line[PBUS_GPIOIN_INTERRUPT];
-    plic_int_line[PLIC_TIM0_INTERRUPT] = pbus_int_line[PBUS_TIM0_INTERRUPT];
-    plic_int_line[PLIC_TIM1_INTERRUPT] = pbus_int_line[PBUS_TIM1_INTERRUPT];
-    plic_int_line[PLIC_UART_INTERRUPT] = pbus_int_line[PBUS_UART_INTERRUPT];
-    rvm_socket_interrupt_line[CORE_EXT_INTERRUPT] = plic_int_irq_o;
-    #1;
-    if (CORE_EXT_INTERRUPT != 11 || rvm_socket_interrupt_line[11] !== 1'b1) begin
-      $fatal(1, "FAIL: PLIC IRQ must map to core external interrupt bit 11");
-    end
-    if (plic_int_line[PLIC_UART_INTERRUPT] !== pbus_int_line[PBUS_UART_INTERRUPT]) begin
-      $fatal(1, "FAIL: PBUS UART interrupt must map through package constants");
-    end
-    $display("PASS: T_COMPLETION directed testcase sequence completed");
-    $display("PASS: HiSA-Team_Simply-V_pr68 interrupt constants elaborate from uninasoc_pkg");
-    $finish;
-  end
-endmodule
-SV
-  } >"verilator_${tag}_build.log"
-
-  if [ "$tag" = buggy ]; then
-    verilator --lint-only --timing --sv \
-      --Wno-fatal --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \
-      --timescale 1ns/1ps \
-      "$SCRATCH/hw/xilinx/rtl/peripheral_bus.sv" \
-      "$SCRATCH/hw/xilinx/rtl/rvm_socket.sv" \
-      "$SCRATCH/hw/xilinx/rtl/uninasoc.sv" \
-      "$SCRATCH/hw/xilinx/rtl/uninasoc_pkg.sv" \
-      2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null || true
-    echo "FAIL: $NAME buggy state does not expose interrupt mapping constants" >"verilator_${tag}.log"
-    return 1
-  fi
-
-  cat > "$SCRATCH/tb_interrupt_pkg.sv" <<'SV'
-module tb_interrupt_pkg;
-  logic [31:0] rvm_socket_interrupt_line;
-  logic plic_int_irq_o;
-  initial begin
-    plic_int_irq_o = 1'b1;
-    rvm_socket_interrupt_line = '0;
-    rvm_socket_interrupt_line[11] = plic_int_irq_o;
-    #1;
-    if (rvm_socket_interrupt_line[11] !== 1'b1) begin
-      $fatal(1, "FAIL: PLIC IRQ must map to external interrupt bit 11");
-    end
-    $display("PASS: T_COMPLETION directed testcase sequence completed");
-    $display("PASS: HiSA-Team_Simply-V_pr68 interrupt fixed phase elaborated");
-    $finish;
-  end
-endmodule
-SV
-
-  verilator --binary --timing --sv \
-    --Wno-fatal --Wno-WIDTH --Wno-UNUSEDSIGNAL --Wno-DECLFILENAME \
-    --timescale 1ns/1ps \
-    "$SCRATCH/tb_interrupt_pkg.sv" \
-    --top-module tb_interrupt_pkg \
-    -Mdir obj_dir -o simv_vlt 2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null
-  local rc=${PIPESTATUS[0]}
-  [ "$rc" -eq 0 ] || return "$rc"
-
-  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee "verilator_${tag}.log" >/dev/null
-  rc=${PIPESTATUS[0]}
-  [ "$rc" -eq 0 ] || return "$rc"
-  grep -qE '(^|[^A-Za-z])PASS:' "verilator_${tag}.log" \
-    && ! grep -qE '(^|[^A-Za-z])(FAIL:|\$fatal|Aborting\.\.\.)' "verilator_${tag}.log"
+  for core in CORE_CV32E40P CORE_MICROBLAZEV; do
+    run_core "$tag" "$core" || rc=$?
+    rm -rf "obj_dir_$core"
+  done
+  return "$rc"
 }
 
 echo BUGGY
 prepare_phase buggy
-prep_buggy=$?
-if [ "$prep_buggy" = "0" ]; then
-  run_phase buggy
-  rc_buggy=$?
-else
-  rc_buggy=$prep_buggy
-fi
-if [ "$rc_buggy" != "0" ]; then
-  touch verilator_buggy.log
-  grep -qE '^\s*(\[FAIL\]|FAIL)\b' verilator_buggy.log \
-    || echo "FAIL: $NAME buggy state rejected by real Verilator package elaboration" >> verilator_buggy.log
-fi
+run_phase buggy
+rc_buggy=$?
 
 echo FIXED
 prepare_phase fixed
-prep_fixed=$?
-if [ "$prep_fixed" = "0" ]; then
-  run_phase fixed
-  rc_fixed=$?
-else
-  rc_fixed=$prep_fixed
-fi
+run_phase fixed
+rc_fixed=$?
 
 echo "buggy:$rc_buggy fixed:$rc_fixed"
-([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] \
-  && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } \
-  || { echo "FAIL: $NAME"; exit 1; }
+([ "$rc_buggy" != "0" ] && [ "$rc_fixed" = "0" ]) &&
+  { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } ||
+  { echo "FAIL: $NAME"; exit 1; }

testbench/HiSA-Team_Simply-V_pr68/tb_hisa_simplyv_pr68_verilator.sv

@@ -1,25 +1,54 @@
-module uninasoc_irq_map_buggy(
-  input logic plic_int_irq_o,
-  output logic [31:0] rvm_socket_interrupt_line
-);
-  assign rvm_socket_interrupt_line = {21'h0, plic_int_irq_o, 10'h0};
-endmodule
+`timescale 1ns/1ps
 
+// Real uninasoc + rvm_socket with stubbed IPs. A PLIC irq_o must reach the
+// selected core as the machine external interrupt (mcause 11), and PBUS
+// interrupts must reach the PLIC sources 1..4.
 module tb_hisa_simplyv_pr68_verilator;
-  logic plic_int_irq_o;
-  logic [31:0] rvm_socket_interrupt_line;
+  logic clk = 1'b0;
+  logic rst = 1'b1;
+  logic uart_tx;
+  logic [15:0] gpio_out;
+  always #5 clk = ~clk;
 
-  uninasoc_irq_map_buggy dut(
-    .plic_int_irq_o(plic_int_irq_o),
-    .rvm_socket_interrupt_line(rvm_socket_interrupt_line)
+  uninasoc dut (
+    .sys_clock_i(clk), .sys_reset_i(rst),
+    .uart_rx_i(1'b1), .uart_tx_o(uart_tx),
+    .gpio_in_i(16'h0), .gpio_out_o(gpio_out)
   );
 
+  int errors = 0;
+  task automatic settle(); repeat (4) @(posedge clk); #1; endtask
+  task automatic check(input string what, input logic [31:0] got, want);
+    if (got !== want) begin
+      $display("FAIL: %s = 0x%08h, expected 0x%08h", what, got, want);
+      errors++;
+    end
+  endtask
+
   initial begin
-    plic_int_irq_o = 1'b1;
-    #1;
-    if (rvm_socket_interrupt_line[11] !== 1'b1) $fatal(1, "PLIC IRQ must map to EXT interrupt bit 11");
-    $display("PASS: T_COMPLETION directed testcase sequence completed");
-    $display("PASS: hisa simply-v pr68");
+    settle();
+    rst = 1'b0;
+    settle();
+    tbsig::plic_irq = 1'b0; tbsig::pbus_int = '0;
+    settle();
+    check("core irq, PLIC idle", tbsig::core_irq, 32'h0);
+    check("PLIC sources, PBUS idle", tbsig::plic_src, 32'h0);
+
+    tbsig::plic_irq = 1'b1;
+    settle();
+    check("core irq, PLIC asserted", tbsig::core_irq, 32'h1 << 11);
+
+    tbsig::plic_irq = 1'b0;
+    settle();
+    check("core irq, PLIC released", tbsig::core_irq, 32'h0);
+
+    for (int i = 0; i < 4; i++) begin
+      tbsig::pbus_int = 32'h1 << i;
+      settle();
+      check("PLIC sources for one PBUS line", tbsig::plic_src, 32'h2 << i);
+    end
+    if (errors != 0) $fatal(1, "FAIL: interrupt routing incorrect");
+    $display("PASS: interrupt routing correct");
     $finish;
   end
 endmodule

testbench/HiSA-Team_Simply-V_pr68/uninasoc_tb_stubs_pkg.sv

@@ -0,0 +1,7 @@
+// Observation points shared by the generated stubs and the testbench.
+package tbsig;
+  logic        plic_irq = 1'b0;   // driven by the testbench, PLIC irq_o
+  logic [31:0] plic_src;          // what uninasoc feeds to PLIC intr_src_i
+  logic [31:0] pbus_int = '0;     // driven by the testbench, PBUS int_o
+  logic [31:0] core_irq;          // interrupt vector reaching the selected core
+endpackage

testbench/HiSA-Team_Simply-V_pr68/verilator_buggy.log

@@ -1 +0,0 @@
-FAIL: HiSA-Team_Simply-V_pr68 buggy state does not expose interrupt mapping constants

testbench/HiSA-Team_Simply-V_pr68/verilator_buggy_build.log

@@ -1,165 +0,0 @@
-INFO: patch target hw/xilinx/rtl/peripheral_bus.sv
-INFO: patch target hw/xilinx/rtl/rvm_socket.sv
-INFO: patch target hw/xilinx/rtl/uninasoc.sv
-INFO: patch target hw/xilinx/rtl/uninasoc_pkg.sv
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:35:10: Cannot find include file: 'uninasoc_axi.svh'
-   35 | `include "uninasoc_axi.svh"
-      |          ^~~~~~~~~~~~~~~~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
-        ... This may be because there's no search path specified with -I<dir>.
-        ... Looked in:
-             uninasoc_axi.svh
-             uninasoc_axi.svh.v
-             uninasoc_axi.svh.sv
-             obj_dir/uninasoc_axi.svh
-             obj_dir/uninasoc_axi.svh.v
-             obj_dir/uninasoc_axi.svh.sv
-        ... With current working directory 'testbench/HiSA-Team_Simply-V_pr68'
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:44:5: Define or directive not defined: '`DEFINE_AXI_SLAVE_PORTS'
-   44 |     `DEFINE_AXI_SLAVE_PORTS(s),
-      |     ^~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:44:28: syntax error, unexpected '(', expecting '['
-   44 |     `DEFINE_AXI_SLAVE_PORTS(s),
-      |                            ^
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:49:5: syntax error, unexpected output
-   49 |     output logic                        uart_tx_o,
-      |     ^~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:52:5: syntax error, unexpected input
-   52 |     input  logic [NUM_GPIO_IN  -1 : 0]  gpio_in_i,
-      |     ^~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:53:5: syntax error, unexpected output
-   53 |     output logic [NUM_GPIO_OUT -1 : 0]  gpio_out_o,
-      |     ^~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:56:5: syntax error, unexpected output
-   56 |     output logic [NUM_IRQ - 1 : 0]      int_o
-      |     ^~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:58:1: syntax error, unexpected ')', expecting ',' or ';'
-   58 | );
-      | ^
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:65:5: Define or directive not defined: '`DECLARE_AXILITE_BUS'
-   65 |     `DECLARE_AXILITE_BUS(prot_conv_to_xbar);
-      |     ^~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:68:5: Define or directive not defined: '`DECLARE_AXILITE_BUS_ARRAY'
-   68 |     `DECLARE_AXILITE_BUS_ARRAY(xbar_slaves, PBUS_NUM_MI);
-      |     ^~~~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:71:5: Define or directive not defined: '`DECLARE_AXILITE_BUS'
-   71 |     `DECLARE_AXILITE_BUS(xbar_to_uart);
-      |     ^~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:74:5: Define or directive not defined: '`DECLARE_AXILITE_BUS'
-   74 |     `DECLARE_AXILITE_BUS(xbar_to_tim0);
-      |     ^~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:77:5: Define or directive not defined: '`DECLARE_AXILITE_BUS'
-   77 |     `DECLARE_AXILITE_BUS(xbar_to_tim1);
-      |     ^~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:81:5: Define or directive not defined: '`DECLARE_AXILITE_BUS'
-   81 |     `DECLARE_AXILITE_BUS(xbar_to_gpio_in);
-      |     ^~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:82:5: Define or directive not defined: '`DECLARE_AXILITE_BUS'
-   82 |     `DECLARE_AXILITE_BUS(xbar_to_gpio_out);
-      |     ^~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/peripheral_bus.sv:100:5: syntax error, unexpected assign
-  100 |     assign int_o = {uart_int, tim1_int, tim0_int, gpio_in_int};
-      |     ^~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:10:10: Cannot find include file: 'uninasoc_axi.svh'
-   10 | `include "uninasoc_axi.svh"
-      |          ^~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:11:10: Cannot find include file: 'uninasoc_mem.svh'
-   11 | `include "uninasoc_mem.svh"
-      |          ^~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:26:5: Define or directive not defined: '`DEFINE_AXI_MASTER_PORTS'
-   26 |     `DEFINE_AXI_MASTER_PORTS(rvm_socket_instr),
-      |     ^~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:26:29: syntax error, unexpected '(', expecting '['
-   26 |     `DEFINE_AXI_MASTER_PORTS(rvm_socket_instr),
-      |                             ^
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:27:5: Define or directive not defined: '`DEFINE_AXI_MASTER_PORTS'
-   27 |     `DEFINE_AXI_MASTER_PORTS(rvm_socket_data),
-      |     ^~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:30:5: Define or directive not defined: '`DEFINE_AXI_MASTER_PORTS'
-   30 |     `DEFINE_AXI_MASTER_PORTS(dbg_master),
-      |     ^~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:31:5: Define or directive not defined: '`DEFINE_AXI_SLAVE_PORTS'
-   31 |     `DEFINE_AXI_SLAVE_PORTS(dbg_slave)
-      |     ^~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:68:5: syntax error, unexpected assign
-   68 |     assign core_resetn_internal = rst_ni & core_resetn_i;
-      |     ^~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:71:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-   71 |     `DECLARE_AXI_BUS(core_instr_to_socket_instr, DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:72:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-   72 |     `DECLARE_AXI_BUS(core_data_to_socket_data, DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:75:5: Define or directive not defined: '`DECLARE_MEM_BUS'
-   75 |     `DECLARE_MEM_BUS(core_instr, DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:76:5: Define or directive not defined: '`DECLARE_MEM_BUS'
-   76 |     `DECLARE_MEM_BUS(core_data, DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:89:5: syntax error, unexpected generate
-   89 |     generate
-      |     ^~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:239:13: Define or directive not defined: '`DECLARE_AXI_BUS'
-  239 |             `DECLARE_AXI_BUS(microblaze_data,DATA_WIDTH);
-      |             ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:239:29: syntax error, unexpected '('
-  239 |             `DECLARE_AXI_BUS(microblaze_data,DATA_WIDTH);
-      |                             ^
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:240:13: Define or directive not defined: '`DECLARE_AXILITE_BUS'
-  240 |             `DECLARE_AXILITE_BUS(microblaze_instr);
-      |             ^~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:243:13: Define or directive not defined: '`DECLARE_AXI_BUS'
-  243 |             `DECLARE_AXI_BUS(converter_instr,DATA_WIDTH);
-      |             ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:341:13: Define or directive not defined: '`ASSIGN_AXI_BUS'
-  341 |             `ASSIGN_AXI_BUS( rvm_socket_data , microblaze_data );
-      |             ^~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:342:13: Define or directive not defined: '`ASSIGN_AXI_BUS'
-  342 |             `ASSIGN_AXI_BUS( rvm_socket_instr , converter_instr);
-      |             ^~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:452:9: Define or directive not defined: '`ASSIGN_AXI_BUS'
-  452 |         `ASSIGN_AXI_BUS( rvm_socket_instr, core_instr_to_socket_instr );
-      |         ^~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:453:9: Define or directive not defined: '`ASSIGN_AXI_BUS'
-  453 |         `ASSIGN_AXI_BUS( rvm_socket_data, core_data_to_socket_data );
-      |         ^~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:679:9: Define or directive not defined: '`SINK_AXI_MASTER_INTERFACE'
-  679 |         `SINK_AXI_MASTER_INTERFACE(dbg_master);
-      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/rvm_socket.sv:680:9: Define or directive not defined: '`SINK_AXI_SLAVE_INTERFACE'
-  680 |         `SINK_AXI_SLAVE_INTERFACE(dbg_slave);
-      |         ^~~~~~~~~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:43:10: Cannot find include file: 'uninasoc_axi.svh'
-   43 | `include "uninasoc_axi.svh"
-      |          ^~~~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:117:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  117 |     `DECLARE_AXI_BUS(sys_master_to_xbar, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:117:21: syntax error, unexpected '('
-  117 |     `DECLARE_AXI_BUS(sys_master_to_xbar, AXI_DATA_WIDTH);
-      |                     ^
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:119:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  119 |     `DECLARE_AXI_BUS(rvm_socket_instr , AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:120:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  120 |     `DECLARE_AXI_BUS(rvm_socket_data  , AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:121:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  121 |     `DECLARE_AXI_BUS(dbg_master       , AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:123:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  123 |     `DECLARE_AXI_BUS(dbg_slave        , AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:130:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  130 |     `DECLARE_AXI_BUS(xbar_to_main_mem, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:133:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  133 |     `DECLARE_AXI_BUS(xbar_to_plic, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:136:5: Define or directive not defined: '`DECLARE_AXI_BUS'
-  136 |     `DECLARE_AXI_BUS(xbar_to_peripheral_bus, AXI_DATA_WIDTH);
-      |     ^~~~~~~~~~~~~~~~
-%Error: testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/hw/xilinx/rtl/uninasoc.sv:147:5: Define or directive not defined: '`DECLARE_AXI_BUS_ARRAY'
-  147 |     `DECLARE_AXI_BUS_ARRAY(xbar_masters, NUM_SI);
-      |     ^~~~~~~~~~~~~~~~~~~~~~
-%Error: Exiting due to too many errors encountered; --error-limit=50

testbench/HiSA-Team_Simply-V_pr68/verilator_fixed.log

@@ -1,6 +0,0 @@
-PASS: T_COMPLETION directed testcase sequence completed
-PASS: HiSA-Team_Simply-V_pr68 interrupt fixed phase elaborated
-- testbench/HiSA-Team_Simply-V_pr68/snapshot_scratch/tb_interrupt_pkg.sv:14: Verilog $finish
-- S i m u l a t i o n   R e p o r t: Verilator 5.047 devel
-- Verilator: $finish at 1ns; walltime 0.000 s; speed 34.014 us/s
-- Verilator: cpu 0.000 s on 1 threads; allocated 6 MB

testbench/HiSA-Team_Simply-V_pr68/verilator_fixed_build.log

@@ -1,16 +0,0 @@
-INFO: patch target hw/xilinx/rtl/peripheral_bus.sv
-INFO: patch target hw/xilinx/rtl/rvm_socket.sv
-INFO: patch target hw/xilinx/rtl/uninasoc.sv
-INFO: patch target hw/xilinx/rtl/uninasoc_pkg.sv
-make: Entering directory 'testbench/HiSA-Team_Simply-V_pr68/obj_dir'
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
-python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_interrupt_pkg.cpp Vtb_interrupt_pkg___024root__0.cpp Vtb_interrupt_pkg__main.cpp Vtb_interrupt_pkg___024root__Slow.cpp Vtb_interrupt_pkg___024root__0__Slow.cpp Vtb_interrupt_pkg__Syms__Slow.cpp > Vtb_interrupt_pkg__ALL.cpp
-g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o Vtb_interrupt_pkg__ALL.o Vtb_interrupt_pkg__ALL.cpp
-g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    verilated.o verilated_timing.o verilated_threads.o Vtb_interrupt_pkg__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
-rm Vtb_interrupt_pkg__ALL.verilator_deplist.tmp
-make: Leaving directory 'testbench/HiSA-Team_Simply-V_pr68/obj_dir'
-- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
-- Verilator: Built from 0.032 MB sources in 2 modules, into 0.025 MB in 6 C++ files needing 0.000 MB
-- Verilator: Walltime 5.829 s (elab=0.000, cvt=0.002, bld=5.824); cpu 0.005 s on 1 threads; allocated 20.332 MB

testbench/MiSTer-devel_Gameboy_MiSTer_pr24/coverage.dat

@@ -1,102 +0,0 @@
-# SystemC::Coverage-3
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[0]
hTOP.tb_gameboy_pr24_verilator.dut' 2
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[1]
hTOP.tb_gameboy_pr24_verilator.dut' 1
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[2]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[3]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[4]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[5]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[6]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l10
n15
pagev_toggle/save_ram_path
ord_addr[7]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l13
n14
pagev_toggle/save_ram_path
owr_addr[0]
hTOP.tb_gameboy_pr24_verilator.dut' 4
-C '
ftb_gameboy_pr24_verilator.sv
l13
n14
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owr_addr[1]
hTOP.tb_gameboy_pr24_verilator.dut' 3
-C '
ftb_gameboy_pr24_verilator.sv
l13
n14
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owr_addr[2]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l13
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owr_addr[3]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l13
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owr_addr[4]
hTOP.tb_gameboy_pr24_verilator.dut' 0
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ftb_gameboy_pr24_verilator.sv
l13
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owr_addr[5]
hTOP.tb_gameboy_pr24_verilator.dut' 0
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ftb_gameboy_pr24_verilator.sv
l13
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owr_addr[6]
hTOP.tb_gameboy_pr24_verilator.dut' 0
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ftb_gameboy_pr24_verilator.sv
l13
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owr_addr[7]
hTOP.tb_gameboy_pr24_verilator.dut' 0
-C '
ftb_gameboy_pr24_verilator.sv
l18
n3
pagev_line/save_ram_path
oblock
S18
hTOP.tb_gameboy_pr24_verilator.dut' 8
-C '
ftb_gameboy_pr24_verilator.sv
l19
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oif
S19-20
hTOP.tb_gameboy_pr24_verilator.dut' 2
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ftb_gameboy_pr24_verilator.sv
l19
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oelse
hTOP.tb_gameboy_pr24_verilator.dut' 6
-C '
ftb_gameboy_pr24_verilator.sv
l2
n23
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oclk
hTOP.tb_gameboy_pr24_verilator.dut' 16
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ftb_gameboy_pr24_verilator.sv
l22
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oelse
hTOP.tb_gameboy_pr24_verilator.dut' 6
-C '
ftb_gameboy_pr24_verilator.sv
l3
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obk_wr
hTOP.tb_gameboy_pr24_verilator.dut' 4
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l31
n15
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S31
hTOP.tb_gameboy_pr24_verilator' 1
-C '
ftb_gameboy_pr24_verilator.sv
l31
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oclk
hTOP.tb_gameboy_pr24_verilator' 16
-C '
ftb_gameboy_pr24_verilator.sv
l32
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S32
hTOP.tb_gameboy_pr24_verilator' 1
-C '
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l32
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hTOP.tb_gameboy_pr24_verilator' 4
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l33
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hTOP.tb_gameboy_pr24_verilator' 4
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hTOP.tb_gameboy_pr24_verilator' 0
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hTOP.tb_gameboy_pr24_verilator' 0
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hTOP.tb_gameboy_pr24_verilator' 0
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l33
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hTOP.tb_gameboy_pr24_verilator' 3
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hTOP.tb_gameboy_pr24_verilator' 0
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hTOP.tb_gameboy_pr24_verilator' 0
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hTOP.tb_gameboy_pr24_verilator' 0
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hTOP.tb_gameboy_pr24_verilator' 0
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hTOP.tb_gameboy_pr24_verilator' 0
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hTOP.tb_gameboy_pr24_verilator' 1
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hTOP.tb_gameboy_pr24_verilator' 1
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testbench/MiSTer-devel_Gameboy_MiSTer_pr24/iverilog_buggy_build.log

@@ -1,215 +0,0 @@
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: warning: implicit definition of wire 'speed'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: warning: implicit definition of wire 'ce_cpu2x'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: warning: implicit definition of wire 'ce_cpu'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:504: warning: implicit definition of wire 'clk_cpu'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:505: warning: implicit definition of wire 'clk_cpu2x'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520: warning: implicit definition of wire 'bios_addr'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:521: warning: implicit definition of wire 'bios_do'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:541: warning: implicit definition of wire 'ce_pix'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:584: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:675: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:698: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:698: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:82: warning: implicit definition of wire 'lcdc_spr_siz'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:84: warning: implicit definition of wire 'v_cnt'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:85: warning: implicit definition of wire 'h_cnt'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:103: warning: implicit definition of wire 'oam_wr'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:104: warning: implicit definition of wire 'oam_addr'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:105: warning: implicit definition of wire 'oam_di'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56: warning: implicit definition of wire 'pixel_reg'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:117: error: Unable to bind wire/reg/memory `ioctl_download' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:177:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:117: error: Unable to elaborate r-value: ioctl_download
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:121: error: Unable to bind wire/reg/memory `status['sd4:'sd3]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:174:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:121: error: Unable to elaborate r-value: ((status['sd4:'sd3])==(2'd2))?(8'd16):(((status['sd4:'sd3])==(2'd1))?(8'd10):(8'd4))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:125: error: Unable to bind wire/reg/memory `status['sd4:'sd3]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:174:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:125: error: Unable to elaborate r-value: ((status['sd4:'sd3])==(2'd2))?(8'd9):(((status['sd4:'sd3])==(2'd1))?(8'd9):(8'd3))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:129: error: Unable to bind wire/reg/memory `status['sd8:'sd7]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:174:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:129: error: Unable to elaborate r-value: status['sd8:'sd7]
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:163: warning: Port 2 (rst) of module pll expects 1 bit(s), given 32.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:163:        : Pruning (signed) 31 high bits of the expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 11 (status_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 12 (status_set) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 13 (new_vmode) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 21 (sd_conf) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 36 (uart_mode) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 39 (ps2_kbd_clk_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 40 (ps2_kbd_data_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 41 (ps2_kbd_led_status) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 42 (ps2_kbd_led_use) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 45 (ps2_mouse_clk_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 46 (ps2_mouse_data_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Unable to bind wire/reg/memory `cart_addr['sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Unable to bind wire/reg/memory `cart_addr['sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Concatenation/replication may not have zero width in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Unable to elaborate r-value: (cart_download)?(2'd3):({cart_addr['sd0], ~(cart_addr['sd0])})
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:241: error: Unable to bind wire/reg/memory `mbc_bank' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:442:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:241: error: Unable to bind wire/reg/memory `cart_addr['sd12:'sd1]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:242: error: Unable to bind wire/reg/memory `cart_rd' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:488:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:242: error: Unable to bind wire/reg/memory `cram_rd' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:634:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:242: error: Unable to elaborate r-value: ((~(cart_download))&(cart_rd))&(~(cram_rd))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:243: error: Unable to bind wire/reg/memory `dn_write' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:273:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:243: error: Unable to elaborate r-value: (cart_download)&(dn_write)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:116: error: Unable to bind wire/reg/memory `mode['sd1]' in `tb_gameboy_pr24_verilator.dut.sdram'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:118:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:116: error: Unable to elaborate r-value: (mode['sd1])?(din_r):(16'bzzzzzzzzzzzzzzzz)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:88: error: Unable to bind wire/reg/memory `stage' in `tb_gameboy_pr24_verilator.dut.sdram'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:120:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:88: error: Unable to elaborate condition expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: error: Unable to bind wire/reg/memory `speed' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:499:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: error: Failed to elaborate input port 'sync' expression ((speed)?(ce_cpu2x):(ce_cpu)) in instance dut.sdram of module: sdram.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:301: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:300: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({2'd0, mbc1_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:306: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:305: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({2'd0, mbc2_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:311: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:310: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({2'd0, mbc3_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:316: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:315: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({mbc5_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:324: error: Unable to bind wire/reg/memory `mbc1_mode' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:347:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:324: error: Unable to bind wire/reg/memory `ram_mask['sd1:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:410:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:324: error: Unable to elaborate r-value: ((mbc1_mode)?(mbc_ram_bank_reg['sd1:'sd0]):(2'd0))&(ram_mask['sd1:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:325: error: Unable to bind wire/reg/memory `mbc_ram_bank_reg['sd1:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:350:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:325: error: Unable to bind wire/reg/memory `ram_mask['sd1:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:410:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:325: error: Unable to elaborate r-value: (mbc_ram_bank_reg['sd1:'sd0])&(ram_mask['sd1:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:326: error: Unable to bind wire/reg/memory `mbc_ram_bank_reg' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:350:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:326: error: Unable to bind wire/reg/memory `ram_mask' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:410:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:326: error: Unable to elaborate r-value: (mbc_ram_bank_reg)&(ram_mask)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Unable to bind wire/reg/memory `mbc1_mode' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:347:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg['sd4:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Concatenation/replication may not have zero width in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Unable to elaborate r-value: {(mbc1_mode)?(2'd0):(mbc_ram_bank_reg['sd1:'sd0]), mbc_rom_bank_reg['sd4:'sd0]}
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:339: error: Unable to bind wire/reg/memory `rom_mask['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:339: error: Unable to elaborate r-value: (mbc1_rom_bank_mode)&(rom_mask['sd6:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:340: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:340: error: Unable to bind wire/reg/memory `rom_mask['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:340: error: Unable to elaborate r-value: (mbc_rom_bank_reg['sd6:'sd0])&(rom_mask['sd6:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:341: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:341: error: Unable to bind wire/reg/memory `rom_mask['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:341: error: Unable to elaborate r-value: (mbc_rom_bank_reg['sd6:'sd0])&(rom_mask['sd6:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:342: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:342: error: Unable to bind wire/reg/memory `rom_mask' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:342: error: Unable to elaborate r-value: (mbc_rom_bank_reg)&(rom_mask)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:450: error: Unable to bind wire/reg/memory `cart_addr['sd14:'sd13]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:480: error: Unable to bind wire/reg/memory `cram_rd' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:634:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:477: error: Unable to elaborate r-value: (~(cart_ready))?(8'd0):((cram_rd)?(cram_do):((cart_addr['sd0])?(sdram_do['sd15:'sd8]):(sdram_do['sd7:'sd0])))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:498: error: Unable to bind wire/reg/memory `bk_loading' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:686:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:498: error: Unable to elaborate r-value: (((((RESET)|(status['sd0]))|(status['sd6]))|(buttons['sd1]))|(cart_download))|(bk_loading)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: error: port ``clk'' is not a port of gb.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: error: port ``clk2x'' is not a port of gb.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 2 (clk_sys) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 3 (ce) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 4 (ce_2x) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Port 6 (joystick) of module gb expects 8 bit(s), given 16.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502:        : Pruning 8 high bits of the expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520: error: Net bios_addr is not defined in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:595:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520: error: Output port expression must support a continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520:      : Port 14 (gbc_bios_addr) of gb is connected to tb_gameboy_pr24_verilator.dut.bios_addr
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:521: error: Unable to bind wire/reg/memory `bios_do' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:594:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:521: error: Failed to elaborate input port 'gbc_bios_do' expression (bios_do) in instance dut.gb of module: gb.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 23 (joy_din) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 25 (gg_reset) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 26 (gg_en) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 27 (gg_code) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 29 (serial_ena) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 31 (serial_clk_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 33 (serial_data_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:45: warning: Instantiating module dpram with dangling input port 9 (data_b) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56: error: Net pixel_reg is not defined in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:128:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56: error: Output port expression must support a continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56:      : Port 10 (q_b) of dpram is connected to tb_gameboy_pr24_verilator.dut.lcd.pixel_reg
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:542: error: Unable to bind wire/reg/memory `clk_cpu' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:579:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:542: error: Failed to elaborate input port 'clk' expression (clk_cpu) in instance dut.lcd of module: lcd.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:541: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:541: error: Failed to elaborate input port 'pce' expression (ce_pix) in instance dut.lcd of module: lcd.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:574: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:574: error: Unable to bind wire/reg/memory `line_cnt' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:729:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:574: error: Unable to elaborate r-value: (ce_pix)&(!(line_cnt))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:578: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:578: error: Unable to elaborate r-value: ce_pix
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:579: error: Unable to bind wire/reg/memory `ce_cpu' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:579: error: Unable to elaborate r-value: (clk_sys)&(ce_cpu)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:580: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:580: error: Unable to elaborate r-value: (clk_sys)&(ce_pix)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:597: warning: Instantiating module dpram_dif with dangling input port 3 (wren_a) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:597: warning: Instantiating module dpram_dif with dangling input port 4 (data_a) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:623: error: Unable to bind wire/reg/memory `cram_q['sd3:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:626: error: Unable to bind wire/reg/memory `cram_q' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:620: error: Unable to elaborate r-value: (mbc_ram_enable)?((((cart_addr['sd15:'sd9])==(7'd80))&&(mbc2))?({4'd15, cram_q['sd3:'sd0]}):((mbc3_mode)?(8'd0):(cram_q))):(8'd255)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629: error: Unable to bind wire/reg/memory `cram_addr['sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:636:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629: error: Unable to elaborate r-value: (cram_addr['sd0])?(cram_q_h):(cram_q_l)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 4 (data_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 5 (q_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 9 (data_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 10 (q_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 4 (data_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 5 (q_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 9 (data_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 10 (q_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:277: error: Unable to bind wire/reg/memory `speed' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:499:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:277: error: Unable to elaborate condition expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:354: error: Unable to bind wire/reg/memory `reset' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:498:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:354: error: Unable to elaborate condition expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:63: error: Variable 'HPS_BUS' cannot be driven by a primitive or continuous assignment with non-default strength.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:63: error: Inout port expression must support continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:63:      : Port 3 (HPS_BUS) of emu is connected to HPS_BUS
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:103: error: Variable 'SDRAM_DQ' cannot be driven by a primitive or continuous assignment with non-default strength.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:103: error: Inout port expression must support continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:103:      : Port 43 (SDRAM_DQ) of emu is connected to SDRAM_DQ
-96 error(s) during elaboration.

testbench/MiSTer-devel_Gameboy_MiSTer_pr24/iverilog_fixed_build.log

@@ -1,215 +0,0 @@
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: warning: implicit definition of wire 'speed'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: warning: implicit definition of wire 'ce_cpu2x'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: warning: implicit definition of wire 'ce_cpu'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:504: warning: implicit definition of wire 'clk_cpu'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:505: warning: implicit definition of wire 'clk_cpu2x'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520: warning: implicit definition of wire 'bios_addr'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:521: warning: implicit definition of wire 'bios_do'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:541: warning: implicit definition of wire 'ce_pix'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:584: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:675: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:698: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:698: warning: Static variable initialization requires explicit lifetime in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:82: warning: implicit definition of wire 'lcdc_spr_siz'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:84: warning: implicit definition of wire 'v_cnt'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:85: warning: implicit definition of wire 'h_cnt'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:103: warning: implicit definition of wire 'oam_wr'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:104: warning: implicit definition of wire 'oam_addr'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v:105: warning: implicit definition of wire 'oam_di'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56: warning: implicit definition of wire 'pixel_reg'.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:117: error: Unable to bind wire/reg/memory `ioctl_download' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:177:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:117: error: Unable to elaborate r-value: ioctl_download
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:121: error: Unable to bind wire/reg/memory `status['sd4:'sd3]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:174:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:121: error: Unable to elaborate r-value: ((status['sd4:'sd3])==(2'd2))?(8'd16):(((status['sd4:'sd3])==(2'd1))?(8'd10):(8'd4))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:125: error: Unable to bind wire/reg/memory `status['sd4:'sd3]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:174:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:125: error: Unable to elaborate r-value: ((status['sd4:'sd3])==(2'd2))?(8'd9):(((status['sd4:'sd3])==(2'd1))?(8'd9):(8'd3))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:129: error: Unable to bind wire/reg/memory `status['sd8:'sd7]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:174:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:129: error: Unable to elaborate r-value: status['sd8:'sd7]
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:163: warning: Port 2 (rst) of module pll expects 1 bit(s), given 32.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:163:        : Pruning (signed) 31 high bits of the expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 11 (status_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 12 (status_set) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 13 (new_vmode) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 21 (sd_conf) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 36 (uart_mode) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 39 (ps2_kbd_clk_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 40 (ps2_kbd_data_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 41 (ps2_kbd_led_status) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 42 (ps2_kbd_led_use) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 45 (ps2_mouse_clk_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:199: warning: Instantiating module hps_io with dangling input port 46 (ps2_mouse_data_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Unable to bind wire/reg/memory `cart_addr['sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Unable to bind wire/reg/memory `cart_addr['sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Concatenation/replication may not have zero width in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:238: error: Unable to elaborate r-value: (cart_download)?(2'd3):({cart_addr['sd0], ~(cart_addr['sd0])})
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:241: error: Unable to bind wire/reg/memory `mbc_bank' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:442:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:241: error: Unable to bind wire/reg/memory `cart_addr['sd12:'sd1]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:242: error: Unable to bind wire/reg/memory `cart_rd' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:488:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:242: error: Unable to bind wire/reg/memory `cram_rd' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:634:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:242: error: Unable to elaborate r-value: ((~(cart_download))&(cart_rd))&(~(cram_rd))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:243: error: Unable to bind wire/reg/memory `dn_write' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:273:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:243: error: Unable to elaborate r-value: (cart_download)&(dn_write)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:116: error: Unable to bind wire/reg/memory `mode['sd1]' in `tb_gameboy_pr24_verilator.dut.sdram'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:118:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:116: error: Unable to elaborate r-value: (mode['sd1])?(din_r):(16'bzzzzzzzzzzzzzzzz)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:88: error: Unable to bind wire/reg/memory `stage' in `tb_gameboy_pr24_verilator.dut.sdram'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:120:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv:88: error: Unable to elaborate condition expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: error: Unable to bind wire/reg/memory `speed' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:499:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:260: error: Failed to elaborate input port 'sync' expression ((speed)?(ce_cpu2x):(ce_cpu)) in instance dut.sdram of module: sdram.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:301: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:300: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({2'd0, mbc1_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:306: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:305: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({2'd0, mbc2_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:311: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:310: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({2'd0, mbc3_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:316: error: Unable to bind wire/reg/memory `cart_addr['sd15:'sd14]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:315: error: Unable to elaborate r-value: ((cart_addr['sd15:'sd14])==(2'd0))?({9'd0, cart_addr['sd13]}):(((cart_addr['sd15:'sd14])==(2'd1))?({mbc5_rom_bank, cart_addr['sd13]}):(9'd0))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:324: error: Unable to bind wire/reg/memory `mbc1_mode' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:347:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:324: error: Unable to bind wire/reg/memory `ram_mask['sd1:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:410:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:324: error: Unable to elaborate r-value: ((mbc1_mode)?(mbc_ram_bank_reg['sd1:'sd0]):(2'd0))&(ram_mask['sd1:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:325: error: Unable to bind wire/reg/memory `mbc_ram_bank_reg['sd1:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:350:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:325: error: Unable to bind wire/reg/memory `ram_mask['sd1:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:410:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:325: error: Unable to elaborate r-value: (mbc_ram_bank_reg['sd1:'sd0])&(ram_mask['sd1:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:326: error: Unable to bind wire/reg/memory `mbc_ram_bank_reg' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:350:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:326: error: Unable to bind wire/reg/memory `ram_mask' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:410:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:326: error: Unable to elaborate r-value: (mbc_ram_bank_reg)&(ram_mask)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Unable to bind wire/reg/memory `mbc1_mode' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:347:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg['sd4:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Concatenation/replication may not have zero width in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:332: error: Unable to elaborate r-value: {(mbc1_mode)?(2'd0):(mbc_ram_bank_reg['sd1:'sd0]), mbc_rom_bank_reg['sd4:'sd0]}
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:339: error: Unable to bind wire/reg/memory `rom_mask['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:339: error: Unable to elaborate r-value: (mbc1_rom_bank_mode)&(rom_mask['sd6:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:340: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:340: error: Unable to bind wire/reg/memory `rom_mask['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:340: error: Unable to elaborate r-value: (mbc_rom_bank_reg['sd6:'sd0])&(rom_mask['sd6:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:341: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:341: error: Unable to bind wire/reg/memory `rom_mask['sd6:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:341: error: Unable to elaborate r-value: (mbc_rom_bank_reg['sd6:'sd0])&(rom_mask['sd6:'sd0])
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:342: error: Unable to bind wire/reg/memory `mbc_rom_bank_reg' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:349:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:342: error: Unable to bind wire/reg/memory `rom_mask' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:417:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:342: error: Unable to elaborate r-value: (mbc_rom_bank_reg)&(rom_mask)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:450: error: Unable to bind wire/reg/memory `cart_addr['sd14:'sd13]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:487:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:480: error: Unable to bind wire/reg/memory `cram_rd' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:634:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:477: error: Unable to elaborate r-value: (~(cart_ready))?(8'd0):((cram_rd)?(cram_do):((cart_addr['sd0])?(sdram_do['sd15:'sd8]):(sdram_do['sd7:'sd0])))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:498: error: Unable to bind wire/reg/memory `bk_loading' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:686:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:498: error: Unable to elaborate r-value: (((((RESET)|(status['sd0]))|(status['sd6]))|(buttons['sd1]))|(cart_download))|(bk_loading)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: error: port ``clk'' is not a port of gb.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: error: port ``clk2x'' is not a port of gb.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 2 (clk_sys) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 3 (ce) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 4 (ce_2x) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Port 6 (joystick) of module gb expects 8 bit(s), given 16.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502:        : Pruning 8 high bits of the expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520: error: Net bios_addr is not defined in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:595:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520: error: Output port expression must support a continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:520:      : Port 14 (gbc_bios_addr) of gb is connected to tb_gameboy_pr24_verilator.dut.bios_addr
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:521: error: Unable to bind wire/reg/memory `bios_do' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:594:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:521: error: Failed to elaborate input port 'gbc_bios_do' expression (bios_do) in instance dut.gb of module: gb.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 23 (joy_din) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 25 (gg_reset) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 26 (gg_en) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 27 (gg_code) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 29 (serial_ena) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 31 (serial_clk_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:502: warning: Instantiating module gb with dangling input port 33 (serial_data_in) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:45: warning: Instantiating module dpram with dangling input port 9 (data_b) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56: error: Net pixel_reg is not defined in this context.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:128:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56: error: Output port expression must support a continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v:56:      : Port 10 (q_b) of dpram is connected to tb_gameboy_pr24_verilator.dut.lcd.pixel_reg
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:542: error: Unable to bind wire/reg/memory `clk_cpu' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:579:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:542: error: Failed to elaborate input port 'clk' expression (clk_cpu) in instance dut.lcd of module: lcd.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:541: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:541: error: Failed to elaborate input port 'pce' expression (ce_pix) in instance dut.lcd of module: lcd.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:574: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:574: error: Unable to bind wire/reg/memory `line_cnt' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:729:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:574: error: Unable to elaborate r-value: (ce_pix)&(!(line_cnt))
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:578: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:578: error: Unable to elaborate r-value: ce_pix
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:579: error: Unable to bind wire/reg/memory `ce_cpu' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:579: error: Unable to elaborate r-value: (clk_sys)&(ce_cpu)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:580: error: Unable to bind wire/reg/memory `ce_pix' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:582:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:580: error: Unable to elaborate r-value: (clk_sys)&(ce_pix)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:597: warning: Instantiating module dpram_dif with dangling input port 3 (wren_a) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:597: warning: Instantiating module dpram_dif with dangling input port 4 (data_a) floating.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:623: error: Unable to bind wire/reg/memory `cram_q['sd3:'sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:626: error: Unable to bind wire/reg/memory `cram_q' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:620: error: Unable to elaborate r-value: (mbc_ram_enable)?((((cart_addr['sd15:'sd9])==(7'd80))&&(mbc2))?({4'd15, cram_q['sd3:'sd0]}):((mbc3_mode)?(8'd0):(cram_q))):(8'd255)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629: error: Unable to bind wire/reg/memory `cram_addr['sd0]' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:636:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:629: error: Unable to elaborate r-value: (cram_addr['sd0])?(cram_q_h):(cram_q_l)
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 4 (data_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 5 (q_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 9 (data_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643: warning: Port 10 (q_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:643:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 4 (data_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 5 (q_a) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 9 (data_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657: warning: Port 10 (q_b) of module dpram expects 16 bit(s), given 8.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:657:        : Padding 8 high bits of the port.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:277: error: Unable to bind wire/reg/memory `speed' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:499:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:277: error: Unable to elaborate condition expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:354: error: Unable to bind wire/reg/memory `reset' in `tb_gameboy_pr24_verilator.dut'
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:498:      : A symbol with that name was declared here. Check for declaration after use.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:354: error: Unable to elaborate condition expression.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:63: error: Variable 'HPS_BUS' cannot be driven by a primitive or continuous assignment with non-default strength.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:63: error: Inout port expression must support continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:63:      : Port 3 (HPS_BUS) of emu is connected to HPS_BUS
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:103: error: Variable 'SDRAM_DQ' cannot be driven by a primitive or continuous assignment with non-default strength.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:103: error: Inout port expression must support continuous assignment.
-testbench/MiSTer-devel_Gameboy_MiSTer_pr24/tb_gameboy_pr24_verilator.sv:103:      : Port 43 (SDRAM_DQ) of emu is connected to SDRAM_DQ
-96 error(s) during elaboration.

testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_p2p_buggy.log

@@ -1,63 +0,0 @@
-INFO: open-tool P2P fallback (buggy)
-INFO: native simulation P2P not applicable for this case
-
-### qsf_surelog:Gameboy-vip.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sys' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/timer.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite_sort.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprites.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/gb.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/hdma.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv' '-odir' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf'
-[INF:CM0023] Creating log file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf/slpp_all/surelog.log".
-
-[ERR:PP0101] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:131: Cannot open include file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/build_id.v".
-
-[ERR:PP0102] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:8: Unknown macro "BUILD_DATE".
-
-[SNT:PA0207] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:7: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier},
-	"V,v",SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!! 
-       ^-- testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf/slpp_all/lib/work/Gameboy.sv:155:7:.
-
-[  FATAL] : 0
-[ SYNTAX] : 1
-[  ERROR] : 2
-[WARNING] : 0
-[   NOTE] : 0
-
-rc=7
-
-### qsf_surelog:Gameboy.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sys' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/timer.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite_sort.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprites.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/gb.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/hdma.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv' '-odir' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf'
-[INF:CM0023] Creating log file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf/slpp_all/surelog.log".
-
-[ERR:PP0101] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:131: Cannot open include file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/build_id.v".
-
-[ERR:PP0102] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:8: Unknown macro "BUILD_DATE".
-
-[SNT:PA0207] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:7: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier},
-	"V,v",SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!! 
-       ^-- testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf/slpp_all/lib/work/Gameboy.sv:155:7:.
-
-[  FATAL] : 0
-[ SYNTAX] : 1
-[  ERROR] : 2
-[WARNING] : 0
-[   NOTE] : 0
-
-rc=7
-
-### qsf_surelog:Gameboy_Q13.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sys' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/timer.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite_sort.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprites.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/gb.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv' '-odir' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf'
-[INF:CM0023] Creating log file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf/slpp_all/surelog.log".
-
-[ERR:PP0101] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:131: Cannot open include file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/build_id.v".
-
-[ERR:PP0102] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:8: Unknown macro "BUILD_DATE".
-
-[SNT:PA0207] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:7: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier},
-	"V,v",SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!! 
-       ^-- testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_buggy_qsf/slpp_all/lib/work/Gameboy.sv:155:7:.
-
-[  FATAL] : 0
-[ SYNTAX] : 1
-[  ERROR] : 2
-[WARNING] : 0
-[   NOTE] : 0
-
-rc=7
-PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_p2p_fixed.log

@@ -1,63 +0,0 @@
-INFO: open-tool P2P fallback (fixed)
-INFO: native simulation P2P not applicable for this case
-
-### qsf_surelog:Gameboy-vip.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sys' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/timer.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite_sort.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprites.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/gb.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/hdma.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv' '-odir' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf'
-[INF:CM0023] Creating log file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf/slpp_all/surelog.log".
-
-[ERR:PP0101] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:131: Cannot open include file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/build_id.v".
-
-[ERR:PP0102] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:8: Unknown macro "BUILD_DATE".
-
-[SNT:PA0207] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:7: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier},
-	"V,v",SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!! 
-       ^-- testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf/slpp_all/lib/work/Gameboy.sv:155:7:.
-
-[  FATAL] : 0
-[ SYNTAX] : 1
-[  ERROR] : 2
-[WARNING] : 0
-[   NOTE] : 0
-
-rc=7
-
-### qsf_surelog:Gameboy.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sys' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/timer.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite_sort.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprites.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/gb.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/hdma.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv' '-odir' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf'
-[INF:CM0023] Creating log file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf/slpp_all/surelog.log".
-
-[ERR:PP0101] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:131: Cannot open include file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/build_id.v".
-
-[ERR:PP0102] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:8: Unknown macro "BUILD_DATE".
-
-[SNT:PA0207] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:7: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier},
-	"V,v",SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!! 
-       ^-- testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf/slpp_all/lib/work/Gameboy.sv:155:7:.
-
-[  FATAL] : 0
-[ SYNTAX] : 1
-[  ERROR] : 2
-[WARNING] : 0
-[   NOTE] : 0
-
-rc=7
-
-### qsf_surelog:Gameboy_Q13.qsf
-'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch' '-Itestbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sys' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sdram.sv' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/video.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/timer.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite_sort.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprites.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/sprite.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/lcd.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/gb.v' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv' '-odir' 'testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf'
-[INF:CM0023] Creating log file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf/slpp_all/surelog.log".
-
-[ERR:PP0101] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:131: Cannot open include file "testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/build_id.v".
-
-[ERR:PP0102] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:8: Unknown macro "BUILD_DATE".
-
-[SNT:PA0207] testbench/MiSTer-devel_Gameboy_MiSTer_pr24/snapshot_scratch/Gameboy.sv:155:7: Syntax error: mismatched input 'SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!!' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'type', 'const', 'local', 'super', '{', 'string', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier},
-	"V,v",SURELOG_MACRO_NOT_DEFINED:BUILD_DATE!!! 
-       ^-- testbench/MiSTer-devel_Gameboy_MiSTer_pr24/open_tool_fixed_qsf/slpp_all/lib/work/Gameboy.sv:155:7:.
-
-[  FATAL] : 0
-[ SYNTAX] : 1
-[  ERROR] : 2
-[WARNING] : 0
-[   NOTE] : 0
-
-rc=7
-PASS: open-tool P2P fallback not applicable: no open-tool check passed