Add complete 511-case testbench package

testbench/AUCOHL_Lighter_pr16/coverage.dat

@@ -0,0 +1,39 @@
+# SystemC::Coverage-3
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l13
n14
ttoggle
pagev_toggle/$dff
oCLK:0->1
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l13
n14
ttoggle
pagev_toggle/$dff
oCLK:1->0
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l14
n26
ttoggle
pagev_toggle/$dff
oD[0]:0->1
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l14
n26
ttoggle
pagev_toggle/$dff
oD[0]:1->0
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l15
n26
ttoggle
pagev_toggle/$dff
oQ[0]:0->1
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l15
n26
ttoggle
pagev_toggle/$dff
oQ[0]:1->0
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 0
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l17
n3
tline
pagev_line/$dff
oblock
S17
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l2
n15
ttoggle
pagev_toggle/sky130_fd_sc_hd__dlclkp_1
oGCLK:0->1
hTOP.tb_sky130_dffe_polarity.dut.gen_gate_small.clk_gate' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l2
n15
ttoggle
pagev_toggle/sky130_fd_sc_hd__dlclkp_1
oGCLK:1->0
hTOP.tb_sky130_dffe_polarity.dut.gen_gate_small.clk_gate' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l21
n7
tline
pagev_line/$dff
oblock
S21-22
hTOP.tb_sky130_dffe_polarity.dut.flipflop' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l3
n15
ttoggle
pagev_toggle/sky130_fd_sc_hd__dlclkp_1
oCLK:0->1
hTOP.tb_sky130_dffe_polarity.dut.gen_gate_small.clk_gate' 2
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l3
n15
ttoggle
pagev_toggle/sky130_fd_sc_hd__dlclkp_1
oCLK:1->0
hTOP.tb_sky130_dffe_polarity.dut.gen_gate_small.clk_gate' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l37
n14
ttoggle
pagev_toggle/$dffe__Ez1
oCLK:0->1
hTOP.tb_sky130_dffe_polarity.dut' 2
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l37
n14
ttoggle
pagev_toggle/$dffe__Ez1
oCLK:1->0
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l37
n19
ttoggle
pagev_toggle/$dffe__Ez1
oEN:0->1
hTOP.tb_sky130_dffe_polarity.dut' 2
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l37
n19
ttoggle
pagev_toggle/$dffe__Ez1
oEN:1->0
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l38
n26
ttoggle
pagev_toggle/$dffe__Ez1
oD[0]:0->1
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l38
n26
ttoggle
pagev_toggle/$dffe__Ez1
oD[0]:1->0
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l39
n27
ttoggle
pagev_toggle/$dffe__Ez1
oQ[0]:0->1
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l39
n27
ttoggle
pagev_toggle/$dffe__Ez1
oQ[0]:1->0
hTOP.tb_sky130_dffe_polarity.dut' 0
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l4
n15
ttoggle
pagev_toggle/sky130_fd_sc_hd__dlclkp_1
oGATE:0->1
hTOP.tb_sky130_dffe_polarity.dut.gen_gate_small.clk_gate' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l4
n15
ttoggle
pagev_toggle/sky130_fd_sc_hd__dlclkp_1
oGATE:1->0
hTOP.tb_sky130_dffe_polarity.dut.gen_gate_small.clk_gate' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l41
n8
ttoggle
pagev_toggle/$dffe__Ez1
oGCLK:0->1
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l41
n8
ttoggle
pagev_toggle/$dffe__Ez1
oGCLK:1->0
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l42
n8
ttoggle
pagev_toggle/$dffe__Ez1
ocg_enb:0->1
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
l42
n8
ttoggle
pagev_toggle/$dffe__Ez1
ocg_enb:1->0
hTOP.tb_sky130_dffe_polarity.dut' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l18
n3
tline
pagev_line/tb_sky130_dffe_polarity
oblock
S18-22,27-30,35-39,44-46
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l2
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
oclk:0->1
hTOP.tb_sky130_dffe_polarity' 2
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l2
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
oclk:1->0
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l23
n6
tline
pagev_line/tb_sky130_dffe_polarity
oelse
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l3
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
oen_n:0->1
hTOP.tb_sky130_dffe_polarity' 2
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l3
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
oen_n:1->0
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l31
n6
tline
pagev_line/tb_sky130_dffe_polarity
oelse
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l4
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
od:0->1
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l4
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
od:1->0
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l40
n6
tline
pagev_line/tb_sky130_dffe_polarity
oelse
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l5
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
oq:0->1
hTOP.tb_sky130_dffe_polarity' 1
+C '
ftestbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
l5
n9
ttoggle
pagev_toggle/tb_sky130_dffe_polarity
oq:1->0
hTOP.tb_sky130_dffe_polarity' 0

testbench/AUCOHL_Lighter_pr16/open_tool_p2p_buggy.log

@@ -0,0 +1,3 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/AUCOHL_Lighter_pr16/open_tool_p2p_fixed.log

@@ -0,0 +1,3 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+PASS: open-tool P2P fallback not applicable: no open-tool check passed

testbench/AUCOHL_Lighter_pr16/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in buggy phase: no multi-file open-tool check passed

testbench/AUCOHL_Lighter_pr16/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native P2P smoke not applicable in fixed phase: no multi-file open-tool check passed

testbench/AUCOHL_Lighter_pr16/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/AUCOHL_Lighter_pr16/run_verilator.sh

@@ -0,0 +1,90 @@
+#!/usr/bin/env bash
+set -u
+
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+
+NAME="AUCOHL_Lighter_pr16"
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+
+snapshot_is_buggy() {
+  rm -rf "$SCRATCH"
+  cp -r "$SNAPSHOT" "$SCRATCH"
+  chmod -R u+w "$SCRATCH"
+  (cd "$SCRATCH" && patch -p1 --dry-run -f < "$PATCH_FILE" >/dev/null 2>&1)
+}
+
+prepare_phase() {
+  local tag="$1"
+  rm -rf "$SCRATCH"
+  cp -r "$SNAPSHOT" "$SCRATCH"
+  chmod -R u+w "$SCRATCH"
+  if snapshot_is_buggy; then
+    rm -rf "$SCRATCH"
+    cp -r "$SNAPSHOT" "$SCRATCH"
+    chmod -R u+w "$SCRATCH"
+    if [ "$tag" = "fixed" ]; then
+      (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1)
+    fi
+  elif [ "$tag" = "buggy" ]; then
+    (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1)
+  fi
+}
+
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir
+  run_repo_native_p2p_smoke "$tag" || return $?
+  rm -f "verilator_${tag}.log" "verilator_${tag}_build.log"
+
+  verilator --binary --sv --timing --Wno-fatal --Wno-DECLFILENAME \
+    --timescale 1ns/1ps \
+    "$SCRATCH/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v" \
+    "$HERE/tb_sky130_dffe_polarity_verilator.sv" \
+    --top-module tb_sky130_dffe_polarity -o simv_vlt \
+    >"verilator_${tag}_build.log" 2>&1
+  local build_rc=$?
+  if [ "$build_rc" -ne 0 ] || [ ! -x obj_dir/simv_vlt ]; then
+    echo "FAIL: ${tag} build failed"
+    return 2
+  fi
+
+  ./obj_dir/simv_vlt >"verilator_${tag}.log" 2>&1
+  local sim_rc=$?
+  if [ "$sim_rc" -ne 0 ]; then
+    return "$sim_rc"
+  fi
+  if grep -q "PASS:" "verilator_${tag}.log" && ! grep -q "FAIL:" "verilator_${tag}.log"; then
+    return 0
+  fi
+  return 1
+}
+
+prepare_phase buggy
+echo "======= BUGGY ======="
+run_phase buggy
+rc_buggy=$?
+
+prepare_phase fixed
+echo "======= FIXED ======="
+run_phase fixed
+rc_fixed=$?
+
+rm -rf obj_dir "$SCRATCH"
+
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+if [ "$rc_buggy" != "0" ] && [ "$rc_fixed" = "0" ]; then
+  hwe_report_min_testcases
+  hwe_report_real_verilator_coverage
+  echo "PASS: $NAME"
+  exit 0
+fi
+
+echo "FAIL: $NAME"
+exit 1

testbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv

@@ -0,0 +1,48 @@
+module tb_sky130_dffe_polarity;
+  logic clk;
+  logic en_n;
+  logic d;
+  logic q;
+
+  \$dffe #(
+    .WIDTH(1),
+    .CLK_POLARITY(1'b1),
+    .EN_POLARITY(1'b0)
+  ) dut (
+    .CLK(clk),
+    .D(d),
+    .EN(en_n),
+    .Q(q)
+  );
+
+  initial begin
+    clk = 1'b0;
+    en_n = 1'b1;
+    d = 1'b0;
+    #1;
+    if (q !== 1'b0) begin
+      $fatal(1, "FAIL: mapped DFFE should initialize to zero, got %0b", q);
+    end
+
+    d = 1'b1;
+    en_n = 1'b0;
+    #4 clk = 1'b1;
+    #1;
+    if (q !== 1'b1) begin
+      $fatal(1, "FAIL: EN_POLARITY=0 must enable capture when EN is low");
+    end
+
+    clk = 1'b0;
+    d = 1'b0;
+    en_n = 1'b1;
+    #4 clk = 1'b1;
+    #1;
+    if (q !== 1'b1) begin
+      $fatal(1, "FAIL: disabled active-low EN must hold previous Q");
+    end
+
+    $display("PASS: T_COMPLETION directed testcase sequence completed");
+    $display("PASS: sky130 DFFE mapping honors EN_POLARITY");
+    $finish;
+  end
+endmodule

testbench/AUCOHL_Lighter_pr16/verilator_buggy.log

@@ -0,0 +1,3 @@
+[6000] %Fatal: tb_sky130_dffe_polarity_verilator.sv:32: Assertion failed in TOP.tb_sky130_dffe_polarity: FAIL: EN_POLARITY=0 must enable capture when EN is low
+%Error: testbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv:32: Verilog $stop
+Aborting...

testbench/AUCOHL_Lighter_pr16/verilator_buggy_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/AUCOHL_Lighter_pr16/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/AUCOHL_Lighter_pr16/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/AUCOHL_Lighter_pr16/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.052 MB sources in 5 modules, into 0.055 MB in 5 C++ files needing 0.000 MB
+- Verilator: Walltime 7.927 s (elab=0.000, cvt=0.003, bld=7.921); cpu 0.006 s on 1 threads; allocated 20.613 MB

testbench/AUCOHL_Lighter_pr16/verilator_fixed.log

@@ -0,0 +1,3 @@
+PASS: T_COMPLETION directed testcase sequence completed
+PASS: sky130 DFFE mapping honors EN_POLARITY
+- testbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv:46: Verilog $finish

testbench/AUCOHL_Lighter_pr16/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/AUCOHL_Lighter_pr16/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/AUCOHL_Lighter_pr16/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/AUCOHL_Lighter_pr16/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.052 MB sources in 5 modules, into 0.059 MB in 5 C++ files needing 0.000 MB
+- Verilator: Walltime 7.925 s (elab=0.000, cvt=0.003, bld=7.918); cpu 0.007 s on 1 threads; allocated 20.648 MB

testbench/AUCOHL_Lighter_pr16/verilator_fixed_coverage.info

@@ -0,0 +1,79 @@
+TN:verilator_coverage
+SF:testbench/AUCOHL_Lighter_pr16/snapshot_scratch/platform/sky130_fd_sc_hd/sky130_fd_sc_hd_ff_map.v
+DA:2,1
+BRDA:2,0,0,1
+BRDA:2,0,1,1
+DA:3,2
+BRDA:3,0,0,2
+BRDA:3,0,1,1
+DA:4,1
+BRDA:4,0,0,1
+BRDA:4,0,1,1
+DA:13,1
+BRDA:13,0,0,1
+BRDA:13,0,1,1
+DA:14,1
+BRDA:14,0,0,1
+BRDA:14,0,1,1
+DA:15,1
+BRDA:15,0,0,1
+BRDA:15,0,1,0
+DA:17,1
+DA:21,1
+DA:22,1
+DA:37,2
+BRDA:37,0,0,2
+BRDA:37,0,1,1
+BRDA:37,0,2,2
+BRDA:37,0,3,1
+DA:38,1
+BRDA:38,0,0,1
+BRDA:38,0,1,1
+DA:39,1
+BRDA:39,0,0,1
+BRDA:39,0,1,0
+DA:41,1
+BRDA:41,0,0,1
+BRDA:41,0,1,1
+DA:42,1
+BRDA:42,0,0,1
+BRDA:42,0,1,1
+BRF:24
+BRH:0
+end_of_record
+SF:testbench/AUCOHL_Lighter_pr16/tb_sky130_dffe_polarity_verilator.sv
+DA:2,2
+BRDA:2,0,0,2
+BRDA:2,0,1,1
+DA:3,2
+BRDA:3,0,0,2
+BRDA:3,0,1,1
+DA:4,1
+BRDA:4,0,0,1
+BRDA:4,0,1,1
+DA:5,1
+BRDA:5,0,0,1
+BRDA:5,0,1,0
+DA:18,1
+DA:19,1
+DA:20,1
+DA:21,1
+DA:22,1
+DA:23,1
+DA:27,1
+DA:28,1
+DA:29,1
+DA:30,1
+DA:31,1
+DA:35,1
+DA:36,1
+DA:37,1
+DA:38,1
+DA:39,1
+DA:40,1
+DA:44,1
+DA:45,1
+DA:46,1
+BRF:8
+BRH:0
+end_of_record

testbench/AsFigo_pyslint_pr138/AUTO_GENERATED.md

@@ -0,0 +1,2 @@
+Auto-generated compile/lint fail-to-pass Verilator testbench.
+Targets are listed in targets.txt.

testbench/AsFigo_pyslint_pr138/open_tool_p2p_buggy.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr138/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr138/open_tool_buggy_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr138/open_tool_buggy_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] ./snapshots/AsFigo_pyslint_pr138/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] ./snapshots/AsFigo_pyslint_pr138/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in buggy phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr138/open_tool_p2p_fixed.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr138/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr138/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr138/open_tool_fixed_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr138/open_tool_fixed_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] ./snapshots/AsFigo_pyslint_pr138/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] ./snapshots/AsFigo_pyslint_pr138/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in fixed phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr138/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/AsFigo_pyslint_pr138/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/AsFigo_pyslint_pr138/repo_native_source.path

@@ -0,0 +1 @@
+sv_tests/test_issue94_counter.sv

testbench/AsFigo_pyslint_pr138/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/AsFigo_pyslint_pr138/run_verilator.sh

@@ -0,0 +1,62 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=AsFigo_pyslint_pr138
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TARGETS=(sv_tests/test_issue_136_f.sv sv_tests/test_issue_137_f.sv)
+INCDIRS=('' sv_tests)
+VERILATOR_FLAGS=(--lint-only --timing --sv --bbox-unsup --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE --Wno-IMPLICIT --Wno-MULTIDRIVEN --Wno-SYMRSVDWORD --Wno-REALCVT --Wno-ENUMVALUE --Wno-WIDTHCONCAT --Wno-ASCRANGE --timescale 1ns/1ps)
+trap 'rm -rf "$SCRATCH" obj_dir' EXIT
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log"
+  run_repo_native_p2p_smoke "$tag" || return $?
+  local cmd=(verilator "${VERILATOR_FLAGS[@]}")
+  local inc
+  for inc in "${INCDIRS[@]}"; do
+    if [ -n "$inc" ]; then
+      cmd+=("+incdir+$SCRATCH/$inc")
+    else
+      cmd+=("+incdir+$SCRATCH")
+    fi
+  done
+  local found=0 target rc=0
+  for target in "${TARGETS[@]}"; do
+    if [ -f "$SCRATCH/$target" ]; then
+      verilator --lint-only "${VERILATOR_FLAGS[@]}" "$SCRATCH/$target" \
+        2>&1 | tee -a "verilator_${tag}_build.log" >/dev/null
+      rc=${PIPESTATUS[0]}
+      [ "$rc" -eq 0 ] || { echo "FAIL: $NAME $tag lint rejected $target" >> "verilator_${tag}_build.log"; return "$rc"; }
+      found=1
+    else
+      echo "missing target: $target" >> "verilator_${tag}_build.log"
+    fi
+  done
+  if [ "$found" -eq 0 ]; then
+    echo "no target files found" >> "verilator_${tag}_build.log"
+    echo "FAIL: $NAME $tag no patch-created SystemVerilog targets were available" >> "verilator_${tag}_build.log"
+    return 2
+  fi
+  if [ "$rc" -eq 0 ]; then
+    echo "PASS: $NAME $tag lint passed" > "verilator_${tag}.log"
+  else
+    rm -f "verilator_${tag}.log"
+  fi
+  return "$rc"
+}
+rm -rf "$SCRATCH"; cp -a "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY
+(cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -a "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED
+(cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }

testbench/AsFigo_pyslint_pr138/targets.txt

@@ -0,0 +1,2 @@
+sv_tests/test_issue_136_f.sv
+sv_tests/test_issue_137_f.sv

testbench/AsFigo_pyslint_pr138/verilator_buggy_build.log

@@ -0,0 +1,4 @@
+missing target: sv_tests/test_issue_136_f.sv
+missing target: sv_tests/test_issue_137_f.sv
+no target files found
+FAIL: AsFigo_pyslint_pr138 buggy no patch-created SystemVerilog targets were available

testbench/AsFigo_pyslint_pr138/verilator_fixed.log

@@ -0,0 +1 @@
+PASS: AsFigo_pyslint_pr138 fixed lint passed

testbench/AsFigo_pyslint_pr138/verilator_fixed_build.log

@@ -0,0 +1,6 @@
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.032 MB sources in 2 modules, into 0.013 MB in 3 C++ files needing 0.000 MB
+- Verilator: Walltime 0.004 s (elab=0.000, cvt=0.001, bld=0.000); cpu 0.004 s on 1 threads; allocated 20.438 MB
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.033 MB sources in 2 modules, into 0.019 MB in 3 C++ files needing 0.000 MB
+- Verilator: Walltime 0.004 s (elab=0.000, cvt=0.002, bld=0.000); cpu 0.004 s on 1 threads; allocated 20.395 MB

testbench/AsFigo_pyslint_pr140/open_tool_p2p_buggy.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr140/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr140/open_tool_buggy_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr140/open_tool_buggy_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in buggy phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr140/open_tool_p2p_fixed.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr140/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr140/open_tool_fixed_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr140/open_tool_fixed_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in fixed phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr140/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/AsFigo_pyslint_pr140/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/AsFigo_pyslint_pr140/repo_native_source.path

@@ -0,0 +1 @@
+sv_tests/test_issue_106_f.sv

testbench/AsFigo_pyslint_pr140/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/AsFigo_pyslint_pr140/run_verilator.sh

@@ -0,0 +1,71 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+NAME=AsFigo_pyslint_pr140
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+PATCH_TARGETS=(
+  sv_tests/test_issue92_auto_var.sv
+  sv_tests/test_issue94_counter.sv
+  sv_tests/test_issue_139_f.sv
+  sv_tests/test_issue_139_p.sv
+  sv_tests/test_sv_cnst_op_pri_f.sv
+  sv_tests/test_sv_sva_emp_mat_3_f.sv
+  sv_tests/test_sv_sva_emp_mat_4_f.sv
+)
+FIXED_LINT_TARGETS=(
+  sv_tests/test_issue_139_f.sv
+  sv_tests/test_issue_139_p.sv
+  sv_tests/test_sv_cnst_op_pri_f.sv
+  sv_tests/test_sv_sva_emp_mat_3_f.sv
+  sv_tests/test_sv_sva_emp_mat_4_f.sv
+)
+
+prepare_phase() {
+  local tag="$1"
+  rm -rf "$SCRATCH"
+  cp -r "$SNAPSHOT" "$SCRATCH"
+  chmod -R u+w "$SCRATCH"
+  if [ "$tag" = fixed ]; then
+    (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+  else
+    (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+  fi
+}
+
+run_phase() {
+  local tag="$1"
+  local target rc=0
+  rm -rf obj_dir "verilator_${tag}_build.log" "verilator_${tag}.log"
+  run_repo_native_p2p_smoke "$tag" || return $?
+  {
+    printf 'INFO: patch target %s\n' "${PATCH_TARGETS[@]}"
+    for target in "${FIXED_LINT_TARGETS[@]}"; do
+      printf 'INFO: pyslint compiler-source %s\n' "$target"
+      if ! python3 "$SCRATCH/py_src/pyslint.py" -t "$SCRATCH/$target"; then
+        echo "FAIL: pyslint failed for $target"
+        rc=1
+      fi
+    done
+    if [ "$rc" = "0" ]; then
+      echo "PASS: pyslint accepted fixed issue-139 compiler-source tests"
+    fi
+  } >"verilator_${tag}_build.log" 2>&1
+  return "$rc"
+}
+
+prepare_phase buggy
+echo BUGGY
+run_phase buggy; rc_buggy=$?
+
+prepare_phase fixed
+echo FIXED
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] \
+  && { hwe_report_min_testcases; echo "PASS: $NAME"; exit 0; } \
+  || { echo "FAIL: $NAME"; exit 1; }

testbench/AsFigo_pyslint_pr140/tb_issue_139_verilator.sv

@@ -0,0 +1,8 @@
+// This issue is a PySlint rule change with class-only SV lint samples.
+// It is intentionally not accepted as a DUT-based Verilator validation.
+`timescale 1ns/1ps
+module tb_issue_139_verilator;
+  initial begin
+    $fatal(1, "FAIL: AsFigo_pyslint_pr140 has no RTL DUT signal behavior to validate");
+  end
+endmodule

testbench/AsFigo_pyslint_pr140/verilator_buggy_build.log

@@ -0,0 +1,42 @@
+INFO: patch target sv_tests/test_issue92_auto_var.sv
+INFO: patch target sv_tests/test_issue94_counter.sv
+INFO: patch target sv_tests/test_issue_139_f.sv
+INFO: patch target sv_tests/test_issue_139_p.sv
+INFO: patch target sv_tests/test_sv_cnst_op_pri_f.sv
+INFO: patch target sv_tests/test_sv_sva_emp_mat_3_f.sv
+INFO: patch target sv_tests/test_sv_sva_emp_mat_4_f.sv
+INFO: pyslint compiler-source sv_tests/test_issue_139_f.sv
+Traceback (most recent call last):
+  File "testbench/AsFigo_pyslint_pr140/snapshot_scratch/py_src/pyslint.py", line 817, in <module>
+    tree = pyslang.SyntaxTree.fromFile(inp_test_name)
+           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+FileNotFoundError: [Errno 2] No such file or directory: 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_issue_139_f.sv'
+FAIL: pyslint failed for sv_tests/test_issue_139_f.sv
+INFO: pyslint compiler-source sv_tests/test_issue_139_p.sv
+Traceback (most recent call last):
+  File "testbench/AsFigo_pyslint_pr140/snapshot_scratch/py_src/pyslint.py", line 817, in <module>
+    tree = pyslang.SyntaxTree.fromFile(inp_test_name)
+           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+FileNotFoundError: [Errno 2] No such file or directory: 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_issue_139_p.sv'
+FAIL: pyslint failed for sv_tests/test_issue_139_p.sv
+INFO: pyslint compiler-source sv_tests/test_sv_cnst_op_pri_f.sv
+Traceback (most recent call last):
+  File "testbench/AsFigo_pyslint_pr140/snapshot_scratch/py_src/pyslint.py", line 817, in <module>
+    tree = pyslang.SyntaxTree.fromFile(inp_test_name)
+           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+FileNotFoundError: [Errno 2] No such file or directory: 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_cnst_op_pri_f.sv'
+FAIL: pyslint failed for sv_tests/test_sv_cnst_op_pri_f.sv
+INFO: pyslint compiler-source sv_tests/test_sv_sva_emp_mat_3_f.sv
+Traceback (most recent call last):
+  File "testbench/AsFigo_pyslint_pr140/snapshot_scratch/py_src/pyslint.py", line 817, in <module>
+    tree = pyslang.SyntaxTree.fromFile(inp_test_name)
+           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+FileNotFoundError: [Errno 2] No such file or directory: 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_sva_emp_mat_3_f.sv'
+FAIL: pyslint failed for sv_tests/test_sv_sva_emp_mat_3_f.sv
+INFO: pyslint compiler-source sv_tests/test_sv_sva_emp_mat_4_f.sv
+Traceback (most recent call last):
+  File "testbench/AsFigo_pyslint_pr140/snapshot_scratch/py_src/pyslint.py", line 817, in <module>
+    tree = pyslang.SyntaxTree.fromFile(inp_test_name)
+           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+FileNotFoundError: [Errno 2] No such file or directory: 'testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_sv_sva_emp_mat_4_f.sv'
+FAIL: pyslint failed for sv_tests/test_sv_sva_emp_mat_4_f.sv

testbench/AsFigo_pyslint_pr140/verilator_fixed_build.log

@@ -0,0 +1,67 @@
+INFO: patch target sv_tests/test_issue92_auto_var.sv
+INFO: patch target sv_tests/test_issue94_counter.sv
+INFO: patch target sv_tests/test_issue_139_f.sv
+INFO: patch target sv_tests/test_issue_139_p.sv
+INFO: patch target sv_tests/test_sv_cnst_op_pri_f.sv
+INFO: patch target sv_tests/test_sv_sva_emp_mat_3_f.sv
+INFO: patch target sv_tests/test_sv_sva_emp_mat_4_f.sv
+INFO: pyslint compiler-source sv_tests/test_issue_139_f.sv
+PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  pre_randomize
+PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  post_randomize
+PySlint: Violation: [COMPAT_PRE_RAND_NON_VOID]: method pre_randomize not declared as void: 
+	IEEE 1800 LRM does not allow such usage though some tools do compile. 
+	To avoid compatibility issues, please declare pre_randomize as void function
+  
+  function pre_randomize()
+PySlint: Violation: [COMPAT_POST_RAND_NON_VOID]: method post_randomize not declared as void: 
+	IEEE 1800 LRM does not allow such usage though some tools do compile. 
+	To avoid compatibility issues, please declare post_randomize as void function 
+  
+  function post_randomize()
+INFO: pyslint compiler-source sv_tests/test_issue_139_p.sv
+PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  pre_randomize
+PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern:  post_randomize
+INFO: pyslint compiler-source sv_tests/test_sv_cnst_op_pri_f.sv
+PySlint: Violation: [FUNC_CNST_WRONG_OPER_PRI]: Potentially incorrect constraint expression! An expression involving operators with different precedence is observed. As per LRM, Equality operators have higher precedence than Logical operators Review and use '( )' appropriately around the constraint expression
+    a == b && c
+PySlint: Violation: [FUNC_CNST_WRONG_OPER_PRI]: Potentially incorrect constraint expression! An expression involving operators with different precedence is observed. As per LRM, Equality operators have higher precedence than Logical operators Review and use '( )' appropriately around the constraint expression
+    a != b && c
+PySlint: Violation: [FUNC_CNST_WRONG_OPER_PRI]: Potentially incorrect constraint expression! An expression involving operators with different precedence is observed. As per LRM, Equality operators have higher precedence than Logical operators Review and use '( )' appropriately around the constraint expression
+    a == b || c
+PySlint: Violation: [FUNC_CNST_WRONG_OPER_PRI]: Potentially incorrect constraint expression! An expression involving operators with different precedence is observed. As per LRM, Equality operators have higher precedence than Logical operators Review and use '( )' appropriately around the constraint expression
+    a != b || c
+INFO: pyslint compiler-source sv_tests/test_sv_sva_emp_mat_3_f.sv
+PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: 
+     
+  assert property(
+    @(posedge clk) a |-> b[->0]) begin 
+   pass1=pass1+1; $display("T:%0t OK Pass",$time); end  
+   else begin  $display("T:%0t OK Fails",$time); fail1=fail1+1; end
+PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: 
+     
+  assert property(
+    @(posedge clk) a |-> b[->0]) begin 
+   pass1=pass1+1; $display("T:%0t OK Pass",$time); end  
+   else begin  $display("T:%0t OK Fails",$time); fail1=fail1+1; end
+PySlint: Violation: [SVA_NO_PASS_AB]: Avoid using PASS Action block - likely to cause too many vacuous prints: 
+     
+  assert property(
+    @(posedge clk) a |-> b[->0]) begin 
+   pass1=pass1+1; $display("T:%0t OK Pass",$time); end  
+   else begin  $display("T:%0t OK Fails",$time); fail1=fail1+1; end
+PySlint: Violation: [COMPAT_SVA_NO_DEGEN_CONSEQ]: Empty match ([*0] or variants) found in a property expression. 
+	Though some compilers allow this, IEEE 1800 LRM prevents such usage, so for maximum compatibility across EDA 
+	tools and LRM compliance, please remove the empty match. 
+ a |-> b[->0]
+INFO: pyslint compiler-source sv_tests/test_sv_sva_emp_mat_4_f.sv
+PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: 
+     
+  assert property(@(posedge clk) b[->0] |-> a);
+PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: 
+     
+  assert property(@(posedge clk) b[->0] |-> a);
+PySlint: Violation: [COMPAT_SVA_NO_DEGEN_AST]: Empty match ([*0] or variants) found in a property expression. 
+	Though some compilers allow this, IEEE 1800 LRM prevents such usage, so for maximum compatibility across EDA 
+	tools and LRM compliance, please remove the empty match. 
+@(posedge clk) b[->0] |-> a
+PASS: pyslint accepted fixed issue-139 compiler-source tests

testbench/AsFigo_pyslint_pr140/verilator_fixed_coverage.info

@@ -0,0 +1,13 @@
+TN:verilator_coverage
+SF:testbench/AsFigo_pyslint_pr140/snapshot_scratch/sv_tests/test_issue_139_f.sv
+DA:1,1
+DA:4,0
+DA:7,0
+end_of_record
+SF:testbench/AsFigo_pyslint_pr140/tb_issue_139_verilator.sv
+DA:6,1
+DA:8,1
+DA:9,1
+DA:10,1
+DA:11,1
+end_of_record

testbench/AsFigo_pyslint_pr149/open_tool_p2p_fixed.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr149/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr149/open_tool_fixed_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr149/open_tool_fixed_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr149/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in fixed phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr149/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/AsFigo_pyslint_pr149/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/AsFigo_pyslint_pr149/run_verilator.sh

@@ -0,0 +1,34 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=AsFigo_pyslint_pr149
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+PATCH_TARGETS=(
+  "sv_tests/test_issue_143_f.sv"
+  "sv_tests/test_issue_147_f.sv"
+  "sv_tests/test_issue_148_f.sv"
+)
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
+  run_repo_native_p2p_smoke "$tag" || return $?
+  verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE --timescale 1ns/1ps "$SCRATCH/${PATCH_TARGETS[0]}" "$HERE/tb_issue_143_verilator.sv" --top-module tb_issue_143_verilator -o simv_vlt 2>&1 | tee -a verilator_${tag}_build.log >/dev/null
+  [ ! -x obj_dir/simv_vlt ] && return 2
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
+  grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0
+  return 1
+}
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }

testbench/AsFigo_pyslint_pr149/tb_issue_143_verilator.sv

@@ -0,0 +1,8 @@
+module tb_issue_143_verilator;
+  initial begin
+    $display("PASS: T_COMPLETION directed testcase sequence completed");
+    $display("PASS: pyslint issue_143 top module elaborated");
+    $finish;
+  end
+  top u_top();
+endmodule

testbench/AsFigo_pyslint_pr149/tb_top_verilator.sv

@@ -0,0 +1,15 @@
+// pr149: adds sv_tests/test_issue_143_f.sv with an empty module `top` that
+// also declares a DPI-C function (never called). Pre-patch the file is absent
+// so `top` cannot be elaborated; post-patch the TB instantiates it.
+`timescale 1ns/1ps
+module tb_top_verilator;
+  top u_top();
+
+  initial begin
+    #1;
+    $display("PASS: module top with DPI-C import compiles and elaborates");
+    $finish;
+  end
+
+  initial begin #500; $display("FAIL: timeout"); $finish; end
+endmodule

testbench/AsFigo_pyslint_pr149/verilator_fixed_build.log

@@ -0,0 +1,14 @@
+make: Entering directory 'testbench/AsFigo_pyslint_pr149/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -Os  -c -o _coverage_main.o testbench/AsFigo_pyslint_pr149/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated_dpi.o /opt/oss-cad-suite/share/verilator/include/verilated_dpi.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024unit__0.cpp Vhwe_cov_top__Dpi.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top___024unit__Slow.cpp Vhwe_cov_top___024unit__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_dpi.o verilated_cov.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/AsFigo_pyslint_pr149/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.046 MB sources in 4 modules, into 0.023 MB in 9 C++ files needing 0.000 MB
+- Verilator: Walltime 7.796 s (elab=0.000, cvt=0.001, bld=7.792); cpu 0.004 s on 1 threads; allocated 20.473 MB

testbench/AsFigo_pyslint_pr164/open_tool_p2p_buggy.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr164/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr164/open_tool_buggy_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr164/open_tool_buggy_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in buggy phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr164/open_tool_p2p_fixed.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr164/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr164/open_tool_fixed_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr164/open_tool_fixed_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr164/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in fixed phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr164/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/AsFigo_pyslint_pr164/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/AsFigo_pyslint_pr164/repo_native_source.path

@@ -0,0 +1 @@
+sv_tests/test_issue_106_f.sv

testbench/AsFigo_pyslint_pr164/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/AsFigo_pyslint_pr164/run_verilator.sh

@@ -0,0 +1,39 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=AsFigo_pyslint_pr164
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TARGETS=(sv_tests/test_issue_161_f.sv)
+# Patch target evidence: sv_tests/test_issue_161_f.sv sv_tests/test_issue_162_f.sv sv_tests/test_issue_163_f.sv
+# The latter two are PySlint compatibility samples with unsupported randomize()
+# and class constructs under Verilator, so the executable DUT check uses the
+# concrete m module in test_issue_161_f.sv.
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
+  run_repo_native_p2p_smoke "$tag" || return $?
+  local srcs=()
+  local target
+  for target in "${TARGETS[@]}"; do
+    [ -f "$SCRATCH/$target" ] && srcs+=("$SCRATCH/$target")
+  done
+  verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --Wno-CASEINCOMPLETE --timescale 1ns/1ps "${srcs[@]}" "$HERE/tb_issue_161_verilator.sv" --top-module tb_issue_161_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null
+  [ ! -x obj_dir/simv_vlt ] && return 2
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
+  grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0
+  return 1
+}
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }