{\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if they registers are known","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"Nitpick. IMO, looks more natural to read in English if it is in imperative mode than third person singular.\n```suggestion\n (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n```","path":"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs","hunk":"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"Same.\n```suggestion\n (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n```","path":"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs","hunk":"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"```suggestion\n commutative: true;\n```","path":"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs","hunk":"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if they registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n+\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assigns right;\n+ if right is 0 assigns left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assigns left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assigns right;\n+ if right is 1 assigns left;\n+ if left is 0 assigns 0;\n+ if right is 0 assigns 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assigns left;\n+ if left is 0 assigns 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assigns 1;\n+ if right is 1 assigns left;\n+ if left is 0 assigns 0;\n+ if left is 1 assigns 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assigns 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assigns left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assigns 0;\n+ if right is 0 assigns 0;\n+ commutative: true;","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"Just thinking, for testing `constant_propagate` it makes no difference, but in a general case, optimizations run on functions and most of them do not care if it is an entry or not.\n\nSo I guess the most general case would be `function: Some((\"dummy_test_fn\", false))` but indeed if feels strange as a default.\n\nI would say let's keep it like this and once we start adding tests for other optimizations we can have in addition `optimise_fn`, `optimise_entry` or whatever needed.","path":"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs","hunk":"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assigns $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if they registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n+\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assigns right;\n+ if right is 0 assigns left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assigns left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assigns right;\n+ if right is 1 assigns left;\n+ if left is 0 assigns 0;\n+ if right is 0 assigns 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assigns left;\n+ if left is 0 assigns 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assigns 1;\n+ if right is 1 assigns left;\n+ if left is 0 assigns 0;\n+ if left is 1 assigns 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assigns 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assigns left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assigns 0;\n+ if right is 0 assigns 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assigns right;\n+ if right is 0 assigns left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assigns right;\n+ if right is 0 assigns left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assigns left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assigns left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n- }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::Full,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::Full\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::Full,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::Full,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"Having a test for overflow would be good. Adding two known values that result in an overflow should not do any replacement.","path":"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs","hunk":"@@ -174,75 +204,697 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n+\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n- }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"Same here for underflow.","path":"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs","hunk":"@@ -174,75 +204,697 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n+\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n- }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"And here for overflow again.","path":"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs","hunk":"@@ -174,75 +204,697 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n+\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n- }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\nindex 1f0a93772bb..90ecbdb9768 100644\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\n@@ -1,13 +1,15 @@\n-use std::collections::hash_map::Entry;\n-\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use crate::asm_lang::{\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\n+ VirtualRegister,\n+};\n use either::Either;\n use rustc_hash::FxHashMap;\n-\n-use crate::asm_lang::{\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\n+use std::{\n+ collections::hash_map::Entry,\n+ ops::{BitAnd, BitOr, BitXor, Not},\n };\n-\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\n+use sway_types::Span;\n \n #[derive(Clone, Debug, PartialEq, Eq)]\n enum KnownRegValue {\n@@ -36,6 +38,11 @@ impl KnownRegValue {\n }\n }\n \n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\n+ let raw = self.value()?;\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\n+ }\n+\n /// Check if the value depends on value of another register.\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\n match self {\n@@ -60,14 +67,24 @@ impl KnownValues {\n }\n }\n \n- /// Clear values that depend on a register having a specific value.\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\n- self.values.retain(|_, v| !v.depends_on(reg));\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\n+ let mut worklist = vec![reg.clone()];\n+\n+ while let Some(reg) = worklist.pop() {\n+ let keys = self\n+ .values\n+ .extract_if(|_, v| v.depends_on(®))\n+ .map(|(k, _)| k);\n+ worklist.extend(keys);\n+\n+ self.values.remove(®);\n+ }\n }\n \n /// Insert a known value for a register.\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\n- self.clear_dependent_on(&dst);\n+ self.remove_reg_and_dependents(&dst);\n self.values.insert(dst, value);\n }\n }\n@@ -75,34 +92,42 @@ impl KnownValues {\n /// What knowledge is lost after an op we don't know how to interpret?\n #[derive(Clone, Debug)]\n enum ResetKnown {\n- /// Reset all known values\n- Full,\n- /// Reset non-virtual registers in addition to defs\n- NonVirtual,\n+ /// Do nothing\n+ Nothing,\n /// Only the `def_registers` and `def_const_registers` are reset\n Defs,\n+ /// Reset non-virtual registers in addition to defs\n+ DefsAndNonVirtuals,\n+ /// Reset all known values\n+ All,\n }\n+\n impl ResetKnown {\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\n+ // All instruction write to $of and $err somehow.\n+ // Majority of cases we clear them\n+ known_values\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\n+\n match self {\n- ResetKnown::Full => {\n- known_values.values.clear();\n+ ResetKnown::Nothing => {}\n+ ResetKnown::Defs => {\n+ for d in op.def_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n+ for d in op.def_const_registers() {\n+ known_values.remove_reg_and_dependents(d);\n+ }\n }\n- ResetKnown::NonVirtual => {\n+ ResetKnown::DefsAndNonVirtuals => {\n Self::Defs.apply(op, known_values);\n known_values\n .values\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\n }\n- ResetKnown::Defs => {\n- for d in op.def_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n- for d in op.def_const_registers() {\n- known_values.clear_dependent_on(d);\n- known_values.values.remove(d);\n- }\n+ ResetKnown::All => {\n+ known_values.values.clear();\n }\n }\n }\n@@ -110,7 +135,10 @@ impl ResetKnown {\n \n impl AbstractInstructionSet {\n /// Symbolically interpret code and propagate known register values.\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\n+ pub(crate) fn constant_propagate(\n+ mut self,\n+ mut log: impl FnMut(&str),\n+ ) -> AbstractInstructionSet {\n if self.ops.is_empty() {\n return self;\n }\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\n \n for op in &mut self.ops {\n // Perform constant propagation on the instruction.\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\n- for reg in uses_regs.iter_mut() {\n+ for reg in op.use_registers_mut() {\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\n if !reg.is_virtual() {\n continue;\n }\n+\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\n- **reg = r;\n+ *reg = r;\n }\n }\n \n- // Some instructions can be further simplified with the known values.\n+ // Replace \"JNZ reg LABEL\" to\n+ // - NOOP if the reg is zero, or\n+ // - \"JMP LABEL\" if reg is not zero\n if let Either::Right(ControlFlowOp::Jump {\n to,\n type_: JumpType::NotZero(reg),\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\n }\n }\n \n- // Some ops are known to produce certain results, interpret them here.\n- let interpreted_op = match &op.opcode {\n+ // This macro must be declared here to be able to capture some variables\n+ macro_rules! transform_operator {\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\n+ };\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\n+ };\n+ // If the value is one of the operands, we will use MOVE\n+ // if it is a literal we will use MOVI\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\n+ };\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\n+ }};\n+ // if left == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // if right == $initial_value assign $end_value\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\n+ // The line above can bail so we must run it before we change anything\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\n+ op.opcode = new_opcode;\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // When both register values are known transform to MOVI\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\n+ return Some(ResetKnown::Nothing);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ // Transform from $op to $opI because $op is commutative\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\n+ };\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\n+ };\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\n+ compile_error!(stringify!($($rest)*))\n+ };\n+ // Transform from $op to $opI if $opI was defined.\n+ // Otherwise does not generate code\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ };\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\n+ return Some(ResetKnown::Defs);\n+ }\n+ };\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\n+ let mut f = || -> Option<ResetKnown> {\n+ match &op.opcode {\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\n+ let lv = known_values.resolve(&l);\n+ let rv = known_values.resolve(&r);\n+ log(&format!(\" {:?} {:?}\\n\", lv, rv));\n+\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\n+ }\n+ _ => {}\n+ };\n+ None\n+ };\n+ f()\n+ }};\n+ }\n+\n+ let before = format!(\"{op}\");\n+ log(&format!(\"{op}\\n\"));\n+\n+ // Propagate constant of some ops\n+ // Also transform them if their registers are known\n+ let reset = match op.opcode.clone() {\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\n let imm = KnownRegValue::Const(imm.value() as u64);\n- if known_values.resolve(dst) == Some(imm.clone()) {\n+\n+ // transform\n+ // movi <dest is known> <imm>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), imm);\n+ known_values.assign(dst, imm);\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n Either::Left(VirtualOp::MOVE(dst, src)) => {\n- if let Some(known) = known_values.resolve(src) {\n- if known_values.resolve(dst) == Some(known.clone()) {\n+ if let Some(known_src) = known_values.resolve(&src) {\n+ // transform\n+ // move <dest is known> <src is known>\n+ // to\n+ // noop\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\n op.opcode = Either::Left(VirtualOp::NOOP);\n } else {\n- known_values.assign(dst.clone(), known);\n+ // transform\n+ // move <dest is unknown> <src is known>\n+ // to\n+ // movi dest imm\n+ if let Some(imm) = known_src.value_as_imm18() {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\n+ }\n+\n+ known_values.assign(dst.clone(), known_src);\n }\n } else {\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\n+ known_values.assign(dst, KnownRegValue::Eq(src));\n }\n- true\n+\n+ Some(ResetKnown::Nothing)\n }\n- _ => false,\n- };\n \n- // If we don't know how to interpret the op, it's outputs are not known.\n- if !interpreted_op {\n- let reset = match &op.opcode {\n- Either::Left(op) => match op {\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\n- // TODO: this constraint can be relaxed\n- _ if op.has_side_effect() => ResetKnown::Full,\n- _ => ResetKnown::Defs,\n- },\n- Either::Right(op) => match op {\n- // If this is a jump target, then multiple execution paths can lead to it,\n- // and we can't assume to know register values.\n- ControlFlowOp::Label(label) => {\n- if jump_target_labels.contains_key(label) {\n- ResetKnown::Full\n- } else {\n- ResetKnown::Defs\n- }\n+ // algebraic operators\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\n+ both_known: u64::checked_add;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\n+ both_known: u64::checked_sub;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\n+ both_known: u64::checked_mul;\n+ if left is 1 assign right;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\n+ both_known: u64::checked_div;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ },\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\n+ both_known: u64::checked_pow;\n+ if right is 0 assign 1;\n+ if right is 1 assign left;\n+ if left is 0 assign 0;\n+ if left is 1 assign 1;\n+ },\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\n+ both_known: u64::checked_ilog;\n+ },\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\n+ both_known: u64::checked_rem;\n+ if right is 1 assign 0;\n+ },\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\n+ both_known: checked_nth_root;\n+ if right is 1 assign left;\n+ },\n+\n+ // bitwise\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\n+ let argv = known_values.resolve(&arg);\n+ log(&format!(\" {:?}\\n\", argv));\n+ if let Some(KnownRegValue::Const(argv)) = argv {\n+ let raw = argv.not();\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\n+\n+ let span = op.owning_span.clone();\n+ if let Ok(v) =\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\n+ {\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\n }\n- // Jumping away doesn't invalidate state, but for calls:\n- // TODO: `def_const_registers` doesn't contain return value, which\n- // seems incorrect, so I'm clearing everything as a precaution\n- ControlFlowOp::Jump { type_, .. } => match type_ {\n- JumpType::Call => ResetKnown::Full,\n+\n+ Some(ResetKnown::Nothing)\n+ } else {\n+ None\n+ }\n+ }\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\n+ both_known: u64_bitand;\n+ if left is 0 assign 0;\n+ if right is 0 assign 0;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\n+ both_known: u64_bitor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\n+ both_known: u64_bitxor;\n+ if left is 0 assign right;\n+ if right is 0 assign left;\n+ commutative: true;\n+ },\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\n+ both_known: u64::checked_shl;\n+ if right is 0 assign left;\n+ },\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\n+ both_known: u64::checked_shr;\n+ if right is 0 assign left;\n+ },\n+\n+ // Comparisons\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\n+ both_known: u64_eq;\n+ },\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\n+ both_known: u64_gt;\n+ },\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\n+ both_known: u64_lt;\n+ },\n+ _ => None,\n+ };\n+\n+ let after = format!(\"{op}\");\n+ if before != after {\n+ log(&format!(\" changed to: {op}\\n\"));\n+ }\n+\n+ let reset = match reset {\n+ None => {\n+ match &op.opcode {\n+ Either::Left(op) => match op {\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\n+ // TODO: this constraint can be relaxed\n+ _ if op.has_side_effect() => ResetKnown::All,\n _ => ResetKnown::Defs,\n },\n- // These ops mark their outputs properly and cause no control-flow effects\n- ControlFlowOp::Comment\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n- // This changes the stack pointer\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\n- // This can be considered to destroy all known values\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\n- },\n- };\n+ Either::Right(op) => match op {\n+ ControlFlowOp::Label(label) => {\n+ if jump_target_labels.contains_key(label) {\n+ ResetKnown::All\n+ } else {\n+ ResetKnown::Defs\n+ }\n+ }\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\n+ JumpType::Call => ResetKnown::All,\n+ _ => ResetKnown::Defs,\n+ },\n+ ControlFlowOp::Comment\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\n+ },\n+ }\n+ }\n+ Some(reset) => reset,\n+ };\n \n- reset.apply(op, &mut known_values);\n- }\n+ log(&format!(\" {reset:?}\\n\"));\n+ reset.apply(op, &mut known_values);\n }\n \n self\n }\n }\n+\n+#[inline(always)]\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitand(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\n+ Some(l.bitxor(r))\n+}\n+\n+#[inline(always)]\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\n+ Some(if l == r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l > r { 1 } else { 0 })\n+}\n+\n+#[inline(always)]\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\n+ Some(if l < r { 1 } else { 0 })\n+}\n+\n+// Copied from fuel_vm to guarantee exactly same behaviour.\n+// See fuel-vm/src/interpreter/executors/instruction.rs\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\n+ if nth_root == 0 {\n+ // Zeroth root is not defined\n+ return None;\n+ }\n+\n+ if nth_root == 1 || target <= 1 {\n+ // Corner cases\n+ return Some(target);\n+ }\n+\n+ if nth_root >= target || nth_root > 64 {\n+ // For any root >= target, result always 1\n+ // For any n>1, n**64 can never fit into u64\n+ return Some(1);\n+ }\n+\n+ let nth_root = u32::try_from(nth_root).expect(\"Never loses bits, checked above\");\n+\n+ // Use floating point operation to get an approximation for the starting point.\n+ // This is at most off by one in either direction.\n+\n+ let powf = f64::powf;\n+\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\n+\n+ debug_assert!(guess != 0, \"This should never occur for {{target, n}} > 1\");\n+\n+ // Check if a value raised to nth_power is below the target value, handling overflow\n+ // correctly\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\n+ Some(pow) => target < pow,\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\n+ };\n+\n+ // Compute guess**n to check if the guess is too large.\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\n+ // here.\n+ if is_nth_power_below_target(guess) {\n+ return Some(guess.saturating_sub(1));\n+ }\n+\n+ // Check if the initial guess was correct\n+ let guess_plus_one = guess\n+ .checked_add(1)\n+ .expect(\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\");\n+ if is_nth_power_below_target(guess_plus_one) {\n+ return Some(guess);\n+ }\n+\n+ // If not, then the value above must be the correct one.\n+ Some(guess_plus_one)\n+}\n+\n+#[cfg(test)]\n+mod tests {\n+ use super::*;\n+ use expect_test::expect;\n+\n+ fn optimise(\n+ ops: impl IntoIterator<Item = Op>,\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\n+ ) {\n+ let mut ops = AbstractInstructionSet {\n+ function: None,\n+ ops: ops.into_iter().collect(),\n+ };\n+\n+ for i in 0..ops.ops.len() {\n+ ops.ops[i].comment = i.to_string();\n+ }\n+\n+ f(ops);\n+ }\n+\n+ #[test]\n+ fn constant_propagate_transform() {\n+ let mut str = String::new();\n+ let capture = |s: &str| {\n+ str.push_str(s);\n+ };\n+ optimise(\n+ [\n+ VirtualOp::movi(\"0\", 10).into(),\n+ VirtualOp::movi(\"1\", 10).into(),\n+ VirtualOp::movi(\"2\", 2).into(),\n+ VirtualOp::movi(\"3\", 8).into(),\n+ VirtualOp::movi(\"4\", 9).into(),\n+ // movi\n+ VirtualOp::movi(\"0\", 10).into(),\n+ // mov\n+ VirtualOp::r#move(\"0\", \"1\").into(),\n+ //add\n+ VirtualOp::add(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg2, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::add(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ // add when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::add(\"11\", \"10\", ConstantRegister::One).into(),\n+ //sub\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ // sub when underflow\n+ VirtualOp::sub(\"11\", ConstantRegister::Zero, ConstantRegister::One).into(),\n+ //mul\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \"5\", \"0\").into(),\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \"0\", \"5\").into(),\n+ // mul when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::mul(\"11\", \"10\", \"10\").into(),\n+ // div\n+ VirtualOp::div(ConstantRegister::FuncArg0, \"0\", \"1\").into(),\n+ VirtualOp::div(ConstantRegister::FuncArg1, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \"0\").into(),\n+ // div with invalid args\n+ VirtualOp::div(\"11\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\n+ // exp\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::exp(\n+ ConstantRegister::FuncArg0,\n+ ConstantRegister::Zero,\n+ ConstantRegister::Zero,\n+ )\n+ .into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \"0\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \"0\", ConstantRegister::One).into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \"0\").into(),\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \"0\").into(),\n+ // exp when overflow\n+ VirtualOp::not(\"10\", ConstantRegister::Zero).into(),\n+ VirtualOp::exp(\"11\", \"10\", \"10\").into(),\n+ // mlog\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \"3\", \"2\").into(),\n+ // mlog with invalid args\n+ VirtualOp::mlog(\"11\", ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::Zero).into(),\n+ VirtualOp::mlog(\"11\", \"3\", ConstantRegister::One).into(),\n+ // mod\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mod with invalid args\n+ VirtualOp::r#mod(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ // mroo\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \"4\", \"2\").into(),\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \"4\", ConstantRegister::One).into(),\n+ // mroo with invalid args\n+ VirtualOp::mroo(\"11\", \"4\", ConstantRegister::Zero).into(),\n+ //and\n+ VirtualOp::and(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::and(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::and(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //or\n+ VirtualOp::or(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::or(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::or(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //xor\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \"2\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \"5\", \"0\").into(),\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \"0\", \"5\").into(),\n+ //sll\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //srl\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \"2\", ConstantRegister::Zero).into(),\n+ //eq\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //gt\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ //lt\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \"0\", \"2\").into(),\n+ // err register\n+ // we dot not want propagation in this case\n+ VirtualOp::r#move(\"0\", ConstantRegister::Error).into(),\n+ VirtualOp::eq(\"1\", \"0\", ConstantRegister::One).into(),\n+ ],\n+ |ops| ops.constant_propagate(capture),\n+ );\n+\n+ expect![[r#\"\n+ movi $r0 i10 ; 0\n+ Nothing\n+ movi $r1 i10 ; 1\n+ Nothing\n+ movi $r2 i2 ; 2\n+ Nothing\n+ movi $r3 i8 ; 3\n+ Nothing\n+ movi $r4 i9 ; 4\n+ Nothing\n+ movi $r0 i10 ; 5\n+ changed to: noop ; 5\n+ Nothing\n+ move $r0 $r1 ; 6\n+ changed to: noop ; 6\n+ Nothing\n+ add $$arg0 $r0 $r1 ; 7\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i20 ; 7\n+ Nothing\n+ add $$arg1 $zero $r0 ; 8\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 8\n+ Nothing\n+ add $$arg2 $r0 $zero ; 9\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg2 i10 ; 9\n+ Nothing\n+ add $$arg3 $r5 $r0 ; 10\n+ None Some(Const(10))\n+ changed to: addi $$arg3 $r5 i10 ; 10\n+ Defs\n+ add $$arg4 $r0 $r5 ; 11\n+ Some(Const(10)) None\n+ changed to: addi $$arg4 $r5 i10 ; 11\n+ Defs\n+ not $r10 $zero ; 12\n+ Some(Const(0))\n+ Nothing\n+ add $r11 $r10 $one ; 13\n+ Some(Const(18446744073709551615)) Some(Const(1))\n+ Defs\n+ sub $$arg0 $r0 $r1 ; 14\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i0 ; 14\n+ Nothing\n+ sub $$arg1 $r0 $zero ; 15\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i10 ; 15\n+ Nothing\n+ sub $r11 $zero $one ; 16\n+ Some(Const(0)) Some(Const(1))\n+ Defs\n+ mul $$arg0 $r0 $r1 ; 17\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i100 ; 17\n+ Nothing\n+ mul $$arg1 $one $r0 ; 18\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg1 i10 ; 18\n+ Nothing\n+ mul $$arg2 $r0 $one ; 19\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 19\n+ Nothing\n+ mul $$arg3 $zero $r0 ; 20\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 20\n+ Nothing\n+ mul $$arg4 $r0 $zero ; 21\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg4 i0 ; 21\n+ Nothing\n+ mul $$arg5 $r5 $r0 ; 22\n+ None Some(Const(10))\n+ changed to: muli $$arg5 $r5 i10 ; 22\n+ Defs\n+ mul $$arg0 $r0 $r5 ; 23\n+ Some(Const(10)) None\n+ changed to: muli $$arg0 $r5 i10 ; 23\n+ Defs\n+ not $r10 $zero ; 24\n+ Some(Const(0))\n+ Nothing\n+ mul $r11 $r10 $r10 ; 25\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ div $$arg0 $r0 $r1 ; 26\n+ Some(Const(10)) Some(Const(10))\n+ changed to: movi $$arg0 i1 ; 26\n+ Nothing\n+ div $$arg1 $r0 $one ; 27\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg1 i10 ; 27\n+ Nothing\n+ div $$arg2 $zero $r0 ; 28\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg2 i0 ; 28\n+ Nothing\n+ div $r11 $zero $zero ; 29\n+ Some(Const(0)) Some(Const(0))\n+ Defs\n+ exp $$arg0 $r0 $r2 ; 30\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i100 ; 30\n+ Nothing\n+ exp $$arg0 $zero $zero ; 31\n+ Some(Const(0)) Some(Const(0))\n+ changed to: movi $$arg0 i1 ; 31\n+ Nothing\n+ exp $$arg1 $r0 $zero ; 32\n+ Some(Const(10)) Some(Const(0))\n+ changed to: movi $$arg1 i1 ; 32\n+ Nothing\n+ exp $$arg2 $r0 $one ; 33\n+ Some(Const(10)) Some(Const(1))\n+ changed to: movi $$arg2 i10 ; 33\n+ Nothing\n+ exp $$arg3 $zero $r0 ; 34\n+ Some(Const(0)) Some(Const(10))\n+ changed to: movi $$arg3 i0 ; 34\n+ Nothing\n+ exp $$arg4 $one $r0 ; 35\n+ Some(Const(1)) Some(Const(10))\n+ changed to: movi $$arg4 i1 ; 35\n+ Nothing\n+ not $r10 $zero ; 36\n+ Some(Const(0))\n+ Nothing\n+ exp $r11 $r10 $r10 ; 37\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\n+ Defs\n+ mlog $$arg0 $r3 $r2 ; 38\n+ Some(Const(8)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 38\n+ Nothing\n+ mlog $r11 $zero $r2 ; 39\n+ Some(Const(0)) Some(Const(2))\n+ Defs\n+ mlog $r11 $r3 $zero ; 40\n+ Some(Const(8)) Some(Const(0))\n+ Defs\n+ mlog $r11 $r3 $one ; 41\n+ Some(Const(8)) Some(Const(1))\n+ Defs\n+ mod $$arg0 $r4 $r2 ; 42\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 42\n+ Nothing\n+ mod $$arg1 $r4 $one ; 43\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i0 ; 43\n+ Nothing\n+ mod $r11 $r4 $zero ; 44\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ mroo $$arg0 $r4 $r2 ; 45\n+ Some(Const(9)) Some(Const(2))\n+ changed to: movi $$arg0 i3 ; 45\n+ Nothing\n+ mroo $$arg1 $r4 $one ; 46\n+ Some(Const(9)) Some(Const(1))\n+ changed to: movi $$arg1 i9 ; 46\n+ Nothing\n+ mroo $r11 $r4 $zero ; 47\n+ Some(Const(9)) Some(Const(0))\n+ Defs\n+ and $$arg0 $r0 $r2 ; 48\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 48\n+ Nothing\n+ and $$arg1 $zero $r2 ; 49\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i0 ; 49\n+ Nothing\n+ and $$arg2 $r2 $zero ; 50\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i0 ; 50\n+ Nothing\n+ and $$arg3 $r5 $r0 ; 51\n+ None Some(Const(10))\n+ changed to: andi $$arg3 $r5 i10 ; 51\n+ Defs\n+ and $$arg4 $r0 $r5 ; 52\n+ Some(Const(10)) None\n+ changed to: andi $$arg4 $r5 i10 ; 52\n+ Defs\n+ or $$arg0 $r0 $r2 ; 53\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i10 ; 53\n+ Nothing\n+ or $$arg1 $zero $r2 ; 54\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 54\n+ Nothing\n+ or $$arg2 $r2 $zero ; 55\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 55\n+ Nothing\n+ or $$arg3 $r5 $r0 ; 56\n+ None Some(Const(10))\n+ changed to: ori $$arg3 $r5 i10 ; 56\n+ Defs\n+ or $$arg4 $r0 $r5 ; 57\n+ Some(Const(10)) None\n+ changed to: ori $$arg4 $r5 i10 ; 57\n+ Defs\n+ xor $$arg0 $r0 $r2 ; 58\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i8 ; 58\n+ Nothing\n+ xor $$arg1 $zero $r2 ; 59\n+ Some(Const(0)) Some(Const(2))\n+ changed to: movi $$arg1 i2 ; 59\n+ Nothing\n+ xor $$arg2 $r2 $zero ; 60\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 60\n+ Nothing\n+ xor $$arg3 $r5 $r0 ; 61\n+ None Some(Const(10))\n+ changed to: xori $$arg3 $r5 i10 ; 61\n+ Defs\n+ xor $$arg4 $r0 $r5 ; 62\n+ Some(Const(10)) None\n+ changed to: xori $$arg4 $r5 i10 ; 62\n+ Defs\n+ sll $$arg0 $r0 $r2 ; 63\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i40 ; 63\n+ Nothing\n+ sll $$arg2 $r2 $zero ; 64\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 64\n+ Nothing\n+ srl $$arg0 $r0 $r2 ; 65\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i2 ; 65\n+ Nothing\n+ srl $$arg2 $r2 $zero ; 66\n+ Some(Const(2)) Some(Const(0))\n+ changed to: movi $$arg2 i2 ; 66\n+ Nothing\n+ eq $$arg0 $r0 $r2 ; 67\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 67\n+ Nothing\n+ gt $$arg0 $r0 $r2 ; 68\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i1 ; 68\n+ Nothing\n+ lt $$arg0 $r0 $r2 ; 69\n+ Some(Const(10)) Some(Const(2))\n+ changed to: movi $$arg0 i0 ; 69\n+ Nothing\n+ move $r0 $err ; 70\n+ Nothing\n+ eq $r1 $r0 $one ; 71\n+ None Some(Const(1))\n+ Defs\n+ \"#]]\n+ .assert_eq(&str);\n+ }\n+}\n"},{"comment":"Nit.\n```suggestion\n /// Examples: Error, Overflow, Flags, etc.\n```","path":"sway-core/src/asm_lang/mod.rs","hunk":"@@ -700,20 +710,24 @@ impl Op {\n }\n \n /// Returns a list of all registers *read* by instruction `self`.\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\n match &mut self.opcode {\n Either::Left(virt_op) => virt_op.use_registers_mut(),\n Either::Right(org_op) => org_op.use_registers_mut(),\n }\n }\n \n+ /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\n+ /// exactly 0 or 1 register, so the size of this returned vector should always be at most 1.\n pub(crate) fn def_registers(&self) -> BTreeSet<&VirtualRegister> {\n match &self.opcode {\n Either::Left(virt_op) => virt_op.def_registers(),\n Either::Right(org_op) => org_op.def_registers(),\n }\n }\n \n+ /// What are the special registers that an OP may set.\n+ /// Examples: Error, Overflow, Flags etc...","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_lang/mod.rs b/sway-core/src/asm_lang/mod.rs\nindex 805470d600f..cc302e5fe37 100644\n--- a/sway-core/src/asm_lang/mod.rs\n+++ b/sway-core/src/asm_lang/mod.rs\n@@ -94,6 +94,16 @@ pub(crate) struct Op {\n pub(crate) owning_span: Option<Span>,\n }\n \n+impl From<VirtualOp> for Op {\n+ fn from(opcode: VirtualOp) -> Self {\n+ Op {\n+ opcode: Either::Left(opcode),\n+ comment: String::new(),\n+ owning_span: None,\n+ }\n+ }\n+}\n+\n #[derive(Clone, Debug)]\n pub(crate) struct AllocatedAbstractOp {\n pub(crate) opcode: Either<AllocatedInstruction, ControlFlowOp<AllocatedRegister>>,\n@@ -700,13 +710,15 @@ impl Op {\n }\n \n /// Returns a list of all registers *read* by instruction `self`.\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\n match &mut self.opcode {\n Either::Left(virt_op) => virt_op.use_registers_mut(),\n Either::Right(org_op) => org_op.use_registers_mut(),\n }\n }\n \n+ /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\n+ /// exactly 0 or 1 register, so the size of this returned vector should always be at most 1.\n pub(crate) fn def_registers(&self) -> BTreeSet<&VirtualRegister> {\n match &self.opcode {\n Either::Left(virt_op) => virt_op.def_registers(),\n@@ -714,6 +726,8 @@ impl Op {\n }\n }\n \n+ /// What are the special registers that an OP may set.\n+ /// Examples: Error, Overflow, Flags, etc.\n pub(crate) fn def_const_registers(&self) -> BTreeSet<&VirtualRegister> {\n match &self.opcode {\n Either::Left(virt_op) => virt_op.def_const_registers(),\n@@ -1144,7 +1158,7 @@ impl fmt::Display for VirtualOp {\n MROO(a, b, c) => write!(fmtr, \"mroo {a} {b} {c}\"),\n MUL(a, b, c) => write!(fmtr, \"mul {a} {b} {c}\"),\n MULI(a, b, c) => write!(fmtr, \"muli {a} {b} {c}\"),\n- NOOP => Ok(()),\n+ NOOP => write!(fmtr, \"noop\"),\n NOT(a, b) => write!(fmtr, \"not {a} {b}\"),\n OR(a, b, c) => write!(fmtr, \"or {a} {b} {c}\"),\n ORI(a, b, c) => write!(fmtr, \"ori {a} {b} {c}\"),\n@@ -1359,9 +1373,10 @@ impl<Reg: Clone + Eq + Ord + Hash> ControlFlowOp<Reg> {\n }\n \n /// Returns a list of all registers *read* by instruction `self`.\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut Reg> {\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut Reg> {\n use ControlFlowOp::*;\n- (match self {\n+\n+ match self {\n Label(_)\n | Comment\n | DataSectionOffsetPlaceholder\n@@ -1375,9 +1390,7 @@ impl<Reg: Clone + Eq + Ord + Hash> ControlFlowOp<Reg> {\n },\n JumpToAddr(r0) => vec![r0],\n ReturnFromCall { zero, reta } => vec![zero, reta],\n- })\n- .into_iter()\n- .collect()\n+ }\n }\n \n pub(crate) fn def_registers(&self) -> BTreeSet<&Reg> {\n"},{"comment":"```suggestion\n pub fn movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {\n```","path":"sway-core/src/asm_lang/virtual_ops.rs","hunk":"@@ -249,6 +249,142 @@ pub(crate) enum VirtualOp {\n }\n \n impl VirtualOp {\n+ pub fn r#move(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\n+ VirtualOp::MOVE(a.into(), b.into())\n+ }\n+\n+ pub fn r#movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_lang/virtual_ops.rs b/sway-core/src/asm_lang/virtual_ops.rs\nindex 57ac24ff488..f5a6a2dba6d 100644\n--- a/sway-core/src/asm_lang/virtual_ops.rs\n+++ b/sway-core/src/asm_lang/virtual_ops.rs\n@@ -249,6 +249,146 @@ pub(crate) enum VirtualOp {\n }\n \n impl VirtualOp {\n+ pub fn r#move(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\n+ VirtualOp::MOVE(a.into(), b.into())\n+ }\n+\n+ pub fn movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {\n+ VirtualOp::MOVI(a.into(), b.into())\n+ }\n+\n+ pub fn add(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::ADD(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn sub(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::SUB(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn mul(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MUL(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn div(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::DIV(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn exp(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::EXP(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn mlog(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MLOG(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn r#mod(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MOD(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn mroo(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MROO(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn not(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\n+ VirtualOp::NOT(a.into(), b.into())\n+ }\n+\n+ pub fn and(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::AND(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn or(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::OR(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn xor(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::XOR(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn sll(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::SLL(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn srl(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::SRL(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn eq(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::EQ(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn gt(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::GT(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn lt(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::LT(a.into(), b.into(), c.into())\n+ }\n+\n pub(crate) fn registers(&self) -> BTreeSet<&VirtualRegister> {\n use VirtualOp::*;\n (match self {\n@@ -480,7 +620,8 @@ impl VirtualOp {\n }\n }\n \n- // What are the special registers that an OP may set.\n+ /// What are the special registers that an OP may set.\n+ /// Examples: Error, Overflow, Flags, etc.\n pub(crate) fn def_const_registers(&self) -> BTreeSet<&VirtualRegister> {\n use ConstantRegister::*;\n use VirtualOp::*;\n@@ -712,9 +853,9 @@ impl VirtualOp {\n }\n \n /// Returns a list of all registers *read* by instruction `self`.\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\n use VirtualOp::*;\n- (match self {\n+ match self {\n /* Arithmetic/Logic (ALU) Instructions */\n ADD(_r1, r2, r3) => vec![r2, r3],\n ADDI(_r1, r2, _i) => vec![r2],\n@@ -828,9 +969,7 @@ impl VirtualOp {\n AddrDataId(_r1, _i) => vec![],\n \n Undefined => vec![],\n- })\n- .into_iter()\n- .collect()\n+ }\n }\n \n /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\n"},{"comment":"```suggestion\n /// Examples: Error, Overflow, Flags, etc.\n```","path":"sway-core/src/asm_lang/virtual_ops.rs","hunk":"@@ -480,7 +616,8 @@ impl VirtualOp {\n }\n }\n \n- // What are the special registers that an OP may set.\n+ /// What are the special registers that an OP may set.\n+ /// Examples: Error, Overflow, Flags etc...","resolving_sha":"2765f4af57abc203a826d5890c77e4593c6095ff","resolving_diff":"diff --git a/sway-core/src/asm_lang/virtual_ops.rs b/sway-core/src/asm_lang/virtual_ops.rs\nindex 57ac24ff488..f5a6a2dba6d 100644\n--- a/sway-core/src/asm_lang/virtual_ops.rs\n+++ b/sway-core/src/asm_lang/virtual_ops.rs\n@@ -249,6 +249,146 @@ pub(crate) enum VirtualOp {\n }\n \n impl VirtualOp {\n+ pub fn r#move(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\n+ VirtualOp::MOVE(a.into(), b.into())\n+ }\n+\n+ pub fn movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {\n+ VirtualOp::MOVI(a.into(), b.into())\n+ }\n+\n+ pub fn add(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::ADD(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn sub(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::SUB(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn mul(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MUL(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn div(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::DIV(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn exp(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::EXP(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn mlog(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MLOG(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn r#mod(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MOD(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn mroo(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::MROO(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn not(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\n+ VirtualOp::NOT(a.into(), b.into())\n+ }\n+\n+ pub fn and(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::AND(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn or(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::OR(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn xor(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::XOR(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn sll(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::SLL(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn srl(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::SRL(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn eq(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::EQ(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn gt(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::GT(a.into(), b.into(), c.into())\n+ }\n+\n+ pub fn lt(\n+ a: impl Into<VirtualRegister>,\n+ b: impl Into<VirtualRegister>,\n+ c: impl Into<VirtualRegister>,\n+ ) -> VirtualOp {\n+ VirtualOp::LT(a.into(), b.into(), c.into())\n+ }\n+\n pub(crate) fn registers(&self) -> BTreeSet<&VirtualRegister> {\n use VirtualOp::*;\n (match self {\n@@ -480,7 +620,8 @@ impl VirtualOp {\n }\n }\n \n- // What are the special registers that an OP may set.\n+ /// What are the special registers that an OP may set.\n+ /// Examples: Error, Overflow, Flags, etc.\n pub(crate) fn def_const_registers(&self) -> BTreeSet<&VirtualRegister> {\n use ConstantRegister::*;\n use VirtualOp::*;\n@@ -712,9 +853,9 @@ impl VirtualOp {\n }\n \n /// Returns a list of all registers *read* by instruction `self`.\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\n use VirtualOp::*;\n- (match self {\n+ match self {\n /* Arithmetic/Logic (ALU) Instructions */\n ADD(_r1, r2, r3) => vec![r2, r3],\n ADDI(_r1, r2, _i) => vec![r2],\n@@ -828,9 +969,7 @@ impl VirtualOp {\n AddrDataId(_r1, _i) => vec![],\n \n Undefined => vec![],\n- })\n- .into_iter()\n- .collect()\n+ }\n }\n \n /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\n"}],"string":"[\n {\n \"comment\": \"### EXP optimization incorrectly folds `0^x` to zero\\n\\n**High Severity**\\n\\n<!-- DESCRIPTION START -->\\nThe rule `if left is 0 assigns 0` for `EXP` assumes `0^x = 0` for all `x`, but `0^0 = 1`. When the left operand is known to be 0 and the right operand is unknown at compile time, the optimizer replaces the `EXP` instruction with `MOVI dst 0`. At runtime, if the exponent happens to be 0, the correct result is 1 (matching `u64::checked_pow(0, 0) = Some(1)` and FuelVM behavior), but the optimized code produces 0.\\n<!-- DESCRIPTION END -->\\n\\n<!-- BUGBOT_BUG_ID: fc0797c3-212e-46a6-bfae-2a8b102bd0aa -->\\n\\n<!-- LOCATIONS START\\nsway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs#L367-L368\\nLOCATIONS END -->\\n<p><a href=\\\"https://cursor.com/open?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9DVVJTT1IiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90OmEyMDM1MzZmLWU0NWMtNDYxNy04N2U2LTg2MGI3Mzk4NmFiZSIsImVuY3J5cHRpb25LZXkiOiI2VC1oazdQMzFTbG5JUFhmb1BSaHVtOVpsU3VMcVRoanRzclBsMlQyblVNIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSJ9LCJpYXQiOjE3NzE0MjA1MzgsImV4cCI6MTc3NDAxMjUzOH0.TO4MvppVhMVTug_5jbNEQcHmOlab0WiKBvc4gteDvc0HGQkKyVo7M7jxOR8XSJ5XH_zaGmXOHhm2uT643MLHTs1Rh_EI9ipsQd5DiAq5fz3VBNAZ3xUoMCmKFcrWEvKRTlT6blHg9dz8XE6cIEWgX-SydyDKY50VbdOm0UVikontVCf1iLc_c9blSTd7XBW-YE5bgYAcIPykAItRodkkRgoAnH0IdpKjoyCaKwgCoEkN-OZDJClW_6X-28A32QaDtCLGxAkrrGQQs4B816krDu0CHJcWEqQLfNHHcd9ATgXAMKpGRFPEexgZ7b-fDyntASNRvLlOHSr9KUaAk52FRw\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-light.png\\\"><img alt=\\\"Fix in Cursor\\\" width=\\\"115\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"></picture></a> <a href=\\\"https://cursor.com/agents?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9XRUIiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90OmEyMDM1MzZmLWU0NWMtNDYxNy04N2U2LTg2MGI3Mzk4NmFiZSIsImVuY3J5cHRpb25LZXkiOiI2VC1oazdQMzFTbG5JUFhmb1BSaHVtOVpsU3VMcVRoanRzclBsMlQyblVNIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSIsInByTnVtYmVyIjo3NTUwLCJjb21taXRTaGEiOiIxMjZmMWNlZDExZmM2NTgxY2ZjYjM5OTM4ODZlZmE3YTllZmQxNDM5IiwicHJvdmlkZXIiOiJnaXRodWIifSwiaWF0IjoxNzcxNDIwNTM4LCJleHAiOjE3NzQwMTI1Mzh9.y0GY0rJMfO4ZX2BGYjcYQrSmK67ab2QrLWL-oU2_gErb7GNcetYEqEYELyA2gYEEkz6qMKMN1BGp2QTVPzR-DPgU06V4dB0a2YkmGPrKOhF4YAcCJTn5-8-Gv5NoRNiRW5OGBopwWRNf-RUxWTaxwgAcbq3zpwrx2nht5WrM7t9nTx81lA1Bm6ABLWDPjv7XartcHyDzDN8JIuz1M6AQx_zrxhQ8LaF1sV55pxYLDlTbTaDQs9mmF0ZWGCkr7IB6HiR3nIiZf1HS5RnbuYAIf5seRMYN3c-5nZXKEkolC0Ga-D7j79tfIvJB0J4xOT64KIFK3_64qwjUgOQXCEeH2A\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-light.png\\\"><img alt=\\\"Fix in Web\\\" width=\\\"99\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"></picture></a></p>\\n\\n\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -165,73 +192,694 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if they registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n+\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assigns right;\\n+ if right is 0 assigns left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assigns left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assigns right;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ if right is 0 assigns 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assigns 1;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"### DIV optimization suppresses panic on division by zero\\n\\n**Medium Severity**\\n\\n<!-- DESCRIPTION START -->\\nThe `DIV` rule `if left is 0 assigns 0` replaces `DIV(dst, 0, x)` with `MOVI(dst, 0)` when the dividend is known to be zero but the divisor is unknown. FuelVM defines division by zero as a panic condition. If `x` is 0 at runtime, the original code would panic/revert, but the optimized code silently produces 0 and continues execution, changing observable program behavior.\\n<!-- DESCRIPTION END -->\\n\\n<!-- BUGBOT_BUG_ID: 76c0a1fb-5fc6-490e-a373-89ee11cd63af -->\\n\\n<!-- LOCATIONS START\\nsway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs#L361-L362\\nLOCATIONS END -->\\n<p><a href=\\\"https://cursor.com/open?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9DVVJTT1IiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90OmQwN2JlYWZjLTJkNDEtNDE1Zi1iYWE2LWViNTY2MGY5MDJjNSIsImVuY3J5cHRpb25LZXkiOiJfSmprVklSTTA0Vnc0YmdtLU9IaTVQRzlwd2wxaG1xVU1nT3R4YXhrdjRRIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSJ9LCJpYXQiOjE3NzE0MjIxMTMsImV4cCI6MTc3NDAxNDExM30.U4RktfXaYNCCdvsci6wUNV6YcoFrvwRddEEc-GM45lpeu1za3b0BwM2vi6Xt39ZOaW69QHOjYPzRxnmvZ_53xmcOqypu03g7nvcF2m9C3HiZ7GIlANPfUWyz8jW9oMlUaEr0NAUBa2HCjIzfucJy_xziNCePxPz8D4OyCtdGnGYVJeDMnr4uDdhGLSSF_60I_No7-AHs8JN12zFWB9aQzDbCFgRaZpEKrs9BLCkvGBh6VOLElskc5khejsfdT9wqceRiOJFWLVR3zpKvGUrXhVKc7MidDCTLpMnp0ERO_oIkpQkm7gAjSSuwGr3UjpXzRXGOKwT2rpy6tNWhU2KE7Q\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-light.png\\\"><img alt=\\\"Fix in Cursor\\\" width=\\\"115\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"></picture></a> <a href=\\\"https://cursor.com/agents?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9XRUIiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90OmQwN2JlYWZjLTJkNDEtNDE1Zi1iYWE2LWViNTY2MGY5MDJjNSIsImVuY3J5cHRpb25LZXkiOiJfSmprVklSTTA0Vnc0YmdtLU9IaTVQRzlwd2wxaG1xVU1nT3R4YXhrdjRRIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSIsInByTnVtYmVyIjo3NTUwLCJjb21taXRTaGEiOiI5MTg2MWQxNGNiOGJiZThkMWE5MWY1ZjgyOWJiZGFjYmUzNmZmNmM2IiwicHJvdmlkZXIiOiJnaXRodWIifSwiaWF0IjoxNzcxNDIyMTEzLCJleHAiOjE3NzQwMTQxMTN9.PicbRyo7i-fcrUHx9Bw6CS-ssy1fHgJ2jUAfIdvloR5N04Pyi248vERmPagDUlL7f8KDPwV1shXjFf8xhtTrF2lfuJuL_cHydNAnMBqX1tNVbLIKkQlRi38Zw8ViX4TcakieYwmPVockhB0OKd1eroDwzsIIoByRHU3ynMX30sGmGi8zE4xE_pHWuckRejyCRl8PBi9PiHOusQbiEAN4zDwzk_i11UpjPHhNQp0SpePqAVm_nbIknZGxg2om6YQmatt7FRj7BLy_nK4NSrij7il4OI-QEao6UXj_6UALL-J6O9gB924gwbQJDVFBchpP8KYkMHKflexbE_R5Vlfd9A\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-light.png\\\"><img alt=\\\"Fix in Web\\\" width=\\\"99\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"></picture></a></p>\\n\\n\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -165,73 +192,694 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if they registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n+\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assigns right;\\n+ if right is 0 assigns left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assigns left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assigns right;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ if right is 0 assigns 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"### `both_known` bail skips applicable identity and commutative rules\\n\\n**Medium Severity**\\n\\n<!-- DESCRIPTION START -->\\nWhen both operands are known constants, the `both_known` macro arm enters its `if let` block. If the computed result doesn't fit in an 18-bit immediate, the `?` operator on `VirtualImmediate18::try_new` returns `None` from the *entire closure*, skipping all subsequent identity rules, commutative transformations, and `replace_imm` conversions that would have been valid. For example, `ADD dst const(0) const(large)` could be simplified to `MOVE dst large_reg` via the `if left is 0` rule, but the `both_known` bail prevents this.\\n<!-- DESCRIPTION END -->\\n\\n<!-- BUGBOT_BUG_ID: 16476081-1866-42ad-a13b-74fa4b1519fe -->\\n\\n<!-- LOCATIONS START\\nsway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs#L240-L249\\nLOCATIONS END -->\\n<p><a href=\\\"https://cursor.com/open?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9DVVJTT1IiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90Ojc4YTdhNDdiLWRmYTAtNGYwYS1hY2Q0LTg5YWQwNjNjZWVkZCIsImVuY3J5cHRpb25LZXkiOiIyMmhZa2RYTmlscVJnUTdibXFFSWR1NHAyUXhRNE1DYmtVT2FaNGpKajRFIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSJ9LCJpYXQiOjE3NzE0MjczNDEsImV4cCI6MTc3NDAxOTM0MX0.bpZXxgxbyaxmo4FQmAtIcFC-Wn0akd6I_XVQ1ccGEAbGF9wEuUuo_B8Y2aZ3AhFztLK-ch9ywO61MiwFKd7Z4N3mr6eAlKYDo-xSzT0v6mVLshVeSEyCPd0B1gUk5iin1-2DN_eKrWrHjOYRa2_hPJxAizbaXI3RTxg5y-fRL-tZDdjWmnP20ypVmME8cCw6zKCS81rRvqk24I0XziY437CX8uX_Xo1LZSmVUwPc_HQIDxCEdqMhMircq4AmB-1AVIplguw3yjqVidyOIySp-vb1NL-Hp6Nd-Wm3goscVCDsG1HOxULdZRLJkQmfqVXRWTM-L57YHW3BMK_B3_Shgw\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-light.png\\\"><img alt=\\\"Fix in Cursor\\\" width=\\\"115\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"></picture></a> <a href=\\\"https://cursor.com/agents?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9XRUIiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90Ojc4YTdhNDdiLWRmYTAtNGYwYS1hY2Q0LTg5YWQwNjNjZWVkZCIsImVuY3J5cHRpb25LZXkiOiIyMmhZa2RYTmlscVJnUTdibXFFSWR1NHAyUXhRNE1DYmtVT2FaNGpKajRFIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSIsInByTnVtYmVyIjo3NTUwLCJjb21taXRTaGEiOiJmODFmMDc3ZDJjOTUzYWFlMTc0OGQxNzljM2IwMzE3YTNhOGJlYTU0IiwicHJvdmlkZXIiOiJnaXRodWIifSwiaWF0IjoxNzcxNDI3MzQxLCJleHAiOjE3NzQwMTkzNDF9.kMFaBQC0j7FnRGg3fMPSKY34n0icFKwEU1WweF8wX_kATq_HFf-H4yja28n_HoaXin4NPw1c8N8Cxo6vVe-rZGBzQFWJwWT_UcqZNcxq7K7L83JDXdNS-EuvgDTph0cyOhIjQR8CYyophyeAcsssmrgjErvqkBI7xI0xyvEyjlci0x2cbTxTyt5EicYi-HyTRiXFxUNivu6ZF5_KT36bCVW9VrFtETw_5BvJi0nrOpkdQmotPH_law44tdxpBOjRG9AhsXS2a3zfW4nTrc2NiGxfNTqk6xNcAq71LXGQE69dXEQ-2BNRmhZp10TX_dGEnswskcryBa4IxAgomxf93A\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-light.png\\\"><img alt=\\\"Fix in Web\\\" width=\\\"99\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"></picture></a></p>\\n\\n\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -165,73 +192,695 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"### Panicking `From<u64>` for `VirtualImmediate18` is unsound\\n\\n**Medium Severity**\\n\\n<!-- DESCRIPTION START -->\\nThe `From<u64>` implementation for `VirtualImmediate18` calls `new()`, which panics if the value exceeds 18 bits. The `From` trait contract implies infallible conversion. A `TryFrom` implementation (like the one for `VirtualImmediate12`) would be appropriate here instead, preventing unexpected panics if this conversion is ever used outside test helpers.\\n<!-- DESCRIPTION END -->\\n\\n<!-- BUGBOT_BUG_ID: 4f2f2f40-9fc0-4bc4-a2d5-70e9b2e524cd -->\\n\\n<!-- LOCATIONS START\\nsway-core/src/asm_lang/virtual_immediate.rs#L136-L141\\nLOCATIONS END -->\\n<p><a href=\\\"https://cursor.com/open?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9DVVJTT1IiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90OjRhN2IxNWU2LTJhMTYtNDQzOC04MGIxLThjZTBlMzhhYzYxNiIsImVuY3J5cHRpb25LZXkiOiJ1bnNRVUpYVWhnRmIzU2lsRDYtOEFuVzdEcmpqc1U2bF9TWWRJbVVBTFFBIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSJ9LCJpYXQiOjE3NzI4MTc5MjQsImV4cCI6MTc3NTQwOTkyNH0.Xp-uyHdIjC-Zp-JEmu-tGegKCbEUdwLfqlWHBlAxQqc60gtDfAK5mymvUud2mo-chr2iYj84rmzBu4feaK1BEn9kddfntnZACNu2JF_vRIanwUWLz0LETWiqcHZm928kwvGPRX_57ZNrQHiYXY20iS4Ts81pJjr3XY8ls61-cOHfencLoY1wg9DDh-y1DyxJOn1BOZ3M0atyB6etCPpIjIH1Jt15FSCPPPkk_U0RVLeToFLAuGO09ml1mKHyUBK4N9WkL_GowWraf8MXcVlM3eVgMRngONYIbSZwGh2JFQbHtU5VX4raXqH5KsIxKA7kSDp9vQa2WPTEw9aZz4tBXQ\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-cursor-light.png\\\"><img alt=\\\"Fix in Cursor\\\" width=\\\"115\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-cursor-dark.png\\\"></picture></a> <a href=\\\"https://cursor.com/agents?data=eyJhbGciOiJSUzI1NiIsInR5cCI6IkpXVCIsImtpZCI6ImJ1Z2JvdC12MiJ9.eyJ2ZXJzaW9uIjoxLCJ0eXBlIjoiQlVHQk9UX0ZJWF9JTl9XRUIiLCJkYXRhIjp7InJlZGlzS2V5IjoiYnVnYm90OjRhN2IxNWU2LTJhMTYtNDQzOC04MGIxLThjZTBlMzhhYzYxNiIsImVuY3J5cHRpb25LZXkiOiJ1bnNRVUpYVWhnRmIzU2lsRDYtOEFuVzdEcmpqc1U2bF9TWWRJbVVBTFFBIiwiYnJhbmNoIjoieHVuaWxyai9hc20tY29uc3QtcHJvcC1pbXByb3YiLCJyZXBvT3duZXIiOiJGdWVsTGFicyIsInJlcG9OYW1lIjoic3dheSIsInByTnVtYmVyIjo3NTUwLCJjb21taXRTaGEiOiJmNmYwMzUxNGNkYjNlZWQ2OWQ1NGY3YWE2MTJmYzIyYTJjM2Q2MDI0IiwicHJvdmlkZXIiOiJnaXRodWIifSwiaWF0IjoxNzcyODE3OTI0LCJleHAiOjE3NzU0MDk5MjR9.vIacepRoXJgdDgSyujr98_-9a5hYTwPHz6GkrFSnuzPmG2kG6eCybZW-8hOhFjGdR4MBg5CdS9lgnd9DH7Q_FyO8Yym1nBVxb0rYkTkxSsYST-gLZp3ezR-BaDbl2zZoAwdvZWKtJlZzcxfELKfUWt1DsWgm35FZ_-iXS6kmLOoMVH4wMzx4YhK8JZtpTH3xuAf09TGiyLZgrO0FsgaQpHn60NvLB35ZnlawaDQC8AaRtZ-qeI5ajjqbN3P_WrS_qvq4jTQJBE2FH8iWyluGoJcf-g6l--dmnsrkX8Tv5K_BoUmoIENxEduZ87rwg9jNabpnkRNJq2-hwbsp7WojCQ\\\" target=\\\"_blank\\\" rel=\\\"noopener noreferrer\\\"><picture><source media=\\\"(prefers-color-scheme: dark)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"><source media=\\\"(prefers-color-scheme: light)\\\" srcset=\\\"https://cursor.com/assets/images/fix-in-web-light.png\\\"><img alt=\\\"Fix in Web\\\" width=\\\"99\\\" height=\\\"28\\\" src=\\\"https://cursor.com/assets/images/fix-in-web-dark.png\\\"></picture></a></p>\\n\\n\",\n \"path\": \"sway-core/src/asm_lang/virtual_immediate.rs\",\n \"hunk\": \"@@ -120,11 +120,26 @@ impl fmt::Display for VirtualImmediate12 {\\n }\\n }\\n \\n+impl TryInto<VirtualImmediate12> for u64 {\\n+ type Error = CompileError;\\n+\\n+ fn try_into(self) -> Result<VirtualImmediate12, Self::Error> {\\n+ VirtualImmediate12::try_new(self, Span::dummy())\\n+ }\\n+}\\n+\\n /// 18-bits immediate value type\\n #[derive(Clone, Debug)]\\n pub struct VirtualImmediate18 {\\n value: u32,\\n }\\n+\\n+impl From<u64> for VirtualImmediate18 {\\n+ fn from(value: u64) -> Self {\\n+ VirtualImmediate18::new(value)\\n+ }\\n+}\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_lang/virtual_immediate.rs b/sway-core/src/asm_lang/virtual_immediate.rs\\nindex 8881fff9544..1844a0a94cb 100644\\n--- a/sway-core/src/asm_lang/virtual_immediate.rs\\n+++ b/sway-core/src/asm_lang/virtual_immediate.rs\\n@@ -120,11 +120,26 @@ impl fmt::Display for VirtualImmediate12 {\\n }\\n }\\n \\n+impl TryInto<VirtualImmediate12> for u64 {\\n+ type Error = CompileError;\\n+\\n+ fn try_into(self) -> Result<VirtualImmediate12, Self::Error> {\\n+ VirtualImmediate12::try_new(self, Span::dummy())\\n+ }\\n+}\\n+\\n /// 18-bits immediate value type\\n #[derive(Clone, Debug)]\\n pub struct VirtualImmediate18 {\\n value: u32,\\n }\\n+\\n+impl From<u8> for VirtualImmediate18 {\\n+ fn from(value: u8) -> Self {\\n+ VirtualImmediate18::new(value as u64)\\n+ }\\n+}\\n+\\n impl VirtualImmediate18 {\\n pub(crate) fn try_new(raw: u64, err_msg_span: Span) -> Result<Self, CompileError> {\\n if raw > compiler_constants::EIGHTEEN_BITS {\\n\"\n },\n {\n \"comment\": \"For me being a first time reader of this code, the original comment wasn't informative enough. Proposal is to expand on it a bit. \\n```suggestion\\n /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -62,7 +69,18 @@ impl KnownValues {\\n \\n /// Clear values that depend on a register having a specific value.\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"On first reading `clear` sounded like we are not _removing_ the values but rather setting them on some \\\"cleared\\\" value. IMO using _remove_ here will be much clearer.\\n```suggestion\\n fn remove_dependent_on(&mut self, reg: &VirtualRegister) {\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -62,7 +69,18 @@ impl KnownValues {\\n \\n /// Clear values that depend on a register having a specific value.\\n fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"In other parts of the compiler we name this kind of a list a `worklist`. Proposal is to use the same name here.\\n```suggestion\\n let mut worklist = vec![reg.clone()];\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -62,7 +69,18 @@ impl KnownValues {\\n \\n /// Clear values that depend on a register having a specific value.\\n fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ let mut q = vec![reg.clone()];\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"`extend` accepts an iterator so we don't need to `collect` here. Also, the `extract_if` will be fully iterated in `extend` and the elements removed.\\n```suggestion\\n .map(|(k, _)| k);\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -62,7 +69,18 @@ impl KnownValues {\\n \\n /// Clear values that depend on a register having a specific value.\\n fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ let mut q = vec![reg.clone()];\\n+\\n+ while let Some(reg) = q.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k)\\n+ .collect::<Vec<_>>();\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Nitpick. Proposing as IMO better sounding enum variant name that align with \\\"Reset what?\\\".\\n```suggestion\\n All,\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -75,25 +93,31 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ Full,\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Is this needed? `clear_dependent_on` also always removes the `reg` passed as an argument. So the above call to `clear_dependent_on` will also remove the `Overflow`.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -75,25 +93,31 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ Full,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values.clear_dependent_on(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values\\n+ .values\\n+ .remove(&VirtualRegister::Constant(ConstantRegister::Overflow));\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Same here for `Error`.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -75,25 +93,31 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ Full,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values.clear_dependent_on(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values\\n+ .values\\n+ .remove(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.clear_dependent_on(&VirtualRegister::Constant(ConstantRegister::Error));\\n+ known_values\\n+ .values\\n+ .remove(&VirtualRegister::Constant(ConstantRegister::Error));\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Same here, `d` should be removed in the above `clear_dependent_on` call. \\n```suggestion\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -104,13 +128,25 @@ impl ResetKnown {\\n known_values.values.remove(d);\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Same here.\\n```suggestion\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"I am thinking here about adding the `log` than to all optimization methods (`dce`, `simplify_cfg`, ...) for completeness and that it's clear we want to use this as a pattern. Currently, it looks more as a temporary exception.\\n\\nMoreover, we can pass than the log to `AbstractInstructionSet::optimize` from the `optimize` caller.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -104,13 +128,25 @@ impl ResetKnown {\\n known_values.values.remove(d);\\n }\\n }\\n+ ResetKnown::DefsAndNonVirtuals => {\\n+ Self::Defs.apply(op, known_values);\\n+ known_values\\n+ .values\\n+ .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n+ }\\n+ ResetKnown::Full => {\\n+ known_values.values.clear();\\n+ }\\n }\\n }\\n }\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"```suggestion\\n // - \\\"JMP LABEL\\\" if reg is not zero\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -137,18 +173,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is zero\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Great idea to express the transformation as a DSL! ❤️ It makes both defining the transformations and reviewing them so much easier.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"```suggestion\\n // If the value is one of the operands, we will use MOVE,\\n // if it is a literal we will use MOVI\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"```suggestion\\n // Also transform them if their registers are known\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if they registers are known\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Nitpick. IMO, looks more natural to read in English if it is in imperative mode than third person singular.\\n```suggestion\\n (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Same.\\n```suggestion\\n (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"```suggestion\\n commutative: true;\\n```\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if they registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n+\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assigns right;\\n+ if right is 0 assigns left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assigns left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assigns right;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ if right is 0 assigns 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assigns 1;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ if left is 1 assigns 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assigns 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assigns left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assigns 0;\\n+ if right is 0 assigns 0;\\n+ commutative: true;\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Just thinking, for testing `constant_propagate` it makes no difference, but in a general case, optimizations run on functions and most of them do not care if it is an entry or not.\\n\\nSo I guess the most general case would be `function: Some((\\\"dummy_test_fn\\\", false))` but indeed if feels strange as a default.\\n\\nI would say let's keep it like this and once we start adding tests for other optimizations we can have in addition `optimise_fn`, `optimise_entry` or whatever needed.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +212,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assigns $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assigns $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if they registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n+\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assigns right;\\n+ if right is 0 assigns left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assigns left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assigns right;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ if right is 0 assigns 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assigns 1;\\n+ if right is 1 assigns left;\\n+ if left is 0 assigns 0;\\n+ if left is 1 assigns 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assigns 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assigns left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assigns 0;\\n+ if right is 0 assigns 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assigns right;\\n+ if right is 0 assigns left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assigns right;\\n+ if right is 0 assigns left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assigns left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assigns left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n- }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::Full,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::Full\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::Full,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Having a test for overflow would be good. Adding two known values that result in an overflow should not do any replacement.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +204,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n+\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n- }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Same here for underflow.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +204,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n+\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n- }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"And here for overflow again.\",\n \"path\": \"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\",\n \"hunk\": \"@@ -174,75 +204,697 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n+\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n- }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\nindex 1f0a93772bb..90ecbdb9768 100644\\n--- a/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n+++ b/sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs\\n@@ -1,13 +1,15 @@\\n-use std::collections::hash_map::Entry;\\n-\\n+use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use crate::asm_lang::{\\n+ ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualImmediate18, VirtualOp,\\n+ VirtualRegister,\\n+};\\n use either::Either;\\n use rustc_hash::FxHashMap;\\n-\\n-use crate::asm_lang::{\\n- ConstantRegister, ControlFlowOp, JumpType, Label, Op, VirtualOp, VirtualRegister,\\n+use std::{\\n+ collections::hash_map::Entry,\\n+ ops::{BitAnd, BitOr, BitXor, Not},\\n };\\n-\\n-use super::super::abstract_instruction_set::AbstractInstructionSet;\\n+use sway_types::Span;\\n \\n #[derive(Clone, Debug, PartialEq, Eq)]\\n enum KnownRegValue {\\n@@ -36,6 +38,11 @@ impl KnownRegValue {\\n }\\n }\\n \\n+ fn value_as_imm18(&self) -> Option<VirtualImmediate18> {\\n+ let raw = self.value()?;\\n+ VirtualImmediate18::try_new(raw, Span::dummy()).ok()\\n+ }\\n+\\n /// Check if the value depends on value of another register.\\n fn depends_on(&self, reg: &VirtualRegister) -> bool {\\n match self {\\n@@ -60,14 +67,24 @@ impl KnownValues {\\n }\\n }\\n \\n- /// Clear values that depend on a register having a specific value.\\n- fn clear_dependent_on(&mut self, reg: &VirtualRegister) {\\n- self.values.retain(|_, v| !v.depends_on(reg));\\n+ /// Remove `reg` and other known values that directly or indirectly (recursively) depend on `reg`.\\n+ fn remove_reg_and_dependents(&mut self, reg: &VirtualRegister) {\\n+ let mut worklist = vec![reg.clone()];\\n+\\n+ while let Some(reg) = worklist.pop() {\\n+ let keys = self\\n+ .values\\n+ .extract_if(|_, v| v.depends_on(®))\\n+ .map(|(k, _)| k);\\n+ worklist.extend(keys);\\n+\\n+ self.values.remove(®);\\n+ }\\n }\\n \\n /// Insert a known value for a register.\\n fn assign(&mut self, dst: VirtualRegister, value: KnownRegValue) {\\n- self.clear_dependent_on(&dst);\\n+ self.remove_reg_and_dependents(&dst);\\n self.values.insert(dst, value);\\n }\\n }\\n@@ -75,34 +92,42 @@ impl KnownValues {\\n /// What knowledge is lost after an op we don't know how to interpret?\\n #[derive(Clone, Debug)]\\n enum ResetKnown {\\n- /// Reset all known values\\n- Full,\\n- /// Reset non-virtual registers in addition to defs\\n- NonVirtual,\\n+ /// Do nothing\\n+ Nothing,\\n /// Only the `def_registers` and `def_const_registers` are reset\\n Defs,\\n+ /// Reset non-virtual registers in addition to defs\\n+ DefsAndNonVirtuals,\\n+ /// Reset all known values\\n+ All,\\n }\\n+\\n impl ResetKnown {\\n fn apply(&self, op: &Op, known_values: &mut KnownValues) {\\n+ // All instruction write to $of and $err somehow.\\n+ // Majority of cases we clear them\\n+ known_values\\n+ .remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Overflow));\\n+ known_values.remove_reg_and_dependents(&VirtualRegister::Constant(ConstantRegister::Error));\\n+\\n match self {\\n- ResetKnown::Full => {\\n- known_values.values.clear();\\n+ ResetKnown::Nothing => {}\\n+ ResetKnown::Defs => {\\n+ for d in op.def_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n+ for d in op.def_const_registers() {\\n+ known_values.remove_reg_and_dependents(d);\\n+ }\\n }\\n- ResetKnown::NonVirtual => {\\n+ ResetKnown::DefsAndNonVirtuals => {\\n Self::Defs.apply(op, known_values);\\n known_values\\n .values\\n .retain(|k, _| matches!(k, VirtualRegister::Virtual(_)));\\n }\\n- ResetKnown::Defs => {\\n- for d in op.def_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n- for d in op.def_const_registers() {\\n- known_values.clear_dependent_on(d);\\n- known_values.values.remove(d);\\n- }\\n+ ResetKnown::All => {\\n+ known_values.values.clear();\\n }\\n }\\n }\\n@@ -110,7 +135,10 @@ impl ResetKnown {\\n \\n impl AbstractInstructionSet {\\n /// Symbolically interpret code and propagate known register values.\\n- pub(crate) fn constant_propagate(mut self) -> AbstractInstructionSet {\\n+ pub(crate) fn constant_propagate(\\n+ mut self,\\n+ mut log: impl FnMut(&str),\\n+ ) -> AbstractInstructionSet {\\n if self.ops.is_empty() {\\n return self;\\n }\\n@@ -137,18 +165,20 @@ impl AbstractInstructionSet {\\n \\n for op in &mut self.ops {\\n // Perform constant propagation on the instruction.\\n- let mut uses_regs: Vec<_> = op.use_registers_mut().into_iter().collect();\\n- for reg in uses_regs.iter_mut() {\\n+ for reg in op.use_registers_mut() {\\n // We only optimize over virtual registers here, constant registers shouldn't be replaced\\n if !reg.is_virtual() {\\n continue;\\n }\\n+\\n if let Some(r) = known_values.resolve(reg).and_then(|r| r.register()) {\\n- **reg = r;\\n+ *reg = r;\\n }\\n }\\n \\n- // Some instructions can be further simplified with the known values.\\n+ // Replace \\\"JNZ reg LABEL\\\" to\\n+ // - NOOP if the reg is zero, or\\n+ // - \\\"JMP LABEL\\\" if reg is not zero\\n if let Either::Right(ControlFlowOp::Jump {\\n to,\\n type_: JumpType::NotZero(reg),\\n@@ -174,75 +204,788 @@ impl AbstractInstructionSet {\\n }\\n }\\n \\n- // Some ops are known to produce certain results, interpret them here.\\n- let interpreted_op = match &op.opcode {\\n+ // This macro must be declared here to be able to capture some variables\\n+ macro_rules! transform_operator {\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; left) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($l.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; right) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Eq($r.clone()));\\n+ };\\n+ (assign_value; $dst:ident, $l:ident, $r:ident; $v:literal) => {\\n+ known_values.assign($dst.clone(), KnownRegValue::Const($v));\\n+ };\\n+ // If the value is one of the operands, we will use MOVE\\n+ // if it is a literal we will use MOVI\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; left) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $l.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; right) => {\\n+ Either::Left(VirtualOp::MOVE($dst.clone(), $r.clone()))\\n+ };\\n+ (new_opcode; $dst:ident, $l:ident, $r:ident; $v:literal) => {{\\n+ let imm = VirtualImmediate18::try_new($v, Span::dummy()).ok()?;\\n+ Either::Left(VirtualOp::MOVI($dst.clone(), imm))\\n+ }};\\n+ // if left == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if left is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($initial_value)), _) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // if right == $initial_value assign $end_value\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; if right is $initial_value:literal assign $end_value:tt; $($rest:tt)*) => {\\n+ if let (_, Some(KnownRegValue::Const($initial_value))) = (&$lv, &$rv) {\\n+ let new_opcode = transform_operator!{new_opcode; $dst, $l, $r; $end_value};\\n+ // The line above can bail so we must run it before we change anything\\n+ transform_operator!{assign_value; $dst, $l, $r; $end_value};\\n+ op.opcode = new_opcode;\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // When both register values are known transform to MOVI\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; both_known: $f:path; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), Some(KnownRegValue::Const($rv))) = (&$lv, &$rv) {\\n+ let raw = $f(*$lv, (*$rv).try_into().ok()?)?.into();\\n+ let imm = VirtualImmediate18::try_new(raw, Span::dummy()).ok()?;\\n+ known_values.assign($dst.clone(), KnownRegValue::Const(raw));\\n+ op.opcode = Either::Left(VirtualOp::MOVI($dst.clone(), imm));\\n+ return Some(ResetKnown::Nothing);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ // Transform from $op to $opI because $op is commutative\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident; commutative: true; $($rest:tt)*) => {\\n+ if let (Some(KnownRegValue::Const($lv)), _) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $r.clone(), (*$lv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ transform_operator!{gen; $op, $opI; $dst, $l, $r, $lv, $rv; $($rest)*}\\n+ };\\n+ (gen; $op:ident, $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident;) => {\\n+ };\\n+ (gen; $op:ident, $opI:ident; $($rest:tt)*) => {\\n+ compile_error!(stringify!($($rest)*))\\n+ };\\n+ // Transform from $op to $opI if $opI was defined.\\n+ // Otherwise does not generate code\\n+ (replace_imm; None; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ };\\n+ (replace_imm; $opI:ident; $dst:ident, $l:ident, $r:ident, $lv: ident, $rv:ident) => {\\n+ if let (_, Some(KnownRegValue::Const(rv))) = (&$lv, &$rv) {\\n+ op.opcode = Either::Left(VirtualOp::$opI($dst.clone(), $l.clone(), (*rv).try_into().ok()?));\\n+ return Some(ResetKnown::Defs);\\n+ }\\n+ };\\n+ ($op:ident, $opI:ident; $($rest:tt)*) => {{\\n+ let mut f = || -> Option<ResetKnown> {\\n+ match &op.opcode {\\n+ Either::Left(VirtualOp::$op(dst, l, r)) => {\\n+ let lv = known_values.resolve(&l);\\n+ let rv = known_values.resolve(&r);\\n+ log(&format!(\\\" {:?} {:?}\\\\n\\\", lv, rv));\\n+\\n+ transform_operator!{gen; $op, $opI; dst, l, r, lv, rv; $($rest)*}\\n+ transform_operator!{replace_imm; $opI; dst, l, r, lv, rv}\\n+ }\\n+ _ => {}\\n+ };\\n+ None\\n+ };\\n+ f()\\n+ }};\\n+ }\\n+\\n+ let before = format!(\\\"{op}\\\");\\n+ log(&format!(\\\"{op}\\\\n\\\"));\\n+\\n+ // Propagate constant of some ops\\n+ // Also transform them if their registers are known\\n+ let reset = match op.opcode.clone() {\\n Either::Left(VirtualOp::MOVI(dst, imm)) => {\\n let imm = KnownRegValue::Const(imm.value() as u64);\\n- if known_values.resolve(dst) == Some(imm.clone()) {\\n+\\n+ // transform\\n+ // movi <dest is known> <imm>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(imm.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), imm);\\n+ known_values.assign(dst, imm);\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n Either::Left(VirtualOp::MOVE(dst, src)) => {\\n- if let Some(known) = known_values.resolve(src) {\\n- if known_values.resolve(dst) == Some(known.clone()) {\\n+ if let Some(known_src) = known_values.resolve(&src) {\\n+ // transform\\n+ // move <dest is known> <src is known>\\n+ // to\\n+ // noop\\n+ if known_values.resolve(&dst) == Some(known_src.clone()) {\\n op.opcode = Either::Left(VirtualOp::NOOP);\\n } else {\\n- known_values.assign(dst.clone(), known);\\n+ // transform\\n+ // move <dest is unknown> <src is known>\\n+ // to\\n+ // movi dest imm\\n+ if let Some(imm) = known_src.value_as_imm18() {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), imm));\\n+ }\\n+\\n+ known_values.assign(dst.clone(), known_src);\\n }\\n } else {\\n- known_values.assign(dst.clone(), KnownRegValue::Eq(src.clone()));\\n+ known_values.assign(dst, KnownRegValue::Eq(src));\\n }\\n- true\\n+\\n+ Some(ResetKnown::Nothing)\\n }\\n- _ => false,\\n- };\\n \\n- // If we don't know how to interpret the op, it's outputs are not known.\\n- if !interpreted_op {\\n- let reset = match &op.opcode {\\n- Either::Left(op) => match op {\\n- VirtualOp::ECAL(_, _, _, _) => ResetKnown::Full,\\n- // TODO: this constraint can be relaxed\\n- _ if op.has_side_effect() => ResetKnown::Full,\\n- _ => ResetKnown::Defs,\\n- },\\n- Either::Right(op) => match op {\\n- // If this is a jump target, then multiple execution paths can lead to it,\\n- // and we can't assume to know register values.\\n- ControlFlowOp::Label(label) => {\\n- if jump_target_labels.contains_key(label) {\\n- ResetKnown::Full\\n- } else {\\n- ResetKnown::Defs\\n- }\\n+ // algebraic operators\\n+ Either::Left(VirtualOp::ADD(..)) => transform_operator! {ADD, ADDI;\\n+ both_known: u64::checked_add;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SUB(..)) => transform_operator! {SUB, SUBI;\\n+ both_known: u64::checked_sub;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::MUL(..)) => transform_operator! {MUL, MULI;\\n+ both_known: u64::checked_mul;\\n+ if left is 1 assign right;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::DIV(..)) => transform_operator! {DIV, DIVI;\\n+ both_known: u64::checked_div;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::EXP(..)) => transform_operator! {EXP, EXPI;\\n+ both_known: u64::checked_pow;\\n+ if right is 0 assign 1;\\n+ if right is 1 assign left;\\n+ if left is 0 assign 0;\\n+ if left is 1 assign 1;\\n+ },\\n+ Either::Left(VirtualOp::MLOG(..)) => transform_operator! {MLOG, None;\\n+ both_known: u64::checked_ilog;\\n+ },\\n+ Either::Left(VirtualOp::MOD(..)) => transform_operator! {MOD, MODI;\\n+ both_known: u64::checked_rem;\\n+ if right is 1 assign 0;\\n+ },\\n+ Either::Left(VirtualOp::MROO(..)) => transform_operator! {MROO, None;\\n+ both_known: checked_nth_root;\\n+ if right is 1 assign left;\\n+ },\\n+\\n+ // bitwise\\n+ Either::Left(VirtualOp::NOT(dst, arg)) => {\\n+ let argv = known_values.resolve(&arg);\\n+ log(&format!(\\\" {:?}\\\\n\\\", argv));\\n+ if let Some(KnownRegValue::Const(argv)) = argv {\\n+ let raw = argv.not();\\n+ known_values.assign(dst.clone(), KnownRegValue::Const(raw));\\n+\\n+ let span = op.owning_span.clone();\\n+ if let Ok(v) =\\n+ VirtualImmediate18::try_new(raw, span.unwrap_or_else(Span::dummy))\\n+ {\\n+ op.opcode = Either::Left(VirtualOp::MOVI(dst.clone(), v));\\n }\\n- // Jumping away doesn't invalidate state, but for calls:\\n- // TODO: `def_const_registers` doesn't contain return value, which\\n- // seems incorrect, so I'm clearing everything as a precaution\\n- ControlFlowOp::Jump { type_, .. } => match type_ {\\n- JumpType::Call => ResetKnown::Full,\\n+\\n+ Some(ResetKnown::Nothing)\\n+ } else {\\n+ None\\n+ }\\n+ }\\n+ Either::Left(VirtualOp::AND(..)) => transform_operator! {AND, ANDI;\\n+ both_known: u64_bitand;\\n+ if left is 0 assign 0;\\n+ if right is 0 assign 0;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::OR(..)) => transform_operator! {OR, ORI;\\n+ both_known: u64_bitor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::XOR(..)) => transform_operator! {XOR, XORI;\\n+ both_known: u64_bitxor;\\n+ if left is 0 assign right;\\n+ if right is 0 assign left;\\n+ commutative: true;\\n+ },\\n+ Either::Left(VirtualOp::SLL(..)) => transform_operator! {SLL, SLLI;\\n+ both_known: u64::checked_shl;\\n+ if right is 0 assign left;\\n+ },\\n+ Either::Left(VirtualOp::SRL(..)) => transform_operator! {SRL, SRLI;\\n+ both_known: u64::checked_shr;\\n+ if right is 0 assign left;\\n+ },\\n+\\n+ // Comparisons\\n+ Either::Left(VirtualOp::EQ(..)) => transform_operator! {EQ, None;\\n+ both_known: u64_eq;\\n+ },\\n+ Either::Left(VirtualOp::GT(..)) => transform_operator! {GT, None;\\n+ both_known: u64_gt;\\n+ },\\n+ Either::Left(VirtualOp::LT(..)) => transform_operator! {LT, None;\\n+ both_known: u64_lt;\\n+ },\\n+ _ => None,\\n+ };\\n+\\n+ let after = format!(\\\"{op}\\\");\\n+ if before != after {\\n+ log(&format!(\\\" changed to: {op}\\\\n\\\"));\\n+ }\\n+\\n+ let reset = match reset {\\n+ None => {\\n+ match &op.opcode {\\n+ Either::Left(op) => match op {\\n+ VirtualOp::ECAL(_, _, _, _) => ResetKnown::All,\\n+ // TODO: this constraint can be relaxed\\n+ _ if op.has_side_effect() => ResetKnown::All,\\n _ => ResetKnown::Defs,\\n },\\n- // These ops mark their outputs properly and cause no control-flow effects\\n- ControlFlowOp::Comment\\n- | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n- | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n- // This changes the stack pointer\\n- ControlFlowOp::PushAll(_) => ResetKnown::NonVirtual,\\n- // This can be considered to destroy all known values\\n- ControlFlowOp::PopAll(_) => ResetKnown::Full,\\n- ControlFlowOp::JumpToAddr(_) => ResetKnown::Full,\\n- ControlFlowOp::ReturnFromCall { .. } => ResetKnown::Full,\\n- },\\n- };\\n+ Either::Right(op) => match op {\\n+ ControlFlowOp::Label(label) => {\\n+ if jump_target_labels.contains_key(label) {\\n+ ResetKnown::All\\n+ } else {\\n+ ResetKnown::Defs\\n+ }\\n+ }\\n+ ControlFlowOp::Jump { type_, .. } => match type_ {\\n+ JumpType::Call => ResetKnown::All,\\n+ _ => ResetKnown::Defs,\\n+ },\\n+ ControlFlowOp::Comment\\n+ | ControlFlowOp::ConfigurablesOffsetPlaceholder\\n+ | ControlFlowOp::DataSectionOffsetPlaceholder => ResetKnown::Defs,\\n+ ControlFlowOp::PushAll(_) => ResetKnown::DefsAndNonVirtuals,\\n+ ControlFlowOp::PopAll(_) => ResetKnown::All,\\n+ ControlFlowOp::JumpToAddr(_) => ResetKnown::All,\\n+ ControlFlowOp::ReturnFromCall { .. } => ResetKnown::All,\\n+ },\\n+ }\\n+ }\\n+ Some(reset) => reset,\\n+ };\\n \\n- reset.apply(op, &mut known_values);\\n- }\\n+ log(&format!(\\\" {reset:?}\\\\n\\\"));\\n+ reset.apply(op, &mut known_values);\\n }\\n \\n self\\n }\\n }\\n+\\n+#[inline(always)]\\n+fn u64_bitand(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitand(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_bitxor(l: u64, r: u64) -> Option<u64> {\\n+ Some(l.bitxor(r))\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_eq(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l == r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_gt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l > r { 1 } else { 0 })\\n+}\\n+\\n+#[inline(always)]\\n+fn u64_lt(l: u64, r: u64) -> Option<u64> {\\n+ Some(if l < r { 1 } else { 0 })\\n+}\\n+\\n+// Copied from fuel_vm to guarantee exactly same behaviour.\\n+// See fuel-vm/src/interpreter/executors/instruction.rs\\n+pub fn checked_nth_root(target: u64, nth_root: u64) -> Option<u64> {\\n+ if nth_root == 0 {\\n+ // Zeroth root is not defined\\n+ return None;\\n+ }\\n+\\n+ if nth_root == 1 || target <= 1 {\\n+ // Corner cases\\n+ return Some(target);\\n+ }\\n+\\n+ if nth_root >= target || nth_root > 64 {\\n+ // For any root >= target, result always 1\\n+ // For any n>1, n**64 can never fit into u64\\n+ return Some(1);\\n+ }\\n+\\n+ let nth_root = u32::try_from(nth_root).expect(\\\"Never loses bits, checked above\\\");\\n+\\n+ // Use floating point operation to get an approximation for the starting point.\\n+ // This is at most off by one in either direction.\\n+\\n+ let powf = f64::powf;\\n+\\n+ #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]\\n+ let guess = powf(target as f64, (nth_root as f64).recip()) as u64;\\n+\\n+ debug_assert!(guess != 0, \\\"This should never occur for {{target, n}} > 1\\\");\\n+\\n+ // Check if a value raised to nth_power is below the target value, handling overflow\\n+ // correctly\\n+ let is_nth_power_below_target = |v: u64| match v.checked_pow(nth_root) {\\n+ Some(pow) => target < pow,\\n+ None => true, // v**nth_root >= 2**64 and target < 2**64\\n+ };\\n+\\n+ // Compute guess**n to check if the guess is too large.\\n+ // Note that if guess == 1, then g1 == 1 as well, meaning that we will not return\\n+ // here.\\n+ if is_nth_power_below_target(guess) {\\n+ return Some(guess.saturating_sub(1));\\n+ }\\n+\\n+ // Check if the initial guess was correct\\n+ let guess_plus_one = guess\\n+ .checked_add(1)\\n+ .expect(\\\"Guess cannot be u64::MAX, as we have taken a root > 2 of a value to get it\\\");\\n+ if is_nth_power_below_target(guess_plus_one) {\\n+ return Some(guess);\\n+ }\\n+\\n+ // If not, then the value above must be the correct one.\\n+ Some(guess_plus_one)\\n+}\\n+\\n+#[cfg(test)]\\n+mod tests {\\n+ use super::*;\\n+ use expect_test::expect;\\n+\\n+ fn optimise(\\n+ ops: impl IntoIterator<Item = Op>,\\n+ f: impl FnOnce(AbstractInstructionSet) -> AbstractInstructionSet,\\n+ ) {\\n+ let mut ops = AbstractInstructionSet {\\n+ function: None,\\n+ ops: ops.into_iter().collect(),\\n+ };\\n+\\n+ for i in 0..ops.ops.len() {\\n+ ops.ops[i].comment = i.to_string();\\n+ }\\n+\\n+ f(ops);\\n+ }\\n+\\n+ #[test]\\n+ fn constant_propagate_transform() {\\n+ let mut str = String::new();\\n+ let capture = |s: &str| {\\n+ str.push_str(s);\\n+ };\\n+ optimise(\\n+ [\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ VirtualOp::movi(\\\"1\\\", 10).into(),\\n+ VirtualOp::movi(\\\"2\\\", 2).into(),\\n+ VirtualOp::movi(\\\"3\\\", 8).into(),\\n+ VirtualOp::movi(\\\"4\\\", 9).into(),\\n+ // movi\\n+ VirtualOp::movi(\\\"0\\\", 10).into(),\\n+ // mov\\n+ VirtualOp::r#move(\\\"0\\\", \\\"1\\\").into(),\\n+ //add\\n+ VirtualOp::add(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::add(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ // add when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::add(\\\"11\\\", \\\"10\\\", ConstantRegister::One).into(),\\n+ //sub\\n+ VirtualOp::sub(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::sub(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ // sub when underflow\\n+ VirtualOp::sub(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::One).into(),\\n+ //mul\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg1, ConstantRegister::One, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg4, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg5, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::mul(ConstantRegister::FuncArg0, \\\"0\\\", \\\"5\\\").into(),\\n+ // mul when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mul(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // div\\n+ VirtualOp::div(ConstantRegister::FuncArg0, \\\"0\\\", \\\"1\\\").into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::div(ConstantRegister::FuncArg2, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ // div with invalid args\\n+ VirtualOp::div(\\\"11\\\", ConstantRegister::Zero, ConstantRegister::Zero).into(),\\n+ // exp\\n+ VirtualOp::exp(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::exp(\\n+ ConstantRegister::FuncArg0,\\n+ ConstantRegister::Zero,\\n+ ConstantRegister::Zero,\\n+ )\\n+ .into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg1, \\\"0\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg2, \\\"0\\\", ConstantRegister::One).into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg3, ConstantRegister::Zero, \\\"0\\\").into(),\\n+ VirtualOp::exp(ConstantRegister::FuncArg4, ConstantRegister::One, \\\"0\\\").into(),\\n+ // exp when overflow\\n+ VirtualOp::not(\\\"10\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::exp(\\\"11\\\", \\\"10\\\", \\\"10\\\").into(),\\n+ // mlog\\n+ VirtualOp::mlog(ConstantRegister::FuncArg0, \\\"3\\\", \\\"2\\\").into(),\\n+ // mlog with invalid args\\n+ VirtualOp::mlog(\\\"11\\\", ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::mlog(\\\"11\\\", \\\"3\\\", ConstantRegister::One).into(),\\n+ // mod\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::r#mod(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mod with invalid args\\n+ VirtualOp::r#mod(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ // mroo\\n+ VirtualOp::mroo(ConstantRegister::FuncArg0, \\\"4\\\", \\\"2\\\").into(),\\n+ VirtualOp::mroo(ConstantRegister::FuncArg1, \\\"4\\\", ConstantRegister::One).into(),\\n+ // mroo with invalid args\\n+ VirtualOp::mroo(\\\"11\\\", \\\"4\\\", ConstantRegister::Zero).into(),\\n+ //and\\n+ VirtualOp::and(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::and(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //or\\n+ VirtualOp::or(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::or(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //xor\\n+ VirtualOp::xor(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg1, ConstantRegister::Zero, \\\"2\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg3, \\\"5\\\", \\\"0\\\").into(),\\n+ VirtualOp::xor(ConstantRegister::FuncArg4, \\\"0\\\", \\\"5\\\").into(),\\n+ //sll\\n+ VirtualOp::sll(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::sll(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //srl\\n+ VirtualOp::srl(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ VirtualOp::srl(ConstantRegister::FuncArg2, \\\"2\\\", ConstantRegister::Zero).into(),\\n+ //eq\\n+ VirtualOp::eq(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //gt\\n+ VirtualOp::gt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ //lt\\n+ VirtualOp::lt(ConstantRegister::FuncArg0, \\\"0\\\", \\\"2\\\").into(),\\n+ // err register\\n+ // we dot not want propagation in this case\\n+ VirtualOp::r#move(\\\"0\\\", ConstantRegister::Error).into(),\\n+ VirtualOp::eq(\\\"1\\\", \\\"0\\\", ConstantRegister::One).into(),\\n+ ],\\n+ |ops| ops.constant_propagate(capture),\\n+ );\\n+\\n+ expect![[r#\\\"\\n+ movi $r0 i10 ; 0\\n+ Nothing\\n+ movi $r1 i10 ; 1\\n+ Nothing\\n+ movi $r2 i2 ; 2\\n+ Nothing\\n+ movi $r3 i8 ; 3\\n+ Nothing\\n+ movi $r4 i9 ; 4\\n+ Nothing\\n+ movi $r0 i10 ; 5\\n+ changed to: noop ; 5\\n+ Nothing\\n+ move $r0 $r1 ; 6\\n+ changed to: noop ; 6\\n+ Nothing\\n+ add $$arg0 $r0 $r1 ; 7\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i20 ; 7\\n+ Nothing\\n+ add $$arg1 $zero $r0 ; 8\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 8\\n+ Nothing\\n+ add $$arg2 $r0 $zero ; 9\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg2 i10 ; 9\\n+ Nothing\\n+ add $$arg3 $r5 $r0 ; 10\\n+ None Some(Const(10))\\n+ changed to: addi $$arg3 $r5 i10 ; 10\\n+ Defs\\n+ add $$arg4 $r0 $r5 ; 11\\n+ Some(Const(10)) None\\n+ changed to: addi $$arg4 $r5 i10 ; 11\\n+ Defs\\n+ not $r10 $zero ; 12\\n+ Some(Const(0))\\n+ Nothing\\n+ add $r11 $r10 $one ; 13\\n+ Some(Const(18446744073709551615)) Some(Const(1))\\n+ Defs\\n+ sub $$arg0 $r0 $r1 ; 14\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i0 ; 14\\n+ Nothing\\n+ sub $$arg1 $r0 $zero ; 15\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i10 ; 15\\n+ Nothing\\n+ sub $r11 $zero $one ; 16\\n+ Some(Const(0)) Some(Const(1))\\n+ Defs\\n+ mul $$arg0 $r0 $r1 ; 17\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i100 ; 17\\n+ Nothing\\n+ mul $$arg1 $one $r0 ; 18\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg1 i10 ; 18\\n+ Nothing\\n+ mul $$arg2 $r0 $one ; 19\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 19\\n+ Nothing\\n+ mul $$arg3 $zero $r0 ; 20\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 20\\n+ Nothing\\n+ mul $$arg4 $r0 $zero ; 21\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg4 i0 ; 21\\n+ Nothing\\n+ mul $$arg5 $r5 $r0 ; 22\\n+ None Some(Const(10))\\n+ changed to: muli $$arg5 $r5 i10 ; 22\\n+ Defs\\n+ mul $$arg0 $r0 $r5 ; 23\\n+ Some(Const(10)) None\\n+ changed to: muli $$arg0 $r5 i10 ; 23\\n+ Defs\\n+ not $r10 $zero ; 24\\n+ Some(Const(0))\\n+ Nothing\\n+ mul $r11 $r10 $r10 ; 25\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ div $$arg0 $r0 $r1 ; 26\\n+ Some(Const(10)) Some(Const(10))\\n+ changed to: movi $$arg0 i1 ; 26\\n+ Nothing\\n+ div $$arg1 $r0 $one ; 27\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg1 i10 ; 27\\n+ Nothing\\n+ div $$arg2 $zero $r0 ; 28\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg2 i0 ; 28\\n+ Nothing\\n+ div $r11 $zero $zero ; 29\\n+ Some(Const(0)) Some(Const(0))\\n+ Defs\\n+ exp $$arg0 $r0 $r2 ; 30\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i100 ; 30\\n+ Nothing\\n+ exp $$arg0 $zero $zero ; 31\\n+ Some(Const(0)) Some(Const(0))\\n+ changed to: movi $$arg0 i1 ; 31\\n+ Nothing\\n+ exp $$arg1 $r0 $zero ; 32\\n+ Some(Const(10)) Some(Const(0))\\n+ changed to: movi $$arg1 i1 ; 32\\n+ Nothing\\n+ exp $$arg2 $r0 $one ; 33\\n+ Some(Const(10)) Some(Const(1))\\n+ changed to: movi $$arg2 i10 ; 33\\n+ Nothing\\n+ exp $$arg3 $zero $r0 ; 34\\n+ Some(Const(0)) Some(Const(10))\\n+ changed to: movi $$arg3 i0 ; 34\\n+ Nothing\\n+ exp $$arg4 $one $r0 ; 35\\n+ Some(Const(1)) Some(Const(10))\\n+ changed to: movi $$arg4 i1 ; 35\\n+ Nothing\\n+ not $r10 $zero ; 36\\n+ Some(Const(0))\\n+ Nothing\\n+ exp $r11 $r10 $r10 ; 37\\n+ Some(Const(18446744073709551615)) Some(Const(18446744073709551615))\\n+ Defs\\n+ mlog $$arg0 $r3 $r2 ; 38\\n+ Some(Const(8)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 38\\n+ Nothing\\n+ mlog $r11 $zero $r2 ; 39\\n+ Some(Const(0)) Some(Const(2))\\n+ Defs\\n+ mlog $r11 $r3 $zero ; 40\\n+ Some(Const(8)) Some(Const(0))\\n+ Defs\\n+ mlog $r11 $r3 $one ; 41\\n+ Some(Const(8)) Some(Const(1))\\n+ Defs\\n+ mod $$arg0 $r4 $r2 ; 42\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 42\\n+ Nothing\\n+ mod $$arg1 $r4 $one ; 43\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i0 ; 43\\n+ Nothing\\n+ mod $r11 $r4 $zero ; 44\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ mroo $$arg0 $r4 $r2 ; 45\\n+ Some(Const(9)) Some(Const(2))\\n+ changed to: movi $$arg0 i3 ; 45\\n+ Nothing\\n+ mroo $$arg1 $r4 $one ; 46\\n+ Some(Const(9)) Some(Const(1))\\n+ changed to: movi $$arg1 i9 ; 46\\n+ Nothing\\n+ mroo $r11 $r4 $zero ; 47\\n+ Some(Const(9)) Some(Const(0))\\n+ Defs\\n+ and $$arg0 $r0 $r2 ; 48\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 48\\n+ Nothing\\n+ and $$arg1 $zero $r2 ; 49\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i0 ; 49\\n+ Nothing\\n+ and $$arg2 $r2 $zero ; 50\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i0 ; 50\\n+ Nothing\\n+ and $$arg3 $r5 $r0 ; 51\\n+ None Some(Const(10))\\n+ changed to: andi $$arg3 $r5 i10 ; 51\\n+ Defs\\n+ and $$arg4 $r0 $r5 ; 52\\n+ Some(Const(10)) None\\n+ changed to: andi $$arg4 $r5 i10 ; 52\\n+ Defs\\n+ or $$arg0 $r0 $r2 ; 53\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i10 ; 53\\n+ Nothing\\n+ or $$arg1 $zero $r2 ; 54\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 54\\n+ Nothing\\n+ or $$arg2 $r2 $zero ; 55\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 55\\n+ Nothing\\n+ or $$arg3 $r5 $r0 ; 56\\n+ None Some(Const(10))\\n+ changed to: ori $$arg3 $r5 i10 ; 56\\n+ Defs\\n+ or $$arg4 $r0 $r5 ; 57\\n+ Some(Const(10)) None\\n+ changed to: ori $$arg4 $r5 i10 ; 57\\n+ Defs\\n+ xor $$arg0 $r0 $r2 ; 58\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i8 ; 58\\n+ Nothing\\n+ xor $$arg1 $zero $r2 ; 59\\n+ Some(Const(0)) Some(Const(2))\\n+ changed to: movi $$arg1 i2 ; 59\\n+ Nothing\\n+ xor $$arg2 $r2 $zero ; 60\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 60\\n+ Nothing\\n+ xor $$arg3 $r5 $r0 ; 61\\n+ None Some(Const(10))\\n+ changed to: xori $$arg3 $r5 i10 ; 61\\n+ Defs\\n+ xor $$arg4 $r0 $r5 ; 62\\n+ Some(Const(10)) None\\n+ changed to: xori $$arg4 $r5 i10 ; 62\\n+ Defs\\n+ sll $$arg0 $r0 $r2 ; 63\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i40 ; 63\\n+ Nothing\\n+ sll $$arg2 $r2 $zero ; 64\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 64\\n+ Nothing\\n+ srl $$arg0 $r0 $r2 ; 65\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i2 ; 65\\n+ Nothing\\n+ srl $$arg2 $r2 $zero ; 66\\n+ Some(Const(2)) Some(Const(0))\\n+ changed to: movi $$arg2 i2 ; 66\\n+ Nothing\\n+ eq $$arg0 $r0 $r2 ; 67\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 67\\n+ Nothing\\n+ gt $$arg0 $r0 $r2 ; 68\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i1 ; 68\\n+ Nothing\\n+ lt $$arg0 $r0 $r2 ; 69\\n+ Some(Const(10)) Some(Const(2))\\n+ changed to: movi $$arg0 i0 ; 69\\n+ Nothing\\n+ move $r0 $err ; 70\\n+ Nothing\\n+ eq $r1 $r0 $one ; 71\\n+ None Some(Const(1))\\n+ Defs\\n+ \\\"#]]\\n+ .assert_eq(&str);\\n+ }\\n+}\\n\"\n },\n {\n \"comment\": \"Nit.\\n```suggestion\\n /// Examples: Error, Overflow, Flags, etc.\\n```\",\n \"path\": \"sway-core/src/asm_lang/mod.rs\",\n \"hunk\": \"@@ -700,20 +710,24 @@ impl Op {\\n }\\n \\n /// Returns a list of all registers *read* by instruction `self`.\\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\\n match &mut self.opcode {\\n Either::Left(virt_op) => virt_op.use_registers_mut(),\\n Either::Right(org_op) => org_op.use_registers_mut(),\\n }\\n }\\n \\n+ /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\\n+ /// exactly 0 or 1 register, so the size of this returned vector should always be at most 1.\\n pub(crate) fn def_registers(&self) -> BTreeSet<&VirtualRegister> {\\n match &self.opcode {\\n Either::Left(virt_op) => virt_op.def_registers(),\\n Either::Right(org_op) => org_op.def_registers(),\\n }\\n }\\n \\n+ /// What are the special registers that an OP may set.\\n+ /// Examples: Error, Overflow, Flags etc...\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_lang/mod.rs b/sway-core/src/asm_lang/mod.rs\\nindex 805470d600f..cc302e5fe37 100644\\n--- a/sway-core/src/asm_lang/mod.rs\\n+++ b/sway-core/src/asm_lang/mod.rs\\n@@ -94,6 +94,16 @@ pub(crate) struct Op {\\n pub(crate) owning_span: Option<Span>,\\n }\\n \\n+impl From<VirtualOp> for Op {\\n+ fn from(opcode: VirtualOp) -> Self {\\n+ Op {\\n+ opcode: Either::Left(opcode),\\n+ comment: String::new(),\\n+ owning_span: None,\\n+ }\\n+ }\\n+}\\n+\\n #[derive(Clone, Debug)]\\n pub(crate) struct AllocatedAbstractOp {\\n pub(crate) opcode: Either<AllocatedInstruction, ControlFlowOp<AllocatedRegister>>,\\n@@ -700,13 +710,15 @@ impl Op {\\n }\\n \\n /// Returns a list of all registers *read* by instruction `self`.\\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\\n match &mut self.opcode {\\n Either::Left(virt_op) => virt_op.use_registers_mut(),\\n Either::Right(org_op) => org_op.use_registers_mut(),\\n }\\n }\\n \\n+ /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\\n+ /// exactly 0 or 1 register, so the size of this returned vector should always be at most 1.\\n pub(crate) fn def_registers(&self) -> BTreeSet<&VirtualRegister> {\\n match &self.opcode {\\n Either::Left(virt_op) => virt_op.def_registers(),\\n@@ -714,6 +726,8 @@ impl Op {\\n }\\n }\\n \\n+ /// What are the special registers that an OP may set.\\n+ /// Examples: Error, Overflow, Flags, etc.\\n pub(crate) fn def_const_registers(&self) -> BTreeSet<&VirtualRegister> {\\n match &self.opcode {\\n Either::Left(virt_op) => virt_op.def_const_registers(),\\n@@ -1144,7 +1158,7 @@ impl fmt::Display for VirtualOp {\\n MROO(a, b, c) => write!(fmtr, \\\"mroo {a} {b} {c}\\\"),\\n MUL(a, b, c) => write!(fmtr, \\\"mul {a} {b} {c}\\\"),\\n MULI(a, b, c) => write!(fmtr, \\\"muli {a} {b} {c}\\\"),\\n- NOOP => Ok(()),\\n+ NOOP => write!(fmtr, \\\"noop\\\"),\\n NOT(a, b) => write!(fmtr, \\\"not {a} {b}\\\"),\\n OR(a, b, c) => write!(fmtr, \\\"or {a} {b} {c}\\\"),\\n ORI(a, b, c) => write!(fmtr, \\\"ori {a} {b} {c}\\\"),\\n@@ -1359,9 +1373,10 @@ impl<Reg: Clone + Eq + Ord + Hash> ControlFlowOp<Reg> {\\n }\\n \\n /// Returns a list of all registers *read* by instruction `self`.\\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut Reg> {\\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut Reg> {\\n use ControlFlowOp::*;\\n- (match self {\\n+\\n+ match self {\\n Label(_)\\n | Comment\\n | DataSectionOffsetPlaceholder\\n@@ -1375,9 +1390,7 @@ impl<Reg: Clone + Eq + Ord + Hash> ControlFlowOp<Reg> {\\n },\\n JumpToAddr(r0) => vec![r0],\\n ReturnFromCall { zero, reta } => vec![zero, reta],\\n- })\\n- .into_iter()\\n- .collect()\\n+ }\\n }\\n \\n pub(crate) fn def_registers(&self) -> BTreeSet<&Reg> {\\n\"\n },\n {\n \"comment\": \"```suggestion\\n pub fn movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {\\n```\",\n \"path\": \"sway-core/src/asm_lang/virtual_ops.rs\",\n \"hunk\": \"@@ -249,6 +249,142 @@ pub(crate) enum VirtualOp {\\n }\\n \\n impl VirtualOp {\\n+ pub fn r#move(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\\n+ VirtualOp::MOVE(a.into(), b.into())\\n+ }\\n+\\n+ pub fn r#movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_lang/virtual_ops.rs b/sway-core/src/asm_lang/virtual_ops.rs\\nindex 57ac24ff488..f5a6a2dba6d 100644\\n--- a/sway-core/src/asm_lang/virtual_ops.rs\\n+++ b/sway-core/src/asm_lang/virtual_ops.rs\\n@@ -249,6 +249,146 @@ pub(crate) enum VirtualOp {\\n }\\n \\n impl VirtualOp {\\n+ pub fn r#move(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\\n+ VirtualOp::MOVE(a.into(), b.into())\\n+ }\\n+\\n+ pub fn movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {\\n+ VirtualOp::MOVI(a.into(), b.into())\\n+ }\\n+\\n+ pub fn add(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::ADD(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn sub(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::SUB(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn mul(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MUL(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn div(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::DIV(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn exp(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::EXP(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn mlog(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MLOG(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn r#mod(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MOD(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn mroo(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MROO(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn not(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\\n+ VirtualOp::NOT(a.into(), b.into())\\n+ }\\n+\\n+ pub fn and(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::AND(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn or(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::OR(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn xor(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::XOR(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn sll(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::SLL(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn srl(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::SRL(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn eq(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::EQ(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn gt(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::GT(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn lt(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::LT(a.into(), b.into(), c.into())\\n+ }\\n+\\n pub(crate) fn registers(&self) -> BTreeSet<&VirtualRegister> {\\n use VirtualOp::*;\\n (match self {\\n@@ -480,7 +620,8 @@ impl VirtualOp {\\n }\\n }\\n \\n- // What are the special registers that an OP may set.\\n+ /// What are the special registers that an OP may set.\\n+ /// Examples: Error, Overflow, Flags, etc.\\n pub(crate) fn def_const_registers(&self) -> BTreeSet<&VirtualRegister> {\\n use ConstantRegister::*;\\n use VirtualOp::*;\\n@@ -712,9 +853,9 @@ impl VirtualOp {\\n }\\n \\n /// Returns a list of all registers *read* by instruction `self`.\\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\\n use VirtualOp::*;\\n- (match self {\\n+ match self {\\n /* Arithmetic/Logic (ALU) Instructions */\\n ADD(_r1, r2, r3) => vec![r2, r3],\\n ADDI(_r1, r2, _i) => vec![r2],\\n@@ -828,9 +969,7 @@ impl VirtualOp {\\n AddrDataId(_r1, _i) => vec![],\\n \\n Undefined => vec![],\\n- })\\n- .into_iter()\\n- .collect()\\n+ }\\n }\\n \\n /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\\n\"\n },\n {\n \"comment\": \"```suggestion\\n /// Examples: Error, Overflow, Flags, etc.\\n```\",\n \"path\": \"sway-core/src/asm_lang/virtual_ops.rs\",\n \"hunk\": \"@@ -480,7 +616,8 @@ impl VirtualOp {\\n }\\n }\\n \\n- // What are the special registers that an OP may set.\\n+ /// What are the special registers that an OP may set.\\n+ /// Examples: Error, Overflow, Flags etc...\",\n \"resolving_sha\": \"2765f4af57abc203a826d5890c77e4593c6095ff\",\n \"resolving_diff\": \"diff --git a/sway-core/src/asm_lang/virtual_ops.rs b/sway-core/src/asm_lang/virtual_ops.rs\\nindex 57ac24ff488..f5a6a2dba6d 100644\\n--- a/sway-core/src/asm_lang/virtual_ops.rs\\n+++ b/sway-core/src/asm_lang/virtual_ops.rs\\n@@ -249,6 +249,146 @@ pub(crate) enum VirtualOp {\\n }\\n \\n impl VirtualOp {\\n+ pub fn r#move(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\\n+ VirtualOp::MOVE(a.into(), b.into())\\n+ }\\n+\\n+ pub fn movi(a: impl Into<VirtualRegister>, b: impl Into<VirtualImmediate18>) -> VirtualOp {\\n+ VirtualOp::MOVI(a.into(), b.into())\\n+ }\\n+\\n+ pub fn add(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::ADD(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn sub(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::SUB(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn mul(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MUL(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn div(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::DIV(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn exp(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::EXP(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn mlog(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MLOG(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn r#mod(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MOD(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn mroo(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::MROO(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn not(a: impl Into<VirtualRegister>, b: impl Into<VirtualRegister>) -> VirtualOp {\\n+ VirtualOp::NOT(a.into(), b.into())\\n+ }\\n+\\n+ pub fn and(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::AND(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn or(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::OR(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn xor(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::XOR(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn sll(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::SLL(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn srl(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::SRL(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn eq(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::EQ(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn gt(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::GT(a.into(), b.into(), c.into())\\n+ }\\n+\\n+ pub fn lt(\\n+ a: impl Into<VirtualRegister>,\\n+ b: impl Into<VirtualRegister>,\\n+ c: impl Into<VirtualRegister>,\\n+ ) -> VirtualOp {\\n+ VirtualOp::LT(a.into(), b.into(), c.into())\\n+ }\\n+\\n pub(crate) fn registers(&self) -> BTreeSet<&VirtualRegister> {\\n use VirtualOp::*;\\n (match self {\\n@@ -480,7 +620,8 @@ impl VirtualOp {\\n }\\n }\\n \\n- // What are the special registers that an OP may set.\\n+ /// What are the special registers that an OP may set.\\n+ /// Examples: Error, Overflow, Flags, etc.\\n pub(crate) fn def_const_registers(&self) -> BTreeSet<&VirtualRegister> {\\n use ConstantRegister::*;\\n use VirtualOp::*;\\n@@ -712,9 +853,9 @@ impl VirtualOp {\\n }\\n \\n /// Returns a list of all registers *read* by instruction `self`.\\n- pub(crate) fn use_registers_mut(&mut self) -> BTreeSet<&mut VirtualRegister> {\\n+ pub(crate) fn use_registers_mut(&mut self) -> Vec<&mut VirtualRegister> {\\n use VirtualOp::*;\\n- (match self {\\n+ match self {\\n /* Arithmetic/Logic (ALU) Instructions */\\n ADD(_r1, r2, r3) => vec![r2, r3],\\n ADDI(_r1, r2, _i) => vec![r2],\\n@@ -828,9 +969,7 @@ impl VirtualOp {\\n AddrDataId(_r1, _i) => vec![],\\n \\n Undefined => vec![],\\n- })\\n- .into_iter()\\n- .collect()\\n+ }\\n }\\n \\n /// Returns a list of all registers *written* by instruction `self`. All of our opcodes define\\n\"\n }\n]","isConversational":false},"test_patch":{"kind":"string","value":"diff --git a/forc/tests/cli_integration.rs b/forc/tests/cli_integration.rs\nindex de22c0bf9d6..e383db3c042 100644\n--- a/forc/tests/cli_integration.rs\n+++ b/forc/tests/cli_integration.rs\n@@ -51,10 +51,10 @@ fn test_forc_test_raw_logs() -> Result<(), rexpect::error::Error> {\n // Assert that the output is correct\n process.exp_string(\" test test_log_4\")?;\n process.exp_string(\"raw logs:\")?;\n- process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000004\",\"digest\":\"8005f02d43fa06e7d0585fb64c961d57e318b27a145c857bcd3a6bdb413ff7fc\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11320,\"ptr\":12512,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n+ process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000004\",\"digest\":\"8005f02d43fa06e7d0585fb64c961d57e318b27a145c857bcd3a6bdb413ff7fc\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11292,\"ptr\":12480,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n process.exp_string(\" test test_log_2\")?;\n process.exp_string(\"raw logs:\")?;\n- process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000002\",\"digest\":\"cd04a4754498e06db5a13c5f371f1f04ff6d2470f24aa9bd886540e5dce77f70\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11320,\"ptr\":12512,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n+ process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000002\",\"digest\":\"cd04a4754498e06db5a13c5f371f1f04ff6d2470f24aa9bd886540e5dce77f70\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11292,\"ptr\":12480,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n \n process.process.exit()?;\n Ok(())\n@@ -77,12 +77,12 @@ fn test_forc_test_both_logs() -> Result<(), rexpect::error::Error> {\n process.exp_string(\"decoded log values:\")?;\n process.exp_string(\"4, log rb: 1515152261580153489\")?;\n process.exp_string(\"raw logs:\")?;\n- process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000004\",\"digest\":\"8005f02d43fa06e7d0585fb64c961d57e318b27a145c857bcd3a6bdb413ff7fc\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11320,\"ptr\":12512,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n+ process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000004\",\"digest\":\"8005f02d43fa06e7d0585fb64c961d57e318b27a145c857bcd3a6bdb413ff7fc\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11292,\"ptr\":12480,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n process.exp_string(\" test test_log_2\")?;\n process.exp_string(\"decoded log values:\")?;\n process.exp_string(\"2, log rb: 1515152261580153489\")?;\n process.exp_string(\"raw logs:\")?;\n- process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000002\",\"digest\":\"cd04a4754498e06db5a13c5f371f1f04ff6d2470f24aa9bd886540e5dce77f70\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11320,\"ptr\":12512,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n+ process.exp_string(r#\"[{\"LogData\":{\"data\":\"0000000000000002\",\"digest\":\"cd04a4754498e06db5a13c5f371f1f04ff6d2470f24aa9bd886540e5dce77f70\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":11292,\"ptr\":12480,\"ra\":0,\"rb\":1515152261580153489}}]\"#)?;\n process.process.exit()?;\n Ok(())\n }\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/array_wrong_elements_types/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/array_wrong_elements_types/stdout.snap\nindex 8fb81c97b42..d24cab1f159 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/array_wrong_elements_types/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/array_wrong_elements_types/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/array_wrong_elements_types\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract/stdout.snap\nindex d4011314ebb..5724e5c8f7b 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_configurable/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_configurable/stdout.snap\nindex 8d89fae4828..a4418efc495 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_configurable/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_configurable/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_configurable\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_storage/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_storage/stdout.snap\nindex da3996ba4fe..6bf6e1b74ca 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_storage/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_storage/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_storage\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/contract_implements_multiple_abis_with_same_methods/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/contract_implements_multiple_abis_with_same_methods/stdout.snap\nindex 55f24840cc6..d73375fc9af 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/contract_implements_multiple_abis_with_same_methods/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/contract_implements_multiple_abis_with_same_methods/stdout.snap\n@@ -1,5 +1,5 @@\n ---\n-source: test/tests/tests.rs\n+source: test/src/snapshot/mod.rs\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/contract_implements_multiple_abis_with_same_methods\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/language/intrinsics/transmute/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/language/intrinsics/transmute/stdout.snap\nindex a97a234bd0c..cd2f6e9ae12 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/language/intrinsics/transmute/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/language/intrinsics/transmute/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/language/intrinsics/transmute\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panic_expressions/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panic_expressions/stdout.snap\nindex 3d91b30b3b6..2e87aa6e16b 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panic_expressions/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panic_expressions/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panic_expressions\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panicking_calls/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panicking_calls/stdout.snap\nindex d1aed68ba77..28f898297a6 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panicking_calls/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panicking_calls/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/language/panic_expression/too_many_panicking_calls\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/method_not_found/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/method_not_found/stdout.snap\nindex 826d5103827..2907d0e0964 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/method_not_found/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/method_not_found/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/method_not_found\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_fail/type_check_analyze_errors/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/type_check_analyze_errors/stdout.snap\nindex 9752e6db34a..2ca3d542a21 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_fail/type_check_analyze_errors/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_fail/type_check_analyze_errors/stdout.snap\n@@ -1,5 +1,5 @@\n ---\n-source: test/tests/tests.rs\n+source: test/src/snapshot/mod.rs\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_fail/type_check_analyze_errors\n exit status: 1\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap\nindex 637ecb51f20..6199f3cdf73 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap\n@@ -524,93 +524,90 @@ move $$locbase $sp ; [fn init: main_0]: set locals base register\n cfei i264920 ; [fn init: main_0]: allocate: locals 264920 byte(s), call args 0 slot(s)\n move $r1 $$reta ; [fn init: main_0]: save return address\n move $$arg0 $$locbase ; [call: array_repeat_zero_small_u8_1]: pass argument 0\n-jal $$reta $pc i94 ; [call: array_repeat_zero_small_u8_1]: call function\n+jal $$reta $pc i91 ; [call: array_repeat_zero_small_u8_1]: call function\n addi $r0 $$locbase i8 ; get offset to local __ptr [u64; 5]\n move $$arg0 $r0 ; [call: array_repeat_zero_small_u16_2]: pass argument 0\n-jal $$reta $pc i95 ; [call: array_repeat_zero_small_u16_2]: call function\n+jal $$reta $pc i92 ; [call: array_repeat_zero_small_u16_2]: call function\n addi $r0 $$locbase i48 ; get offset to local __ptr [u64; 5]\n move $$arg0 $r0 ; [call: array_repeat_zero_small_u16_2]: pass argument 0\n-jal $$reta $pc i92 ; [call: array_repeat_zero_small_u16_2]: call function\n+jal $$reta $pc i89 ; [call: array_repeat_zero_small_u16_2]: call function\n movi $r0 i32989 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_small_u16_2]: pass argument 0\n-jal $$reta $pc i87 ; [call: array_repeat_zero_small_u16_2]: call function\n+jal $$reta $pc i84 ; [call: array_repeat_zero_small_u16_2]: call function\n movi $r0 i32994 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_small_u256_5]: pass argument 0\n-jal $$reta $pc i86 ; [call: array_repeat_zero_small_u256_5]: call function\n+jal $$reta $pc i83 ; [call: array_repeat_zero_small_u256_5]: call function\n movi $r0 i33014 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_small_b256_6]: pass argument 0\n-jal $$reta $pc i85 ; [call: array_repeat_zero_small_b256_6]: call function\n+jal $$reta $pc i82 ; [call: array_repeat_zero_small_b256_6]: call function\n movi $r0 i33034 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_small_bool_7]: pass argument 0\n-jal $$reta $pc i84 ; [call: array_repeat_zero_small_bool_7]: call function\n+jal $$reta $pc i81 ; [call: array_repeat_zero_small_bool_7]: call function\n movi $r0 i33035 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_big_u8_8]: pass argument 0\n-jal $$reta $pc i83 ; [call: array_repeat_zero_big_u8_8]: call function\n+jal $$reta $pc i80 ; [call: array_repeat_zero_big_u8_8]: call function\n movi $r0 i33039 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_big_u32_10]: pass argument 0\n-jal $$reta $pc i82 ; [call: array_repeat_zero_big_u32_10]: call function\n+jal $$reta $pc i79 ; [call: array_repeat_zero_big_u32_10]: call function\n movi $r0 i33064 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_big_u32_10]: pass argument 0\n-jal $$reta $pc i77 ; [call: array_repeat_zero_big_u32_10]: call function\n+jal $$reta $pc i74 ; [call: array_repeat_zero_big_u32_10]: call function\n movi $r0 i33089 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: array_repeat_zero_big_u32_10]: pass argument 0\n-jal $$reta $pc i72 ; [call: array_repeat_zero_big_u32_10]: call function\n+jal $$reta $pc i69 ; [call: array_repeat_zero_big_u32_10]: call function\n addi $r0 $$locbase i88 ; get offset to local __ptr [u256; 25]\n move $$arg0 $r0 ; [call: array_repeat_zero_big_u256_12]: pass argument 0\n-jal $$reta $pc i73 ; [call: array_repeat_zero_big_u256_12]: call function\n+jal $$reta $pc i70 ; [call: array_repeat_zero_big_u256_12]: call function\n addi $r0 $$locbase i888 ; get offset to local __ptr [b256; 25]\n move $$arg0 $r0 ; [call: array_repeat_zero_big_b256_13]: pass argument 0\n-jal $$reta $pc i74 ; [call: array_repeat_zero_big_b256_13]: call function\n+jal $$reta $pc i71 ; [call: array_repeat_zero_big_b256_13]: call function\n addi $r0 $$locbase i1688 ; get offset to local __ptr [bool; 25]\n move $$arg0 $r0 ; [call: array_repeat_zero_big_bool_14]: pass argument 0\n-jal $$reta $pc i75 ; [call: array_repeat_zero_big_bool_14]: call function\n+jal $$reta $pc i72 ; [call: array_repeat_zero_big_bool_14]: call function\n addi $r0 $$locbase i1720 ; get offset to local __ptr [bool; 5]\n move $$arg0 $r0 ; [call: small_array_repeat_15]: pass argument 0\n-jal $$reta $pc i76 ; [call: small_array_repeat_15]: call function\n+jal $$reta $pc i73 ; [call: small_array_repeat_15]: call function\n addi $r0 $$locbase i1728 ; get offset to local __ptr [bool; 25]\n move $$arg0 $r0 ; [call: big_array_repeat_16]: pass argument 0\n-jal $$reta $pc i96 ; [call: big_array_repeat_16]: call function\n+jal $$reta $pc i84 ; [call: big_array_repeat_16]: call function\n addi $r0 $$locbase i1760 ; get offset to local __ptr [u8; 262145]\n move $$arg0 $r0 ; [call: u8_array_bigger_than_18_bits_17]: pass argument 0\n-jal $$reta $pc i106 ; [call: u8_array_bigger_than_18_bits_17]: call function\n-jal $$reta $pc i110 ; [call: arrays_with_const_length_18]: call function\n+jal $$reta $pc i93 ; [call: u8_array_bigger_than_18_bits_17]: call function\n+jal $$reta $pc i97 ; [call: arrays_with_const_length_18]: call function\n movi $r0 i33114 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n move $$arg0 $r0 ; [call: decode_array_19]: pass argument 0\n-jal $$reta $pc i108 ; [call: decode_array_19]: call function\n+jal $$reta $pc i95 ; [call: decode_array_19]: call function\n movi $r0 i33114 ; get word offset to local from base\n muli $r0 $r0 i8 ; get byte offset to local from base\n add $r0 $$locbase $r0 ; get absolute byte offset to local\n-mul $r2 $zero $one ; get offset to array element\n-add $r2 $r0 $r2 ; add array element offset to array base\n-lb $r0 $r2 i0 ; load byte\n+lb $r0 $r0 i0 ; load byte\n movi $r2 i255 ; initialize constant into register\n eq $r2 $r0 $r2\n eq $r2 $r2 $zero\n jnzf $r2 $zero i1\n-jmpf $zero i7\n+jmpf $zero i6\n move $$arg0 $r0 ; [call: log_46]: pass argument 0\n-jal $$reta $pc i151 ; [call: log_46]: call function\n-movi $r0 i255 ; initialize constant into register\n-move $$arg0 $r0 ; [call: log_46]: pass argument 0\n-jal $$reta $pc i148 ; [call: log_46]: call function\n+jal $$reta $pc i134 ; [call: log_46]: call function\n+movi $$arg0 i255 ; [call: log_46]: pass argument 0\n+jal $$reta $pc i132 ; [call: log_46]: call function\n load $r0 data_NonConfigurable_0; load constant from data section\n rvrt $r0\n cfsi i264920 ; [fn end: main_0] free: locals 264920 byte(s), call args 0 slot(s)\n@@ -660,37 +657,27 @@ poph i524288 ; [fn end: array_repeat_zero_big_bool_14]: restore\n jal $zero $$reta i0 ; [fn end: array_repeat_zero_big_bool_14] return from call\n pshl i1 ; [fn init: small_array_repeat_15]: push used low registers 16..40\n pshh i524288 ; [fn init: small_array_repeat_15]: push used high registers 40..64\n-mul $r0 $zero $one ; get offset to array element\n-add $r0 $$arg0 $r0 ; add array element offset to array base\n-sb $r0 $one i0 ; store byte\n-mul $r0 $one $one ; get offset to array element\n-add $r0 $$arg0 $r0 ; add array element offset to array base\n+sb $$arg0 $one i0 ; store byte\n+addi $r0 $$arg0 i1 ; add array element offset to array base\n sb $r0 $one i0 ; store byte\n-movi $r0 i2 ; initialize constant into register\n-mul $r0 $r0 $one ; get offset to array element\n-add $r0 $$arg0 $r0 ; add array element offset to array base\n+addi $r0 $$arg0 i2 ; add array element offset to array base\n sb $r0 $one i0 ; store byte\n-movi $r0 i3 ; initialize constant into register\n-mul $r0 $r0 $one ; get offset to array element\n-add $r0 $$arg0 $r0 ; add array element offset to array base\n+addi $r0 $$arg0 i3 ; add array element offset to array base\n sb $r0 $one i0 ; store byte\n-movi $r0 i4 ; initialize constant into register\n-mul $r0 $r0 $one ; get offset to array element\n-add $r0 $$arg0 $r0 ; add array element offset to array base\n+addi $r0 $$arg0 i4 ; add array element offset to array base\n sb $r0 $one i0 ; store byte\n poph i524288 ; [fn end: small_array_repeat_15]: restore used high registers 40..64\n popl i1 ; [fn end: small_array_repeat_15]: restore used low registers 16..40\n jal $zero $$reta i0 ; [fn end: small_array_repeat_15] return from call\n pshl i3 ; [fn init: big_array_repeat_16]: push used low registers 16..40\n pshh i524288 ; [fn init: big_array_repeat_16]: push used high registers 40..64\n-move $r1 $zero ; move parameter from branch to block argument\n-mul $r0 $r1 $one ; get offset to array element\n-add $r0 $$arg0 $r0 ; add array element offset to array base\n+movi $r1 i0 ; move parameter from branch to block argument\n+add $r0 $$arg0 $r1 ; add array element offset to array base\n sb $r0 $one i0 ; store byte\n-add $r1 $r1 $one\n+addi $r1 $r1 i1\n movi $r0 i25 ; initialize constant into register\n lt $r0 $r1 $r0\n-jnzb $r0 $zero i5\n+jnzb $r0 $zero i4\n poph i524288 ; [fn end: big_array_repeat_16]: restore used high registers 40..64\n popl i3 ; [fn end: big_array_repeat_16]: restore used low registers 16..40\n jal $zero $$reta i0 ; [fn end: big_array_repeat_16] return from call\n@@ -709,15 +696,13 @@ cfei i72 ; [fn init: decode_array_19]: allocate: locals 72\n move $r2 $$arg0 ; [fn init: decode_array_19]: copy argument 0 (__ret_value)\n move $r3 $$reta ; [fn init: decode_array_19]: save return address\n addi $r0 $$locbase i16 ; get offset to local __ptr [u8; 1]\n-mul $r1 $zero $one ; get offset to array element\n-add $r1 $r0 $r1 ; add array element offset to array base\n-movi $r0 i255 ; initialize constant into register\n-sb $r1 $r0 i0 ; store byte\n+movi $r1 i255 ; initialize constant into register\n+sb $r0 $r1 i0 ; store byte\n addi $r0 $$locbase i16 ; get offset to local __ptr [u8; 1]\n addi $r1 $$locbase i24 ; get offset to local __ptr slice\n move $$arg0 $r0 ; [call: to_slice_20]: pass argument 0\n move $$arg1 $r1 ; [call: to_slice_20]: pass argument 1\n-jal $$reta $pc i25 ; [call: to_slice_20]: call function\n+jal $$reta $pc i21 ; [call: to_slice_20]: call function\n addi $r0 $$locbase i40 ; get offset to local __ptr slice\n mcpi $r0 $r1 i16 ; copy memory\n addi $r0 $$locbase i40 ; get offset to local __ptr slice\n@@ -728,15 +713,11 @@ lw $r1 $$locbase i8 ; load word\n sw $$locbase $r0 i0 ; store word\n sw $$locbase $r1 i1 ; store word\n lw $r0 $$locbase i0 ; load word\n-move $r1 $one ; copy ASM block argument's constant initial value to register\n+movi $r1 i1 ; copy ASM block argument's constant initial value to register\n aloc $one ; aloc size\n mcp $hp $r0 $r1 ; mcp hp src size\n-mul $r0 $zero $one ; get offset to array element\n-add $r0 $hp $r0 ; add array element offset to array base\n-lb $r0 $r0 i0 ; load byte\n-mul $r1 $zero $one ; get offset to array element\n-add $r1 $r2 $r1 ; add array element offset to array base\n-sb $r1 $r0 i0 ; store byte\n+lb $r0 $hp i0 ; load byte\n+sb $r2 $r0 i0 ; store byte\n cfsi i72 ; [fn end: decode_array_19] free: locals 72 byte(s), call args 0 slot(s)\n move $$reta $r3 ; [fn end: decode_array_19] restore return address\n poph i524288 ; [fn end: decode_array_19]: restore used high registers 40..64\n@@ -787,7 +768,7 @@ data_NonConfigurable_2 .word 14454674236531057292\n \n 0x00000000 MOVE R60 $pc ;; [26, 240, 48, 0]\n 0x00000004 JMPF $zero 0x4 ;; [116, 0, 0, 4]\n-0x00000008 ;; [0, 0, 0, 0, 0, 0, 4, 56]\n+0x00000008 ;; [0, 0, 0, 0, 0, 0, 3, 240]\n 0x00000010 ;; [0, 0, 0, 0, 0, 0, 0, 0]\n 0x00000018 LW R63 R60 0x1 ;; [93, 255, 192, 1]\n 0x0000001c ADD R63 R63 R60 ;; [16, 255, 255, 0]\n@@ -800,263 +781,245 @@ data_NonConfigurable_2 .word 14454674236531057292\n 0x00000038 CFEI 0x40ad8 ;; [145, 4, 10, 216]\n 0x0000003c MOVE R17 R62 ;; [26, 71, 224, 0]\n 0x00000040 MOVE R58 R59 ;; [26, 235, 176, 0]\n-0x00000044 JAL R62 $pc 0x5e ;; [153, 248, 48, 94]\n+0x00000044 JAL R62 $pc 0x5b ;; [153, 248, 48, 91]\n 0x00000048 ADDI $writable R59 0x8 ;; [80, 67, 176, 8]\n 0x0000004c MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000050 JAL R62 $pc 0x5f ;; [153, 248, 48, 95]\n+0x00000050 JAL R62 $pc 0x5c ;; [153, 248, 48, 92]\n 0x00000054 ADDI $writable R59 0x30 ;; [80, 67, 176, 48]\n 0x00000058 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x0000005c JAL R62 $pc 0x5c ;; [153, 248, 48, 92]\n+0x0000005c JAL R62 $pc 0x59 ;; [153, 248, 48, 89]\n 0x00000060 MOVI $writable 0x80dd ;; [114, 64, 128, 221]\n 0x00000064 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x00000068 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x0000006c MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000070 JAL R62 $pc 0x57 ;; [153, 248, 48, 87]\n+0x00000070 JAL R62 $pc 0x54 ;; [153, 248, 48, 84]\n 0x00000074 MOVI $writable 0x80e2 ;; [114, 64, 128, 226]\n 0x00000078 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x0000007c ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x00000080 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000084 JAL R62 $pc 0x56 ;; [153, 248, 48, 86]\n+0x00000084 JAL R62 $pc 0x53 ;; [153, 248, 48, 83]\n 0x00000088 MOVI $writable 0x80f6 ;; [114, 64, 128, 246]\n 0x0000008c MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x00000090 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x00000094 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000098 JAL R62 $pc 0x55 ;; [153, 248, 48, 85]\n+0x00000098 JAL R62 $pc 0x52 ;; [153, 248, 48, 82]\n 0x0000009c MOVI $writable 0x810a ;; [114, 64, 129, 10]\n 0x000000a0 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x000000a4 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x000000a8 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x000000ac JAL R62 $pc 0x54 ;; [153, 248, 48, 84]\n+0x000000ac JAL R62 $pc 0x51 ;; [153, 248, 48, 81]\n 0x000000b0 MOVI $writable 0x810b ;; [114, 64, 129, 11]\n 0x000000b4 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x000000b8 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x000000bc MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x000000c0 JAL R62 $pc 0x53 ;; [153, 248, 48, 83]\n+0x000000c0 JAL R62 $pc 0x50 ;; [153, 248, 48, 80]\n 0x000000c4 MOVI $writable 0x810f ;; [114, 64, 129, 15]\n 0x000000c8 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x000000cc ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x000000d0 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x000000d4 JAL R62 $pc 0x52 ;; [153, 248, 48, 82]\n+0x000000d4 JAL R62 $pc 0x4f ;; [153, 248, 48, 79]\n 0x000000d8 MOVI $writable 0x8128 ;; [114, 64, 129, 40]\n 0x000000dc MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x000000e0 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x000000e4 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x000000e8 JAL R62 $pc 0x4d ;; [153, 248, 48, 77]\n+0x000000e8 JAL R62 $pc 0x4a ;; [153, 248, 48, 74]\n 0x000000ec MOVI $writable 0x8141 ;; [114, 64, 129, 65]\n 0x000000f0 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x000000f4 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x000000f8 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x000000fc JAL R62 $pc 0x48 ;; [153, 248, 48, 72]\n+0x000000fc JAL R62 $pc 0x45 ;; [153, 248, 48, 69]\n 0x00000100 ADDI $writable R59 0x58 ;; [80, 67, 176, 88]\n 0x00000104 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000108 JAL R62 $pc 0x49 ;; [153, 248, 48, 73]\n+0x00000108 JAL R62 $pc 0x46 ;; [153, 248, 48, 70]\n 0x0000010c ADDI $writable R59 0x378 ;; [80, 67, 179, 120]\n 0x00000110 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000114 JAL R62 $pc 0x4a ;; [153, 248, 48, 74]\n+0x00000114 JAL R62 $pc 0x47 ;; [153, 248, 48, 71]\n 0x00000118 ADDI $writable R59 0x698 ;; [80, 67, 182, 152]\n 0x0000011c MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000120 JAL R62 $pc 0x4b ;; [153, 248, 48, 75]\n+0x00000120 JAL R62 $pc 0x48 ;; [153, 248, 48, 72]\n 0x00000124 ADDI $writable R59 0x6b8 ;; [80, 67, 182, 184]\n 0x00000128 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x0000012c JAL R62 $pc 0x4c ;; [153, 248, 48, 76]\n+0x0000012c JAL R62 $pc 0x49 ;; [153, 248, 48, 73]\n 0x00000130 ADDI $writable R59 0x6c0 ;; [80, 67, 182, 192]\n 0x00000134 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000138 JAL R62 $pc 0x60 ;; [153, 248, 48, 96]\n+0x00000138 JAL R62 $pc 0x54 ;; [153, 248, 48, 84]\n 0x0000013c ADDI $writable R59 0x6e0 ;; [80, 67, 182, 224]\n 0x00000140 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000144 JAL R62 $pc 0x6a ;; [153, 248, 48, 106]\n-0x00000148 JAL R62 $pc 0x6e ;; [153, 248, 48, 110]\n+0x00000144 JAL R62 $pc 0x5d ;; [153, 248, 48, 93]\n+0x00000148 JAL R62 $pc 0x61 ;; [153, 248, 48, 97]\n 0x0000014c MOVI $writable 0x815a ;; [114, 64, 129, 90]\n 0x00000150 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x00000154 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n 0x00000158 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x0000015c JAL R62 $pc 0x6c ;; [153, 248, 48, 108]\n+0x0000015c JAL R62 $pc 0x5f ;; [153, 248, 48, 95]\n 0x00000160 MOVI $writable 0x815a ;; [114, 64, 129, 90]\n 0x00000164 MULI $writable $writable 0x8 ;; [85, 65, 0, 8]\n 0x00000168 ADD $writable R59 $writable ;; [16, 67, 180, 0]\n-0x0000016c MUL R18 $zero $one ;; [27, 72, 0, 64]\n-0x00000170 ADD R18 $writable R18 ;; [16, 73, 4, 128]\n-0x00000174 LB $writable R18 0x0 ;; [92, 65, 32, 0]\n-0x00000178 MOVI R18 0xff ;; [114, 72, 0, 255]\n-0x0000017c EQ R18 $writable R18 ;; [19, 73, 4, 128]\n-0x00000180 EQ R18 R18 $zero ;; [19, 73, 32, 0]\n-0x00000184 JNZF R18 $zero 0x1 ;; [118, 72, 0, 1]\n-0x00000188 JMPF $zero 0x7 ;; [116, 0, 0, 7]\n-0x0000018c MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000190 JAL R62 $pc 0x97 ;; [153, 248, 48, 151]\n-0x00000194 MOVI $writable 0xff ;; [114, 64, 0, 255]\n-0x00000198 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x0000019c JAL R62 $pc 0x94 ;; [153, 248, 48, 148]\n-0x000001a0 LW $writable R63 0x0 ;; [93, 67, 240, 0]\n-0x000001a4 RVRT $writable ;; [54, 64, 0, 0]\n-0x000001a8 CFSI 0x40ad8 ;; [146, 4, 10, 216]\n-0x000001ac MOVE R62 R17 ;; [26, 249, 16, 0]\n-0x000001b0 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000001b4 POPL 0x7 ;; [151, 0, 0, 7]\n-0x000001b8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000001bc PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000001c0 MCLI R58 0x5 ;; [112, 232, 0, 5]\n-0x000001c4 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000001c8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000001cc PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000001d0 MCLI R58 0x28 ;; [112, 232, 0, 40]\n-0x000001d4 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000001d8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000001dc PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000001e0 MCLI R58 0xa0 ;; [112, 232, 0, 160]\n-0x000001e4 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000001e8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000001ec PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000001f0 MCLI R58 0xa0 ;; [112, 232, 0, 160]\n-0x000001f4 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000001f8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000001fc PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000200 MCLI R58 0x5 ;; [112, 232, 0, 5]\n-0x00000204 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000208 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x0000020c PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000210 MCLI R58 0x19 ;; [112, 232, 0, 25]\n-0x00000214 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000218 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x0000021c PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000220 MCLI R58 0xc8 ;; [112, 232, 0, 200]\n-0x00000224 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000228 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x0000022c PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000230 MCLI R58 0x320 ;; [112, 232, 3, 32]\n-0x00000234 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000238 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x0000023c PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000240 MCLI R58 0x320 ;; [112, 232, 3, 32]\n-0x00000244 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000248 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x0000024c PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000250 MCLI R58 0x19 ;; [112, 232, 0, 25]\n-0x00000254 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000258 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x0000025c PSHL 0x1 ;; [149, 0, 0, 1]\n-0x00000260 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000264 MUL $writable $zero $one ;; [27, 64, 0, 64]\n-0x00000268 ADD $writable R58 $writable ;; [16, 67, 164, 0]\n-0x0000026c SB $writable $one 0x0 ;; [94, 64, 16, 0]\n-0x00000270 MUL $writable $one $one ;; [27, 64, 16, 64]\n-0x00000274 ADD $writable R58 $writable ;; [16, 67, 164, 0]\n+0x0000016c LB $writable $writable 0x0 ;; [92, 65, 0, 0]\n+0x00000170 MOVI R18 0xff ;; [114, 72, 0, 255]\n+0x00000174 EQ R18 $writable R18 ;; [19, 73, 4, 128]\n+0x00000178 EQ R18 R18 $zero ;; [19, 73, 32, 0]\n+0x0000017c JNZF R18 $zero 0x1 ;; [118, 72, 0, 1]\n+0x00000180 JMPF $zero 0x6 ;; [116, 0, 0, 6]\n+0x00000184 MOVE R58 $writable ;; [26, 233, 0, 0]\n+0x00000188 JAL R62 $pc 0x86 ;; [153, 248, 48, 134]\n+0x0000018c MOVI R58 0xff ;; [114, 232, 0, 255]\n+0x00000190 JAL R62 $pc 0x84 ;; [153, 248, 48, 132]\n+0x00000194 LW $writable R63 0x0 ;; [93, 67, 240, 0]\n+0x00000198 RVRT $writable ;; [54, 64, 0, 0]\n+0x0000019c CFSI 0x40ad8 ;; [146, 4, 10, 216]\n+0x000001a0 MOVE R62 R17 ;; [26, 249, 16, 0]\n+0x000001a4 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000001a8 POPL 0x7 ;; [151, 0, 0, 7]\n+0x000001ac JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000001b0 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000001b4 MCLI R58 0x5 ;; [112, 232, 0, 5]\n+0x000001b8 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000001bc JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000001c0 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000001c4 MCLI R58 0x28 ;; [112, 232, 0, 40]\n+0x000001c8 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000001cc JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000001d0 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000001d4 MCLI R58 0xa0 ;; [112, 232, 0, 160]\n+0x000001d8 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000001dc JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000001e0 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000001e4 MCLI R58 0xa0 ;; [112, 232, 0, 160]\n+0x000001e8 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000001ec JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000001f0 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000001f4 MCLI R58 0x5 ;; [112, 232, 0, 5]\n+0x000001f8 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000001fc JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000200 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000204 MCLI R58 0x19 ;; [112, 232, 0, 25]\n+0x00000208 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x0000020c JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000210 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000214 MCLI R58 0xc8 ;; [112, 232, 0, 200]\n+0x00000218 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x0000021c JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000220 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000224 MCLI R58 0x320 ;; [112, 232, 3, 32]\n+0x00000228 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x0000022c JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000230 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000234 MCLI R58 0x320 ;; [112, 232, 3, 32]\n+0x00000238 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x0000023c JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000240 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000244 MCLI R58 0x19 ;; [112, 232, 0, 25]\n+0x00000248 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x0000024c JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000250 PSHL 0x1 ;; [149, 0, 0, 1]\n+0x00000254 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000258 SB R58 $one 0x0 ;; [94, 232, 16, 0]\n+0x0000025c ADDI $writable R58 0x1 ;; [80, 67, 160, 1]\n+0x00000260 SB $writable $one 0x0 ;; [94, 64, 16, 0]\n+0x00000264 ADDI $writable R58 0x2 ;; [80, 67, 160, 2]\n+0x00000268 SB $writable $one 0x0 ;; [94, 64, 16, 0]\n+0x0000026c ADDI $writable R58 0x3 ;; [80, 67, 160, 3]\n+0x00000270 SB $writable $one 0x0 ;; [94, 64, 16, 0]\n+0x00000274 ADDI $writable R58 0x4 ;; [80, 67, 160, 4]\n 0x00000278 SB $writable $one 0x0 ;; [94, 64, 16, 0]\n-0x0000027c MOVI $writable 0x2 ;; [114, 64, 0, 2]\n-0x00000280 MUL $writable $writable $one ;; [27, 65, 0, 64]\n-0x00000284 ADD $writable R58 $writable ;; [16, 67, 164, 0]\n-0x00000288 SB $writable $one 0x0 ;; [94, 64, 16, 0]\n-0x0000028c MOVI $writable 0x3 ;; [114, 64, 0, 3]\n-0x00000290 MUL $writable $writable $one ;; [27, 65, 0, 64]\n-0x00000294 ADD $writable R58 $writable ;; [16, 67, 164, 0]\n+0x0000027c POPH 0x80000 ;; [152, 8, 0, 0]\n+0x00000280 POPL 0x1 ;; [151, 0, 0, 1]\n+0x00000284 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000288 PSHL 0x3 ;; [149, 0, 0, 3]\n+0x0000028c PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000290 MOVI R17 0x0 ;; [114, 68, 0, 0]\n+0x00000294 ADD $writable R58 R17 ;; [16, 67, 164, 64]\n 0x00000298 SB $writable $one 0x0 ;; [94, 64, 16, 0]\n-0x0000029c MOVI $writable 0x4 ;; [114, 64, 0, 4]\n-0x000002a0 MUL $writable $writable $one ;; [27, 65, 0, 64]\n-0x000002a4 ADD $writable R58 $writable ;; [16, 67, 164, 0]\n-0x000002a8 SB $writable $one 0x0 ;; [94, 64, 16, 0]\n+0x0000029c ADDI R17 R17 0x1 ;; [80, 69, 16, 1]\n+0x000002a0 MOVI $writable 0x19 ;; [114, 64, 0, 25]\n+0x000002a4 LT $writable R17 $writable ;; [22, 65, 20, 0]\n+0x000002a8 JNZB $writable $zero 0x4 ;; [119, 64, 0, 4]\n 0x000002ac POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000002b0 POPL 0x1 ;; [151, 0, 0, 1]\n+0x000002b0 POPL 0x3 ;; [151, 0, 0, 3]\n 0x000002b4 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000002b8 PSHL 0x3 ;; [149, 0, 0, 3]\n-0x000002bc PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000002c0 MOVE R17 $zero ;; [26, 68, 0, 0]\n-0x000002c4 MUL $writable R17 $one ;; [27, 65, 16, 64]\n-0x000002c8 ADD $writable R58 $writable ;; [16, 67, 164, 0]\n-0x000002cc SB $writable $one 0x0 ;; [94, 64, 16, 0]\n-0x000002d0 ADD R17 R17 $one ;; [16, 69, 16, 64]\n-0x000002d4 MOVI $writable 0x19 ;; [114, 64, 0, 25]\n-0x000002d8 LT $writable R17 $writable ;; [22, 65, 20, 0]\n-0x000002dc JNZB $writable $zero 0x5 ;; [119, 64, 0, 5]\n-0x000002e0 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000002e4 POPL 0x3 ;; [151, 0, 0, 3]\n-0x000002e8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000002ec PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000002f0 LW R60 R63 0x1 ;; [93, 243, 240, 1]\n-0x000002f4 MCL R58 R60 ;; [39, 235, 192, 0]\n-0x000002f8 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000002fc JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x00000300 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000304 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000308 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x0000030c PSHL 0xf ;; [149, 0, 0, 15]\n-0x00000310 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x00000314 MOVE R59 $sp ;; [26, 236, 80, 0]\n-0x00000318 CFEI 0x48 ;; [145, 0, 0, 72]\n-0x0000031c MOVE R18 R58 ;; [26, 75, 160, 0]\n-0x00000320 MOVE R19 R62 ;; [26, 79, 224, 0]\n-0x00000324 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n-0x00000328 MUL R17 $zero $one ;; [27, 68, 0, 64]\n-0x0000032c ADD R17 $writable R17 ;; [16, 69, 4, 64]\n-0x00000330 MOVI $writable 0xff ;; [114, 64, 0, 255]\n-0x00000334 SB R17 $writable 0x0 ;; [94, 69, 0, 0]\n-0x00000338 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n-0x0000033c ADDI R17 R59 0x18 ;; [80, 71, 176, 24]\n-0x00000340 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000344 MOVE R57 R17 ;; [26, 229, 16, 0]\n-0x00000348 JAL R62 $pc 0x19 ;; [153, 248, 48, 25]\n-0x0000034c ADDI $writable R59 0x28 ;; [80, 67, 176, 40]\n-0x00000350 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n-0x00000354 ADDI $writable R59 0x28 ;; [80, 67, 176, 40]\n-0x00000358 ADDI R17 R59 0x38 ;; [80, 71, 176, 56]\n-0x0000035c MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x00000360 LW $writable R59 0x7 ;; [93, 67, 176, 7]\n-0x00000364 LW R17 R59 0x8 ;; [93, 71, 176, 8]\n-0x00000368 SW R59 $writable 0x0 ;; [95, 237, 0, 0]\n-0x0000036c SW R59 R17 0x1 ;; [95, 237, 16, 1]\n-0x00000370 LW $writable R59 0x0 ;; [93, 67, 176, 0]\n-0x00000374 MOVE R17 $one ;; [26, 68, 16, 0]\n-0x00000378 ALOC $one ;; [38, 4, 0, 0]\n-0x0000037c MCP $hp $writable R17 ;; [40, 29, 4, 64]\n-0x00000380 MUL $writable $zero $one ;; [27, 64, 0, 64]\n-0x00000384 ADD $writable $hp $writable ;; [16, 64, 116, 0]\n-0x00000388 LB $writable $writable 0x0 ;; [92, 65, 0, 0]\n-0x0000038c MUL R17 $zero $one ;; [27, 68, 0, 64]\n-0x00000390 ADD R17 R18 R17 ;; [16, 69, 36, 64]\n-0x00000394 SB R17 $writable 0x0 ;; [94, 69, 0, 0]\n-0x00000398 CFSI 0x48 ;; [146, 0, 0, 72]\n-0x0000039c MOVE R62 R19 ;; [26, 249, 48, 0]\n-0x000003a0 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000003a4 POPL 0xf ;; [151, 0, 0, 15]\n-0x000003a8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000003ac PSHL 0x1 ;; [149, 0, 0, 1]\n-0x000003b0 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000003b4 MOVE R59 $sp ;; [26, 236, 80, 0]\n-0x000003b8 CFEI 0x28 ;; [145, 0, 0, 40]\n-0x000003bc ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n-0x000003c0 MCPI $writable R58 0x1 ;; [96, 67, 160, 1]\n+0x000002b8 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000002bc LW R60 R63 0x1 ;; [93, 243, 240, 1]\n+0x000002c0 MCL R58 R60 ;; [39, 235, 192, 0]\n+0x000002c4 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000002c8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000002cc PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000002d0 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000002d4 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000002d8 PSHL 0xf ;; [149, 0, 0, 15]\n+0x000002dc PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000002e0 MOVE R59 $sp ;; [26, 236, 80, 0]\n+0x000002e4 CFEI 0x48 ;; [145, 0, 0, 72]\n+0x000002e8 MOVE R18 R58 ;; [26, 75, 160, 0]\n+0x000002ec MOVE R19 R62 ;; [26, 79, 224, 0]\n+0x000002f0 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n+0x000002f4 MOVI R17 0xff ;; [114, 68, 0, 255]\n+0x000002f8 SB $writable R17 0x0 ;; [94, 65, 16, 0]\n+0x000002fc ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n+0x00000300 ADDI R17 R59 0x18 ;; [80, 71, 176, 24]\n+0x00000304 MOVE R58 $writable ;; [26, 233, 0, 0]\n+0x00000308 MOVE R57 R17 ;; [26, 229, 16, 0]\n+0x0000030c JAL R62 $pc 0x15 ;; [153, 248, 48, 21]\n+0x00000310 ADDI $writable R59 0x28 ;; [80, 67, 176, 40]\n+0x00000314 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n+0x00000318 ADDI $writable R59 0x28 ;; [80, 67, 176, 40]\n+0x0000031c ADDI R17 R59 0x38 ;; [80, 71, 176, 56]\n+0x00000320 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x00000324 LW $writable R59 0x7 ;; [93, 67, 176, 7]\n+0x00000328 LW R17 R59 0x8 ;; [93, 71, 176, 8]\n+0x0000032c SW R59 $writable 0x0 ;; [95, 237, 0, 0]\n+0x00000330 SW R59 R17 0x1 ;; [95, 237, 16, 1]\n+0x00000334 LW $writable R59 0x0 ;; [93, 67, 176, 0]\n+0x00000338 MOVI R17 0x1 ;; [114, 68, 0, 1]\n+0x0000033c ALOC $one ;; [38, 4, 0, 0]\n+0x00000340 MCP $hp $writable R17 ;; [40, 29, 4, 64]\n+0x00000344 LB $writable $hp 0x0 ;; [92, 64, 112, 0]\n+0x00000348 SB R18 $writable 0x0 ;; [94, 73, 0, 0]\n+0x0000034c CFSI 0x48 ;; [146, 0, 0, 72]\n+0x00000350 MOVE R62 R19 ;; [26, 249, 48, 0]\n+0x00000354 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x00000358 POPL 0xf ;; [151, 0, 0, 15]\n+0x0000035c JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x00000360 PSHL 0x1 ;; [149, 0, 0, 1]\n+0x00000364 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000368 MOVE R59 $sp ;; [26, 236, 80, 0]\n+0x0000036c CFEI 0x28 ;; [145, 0, 0, 40]\n+0x00000370 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n+0x00000374 MCPI $writable R58 0x1 ;; [96, 67, 160, 1]\n+0x00000378 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n+0x0000037c SW R59 $writable 0x3 ;; [95, 237, 0, 3]\n+0x00000380 SW R59 $one 0x4 ;; [95, 236, 16, 4]\n+0x00000384 ADDI $writable R59 0x18 ;; [80, 67, 176, 24]\n+0x00000388 MCPI R59 $writable 0x10 ;; [96, 237, 0, 16]\n+0x0000038c MCPI R57 R59 0x10 ;; [96, 231, 176, 16]\n+0x00000390 CFSI 0x28 ;; [146, 0, 0, 40]\n+0x00000394 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x00000398 POPL 0x1 ;; [151, 0, 0, 1]\n+0x0000039c JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000003a0 PSHL 0x7 ;; [149, 0, 0, 7]\n+0x000003a4 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000003a8 MOVE R59 $sp ;; [26, 236, 80, 0]\n+0x000003ac CFEI 0x28 ;; [145, 0, 0, 40]\n+0x000003b0 ADDI $writable R59 0x20 ;; [80, 67, 176, 32]\n+0x000003b4 SB $writable R58 0x0 ;; [94, 67, 160, 0]\n+0x000003b8 ADDI $writable R59 0x20 ;; [80, 67, 176, 32]\n+0x000003bc SW R59 $writable 0x0 ;; [95, 237, 0, 0]\n+0x000003c0 SW R59 $one 0x1 ;; [95, 236, 16, 1]\n 0x000003c4 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n-0x000003c8 SW R59 $writable 0x3 ;; [95, 237, 0, 3]\n-0x000003cc SW R59 $one 0x4 ;; [95, 236, 16, 4]\n-0x000003d0 ADDI $writable R59 0x18 ;; [80, 67, 176, 24]\n-0x000003d4 MCPI R59 $writable 0x10 ;; [96, 237, 0, 16]\n-0x000003d8 MCPI R57 R59 0x10 ;; [96, 231, 176, 16]\n+0x000003c8 MCPI $writable R59 0x10 ;; [96, 67, 176, 16]\n+0x000003cc LW $writable R63 0x2 ;; [93, 67, 240, 2]\n+0x000003d0 LW R17 R59 0x2 ;; [93, 71, 176, 2]\n+0x000003d4 LW R18 R59 0x3 ;; [93, 75, 176, 3]\n+0x000003d8 LOGD $zero $writable R17 R18 ;; [52, 1, 4, 82]\n 0x000003dc CFSI 0x28 ;; [146, 0, 0, 40]\n 0x000003e0 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000003e4 POPL 0x1 ;; [151, 0, 0, 1]\n+0x000003e4 POPL 0x7 ;; [151, 0, 0, 7]\n 0x000003e8 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000003ec PSHL 0x7 ;; [149, 0, 0, 7]\n-0x000003f0 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000003f4 MOVE R59 $sp ;; [26, 236, 80, 0]\n-0x000003f8 CFEI 0x28 ;; [145, 0, 0, 40]\n-0x000003fc ADDI $writable R59 0x20 ;; [80, 67, 176, 32]\n-0x00000400 SB $writable R58 0x0 ;; [94, 67, 160, 0]\n-0x00000404 ADDI $writable R59 0x20 ;; [80, 67, 176, 32]\n-0x00000408 SW R59 $writable 0x0 ;; [95, 237, 0, 0]\n-0x0000040c SW R59 $one 0x1 ;; [95, 236, 16, 1]\n-0x00000410 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n-0x00000414 MCPI $writable R59 0x10 ;; [96, 67, 176, 16]\n-0x00000418 LW $writable R63 0x2 ;; [93, 67, 240, 2]\n-0x0000041c LW R17 R59 0x2 ;; [93, 71, 176, 2]\n-0x00000420 LW R18 R59 0x3 ;; [93, 75, 176, 3]\n-0x00000424 LOGD $zero $writable R17 R18 ;; [52, 1, 4, 82]\n-0x00000428 CFSI 0x28 ;; [146, 0, 0, 40]\n-0x0000042c POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000430 POPL 0x7 ;; [151, 0, 0, 7]\n-0x00000434 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000003ec NOOP ;; [71, 0, 0, 0]\n .data_section:\n-0x00000438 .word i18446744073709486083, as hex be bytes ([FF, FF, FF, FF, FF, FF, 00, 03])\n-0x00000440 .word i262145, as hex be bytes ([00, 00, 00, 00, 00, 04, 00, 01])\n-0x00000448 .word i14454674236531057292, as hex be bytes ([C8, 99, 51, A2, 4C, 6C, A2, 8C])\n+0x000003f0 .word i18446744073709486083, as hex be bytes ([FF, FF, FF, FF, FF, FF, 00, 03])\n+0x000003f8 .word i262145, as hex be bytes ([00, 00, 00, 00, 00, 04, 00, 01])\n+0x00000400 .word i14454674236531057292, as hex be bytes ([C8, 99, 51, A2, 4C, 6C, A2, 8C])\n ;; --- END OF TARGET BYTECODE ---\n \n warning\n@@ -1156,7 +1119,7 @@ warning\n ____\n \n Compiled script \"array_repeat\" with 8 warnings.\n- Finished release [optimized + fuel] target(s) [1.104 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.032 KB] in ???\n \n > forc test --path test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat --verbose --release\n exit status: 0\n@@ -1164,15 +1127,15 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-assert)\n Compiling script array_repeat (test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat)\n- Finished release [optimized + fuel] target(s) [2.288 KB] in ???\n+ Finished release [optimized + fuel] target(s) [2.144 KB] in ???\n script array_repeat\n- Bytecode size: 2288 bytes (2.288 KB)\n- Bytecode hash: 0xe5a340658508bd113ab881f379d12c5f90c3ae523d9ed90a11444c58a669baff\n+ Bytecode size: 2144 bytes (2.144 KB)\n+ Bytecode hash: 0xabd375e17dfb789d46e484affebec14ba4b174616abc3f2034be7b0554350ae4\n Running 1 test, filtered 0 tests\n \n tested -- array_repeat\n \n- test test_array_repeat_zero ... ok (???, 6299319 gas)\n+ test test_array_repeat_zero ... ok (???, 5774597 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/asm/asm_patch/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/asm/asm_patch/stdout.snap\nindex c44e209fd20..550244eb20e 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/asm/asm_patch/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/asm/asm_patch/stdout.snap\n@@ -32,16 +32,16 @@ output:\n 15 60 LW { dst: 0x10, addr: 0x3b, offset: 1 } 5d 43 b0 01 \n 16 64 LW { dst: 0x11, addr: 0x3b, offset: 2 } 5d 47 b0 02 \n 17 68 RETD { addr: 0x10, len: 0x11 } 25 41 10 00 \n- 18 72 PSHL { bitmask: 3 } 95 00 00 03 \n+ 18 72 PSHL { bitmask: 1 } 95 00 00 01 \n 19 76 PSHH { bitmask: 524288 } 96 08 00 00 \n- 20 80 MOVE { dst: 0x11, src: 0x0 } 1a 44 00 00 \n- 21 84 ADDI { dst: 0x10, lhs: 0x0, rhs: 3 } 50 40 00 03 \n- 22 88 LOG { a: 0x11, b: 0x11, c: 0x11, d: 0x0 } 33 45 14 40 \n- 23 92 ADDI { dst: 0x10, lhs: 0x10, rhs: 5 } 50 41 00 05 \n- 24 96 MOVE { dst: 0x3d, src: 0x10 } 1a f5 00 00 \n- 25 100 POPH { bitmask: 524288 } 98 08 00 00 \n- 26 104 POPL { bitmask: 3 } 97 00 00 03 \n- 27 108 JAL { ret_addr: 0x0, target: 0x3e, offset: 0 } 99 03 e0 00 \n+ 20 80 ADDI { dst: 0x10, lhs: 0x0, rhs: 3 } 50 40 00 03 \n+ 21 84 LOG { a: 0x0, b: 0x0, c: 0x0, d: 0x0 } 33 00 00 00 \n+ 22 88 ADDI { dst: 0x10, lhs: 0x10, rhs: 5 } 50 41 00 05 \n+ 23 92 MOVE { dst: 0x3d, src: 0x10 } 1a f5 00 00 \n+ 24 96 POPH { bitmask: 524288 } 98 08 00 00 \n+ 25 100 POPL { bitmask: 1 } 97 00 00 01 \n+ 26 104 JAL { ret_addr: 0x0, target: 0x3e, offset: 0 } 99 03 e0 00 \n+ 27 108 NOOP 47 00 00 00 \n \n \n \n@@ -70,21 +70,21 @@ output:\n 15 60 LW { dst: 0x10, addr: 0x3b, offset: 1 } 5d 43 b0 01 \n 16 64 LW { dst: 0x11, addr: 0x3b, offset: 2 } 5d 47 b0 02 \n 17 68 RETD { addr: 0x10, len: 0x11 } 25 41 10 00 \n- 18 72 PSHL { bitmask: 3 } 95 00 00 03 \n+ 18 72 PSHL { bitmask: 1 } 95 00 00 01 \n 19 76 PSHH { bitmask: 524288 } 96 08 00 00 \n- 20 80 MOVE { dst: 0x11, src: 0x0 } 1a 44 00 00 \n- 21 84 ADDI { dst: 0x10, lhs: 0x0, rhs: 3 } 50 40 00 03 \n- 22 88 ADDI { dst: 0x10, lhs: 0x10, rhs: 4 } 50 41 00 04 \n- 23 92 ADDI { dst: 0x10, lhs: 0x10, rhs: 5 } 50 41 00 05 \n- 24 96 ADDI { dst: 0x10, lhs: 0x10, rhs: 4 } 50 41 00 04 \n- 25 100 POPH { bitmask: 524288 } 98 08 00 00 \n- 26 104 POPL { bitmask: 3 } 97 00 00 03 \n- 27 108 JAL { ret_addr: 0x0, target: 0x3e, offset: 0 } 99 03 e0 00 \n+ 20 80 ADDI { dst: 0x10, lhs: 0x0, rhs: 3 } 50 40 00 03 \n+ 21 84 ADDI { dst: 0x10, lhs: 0x10, rhs: 4 } 50 41 00 04 \n+ 22 88 ADDI { dst: 0x10, lhs: 0x10, rhs: 5 } 50 41 00 05 \n+ 23 92 ADDI { dst: 0x10, lhs: 0x10, rhs: 4 } 50 41 00 04 \n+ 24 96 POPH { bitmask: 524288 } 98 08 00 00 \n+ 25 100 POPL { bitmask: 1 } 97 00 00 01 \n+ 26 104 JAL { ret_addr: 0x0, target: 0x3e, offset: 0 } 99 03 e0 00 \n+ 27 108 NOOP 47 00 00 00 \n \n \n \n > fuel-vm run test/src/e2e_vm_tests/test_programs/should_pass/language/asm/asm_patch/out/debug/asm_patch.bin\n-Gas: 406\n+Gas: 404\n Logs:\n ReturnData {\n id: 0x0000000000000000000000000000000000000000000000000000000000000000,\n@@ -101,5 +101,5 @@ ReturnData {\n }\n ScriptResult {\n result: Success,\n- gas_used: 406,\n+ gas_used: 404,\n }\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_deprecated/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_deprecated/stdout.snap\nindex f83de9032c6..ce8b8ad9c2e 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_deprecated/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_deprecated/stdout.snap\n@@ -182,4 +182,4 @@ warning: Function is deprecated\n ____\n \n Compiled contract \"attributes_deprecated\" with 19 warnings.\n- Finished release [optimized + fuel] target(s) [384 B] in ???\n+ Finished release [optimized + fuel] target(s) [376 B] in ???\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_unknown/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_unknown/stdout.snap\nindex 5fc07eda42e..e3822201453 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_unknown/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_unknown/stdout.snap\n@@ -1,5 +1,5 @@\n ---\n-source: test/tests/tests.rs\n+source: test/src/snapshot/mod.rs\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_pass/language/attributes_unknown --release\n exit status: 0\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/configurable_consts/json_abi_oracle_new_encoding.release.json b/test/src/e2e_vm_tests/test_programs/should_pass/language/configurable_consts/json_abi_oracle_new_encoding.release.json\nindex 6ad3903331a..d0d2cb25fab 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/configurable_consts/json_abi_oracle_new_encoding.release.json\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/configurable_consts/json_abi_oracle_new_encoding.release.json\n@@ -63,97 +63,97 @@\n \"concreteTypeId\": \"b760f44fa5965c2474a3b471467a22c43185152129295af588b022ae50b50903\",\n \"indirect\": false,\n \"name\": \"BOOL\",\n- \"offset\": 4224\n+ \"offset\": 4120\n },\n {\n \"concreteTypeId\": \"c89951a24c6ca28c13fd1cfdc646b2b656d69e61a92b91023be7eb58eb914b6b\",\n \"indirect\": false,\n \"name\": \"U8\",\n- \"offset\": 4416\n+ \"offset\": 4312\n },\n {\n \"concreteTypeId\": \"c89951a24c6ca28c13fd1cfdc646b2b656d69e61a92b91023be7eb58eb914b6b\",\n \"indirect\": false,\n \"name\": \"ANOTHER_U8\",\n- \"offset\": 4152\n+ \"offset\": 4048\n },\n {\n \"concreteTypeId\": \"29881aad8730c5ab11d275376323d8e4ff4179aae8ccb6c13fe4902137e162ef\",\n \"indirect\": false,\n \"name\": \"U16\",\n- \"offset\": 4360\n+ \"offset\": 4256\n },\n {\n \"concreteTypeId\": \"d7649d428b9ff33d188ecbf38a7e4d8fd167fa01b2e10fe9a8f9308e52f1d7cc\",\n \"indirect\": false,\n \"name\": \"U32\",\n- \"offset\": 4400\n+ \"offset\": 4296\n },\n {\n \"concreteTypeId\": \"d7649d428b9ff33d188ecbf38a7e4d8fd167fa01b2e10fe9a8f9308e52f1d7cc\",\n \"indirect\": false,\n \"name\": \"U64\",\n- \"offset\": 4408\n+ \"offset\": 4304\n },\n {\n \"concreteTypeId\": \"1b5759d94094368cfd443019e7ca5ec4074300e544e5ea993a979f5da627261e\",\n \"indirect\": false,\n \"name\": \"U256\",\n- \"offset\": 4368\n+ \"offset\": 4264\n },\n {\n \"concreteTypeId\": \"7c5ee1cecf5f8eacd1284feb5f0bf2bdea533a51e2f0c9aabe9236d335989f3b\",\n \"indirect\": false,\n \"name\": \"B256\",\n- \"offset\": 4192\n+ \"offset\": 4088\n },\n {\n \"concreteTypeId\": \"81fc10c4681a3271cf2d66b2ec6fbc8ed007a442652930844fcf11818c295bff\",\n \"indirect\": false,\n \"name\": \"CONFIGURABLE_STRUCT\",\n- \"offset\": 4312\n+ \"offset\": 4208\n },\n {\n \"concreteTypeId\": \"a2922861f03be8a650595dd76455b95383a61b46dd418f02607fa2e00dc39d5c\",\n \"indirect\": false,\n \"name\": \"CONFIGURABLE_ENUM_A\",\n- \"offset\": 4232\n+ \"offset\": 4128\n },\n {\n \"concreteTypeId\": \"a2922861f03be8a650595dd76455b95383a61b46dd418f02607fa2e00dc39d5c\",\n \"indirect\": false,\n \"name\": \"CONFIGURABLE_ENUM_B\",\n- \"offset\": 4272\n+ \"offset\": 4168\n },\n {\n \"concreteTypeId\": \"4926d35d1a5157936b0a29bc126b8aace6d911209a5c130e9b716b0c73643ea6\",\n \"indirect\": false,\n \"name\": \"ARRAY_BOOL\",\n- \"offset\": 4160\n+ \"offset\": 4056\n },\n {\n \"concreteTypeId\": \"776fb5a3824169d6736138565fdc20aad684d9111266a5ff6d5c675280b7e199\",\n \"indirect\": false,\n \"name\": \"ARRAY_U64\",\n- \"offset\": 4168\n+ \"offset\": 4064\n },\n {\n \"concreteTypeId\": \"c998ca9a5f221fe7b5c66ae70c8a9562b86d964408b00d17f883c906bc1fe4be\",\n \"indirect\": false,\n \"name\": \"TUPLE_BOOL_U64\",\n- \"offset\": 4344\n+ \"offset\": 4240\n },\n {\n \"concreteTypeId\": \"94f0fa95c830be5e4f711963e83259fe7e8bc723278ab6ec34449e791a99b53a\",\n \"indirect\": false,\n \"name\": \"STR_4\",\n- \"offset\": 4336\n+ \"offset\": 4232\n },\n {\n \"concreteTypeId\": \"c89951a24c6ca28c13fd1cfdc646b2b656d69e61a92b91023be7eb58eb914b6b\",\n \"indirect\": false,\n \"name\": \"NOT_USED\",\n- \"offset\": 4328\n+ \"offset\": 4224\n }\n ],\n \"encodingVersion\": \"1\",\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/const_generics/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/const_generics/stdout.snap\nindex b3fe7d8cf3c..82dbaace9d1 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/const_generics/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/const_generics/stdout.snap\n@@ -410,12 +410,12 @@ warning\n ____\n \n Compiled script \"const_generics\" with 2 warnings.\n- Finished release [optimized + fuel] target(s) [760 B] in ???\n+ Finished release [optimized + fuel] target(s) [680 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_generics\n \n- test run_main ... ok (???, 448 gas)\n+ test run_main ... ok (???, 386 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/if/inline_if_expr_const/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/if/inline_if_expr_const/stdout.snap\nindex d72294ac816..150bad07ec9 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/if/inline_if_expr_const/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/if/inline_if_expr_const/stdout.snap\n@@ -7,12 +7,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/language/if/inline_if_expr_const\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-assert)\n Compiling script inline_if_expr_const (test/src/e2e_vm_tests/test_programs/should_pass/language/if/inline_if_expr_const)\n- Finished debug [unoptimized + fuel] target(s) [656 B] in ???\n+ Finished debug [unoptimized + fuel] target(s) [632 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- inline_if_expr_const\n \n- test test_if_works ... ok (???, 601 gas)\n+ test test_if_works ... ok (???, 585 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -208,31 +208,23 @@ move $$locbase $sp ; [fn init: if_not_const_5]: set locals base regis\n cfei i8 ; [fn init: if_not_const_5]: allocate: locals 8 byte(s), call args 0 slot(s)\n sb $$locbase $$arg0 i0 ; store byte\n lb $r0 $$locbase i0 ; load byte\n-movi $r1 i10 ; initialize constant into register\n+movi $r1 i10 ; move parameter from branch to block argument\n jnzf $r0 $zero i1\n-movi $r1 i20 ; initialize constant into register\n+movi $r1 i20 ; move parameter from branch to block argument\n move $$retv $r1 ; [fn end: if_not_const_5] set return value\n cfsi i8 ; [fn end: if_not_const_5] free: locals 8 byte(s), call args 0 slot(s)\n poph i524288 ; [fn end: if_not_const_5]: restore used high registers 40..64\n popl i3 ; [fn end: if_not_const_5]: restore used low registers 16..40\n jal $zero $$reta i0 ; [fn end: if_not_const_5] return from call\n \n-\n-pshl i1 ; [fn init: if_const_true_6]: push used low registers 16..40\n pshh i524288 ; [fn init: if_const_true_6]: push used high registers 40..64\n-movi $r0 i10 ; initialize constant into register\n-move $$retv $r0 ; [fn end: if_const_true_6] set return value\n+movi $$retv i10 ; [fn end: if_const_true_6] set return value\n poph i524288 ; [fn end: if_const_true_6]: restore used high registers 40..64\n-popl i1 ; [fn end: if_const_true_6]: restore used low registers 16..40\n jal $zero $$reta i0 ; [fn end: if_const_true_6] return from call\n \n-\n-pshl i1 ; [fn init: if_const_false_7]: push used low registers 16..40\n pshh i524288 ; [fn init: if_const_false_7]: push used high registers 40..64\n-movi $r0 i20 ; initialize constant into register\n-move $$retv $r0 ; [fn end: if_const_false_7] set return value\n+movi $$retv i20 ; [fn end: if_const_false_7] set return value\n poph i524288 ; [fn end: if_const_false_7]: restore used high registers 40..64\n-popl i1 ; [fn end: if_const_false_7]: restore used low registers 16..40\n jal $zero $$reta i0 ; [fn end: if_const_false_7] return from call\n \n \n@@ -247,9 +239,9 @@ sw $$locbase $one i0 ; store word\n lw $r0 $$locbase i1 ; load word\n lw $r1 $$locbase i0 ; load word\n eq $r0 $r0 $r1\n-movi $r1 i10 ; initialize constant into register\n+movi $r1 i10 ; move parameter from branch to block argument\n jnzf $r0 $zero i1\n-movi $r1 i20 ; initialize constant into register\n+movi $r1 i20 ; move parameter from branch to block argument\n move $$retv $r1 ; [fn end: if_const_generic_8] set return value\n cfsi i16 ; [fn end: if_const_generic_8] free: locals 16 byte(s), call args 0 slot(s)\n poph i524288 ; [fn end: if_const_generic_8]: restore used high registers 40..64\n@@ -267,11 +259,11 @@ sw $$locbase $zero i1 ; store word\n sw $$locbase $one i0 ; store word\n lw $r0 $$locbase i1 ; load word\n lw $r1 $$locbase i0 ; load word\n-eq $r1 $r0 $r1\n-movi $r0 i10 ; initialize constant into register\n-jnzf $r1 $zero i1\n-movi $r0 i20 ; initialize constant into register\n-move $$retv $r0 ; [fn end: if_const_generic_9] set return value\n+eq $r0 $r0 $r1\n+movi $r1 i10 ; move parameter from branch to block argument\n+jnzf $r0 $zero i1\n+movi $r1 i20 ; move parameter from branch to block argument\n+move $$retv $r1 ; [fn end: if_const_generic_9] set return value\n cfsi i16 ; [fn end: if_const_generic_9] free: locals 16 byte(s), call args 0 slot(s)\n poph i524288 ; [fn end: if_const_generic_9]: restore used high registers 40..64\n popl i3 ; [fn end: if_const_generic_9]: restore used low registers 16..40\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/dbg/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/dbg/stdout.snap\nindex 634dfb3c8a8..f8701bce06d 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/dbg/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/dbg/stdout.snap\n@@ -71,12 +71,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/dbg\n Compiling library std (sway-lib-std)\n Compiling script dbg (test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/dbg)\n- Finished debug [unoptimized + fuel] target(s) [37.024 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [36.8 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- dbg\n \n- test call_main ... ok (???, 211316 gas)\n+ test call_main ... ok (???, 202786 gas)\n debug output:\n [src/main.sw:13:13] () = ()\n [src/main.sw:15:13] true = true\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/logging/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/logging/stdout.snap\nindex d1a86fc1b29..27bdb05ad00 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/logging/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/logging/stdout.snap\n@@ -1732,7 +1732,7 @@ warning\n ____\n \n Compiled script \"logging\" with 6 warnings.\n- Finished release [optimized + fuel] target(s) [2.792 KB] in ???\n+ Finished release [optimized + fuel] target(s) [2.688 KB] in ???\n \n > forc test --path test/src/e2e_vm_tests/test_programs/should_pass/language/logging --release\n exit status: 0\n@@ -1828,12 +1828,12 @@ warning\n ____\n \n Compiled script \"logging\" with 7 warnings.\n- Finished release [optimized + fuel] target(s) [2.8 KB] in ???\n+ Finished release [optimized + fuel] target(s) [2.704 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- logging\n \n- test call_main ... ok (???, 5570 gas)\n+ test call_main ... ok (???, 5508 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_one_u64/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_one_u64/stdout.snap\nindex a4782ce92d6..ed9cceb6bfe 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_one_u64/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_one_u64/stdout.snap\n@@ -123,7 +123,7 @@ movi $r1 i8 ; initialize constant into register\n retd $r0 $r1 ; [entry end: __entry] return slice\n pshl i1 ; [fn init: main_11]: push used low registers 16..40\n pshh i524288 ; [fn init: main_11]: push used high registers 40..64\n-add $r0 $$arg0 $one\n+addi $r0 $$arg0 i1\n move $$retv $r0 ; [fn end: main_11] set return value\n poph i524288 ; [fn end: main_11]: restore used high registers 40..64\n popl i1 ; [fn end: main_11]: restore used low registers 16..40\n@@ -154,7 +154,7 @@ jal $zero $$reta i0 ; [fn end: main_11] return from call\n 0x00000050 RETD $writable R17 ;; [37, 65, 16, 0]\n 0x00000054 PSHL 0x1 ;; [149, 0, 0, 1]\n 0x00000058 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x0000005c ADD $writable R58 $one ;; [16, 67, 160, 64]\n+0x0000005c ADDI $writable R58 0x1 ;; [80, 67, 160, 1]\n 0x00000060 MOVE R61 $writable ;; [26, 245, 0, 0]\n 0x00000064 POPH 0x80000 ;; [152, 8, 0, 0]\n 0x00000068 POPL 0x1 ;; [151, 0, 0, 1]\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_ref/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_ref/stdout.snap\nindex 0540c196cfe..672a181967e 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_ref/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_ref/stdout.snap\n@@ -381,4 +381,4 @@ script {\n !166 = span !27 1328 1333\n !167 = (!162 !163 !166)\n \n- Finished debug [unoptimized + fuel] target(s) [464 B] in ???\n+ Finished debug [unoptimized + fuel] target(s) [456 B] in ???\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_various_types/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_various_types/stdout.snap\nindex dbd1e4f29be..f23997e97b1 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_various_types/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/main_args/main_args_various_types/stdout.snap\n@@ -1328,48 +1328,46 @@ addi $r1 $$locbase i168 ; get offset to local __ptr { ptr }\n sw $$locbase $r0 i21 ; store word\n addi $r0 $$locbase i440 ; get offset to local __ptr { ptr }\n mcpi $r0 $r1 i8 ; copy memory\n-addi $r6 $$locbase i440 ; get offset to local __ptr { ptr }\n-addi $r5 $$locbase i248 ; get offset to local __ptr { [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2] }\n+addi $r5 $$locbase i440 ; get offset to local __ptr { ptr }\n+addi $r4 $$locbase i248 ; get offset to local __ptr { [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2] }\n addi $r0 $$locbase i112 ; get offset to local __ptr [u8; 48]\n mcli $r0 i48 ; clear memory [u8; 48], 48 bytes\n addi $r1 $$locbase i392 ; get offset to local __ptr [u8; 48]\n mcpi $r1 $r0 i48 ; copy memory\n-addi $r4 $$locbase i392 ; get offset to local __ptr [u8; 48]\n-move $r3 $zero ; move parameter from branch to block argument\n+addi $r3 $$locbase i392 ; get offset to local __ptr [u8; 48]\n+movi $r2 i0 ; move parameter from branch to block argument\n movi $r0 i2 ; initialize constant into register\n-lt $r0 $r3 $r0\n+lt $r0 $r2 $r0\n jnzf $r0 $zero i15\n-mcpi $r5 $r4 i48 ; copy memory\n+mcpi $r4 $r3 i48 ; copy memory\n addi $r0 $$locbase i344 ; get offset to local __ptr { [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2] }\n-mcpi $r0 $r5 i48 ; copy memory\n+mcpi $r0 $r4 i48 ; copy memory\n addi $r0 $$locbase i344 ; get offset to local __ptr { [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2] }\n addi $r1 $$locbase i184 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n mcpi $r1 $r0 i48 ; copy memory\n addi $r0 $$locbase i160 ; get offset to local __ptr { u64 }\n move $$arg0 $r1 ; [call: main_32]: pass argument 0\n move $$arg1 $r0 ; [call: main_32]: pass argument 1\n-jal $$reta $pc i82 ; [call: main_32]: call function\n+jal $$reta $pc i77 ; [call: main_32]: call function\n addi $r1 $$locbase i336 ; get offset to local __ptr { u64 }\n mcpi $r1 $r0 i8 ; copy memory\n addi $r0 $$locbase i336 ; get offset to local __ptr { u64 }\n movi $r1 i8 ; initialize constant into register\n retd $r0 $r1 ; [entry end: __entry] return slice\n-movi $r0 i24 ; initialize constant into register\n-mul $r0 $r3 $r0\n-add $r8 $r4 $r0\n-addi $r10 $$locbase i296 ; get offset to local __ptr { { string<3> }, { u64, ( u64 | u64 ) } }\n-addi $r9 $$locbase i176 ; get offset to local __ptr { string<3> }\n+muli $r0 $r2 i24\n+add $r7 $r3 $r0\n+addi $r9 $$locbase i296 ; get offset to local __ptr { { string<3> }, { u64, ( u64 | u64 ) } }\n+addi $r8 $$locbase i176 ; get offset to local __ptr { string<3> }\n addi $r0 $$locbase i320 ; get offset to local __ptr { ptr, u64 }\n-mcpi $r0 $r6 i8 ; copy memory\n+mcpi $r0 $r5 i8 ; copy memory\n movi $r1 i3 ; initialize constant into register\n sw $$locbase $r1 i41 ; store word\n mcpi $$locbase $r0 i16 ; copy memory\n addi $r0 $$locbase i480 ; get offset to local __ptr slice\n mcpi $r0 $$locbase i16 ; copy memory\n-lw $r0 $r6 i0 ; load word\n-movi $r1 i3 ; initialize constant into register\n-add $r0 $r0 $r1\n-sw $r6 $r0 i0 ; store word\n+lw $r0 $r5 i0 ; load word\n+addi $r0 $r0 i3\n+sw $r5 $r0 i0 ; store word\n addi $r0 $$locbase i480 ; get offset to local __ptr slice\n addi $r1 $$locbase i448 ; get offset to local __ptr slice\n mcpi $r1 $r0 i16 ; copy memory\n@@ -1387,55 +1385,52 @@ mcpi $r0 $r1 i16 ; copy memory\n lw $r0 $$locbase i8 ; load word\n addi $r1 $$locbase i32 ; get offset to local __ptr string<3>\n mcpi $r1 $r0 i8 ; copy memory\n-mcpi $r9 $r1 i8 ; copy memory\n-lw $r0 $r6 i0 ; load word\n+mcpi $r8 $r1 i8 ; copy memory\n+lw $r0 $r5 i0 ; load word\n lw $r0 $r0 i0 ; lw val ptr i0\n-lw $r1 $r6 i0 ; load word\n-movi $r2 i8 ; initialize constant into register\n-add $r1 $r1 $r2\n-sw $r6 $r1 i0 ; store word\n+lw $r1 $r5 i0 ; load word\n+addi $r1 $r1 i8\n+sw $r5 $r1 i0 ; store word\n eq $r1 $r0 $zero\n-jnzf $r1 $zero i15\n+jnzf $r1 $zero i14\n eq $r0 $r0 $one\n jnzf $r0 $zero i1\n rvrt $zero\n addi $r0 $$locbase i96 ; get offset to local __ptr { u64, ( u64 | u64 ) }\n sw $$locbase $one i12 ; store word\n-lw $r1 $r6 i0 ; load word\n+lw $r1 $r5 i0 ; load word\n lw $r1 $r1 i0 ; lw val ptr i0\n-lw $r2 $r6 i0 ; load word\n-movi $r7 i8 ; initialize constant into register\n-add $r2 $r2 $r7\n-sw $r6 $r2 i0 ; store word\n+lw $r6 $r5 i0 ; load word\n+addi $r6 $r6 i8\n+sw $r5 $r6 i0 ; store word\n sw $$locbase $r1 i13 ; store word\n addi $r1 $$locbase i232 ; get offset to local __ptr { u64, ( u64 | u64 ) }\n mcpi $r1 $r0 i16 ; copy memory\n-jmpf $zero i11\n+jmpf $zero i10\n addi $r0 $$locbase i80 ; get offset to local __ptr { u64, ( u64 | u64 ) }\n sw $$locbase $zero i10 ; store word\n-lw $r1 $r6 i0 ; load word\n+lw $r1 $r5 i0 ; load word\n lw $r1 $r1 i0 ; lw val ptr i0\n-lw $r2 $r6 i0 ; load word\n-movi $r7 i8 ; initialize constant into register\n-add $r2 $r2 $r7\n-sw $r6 $r2 i0 ; store word\n+lw $r6 $r5 i0 ; load word\n+addi $r6 $r6 i8\n+sw $r5 $r6 i0 ; store word\n sw $$locbase $r1 i11 ; store word\n addi $r1 $$locbase i232 ; get offset to local __ptr { u64, ( u64 | u64 ) }\n mcpi $r1 $r0 i16 ; copy memory\n-mcpi $r10 $r9 i8 ; copy memory\n-addi $r0 $r10 i8 ; get offset to aggregate element\n+mcpi $r9 $r8 i8 ; copy memory\n+addi $r0 $r9 i8 ; get offset to aggregate element\n mcpi $r0 $r1 i16 ; copy memory\n addi $r0 $$locbase i40 ; get offset to local __ptr { { string<3> }, { u64, ( u64 | u64 ) } }\n-mcpi $r0 $r10 i24 ; copy memory\n-mcpi $r8 $r0 i24 ; copy memory\n-add $r3 $r3 $one\n-jmpb $zero i92\n+mcpi $r0 $r9 i24 ; copy memory\n+mcpi $r7 $r0 i24 ; copy memory\n+addi $r2 $r2 i1\n+jmpb $zero i87\n pshl i1023 ; [fn init: main_32]: push used low registers 16..40\n pshh i524288 ; [fn init: main_32]: push used high registers 40..64\n move $$locbase $sp ; [fn init: main_32]: set locals base register\n cfei i1264 ; [fn init: main_32]: allocate: locals 1264 byte(s), call args 0 slot(s)\n-move $r5 $$arg1 ; [fn init: main_32]: copy argument 1 (__ret_value)\n-move $r4 $$reta ; [fn init: main_32]: save return address\n+move $r6 $$arg1 ; [fn init: main_32]: copy argument 1 (__ret_value)\n+move $r5 $$reta ; [fn init: main_32]: save return address\n addi $r0 $$locbase i1088 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n mcpi $r0 $$arg0 i48 ; copy memory\n addi $r0 $$locbase i1088 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n@@ -1456,7 +1451,7 @@ mcpi $r0 $r1 i24 ; copy memory\n addi $r0 $$locbase i752 ; get offset to local __ptr { { ptr, u64, u64 } }\n addi $r1 $$locbase i872 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r1 $r0 i24 ; copy memory\n-move $r9 $zero ; move parameter from branch to block argument\n+movi $r9 i0 ; move parameter from branch to block argument\n movi $r0 i2 ; initialize constant into register\n lt $r0 $r9 $r0\n jnzf $r0 $zero i21\n@@ -1480,10 +1475,9 @@ addi $r0 $$locbase i96 ; get offset to local __ptr slice\n mcpi $r0 $r2 i16 ; copy memory\n addi $r1 $$locbase i696 ; get offset to local __ptr slice\n mcpi $r1 $r0 i16 ; copy memory\n-jmpf $zero i136\n+jmpf $zero i132\n addi $r0 $$locbase i1192 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n-movi $r1 i24 ; get array element size\n-mul $r1 $r9 $r1 ; get offset to array element\n+muli $r1 $r9 i24 ; get offset to array element\n add $r1 $r0 $r1 ; add array element offset to array base\n addi $r0 $$locbase i872 ; get offset to local __ptr { { ptr, u64, u64 } }\n addi $r2 $$locbase i1152 ; get offset to local __ptr { { string<3> }, { u64, ( u64 | u64 ) } }\n@@ -1512,15 +1506,12 @@ lw $r1 $$locbase i21 ; load word\n lw $r8 $$locbase i22 ; load word\n lw $r2 $$locbase i23 ; load word\n addi $r3 $$locbase i1144 ; get offset to local __ptr string<3>\n-movi $r6 i3 ; initialize constant into register\n-add $r6 $r2 $r6\n-gt $r7 $r6 $r8\n+addi $r4 $r2 i3\n+gt $r7 $r4 $r8\n jnzf $r7 $zero i1\n-jmpf $zero i7\n-movi $r7 i2 ; initialize constant into register\n-mul $r7 $r8 $r7\n-movi $r8 i3 ; initialize constant into register\n-add $r8 $r7 $r8\n+jmpf $zero i5\n+muli $r7 $r8 i2\n+addi $r8 $r7 i3\n aloc $r8\n mcp $hp $r1 $r2\n move $r1 $hp ; move parameter from branch to block argument\n@@ -1531,7 +1522,7 @@ mcpi $r2 $r7 i3 ; copy memory\n addi $r2 $$locbase i272 ; get offset to local __ptr { ptr, u64, u64 }\n sw $$locbase $r1 i34 ; store word\n sw $$locbase $r8 i35 ; store word\n-sw $$locbase $r6 i36 ; store word\n+sw $$locbase $r4 i36 ; store word\n addi $r1 $$locbase i48 ; get offset to local __ptr { ptr, u64, u64 }\n mcpi $r1 $r2 i24 ; copy memory\n mcpi $r0 $r1 i24 ; copy memory\n@@ -1563,10 +1554,10 @@ addi $r1 $$locbase i848 ; get offset to local __ptr { { ptr, u64, u64 } }\n addi $r2 $$locbase i576 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r2 $r1 i24 ; copy memory\n addi $r1 $$locbase i424 ; get offset to local __ptr { { ptr, u64, u64 } }\n-move $$arg0 $one ; [call: abi_encode_51]: pass argument 0\n+movi $$arg0 i1 ; [call: abi_encode_51]: pass argument 0\n move $$arg1 $r2 ; [call: abi_encode_51]: pass argument 1\n move $$arg2 $r1 ; [call: abi_encode_51]: pass argument 2\n-jal $$reta $pc i148 ; [call: abi_encode_51]: call function\n+jal $$reta $pc i138 ; [call: abi_encode_51]: call function\n addi $r2 $$locbase i1016 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r2 $r1 i24 ; copy memory\n addi $r1 $$locbase i1016 ; get offset to local __ptr { { ptr, u64, u64 } }\n@@ -1576,7 +1567,7 @@ addi $r1 $$locbase i448 ; get offset to local __ptr { { ptr, u64, u64 } }\n move $$arg0 $r0 ; [call: abi_encode_51]: pass argument 0\n move $$arg1 $r2 ; [call: abi_encode_51]: pass argument 1\n move $$arg2 $r1 ; [call: abi_encode_51]: pass argument 2\n-jal $$reta $pc i138 ; [call: abi_encode_51]: call function\n+jal $$reta $pc i128 ; [call: abi_encode_51]: call function\n addi $r0 $$locbase i1040 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r0 $r1 i24 ; copy memory\n addi $r0 $$locbase i1040 ; get offset to local __ptr { { ptr, u64, u64 } }\n@@ -1588,10 +1579,10 @@ addi $r1 $$locbase i848 ; get offset to local __ptr { { ptr, u64, u64 } }\n addi $r2 $$locbase i528 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r2 $r1 i24 ; copy memory\n addi $r1 $$locbase i376 ; get offset to local __ptr { { ptr, u64, u64 } }\n-move $$arg0 $zero ; [call: abi_encode_51]: pass argument 0\n+movi $$arg0 i0 ; [call: abi_encode_51]: pass argument 0\n move $$arg1 $r2 ; [call: abi_encode_51]: pass argument 1\n move $$arg2 $r1 ; [call: abi_encode_51]: pass argument 2\n-jal $$reta $pc i123 ; [call: abi_encode_51]: call function\n+jal $$reta $pc i113 ; [call: abi_encode_51]: call function\n addi $r2 $$locbase i944 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r2 $r1 i24 ; copy memory\n addi $r1 $$locbase i944 ; get offset to local __ptr { { ptr, u64, u64 } }\n@@ -1601,7 +1592,7 @@ addi $r1 $$locbase i400 ; get offset to local __ptr { { ptr, u64, u64 } }\n move $$arg0 $r0 ; [call: abi_encode_51]: pass argument 0\n move $$arg1 $r2 ; [call: abi_encode_51]: pass argument 1\n move $$arg2 $r1 ; [call: abi_encode_51]: pass argument 2\n-jal $$reta $pc i113 ; [call: abi_encode_51]: call function\n+jal $$reta $pc i103 ; [call: abi_encode_51]: call function\n addi $r0 $$locbase i992 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r0 $r1 i24 ; copy memory\n addi $r0 $$locbase i992 ; get offset to local __ptr { { ptr, u64, u64 } }\n@@ -1615,8 +1606,8 @@ mcpi $r1 $r0 i24 ; copy memory\n addi $r0 $$locbase i968 ; get offset to local __ptr { { ptr, u64, u64 } }\n addi $r1 $$locbase i872 ; get offset to local __ptr { { ptr, u64, u64 } }\n mcpi $r1 $r0 i24 ; copy memory\n-add $r9 $r9 $one\n-jmpb $zero i158\n+addi $r9 $r9 i1\n+jmpb $zero i154\n addi $r0 $$locbase i312 ; get offset to local __ptr slice\n mcpi $r0 $r1 i16 ; copy memory\n load $r0 data_NonConfigurable_1; load constant from data section\n@@ -1624,30 +1615,24 @@ lw $r1 $$locbase i39 ; load slice pointer for logging data\n lw $r2 $$locbase i40 ; load slice size for logging data\n logd $zero $r0 $r1 $r2 ; log slice\n addi $r0 $$locbase i1088 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n-movi $r1 i24 ; get array element size\n-mul $r1 $zero $r1 ; get offset to array element\n-add $r1 $r0 $r1 ; add array element offset to array base\n-addr $r0 data_NonConfigurable_2; get __const_global's address in data section\n+addr $r1 data_NonConfigurable_2; get __const_global's address in data section\n addi $r2 $$locbase i112 ; get offset to local __ptr { ptr, u64 }\n-sw $$locbase $r0 i14 ; store word\n-movi $r0 i3 ; initialize constant into register\n-sw $$locbase $r0 i15 ; store word\n-addi $r0 $$locbase i216 ; get offset to local __ptr slice\n-mcpi $r0 $r2 i16 ; copy memory\n+sw $$locbase $r1 i14 ; store word\n+movi $r1 i3 ; initialize constant into register\n+sw $$locbase $r1 i15 ; store word\n+addi $r1 $$locbase i216 ; get offset to local __ptr slice\n+mcpi $r1 $r2 i16 ; copy memory\n addi $r2 $$locbase i624 ; get offset to local __ptr string<3>\n-mcpi $r2 $r1 i8 ; copy memory\n-addi $r1 $$locbase i632 ; get offset to local __ptr slice\n-mcpi $r1 $r0 i16 ; copy memory\n+mcpi $r2 $r0 i8 ; copy memory\n+addi $r0 $$locbase i632 ; get offset to local __ptr slice\n+mcpi $r0 $r1 i16 ; copy memory\n move $$arg0 $r2 ; [call: eq_str_3_57]: pass argument 0\n-move $$arg1 $r1 ; [call: eq_str_3_57]: pass argument 1\n-jal $$reta $pc i113 ; [call: eq_str_3_57]: call function\n+move $$arg1 $r0 ; [call: eq_str_3_57]: pass argument 1\n+jal $$reta $pc i103 ; [call: eq_str_3_57]: call function\n eq $r0 $$retv $zero\n-jnzf $r0 $zero i63\n+jnzf $r0 $zero i56\n addi $r0 $$locbase i1088 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n-movi $r1 i24 ; get array element size\n-mul $r1 $zero $r1 ; get offset to array element\n-add $r1 $r0 $r1 ; add array element offset to array base\n-addi $r0 $r1 i8 ; get offset to aggregate element\n+addi $r0 $r0 i8 ; get offset to aggregate element\n addi $r1 $$locbase i328 ; get offset to local __ptr { u64, ( u64 | u64 ) }\n mcpi $r1 $r0 i16 ; copy memory\n lw $r0 $$locbase i41 ; load word\n@@ -1658,32 +1643,28 @@ lw $r0 $$locbase i42 ; load word\n movi $r1 i1338 ; initialize constant into register\n eq $r0 $r0 $r1\n eq $r0 $r0 $zero\n-jnzf $r0 $zero i45\n+jnzf $r0 $zero i41\n addi $r0 $$locbase i1088 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n-movi $r1 i24 ; get array element size\n-mul $r1 $one $r1 ; get offset to array element\n-add $r1 $r0 $r1 ; add array element offset to array base\n-addr $r0 data_NonConfigurable_3; get __const_global0's address in data section\n+addi $r0 $r0 i24 ; add array element offset to array base\n+addr $r1 data_NonConfigurable_3; get __const_global0's address in data section\n addi $r2 $$locbase i256 ; get offset to local __ptr { ptr, u64 }\n-sw $$locbase $r0 i32 ; store word\n-movi $r0 i3 ; initialize constant into register\n-sw $$locbase $r0 i33 ; store word\n-addi $r0 $$locbase i296 ; get offset to local __ptr slice\n-mcpi $r0 $r2 i16 ; copy memory\n+sw $$locbase $r1 i32 ; store word\n+movi $r1 i3 ; initialize constant into register\n+sw $$locbase $r1 i33 ; store word\n+addi $r1 $$locbase i296 ; get offset to local __ptr slice\n+mcpi $r1 $r2 i16 ; copy memory\n addi $r2 $$locbase i648 ; get offset to local __ptr string<3>\n-mcpi $r2 $r1 i8 ; copy memory\n-addi $r1 $$locbase i656 ; get offset to local __ptr slice\n-mcpi $r1 $r0 i16 ; copy memory\n+mcpi $r2 $r0 i8 ; copy memory\n+addi $r0 $$locbase i656 ; get offset to local __ptr slice\n+mcpi $r0 $r1 i16 ; copy memory\n move $$arg0 $r2 ; [call: eq_str_3_57]: pass argument 0\n-move $$arg1 $r1 ; [call: eq_str_3_57]: pass argument 1\n-jal $$reta $pc i76 ; [call: eq_str_3_57]: call function\n+move $$arg1 $r0 ; [call: eq_str_3_57]: pass argument 1\n+jal $$reta $pc i71 ; [call: eq_str_3_57]: call function\n eq $r0 $$retv $zero\n-jnzf $r0 $zero i22\n+jnzf $r0 $zero i20\n addi $r0 $$locbase i1088 ; get offset to local __ptr [{ { string<3> }, { u64, ( u64 | u64 ) } }; 2]\n-movi $r1 i24 ; get array element size\n-mul $r1 $one $r1 ; get offset to array element\n-add $r1 $r0 $r1 ; add array element offset to array base\n-addi $r0 $r1 i8 ; get offset to aggregate element\n+addi $r0 $r0 i24 ; add array element offset to array base\n+addi $r0 $r0 i8 ; get offset to aggregate element\n addi $r1 $$locbase i360 ; get offset to local __ptr { u64, ( u64 | u64 ) }\n mcpi $r1 $r0 i16 ; copy memory\n lw $r0 $$locbase i45 ; load word\n@@ -1697,7 +1678,7 @@ eq $r0 $r0 $zero\n jnzf $r0 $zero i4\n addi $r0 $$locbase i472 ; get offset to local __ptr { u64 }\n sw $$locbase $one i59 ; store word\n-mcpi $r5 $r0 i8 ; copy memory\n+mcpi $r6 $r0 i8 ; copy memory\n jmpf $zero i8\n load $r0 data_NonConfigurable_4; load constant from data section\n rvrt $r0\n@@ -1708,7 +1689,7 @@ rvrt $r0\n load $r0 data_NonConfigurable_4; load constant from data section\n rvrt $r0\n cfsi i1264 ; [fn end: main_32] free: locals 1264 byte(s), call args 0 slot(s)\n-move $$reta $r4 ; [fn end: main_32] restore return address\n+move $$reta $r5 ; [fn end: main_32] restore return address\n poph i524288 ; [fn end: main_32]: restore used high registers 40..64\n popl i1023 ; [fn end: main_32]: restore used low registers 16..40\n jal $zero $$reta i0 ; [fn end: main_32] return from call\n@@ -1726,15 +1707,12 @@ mcpi $r1 $$locbase i24 ; copy memory\n lw $r1 $$locbase i6 ; load word\n lw $r5 $$locbase i7 ; load word\n lw $r2 $$locbase i8 ; load word\n-movi $r3 i8 ; initialize constant into register\n-add $r3 $r2 $r3\n+addi $r3 $r2 i8\n gt $r4 $r3 $r5\n jnzf $r4 $zero i1\n-jmpf $zero i7\n-movi $r4 i2 ; initialize constant into register\n-mul $r4 $r5 $r4\n-movi $r5 i8 ; initialize constant into register\n-add $r5 $r4 $r5\n+jmpf $zero i5\n+muli $r4 $r5 i2\n+addi $r5 $r4 i8\n aloc $r5\n mcp $hp $r1 $r2\n move $r1 $hp ; move parameter from branch to block argument\n@@ -1785,7 +1763,7 @@ data_NonConfigurable_4 .word 18446744073709486084\n \n 0x00000000 MOVE R60 $pc ;; [26, 240, 48, 0]\n 0x00000004 JMPF $zero 0x4 ;; [116, 0, 0, 4]\n-0x00000008 ;; [0, 0, 0, 0, 0, 0, 7, 56]\n+0x00000008 ;; [0, 0, 0, 0, 0, 0, 6, 224]\n 0x00000010 ;; [0, 0, 0, 0, 0, 0, 0, 0]\n 0x00000018 LW R63 R60 0x1 ;; [93, 255, 192, 1]\n 0x0000001c ADD R63 R63 R60 ;; [16, 255, 255, 0]\n@@ -1796,459 +1774,437 @@ data_NonConfigurable_4 .word 18446744073709486084\n 0x00000030 SW R59 $writable 0x15 ;; [95, 237, 0, 21]\n 0x00000034 ADDI $writable R59 0x1b8 ;; [80, 67, 177, 184]\n 0x00000038 MCPI $writable R17 0x8 ;; [96, 65, 16, 8]\n-0x0000003c ADDI R22 R59 0x1b8 ;; [80, 91, 177, 184]\n-0x00000040 ADDI R21 R59 0xf8 ;; [80, 87, 176, 248]\n+0x0000003c ADDI R21 R59 0x1b8 ;; [80, 87, 177, 184]\n+0x00000040 ADDI R20 R59 0xf8 ;; [80, 83, 176, 248]\n 0x00000044 ADDI $writable R59 0x70 ;; [80, 67, 176, 112]\n 0x00000048 MCLI $writable 0x30 ;; [112, 64, 0, 48]\n 0x0000004c ADDI R17 R59 0x188 ;; [80, 71, 177, 136]\n 0x00000050 MCPI R17 $writable 0x30 ;; [96, 69, 0, 48]\n-0x00000054 ADDI R20 R59 0x188 ;; [80, 83, 177, 136]\n-0x00000058 MOVE R19 $zero ;; [26, 76, 0, 0]\n+0x00000054 ADDI R19 R59 0x188 ;; [80, 79, 177, 136]\n+0x00000058 MOVI R18 0x0 ;; [114, 72, 0, 0]\n 0x0000005c MOVI $writable 0x2 ;; [114, 64, 0, 2]\n-0x00000060 LT $writable R19 $writable ;; [22, 65, 52, 0]\n+0x00000060 LT $writable R18 $writable ;; [22, 65, 36, 0]\n 0x00000064 JNZF $writable $zero 0xf ;; [118, 64, 0, 15]\n-0x00000068 MCPI R21 R20 0x30 ;; [96, 85, 64, 48]\n+0x00000068 MCPI R20 R19 0x30 ;; [96, 81, 48, 48]\n 0x0000006c ADDI $writable R59 0x158 ;; [80, 67, 177, 88]\n-0x00000070 MCPI $writable R21 0x30 ;; [96, 65, 80, 48]\n+0x00000070 MCPI $writable R20 0x30 ;; [96, 65, 64, 48]\n 0x00000074 ADDI $writable R59 0x158 ;; [80, 67, 177, 88]\n 0x00000078 ADDI R17 R59 0xb8 ;; [80, 71, 176, 184]\n 0x0000007c MCPI R17 $writable 0x30 ;; [96, 69, 0, 48]\n 0x00000080 ADDI $writable R59 0xa0 ;; [80, 67, 176, 160]\n 0x00000084 MOVE R58 R17 ;; [26, 233, 16, 0]\n 0x00000088 MOVE R57 $writable ;; [26, 229, 0, 0]\n-0x0000008c JAL R62 $pc 0x52 ;; [153, 248, 48, 82]\n+0x0000008c JAL R62 $pc 0x4d ;; [153, 248, 48, 77]\n 0x00000090 ADDI R17 R59 0x150 ;; [80, 71, 177, 80]\n 0x00000094 MCPI R17 $writable 0x8 ;; [96, 69, 0, 8]\n 0x00000098 ADDI $writable R59 0x150 ;; [80, 67, 177, 80]\n 0x0000009c MOVI R17 0x8 ;; [114, 68, 0, 8]\n 0x000000a0 RETD $writable R17 ;; [37, 65, 16, 0]\n-0x000000a4 MOVI $writable 0x18 ;; [114, 64, 0, 24]\n-0x000000a8 MUL $writable R19 $writable ;; [27, 65, 52, 0]\n-0x000000ac ADD R24 R20 $writable ;; [16, 97, 68, 0]\n-0x000000b0 ADDI R26 R59 0x128 ;; [80, 107, 177, 40]\n-0x000000b4 ADDI R25 R59 0xb0 ;; [80, 103, 176, 176]\n-0x000000b8 ADDI $writable R59 0x140 ;; [80, 67, 177, 64]\n-0x000000bc MCPI $writable R22 0x8 ;; [96, 65, 96, 8]\n-0x000000c0 MOVI R17 0x3 ;; [114, 68, 0, 3]\n-0x000000c4 SW R59 R17 0x29 ;; [95, 237, 16, 41]\n-0x000000c8 MCPI R59 $writable 0x10 ;; [96, 237, 0, 16]\n-0x000000cc ADDI $writable R59 0x1e0 ;; [80, 67, 177, 224]\n-0x000000d0 MCPI $writable R59 0x10 ;; [96, 67, 176, 16]\n-0x000000d4 LW $writable R22 0x0 ;; [93, 65, 96, 0]\n-0x000000d8 MOVI R17 0x3 ;; [114, 68, 0, 3]\n-0x000000dc ADD $writable $writable R17 ;; [16, 65, 4, 64]\n-0x000000e0 SW R22 $writable 0x0 ;; [95, 89, 0, 0]\n-0x000000e4 ADDI $writable R59 0x1e0 ;; [80, 67, 177, 224]\n-0x000000e8 ADDI R17 R59 0x1c0 ;; [80, 71, 177, 192]\n-0x000000ec MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x000000f0 ADDI $writable R59 0x1c0 ;; [80, 67, 177, 192]\n-0x000000f4 ADDI R17 R59 0x1d0 ;; [80, 71, 177, 208]\n-0x000000f8 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x000000fc ADDI $writable R59 0x1d0 ;; [80, 67, 177, 208]\n-0x00000100 ADDI R17 R59 0x1f0 ;; [80, 71, 177, 240]\n-0x00000104 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x00000108 ADDI $writable R59 0x1f0 ;; [80, 67, 177, 240]\n-0x0000010c ADDI R17 R59 0x10 ;; [80, 71, 176, 16]\n-0x00000110 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x00000114 ADDI $writable R59 0x40 ;; [80, 67, 176, 64]\n-0x00000118 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n-0x0000011c LW $writable R59 0x8 ;; [93, 67, 176, 8]\n-0x00000120 ADDI R17 R59 0x20 ;; [80, 71, 176, 32]\n-0x00000124 MCPI R17 $writable 0x8 ;; [96, 69, 0, 8]\n-0x00000128 MCPI R25 R17 0x8 ;; [96, 101, 16, 8]\n-0x0000012c LW $writable R22 0x0 ;; [93, 65, 96, 0]\n-0x00000130 LW $writable $writable 0x0 ;; [93, 65, 0, 0]\n-0x00000134 LW R17 R22 0x0 ;; [93, 69, 96, 0]\n-0x00000138 MOVI R18 0x8 ;; [114, 72, 0, 8]\n-0x0000013c ADD R17 R17 R18 ;; [16, 69, 20, 128]\n-0x00000140 SW R22 R17 0x0 ;; [95, 89, 16, 0]\n-0x00000144 EQ R17 $writable $zero ;; [19, 69, 0, 0]\n-0x00000148 JNZF R17 $zero 0xf ;; [118, 68, 0, 15]\n-0x0000014c EQ $writable $writable $one ;; [19, 65, 0, 64]\n-0x00000150 JNZF $writable $zero 0x1 ;; [118, 64, 0, 1]\n-0x00000154 RVRT $zero ;; [54, 0, 0, 0]\n-0x00000158 ADDI $writable R59 0x60 ;; [80, 67, 176, 96]\n-0x0000015c SW R59 $one 0xc ;; [95, 236, 16, 12]\n-0x00000160 LW R17 R22 0x0 ;; [93, 69, 96, 0]\n-0x00000164 LW R17 R17 0x0 ;; [93, 69, 16, 0]\n-0x00000168 LW R18 R22 0x0 ;; [93, 73, 96, 0]\n-0x0000016c MOVI R23 0x8 ;; [114, 92, 0, 8]\n-0x00000170 ADD R18 R18 R23 ;; [16, 73, 37, 192]\n-0x00000174 SW R22 R18 0x0 ;; [95, 89, 32, 0]\n-0x00000178 SW R59 R17 0xd ;; [95, 237, 16, 13]\n-0x0000017c ADDI R17 R59 0xe8 ;; [80, 71, 176, 232]\n-0x00000180 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x00000184 JMPF $zero 0xb ;; [116, 0, 0, 11]\n-0x00000188 ADDI $writable R59 0x50 ;; [80, 67, 176, 80]\n-0x0000018c SW R59 $zero 0xa ;; [95, 236, 0, 10]\n-0x00000190 LW R17 R22 0x0 ;; [93, 69, 96, 0]\n-0x00000194 LW R17 R17 0x0 ;; [93, 69, 16, 0]\n-0x00000198 LW R18 R22 0x0 ;; [93, 73, 96, 0]\n-0x0000019c MOVI R23 0x8 ;; [114, 92, 0, 8]\n-0x000001a0 ADD R18 R18 R23 ;; [16, 73, 37, 192]\n-0x000001a4 SW R22 R18 0x0 ;; [95, 89, 32, 0]\n-0x000001a8 SW R59 R17 0xb ;; [95, 237, 16, 11]\n-0x000001ac ADDI R17 R59 0xe8 ;; [80, 71, 176, 232]\n-0x000001b0 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x000001b4 MCPI R26 R25 0x8 ;; [96, 105, 144, 8]\n-0x000001b8 ADDI $writable R26 0x8 ;; [80, 65, 160, 8]\n-0x000001bc MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n-0x000001c0 ADDI $writable R59 0x28 ;; [80, 67, 176, 40]\n-0x000001c4 MCPI $writable R26 0x18 ;; [96, 65, 160, 24]\n-0x000001c8 MCPI R24 $writable 0x18 ;; [96, 97, 0, 24]\n-0x000001cc ADD R19 R19 $one ;; [16, 77, 48, 64]\n-0x000001d0 JMPB $zero 0x5c ;; [117, 0, 0, 92]\n-0x000001d4 PSHL 0x3ff ;; [149, 0, 3, 255]\n-0x000001d8 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000001dc MOVE R59 $sp ;; [26, 236, 80, 0]\n-0x000001e0 CFEI 0x4f0 ;; [145, 0, 4, 240]\n-0x000001e4 MOVE R21 R57 ;; [26, 87, 144, 0]\n-0x000001e8 MOVE R20 R62 ;; [26, 83, 224, 0]\n-0x000001ec ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n-0x000001f0 MCPI $writable R58 0x30 ;; [96, 67, 160, 48]\n-0x000001f4 ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n-0x000001f8 ADDI R17 R59 0x1e0 ;; [80, 71, 177, 224]\n-0x000001fc MOVI R18 0x400 ;; [114, 72, 4, 0]\n-0x00000200 ALOC R18 ;; [38, 72, 0, 0]\n-0x00000204 ADDI R18 R59 0x90 ;; [80, 75, 176, 144]\n-0x00000208 SW R59 $hp 0x12 ;; [95, 236, 112, 18]\n-0x0000020c MOVI R19 0x400 ;; [114, 76, 4, 0]\n-0x00000210 SW R59 R19 0x13 ;; [95, 237, 48, 19]\n-0x00000214 SW R59 $zero 0x14 ;; [95, 236, 0, 20]\n-0x00000218 MCPI R59 R18 0x18 ;; [96, 237, 32, 24]\n-0x0000021c MCPI R17 R59 0x18 ;; [96, 71, 176, 24]\n-0x00000220 ADDI R18 R59 0x4a8 ;; [80, 75, 180, 168]\n-0x00000224 MCPI R18 $writable 0x30 ;; [96, 73, 0, 48]\n-0x00000228 ADDI $writable R59 0x2f0 ;; [80, 67, 178, 240]\n-0x0000022c MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x00000230 ADDI $writable R59 0x2f0 ;; [80, 67, 178, 240]\n-0x00000234 ADDI R17 R59 0x368 ;; [80, 71, 179, 104]\n-0x00000238 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x0000023c MOVE R25 $zero ;; [26, 100, 0, 0]\n-0x00000240 MOVI $writable 0x2 ;; [114, 64, 0, 2]\n-0x00000244 LT $writable R25 $writable ;; [22, 65, 148, 0]\n-0x00000248 JNZF $writable $zero 0x15 ;; [118, 64, 0, 21]\n-0x0000024c ADDI $writable R59 0x368 ;; [80, 67, 179, 104]\n-0x00000250 ADDI R17 R59 0x2d8 ;; [80, 71, 178, 216]\n-0x00000254 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x00000258 ADDI $writable R59 0x2d8 ;; [80, 67, 178, 216]\n-0x0000025c ADDI R17 R59 0x4d8 ;; [80, 71, 180, 216]\n-0x00000260 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x00000264 ADDI $writable R59 0x4d8 ;; [80, 67, 180, 216]\n-0x00000268 ADDI R17 R59 0x48 ;; [80, 71, 176, 72]\n-0x0000026c MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x00000270 ADDI $writable R59 0xc0 ;; [80, 67, 176, 192]\n-0x00000274 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x00000278 ADDI R17 $writable 0x10 ;; [80, 69, 0, 16]\n-0x0000027c ADDI R18 R59 0xf0 ;; [80, 75, 176, 240]\n-0x00000280 MCPI R18 $writable 0x8 ;; [96, 73, 0, 8]\n-0x00000284 ADDI $writable R18 0x8 ;; [80, 65, 32, 8]\n-0x00000288 MCPI $writable R17 0x8 ;; [96, 65, 16, 8]\n-0x0000028c ADDI $writable R59 0x60 ;; [80, 67, 176, 96]\n-0x00000290 MCPI $writable R18 0x10 ;; [96, 65, 32, 16]\n-0x00000294 ADDI R17 R59 0x2b8 ;; [80, 71, 178, 184]\n-0x00000298 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x0000029c JMPF $zero 0x88 ;; [116, 0, 0, 136]\n-0x000002a0 ADDI $writable R59 0x4a8 ;; [80, 67, 180, 168]\n-0x000002a4 MOVI R17 0x18 ;; [114, 68, 0, 24]\n-0x000002a8 MUL R17 R25 R17 ;; [27, 69, 148, 64]\n-0x000002ac ADD R17 $writable R17 ;; [16, 69, 4, 64]\n-0x000002b0 ADDI $writable R59 0x368 ;; [80, 67, 179, 104]\n-0x000002b4 ADDI R18 R59 0x480 ;; [80, 75, 180, 128]\n-0x000002b8 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x000002bc ADDI R17 R59 0x308 ;; [80, 71, 179, 8]\n-0x000002c0 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x000002c4 ADDI $writable R59 0x480 ;; [80, 67, 180, 128]\n-0x000002c8 ADDI R17 R59 0x308 ;; [80, 71, 179, 8]\n-0x000002cc ADDI R18 R59 0x470 ;; [80, 75, 180, 112]\n+0x000000a4 MULI $writable R18 0x18 ;; [85, 65, 32, 24]\n+0x000000a8 ADD R23 R19 $writable ;; [16, 93, 52, 0]\n+0x000000ac ADDI R25 R59 0x128 ;; [80, 103, 177, 40]\n+0x000000b0 ADDI R24 R59 0xb0 ;; [80, 99, 176, 176]\n+0x000000b4 ADDI $writable R59 0x140 ;; [80, 67, 177, 64]\n+0x000000b8 MCPI $writable R21 0x8 ;; [96, 65, 80, 8]\n+0x000000bc MOVI R17 0x3 ;; [114, 68, 0, 3]\n+0x000000c0 SW R59 R17 0x29 ;; [95, 237, 16, 41]\n+0x000000c4 MCPI R59 $writable 0x10 ;; [96, 237, 0, 16]\n+0x000000c8 ADDI $writable R59 0x1e0 ;; [80, 67, 177, 224]\n+0x000000cc MCPI $writable R59 0x10 ;; [96, 67, 176, 16]\n+0x000000d0 LW $writable R21 0x0 ;; [93, 65, 80, 0]\n+0x000000d4 ADDI $writable $writable 0x3 ;; [80, 65, 0, 3]\n+0x000000d8 SW R21 $writable 0x0 ;; [95, 85, 0, 0]\n+0x000000dc ADDI $writable R59 0x1e0 ;; [80, 67, 177, 224]\n+0x000000e0 ADDI R17 R59 0x1c0 ;; [80, 71, 177, 192]\n+0x000000e4 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x000000e8 ADDI $writable R59 0x1c0 ;; [80, 67, 177, 192]\n+0x000000ec ADDI R17 R59 0x1d0 ;; [80, 71, 177, 208]\n+0x000000f0 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x000000f4 ADDI $writable R59 0x1d0 ;; [80, 67, 177, 208]\n+0x000000f8 ADDI R17 R59 0x1f0 ;; [80, 71, 177, 240]\n+0x000000fc MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x00000100 ADDI $writable R59 0x1f0 ;; [80, 67, 177, 240]\n+0x00000104 ADDI R17 R59 0x10 ;; [80, 71, 176, 16]\n+0x00000108 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x0000010c ADDI $writable R59 0x40 ;; [80, 67, 176, 64]\n+0x00000110 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n+0x00000114 LW $writable R59 0x8 ;; [93, 67, 176, 8]\n+0x00000118 ADDI R17 R59 0x20 ;; [80, 71, 176, 32]\n+0x0000011c MCPI R17 $writable 0x8 ;; [96, 69, 0, 8]\n+0x00000120 MCPI R24 R17 0x8 ;; [96, 97, 16, 8]\n+0x00000124 LW $writable R21 0x0 ;; [93, 65, 80, 0]\n+0x00000128 LW $writable $writable 0x0 ;; [93, 65, 0, 0]\n+0x0000012c LW R17 R21 0x0 ;; [93, 69, 80, 0]\n+0x00000130 ADDI R17 R17 0x8 ;; [80, 69, 16, 8]\n+0x00000134 SW R21 R17 0x0 ;; [95, 85, 16, 0]\n+0x00000138 EQ R17 $writable $zero ;; [19, 69, 0, 0]\n+0x0000013c JNZF R17 $zero 0xe ;; [118, 68, 0, 14]\n+0x00000140 EQ $writable $writable $one ;; [19, 65, 0, 64]\n+0x00000144 JNZF $writable $zero 0x1 ;; [118, 64, 0, 1]\n+0x00000148 RVRT $zero ;; [54, 0, 0, 0]\n+0x0000014c ADDI $writable R59 0x60 ;; [80, 67, 176, 96]\n+0x00000150 SW R59 $one 0xc ;; [95, 236, 16, 12]\n+0x00000154 LW R17 R21 0x0 ;; [93, 69, 80, 0]\n+0x00000158 LW R17 R17 0x0 ;; [93, 69, 16, 0]\n+0x0000015c LW R22 R21 0x0 ;; [93, 89, 80, 0]\n+0x00000160 ADDI R22 R22 0x8 ;; [80, 89, 96, 8]\n+0x00000164 SW R21 R22 0x0 ;; [95, 85, 96, 0]\n+0x00000168 SW R59 R17 0xd ;; [95, 237, 16, 13]\n+0x0000016c ADDI R17 R59 0xe8 ;; [80, 71, 176, 232]\n+0x00000170 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x00000174 JMPF $zero 0xa ;; [116, 0, 0, 10]\n+0x00000178 ADDI $writable R59 0x50 ;; [80, 67, 176, 80]\n+0x0000017c SW R59 $zero 0xa ;; [95, 236, 0, 10]\n+0x00000180 LW R17 R21 0x0 ;; [93, 69, 80, 0]\n+0x00000184 LW R17 R17 0x0 ;; [93, 69, 16, 0]\n+0x00000188 LW R22 R21 0x0 ;; [93, 89, 80, 0]\n+0x0000018c ADDI R22 R22 0x8 ;; [80, 89, 96, 8]\n+0x00000190 SW R21 R22 0x0 ;; [95, 85, 96, 0]\n+0x00000194 SW R59 R17 0xb ;; [95, 237, 16, 11]\n+0x00000198 ADDI R17 R59 0xe8 ;; [80, 71, 176, 232]\n+0x0000019c MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x000001a0 MCPI R25 R24 0x8 ;; [96, 101, 128, 8]\n+0x000001a4 ADDI $writable R25 0x8 ;; [80, 65, 144, 8]\n+0x000001a8 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n+0x000001ac ADDI $writable R59 0x28 ;; [80, 67, 176, 40]\n+0x000001b0 MCPI $writable R25 0x18 ;; [96, 65, 144, 24]\n+0x000001b4 MCPI R23 $writable 0x18 ;; [96, 93, 0, 24]\n+0x000001b8 ADDI R18 R18 0x1 ;; [80, 73, 32, 1]\n+0x000001bc JMPB $zero 0x57 ;; [117, 0, 0, 87]\n+0x000001c0 PSHL 0x3ff ;; [149, 0, 3, 255]\n+0x000001c4 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x000001c8 MOVE R59 $sp ;; [26, 236, 80, 0]\n+0x000001cc CFEI 0x4f0 ;; [145, 0, 4, 240]\n+0x000001d0 MOVE R22 R57 ;; [26, 91, 144, 0]\n+0x000001d4 MOVE R21 R62 ;; [26, 87, 224, 0]\n+0x000001d8 ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n+0x000001dc MCPI $writable R58 0x30 ;; [96, 67, 160, 48]\n+0x000001e0 ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n+0x000001e4 ADDI R17 R59 0x1e0 ;; [80, 71, 177, 224]\n+0x000001e8 MOVI R18 0x400 ;; [114, 72, 4, 0]\n+0x000001ec ALOC R18 ;; [38, 72, 0, 0]\n+0x000001f0 ADDI R18 R59 0x90 ;; [80, 75, 176, 144]\n+0x000001f4 SW R59 $hp 0x12 ;; [95, 236, 112, 18]\n+0x000001f8 MOVI R19 0x400 ;; [114, 76, 4, 0]\n+0x000001fc SW R59 R19 0x13 ;; [95, 237, 48, 19]\n+0x00000200 SW R59 $zero 0x14 ;; [95, 236, 0, 20]\n+0x00000204 MCPI R59 R18 0x18 ;; [96, 237, 32, 24]\n+0x00000208 MCPI R17 R59 0x18 ;; [96, 71, 176, 24]\n+0x0000020c ADDI R18 R59 0x4a8 ;; [80, 75, 180, 168]\n+0x00000210 MCPI R18 $writable 0x30 ;; [96, 73, 0, 48]\n+0x00000214 ADDI $writable R59 0x2f0 ;; [80, 67, 178, 240]\n+0x00000218 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x0000021c ADDI $writable R59 0x2f0 ;; [80, 67, 178, 240]\n+0x00000220 ADDI R17 R59 0x368 ;; [80, 71, 179, 104]\n+0x00000224 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000228 MOVI R25 0x0 ;; [114, 100, 0, 0]\n+0x0000022c MOVI $writable 0x2 ;; [114, 64, 0, 2]\n+0x00000230 LT $writable R25 $writable ;; [22, 65, 148, 0]\n+0x00000234 JNZF $writable $zero 0x15 ;; [118, 64, 0, 21]\n+0x00000238 ADDI $writable R59 0x368 ;; [80, 67, 179, 104]\n+0x0000023c ADDI R17 R59 0x2d8 ;; [80, 71, 178, 216]\n+0x00000240 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000244 ADDI $writable R59 0x2d8 ;; [80, 67, 178, 216]\n+0x00000248 ADDI R17 R59 0x4d8 ;; [80, 71, 180, 216]\n+0x0000024c MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000250 ADDI $writable R59 0x4d8 ;; [80, 67, 180, 216]\n+0x00000254 ADDI R17 R59 0x48 ;; [80, 71, 176, 72]\n+0x00000258 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x0000025c ADDI $writable R59 0xc0 ;; [80, 67, 176, 192]\n+0x00000260 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x00000264 ADDI R17 $writable 0x10 ;; [80, 69, 0, 16]\n+0x00000268 ADDI R18 R59 0xf0 ;; [80, 75, 176, 240]\n+0x0000026c MCPI R18 $writable 0x8 ;; [96, 73, 0, 8]\n+0x00000270 ADDI $writable R18 0x8 ;; [80, 65, 32, 8]\n+0x00000274 MCPI $writable R17 0x8 ;; [96, 65, 16, 8]\n+0x00000278 ADDI $writable R59 0x60 ;; [80, 67, 176, 96]\n+0x0000027c MCPI $writable R18 0x10 ;; [96, 65, 32, 16]\n+0x00000280 ADDI R17 R59 0x2b8 ;; [80, 71, 178, 184]\n+0x00000284 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x00000288 JMPF $zero 0x84 ;; [116, 0, 0, 132]\n+0x0000028c ADDI $writable R59 0x4a8 ;; [80, 67, 180, 168]\n+0x00000290 MULI R17 R25 0x18 ;; [85, 69, 144, 24]\n+0x00000294 ADD R17 $writable R17 ;; [16, 69, 4, 64]\n+0x00000298 ADDI $writable R59 0x368 ;; [80, 67, 179, 104]\n+0x0000029c ADDI R18 R59 0x480 ;; [80, 75, 180, 128]\n+0x000002a0 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x000002a4 ADDI R17 R59 0x308 ;; [80, 71, 179, 8]\n+0x000002a8 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x000002ac ADDI $writable R59 0x480 ;; [80, 67, 180, 128]\n+0x000002b0 ADDI R17 R59 0x308 ;; [80, 71, 179, 8]\n+0x000002b4 ADDI R18 R59 0x470 ;; [80, 75, 180, 112]\n+0x000002b8 MCPI R18 $writable 0x8 ;; [96, 73, 0, 8]\n+0x000002bc ADDI $writable R59 0x320 ;; [80, 67, 179, 32]\n+0x000002c0 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x000002c4 ADDI $writable R59 0x470 ;; [80, 67, 180, 112]\n+0x000002c8 ADDI R17 R59 0x320 ;; [80, 71, 179, 32]\n+0x000002cc ADDI R18 R59 0x478 ;; [80, 75, 180, 120]\n 0x000002d0 MCPI R18 $writable 0x8 ;; [96, 73, 0, 8]\n-0x000002d4 ADDI $writable R59 0x320 ;; [80, 67, 179, 32]\n+0x000002d4 ADDI $writable R59 0x338 ;; [80, 67, 179, 56]\n 0x000002d8 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x000002dc ADDI $writable R59 0x470 ;; [80, 67, 180, 112]\n-0x000002e0 ADDI R17 R59 0x320 ;; [80, 71, 179, 32]\n-0x000002e4 ADDI R18 R59 0x478 ;; [80, 75, 180, 120]\n-0x000002e8 MCPI R18 $writable 0x8 ;; [96, 73, 0, 8]\n-0x000002ec ADDI $writable R59 0x338 ;; [80, 67, 179, 56]\n-0x000002f0 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x000002f4 ADDI $writable R59 0x1f8 ;; [80, 67, 177, 248]\n-0x000002f8 ADDI R17 R59 0x338 ;; [80, 71, 179, 56]\n-0x000002fc ADDI R18 R59 0x18 ;; [80, 75, 176, 24]\n-0x00000300 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x00000304 ADDI R17 R59 0xa8 ;; [80, 71, 176, 168]\n-0x00000308 MCPI R17 R18 0x18 ;; [96, 69, 32, 24]\n-0x0000030c LW R17 R59 0x15 ;; [93, 71, 176, 21]\n-0x00000310 LW R24 R59 0x16 ;; [93, 99, 176, 22]\n-0x00000314 LW R18 R59 0x17 ;; [93, 75, 176, 23]\n-0x00000318 ADDI R19 R59 0x478 ;; [80, 79, 180, 120]\n-0x0000031c MOVI R22 0x3 ;; [114, 88, 0, 3]\n-0x00000320 ADD R22 R18 R22 ;; [16, 89, 37, 128]\n-0x00000324 GT R23 R22 R24 ;; [21, 93, 102, 0]\n-0x00000328 JNZF R23 $zero 0x1 ;; [118, 92, 0, 1]\n-0x0000032c JMPF $zero 0x7 ;; [116, 0, 0, 7]\n-0x00000330 MOVI R23 0x2 ;; [114, 92, 0, 2]\n-0x00000334 MUL R23 R24 R23 ;; [27, 93, 133, 192]\n-0x00000338 MOVI R24 0x3 ;; [114, 96, 0, 3]\n-0x0000033c ADD R24 R23 R24 ;; [16, 97, 118, 0]\n-0x00000340 ALOC R24 ;; [38, 96, 0, 0]\n-0x00000344 MCP $hp R17 R18 ;; [40, 29, 20, 128]\n-0x00000348 MOVE R17 $hp ;; [26, 68, 112, 0]\n-0x0000034c ADDI R23 R59 0xe8 ;; [80, 95, 176, 232]\n-0x00000350 MCPI R23 R19 0x8 ;; [96, 93, 48, 8]\n-0x00000354 ADD R18 R17 R18 ;; [16, 73, 20, 128]\n-0x00000358 MCPI R18 R23 0x3 ;; [96, 73, 112, 3]\n-0x0000035c ADDI R18 R59 0x110 ;; [80, 75, 177, 16]\n-0x00000360 SW R59 R17 0x22 ;; [95, 237, 16, 34]\n-0x00000364 SW R59 R24 0x23 ;; [95, 237, 128, 35]\n-0x00000368 SW R59 R22 0x24 ;; [95, 237, 96, 36]\n-0x0000036c ADDI R17 R59 0x30 ;; [80, 71, 176, 48]\n-0x00000370 MCPI R17 R18 0x18 ;; [96, 69, 32, 24]\n-0x00000374 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x00000378 ADDI R17 R59 0x398 ;; [80, 71, 179, 152]\n-0x0000037c MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x00000380 ADDI $writable R59 0x398 ;; [80, 67, 179, 152]\n-0x00000384 ADDI R17 R59 0x380 ;; [80, 71, 179, 128]\n-0x00000388 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x0000038c ADDI $writable R59 0x480 ;; [80, 67, 180, 128]\n-0x00000390 ADDI $writable $writable 0x8 ;; [80, 65, 0, 8]\n-0x00000394 ADDI R17 R59 0x380 ;; [80, 71, 179, 128]\n-0x00000398 ADDI R18 R59 0x498 ;; [80, 75, 180, 152]\n-0x0000039c MCPI R18 $writable 0x10 ;; [96, 73, 0, 16]\n-0x000003a0 ADDI $writable R59 0x350 ;; [80, 67, 179, 80]\n-0x000003a4 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x000003a8 ADDI $writable R59 0x498 ;; [80, 67, 180, 152]\n-0x000003ac ADDI R17 R59 0x158 ;; [80, 71, 177, 88]\n-0x000003b0 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x000003b4 LW $writable R59 0x2b ;; [93, 67, 176, 43]\n-0x000003b8 EQ $writable $writable $zero ;; [19, 65, 0, 0]\n-0x000003bc JNZF $writable $zero 0x1e ;; [118, 64, 0, 30]\n-0x000003c0 LW $writable R59 0x2b ;; [93, 67, 176, 43]\n-0x000003c4 EQ $writable $writable $one ;; [19, 65, 0, 64]\n-0x000003c8 JNZF $writable $zero 0x2 ;; [118, 64, 0, 2]\n-0x000003cc LW $writable R63 0x0 ;; [93, 67, 240, 0]\n-0x000003d0 RVRT $writable ;; [54, 64, 0, 0]\n-0x000003d4 LW $writable R59 0x2c ;; [93, 67, 176, 44]\n-0x000003d8 ADDI R17 R59 0x350 ;; [80, 71, 179, 80]\n-0x000003dc ADDI R18 R59 0x240 ;; [80, 75, 178, 64]\n-0x000003e0 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x000003e4 ADDI R17 R59 0x1a8 ;; [80, 71, 177, 168]\n-0x000003e8 MOVE R58 $one ;; [26, 232, 16, 0]\n-0x000003ec MOVE R57 R18 ;; [26, 229, 32, 0]\n-0x000003f0 MOVE R56 R17 ;; [26, 225, 16, 0]\n-0x000003f4 JAL R62 $pc 0x94 ;; [153, 248, 48, 148]\n-0x000003f8 ADDI R18 R59 0x3f8 ;; [80, 75, 179, 248]\n-0x000003fc MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x00000400 ADDI R17 R59 0x3f8 ;; [80, 71, 179, 248]\n-0x00000404 ADDI R18 R59 0x258 ;; [80, 75, 178, 88]\n-0x00000408 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x0000040c ADDI R17 R59 0x1c0 ;; [80, 71, 177, 192]\n-0x00000410 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000414 MOVE R57 R18 ;; [26, 229, 32, 0]\n-0x00000418 MOVE R56 R17 ;; [26, 225, 16, 0]\n-0x0000041c JAL R62 $pc 0x8a ;; [153, 248, 48, 138]\n-0x00000420 ADDI $writable R59 0x410 ;; [80, 67, 180, 16]\n-0x00000424 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x00000428 ADDI $writable R59 0x410 ;; [80, 67, 180, 16]\n-0x0000042c ADDI R17 R59 0x2a0 ;; [80, 71, 178, 160]\n-0x00000430 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x00000434 JMPF $zero 0x18 ;; [116, 0, 0, 24]\n-0x00000438 LW $writable R59 0x2c ;; [93, 67, 176, 44]\n-0x0000043c ADDI R17 R59 0x350 ;; [80, 71, 179, 80]\n-0x00000440 ADDI R18 R59 0x210 ;; [80, 75, 178, 16]\n-0x00000444 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x00000448 ADDI R17 R59 0x178 ;; [80, 71, 177, 120]\n-0x0000044c MOVE R58 $zero ;; [26, 232, 0, 0]\n-0x00000450 MOVE R57 R18 ;; [26, 229, 32, 0]\n-0x00000454 MOVE R56 R17 ;; [26, 225, 16, 0]\n-0x00000458 JAL R62 $pc 0x7b ;; [153, 248, 48, 123]\n-0x0000045c ADDI R18 R59 0x3b0 ;; [80, 75, 179, 176]\n-0x00000460 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x00000464 ADDI R17 R59 0x3b0 ;; [80, 71, 179, 176]\n-0x00000468 ADDI R18 R59 0x228 ;; [80, 75, 178, 40]\n-0x0000046c MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n-0x00000470 ADDI R17 R59 0x190 ;; [80, 71, 177, 144]\n-0x00000474 MOVE R58 $writable ;; [26, 233, 0, 0]\n-0x00000478 MOVE R57 R18 ;; [26, 229, 32, 0]\n-0x0000047c MOVE R56 R17 ;; [26, 225, 16, 0]\n-0x00000480 JAL R62 $pc 0x71 ;; [153, 248, 48, 113]\n-0x00000484 ADDI $writable R59 0x3e0 ;; [80, 67, 179, 224]\n-0x00000488 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x0000048c ADDI $writable R59 0x3e0 ;; [80, 67, 179, 224]\n-0x00000490 ADDI R17 R59 0x2a0 ;; [80, 71, 178, 160]\n-0x00000494 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x00000498 ADDI $writable R59 0x428 ;; [80, 67, 180, 40]\n-0x0000049c MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x000004a0 ADDI $writable R59 0x428 ;; [80, 67, 180, 40]\n-0x000004a4 ADDI R17 R59 0x3c8 ;; [80, 71, 179, 200]\n-0x000004a8 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x000004ac ADDI $writable R59 0x3c8 ;; [80, 67, 179, 200]\n-0x000004b0 ADDI R17 R59 0x368 ;; [80, 71, 179, 104]\n-0x000004b4 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n-0x000004b8 ADD R25 R25 $one ;; [16, 101, 144, 64]\n-0x000004bc JMPB $zero 0x9e ;; [117, 0, 0, 158]\n-0x000004c0 ADDI $writable R59 0x138 ;; [80, 67, 177, 56]\n-0x000004c4 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n-0x000004c8 LW $writable R63 0x1 ;; [93, 67, 240, 1]\n-0x000004cc LW R17 R59 0x27 ;; [93, 71, 176, 39]\n-0x000004d0 LW R18 R59 0x28 ;; [93, 75, 176, 40]\n-0x000004d4 LOGD $zero $writable R17 R18 ;; [52, 1, 4, 82]\n-0x000004d8 ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n-0x000004dc MOVI R17 0x18 ;; [114, 68, 0, 24]\n-0x000004e0 MUL R17 $zero R17 ;; [27, 68, 4, 64]\n-0x000004e4 ADD R17 $writable R17 ;; [16, 69, 4, 64]\n-0x000004e8 MOVI $writable 0x10 ;; [114, 64, 0, 16]\n-0x000004ec ADD $writable $writable R63 ;; [16, 65, 15, 192]\n-0x000004f0 ADDI R18 R59 0x70 ;; [80, 75, 176, 112]\n-0x000004f4 SW R59 $writable 0xe ;; [95, 237, 0, 14]\n-0x000004f8 MOVI $writable 0x3 ;; [114, 64, 0, 3]\n-0x000004fc SW R59 $writable 0xf ;; [95, 237, 0, 15]\n-0x00000500 ADDI $writable R59 0xd8 ;; [80, 67, 176, 216]\n-0x00000504 MCPI $writable R18 0x10 ;; [96, 65, 32, 16]\n-0x00000508 ADDI R18 R59 0x270 ;; [80, 75, 178, 112]\n-0x0000050c MCPI R18 R17 0x8 ;; [96, 73, 16, 8]\n-0x00000510 ADDI R17 R59 0x278 ;; [80, 71, 178, 120]\n-0x00000514 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x00000518 MOVE R58 R18 ;; [26, 233, 32, 0]\n-0x0000051c MOVE R57 R17 ;; [26, 229, 16, 0]\n-0x00000520 JAL R62 $pc 0x71 ;; [153, 248, 48, 113]\n-0x00000524 EQ $writable R61 $zero ;; [19, 67, 208, 0]\n-0x00000528 JNZF $writable $zero 0x3f ;; [118, 64, 0, 63]\n-0x0000052c ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n-0x00000530 MOVI R17 0x18 ;; [114, 68, 0, 24]\n-0x00000534 MUL R17 $zero R17 ;; [27, 68, 4, 64]\n-0x00000538 ADD R17 $writable R17 ;; [16, 69, 4, 64]\n-0x0000053c ADDI $writable R17 0x8 ;; [80, 65, 16, 8]\n-0x00000540 ADDI R17 R59 0x148 ;; [80, 71, 177, 72]\n-0x00000544 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x00000548 LW $writable R59 0x29 ;; [93, 67, 176, 41]\n-0x0000054c EQ $writable $writable $zero ;; [19, 65, 0, 0]\n-0x00000550 JNZF $writable $zero 0x1 ;; [118, 64, 0, 1]\n-0x00000554 RVRT $one ;; [54, 4, 0, 0]\n-0x00000558 LW $writable R59 0x2a ;; [93, 67, 176, 42]\n-0x0000055c MOVI R17 0x53a ;; [114, 68, 5, 58]\n-0x00000560 EQ $writable $writable R17 ;; [19, 65, 4, 64]\n-0x00000564 EQ $writable $writable $zero ;; [19, 65, 0, 0]\n-0x00000568 JNZF $writable $zero 0x2d ;; [118, 64, 0, 45]\n-0x0000056c ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n-0x00000570 MOVI R17 0x18 ;; [114, 68, 0, 24]\n-0x00000574 MUL R17 $one R17 ;; [27, 68, 20, 64]\n-0x00000578 ADD R17 $writable R17 ;; [16, 69, 4, 64]\n-0x0000057c MOVI $writable 0x18 ;; [114, 64, 0, 24]\n-0x00000580 ADD $writable $writable R63 ;; [16, 65, 15, 192]\n-0x00000584 ADDI R18 R59 0x100 ;; [80, 75, 177, 0]\n-0x00000588 SW R59 $writable 0x20 ;; [95, 237, 0, 32]\n-0x0000058c MOVI $writable 0x3 ;; [114, 64, 0, 3]\n-0x00000590 SW R59 $writable 0x21 ;; [95, 237, 0, 33]\n-0x00000594 ADDI $writable R59 0x128 ;; [80, 67, 177, 40]\n-0x00000598 MCPI $writable R18 0x10 ;; [96, 65, 32, 16]\n-0x0000059c ADDI R18 R59 0x288 ;; [80, 75, 178, 136]\n-0x000005a0 MCPI R18 R17 0x8 ;; [96, 73, 16, 8]\n-0x000005a4 ADDI R17 R59 0x290 ;; [80, 71, 178, 144]\n-0x000005a8 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x000005ac MOVE R58 R18 ;; [26, 233, 32, 0]\n-0x000005b0 MOVE R57 R17 ;; [26, 229, 16, 0]\n-0x000005b4 JAL R62 $pc 0x4c ;; [153, 248, 48, 76]\n-0x000005b8 EQ $writable R61 $zero ;; [19, 67, 208, 0]\n-0x000005bc JNZF $writable $zero 0x16 ;; [118, 64, 0, 22]\n-0x000005c0 ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n-0x000005c4 MOVI R17 0x18 ;; [114, 68, 0, 24]\n-0x000005c8 MUL R17 $one R17 ;; [27, 68, 20, 64]\n-0x000005cc ADD R17 $writable R17 ;; [16, 69, 4, 64]\n-0x000005d0 ADDI $writable R17 0x8 ;; [80, 65, 16, 8]\n-0x000005d4 ADDI R17 R59 0x168 ;; [80, 71, 177, 104]\n-0x000005d8 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n-0x000005dc LW $writable R59 0x2d ;; [93, 67, 176, 45]\n-0x000005e0 EQ $writable $writable $one ;; [19, 65, 0, 64]\n-0x000005e4 JNZF $writable $zero 0x2 ;; [118, 64, 0, 2]\n-0x000005e8 MOVI $writable 0x2 ;; [114, 64, 0, 2]\n-0x000005ec RVRT $writable ;; [54, 64, 0, 0]\n-0x000005f0 LW $writable R59 0x2e ;; [93, 67, 176, 46]\n-0x000005f4 EQ $writable $writable $one ;; [19, 65, 0, 64]\n-0x000005f8 EQ $writable $writable $zero ;; [19, 65, 0, 0]\n-0x000005fc JNZF $writable $zero 0x4 ;; [118, 64, 0, 4]\n-0x00000600 ADDI $writable R59 0x1d8 ;; [80, 67, 177, 216]\n-0x00000604 SW R59 $one 0x3b ;; [95, 236, 16, 59]\n-0x00000608 MCPI R21 $writable 0x8 ;; [96, 85, 0, 8]\n-0x0000060c JMPF $zero 0x8 ;; [116, 0, 0, 8]\n-0x00000610 LW $writable R63 0x4 ;; [93, 67, 240, 4]\n-0x00000614 RVRT $writable ;; [54, 64, 0, 0]\n-0x00000618 LW $writable R63 0x4 ;; [93, 67, 240, 4]\n-0x0000061c RVRT $writable ;; [54, 64, 0, 0]\n-0x00000620 LW $writable R63 0x4 ;; [93, 67, 240, 4]\n-0x00000624 RVRT $writable ;; [54, 64, 0, 0]\n-0x00000628 LW $writable R63 0x4 ;; [93, 67, 240, 4]\n-0x0000062c RVRT $writable ;; [54, 64, 0, 0]\n-0x00000630 CFSI 0x4f0 ;; [146, 0, 4, 240]\n-0x00000634 MOVE R62 R20 ;; [26, 249, 64, 0]\n-0x00000638 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x0000063c POPL 0x3ff ;; [151, 0, 3, 255]\n-0x00000640 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x00000644 PSHL 0x3f ;; [149, 0, 0, 63]\n-0x00000648 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x0000064c MOVE R59 $sp ;; [26, 236, 80, 0]\n-0x00000650 CFEI 0x90 ;; [145, 0, 0, 144]\n-0x00000654 ADDI $writable R59 0x78 ;; [80, 67, 176, 120]\n-0x00000658 MCPI $writable R57 0x18 ;; [96, 67, 144, 24]\n-0x0000065c ADDI $writable R59 0x60 ;; [80, 67, 176, 96]\n-0x00000660 ADDI R17 R59 0x78 ;; [80, 71, 176, 120]\n-0x00000664 MCPI R59 R17 0x18 ;; [96, 237, 16, 24]\n-0x00000668 ADDI R17 R59 0x30 ;; [80, 71, 176, 48]\n-0x0000066c MCPI R17 R59 0x18 ;; [96, 71, 176, 24]\n-0x00000670 LW R17 R59 0x6 ;; [93, 71, 176, 6]\n-0x00000674 LW R21 R59 0x7 ;; [93, 87, 176, 7]\n-0x00000678 LW R18 R59 0x8 ;; [93, 75, 176, 8]\n-0x0000067c MOVI R19 0x8 ;; [114, 76, 0, 8]\n-0x00000680 ADD R19 R18 R19 ;; [16, 77, 36, 192]\n-0x00000684 GT R20 R19 R21 ;; [21, 81, 53, 64]\n-0x00000688 JNZF R20 $zero 0x1 ;; [118, 80, 0, 1]\n-0x0000068c JMPF $zero 0x7 ;; [116, 0, 0, 7]\n-0x00000690 MOVI R20 0x2 ;; [114, 80, 0, 2]\n-0x00000694 MUL R20 R21 R20 ;; [27, 81, 85, 0]\n-0x00000698 MOVI R21 0x8 ;; [114, 84, 0, 8]\n-0x0000069c ADD R21 R20 R21 ;; [16, 85, 69, 64]\n-0x000006a0 ALOC R21 ;; [38, 84, 0, 0]\n-0x000006a4 MCP $hp R17 R18 ;; [40, 29, 20, 128]\n-0x000006a8 MOVE R17 $hp ;; [26, 68, 112, 0]\n-0x000006ac ADD R18 R17 R18 ;; [16, 73, 20, 128]\n-0x000006b0 SW R18 R58 0x0 ;; [95, 75, 160, 0]\n-0x000006b4 ADDI R18 R59 0x48 ;; [80, 75, 176, 72]\n-0x000006b8 SW R59 R17 0x9 ;; [95, 237, 16, 9]\n-0x000006bc SW R59 R21 0xa ;; [95, 237, 80, 10]\n-0x000006c0 SW R59 R19 0xb ;; [95, 237, 48, 11]\n-0x000006c4 ADDI R17 R59 0x18 ;; [80, 71, 176, 24]\n-0x000006c8 MCPI R17 R18 0x18 ;; [96, 69, 32, 24]\n-0x000006cc MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n-0x000006d0 MCPI R56 $writable 0x18 ;; [96, 225, 0, 24]\n-0x000006d4 CFSI 0x90 ;; [146, 0, 0, 144]\n-0x000006d8 POPH 0x80000 ;; [152, 8, 0, 0]\n-0x000006dc POPL 0x3f ;; [151, 0, 0, 63]\n-0x000006e0 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n-0x000006e4 PSHL 0x7 ;; [149, 0, 0, 7]\n-0x000006e8 PSHH 0x80000 ;; [150, 8, 0, 0]\n-0x000006ec MOVE R59 $sp ;; [26, 236, 80, 0]\n-0x000006f0 CFEI 0x28 ;; [145, 0, 0, 40]\n-0x000006f4 ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n-0x000006f8 MCPI $writable R58 0x8 ;; [96, 67, 160, 8]\n-0x000006fc ADDI $writable R59 0x18 ;; [80, 67, 176, 24]\n-0x00000700 MCPI $writable R57 0x10 ;; [96, 67, 144, 16]\n-0x00000704 LW $writable R59 0x3 ;; [93, 67, 176, 3]\n-0x00000708 LW R17 R59 0x4 ;; [93, 71, 176, 4]\n-0x0000070c SW R59 $writable 0x0 ;; [95, 237, 0, 0]\n-0x00000710 SW R59 R17 0x1 ;; [95, 237, 16, 1]\n-0x00000714 LW $writable R59 0x0 ;; [93, 67, 176, 0]\n-0x00000718 ADDI R17 R59 0x10 ;; [80, 71, 176, 16]\n-0x0000071c MOVI R18 0x3 ;; [114, 72, 0, 3]\n-0x00000720 MEQ $writable R17 $writable R18 ;; [41, 65, 20, 18]\n-0x00000724 MOVE R61 $writable ;; [26, 245, 0, 0]\n-0x00000728 CFSI 0x28 ;; [146, 0, 0, 40]\n-0x0000072c POPH 0x80000 ;; [152, 8, 0, 0]\n-0x00000730 POPL 0x7 ;; [151, 0, 0, 7]\n-0x00000734 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000002dc ADDI $writable R59 0x1f8 ;; [80, 67, 177, 248]\n+0x000002e0 ADDI R17 R59 0x338 ;; [80, 71, 179, 56]\n+0x000002e4 ADDI R18 R59 0x18 ;; [80, 75, 176, 24]\n+0x000002e8 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x000002ec ADDI R17 R59 0xa8 ;; [80, 71, 176, 168]\n+0x000002f0 MCPI R17 R18 0x18 ;; [96, 69, 32, 24]\n+0x000002f4 LW R17 R59 0x15 ;; [93, 71, 176, 21]\n+0x000002f8 LW R24 R59 0x16 ;; [93, 99, 176, 22]\n+0x000002fc LW R18 R59 0x17 ;; [93, 75, 176, 23]\n+0x00000300 ADDI R19 R59 0x478 ;; [80, 79, 180, 120]\n+0x00000304 ADDI R20 R18 0x3 ;; [80, 81, 32, 3]\n+0x00000308 GT R23 R20 R24 ;; [21, 93, 70, 0]\n+0x0000030c JNZF R23 $zero 0x1 ;; [118, 92, 0, 1]\n+0x00000310 JMPF $zero 0x5 ;; [116, 0, 0, 5]\n+0x00000314 MULI R23 R24 0x2 ;; [85, 93, 128, 2]\n+0x00000318 ADDI R24 R23 0x3 ;; [80, 97, 112, 3]\n+0x0000031c ALOC R24 ;; [38, 96, 0, 0]\n+0x00000320 MCP $hp R17 R18 ;; [40, 29, 20, 128]\n+0x00000324 MOVE R17 $hp ;; [26, 68, 112, 0]\n+0x00000328 ADDI R23 R59 0xe8 ;; [80, 95, 176, 232]\n+0x0000032c MCPI R23 R19 0x8 ;; [96, 93, 48, 8]\n+0x00000330 ADD R18 R17 R18 ;; [16, 73, 20, 128]\n+0x00000334 MCPI R18 R23 0x3 ;; [96, 73, 112, 3]\n+0x00000338 ADDI R18 R59 0x110 ;; [80, 75, 177, 16]\n+0x0000033c SW R59 R17 0x22 ;; [95, 237, 16, 34]\n+0x00000340 SW R59 R24 0x23 ;; [95, 237, 128, 35]\n+0x00000344 SW R59 R20 0x24 ;; [95, 237, 64, 36]\n+0x00000348 ADDI R17 R59 0x30 ;; [80, 71, 176, 48]\n+0x0000034c MCPI R17 R18 0x18 ;; [96, 69, 32, 24]\n+0x00000350 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x00000354 ADDI R17 R59 0x398 ;; [80, 71, 179, 152]\n+0x00000358 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x0000035c ADDI $writable R59 0x398 ;; [80, 67, 179, 152]\n+0x00000360 ADDI R17 R59 0x380 ;; [80, 71, 179, 128]\n+0x00000364 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000368 ADDI $writable R59 0x480 ;; [80, 67, 180, 128]\n+0x0000036c ADDI $writable $writable 0x8 ;; [80, 65, 0, 8]\n+0x00000370 ADDI R17 R59 0x380 ;; [80, 71, 179, 128]\n+0x00000374 ADDI R18 R59 0x498 ;; [80, 75, 180, 152]\n+0x00000378 MCPI R18 $writable 0x10 ;; [96, 73, 0, 16]\n+0x0000037c ADDI $writable R59 0x350 ;; [80, 67, 179, 80]\n+0x00000380 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x00000384 ADDI $writable R59 0x498 ;; [80, 67, 180, 152]\n+0x00000388 ADDI R17 R59 0x158 ;; [80, 71, 177, 88]\n+0x0000038c MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x00000390 LW $writable R59 0x2b ;; [93, 67, 176, 43]\n+0x00000394 EQ $writable $writable $zero ;; [19, 65, 0, 0]\n+0x00000398 JNZF $writable $zero 0x1e ;; [118, 64, 0, 30]\n+0x0000039c LW $writable R59 0x2b ;; [93, 67, 176, 43]\n+0x000003a0 EQ $writable $writable $one ;; [19, 65, 0, 64]\n+0x000003a4 JNZF $writable $zero 0x2 ;; [118, 64, 0, 2]\n+0x000003a8 LW $writable R63 0x0 ;; [93, 67, 240, 0]\n+0x000003ac RVRT $writable ;; [54, 64, 0, 0]\n+0x000003b0 LW $writable R59 0x2c ;; [93, 67, 176, 44]\n+0x000003b4 ADDI R17 R59 0x350 ;; [80, 71, 179, 80]\n+0x000003b8 ADDI R18 R59 0x240 ;; [80, 75, 178, 64]\n+0x000003bc MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x000003c0 ADDI R17 R59 0x1a8 ;; [80, 71, 177, 168]\n+0x000003c4 MOVI R58 0x1 ;; [114, 232, 0, 1]\n+0x000003c8 MOVE R57 R18 ;; [26, 229, 32, 0]\n+0x000003cc MOVE R56 R17 ;; [26, 225, 16, 0]\n+0x000003d0 JAL R62 $pc 0x8a ;; [153, 248, 48, 138]\n+0x000003d4 ADDI R18 R59 0x3f8 ;; [80, 75, 179, 248]\n+0x000003d8 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x000003dc ADDI R17 R59 0x3f8 ;; [80, 71, 179, 248]\n+0x000003e0 ADDI R18 R59 0x258 ;; [80, 75, 178, 88]\n+0x000003e4 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x000003e8 ADDI R17 R59 0x1c0 ;; [80, 71, 177, 192]\n+0x000003ec MOVE R58 $writable ;; [26, 233, 0, 0]\n+0x000003f0 MOVE R57 R18 ;; [26, 229, 32, 0]\n+0x000003f4 MOVE R56 R17 ;; [26, 225, 16, 0]\n+0x000003f8 JAL R62 $pc 0x80 ;; [153, 248, 48, 128]\n+0x000003fc ADDI $writable R59 0x410 ;; [80, 67, 180, 16]\n+0x00000400 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x00000404 ADDI $writable R59 0x410 ;; [80, 67, 180, 16]\n+0x00000408 ADDI R17 R59 0x2a0 ;; [80, 71, 178, 160]\n+0x0000040c MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000410 JMPF $zero 0x18 ;; [116, 0, 0, 24]\n+0x00000414 LW $writable R59 0x2c ;; [93, 67, 176, 44]\n+0x00000418 ADDI R17 R59 0x350 ;; [80, 71, 179, 80]\n+0x0000041c ADDI R18 R59 0x210 ;; [80, 75, 178, 16]\n+0x00000420 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x00000424 ADDI R17 R59 0x178 ;; [80, 71, 177, 120]\n+0x00000428 MOVI R58 0x0 ;; [114, 232, 0, 0]\n+0x0000042c MOVE R57 R18 ;; [26, 229, 32, 0]\n+0x00000430 MOVE R56 R17 ;; [26, 225, 16, 0]\n+0x00000434 JAL R62 $pc 0x71 ;; [153, 248, 48, 113]\n+0x00000438 ADDI R18 R59 0x3b0 ;; [80, 75, 179, 176]\n+0x0000043c MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x00000440 ADDI R17 R59 0x3b0 ;; [80, 71, 179, 176]\n+0x00000444 ADDI R18 R59 0x228 ;; [80, 75, 178, 40]\n+0x00000448 MCPI R18 R17 0x18 ;; [96, 73, 16, 24]\n+0x0000044c ADDI R17 R59 0x190 ;; [80, 71, 177, 144]\n+0x00000450 MOVE R58 $writable ;; [26, 233, 0, 0]\n+0x00000454 MOVE R57 R18 ;; [26, 229, 32, 0]\n+0x00000458 MOVE R56 R17 ;; [26, 225, 16, 0]\n+0x0000045c JAL R62 $pc 0x67 ;; [153, 248, 48, 103]\n+0x00000460 ADDI $writable R59 0x3e0 ;; [80, 67, 179, 224]\n+0x00000464 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x00000468 ADDI $writable R59 0x3e0 ;; [80, 67, 179, 224]\n+0x0000046c ADDI R17 R59 0x2a0 ;; [80, 71, 178, 160]\n+0x00000470 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000474 ADDI $writable R59 0x428 ;; [80, 67, 180, 40]\n+0x00000478 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x0000047c ADDI $writable R59 0x428 ;; [80, 67, 180, 40]\n+0x00000480 ADDI R17 R59 0x3c8 ;; [80, 71, 179, 200]\n+0x00000484 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000488 ADDI $writable R59 0x3c8 ;; [80, 67, 179, 200]\n+0x0000048c ADDI R17 R59 0x368 ;; [80, 71, 179, 104]\n+0x00000490 MCPI R17 $writable 0x18 ;; [96, 69, 0, 24]\n+0x00000494 ADDI R25 R25 0x1 ;; [80, 101, 144, 1]\n+0x00000498 JMPB $zero 0x9a ;; [117, 0, 0, 154]\n+0x0000049c ADDI $writable R59 0x138 ;; [80, 67, 177, 56]\n+0x000004a0 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n+0x000004a4 LW $writable R63 0x1 ;; [93, 67, 240, 1]\n+0x000004a8 LW R17 R59 0x27 ;; [93, 71, 176, 39]\n+0x000004ac LW R18 R59 0x28 ;; [93, 75, 176, 40]\n+0x000004b0 LOGD $zero $writable R17 R18 ;; [52, 1, 4, 82]\n+0x000004b4 ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n+0x000004b8 MOVI R17 0x10 ;; [114, 68, 0, 16]\n+0x000004bc ADD R17 R17 R63 ;; [16, 69, 31, 192]\n+0x000004c0 ADDI R18 R59 0x70 ;; [80, 75, 176, 112]\n+0x000004c4 SW R59 R17 0xe ;; [95, 237, 16, 14]\n+0x000004c8 MOVI R17 0x3 ;; [114, 68, 0, 3]\n+0x000004cc SW R59 R17 0xf ;; [95, 237, 16, 15]\n+0x000004d0 ADDI R17 R59 0xd8 ;; [80, 71, 176, 216]\n+0x000004d4 MCPI R17 R18 0x10 ;; [96, 69, 32, 16]\n+0x000004d8 ADDI R18 R59 0x270 ;; [80, 75, 178, 112]\n+0x000004dc MCPI R18 $writable 0x8 ;; [96, 73, 0, 8]\n+0x000004e0 ADDI $writable R59 0x278 ;; [80, 67, 178, 120]\n+0x000004e4 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n+0x000004e8 MOVE R58 R18 ;; [26, 233, 32, 0]\n+0x000004ec MOVE R57 $writable ;; [26, 229, 0, 0]\n+0x000004f0 JAL R62 $pc 0x67 ;; [153, 248, 48, 103]\n+0x000004f4 EQ $writable R61 $zero ;; [19, 67, 208, 0]\n+0x000004f8 JNZF $writable $zero 0x38 ;; [118, 64, 0, 56]\n+0x000004fc ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n+0x00000500 ADDI $writable $writable 0x8 ;; [80, 65, 0, 8]\n+0x00000504 ADDI R17 R59 0x148 ;; [80, 71, 177, 72]\n+0x00000508 MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x0000050c LW $writable R59 0x29 ;; [93, 67, 176, 41]\n+0x00000510 EQ $writable $writable $zero ;; [19, 65, 0, 0]\n+0x00000514 JNZF $writable $zero 0x1 ;; [118, 64, 0, 1]\n+0x00000518 RVRT $one ;; [54, 4, 0, 0]\n+0x0000051c LW $writable R59 0x2a ;; [93, 67, 176, 42]\n+0x00000520 MOVI R17 0x53a ;; [114, 68, 5, 58]\n+0x00000524 EQ $writable $writable R17 ;; [19, 65, 4, 64]\n+0x00000528 EQ $writable $writable $zero ;; [19, 65, 0, 0]\n+0x0000052c JNZF $writable $zero 0x29 ;; [118, 64, 0, 41]\n+0x00000530 ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n+0x00000534 ADDI $writable $writable 0x18 ;; [80, 65, 0, 24]\n+0x00000538 MOVI R17 0x18 ;; [114, 68, 0, 24]\n+0x0000053c ADD R17 R17 R63 ;; [16, 69, 31, 192]\n+0x00000540 ADDI R18 R59 0x100 ;; [80, 75, 177, 0]\n+0x00000544 SW R59 R17 0x20 ;; [95, 237, 16, 32]\n+0x00000548 MOVI R17 0x3 ;; [114, 68, 0, 3]\n+0x0000054c SW R59 R17 0x21 ;; [95, 237, 16, 33]\n+0x00000550 ADDI R17 R59 0x128 ;; [80, 71, 177, 40]\n+0x00000554 MCPI R17 R18 0x10 ;; [96, 69, 32, 16]\n+0x00000558 ADDI R18 R59 0x288 ;; [80, 75, 178, 136]\n+0x0000055c MCPI R18 $writable 0x8 ;; [96, 73, 0, 8]\n+0x00000560 ADDI $writable R59 0x290 ;; [80, 67, 178, 144]\n+0x00000564 MCPI $writable R17 0x10 ;; [96, 65, 16, 16]\n+0x00000568 MOVE R58 R18 ;; [26, 233, 32, 0]\n+0x0000056c MOVE R57 $writable ;; [26, 229, 0, 0]\n+0x00000570 JAL R62 $pc 0x47 ;; [153, 248, 48, 71]\n+0x00000574 EQ $writable R61 $zero ;; [19, 67, 208, 0]\n+0x00000578 JNZF $writable $zero 0x14 ;; [118, 64, 0, 20]\n+0x0000057c ADDI $writable R59 0x440 ;; [80, 67, 180, 64]\n+0x00000580 ADDI $writable $writable 0x18 ;; [80, 65, 0, 24]\n+0x00000584 ADDI $writable $writable 0x8 ;; [80, 65, 0, 8]\n+0x00000588 ADDI R17 R59 0x168 ;; [80, 71, 177, 104]\n+0x0000058c MCPI R17 $writable 0x10 ;; [96, 69, 0, 16]\n+0x00000590 LW $writable R59 0x2d ;; [93, 67, 176, 45]\n+0x00000594 EQ $writable $writable $one ;; [19, 65, 0, 64]\n+0x00000598 JNZF $writable $zero 0x2 ;; [118, 64, 0, 2]\n+0x0000059c MOVI $writable 0x2 ;; [114, 64, 0, 2]\n+0x000005a0 RVRT $writable ;; [54, 64, 0, 0]\n+0x000005a4 LW $writable R59 0x2e ;; [93, 67, 176, 46]\n+0x000005a8 EQ $writable $writable $one ;; [19, 65, 0, 64]\n+0x000005ac EQ $writable $writable $zero ;; [19, 65, 0, 0]\n+0x000005b0 JNZF $writable $zero 0x4 ;; [118, 64, 0, 4]\n+0x000005b4 ADDI $writable R59 0x1d8 ;; [80, 67, 177, 216]\n+0x000005b8 SW R59 $one 0x3b ;; [95, 236, 16, 59]\n+0x000005bc MCPI R22 $writable 0x8 ;; [96, 89, 0, 8]\n+0x000005c0 JMPF $zero 0x8 ;; [116, 0, 0, 8]\n+0x000005c4 LW $writable R63 0x4 ;; [93, 67, 240, 4]\n+0x000005c8 RVRT $writable ;; [54, 64, 0, 0]\n+0x000005cc LW $writable R63 0x4 ;; [93, 67, 240, 4]\n+0x000005d0 RVRT $writable ;; [54, 64, 0, 0]\n+0x000005d4 LW $writable R63 0x4 ;; [93, 67, 240, 4]\n+0x000005d8 RVRT $writable ;; [54, 64, 0, 0]\n+0x000005dc LW $writable R63 0x4 ;; [93, 67, 240, 4]\n+0x000005e0 RVRT $writable ;; [54, 64, 0, 0]\n+0x000005e4 CFSI 0x4f0 ;; [146, 0, 4, 240]\n+0x000005e8 MOVE R62 R21 ;; [26, 249, 80, 0]\n+0x000005ec POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000005f0 POPL 0x3ff ;; [151, 0, 3, 255]\n+0x000005f4 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x000005f8 PSHL 0x3f ;; [149, 0, 0, 63]\n+0x000005fc PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000600 MOVE R59 $sp ;; [26, 236, 80, 0]\n+0x00000604 CFEI 0x90 ;; [145, 0, 0, 144]\n+0x00000608 ADDI $writable R59 0x78 ;; [80, 67, 176, 120]\n+0x0000060c MCPI $writable R57 0x18 ;; [96, 67, 144, 24]\n+0x00000610 ADDI $writable R59 0x60 ;; [80, 67, 176, 96]\n+0x00000614 ADDI R17 R59 0x78 ;; [80, 71, 176, 120]\n+0x00000618 MCPI R59 R17 0x18 ;; [96, 237, 16, 24]\n+0x0000061c ADDI R17 R59 0x30 ;; [80, 71, 176, 48]\n+0x00000620 MCPI R17 R59 0x18 ;; [96, 71, 176, 24]\n+0x00000624 LW R17 R59 0x6 ;; [93, 71, 176, 6]\n+0x00000628 LW R21 R59 0x7 ;; [93, 87, 176, 7]\n+0x0000062c LW R18 R59 0x8 ;; [93, 75, 176, 8]\n+0x00000630 ADDI R19 R18 0x8 ;; [80, 77, 32, 8]\n+0x00000634 GT R20 R19 R21 ;; [21, 81, 53, 64]\n+0x00000638 JNZF R20 $zero 0x1 ;; [118, 80, 0, 1]\n+0x0000063c JMPF $zero 0x5 ;; [116, 0, 0, 5]\n+0x00000640 MULI R20 R21 0x2 ;; [85, 81, 80, 2]\n+0x00000644 ADDI R21 R20 0x8 ;; [80, 85, 64, 8]\n+0x00000648 ALOC R21 ;; [38, 84, 0, 0]\n+0x0000064c MCP $hp R17 R18 ;; [40, 29, 20, 128]\n+0x00000650 MOVE R17 $hp ;; [26, 68, 112, 0]\n+0x00000654 ADD R18 R17 R18 ;; [16, 73, 20, 128]\n+0x00000658 SW R18 R58 0x0 ;; [95, 75, 160, 0]\n+0x0000065c ADDI R18 R59 0x48 ;; [80, 75, 176, 72]\n+0x00000660 SW R59 R17 0x9 ;; [95, 237, 16, 9]\n+0x00000664 SW R59 R21 0xa ;; [95, 237, 80, 10]\n+0x00000668 SW R59 R19 0xb ;; [95, 237, 48, 11]\n+0x0000066c ADDI R17 R59 0x18 ;; [80, 71, 176, 24]\n+0x00000670 MCPI R17 R18 0x18 ;; [96, 69, 32, 24]\n+0x00000674 MCPI $writable R17 0x18 ;; [96, 65, 16, 24]\n+0x00000678 MCPI R56 $writable 0x18 ;; [96, 225, 0, 24]\n+0x0000067c CFSI 0x90 ;; [146, 0, 0, 144]\n+0x00000680 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x00000684 POPL 0x3f ;; [151, 0, 0, 63]\n+0x00000688 JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n+0x0000068c PSHL 0x7 ;; [149, 0, 0, 7]\n+0x00000690 PSHH 0x80000 ;; [150, 8, 0, 0]\n+0x00000694 MOVE R59 $sp ;; [26, 236, 80, 0]\n+0x00000698 CFEI 0x28 ;; [145, 0, 0, 40]\n+0x0000069c ADDI $writable R59 0x10 ;; [80, 67, 176, 16]\n+0x000006a0 MCPI $writable R58 0x8 ;; [96, 67, 160, 8]\n+0x000006a4 ADDI $writable R59 0x18 ;; [80, 67, 176, 24]\n+0x000006a8 MCPI $writable R57 0x10 ;; [96, 67, 144, 16]\n+0x000006ac LW $writable R59 0x3 ;; [93, 67, 176, 3]\n+0x000006b0 LW R17 R59 0x4 ;; [93, 71, 176, 4]\n+0x000006b4 SW R59 $writable 0x0 ;; [95, 237, 0, 0]\n+0x000006b8 SW R59 R17 0x1 ;; [95, 237, 16, 1]\n+0x000006bc LW $writable R59 0x0 ;; [93, 67, 176, 0]\n+0x000006c0 ADDI R17 R59 0x10 ;; [80, 71, 176, 16]\n+0x000006c4 MOVI R18 0x3 ;; [114, 72, 0, 3]\n+0x000006c8 MEQ $writable R17 $writable R18 ;; [41, 65, 20, 18]\n+0x000006cc MOVE R61 $writable ;; [26, 245, 0, 0]\n+0x000006d0 CFSI 0x28 ;; [146, 0, 0, 40]\n+0x000006d4 POPH 0x80000 ;; [152, 8, 0, 0]\n+0x000006d8 POPL 0x7 ;; [151, 0, 0, 7]\n+0x000006dc JAL $zero R62 0x0 ;; [153, 3, 224, 0]\n .data_section:\n-0x00000738 .word i14757395258967588866, as hex be bytes ([CC, CC, CC, CC, CC, CC, 00, 02])\n-0x00000740 .word i3647243719605075626, as hex be bytes ([32, 9D, 9C, D6, CC, 55, BE, AA])\n-0x00000748 .bytes as hex ([73, 65, 74]), len i3, as ascii \"set\"\n-0x00000750 .bytes as hex ([61, 64, 64]), len i3, as ascii \"add\"\n-0x00000758 .word i18446744073709486084, as hex be bytes ([FF, FF, FF, FF, FF, FF, 00, 04])\n+0x000006e0 .word i14757395258967588866, as hex be bytes ([CC, CC, CC, CC, CC, CC, 00, 02])\n+0x000006e8 .word i3647243719605075626, as hex be bytes ([32, 9D, 9C, D6, CC, 55, BE, AA])\n+0x000006f0 .bytes as hex ([73, 65, 74]), len i3, as ascii \"set\"\n+0x000006f8 .bytes as hex ([61, 64, 64]), len i3, as ascii \"add\"\n+0x00000700 .word i18446744073709486084, as hex be bytes ([FF, FF, FF, FF, FF, FF, 00, 04])\n ;; --- END OF TARGET BYTECODE ---\n \n- Finished release [optimized + fuel] target(s) [1.888 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.8 KB] in ???\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/match_expressions_all/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/match_expressions_all/stdout.snap\nindex ee2d32cd960..229dc2666bb 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/match_expressions_all/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/match_expressions_all/stdout.snap\n@@ -116,7 +116,7 @@ addi $r2 $$locbase i16 ; get offset to local __ptr slice\n move $$arg0 $r0 ; [call: eq_9]: pass argument 0\n move $$arg1 $r2 ; [call: eq_9]: pass argument 1\n jal $$reta $pc i40 ; [call: eq_9]: call function\n-move $r0 $one ; move parameter from branch to block argument\n+movi $r0 i1 ; move parameter from branch to block argument\n jnzf $$retv $zero i31\n addi $r0 $$locbase i96 ; get offset to local __ptr slice\n addr $r2 data_NonConfigurable_9; get __const_global0's address in data section\n@@ -130,7 +130,7 @@ addi $r2 $$locbase i48 ; get offset to local __ptr slice\n move $$arg0 $r0 ; [call: eq_9]: pass argument 0\n move $$arg1 $r2 ; [call: eq_9]: pass argument 1\n jal $$reta $pc i25 ; [call: eq_9]: call function\n-movi $r0 i2 ; initialize constant into register\n+movi $r0 i2 ; move parameter from branch to block argument\n jnzf $$retv $zero i16\n addi $r0 $$locbase i96 ; get offset to local __ptr slice\n addr $r2 data_NonConfigurable_10; get __const_global1's address in data section\n@@ -144,9 +144,9 @@ addi $r2 $$locbase i80 ; get offset to local __ptr slice\n move $$arg0 $r0 ; [call: eq_9]: pass argument 0\n move $$arg1 $r2 ; [call: eq_9]: pass argument 1\n jal $$reta $pc i10 ; [call: eq_9]: call function\n-movi $r0 i3 ; initialize constant into register\n+movi $r0 i3 ; move parameter from branch to block argument\n jnzf $$retv $zero i1\n-movi $r0 i1000 ; initialize constant into register\n+movi $r0 i1000 ; move parameter from branch to block argument\n move $$retv $r0 ; [fn end: return_match_on_str_slice_8] set return value\n cfsi i112 ; [fn end: return_match_on_str_slice_8] free: locals 112 byte(s), call args 0 slot(s)\n move $$reta $r1 ; [fn end: return_match_on_str_slice_8] restore return address\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panic_handling_in_unit_tests/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panic_handling_in_unit_tests/stdout.snap\nindex a1fc299b0a5..7415f5911c3 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panic_handling_in_unit_tests/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panic_handling_in_unit_tests/stdout.snap\n@@ -18,12 +18,12 @@ warning: Error message is empty\n ____\n \n Compiled script \"panic_handling_in_unit_tests\" with 1 warning.\n- Finished debug [unoptimized + fuel] target(s) [8.216 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [8.152 KB] in ???\n Running 2 tests, filtered 18 tests\n \n tested -- panic_handling_in_unit_tests\n \n- test passing_dbgs_and_logs ... ok (???, 4238 gas)\n+ test passing_dbgs_and_logs ... ok (???, 4094 gas)\n debug output:\n [src/main.sw:23:13] \"This is a passing test containing `__dbg` outputs.\" = \"This is a passing test containing `__dbg` outputs.\"\n [src/main.sw:25:13] x = 42\n@@ -31,7 +31,7 @@ tested -- panic_handling_in_unit_tests\n AsciiString { data: \"This is a log from the passing test.\" }, log rb: 10098701174489624218\n 42, log rb: 1515152261580153489\n raw logs:\n-[{\"LogData\":{\"data\":\"0000000000000024546869732069732061206c6f672066726f6d207468652070617373696e6720746573742e\",\"digest\":\"29d742ad9093cdf81404ff756467a44448729b85ab3c0d65197829fb61d2dd29\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":44,\"pc\":10832,\"ptr\":67107840,\"ra\":0,\"rb\":10098701174489624218}},{\"LogData\":{\"data\":\"000000000000002a\",\"digest\":\"a6bb133cb1e3638ad7b8a3ff0539668e9e56f9b850ef1b2a810f5422eaa6c323\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":15668,\"ptr\":19352,\"ra\":0,\"rb\":1515152261580153489}}]\n+[{\"LogData\":{\"data\":\"0000000000000024546869732069732061206c6f672066726f6d207468652070617373696e6720746573742e\",\"digest\":\"29d742ad9093cdf81404ff756467a44448729b85ab3c0d65197829fb61d2dd29\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":44,\"pc\":10832,\"ptr\":67107840,\"ra\":0,\"rb\":10098701174489624218}},{\"LogData\":{\"data\":\"000000000000002a\",\"digest\":\"a6bb133cb1e3638ad7b8a3ff0539668e9e56f9b850ef1b2a810f5422eaa6c323\",\"id\":\"0000000000000000000000000000000000000000000000000000000000000000\",\"is\":10368,\"len\":8,\"pc\":15632,\"ptr\":19288,\"ra\":0,\"rb\":1515152261580153489}}]\n test passing_no_dbgs_or_logs ... ok (???, 74 gas)\n \n test result: OK. 2 passed; 0 failed; finished in ???\n@@ -55,31 +55,31 @@ warning: Error message is empty\n ____\n \n Compiled script \"panic_handling_in_unit_tests\" with 1 warning.\n- Finished debug [unoptimized + fuel] target(s) [8.216 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [8.152 KB] in ???\n Running 20 tests, filtered 0 tests\n \n tested -- panic_handling_in_unit_tests\n \n- test passing_dbgs_and_logs ... ok (???, 4238 gas)\n+ test passing_dbgs_and_logs ... ok (???, 4094 gas)\n test passing_no_dbgs_or_logs ... ok (???, 74 gas)\n test failing_revert_intrinsic ... FAILED (???, 79 gas)\n- test failing_revert_function_with_dbgs_and_logs ... FAILED (???, 4362 gas)\n+ test failing_revert_function_with_dbgs_and_logs ... FAILED (???, 4210 gas)\n test failing_error_signal_assert ... FAILED (???, 756 gas)\n- test failing_error_signal_assert_eq ... FAILED (???, 2902 gas)\n- test failing_error_signal_assert_ne ... FAILED (???, 2892 gas)\n- test failing_error_signal_require_str_error ... FAILED (???, 954 gas)\n- test failing_error_signal_require_enum_error ... FAILED (???, 1117 gas)\n+ test failing_error_signal_assert_eq ... FAILED (???, 2892 gas)\n+ test failing_error_signal_assert_ne ... FAILED (???, 2882 gas)\n+ test failing_error_signal_require_str_error ... FAILED (???, 952 gas)\n+ test failing_error_signal_require_enum_error ... FAILED (???, 1113 gas)\n test failing_panic_no_arg ... FAILED (???, 611 gas)\n test failing_panic_unit_arg ... FAILED (???, 611 gas)\n test failing_panic_const_eval_str_arg ... FAILED (???, 79 gas)\n test failing_panic_const_eval_empty_str_arg ... FAILED (???, 79 gas)\n test failing_panic_const_eval_whitespace_str_arg ... FAILED (???, 79 gas)\n- test failing_panic_non_const_eval_str_arg ... FAILED (???, 933 gas)\n- test failing_panic_non_const_eval_str_empty_arg ... FAILED (???, 915 gas)\n- test failing_panic_non_const_eval_str_whitespace_arg ... FAILED (???, 919 gas)\n- test failing_panic_error_enum_arg ... FAILED (???, 1079 gas)\n- test failing_panic_error_enum_arg_with_empty_msg ... FAILED (???, 1230 gas)\n- test failing_panic_error_enum_arg_with_whitespace_msg ... FAILED (???, 1259 gas)\n+ test failing_panic_non_const_eval_str_arg ... FAILED (???, 931 gas)\n+ test failing_panic_non_const_eval_str_empty_arg ... FAILED (???, 911 gas)\n+ test failing_panic_non_const_eval_str_whitespace_arg ... FAILED (???, 915 gas)\n+ test failing_panic_error_enum_arg ... FAILED (???, 1075 gas)\n+ test failing_panic_error_enum_arg_with_empty_msg ... FAILED (???, 1222 gas)\n+ test failing_panic_error_enum_arg_with_whitespace_msg ... FAILED (???, 1251 gas)\n \n failures:\n test failing_revert_intrinsic, \"test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panic_handling_in_unit_tests/src/main.sw\":34\n@@ -149,8 +149,8 @@ AsciiString { data: \"We will get logged the asserted values and this message.\" }\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 8,\n- \"pc\": 15668,\n- \"ptr\": 19304,\n+ \"pc\": 15632,\n+ \"ptr\": 19240,\n \"ra\": 0,\n \"rb\": 1515152261580153489\n }\n@@ -162,8 +162,8 @@ AsciiString { data: \"We will get logged the asserted values and this message.\" }\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 8,\n- \"pc\": 15668,\n- \"ptr\": 19304,\n+ \"pc\": 15632,\n+ \"ptr\": 19240,\n \"ra\": 0,\n \"rb\": 1515152261580153489\n }\n@@ -202,8 +202,8 @@ AsciiString { data: \"We will get logged the asserted values and this message.\" }\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 8,\n- \"pc\": 15668,\n- \"ptr\": 19296,\n+ \"pc\": 15632,\n+ \"ptr\": 19232,\n \"ra\": 0,\n \"rb\": 1515152261580153489\n }\n@@ -215,8 +215,8 @@ AsciiString { data: \"We will get logged the asserted values and this message.\" }\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 8,\n- \"pc\": 15668,\n- \"ptr\": 19296,\n+ \"pc\": 15632,\n+ \"ptr\": 19232,\n \"ra\": 0,\n \"rb\": 1515152261580153489\n }\n@@ -287,7 +287,7 @@ B(true), log rb: 8516346929033386016\n \"is\": 10368,\n \"len\": 0,\n \"pc\": 13264,\n- \"ptr\": 18840,\n+ \"ptr\": 18776,\n \"ra\": 0,\n \"rb\": 3330666440490685604\n }\n@@ -312,7 +312,7 @@ B(true), log rb: 8516346929033386016\n \"is\": 10368,\n \"len\": 0,\n \"pc\": 13316,\n- \"ptr\": 18840,\n+ \"ptr\": 18776,\n \"ra\": 0,\n \"rb\": 3330666440490685604\n }\n@@ -413,7 +413,7 @@ AsciiString { data: \" \" }, log rb: 10098701174489624218\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 12,\n- \"pc\": 13664,\n+ \"pc\": 13660,\n \"ptr\": 67107840,\n \"ra\": 0,\n \"rb\": 10098701174489624218\n@@ -439,7 +439,7 @@ B(true), log rb: 8516346929033386016\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 9,\n- \"pc\": 13748,\n+ \"pc\": 13740,\n \"ptr\": 67107840,\n \"ra\": 0,\n \"rb\": 8516346929033386016\n@@ -465,7 +465,7 @@ C(AsciiString { data: \"This is an error with an empty error message.\" }), log rb\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 61,\n- \"pc\": 13852,\n+ \"pc\": 13844,\n \"ptr\": 67107840,\n \"ra\": 0,\n \"rb\": 8516346929033386016\n@@ -491,7 +491,7 @@ D(AsciiString { data: \"This is an error with a whitespace error message.\" }), lo\n \"id\": \"0000000000000000000000000000000000000000000000000000000000000000\",\n \"is\": 10368,\n \"len\": 65,\n- \"pc\": 13956,\n+ \"pc\": 13948,\n \"ptr\": 67107840,\n \"ra\": 0,\n \"rb\": 8516346929033386016\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_contract/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_contract/stdout.snap\nindex 496908b90bd..e023a48d83a 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_contract/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_contract/stdout.snap\n@@ -8,17 +8,17 @@ output:\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling library panicking_lib (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib)\n Compiling contract panicking_contract (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_contract)\n- Finished debug [unoptimized + fuel] target(s) [8.56 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [8.208 KB] in ???\n Running 12 tests, filtered 0 tests\n \n tested -- panicking_contract\n \n- test test_panicking_in_contract_self_impl ... ok (???, 10987 gas)\n+ test test_panicking_in_contract_self_impl ... ok (???, 10941 gas)\n revert code: 828000000000000c\n ├─ panic message: panicking in contract self impl\n ├─ panicked: in <Contract as PanickingContractAbi>::panicking_in_contract_self_impl\n │ └─ at panicking_contract@1.2.3, src/main.sw:22:9\n- test test_directly_panicking_method ... ok (???, 11998 gas)\n+ test test_directly_panicking_method ... ok (???, 11946 gas)\n revert code: 820000000000000b\n ├─ panic message: Error C.\n ├─ panic value: C(true)\n@@ -26,7 +26,7 @@ tested -- panicking_contract\n │ └─ at panicking_contract@1.2.3, src/main.sw:28:9\n decoded log values:\n C(true), log rb: 5503570629422409978\n- test test_nested_panic_inlined ... ok (???, 12722 gas)\n+ test test_nested_panic_inlined ... ok (???, 12632 gas)\n revert code: 8000000000c01001\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -38,7 +38,7 @@ C(true), log rb: 5503570629422409978\n └─ at panicking_contract@1.2.3, src/main.sw:32:9\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_inlined_same_revert_code ... ok (???, 12722 gas)\n+ test test_nested_panic_inlined_same_revert_code ... ok (???, 12632 gas)\n revert code: 8000000000c01001\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -50,7 +50,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_contract@1.2.3, src/main.sw:32:9\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined ... ok (???, 12824 gas)\n+ test test_nested_panic_non_inlined ... ok (???, 12732 gas)\n revert code: 8180000002804808\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -62,7 +62,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_contract@1.2.3, src/main.sw:40:9\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined_same_revert_code ... ok (???, 12824 gas)\n+ test test_nested_panic_non_inlined_same_revert_code ... ok (???, 12732 gas)\n revert code: 8180000002804808\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -74,7 +74,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_contract@1.2.3, src/main.sw:40:9\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 5503570629422409978\n- test test_generic_panic_with_unit ... ok (???, 11449 gas)\n+ test test_generic_panic_with_unit ... ok (???, 11395 gas)\n revert code: 8100000000003806\n ├─ panic value: ()\n ├─ panicked: in panicking_lib::generic_panic\n@@ -83,7 +83,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_contract@1.2.3, src/main.sw:48:9\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_unit_same_revert_code ... ok (???, 11449 gas)\n+ test test_generic_panic_with_unit_same_revert_code ... ok (???, 11395 gas)\n revert code: 8100000000003806\n ├─ panic value: ()\n ├─ panicked: in panicking_lib::generic_panic\n@@ -92,7 +92,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_contract@1.2.3, src/main.sw:48:9\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_str ... ok (???, 11744 gas)\n+ test test_generic_panic_with_str ... ok (???, 11690 gas)\n revert code: 8080000000002804\n ├─ panic message: generic panic with string\n ├─ panicked: in panicking_lib::generic_panic\n@@ -101,7 +101,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_contract@1.2.3, src/main.sw:56:9\n decoded log values:\n AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_different_str_same_revert_code ... ok (???, 11967 gas)\n+ test test_generic_panic_with_different_str_same_revert_code ... ok (???, 11913 gas)\n revert code: 808000000000d019\n ├─ panic message: generic panic with different string\n ├─ panicked: in panicking_lib::generic_panic\n@@ -110,7 +110,7 @@ AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n └─ at panicking_contract@1.2.3, src/main.sw:60:9\n decoded log values:\n AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_error_type_enum ... ok (???, 11893 gas)\n+ test test_generic_panic_with_error_type_enum ... ok (???, 11837 gas)\n revert code: 830000000000700d\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -120,7 +120,7 @@ AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174\n └─ at panicking_contract@1.2.3, src/main.sw:64:9\n decoded log values:\n A, log rb: 5503570629422409978\n- test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 12160 gas)\n+ test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 12104 gas)\n revert code: 830000000000e01b\n ├─ panic message: Error B.\n ├─ panic value: B(42)\n@@ -142,17 +142,17 @@ output:\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling library panicking_lib (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib)\n Compiling contract panicking_contract (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_contract)\n- Finished release [optimized + fuel] target(s) [6.28 KB] in ???\n+ Finished release [optimized + fuel] target(s) [6.168 KB] in ???\n Running 12 tests, filtered 0 tests\n \n tested -- panicking_contract\n \n- test test_panicking_in_contract_self_impl ... ok (???, 10297 gas)\n+ test test_panicking_in_contract_self_impl ... ok (???, 10284 gas)\n revert code: 8280000000000000\n ├─ panic message: panicking in contract self impl\n └─ panicked: in <Contract as PanickingContractAbi>::panicking_in_contract_self_impl\n └─ at panicking_contract@1.2.3, src/main.sw:22:9\n- test test_directly_panicking_method ... ok (???, 11191 gas)\n+ test test_directly_panicking_method ... ok (???, 11174 gas)\n revert code: 8200000000000000\n ├─ panic message: Error C.\n ├─ panic value: C(true)\n@@ -160,7 +160,7 @@ tested -- panicking_contract\n └─ at panicking_contract@1.2.3, src/main.sw:28:9\n decoded log values:\n C(true), log rb: 5503570629422409978\n- test test_nested_panic_inlined ... ok (???, 11831 gas)\n+ test test_nested_panic_inlined ... ok (???, 11786 gas)\n revert code: 8000000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -168,7 +168,7 @@ C(true), log rb: 5503570629422409978\n └─ at panicking_lib, src/lib.sw:35:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_inlined_same_revert_code ... ok (???, 11831 gas)\n+ test test_nested_panic_inlined_same_revert_code ... ok (???, 11786 gas)\n revert code: 8000000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -176,7 +176,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:35:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined ... ok (???, 11885 gas)\n+ test test_nested_panic_non_inlined ... ok (???, 11840 gas)\n revert code: 8180000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -184,7 +184,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:41:9\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined_same_revert_code ... ok (???, 11885 gas)\n+ test test_nested_panic_non_inlined_same_revert_code ... ok (???, 11840 gas)\n revert code: 8180000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -192,35 +192,35 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_lib, src/lib.sw:41:9\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 5503570629422409978\n- test test_generic_panic_with_unit ... ok (???, 10763 gas)\n+ test test_generic_panic_with_unit ... ok (???, 10750 gas)\n revert code: 8100000000000000\n ├─ panic value: ()\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_unit_same_revert_code ... ok (???, 10763 gas)\n+ test test_generic_panic_with_unit_same_revert_code ... ok (???, 10750 gas)\n revert code: 8100000000000000\n ├─ panic value: ()\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_str ... ok (???, 11044 gas)\n+ test test_generic_panic_with_str ... ok (???, 11029 gas)\n revert code: 8080000000000000\n ├─ panic message: generic panic with string\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_different_str_same_revert_code ... ok (???, 11127 gas)\n+ test test_generic_panic_with_different_str_same_revert_code ... ok (???, 11112 gas)\n revert code: 8080000000000000\n ├─ panic message: generic panic with different string\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_error_type_enum ... ok (???, 11096 gas)\n+ test test_generic_panic_with_error_type_enum ... ok (???, 11081 gas)\n revert code: 8300000000000000\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -228,7 +228,7 @@ AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n A, log rb: 5503570629422409978\n- test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 11243 gas)\n+ test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 11228 gas)\n revert code: 8300000000000000\n ├─ panic message: Error B.\n ├─ panic value: B(42)\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib/stdout.snap\nindex 1fc6215a385..77aa31debb8 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib/stdout.snap\n@@ -7,12 +7,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling library panicking_lib (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib)\n- Finished debug [unoptimized + fuel] target(s) [6.88 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [6.712 KB] in ???\n Running 18 tests, filtered 0 tests\n \n tested -- panicking_lib\n \n- test test_nested_panic_inlined ... ok (???, 1991 gas)\n+ test test_nested_panic_inlined ... ok (???, 1953 gas)\n revert code: 8000000000001001\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -24,7 +24,7 @@ tested -- panicking_lib\n └─ at panicking_lib, src/lib.sw:55:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 2721958641300806892\n- test test_nested_panic_inlined_same_revert_code ... ok (???, 1991 gas)\n+ test test_nested_panic_inlined_same_revert_code ... ok (???, 1953 gas)\n revert code: 8000000000001801\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -36,7 +36,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:60:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 2721958641300806892\n- test test_nested_panic_non_inlined ... ok (???, 2027 gas)\n+ test test_nested_panic_non_inlined ... ok (???, 1987 gas)\n revert code: 8080000000002804\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -48,7 +48,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:65:5\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 2721958641300806892\n- test test_nested_panic_non_inlined_same_revert_code ... ok (???, 2027 gas)\n+ test test_nested_panic_non_inlined_same_revert_code ... ok (???, 1987 gas)\n revert code: 8080000000003004\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -60,7 +60,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_lib, src/lib.sw:70:5\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 2721958641300806892\n- test test_generic_panic_with_unit ... ok (???, 621 gas)\n+ test test_generic_panic_with_unit ... ok (???, 619 gas)\n revert code: 8100000000000007\n ├─ panic value: ()\n ├─ panicked: in panicking_lib::generic_panic\n@@ -69,7 +69,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_lib, src/lib.sw:83:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_unit_same_revert_code ... ok (???, 621 gas)\n+ test test_generic_panic_with_unit_same_revert_code ... ok (???, 619 gas)\n revert code: 8100000000000008\n ├─ panic value: ()\n ├─ panicked: in panicking_lib::generic_panic\n@@ -78,7 +78,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_lib, src/lib.sw:88:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_str ... ok (???, 920 gas)\n+ test test_generic_panic_with_str ... ok (???, 916 gas)\n revert code: 8180000000000009\n ├─ panic message: generic panic with string\n ├─ panicked: in panicking_lib::generic_panic\n@@ -87,7 +87,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_lib, src/lib.sw:93:5\n decoded log values:\n AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_different_str_same_revert_code ... ok (???, 921 gas)\n+ test test_generic_panic_with_different_str_same_revert_code ... ok (???, 917 gas)\n revert code: 818000000000000a\n ├─ panic message: generic panic different string\n ├─ panicked: in panicking_lib::generic_panic\n@@ -96,7 +96,7 @@ AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n └─ at panicking_lib, src/lib.sw:98:5\n decoded log values:\n AsciiString { data: \"generic panic different string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_error_type_enum_variant ... ok (???, 1028 gas)\n+ test test_generic_panic_with_error_type_enum_variant ... ok (???, 1022 gas)\n revert code: 820000000000000b\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -106,7 +106,7 @@ AsciiString { data: \"generic panic different string\" }, log rb: 1009870117448962\n └─ at panicking_lib, src/lib.sw:103:5\n decoded log values:\n A, log rb: 2721958641300806892\n- test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 1028 gas)\n+ test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 1022 gas)\n revert code: 820000000000000c\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -135,7 +135,7 @@ A, log rb: 2721958641300806892\n ├─ panic message: panic with string\n └─ panicked: in panicking_lib::test_panic_with_str\n └─ at panicking_lib, src/lib.sw:123:5\n- test test_panic_with_error_type_enum ... ok (???, 1212 gas)\n+ test test_panic_with_error_type_enum ... ok (???, 1206 gas)\n revert code: 8400000000000000\n ├─ panic message: Error C.\n ├─ panic value: C(true)\n@@ -143,28 +143,28 @@ A, log rb: 2721958641300806892\n └─ at panicking_lib, src/lib.sw:128:5\n decoded log values:\n C(true), log rb: 2721958641300806892\n- test test_panic_with_generic_error_type_enum ... ok (???, 993 gas)\n+ test test_panic_with_generic_error_type_enum ... ok (???, 985 gas)\n revert code: 8480000000000000\n ├─ panic value: A(42)\n └─ panicked: in panicking_lib::test_panic_with_generic_error_type_enum\n └─ at panicking_lib, src/lib.sw:133:5\n decoded log values:\n A(42), log rb: 12408470889216862137\n- test test_panic_with_nested_generic_error_type ... ok (???, 1499 gas)\n+ test test_panic_with_nested_generic_error_type ... ok (???, 1485 gas)\n revert code: 8500000000000000\n ├─ panic value: B(B(C(true)))\n └─ panicked: in panicking_lib::test_panic_with_nested_generic_error_type\n └─ at panicking_lib, src/lib.sw:138:5\n decoded log values:\n B(B(C(true))), log rb: 14988555917426256081\n- test test_panic_with_generic_error_type_enum_with_abi_encode ... ok (???, 993 gas)\n+ test test_panic_with_generic_error_type_enum_with_abi_encode ... ok (???, 985 gas)\n revert code: 8580000000000000\n ├─ panic value: A(42)\n └─ panicked: in panicking_lib::test_panic_with_generic_error_type_enum_with_abi_encode\n └─ at panicking_lib, src/lib.sw:143:5\n decoded log values:\n A(42), log rb: 17388243649088655852\n- test test_panic_with_nested_generic_error_type_enum_with_abi_encode ... ok (???, 1499 gas)\n+ test test_panic_with_nested_generic_error_type_enum_with_abi_encode ... ok (???, 1485 gas)\n revert code: 8600000000000000\n ├─ panic value: B(B(C(true)))\n └─ panicked: in panicking_lib::test_panic_with_nested_generic_error_type_enum_with_abi_encode\n@@ -182,12 +182,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling library panicking_lib (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib)\n- Finished release [optimized + fuel] target(s) [4.416 KB] in ???\n+ Finished release [optimized + fuel] target(s) [4.312 KB] in ???\n Running 18 tests, filtered 0 tests\n \n tested -- panicking_lib\n \n- test test_nested_panic_inlined ... ok (???, 1695 gas)\n+ test test_nested_panic_inlined ... ok (???, 1663 gas)\n revert code: 8000000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -195,7 +195,7 @@ tested -- panicking_lib\n └─ at panicking_lib, src/lib.sw:35:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 2721958641300806892\n- test test_nested_panic_inlined_same_revert_code ... ok (???, 1695 gas)\n+ test test_nested_panic_inlined_same_revert_code ... ok (???, 1663 gas)\n revert code: 8000000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -203,7 +203,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:35:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 2721958641300806892\n- test test_nested_panic_non_inlined ... ok (???, 1727 gas)\n+ test test_nested_panic_non_inlined ... ok (???, 1695 gas)\n revert code: 8080000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -211,7 +211,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:41:9\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 2721958641300806892\n- test test_nested_panic_non_inlined_same_revert_code ... ok (???, 1727 gas)\n+ test test_nested_panic_non_inlined_same_revert_code ... ok (???, 1695 gas)\n revert code: 8080000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -233,21 +233,21 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_str ... ok (???, 854 gas)\n+ test test_generic_panic_with_str ... ok (???, 852 gas)\n revert code: 8180000000000000\n ├─ panic message: generic panic with string\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_different_str_same_revert_code ... ok (???, 855 gas)\n+ test test_generic_panic_with_different_str_same_revert_code ... ok (???, 853 gas)\n revert code: 8180000000000000\n ├─ panic message: generic panic different string\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n AsciiString { data: \"generic panic different string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_error_type_enum_variant ... ok (???, 900 gas)\n+ test test_generic_panic_with_error_type_enum_variant ... ok (???, 898 gas)\n revert code: 8200000000000000\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -255,7 +255,7 @@ AsciiString { data: \"generic panic different string\" }, log rb: 1009870117448962\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n A, log rb: 2721958641300806892\n- test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 900 gas)\n+ test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 898 gas)\n revert code: 8200000000000000\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -282,7 +282,7 @@ A, log rb: 2721958641300806892\n ├─ panic message: panic with string\n └─ panicked: in panicking_lib::test_panic_with_str\n └─ at panicking_lib, src/lib.sw:123:5\n- test test_panic_with_error_type_enum ... ok (???, 1058 gas)\n+ test test_panic_with_error_type_enum ... ok (???, 1054 gas)\n revert code: 8400000000000000\n ├─ panic message: Error C.\n ├─ panic value: C(true)\n@@ -290,28 +290,28 @@ A, log rb: 2721958641300806892\n └─ at panicking_lib, src/lib.sw:128:5\n decoded log values:\n C(true), log rb: 2721958641300806892\n- test test_panic_with_generic_error_type_enum ... ok (???, 908 gas)\n+ test test_panic_with_generic_error_type_enum ... ok (???, 904 gas)\n revert code: 8480000000000000\n ├─ panic value: A(42)\n └─ panicked: in panicking_lib::test_panic_with_generic_error_type_enum\n └─ at panicking_lib, src/lib.sw:133:5\n decoded log values:\n A(42), log rb: 12408470889216862137\n- test test_panic_with_nested_generic_error_type ... ok (???, 1308 gas)\n+ test test_panic_with_nested_generic_error_type ... ok (???, 1300 gas)\n revert code: 8500000000000000\n ├─ panic value: B(B(C(true)))\n └─ panicked: in panicking_lib::test_panic_with_nested_generic_error_type\n └─ at panicking_lib, src/lib.sw:138:5\n decoded log values:\n B(B(C(true))), log rb: 14988555917426256081\n- test test_panic_with_generic_error_type_enum_with_abi_encode ... ok (???, 908 gas)\n+ test test_panic_with_generic_error_type_enum_with_abi_encode ... ok (???, 904 gas)\n revert code: 8580000000000000\n ├─ panic value: A(42)\n └─ panicked: in panicking_lib::test_panic_with_generic_error_type_enum_with_abi_encode\n └─ at panicking_lib, src/lib.sw:143:5\n decoded log values:\n A(42), log rb: 17388243649088655852\n- test test_panic_with_nested_generic_error_type_enum_with_abi_encode ... ok (???, 1308 gas)\n+ test test_panic_with_nested_generic_error_type_enum_with_abi_encode ... ok (???, 1300 gas)\n revert code: 8600000000000000\n ├─ panic value: B(B(C(true)))\n └─ panicked: in panicking_lib::test_panic_with_nested_generic_error_type_enum_with_abi_encode\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_script/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_script/stdout.snap\nindex a7f3f6fe266..d658366d3c1 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_script/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_script/stdout.snap\n@@ -8,12 +8,12 @@ output:\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling library panicking_lib (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib)\n Compiling script panicking_script (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_script)\n- Finished debug [unoptimized + fuel] target(s) [3.928 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [3.768 KB] in ???\n Running 11 tests, filtered 0 tests\n \n tested -- panicking_script\n \n- test test_panic_in_main ... ok (???, 1123 gas)\n+ test test_panic_in_main ... ok (???, 1117 gas)\n revert code: 8000000000000000\n ├─ panic message: Error C.\n ├─ panic value: C(true)\n@@ -21,7 +21,7 @@ tested -- panicking_script\n └─ at panicking_script, src/main.sw:6:5\n decoded log values:\n C(true), log rb: 5503570629422409978\n- test test_nested_panic_inlined ... ok (???, 1926 gas)\n+ test test_nested_panic_inlined ... ok (???, 1888 gas)\n revert code: 8080000000001001\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -33,7 +33,7 @@ C(true), log rb: 5503570629422409978\n └─ at panicking_script, src/main.sw:16:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_inlined_same_revert_code ... ok (???, 1926 gas)\n+ test test_nested_panic_inlined_same_revert_code ... ok (???, 1888 gas)\n revert code: 8080000000001801\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -45,7 +45,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_script, src/main.sw:21:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined ... ok (???, 1960 gas)\n+ test test_nested_panic_non_inlined ... ok (???, 1920 gas)\n revert code: 8100000000002804\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -57,7 +57,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_script, src/main.sw:26:5\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined_same_revert_code ... ok (???, 1960 gas)\n+ test test_nested_panic_non_inlined_same_revert_code ... ok (???, 1920 gas)\n revert code: 8100000000003004\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -69,7 +69,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_script, src/main.sw:31:5\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 5503570629422409978\n- test test_generic_panic_with_unit ... ok (???, 607 gas)\n+ test test_generic_panic_with_unit ... ok (???, 605 gas)\n revert code: 8180000000000007\n ├─ panic value: ()\n ├─ panicked: in panicking_lib::generic_panic\n@@ -78,7 +78,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_script, src/main.sw:36:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_unit_same_revert_code ... ok (???, 607 gas)\n+ test test_generic_panic_with_unit_same_revert_code ... ok (???, 605 gas)\n revert code: 8180000000000008\n ├─ panic value: ()\n ├─ panicked: in panicking_lib::generic_panic\n@@ -87,7 +87,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_script, src/main.sw:41:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_str ... ok (???, 920 gas)\n+ test test_generic_panic_with_str ... ok (???, 916 gas)\n revert code: 8200000000000009\n ├─ panic message: generic panic with string\n ├─ panicked: in panicking_lib::generic_panic\n@@ -96,7 +96,7 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_script, src/main.sw:46:5\n decoded log values:\n AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_different_str_same_revert_code ... ok (???, 923 gas)\n+ test test_generic_panic_with_different_str_same_revert_code ... ok (???, 919 gas)\n revert code: 820000000000000a\n ├─ panic message: generic panic with different string\n ├─ panicked: in panicking_lib::generic_panic\n@@ -105,7 +105,7 @@ AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n └─ at panicking_script, src/main.sw:51:5\n decoded log values:\n AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_error_type_enum ... ok (???, 961 gas)\n+ test test_generic_panic_with_error_type_enum ... ok (???, 955 gas)\n revert code: 828000000000000b\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -115,7 +115,7 @@ AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174\n └─ at panicking_script, src/main.sw:56:5\n decoded log values:\n A, log rb: 5503570629422409978\n- test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 1096 gas)\n+ test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 1090 gas)\n revert code: 828000000000000c\n ├─ panic message: Error B.\n ├─ panic value: B(42)\n@@ -137,12 +137,12 @@ output:\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling library panicking_lib (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_lib)\n Compiling script panicking_script (test/src/e2e_vm_tests/test_programs/should_pass/language/panic_expression/panicking_script)\n- Finished release [optimized + fuel] target(s) [3.136 KB] in ???\n+ Finished release [optimized + fuel] target(s) [3.032 KB] in ???\n Running 11 tests, filtered 0 tests\n \n tested -- panicking_script\n \n- test test_panic_in_main ... ok (???, 986 gas)\n+ test test_panic_in_main ... ok (???, 982 gas)\n revert code: 8000000000000000\n ├─ panic message: Error C.\n ├─ panic value: C(true)\n@@ -150,7 +150,7 @@ tested -- panicking_script\n └─ at panicking_script, src/main.sw:6:5\n decoded log values:\n C(true), log rb: 5503570629422409978\n- test test_nested_panic_inlined ... ok (???, 1653 gas)\n+ test test_nested_panic_inlined ... ok (???, 1621 gas)\n revert code: 8080000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -158,7 +158,7 @@ C(true), log rb: 5503570629422409978\n └─ at panicking_lib, src/lib.sw:35:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_inlined_same_revert_code ... ok (???, 1653 gas)\n+ test test_nested_panic_inlined_same_revert_code ... ok (???, 1621 gas)\n revert code: 8080000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }])\n@@ -166,7 +166,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:35:5\n decoded log values:\n E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString { data: \"in error enum variants\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined ... ok (???, 1683 gas)\n+ test test_nested_panic_non_inlined ... ok (???, 1651 gas)\n revert code: 8100000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -174,7 +174,7 @@ E([AsciiString { data: \"to have\" }, AsciiString { data: \"strings\" }, AsciiString\n └─ at panicking_lib, src/lib.sw:41:9\n decoded log values:\n E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }]), log rb: 5503570629422409978\n- test test_nested_panic_non_inlined_same_revert_code ... ok (???, 1683 gas)\n+ test test_nested_panic_non_inlined_same_revert_code ... ok (???, 1651 gas)\n revert code: 8100000000000000\n ├─ panic message: Error E.\n ├─ panic value: E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { data: \"the best practice\" }])\n@@ -196,21 +196,21 @@ E([AsciiString { data: \"this\" }, AsciiString { data: \"is not\" }, AsciiString { d\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n (), log rb: 3330666440490685604\n- test test_generic_panic_with_str ... ok (???, 854 gas)\n+ test test_generic_panic_with_str ... ok (???, 852 gas)\n revert code: 8200000000000000\n ├─ panic message: generic panic with string\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n AsciiString { data: \"generic panic with string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_different_str_same_revert_code ... ok (???, 857 gas)\n+ test test_generic_panic_with_different_str_same_revert_code ... ok (???, 855 gas)\n revert code: 8200000000000000\n ├─ panic message: generic panic with different string\n └─ panicked: in panicking_lib::generic_panic\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174489624218\n- test test_generic_panic_with_error_type_enum ... ok (???, 856 gas)\n+ test test_generic_panic_with_error_type_enum ... ok (???, 854 gas)\n revert code: 8280000000000000\n ├─ panic message: Error A.\n ├─ panic value: A\n@@ -218,7 +218,7 @@ AsciiString { data: \"generic panic with different string\" }, log rb: 10098701174\n └─ at panicking_lib, src/lib.sw:74:5\n decoded log values:\n A, log rb: 5503570629422409978\n- test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 957 gas)\n+ test test_generic_panic_with_error_type_enum_different_variant_same_revert_code ... ok (???, 955 gas)\n revert code: 8280000000000000\n ├─ panic message: Error B.\n ├─ panic value: B(42)\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/src/main.sw\nindex 181b2a51b61..c923670eac1 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/src/main.sw\n@@ -14,8 +14,15 @@ fn leaf_fn_7(a: u64, b: u64, c: u64, d: u64, e: u64, f: u64, g: u64) -> u64 {\n a + b + c + d + e + f + g\n }\n \n+#[inline(never)]\n+fn leaf_fn_caller() {\n+ leaf_fn_6(0, 1, 2, 3, 4, 5);\n+}\n+\n fn main() {\n leaf_fn_0();\n leaf_fn_6(0, 1, 2, 3, 4, 5);\n leaf_fn_7(0, 1, 2, 3, 4, 5, 6);\n+\n+ leaf_fn_caller();\n }\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/stdout.snap\nindex c5d0768a74b..04fd4f109ed 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/optimisations/leaf_fns/stdout.snap\n@@ -5,31 +5,45 @@ source: test/src/snapshot/mod.rs\n \n fn leaf_fn_0_1() -> () {\n entry():\n- v23v1 = const unit ()\n- ret () v23v1\n+ v24v1 = const unit ()\n+ ret () v24v1\n }\n \n \n fn leaf_fn_6_2(a: u64, b: u64, c: u64, d: u64, e: u64, f: u64) -> u64 {\n entry(a: u64, b: u64, c: u64, d: u64, e: u64, f: u64):\n- v31v1 = add a, b\n- v32v1 = add v31v1, c\n- v33v1 = add v32v1, d\n- v34v1 = add v33v1, e\n- v35v1 = add v34v1, f\n- ret u64 v35v1\n+ v32v1 = add a, b\n+ v33v1 = add v32v1, c\n+ v34v1 = add v33v1, d\n+ v35v1 = add v34v1, e\n+ v36v1 = add v35v1, f\n+ ret u64 v36v1\n }\n \n \n fn leaf_fn_7_4(a: u64, b: u64, c: u64, d: u64, e: u64, f: u64, g: u64) -> u64 {\n entry(a: u64, b: u64, c: u64, d: u64, e: u64, f: u64, g: u64):\n- v44v1 = add a, b\n- v45v1 = add v44v1, c\n- v46v1 = add v45v1, d\n- v47v1 = add v46v1, e\n- v48v1 = add v47v1, f\n- v49v1 = add v48v1, g\n- ret u64 v49v1\n+ v45v1 = add a, b\n+ v46v1 = add v45v1, c\n+ v47v1 = add v46v1, d\n+ v48v1 = add v47v1, e\n+ v49v1 = add v48v1, f\n+ v50v1 = add v49v1, g\n+ ret u64 v50v1\n+}\n+\n+\n+fn leaf_fn_caller_5() -> () {\n+ entry():\n+ v52v1 = const u64 0\n+ v53v1 = const u64 1\n+ v54v1 = const u64 2\n+ v55v1 = const u64 3\n+ v56v1 = const u64 4\n+ v57v1 = const u64 5\n+ v58v1 = call leaf_fn_6_2(v52v1, v53v1, v54v1, v55v1, v56v1, v57v1)\n+ v59v1 = const unit ()\n+ ret () v59v1\n }\n \n \n@@ -67,3 +81,21 @@ move $$retv $r0 ; [fn end: leaf_fn_7_4] set return value\n poph i524288 ; [fn end: leaf_fn_7_4]: restore used high registers 40..64\n popl i7 ; [fn end: leaf_fn_7_4]: restore used low registers 16..40\n jal $zero $$reta i0 ; [fn end: leaf_fn_7_4] return from call\n+\n+\n+\n+pshl i1 ; [fn init: leaf_fn_caller_5]: push used low registers 16..40\n+pshh i524288 ; [fn init: leaf_fn_caller_5]: push used high registers 40..64\n+move $r0 $$reta ; [fn init: leaf_fn_caller_5]: save return address\n+movi $$arg0 i0 ; [call: leaf_fn_6_2]: pass argument 0\n+movi $$arg1 i1 ; [call: leaf_fn_6_2]: pass argument 1\n+movi $$arg2 i2 ; [call: leaf_fn_6_2]: pass argument 2\n+movi $$arg3 i3 ; [call: leaf_fn_6_2]: pass argument 3\n+movi $$arg4 i4 ; [call: leaf_fn_6_2]: pass argument 4\n+movi $$arg5 i5 ; [call: leaf_fn_6_2]: pass argument 5\n+subi $$tmp $pc i136 ; load far jump target address\n+jal $$reta $$tmp i0 ; [call: leaf_fn_6_2]: call function\n+move $$reta $r0 ; [fn end: leaf_fn_caller_5] restore return address\n+poph i524288 ; [fn end: leaf_fn_caller_5]: restore used high registers 40..64\n+popl i1 ; [fn end: leaf_fn_caller_5]: restore used low registers 16..40\n+jal $zero $$reta i0 ; [fn end: leaf_fn_caller_5] return from call\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/panic_in_non_statement_positions/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/panic_in_non_statement_positions/stdout.snap\nindex d18e5e261f9..c51b4c33dfb 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/panic_in_non_statement_positions/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/panic_in_non_statement_positions/stdout.snap\n@@ -286,7 +286,7 @@ warning\n ____\n \n Compiled library \"panic_in_non_statement_positions\" with 23 warnings.\n- Finished debug [unoptimized + fuel] target(s) [1.936 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [1.92 KB] in ???\n Running 16 tests, filtered 0 tests\n \n tested -- panic_in_non_statement_positions\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/array_of_structs_caller/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/array_of_structs_caller/src/main.sw\nindex 6863bbe7554..bc198c5356b 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/array_of_structs_caller/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/array_of_structs_caller/src/main.sw\n@@ -6,7 +6,7 @@ use std::hash::*;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0x14ed3cd06c2947248f69d54bfa681fe40d26267be84df7e19e253622b7921bbe;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0xfdb499f3ef8cb08c6526b32a31785e9a85f3953ee2bfcc0c10ad0744d2663ae9; // AUTO-CONTRACT-ID ../../test_contracts/array_of_structs_contract --release\n+const CONTRACT_ID = 0x25499281c906d7476f199828a999f4d653475409a2be224a05eb7ecc3506413f; // AUTO-CONTRACT-ID ../../test_contracts/array_of_structs_contract --release\n \n fn get_address() -> Option<std::address::Address> {\n Some(CONTRACT_ID.into())\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/asset_ops_test/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/asset_ops_test/src/main.sw\nindex c341339b607..e14bc805e13 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/asset_ops_test/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/asset_ops_test/src/main.sw\n@@ -9,12 +9,12 @@ use test_fuel_coin_abi::*;\n #[cfg(experimental_new_encoding = false)]\n const FUEL_COIN_CONTRACT_ID = 0xec2277ebe007ade87e3d797c3b1e070dcd542d5ef8f038b471f262ef9cebc87c;\n #[cfg(experimental_new_encoding = true)]\n-const FUEL_COIN_CONTRACT_ID = 0xd2ebf3d23df570e5552503f91275474b709a851740c3e345489a726c71c1b495; // AUTO-CONTRACT-ID ../../test_contracts/test_fuel_coin_contract --release\n+const FUEL_COIN_CONTRACT_ID = 0x8313df57ac10501f42e0a5e417a6c250665e6469b3f81f37bf0ea3e4d2545a53; // AUTO-CONTRACT-ID ../../test_contracts/test_fuel_coin_contract --release\n \n #[cfg(experimental_new_encoding = false)]\n const BALANCE_CONTRACT_ID = 0xf6cd545152ac83225e8e7df2efb5c6fa6e37bc9b9e977b5ea8103d28668925df;\n #[cfg(experimental_new_encoding = true)]\n-const BALANCE_CONTRACT_ID = 0x5f15eb17bbad0c13e6c654891bb3026de5c5bab5a9e430c2512fb07cada88bde; // AUTO-CONTRACT-ID ../../test_contracts/balance_test_contract --release\n+const BALANCE_CONTRACT_ID = 0xc52bcc86b51ab9c9317963924d72b73220c49eae934f94594824b0aac151c153; // AUTO-CONTRACT-ID ../../test_contracts/balance_test_contract --release\n \n fn main() -> bool {\n let default_gas = 1_000_000_000_000;\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/bal_opcode/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/bal_opcode/src/main.sw\nindex 41d4cd7aede..1610991a80b 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/bal_opcode/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/bal_opcode/src/main.sw\n@@ -5,7 +5,7 @@ use balance_test_abi::BalanceTest;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0xf6cd545152ac83225e8e7df2efb5c6fa6e37bc9b9e977b5ea8103d28668925df;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0x5f15eb17bbad0c13e6c654891bb3026de5c5bab5a9e430c2512fb07cada88bde; // AUTO-CONTRACT-ID ../../test_contracts/balance_test_contract --release\n+const CONTRACT_ID = 0xc52bcc86b51ab9c9317963924d72b73220c49eae934f94594824b0aac151c153; // AUTO-CONTRACT-ID ../../test_contracts/balance_test_contract --release\n \n fn main() -> bool {\n let balance_test_contract = abi(BalanceTest, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_abi_with_tuples/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_abi_with_tuples/src/main.sw\nindex cd1a9527406..4cb6515856c 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_abi_with_tuples/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_abi_with_tuples/src/main.sw\n@@ -6,7 +6,7 @@ use abi_with_tuples::{MyContract, Location, Person};\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0xfdc14550c8aee742cd556d0ab7f378b7be0d3b1e6e086c097352e94590d4ed02;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0x85ee6a61c4701d923a7cf6bbc53af68f483fd75f7b33d899bf3dfa695ff44ea9; // AUTO-CONTRACT-ID ../../test_contracts/abi_with_tuples_contract --release\n+const CONTRACT_ID = 0x9df81c8cc4551bf06e9de097b162c317ef2023c455771faad844f564c666abee; // AUTO-CONTRACT-ID ../../test_contracts/abi_with_tuples_contract --release\n \n fn main() -> bool {\n let the_abi = abi(MyContract, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_basic_storage/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_basic_storage/src/main.sw\nindex 1e572b093ff..6e8c3c3aafb 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_basic_storage/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_basic_storage/src/main.sw\n@@ -4,7 +4,7 @@ use basic_storage_abi::{BasicStorage, Quad};\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0x94db39f409a31b9f2ebcadeea44378e419208c20de90f5d8e1e33dc1523754cb;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0x5a5db729a6a7b0d51bb31f9086d611a3cd5a41f55584f705215aa0a06cc80307; // AUTO-CONTRACT-ID ../../test_contracts/basic_storage --release\n+const CONTRACT_ID = 0x0273e8c30397bcb30a3774bf34eec8a1a03a45466f4c61a26d6d35daea793278; // AUTO-CONTRACT-ID ../../test_contracts/basic_storage --release\n \n fn main() -> u64 {\n let addr = abi(BasicStorage, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_contract_with_type_aliases/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_contract_with_type_aliases/src/main.sw\nindex a1c7556e7f8..ab899fdd730 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_contract_with_type_aliases/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_contract_with_type_aliases/src/main.sw\n@@ -5,7 +5,7 @@ use contract_with_type_aliases_abi::*;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0x0cbeb6efe3104b460be769bdc4ea101ebf16ccc16f2d7b667ec3e1c7f5ce35b5;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0x27cd76082c266c3932659d998af77387c77cffeeff3d3e1e895f033db45e24b0; // AUTO-CONTRACT-ID ../../test_contracts/contract_with_type_aliases --release\n+const CONTRACT_ID = 0x1876ff2cb4808dca4ab2bf2363217aa6ef352878d01820b83771045a711e4a27; // AUTO-CONTRACT-ID ../../test_contracts/contract_with_type_aliases --release\n \n fn main() {\n let caller = abi(MyContract, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_increment_contract/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_increment_contract/src/main.sw\nindex 62d20eb5532..72412fe3c88 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_increment_contract/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_increment_contract/src/main.sw\n@@ -6,7 +6,7 @@ use dynamic_contract_call::*;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0xd1b4047af7ef111c023ab71069e01dc2abfde487c0a0ce1268e4f447e6c6e4c2;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0xe0345f719080837a4f9d5402d1bf38016706ab52eab84c3d905c237bdeb88f2f; // AUTO-CONTRACT-ID ../../test_contracts/increment_contract --release\n+const CONTRACT_ID = 0x597cdb3d93dfcdec55769791ec006b6f4c94735af43e081dd584f144b0fde0ef; // AUTO-CONTRACT-ID ../../test_contracts/increment_contract --release\n \n fn main() -> bool {\n let the_abi = abi(Incrementor, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_storage_enum/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_storage_enum/src/main.sw\nindex f7b768ff9ed..4098d56703d 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_storage_enum/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/call_storage_enum/src/main.sw\n@@ -5,7 +5,7 @@ use storage_enum_abi::*;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0xc601d11767195485a6654d566c67774134668863d8c797a8c69e8778fb1f89e9;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0xe01ac8dd5609e9d72122e5a29058d336c4f6497f2339f67c1e32417f05e6a2ec; // AUTO-CONTRACT-ID ../../test_contracts/storage_enum_contract --release\n+const CONTRACT_ID = 0x1708051773ed8e0a8efa574bcff9064e65c4418f90dc15e0b54f6993cb88a6db; // AUTO-CONTRACT-ID ../../test_contracts/storage_enum_contract --release\n \n fn main() -> u64 {\n let caller = abi(StorageEnum, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_auth_test/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_auth_test/src/main.sw\nindex f993e40564a..2e17fefdd2c 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_auth_test/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_auth_test/src/main.sw\n@@ -5,7 +5,7 @@ use auth_testing_abi::AuthTesting;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0xc2eec20491b53aab7232cbd27c31d15417b4e9daf0b89c74cc242ef1295f681f;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0x251dd84ae6824faa56ef5d28b173a30a13ec60927ae9a263d49a782562869a53; // AUTO-CONTRACT-ID ../../test_contracts/auth_testing_contract --release\n+const CONTRACT_ID = 0x2b7f4ae22a2224c130c5b5a4a5601dac21a342b3c0180b83a71a6f953f3a5013; // AUTO-CONTRACT-ID ../../test_contracts/auth_testing_contract --release\n \n // should be false in the case of a script\n fn main() -> bool {\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_context_test/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_context_test/src/main.sw\nindex b1dc8918311..a28dac9b2f7 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_context_test/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/caller_context_test/src/main.sw\n@@ -6,7 +6,7 @@ use context_testing_abi::*;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0x6054c11cda000f5990373a4d61929396165be4dfdd61d5b7bd26da60ab0d8577;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0xee8668b2bd34b20705e2f8968efa1c665ad3a260711e444138283c2e038e1c93; // AUTO-CONTRACT-ID ../../test_contracts/context_testing_contract --release\n+const CONTRACT_ID = 0x4f74781865601d02fc0667e47c768cf780b69cc1b9cfbb9eb858bf51d5ec420f; // AUTO-CONTRACT-ID ../../test_contracts/context_testing_contract --release\n \n fn main() -> bool {\n let gas: u64 = u64::max();\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/nested_struct_args_caller/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/nested_struct_args_caller/src/main.sw\nindex e15ebdc70cc..0c016d932e2 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/nested_struct_args_caller/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/nested_struct_args_caller/src/main.sw\n@@ -5,7 +5,7 @@ use nested_struct_args_abi::*;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0xe63d33a1b3a6903808b379f6a41a72fa8a370e8b76626775e7d9d2f9c4c5da40;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0x4cde5d51b89548cc2b4a28be3d7d98b1b310b583d53d66849d16c7d60818a82a; // AUTO-CONTRACT-ID ../../test_contracts/nested_struct_args_contract --release\n+const CONTRACT_ID = 0x31fa30bb8554ae45b0bcbe24b3fbc6609a81054f902655e35b2cc7277add1369; // AUTO-CONTRACT-ID ../../test_contracts/nested_struct_args_contract --release\n \n fn main() -> bool {\n let caller = abi(NestedStructArgs, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/storage_access_caller/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/storage_access_caller/src/main.sw\nindex 48e31d85317..12b8bb29e23 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/storage_access_caller/src/main.sw\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/require_contract_deployment/storage_access_caller/src/main.sw\n@@ -6,7 +6,7 @@ use std::hash::*;\n #[cfg(experimental_new_encoding = false)]\n const CONTRACT_ID = 0x3bc28acd66d327b8c1b9624c1fabfc07e9ffa1b5d71c2832c3bfaaf8f4b805e9;\n #[cfg(experimental_new_encoding = true)]\n-const CONTRACT_ID = 0x35ec6adb91969d7d65cbf0136e54a79b9fd630cea295a11f727dd8420bf946bc; // AUTO-CONTRACT-ID ../../test_contracts/storage_access_contract --release\n+const CONTRACT_ID = 0x44ef9b4bbc0178cbdb7070eab3eb4f9de25d85a3015e3845d8cfe93ed938e661; // AUTO-CONTRACT-ID ../../test_contracts/storage_access_contract --release\n \n fn main() -> bool {\n let caller = abi(StorageAccess, CONTRACT_ID);\ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics/stdout.snap\nindex 50650e519bd..43fdf0ab686 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics/stdout.snap\n@@ -7,12 +7,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-conversions)\n Compiling library intrinsics (test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics)\n- Finished debug [unoptimized + fuel] target(s) [1.312 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [1.288 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- intrinsics\n \n- test t ... ok (???, 1936 gas)\n+ test t ... ok (???, 1926 gas)\n decoded log values:\n 16, log rb: 1515152261580153489\n \n@@ -26,12 +26,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-conversions)\n Compiling library intrinsics (test/src/e2e_vm_tests/test_programs/should_pass/stdlib/intrinsics)\n- Finished debug [unoptimized + fuel] target(s) [1.312 KB] in ???\n+ Finished debug [unoptimized + fuel] target(s) [1.288 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- intrinsics\n \n- test t ... ok (???, 1936 gas)\n+ test t ... ok (???, 1926 gas)\n decoded log values:\n 11, log rb: 1515152261580153489\n \ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call/stdout.snap\nindex a5d1c772b09..19452a6c625 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call/stdout.snap\n@@ -7,40 +7,40 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [19 KB] in ???\n+ Finished release [optimized + fuel] target(s) [18.76 KB] in ???\n Running 29 tests, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test cost_of_in_bool ... ok (???, 11137 gas)\n- test cost_of_in_u8 ... ok (???, 11059 gas)\n- test cost_of_in_u16 ... ok (???, 11378 gas)\n- test cost_of_in_u32 ... ok (???, 11605 gas)\n- test cost_of_in_u64 ... ok (???, 10857 gas)\n- test cost_of_in_u256 ... ok (???, 10898 gas)\n- test cost_of_in_b256 ... ok (???, 10880 gas)\n- test cost_of_in_str_0 ... ok (???, 11376 gas)\n- test cost_of_in_str_1 ... ok (???, 11549 gas)\n- test cost_of_in_str_8 ... ok (???, 11568 gas)\n- test cost_of_in_str_16 ... ok (???, 11561 gas)\n- test cost_of_in_str_32 ... ok (???, 11575 gas)\n- test cost_of_in_array_0 ... ok (???, 10823 gas)\n- test cost_of_in_array_1 ... ok (???, 10910 gas)\n- test cost_of_in_array_8 ... ok (???, 11435 gas)\n- test cost_of_in_array_16 ... ok (???, 10944 gas)\n- test cost_of_in_array_32 ... ok (???, 10998 gas)\n- test cost_of_in_array_64 ... ok (???, 11098 gas)\n- test cost_of_in_tuple_0 ... ok (???, 10848 gas)\n- test cost_of_in_tuple_1 ... ok (???, 10946 gas)\n- test cost_of_in_tuple_2 ... ok (???, 10955 gas)\n- test cost_of_in_tuple_3 ... ok (???, 10968 gas)\n- test cost_of_in_tuple_4 ... ok (???, 10979 gas)\n- test in_struct_u64 ... ok (???, 10915 gas)\n- test in_struct_u64_u64 ... ok (???, 10946 gas)\n- test in_struct_u64_u64_u64 ... ok (???, 10966 gas)\n- test in_enum_u64 ... ok (???, 11048 gas)\n- test in_enum_u64_u64 ... ok (???, 11043 gas)\n- test in_enum_u64_u64_u64 ... ok (???, 11059 gas)\n+ test cost_of_in_bool ... ok (???, 11120 gas)\n+ test cost_of_in_u8 ... ok (???, 11042 gas)\n+ test cost_of_in_u16 ... ok (???, 11351 gas)\n+ test cost_of_in_u32 ... ok (???, 11568 gas)\n+ test cost_of_in_u64 ... ok (???, 10840 gas)\n+ test cost_of_in_u256 ... ok (???, 10881 gas)\n+ test cost_of_in_b256 ... ok (???, 10863 gas)\n+ test cost_of_in_str_0 ... ok (???, 11359 gas)\n+ test cost_of_in_str_1 ... ok (???, 11532 gas)\n+ test cost_of_in_str_8 ... ok (???, 11543 gas)\n+ test cost_of_in_str_16 ... ok (???, 11536 gas)\n+ test cost_of_in_str_32 ... ok (???, 11550 gas)\n+ test cost_of_in_array_0 ... ok (???, 10806 gas)\n+ test cost_of_in_array_1 ... ok (???, 10887 gas)\n+ test cost_of_in_array_8 ... ok (???, 11418 gas)\n+ test cost_of_in_array_16 ... ok (???, 10927 gas)\n+ test cost_of_in_array_32 ... ok (???, 10981 gas)\n+ test cost_of_in_array_64 ... ok (???, 11081 gas)\n+ test cost_of_in_tuple_0 ... ok (???, 10831 gas)\n+ test cost_of_in_tuple_1 ... ok (???, 10929 gas)\n+ test cost_of_in_tuple_2 ... ok (???, 10938 gas)\n+ test cost_of_in_tuple_3 ... ok (???, 10951 gas)\n+ test cost_of_in_tuple_4 ... ok (???, 10962 gas)\n+ test in_struct_u64 ... ok (???, 10898 gas)\n+ test in_struct_u64_u64 ... ok (???, 10929 gas)\n+ test in_struct_u64_u64_u64 ... ok (???, 10949 gas)\n+ test in_enum_u64 ... ok (???, 11023 gas)\n+ test in_enum_u64_u64 ... ok (???, 11018 gas)\n+ test in_enum_u64_u64_u64 ... ok (???, 11034 gas)\n \n test result: OK. 29 passed; 0 failed; finished in ???\n \n@@ -60,7 +60,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_array_0 ... ok (???, 10183 gas)\n+ test isolated_cost_of_in_array_0 ... ok (???, 10180 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -75,12 +75,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [744 B] in ???\n+ Finished release [optimized + fuel] target(s) [728 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_array_1 ... ok (???, 10260 gas)\n+ test isolated_cost_of_in_array_1 ... ok (???, 10251 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -100,7 +100,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_array_16 ... ok (???, 10296 gas)\n+ test isolated_cost_of_in_array_16 ... ok (???, 10293 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -120,7 +120,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_array_32 ... ok (???, 10342 gas)\n+ test isolated_cost_of_in_array_32 ... ok (???, 10339 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -140,7 +140,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_array_64 ... ok (???, 10430 gas)\n+ test isolated_cost_of_in_array_64 ... ok (???, 10427 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -155,12 +155,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [792 B] in ???\n+ Finished release [optimized + fuel] target(s) [784 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_array_8 ... ok (???, 10780 gas)\n+ test isolated_cost_of_in_array_8 ... ok (???, 10778 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -180,7 +180,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_b256 ... ok (???, 10262 gas)\n+ test isolated_cost_of_in_b256 ... ok (???, 10259 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -195,12 +195,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.048 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.04 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_bool ... ok (???, 10446 gas)\n+ test isolated_cost_of_in_bool ... ok (???, 10443 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -215,12 +215,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [880 B] in ???\n+ Finished release [optimized + fuel] target(s) [872 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test in_enum_u64 ... ok (???, 10373 gas)\n+ test in_enum_u64 ... ok (???, 10362 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -235,12 +235,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [928 B] in ???\n+ Finished release [optimized + fuel] target(s) [912 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test in_enum_u64_u64 ... ok (???, 10385 gas)\n+ test in_enum_u64_u64 ... ok (???, 10374 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -255,12 +255,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [992 B] in ???\n+ Finished release [optimized + fuel] target(s) [976 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test in_enum_u64_u64_u64 ... ok (???, 10393 gas)\n+ test in_enum_u64_u64_u64 ... ok (???, 10382 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -275,12 +275,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.152 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.144 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_str_0 ... ok (???, 10644 gas)\n+ test isolated_cost_of_in_str_0 ... ok (???, 10641 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -295,12 +295,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.376 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.368 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_str_1 ... ok (???, 10836 gas)\n+ test isolated_cost_of_in_str_1 ... ok (???, 10833 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -315,12 +315,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.424 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.408 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_str_16 ... ok (???, 10855 gas)\n+ test isolated_cost_of_in_str_16 ... ok (???, 10843 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -335,12 +335,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.44 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.424 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_str_32 ... ok (???, 10860 gas)\n+ test isolated_cost_of_in_str_32 ... ok (???, 10848 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -355,12 +355,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.392 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.376 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_str_8 ... ok (???, 10851 gas)\n+ test isolated_cost_of_in_str_8 ... ok (???, 10839 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -380,7 +380,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test in_struct_u64 ... ok (???, 10254 gas)\n+ test in_struct_u64 ... ok (???, 10251 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -395,12 +395,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [840 B] in ???\n+ Finished release [optimized + fuel] target(s) [824 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test in_struct_u64_u64 ... ok (???, 10271 gas)\n+ test in_struct_u64_u64 ... ok (???, 10268 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -415,12 +415,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [864 B] in ???\n+ Finished release [optimized + fuel] target(s) [848 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test in_struct_u64_u64_u64 ... ok (???, 10275 gas)\n+ test in_struct_u64_u64_u64 ... ok (???, 10272 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -435,12 +435,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [632 B] in ???\n+ Finished release [optimized + fuel] target(s) [624 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_tuple_0 ... ok (???, 10180 gas)\n+ test isolated_cost_of_in_tuple_0 ... ok (???, 10178 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -460,7 +460,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_tuple_1 ... ok (???, 10254 gas)\n+ test isolated_cost_of_in_tuple_1 ... ok (???, 10251 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -475,12 +475,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [824 B] in ???\n+ Finished release [optimized + fuel] target(s) [808 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_tuple_2 ... ok (???, 10270 gas)\n+ test isolated_cost_of_in_tuple_2 ... ok (???, 10267 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -495,12 +495,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [848 B] in ???\n+ Finished release [optimized + fuel] target(s) [832 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_tuple_3 ... ok (???, 10274 gas)\n+ test isolated_cost_of_in_tuple_3 ... ok (???, 10271 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -515,12 +515,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [880 B] in ???\n+ Finished release [optimized + fuel] target(s) [856 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_tuple_4 ... ok (???, 10276 gas)\n+ test isolated_cost_of_in_tuple_4 ... ok (???, 10273 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -535,12 +535,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.24 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.216 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_u16 ... ok (???, 10743 gas)\n+ test isolated_cost_of_in_u16 ... ok (???, 10729 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -560,7 +560,7 @@ output:\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_u256 ... ok (???, 10262 gas)\n+ test isolated_cost_of_in_u256 ... ok (???, 10259 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -575,12 +575,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [1.344 KB] in ???\n+ Finished release [optimized + fuel] target(s) [1.312 KB] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_u32 ... ok (???, 10960 gas)\n+ test isolated_cost_of_in_u32 ... ok (???, 10935 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -595,12 +595,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [688 B] in ???\n+ Finished release [optimized + fuel] target(s) [680 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_u64 ... ok (???, 10232 gas)\n+ test isolated_cost_of_in_u64 ... ok (???, 10230 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \n@@ -615,12 +615,12 @@ output:\n Building test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call\n Compiling library std (test/src/e2e_vm_tests/reduced_std_libs/sway-lib-std-core)\n Compiling contract const_of_contract_call (test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/const_of_contract_call)\n- Finished release [optimized + fuel] target(s) [992 B] in ???\n+ Finished release [optimized + fuel] target(s) [984 B] in ???\n Running 1 test, filtered 0 tests\n \n tested -- const_of_contract_call\n \n- test isolated_cost_of_in_u8 ... ok (???, 10388 gas)\n+ test isolated_cost_of_in_u8 ... ok (???, 10386 gas)\n \n test result: OK. 1 passed; 0 failed; finished in ???\n \ndiff --git a/test/src/e2e_vm_tests/test_programs/should_pass/unused_return_value/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/unused_return_value/stdout.snap\nindex dc9db5c8e25..431eb44bd64 100644\n--- a/test/src/e2e_vm_tests/test_programs/should_pass/unused_return_value/stdout.snap\n+++ b/test/src/e2e_vm_tests/test_programs/should_pass/unused_return_value/stdout.snap\n@@ -1,6 +1,5 @@\n ---\n source: test/src/snapshot/mod.rs\n-assertion_line: 266\n ---\n > forc build --path test/src/e2e_vm_tests/test_programs/should_pass/unused_return_value\n exit status: 0\ndiff --git a/test/src/ir_generation/tests/fn_call_nolocals.sw b/test/src/ir_generation/tests/fn_call_nolocals.sw\nindex bcd8a959e2e..1fe9d3c6d73 100644\n--- a/test/src/ir_generation/tests/fn_call_nolocals.sw\n+++ b/test/src/ir_generation/tests/fn_call_nolocals.sw\n@@ -27,11 +27,8 @@ fn main() -> u64 {\n \n // ::check-asm::\n \n-// regex: IMM=i\\d+\n-// regex: REG=\\$[[:alpha:]][0-9[:alpha:]]*\n-\n-// check: move $$$$arg0 $REG\n-// check: move $$$$arg1 $REG\n-// check: move $$$$arg2 $REG\n-// check: jal $$$$reta $$pc i2\n+// check: movi $$$$arg0 i1\n+// check: movi $$$$arg1 i10\n+// check: movi $$$$arg2 i100\n+// check: jal $$$$reta $$pc i2 ; [call: g_0]: call function\n // check: ret $$$$retv\ndiff --git a/test/src/sdk-harness/test_projects/auth/mod.rs b/test/src/sdk-harness/test_projects/auth/mod.rs\nindex 8b8be4cc6e5..dd602c57faf 100644\n--- a/test/src/sdk-harness/test_projects/auth/mod.rs\n+++ b/test/src/sdk-harness/test_projects/auth/mod.rs\n@@ -585,7 +585,7 @@ async fn can_get_predicate_address() {\n \n // Setup predicate.\n let hex_predicate_address: &str =\n- \"0xf9acc710533729d33e311df5dcbddca07898135691656fc6a95c77fdb36b0940\";\n+ \"0x0b1879dfdd67643f907375e9511e865cdaaf71802f3e4f97f91aa366b598db44\";\n let predicate_address =\n Address::from_str(hex_predicate_address).expect(\"failed to create Address from string\");\n let predicate_data = AuthPredicateEncoder::default()\n@@ -710,7 +710,7 @@ async fn when_incorrect_predicate_address_passed() {\n async fn can_get_predicate_address_in_message() {\n // Setup predicate address.\n let hex_predicate_address: &str =\n- \"0xf9acc710533729d33e311df5dcbddca07898135691656fc6a95c77fdb36b0940\";\n+ \"0x0b1879dfdd67643f907375e9511e865cdaaf71802f3e4f97f91aa366b598db44\";\n let predicate_address =\n Address::from_str(hex_predicate_address).expect(\"failed to create Address from string\");\n \n"},"merged":{"kind":"bool","value":true,"string":"true"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":41,"numItemsPerPage":100,"numTotalItems":87912,"offset":4100,"length":100}},"jwt":"eyJhbGciOiJFZERTQSIsImtpZCI6Im1sR1pFYktIVHRVSGRhX1RRdEczQ0N1S3k5ME9Qd25DNHY5elRjM3FVYzgifQ.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc4MjgwNDg3MCwianRpIjoiNzk0ZWE1ZmMtMjAxZi00ZjljLTg2NzgtMTdiOTY2YWZkYWI4Iiwic3ViIjoiL2RhdGFzZXRzL1BvdGF0b0hEL2dpdGh1Yi1wci1yZXNvbHZlIiwiZXhwIjoxNzgyODA4NDcwLCJpc3MiOiJodHRwczovL2h1Z2dpbmdmYWNlLmNvIn0.pmLc1I12a-rAFSaFsbc7YZyDlQM23-DmiSE-y5s0UIak4y4w1RKaqx_74tGynQWlUTf5s-WMAnkvrYvoqeR-Cg","displayUrls":true,"splitSizeSummaries":[{"config":"default","split":"train","numRows":87912,"numBytesParquet":1412740926}]},"discussionsStats":{"closed":0,"open":0,"total":0},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
repo stringlengths 5 53 | pr_number int32 1 321k | task_type stringclasses 2
values | issue_text stringlengths 0 81.2k | pr_title stringlengths 1 319 | pr_body stringlengths 0 105k | base_sha stringlengths 40 40 | head_sha stringlengths 40 40 | gold_diff stringlengths 0 202M | changed_files listlengths 0 100 | review_threads listlengths 0 100 | test_patch stringlengths 0 23.4M | merged bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
FuelLabs/sway | 7,614 | comment_to_fix | Implement dynamic storage based `StorageVec` | ### Incorrect `from_parts` count causes excessive storage writes
**Medium Severity**
<!-- DESCRIPTION START -->
In the quads-based `store_vec`, `raw_slice::from_parts::<V>(ptr, number_of_words)` incorrectly passes `number_of_words` (which is a byte count: `size_V_bytes_padded * vec.len()`) as the `count` parameter. S... | 514ccec75cccc818254f09e0c284db2c78b2ec2a | ecc2c92ea28c187e76d47f70d6de0024c884c202 | diff --git a/sway-lib-std/src/storage/storage_vec.sw b/sway-lib-std/src/storage/storage_vec.sw
index c1c2073fdd9..369b7de24dc 100644
--- a/sway-lib-std/src/storage/storage_vec.sw
+++ b/sway-lib-std/src/storage/storage_vec.sw
@@ -10,14 +10,89 @@ use ::vec::Vec;
use ::iterator::Iterator;
use ::codec::*;
use ::debug::*... | [
"sway-lib-std/src/storage/storage_vec.sw"
] | [
{
"comment": "### Incorrect `from_parts` count causes excessive storage writes\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nIn the quads-based `store_vec`, `raw_slice::from_parts::<V>(ptr, number_of_words)` incorrectly passes `number_of_words` (which is a byte count: `size_V_bytes_padded * vec.len()`) ... | true | ||
FuelLabs/sway | 7,614 | comment_to_fix | Implement dynamic storage based `StorageVec` | What is the difference from the declaration above? I am only seeing a small diff on the doc-comments. I think it makes more sense to keep just one and make the difference more explicit. | 514ccec75cccc818254f09e0c284db2c78b2ec2a | ecc2c92ea28c187e76d47f70d6de0024c884c202 | diff --git a/sway-lib-std/src/storage/storage_vec.sw b/sway-lib-std/src/storage/storage_vec.sw
index c1c2073fdd9..369b7de24dc 100644
--- a/sway-lib-std/src/storage/storage_vec.sw
+++ b/sway-lib-std/src/storage/storage_vec.sw
@@ -10,14 +10,89 @@ use ::vec::Vec;
use ::iterator::Iterator;
use ::codec::*;
use ::debug::*... | [
"sway-lib-std/src/storage/storage_vec.sw"
] | [
{
"comment": "What is the difference from the declaration above? I am only seeing a small diff on the doc-comments. I think it makes more sense to keep just one and make the difference more explicit.",
"path": "sway-lib-std/src/storage/storage_vec.sw",
"hunk": "@@ -10,14 +10,89 @@ use ::vec::Vec;\n use ... | true | ||
FuelLabs/sway | 7,614 | comment_to_fix | Implement dynamic storage based `StorageVec` | ```suggestion
/// will remain in the storage.**
``` | 514ccec75cccc818254f09e0c284db2c78b2ec2a | ecc2c92ea28c187e76d47f70d6de0024c884c202 | diff --git a/sway-lib-std/src/storage/storage_vec.sw b/sway-lib-std/src/storage/storage_vec.sw
index c1c2073fdd9..369b7de24dc 100644
--- a/sway-lib-std/src/storage/storage_vec.sw
+++ b/sway-lib-std/src/storage/storage_vec.sw
@@ -10,14 +10,89 @@ use ::vec::Vec;
use ::iterator::Iterator;
use ::codec::*;
use ::debug::*... | [
"sway-lib-std/src/storage/storage_vec.sw"
] | [
{
"comment": "```suggestion\n /// will remain in the storage.**\n```",
"path": "sway-lib-std/src/storage/storage_vec.sw",
"hunk": "@@ -34,33 +109,48 @@ impl<V> StorageKey<StorageVec<V>> {\n /// use std::storage::storage_vec::*;\n ///\n /// storage {\n- /// vec: StorageVec<u64> = St... | true | ||
FuelLabs/sway | 7,614 | comment_to_fix | Implement dynamic storage based `StorageVec` | ```suggestion
/// but the nested content of those removed elements will remain in the storage.**
``` | 514ccec75cccc818254f09e0c284db2c78b2ec2a | ecc2c92ea28c187e76d47f70d6de0024c884c202 | diff --git a/sway-lib-std/src/storage/storage_vec.sw b/sway-lib-std/src/storage/storage_vec.sw
index c1c2073fdd9..369b7de24dc 100644
--- a/sway-lib-std/src/storage/storage_vec.sw
+++ b/sway-lib-std/src/storage/storage_vec.sw
@@ -10,14 +10,89 @@ use ::vec::Vec;
use ::iterator::Iterator;
use ::codec::*;
use ::debug::*... | [
"sway-lib-std/src/storage/storage_vec.sw"
] | [
{
"comment": "```suggestion\n /// but the nested content of those removed elements will remain in the storage.**\n```",
"path": "sway-lib-std/src/storage/storage_vec.sw",
"hunk": "@@ -724,13 +854,17 @@ impl<V> StorageKey<StorageVec<V>> {\n /// # Additional Information\n ///\n /// If `new_... | true | ||
FuelLabs/sway | 7,614 | comment_to_fix | Implement dynamic storage based `StorageVec` | ```suggestion
/// will remain in the storage.
``` | 514ccec75cccc818254f09e0c284db2c78b2ec2a | ecc2c92ea28c187e76d47f70d6de0024c884c202 | diff --git a/sway-lib-std/src/storage/storage_vec.sw b/sway-lib-std/src/storage/storage_vec.sw
index c1c2073fdd9..369b7de24dc 100644
--- a/sway-lib-std/src/storage/storage_vec.sw
+++ b/sway-lib-std/src/storage/storage_vec.sw
@@ -10,14 +10,89 @@ use ::vec::Vec;
use ::iterator::Iterator;
use ::codec::*;
use ::debug::*... | [
"sway-lib-std/src/storage/storage_vec.sw"
] | [
{
"comment": "```suggestion\n /// will remain in the storage.\n```",
"path": "sway-lib-std/src/storage/storage_vec.sw",
"hunk": "@@ -1021,10 +1152,1366 @@ impl<V> Iterator for StorageVecIter<V> {\n }\n }\n \n-// Add padding to type so it can correctly use the storage api\n+/// Calculates the offs... | true | ||
FuelLabs/sway | 7,614 | comment_to_fix | Implement dynamic storage based `StorageVec` | ```suggestion
/// but the nested content of those removed elements will remain in the storage.**
``` | 514ccec75cccc818254f09e0c284db2c78b2ec2a | ecc2c92ea28c187e76d47f70d6de0024c884c202 | diff --git a/sway-lib-std/src/storage/storage_vec.sw b/sway-lib-std/src/storage/storage_vec.sw
index c1c2073fdd9..369b7de24dc 100644
--- a/sway-lib-std/src/storage/storage_vec.sw
+++ b/sway-lib-std/src/storage/storage_vec.sw
@@ -10,14 +10,89 @@ use ::vec::Vec;
use ::iterator::Iterator;
use ::codec::*;
use ::debug::*... | [
"sway-lib-std/src/storage/storage_vec.sw"
] | [
{
"comment": "```suggestion\n /// but the nested content of those removed elements will remain in the storage.**\n```",
"path": "sway-lib-std/src/storage/storage_vec.sw",
"hunk": "@@ -1021,10 +1152,1366 @@ impl<V> Iterator for StorageVecIter<V> {\n }\n }\n \n-// Add padding to type so it can corr... | true | ||
FuelLabs/sway | 7,622 | issue_to_patch | Either support or forbid `validate_abi/storage_slots` test options in `unit_tests_pass` tests
Currently, it is allowed to have these options in `unit_test_pass` tests and even set them to true, but they are not checked in the test harness. They are checked only for `compiles` and `runs` tests.
We should either forbid... | Disable initialization of dynamic storage fields larger than 32 bytes | ## Description
This PR disables emitting of `storage_slots.json` entries for `storage` declaration fields whose size is larger than 32 bytes, when compiled with `dynamic_storage` enabled.
This is a temporary solution for the currently missing possibility to create transactions that can initial dynamic storage. In... | c53e7e0cb9183f5ef09c14d4eba94ef4f7e284ce | 14e106959414f2f34152f5f3a0b3626628140232 | diff --git a/sway-core/src/ir_generation/storage.rs b/sway-core/src/ir_generation/storage.rs
index fb0f59751c8..65a35c9a489 100644
--- a/sway-core/src/ir_generation/storage.rs
+++ b/sway-core/src/ir_generation/storage.rs
@@ -121,23 +121,25 @@ pub(super) fn add_to_b256(x: Bytes32, y: u64) -> Bytes32 {
Bytes32::from... | [
"sway-core/src/ir_generation/storage.rs",
"sway-core/src/semantic_analysis/ast_node/declaration/storage.rs",
"test/src/e2e_vm_tests/harness.rs",
"test/src/e2e_vm_tests/mod.rs",
"test/src/e2e_vm_tests/test_programs/should_fail/storage_configurable/json_storage_slots_oracle.json",
"test/src/e2e_vm_tests/tes... | [] | diff --git a/test/src/e2e_vm_tests/harness.rs b/test/src/e2e_vm_tests/harness.rs
index 11316541c4f..2ddb496669c 100644
--- a/test/src/e2e_vm_tests/harness.rs
+++ b/test/src/e2e_vm_tests/harness.rs
@@ -384,8 +384,11 @@ pub(crate) async fn compile_and_run_unit_tests(
.await
}
+/// `relative_test_path` is the path... | true |
FuelLabs/sway | 7,611 | issue_to_patch | Fix tuple codec helpers to avoid LSP stack overflows | ## Summary
I reproduced an LSP crash where opening and incrementally editing `fuel-o2-exports/contracts/order-book/src/main.sw` could abort the server and leave stale semantic highlighting behind in the client.
Daniel pointed out that the generated tuple helpers in `std::codec` are emitted as one large left-associati... | 27f3d9977b5ff5fa0d77d2e3fc75f2710d4dde34 | 692b463220166cf7c1c070ed1866a98b7583efc5 | diff --git a/sway-lib-std/generate.sh b/sway-lib-std/generate.sh
index 16db557f65e..fa873c07087 100755
--- a/sway-lib-std/generate.sh
+++ b/sway-lib-std/generate.sh
@@ -1,12 +1,24 @@
#! /bin/bash
+# Use GNU sed (`gsed` on macOS via `brew install gnu-sed`); BSD sed in-place
+# semantics differ and break the substitut... | [
"sway-lib-std/generate.sh",
"sway-lib-std/src/codec.sw",
"test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap",
"test/src/e2e_vm_tests/test_programs/should_pass/language/configurable_dedup_decode/stdout.snap",
"test/src/e2e_vm_tests/test_programs/should_pass/language/cons... | [] | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap
index 1a242815443..5178a69a0b8 100644
--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.sn... | true | |
FuelLabs/sway | 7,608 | issue_to_patch | Increase test coverage for `dynamic_storage` | ## Description
This PR increases test coverage for `dynamic_storage` experimental feature, by reusing existing E2E storage tests and running them with the `dynamic_storage` feature enabled.
Tests containing `StorageVec` are not included. This will be done in the PR that brings dynamic-storage-based `StorageVec`.
... | 3005dcbf538835975b217cf3b63f5183746ed1cc | 78292cb6ebbad0b270ef56a98c718eee0c03d533 | [
"test/src/e2e_vm_tests/test_programs/should_fail/const_eval_bad_struct/test.dynamic_storage.toml",
"test/src/e2e_vm_tests/test_programs/should_fail/generics_in_contract/src/main.sw",
"test/src/e2e_vm_tests/test_programs/should_fail/generics_in_contract/test.dynamic_storage.toml",
"test/src/e2e_vm_tests/test_p... | [
{
"comment": "### Redundant `experimental_new_encoding` field in test config\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\nThe `experimental_new_encoding = true` field on line 4 is redundant because `experimental = { new_encoding = true, dynamic_storage = true }` on line 2 already enables `new_encoding`. W... | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/const_eval_bad_struct/test.dynamic_storage.toml b/test/src/e2e_vm_tests/test_programs/should_fail/const_eval_bad_struct/test.dynamic_storage.toml
new file mode 100644
index 00000000000..56c5b3a5516
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_programs/shoul... | true | ||
FuelLabs/sway | 7,608 | comment_to_fix | Increase test coverage for `dynamic_storage` | ### Redundant `experimental_new_encoding` field in test config
**Low Severity**
<!-- DESCRIPTION START -->
The `experimental_new_encoding = true` field on line 4 is redundant because `experimental = { new_encoding = true, dynamic_storage = true }` on line 2 already enables `new_encoding`. When the `experimental` tabl... | 3005dcbf538835975b217cf3b63f5183746ed1cc | 78292cb6ebbad0b270ef56a98c718eee0c03d533 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/payable_non_zero_coins/test.dynamic_storage.toml b/test/src/e2e_vm_tests/test_programs/should_pass/payable_non_zero_coins/test.dynamic_storage.toml
new file mode 100644
index 00000000000..d8073b9fa6b
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_programs/sho... | [
"test/src/e2e_vm_tests/test_programs/should_pass/payable_non_zero_coins/test.dynamic_storage.toml"
] | [
{
"comment": "### Redundant `experimental_new_encoding` field in test config\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\nThe `experimental_new_encoding = true` field on line 4 is redundant because `experimental = { new_encoding = true, dynamic_storage = true }` on line 2 already enables `new_encoding`. W... | true | ||
FuelLabs/sway | 7,608 | comment_to_fix | Increase test coverage for `dynamic_storage` | ### Missing ABI oracle files for dynamic_storage tests
**Medium Severity**
<!-- DESCRIPTION START -->
Three `test.dynamic_storage.toml` files set `validate_abi = true` but no corresponding `json_abi_oracle.dynamic_storage.debug.json` / `json_abi_oracle.dynamic_storage.release.json` files are included. The test harnes... | 3005dcbf538835975b217cf3b63f5183746ed1cc | 78292cb6ebbad0b270ef56a98c718eee0c03d533 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/basic_storage/test.dynamic_storage.toml b/test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/basic_storage/test.dynamic_storage.toml
new file mode 100644
index 00000000000..8d611f852b4
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_... | [
"test/src/e2e_vm_tests/test_programs/should_pass/test_contracts/basic_storage/test.dynamic_storage.toml"
] | [
{
"comment": "### Missing ABI oracle files for dynamic_storage tests\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThree `test.dynamic_storage.toml` files set `validate_abi = true` but no corresponding `json_abi_oracle.dynamic_storage.debug.json` / `json_abi_oracle.dynamic_storage.release.json` files ar... | true | ||
FuelLabs/sway | 7,601 | issue_to_patch | Reassignment to const generic array emits "Type is not indexable" error
E.g., this code:
```sway
fn const_generic_array<const N: u64>() -> [u8; N] {
let mut res = [0u8; N];
res[0] = 1;
res
}
```
emits:
```
error: Type is not indexable
--> const-generic-array-not-an-indexable-type/sway_const_generic_arr... | Implement reassignment for arrays declared using const generics | ## Description
This PR implements reassignments for arrays declared using const generic arguments:
```sway
fn const_generic_array<const N: u64>() -> [u8; N] {
let mut res = [0u8; N];
res[0] = 1; // <<<<--- This now works.
res
}
```
During development and testing of this PR, several o... | fe31b4a85b3096812399fa1c319f14cf232892a5 | 3c8b892282de63c81d6dc24e3a0be2b13176f866 | diff --git a/sway-core/src/semantic_analysis/ast_node/expression/typed_expression.rs b/sway-core/src/semantic_analysis/ast_node/expression/typed_expression.rs
index 9ab3cc6921d..c6bb40ece71 100644
--- a/sway-core/src/semantic_analysis/ast_node/expression/typed_expression.rs
+++ b/sway-core/src/semantic_analysis/ast_nod... | [
"sway-core/src/semantic_analysis/ast_node/expression/typed_expression.rs",
"sway-error/src/error.rs",
"test/src/e2e_vm_tests/test_programs/should_fail/array_bad_index/Forc.lock",
"test/src/e2e_vm_tests/test_programs/should_fail/array_invalid_index_type/Forc.lock",
"test/src/e2e_vm_tests/test_programs/should... | [
{
"comment": "### Swapped loop bounds in nested array test function\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nIn `simple_const_generic_nested_array_reassignment`, the loop bounds for `a` and `b` are swapped relative to the array dimensions. The type `[[u64; A]; B]` is an array of `B` elements each o... | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/array_bad_index/Forc.lock b/test/src/e2e_vm_tests/test_programs/should_fail/array_bad_index/Forc.lock
deleted file mode 100644
index 50cb58e1e4c..00000000000
--- a/test/src/e2e_vm_tests/test_programs/should_fail/array_bad_index/Forc.lock
+++ /dev/null
@@ -1,3... | true |
FuelLabs/sway | 7,601 | comment_to_fix | Implement reassignment for arrays declared using const generics | ### Swapped loop bounds in nested array test function
**Medium Severity**
<!-- DESCRIPTION START -->
In `simple_const_generic_nested_array_reassignment`, the loop bounds for `a` and `b` are swapped relative to the array dimensions. The type `[[u64; A]; B]` is an array of `B` elements each of type `[u64; A]`, so `arra... | fe31b4a85b3096812399fa1c319f14cf232892a5 | 3c8b892282de63c81d6dc24e3a0be2b13176f866 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/const_generics_array_in_reassignments/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/language/const_generics_array_in_reassignments/src/main.sw
new file mode 100644
index 00000000000..3fa52bbd21e
--- /dev/null
+++ b/test/src/e2e_vm_tes... | [
"test/src/e2e_vm_tests/test_programs/should_pass/language/const_generics_array_in_reassignments/src/main.sw"
] | [
{
"comment": "### Swapped loop bounds in nested array test function\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nIn `simple_const_generic_nested_array_reassignment`, the loop bounds for `a` and `b` are swapped relative to the array dimensions. The type `[[u64; A]; B]` is an array of `B` elements each o... | true | ||
FuelLabs/sway | 7,601 | comment_to_fix | Implement reassignment for arrays declared using const generics | I left a comment here: https://github.com/FuelLabs/sway-rfcs/pull/51#issuecomment-4335629221
Not emitting an error now makes sense. | fe31b4a85b3096812399fa1c319f14cf232892a5 | 3c8b892282de63c81d6dc24e3a0be2b13176f866 | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/array_oob_const_index/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_fail/array_oob_const_index/src/main.sw
index a82db990b29..36c45d06f24 100644
--- a/test/src/e2e_vm_tests/test_programs/should_fail/array_oob_const_index/src/main.sw
+++ b/test/src/... | [
"test/src/e2e_vm_tests/test_programs/should_fail/array_oob_const_index/src/main.sw"
] | [
{
"comment": "I left a comment here: https://github.com/FuelLabs/sway-rfcs/pull/51#issuecomment-4335629221\n\nNot emitting an error now makes sense.",
"path": "test/src/e2e_vm_tests/test_programs/should_fail/array_oob_const_index/src/main.sw",
"hunk": "@@ -5,15 +5,47 @@ fn literal_index() -> u64 {\n ... | true | ||
FuelLabs/sway | 7,598 | issue_to_patch | Fix issues found during testing of the `Iterator` implementation for `StorageVec`
The tests written in #6821 fails for types `()`, `[u64;0]`, and the `EmptyStruct`.
Using `()` causes an ICE:
```
error
--> /.../sway/sway-lib-std/src/option.sw:191:15
|
189 | /// ```
190 | pub fn unwrap(self) -> T... | Implement dynamic storage for `storage` declaration and `std` | ## Description
This PR is a part of #7560 implementation and implements:
- `storage` fields access compilation for dynamic storage.
- dynamic storage for all the types and functions in the `std::storage` module, except the `StorageVec`.
In the `storage_api`, support for dynamic storage is added as the extension... | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/sway-core/src/ir_generation/function.rs b/sway-core/src/ir_generation/function.rs
index f7658966e6f..b3089c62be5 100644
--- a/sway-core/src/ir_generation/function.rs
+++ b/sway-core/src/ir_generation/function.rs
@@ -796,7 +796,7 @@ impl<'a> FnCompiler<'a> {
self.compile_storage_access(
... | [
"sway-core/src/ir_generation/function.rs",
"sway-core/src/ir_generation/purity.rs",
"sway-core/src/ir_generation/storage.rs",
"sway-core/src/language/parsed/expression/mod.rs",
"sway-core/src/language/ty/declaration/storage.rs",
"sway-core/src/language/ty/expression/storage.rs",
"sway-core/src/semantic_... | [
{
"comment": "### Overly broad storage purity annotation on clear_slice_slot\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\n`clear_slice_slot` is annotated `#[storage(read, write)]` but only calls `__state_clear_slots`, which is a write-only operation. This unnecessarily forces callers (like `StorageByte... | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/purity_of_asm_instructions_and_intrinsics/test.toml b/test/src/e2e_vm_tests/test_programs/should_fail/purity_of_asm_instructions_and_intrinsics/test.toml
index 635449aaeb1..c825f20cb0b 100644
--- a/test/src/e2e_vm_tests/test_programs/should_fail/purity_of_asm... | true |
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | ### Overly broad storage purity annotation on clear_slice_slot
**Medium Severity**
<!-- DESCRIPTION START -->
`clear_slice_slot` is annotated `#[storage(read, write)]` but only calls `__state_clear_slots`, which is a write-only operation. This unnecessarily forces callers (like `StorageBytes::clear()` and `StorageStr... | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/sway-lib-std/src/storage/storable_slice.sw b/sway-lib-std/src/storage/storable_slice.sw
index d611ce08f66..9a6d277c5f1 100644
--- a/sway-lib-std/src/storage/storable_slice.sw
+++ b/sway-lib-std/src/storage/storable_slice.sw
@@ -1,3 +1,14 @@
+//! This module provides:
+//! - a `StorableSlice<T>` trait for s... | [
"sway-lib-std/src/storage/storable_slice.sw"
] | [
{
"comment": "### Overly broad storage purity annotation on clear_slice_slot\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\n`clear_slice_slot` is annotated `#[storage(read, write)]` but only calls `__state_clear_slots`, which is a write-only operation. This unnecessarily forces callers (like `StorageByte... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | ### Test has wrong expected values from copy-paste
**Low Severity**
<!-- DESCRIPTION START -->
In `state_update_slot_offset_equal_slot_length`, the expected array `[42u64, 34u64, 44u64, 45u64, 46u64]` contains `34u64` at index 1, but the stored data was `[42u64, 43u64, 44u64, 45u64]`. The `34u64` was copied from `sta... | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/storage_intrinsics/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/storage_intrinsics/src/main.sw
index f72a2c72f16..5bbe0e0d59c 100644
--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/intrin... | [
"test/src/e2e_vm_tests/test_programs/should_pass/language/intrinsics/storage_intrinsics/src/main.sw"
] | [
{
"comment": "### Test has wrong expected values from copy-paste\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\nIn `state_update_slot_offset_equal_slot_length`, the expected array `[42u64, 34u64, 44u64, 45u64, 46u64]` contains `34u64` at index 1, but the stored data was `[42u64, 43u64, 44u64, 45u64]`. The `... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | ### Inconsistent storage annotations for identical read+clear pattern
**Low Severity**
<!-- DESCRIPTION START -->
`clear_slots_existed` and `StorageKey::clear_existed` use `#[storage(write)]` while `clear_slice_slot_existed` uses `#[storage(read, write)]`, yet all three perform the same pattern: `__state_preload` (a ... | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/sway-lib-std/src/storage/storage_api.sw b/sway-lib-std/src/storage/storage_api.sw
index 2a34d01e20a..e49cdc0d766 100644
--- a/sway-lib-std/src/storage/storage_api.sw
+++ b/sway-lib-std/src/storage/storage_api.sw
@@ -5,37 +5,54 @@ use ::option::Option::{self, *};
use ::ops::*;
use ::primitive_conversions:... | [
"sway-lib-std/src/storage/storage_api.sw"
] | [
{
"comment": "### Inconsistent storage annotations for identical read+clear pattern\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\n`clear_slots_existed` and `StorageKey::clear_existed` use `#[storage(write)]` while `clear_slice_slot_existed` uses `#[storage(read, write)]`, yet all three perform the same pat... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | Shouldn't this be `field_id`? | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/sway-core/src/ir_generation/function.rs b/sway-core/src/ir_generation/function.rs
index f7658966e6f..b3089c62be5 100644
--- a/sway-core/src/ir_generation/function.rs
+++ b/sway-core/src/ir_generation/function.rs
@@ -796,7 +796,7 @@ impl<'a> FnCompiler<'a> {
self.compile_storage_access(
... | [
"sway-core/src/ir_generation/function.rs"
] | [
{
"comment": "Shouldn't this be `field_id`?",
"path": "sway-core/src/ir_generation/function.rs",
"hunk": "@@ -5616,72 +5616,86 @@ impl<'a> FnCompiler<'a> {\n &mut self,\n context: &mut Context,\n md_mgr: &mut MetadataManager,\n- storage_field_names: Vec<String>,\n+ ... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | I think this collides with the previous update? | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/sway-lib-std/src/storage/storage_api.sw b/sway-lib-std/src/storage/storage_api.sw
index 2a34d01e20a..e49cdc0d766 100644
--- a/sway-lib-std/src/storage/storage_api.sw
+++ b/sway-lib-std/src/storage/storage_api.sw
@@ -5,37 +5,54 @@ use ::option::Option::{self, *};
use ::ops::*;
use ::primitive_conversions:... | [
"sway-lib-std/src/storage/storage_api.sw"
] | [
{
"comment": "I think this collides with the previous update?",
"path": "sway-lib-std/src/storage/storage_api.sw",
"hunk": "@@ -60,23 +77,255 @@ pub fn write<T>(slot: b256, offset: u64, value: T) {\n // Copy the value to be stored to `padded_value + offset`.\n padded_value.add::<u64>(place_in_sl... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | Great candidate to be migrated to snapshot tests. | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation/test.toml b/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation/test.toml
index d61220251df..a3faf9ffa87 100644
--- a/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_p... | [
"test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation/test.toml"
] | [
{
"comment": "Great candidate to be migrated to snapshot tests.",
"path": "test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation/test.toml",
"hunk": "@@ -1,4 +1,6 @@\n category = \"compile\"\n+expected_warnings = 3\n \n-# check: $()Storage write after external contract in... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | Great candidate to be migrated to snapshot tests. | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_asm_block_read/test.toml b/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_asm_block_read/test.toml
index 5541a6ffcdf..82200fd0bd5 100644
--- a/test/src/e2e_vm_tests/test_progra... | [
"test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_asm_block_read/test.toml"
] | [
{
"comment": "Great candidate to be migrated to snapshot tests.",
"path": "test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_asm_block_read/test.toml",
"hunk": "@@ -1,4 +1,4 @@\n category = \"compile\"\n \n # check: $()Storage read after external contract interacti... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | Great candidate to be migrated to snapshot tests. | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_codeblocks_other_than_in_functions/test.toml b/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_codeblocks_other_than_in_functions/test.toml
index d61220251df..c8705e39acc 100644... | [
"test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_codeblocks_other_than_in_functions/test.toml"
] | [
{
"comment": "Great candidate to be migrated to snapshot tests.",
"path": "test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_codeblocks_other_than_in_functions/test.toml",
"hunk": "@@ -1,4 +1,7 @@\n category = \"compile\"\n+expected_warnings = 3\n+\n+#unordered: $(... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | Great candidate to be migrated to snapshot tests. | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-1/test.toml b/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-1/test.toml
index 7105f663a21..227a04d0fcc 100644
--- a/test/src/e2e_vm_tests/test_programs/shoul... | [
"test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-1/test.toml"
] | [
{
"comment": "Great candidate to be migrated to snapshot tests.",
"path": "test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-1/test.toml",
"hunk": "@@ -1,4 +1,7 @@\n category = \"compile\"\n-\n-# check: $()Storage write after external contract interaction ... | true | ||
FuelLabs/sway | 7,598 | comment_to_fix | Implement dynamic storage for `storage` declaration and `std` | Great candidate to be migrated to snapshot tests. | e12e6118dee66417a41872ca2b743d279a28174a | 4470322123dad3af6202bfe55d90ea81164eacd1 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-2/test.toml b/test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-2/test.toml
index 7105f663a21..c8705e39acc 100644
--- a/test/src/e2e_vm_tests/test_programs/shoul... | [
"test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-2/test.toml"
] | [
{
"comment": "Great candidate to be migrated to snapshot tests.",
"path": "test/src/e2e_vm_tests/test_programs/should_pass/static_analysis/cei_pattern_violation_in_func_app-2/test.toml",
"hunk": "@@ -1,4 +1,7 @@\n category = \"compile\"\n-\n-# check: $()Storage write after external contract interaction ... | true | ||
FuelLabs/sway | 7,151 | issue_to_patch | Optimize `crypto` module for bytecode size and gas usage | ## Description
This PR optimizes the `std::crypto` module for bytecode size and gas cost by using optimization techniques similar to those used in #7087, #7092, and #7096.
The optimized public functions are listed in the below code snippet. **The bytecode size of that code got reduced from 46104 bytes to 44288 by... | f9fcae93c14937700a61ec031e572d70a5ce41c0 | 5e898c6c00d31a811fefefc9dfe49a7dfa8e6c59 | diff --git a/sway-lib-std/src/bytes.sw b/sway-lib-std/src/bytes.sw
index a2fb83c2d10..04bf122f320 100644
--- a/sway-lib-std/src/bytes.sw
+++ b/sway-lib-std/src/bytes.sw
@@ -956,6 +956,41 @@ impl Bytes {
index: 0,
}
}
+
+ /// Returns true if all the bytes within the `Bytes` are zero.
+ /... | [
"sway-lib-std/src/bytes.sw",
"sway-lib-std/src/crypto/ed25519.sw",
"sway-lib-std/src/crypto/message.sw",
"sway-lib-std/src/crypto/point2d.sw",
"sway-lib-std/src/crypto/public_key.sw",
"sway-lib-std/src/crypto/scalar.sw",
"sway-lib-std/src/crypto/secp256k1.sw",
"sway-lib-std/src/crypto/secp256r1.sw"
] | [] | true | ||
FuelLabs/sway | 6,853 | issue_to_patch | Bump to v0.66.6 | 9e1c320cead802983266e5b5fd9d55d7e40234a6 | 6ecef9652ba1658b9c2033d91a20f81084d44221 | diff --git a/Cargo.lock b/Cargo.lock
index c012ee3100a..6dab0cc2304 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2662,7 +2662,7 @@ checksum = "f81ec6369c545a7d40e4589b5597581fa1c441fe1cce96dd1de43159910a36a2"
[[package]]
name = "forc"
-version = "0.66.5"
+version = "0.66.6"
dependencies = [
"annotate-snippets",
... | [
"Cargo.lock",
"Cargo.toml"
] | [] | true | |||
FuelLabs/sway | 7,237 | issue_to_patch | fix: add forc-call to binary stripping step in ci | ## Description
Fixes ci to add `forc-call` to list of binaries we strip and add to the final binary pack. This should fix the issue of missing forc-call in latest (while having it in nightly as [sway-nightlies](https://github.com/FuelLabs/sway-nightly-binaries/releases) already includes `forc-call`) | cd89f62ece16b3d4ff37dbbd07d68ec056f18a6e | 35e89c895bd7813bcc62d5ec76e8a96a24eceebb | diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 941db16a12d..bfcdc212c66 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -917,13 +917,13 @@ jobs:
- name: Strip release binaries x86_64-linux-gnu
if: matrix.job.target == 'x86_64-unknown-linux-gnu'
ru... | [
".github/workflows/ci.yml"
] | [] | true | ||
FuelLabs/sway | 7,310 | issue_to_patch | feat: fallback into s3 cache in forc-pkg for failed ipfs fetch | ## Description
Adds a the fallback for forc package fetching. If IPFS fails we rely on CDN that is supplied by s3 in forc.pub side.
```console
> ../dev/sway/target/debug/forc build
Building /Users/kayagokalp/fuel/test_me
Fetching std 0.69.1
Fetching from http://ipfs.forc.pub. Note: This can take s... | 631f1db3bab1111dce88f2cb3f7c580648ac1316 | b400478f3f91dc545650a2161aa874b508e70980 | diff --git a/forc-pkg/src/source/reg/mod.rs b/forc-pkg/src/source/reg/mod.rs
index 0e271307ea0..10382582a49 100644
--- a/forc-pkg/src/source/reg/mod.rs
+++ b/forc-pkg/src/source/reg/mod.rs
@@ -11,6 +11,7 @@ use crate::{
};
use anyhow::{anyhow, bail, Context};
use file_location::{location_from_root, Namespace};
+use ... | [
"forc-pkg/src/source/reg/mod.rs"
] | [
{
"comment": "maybe we can improve this message, when trying from IPFS it prints \r\n\r\n``` \r\nFetching from http://ipfs.forc.pub. Note: This can take several minutes.\r\n````\r\n\r\nPerhaps for consistency we could print. \r\n\r\n```\r\nFetching from http://cdn.forc.pub. Note: This can take several minutes.... | true | ||
FuelLabs/sway | 7,310 | comment_to_fix | feat: fallback into s3 cache in forc-pkg for failed ipfs fetch | maybe we can improve this message, when trying from IPFS it prints
```
Fetching from http://ipfs.forc.pub. Note: This can take several minutes.
````
Perhaps for consistency we could print.
```
Fetching from http://cdn.forc.pub. Note: This can take several minutes.
```
| 631f1db3bab1111dce88f2cb3f7c580648ac1316 | b400478f3f91dc545650a2161aa874b508e70980 | diff --git a/forc-pkg/src/source/reg/mod.rs b/forc-pkg/src/source/reg/mod.rs
index 0e271307ea0..10382582a49 100644
--- a/forc-pkg/src/source/reg/mod.rs
+++ b/forc-pkg/src/source/reg/mod.rs
@@ -11,6 +11,7 @@ use crate::{
};
use anyhow::{anyhow, bail, Context};
use file_location::{location_from_root, Namespace};
+use ... | [
"forc-pkg/src/source/reg/mod.rs"
] | [
{
"comment": "maybe we can improve this message, when trying from IPFS it prints \r\n\r\n``` \r\nFetching from http://ipfs.forc.pub. Note: This can take several minutes.\r\n````\r\n\r\nPerhaps for consistency we could print. \r\n\r\n```\r\nFetching from http://cdn.forc.pub. Note: This can take several minutes.... | true | ||
FuelLabs/sway | 7,310 | comment_to_fix | feat: fallback into s3 cache in forc-pkg for failed ipfs fetch | Im assuming this should be `https`?
```suggestion
let cdn_url = format!("https://cdn.forc.pub/{}", pinned.cid.0);
``` | 631f1db3bab1111dce88f2cb3f7c580648ac1316 | b400478f3f91dc545650a2161aa874b508e70980 | diff --git a/forc-pkg/src/source/reg/mod.rs b/forc-pkg/src/source/reg/mod.rs
index 0e271307ea0..10382582a49 100644
--- a/forc-pkg/src/source/reg/mod.rs
+++ b/forc-pkg/src/source/reg/mod.rs
@@ -11,6 +11,7 @@ use crate::{
};
use anyhow::{anyhow, bail, Context};
use file_location::{location_from_root, Namespace};
+use ... | [
"forc-pkg/src/source/reg/mod.rs"
] | [
{
"comment": "Im assuming this should be `https`?\n```suggestion\n let cdn_url = format!(\"https://cdn.forc.pub/{}\", pinned.cid.0);\n```",
"path": "forc-pkg/src/source/reg/mod.rs",
"hunk": "@@ -479,6 +493,61 @@ async fn fetch(fetch_id: u64, pinned: &Pinned, ipfs_node: &IPFSNode) -> anyhow::\n Ok... | true | ||
FuelLabs/sway | 7,310 | comment_to_fix | feat: fallback into s3 cache in forc-pkg for failed ipfs fetch | will probably need to update this aswell; maybe reference the `cdn_url` variable here | 631f1db3bab1111dce88f2cb3f7c580648ac1316 | b400478f3f91dc545650a2161aa874b508e70980 | diff --git a/forc-pkg/src/source/reg/mod.rs b/forc-pkg/src/source/reg/mod.rs
index 0e271307ea0..10382582a49 100644
--- a/forc-pkg/src/source/reg/mod.rs
+++ b/forc-pkg/src/source/reg/mod.rs
@@ -11,6 +11,7 @@ use crate::{
};
use anyhow::{anyhow, bail, Context};
use file_location::{location_from_root, Namespace};
+use ... | [
"forc-pkg/src/source/reg/mod.rs"
] | [
{
"comment": "will probably need to update this aswell; maybe reference the `cdn_url` variable here",
"path": "forc-pkg/src/source/reg/mod.rs",
"hunk": "@@ -479,6 +493,61 @@ async fn fetch(fetch_id: u64, pinned: &Pinned, ipfs_node: &IPFSNode) -> anyhow::\n Ok(path)\n }\n \n+/// Fetches package from ... | true | ||
FuelLabs/sway | 7,310 | comment_to_fix | feat: fallback into s3 cache in forc-pkg for failed ipfs fetch | potential path traversal vulnerability here - since tar can unpack to parent paths.
```suggestion
let mut entry = entry?;
// Validate the entry path to prevent directory traversal
let entry_path = entry.path()?;
if entry_path
.components()
.any(|c| matches!(c, ... | 631f1db3bab1111dce88f2cb3f7c580648ac1316 | b400478f3f91dc545650a2161aa874b508e70980 | diff --git a/forc-pkg/src/source/reg/mod.rs b/forc-pkg/src/source/reg/mod.rs
index 0e271307ea0..10382582a49 100644
--- a/forc-pkg/src/source/reg/mod.rs
+++ b/forc-pkg/src/source/reg/mod.rs
@@ -11,6 +11,7 @@ use crate::{
};
use anyhow::{anyhow, bail, Context};
use file_location::{location_from_root, Namespace};
+use ... | [
"forc-pkg/src/source/reg/mod.rs"
] | [
{
"comment": "potential path traversal vulnerability here - since tar can unpack to parent paths.\n\n\n```suggestion\n let mut entry = entry?;\n\n // Validate the entry path to prevent directory traversal\n let entry_path = entry.path()?;\n if entry_path\n .components()\n ... | true | ||
FuelLabs/sway | 7,310 | comment_to_fix | feat: fallback into s3 cache in forc-pkg for failed ipfs fetch | might want to add explicit request timeout
```suggestion
let client = reqwest::Client::builder()
.timeout(std::time::Duration::from_secs(180)) // 3 minute timeout
.build()
.context("Failed to create HTTP client")?;
``` | 631f1db3bab1111dce88f2cb3f7c580648ac1316 | b400478f3f91dc545650a2161aa874b508e70980 | diff --git a/forc-pkg/src/source/reg/mod.rs b/forc-pkg/src/source/reg/mod.rs
index 0e271307ea0..10382582a49 100644
--- a/forc-pkg/src/source/reg/mod.rs
+++ b/forc-pkg/src/source/reg/mod.rs
@@ -11,6 +11,7 @@ use crate::{
};
use anyhow::{anyhow, bail, Context};
use file_location::{location_from_root, Namespace};
+use ... | [
"forc-pkg/src/source/reg/mod.rs"
] | [
{
"comment": "might want to add explicit request timeout\n\n```suggestion\n let client = reqwest::Client::builder()\n .timeout(std::time::Duration::from_secs(180)) // 3 minute timeout\n .build()\n .context(\"Failed to create HTTP client\")?;\n```",
"path": "forc-pkg/src/source/reg/mo... | true | ||
FuelLabs/sway | 7,385 | issue_to_patch | Trait coherence: disallow inherent impls on external types | This improves the trait coherence checks for impl self case, and polishes a bit of the wording on the existing diagnostics.
We now enforce package-level check in impl-self type checking, which means we now reject inherent impls for external nominal types (struct/enum).
There is still is a specialized whitelist fo... | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs",
"sway-error/src/error.rs",
"sway-error/src/warning.rs",
"test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_alias_external/Forc.lock",
"test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_alias_external/... | [
{
"comment": "I thought that, as we discussed, this whitelisting wasn't actually necessary for licit usages of `impl StorageKey<SomeType>`",
"path": "sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs",
"hunk": "@@ -526,6 +526,56 @@ impl TyImplSelfOrTrait {\n implemen... | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_alias_external/Forc.lock b/test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_alias_external/Forc.lock
new file mode 100644
index 00000000000..5f58e2f4fec
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_programs/should_fa... | true | |
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | I thought that, as we discussed, this whitelisting wasn't actually necessary for licit usages of `impl StorageKey<SomeType>` | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "I thought that, as we discussed, this whitelisting wasn't actually necessary for licit usages of `impl StorageKey<SomeType>`",
"path": "sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs",
"hunk": "@@ -526,6 +526,56 @@ impl TyImplSelfOrTrait {\n implemen... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | ### Bug: Aliases to external types bypass coherence check
<!-- **Medium Severity** -->
<!-- DESCRIPTION START -->
The `is_external` check only handles `TypeInfo::Struct` and `TypeInfo::Enum`, returning `false` for `TypeInfo::Alias`. Since `expect_is_supported_in_impl_blocks_self` explicitly allows `Alias` types for i... | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "### Bug: Aliases to external types bypass coherence check\n\n<!-- **Medium Severity** -->\n\n<!-- DESCRIPTION START -->\nThe `is_external` check only handles `TypeInfo::Struct` and `TypeInfo::Enum`, returning `false` for `TypeInfo::Alias`. Since `expect_is_supported_in_impl_blocks_self` explicitly... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | Nitpick. Single line looks somehow more readable to me.
```suggestion
pkg_name.and_then(|name| name != current_pkg.name().as_str()).unwrap_or_default()
``` | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "Nitpick. Single line looks somehow more readable to me.\n```suggestion\n pkg_name.and_then(|name| name != current_pkg.name().as_str()).unwrap_or_default()\n```",
"path": "sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs",
"hunk": "@@ -527,6 +527,56 ... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | Same here.
```suggestion
pkg_name.and_then(|name| name != current_pkg.name().as_str()).unwrap_or_default()
``` | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "Same here.\n```suggestion\n pkg_name.and_then(|name| name != current_pkg.name().as_str()).unwrap_or_default()\n```",
"path": "sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs",
"hunk": "@@ -527,6 +527,56 @@ impl TyImplSelfOrTrait {\n ... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | The below comment from the Cursor bot is an actual bug. We should use `get_unaliased` here to make sure we are checking the actual type.
```suggestion
let is_external = match &*type_engine.get_unaliased(implementing_for.type_id) {
``` | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "The below comment from the Cursor bot is an actual bug. We should use `get_unaliased` here to make sure we are checking the actual type.\n```suggestion\n let is_external = match &*type_engine.get_unaliased(implementing_for.type_id) {\n```",
"path": "sway-core/src/semantic_analys... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | Strictly speaking, this must be exactly 2 😉
```suggestion
&& s.call_path.prefixes.len() == 2
``` | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "Strictly speaking, this must be exactly 2 😉 \n```suggestion\n && s.call_path.prefixes.len() == 2\n```",
"path": "sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs",
"hunk": "@@ -527,6 +527,56 @@ impl TyImplSelfOrTrait {\n imp... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | Also here we should handle aliases. Ideally, we could have a diagnostic saying that the declaration type is an alias for the external type. But for now we can just make sure we handle this.
```suggestion
let type_definition_span = match &*type_engine.get_unaliased(implementing_for.type_id) {
``` | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "Also here we should handle aliases. Ideally, we could have a diagnostic saying that the declaration type is an alias for the external type. But for now we can just make sure we handle this.\n```suggestion\n let type_definition_span = match &*type_engine.get_unaliased(implementin... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | ### Bug: Missing alias resolution in StorageKey whitelist check
<!-- **Medium Severity** -->
<!-- DESCRIPTION START -->
The `is_storage_key_in_std` check uses `type_engine.get()` while the `is_external` check uses `type_engine.get_unaliased()`. This inconsistency means that if someone creates an alias to `StorageKey`... | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs b/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
index d1e8a611791..bd66481df8c 100644
--- a/sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs
+++ b/sway-core/src/semantic_analysis/ast_node/declaration/i... | [
"sway-core/src/semantic_analysis/ast_node/declaration/impl_trait.rs"
] | [
{
"comment": "### Bug: Missing alias resolution in StorageKey whitelist check\n\n<!-- **Medium Severity** -->\n\n<!-- DESCRIPTION START -->\nThe `is_storage_key_in_std` check uses `type_engine.get()` while the `is_external` check uses `type_engine.get_unaliased()`. This inconsistency means that if someone creat... | true | ||
FuelLabs/sway | 7,385 | comment_to_fix | Trait coherence: disallow inherent impls on external types | ### Bug: Library inherent impls may incorrectly trigger coherence warnings
<!-- **Medium Severity** -->
<!-- DESCRIPTION START -->
The test expectation of `expected_warnings = 2` is suspicious. Each test has only one inherent impl for an external type, which should produce exactly one coherence warning. The library `... | 4a44a36718e049cca3648483c1ac0bf965a59355 | 770e69e537d177d1d82e7692cca913c5b621d051 | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_self_overlap/test.toml b/test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_self_overlap/test.toml
index 29efbacada8..599f06cac9b 100644
--- a/test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_self_ove... | [
"test/src/e2e_vm_tests/test_programs/should_fail/trait_coherence/impl_self_overlap/test.toml"
] | [
{
"comment": "### Bug: Library inherent impls may incorrectly trigger coherence warnings\n\n<!-- **Medium Severity** -->\n\n<!-- DESCRIPTION START -->\nThe test expectation of `expected_warnings = 2` is suspicious. Each test has only one inherent impl for an external type, which should produce exactly one coher... | true | ||
FuelLabs/sway | 7,597 | issue_to_patch | `__smo` and `__log` intrinsics not correctly compiled and can cause ICE
`__smo` and `__log` intrinsics return unit `()` but the returned value is not correctly compiled in the IR. Instead of having a const `()` as their return value they just return their underlaying IR instruction that does not return a value.
E.g. ... | Implement dynamic storage intrinsics | ## Description
This PR adds compiler intrinsics for dynamic storage opcodes. It is the second step in implementing #7560.
Additionally, the PR:
- fixes #7572 by properly returning unit `()` in IR generation.
- partially addresses #7596 by cleaning up the type checking of existing storage intrinsics.
## Check... | fbb524c2dfc726636e321ada342060f51e17de19 | b5e6a40b1fdda31e38456a3572b8f626d17539a9 | diff --git a/docs/book/spell-check-custom-words.txt b/docs/book/spell-check-custom-words.txt
index 733ba3f73e7..a45f2308622 100644
--- a/docs/book/spell-check-custom-words.txt
+++ b/docs/book/spell-check-custom-words.txt
@@ -270,3 +270,8 @@ backtrace
Backtrace
backtracing
Backtracing
+preload
+Preload
+preloads
+Pre... | [
"docs/book/spell-check-custom-words.txt",
"docs/book/src/reference/compiler_intrinsics.md",
"sway-ast/src/intrinsics.rs",
"sway-core/src/error.rs",
"sway-core/src/ir_generation/const_eval.rs",
"sway-core/src/ir_generation/function.rs",
"sway-core/src/semantic_analysis/ast_node/expression/intrinsic_funct... | [
{
"comment": "### `StateLoadWord` always gets two arguments breaking non-dynamic path\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\n`type_check_state_load_word` now always emits two arguments (`vec![key_exp, offset_exp]`) in the typed intrinsic, even when `dynamic_storage` is disabled, by synthesizing a... | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/binop_intrinsics/Forc.lock b/test/src/e2e_vm_tests/test_programs/should_fail/binop_intrinsics/Forc.lock
deleted file mode 100644
index 870bf0a1975..00000000000
--- a/test/src/e2e_vm_tests/test_programs/should_fail/binop_intrinsics/Forc.lock
+++ /dev/null
@@ -... | true |
FuelLabs/sway | 7,597 | comment_to_fix | Implement dynamic storage intrinsics | ### `StateLoadWord` always gets two arguments breaking non-dynamic path
**Medium Severity**
<!-- DESCRIPTION START -->
`type_check_state_load_word` now always emits two arguments (`vec![key_exp, offset_exp]`) in the typed intrinsic, even when `dynamic_storage` is disabled, by synthesizing a dummy `offset_exp` of `0`.... | fbb524c2dfc726636e321ada342060f51e17de19 | b5e6a40b1fdda31e38456a3572b8f626d17539a9 | diff --git a/sway-core/src/semantic_analysis/ast_node/expression/intrinsic_function.rs b/sway-core/src/semantic_analysis/ast_node/expression/intrinsic_function.rs
index 0dab6f365c4..012ceb4c038 100644
--- a/sway-core/src/semantic_analysis/ast_node/expression/intrinsic_function.rs
+++ b/sway-core/src/semantic_analysis/a... | [
"sway-core/src/semantic_analysis/ast_node/expression/intrinsic_function.rs"
] | [
{
"comment": "### `StateLoadWord` always gets two arguments breaking non-dynamic path\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\n`type_check_state_load_word` now always emits two arguments (`vec![key_exp, offset_exp]`) in the typed intrinsic, even when `dynamic_storage` is disabled, by synthesizing a... | true | ||
FuelLabs/sway | 7,597 | comment_to_fix | Implement dynamic storage intrinsics | ### `StateUpdateSlot` missing `StorageRead` effect in CEI analysis
**High Severity**
<!-- DESCRIPTION START -->
`StateUpdateSlot` is assigned only `Effect::StorageWrite`, but it also reads from storage (especially for append operations where existing content must be read). The purity test at `purity_of_asm_instructio... | fbb524c2dfc726636e321ada342060f51e17de19 | b5e6a40b1fdda31e38456a3572b8f626d17539a9 | diff --git a/sway-core/src/semantic_analysis/cei_pattern_analysis.rs b/sway-core/src/semantic_analysis/cei_pattern_analysis.rs
index a23133fd4d4..e13cf98378a 100644
--- a/sway-core/src/semantic_analysis/cei_pattern_analysis.rs
+++ b/sway-core/src/semantic_analysis/cei_pattern_analysis.rs
@@ -637,8 +637,15 @@ fn effects... | [
"sway-core/src/semantic_analysis/cei_pattern_analysis.rs"
] | [
{
"comment": "### `StateUpdateSlot` missing `StorageRead` effect in CEI analysis\n\n**High Severity**\n\n<!-- DESCRIPTION START -->\n`StateUpdateSlot` is assigned only `Effect::StorageWrite`, but it also reads from storage (especially for append operations where existing content must be read). The purity test a... | true | ||
FuelLabs/sway | 7,595 | issue_to_patch | Implement dynamic storage opcodes in the compiler | ## Description
This PR is a step in implementing #7560. It adds compiler support for [dynamic storage opcodes](https://github.com/FuelLabs/fuel-specs/pull/640) by:
- supporting all opcodes in `asm` blocks.
- adding IR instructions for all opcodes.
Note that the `FuelVmInstruction::StatePreload` IR instruction r... | f9b815898a7db0e1cf775d62872a833fe5c87a4a | a871f09720d69cdb15106a526ac2493cbd687796 | diff --git a/forc-plugins/forc-debug/src/server/handlers/handle_variables.rs b/forc-plugins/forc-debug/src/server/handlers/handle_variables.rs
index d056bbeb777..36075512706 100644
--- a/forc-plugins/forc-debug/src/server/handlers/handle_variables.rs
+++ b/forc-plugins/forc-debug/src/server/handlers/handle_variables.rs... | [
"forc-plugins/forc-debug/src/server/handlers/handle_variables.rs",
"sway-ast/src/expr/op_code.rs",
"sway-core/src/asm_generation/fuel/fuel_asm_builder.rs",
"sway-core/src/asm_lang/allocated_ops.rs",
"sway-core/src/asm_lang/mod.rs",
"sway-core/src/asm_lang/virtual_ops.rs",
"sway-core/src/ir_generation/pu... | [
{
"comment": "### Inconsistent offset type check in state slot verification\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe `verify_state_read_slot` method checks `offset` with `Type::is_uint` (accepts any unsigned integer width), while `verify_state_update_slot` checks the semantically identical `off... | diff --git a/sway-ir/tests/serialize/storage_clear.ir b/sway-ir/tests/serialize/storage_clear.ir
new file mode 100644
index 00000000000..fca90d0c8f6
--- /dev/null
+++ b/sway-ir/tests/serialize/storage_clear.ir
@@ -0,0 +1,22 @@
+// regex: VAR=v\d+v\d+
+
+script {
+// check: fn main
+ fn main() -> () {
+ local ... | true | |
FuelLabs/sway | 7,595 | comment_to_fix | Implement dynamic storage opcodes in the compiler | ### Inconsistent offset type check in state slot verification
**Medium Severity**
<!-- DESCRIPTION START -->
The `verify_state_read_slot` method checks `offset` with `Type::is_uint` (accepts any unsigned integer width), while `verify_state_update_slot` checks the semantically identical `offset` parameter with `Type::... | f9b815898a7db0e1cf775d62872a833fe5c87a4a | a871f09720d69cdb15106a526ac2493cbd687796 | diff --git a/sway-ir/src/verify.rs b/sway-ir/src/verify.rs
index 98858891dcc..a6629a353f6 100644
--- a/sway-ir/src/verify.rs
+++ b/sway-ir/src/verify.rs
@@ -308,6 +308,10 @@ impl InstructionVerifier<'_, '_> {
FuelVmInstruction::StateClear {
key,
num... | [
"sway-ir/src/verify.rs"
] | [
{
"comment": "### Inconsistent offset type check in state slot verification\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe `verify_state_read_slot` method checks `offset` with `Type::is_uint` (accepts any unsigned integer width), while `verify_state_update_slot` checks the semantically identical `off... | true | ||
FuelLabs/sway | 7,595 | comment_to_fix | Implement dynamic storage opcodes in the compiler | All storage write opcodes perform an implicit read unless already cached. I tried to understand if this has any issues with `Effect` usage, and that doesn't seem to be the case currently, as the behavior is largely transparent to user code. | f9b815898a7db0e1cf775d62872a833fe5c87a4a | a871f09720d69cdb15106a526ac2493cbd687796 | diff --git a/sway-core/src/semantic_analysis/cei_pattern_analysis.rs b/sway-core/src/semantic_analysis/cei_pattern_analysis.rs
index 0f838ef91c2..a23133fd4d4 100644
--- a/sway-core/src/semantic_analysis/cei_pattern_analysis.rs
+++ b/sway-core/src/semantic_analysis/cei_pattern_analysis.rs
@@ -685,8 +685,19 @@ fn effects... | [
"sway-core/src/semantic_analysis/cei_pattern_analysis.rs"
] | [
{
"comment": "All storage write opcodes perform an implicit read unless already cached. I tried to understand if this has any issues with `Effect` usage, and that doesn't seem to be the case currently, as the behavior is largely transparent to user code.",
"path": "sway-core/src/semantic_analysis/cei_patter... | true | ||
FuelLabs/sway | 7,595 | comment_to_fix | Implement dynamic storage opcodes in the compiler | ### Inconsistent `len` type check in `verify_state_read_slot`
**Medium Severity**
<!-- DESCRIPTION START -->
The `len` parameter in `verify_state_read_slot` is checked with `Type::is_uint64`, while the analogous `len` parameter in `verify_state_write_slot` and `verify_state_update_slot` uses `Type::is_uint` (any unsi... | f9b815898a7db0e1cf775d62872a833fe5c87a4a | a871f09720d69cdb15106a526ac2493cbd687796 | diff --git a/sway-ir/src/verify.rs b/sway-ir/src/verify.rs
index 98858891dcc..a6629a353f6 100644
--- a/sway-ir/src/verify.rs
+++ b/sway-ir/src/verify.rs
@@ -308,6 +308,10 @@ impl InstructionVerifier<'_, '_> {
FuelVmInstruction::StateClear {
key,
num... | [
"sway-ir/src/verify.rs"
] | [
{
"comment": "### Inconsistent `len` type check in `verify_state_read_slot`\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe `len` parameter in `verify_state_read_slot` is checked with `Type::is_uint64`, while the analogous `len` parameter in `verify_state_write_slot` and `verify_state_update_slot` use... | true | ||
FuelLabs/sway | 7,595 | comment_to_fix | Implement dynamic storage opcodes in the compiler | ### Printer missing `maybe_constant_to_doc` for `offset` values
**Medium Severity**
<!-- DESCRIPTION START -->
The `StateReadSlot` and `StateUpdateSlot` printer arms call `maybe_constant_to_doc` only for `len` but not for `offset`, even though `offset` is also a `Value` that could be an inline constant. Compare with ... | f9b815898a7db0e1cf775d62872a833fe5c87a4a | a871f09720d69cdb15106a526ac2493cbd687796 | diff --git a/sway-ir/src/printer.rs b/sway-ir/src/printer.rs
index f4b11cef96e..85657071e97 100644
--- a/sway-ir/src/printer.rs
+++ b/sway-ir/src/printer.rs
@@ -895,7 +895,21 @@ fn instruction_to_doc<'a>(
} => maybe_constant_to_doc(context, md_namer, namer, number_of_slots).append(
... | [
"sway-ir/src/printer.rs"
] | [
{
"comment": "### Printer missing `maybe_constant_to_doc` for `offset` values\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe `StateReadSlot` and `StateUpdateSlot` printer arms call `maybe_constant_to_doc` only for `len` but not for `offset`, even though `offset` is also a `Value` that could be an inl... | true | ||
FuelLabs/sway | 7,594 | issue_to_patch | Bump to 0.71.0 | ## Description
This PR bumps the `std` and the crates in `sway` repository to v0.71.0.
## Checklist
- [ ] I have linked to any relevant issues.
- [ ] I have commented my code, particularly in hard-to-understand areas.
- [ ] I have updated the documentation where relevant (API docs, the reference, and the Swa... | 011b75113331be21b5d3a1ca83f08dbf04654609 | 4c36f20bc9550e5cdf67efbc0326f6564cf8c33a | diff --git a/Cargo.lock b/Cargo.lock
index ce852af8c96..2fb28ed7759 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2505,7 +2505,7 @@ checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
[[package]]
name = "forc"
-version = "0.70.3"
+version = "0.71.0"
dependencies = [
"annotate-snippets",
... | [
"Cargo.lock",
"Cargo.toml",
"sway-lib-std/Forc.toml"
] | [] | true | ||
FuelLabs/sway | 7,593 | issue_to_patch | Fix default gas costs and add perf diff scripts to `storage_benchmarks` | ## Description
This PR:
- fixes inconsistent gas cost values across tools. All default gas costs are now obtained via `GasCostsSource::BuiltIn.provide_gas_costs()` method.
- improves analyzing `storage_benchmarks` by:
- printing histograms optionally when running benchmarks.
- adding the `perf_diff.sh` scrip... | 4382e71f35d8b7f7deed31fdace001dcb797118e | 4264490fe63b8098254a223b489cd8fe6a5be9ea | diff --git a/forc-plugins/forc-debug/src/server/mod.rs b/forc-plugins/forc-debug/src/server/mod.rs
index 5b4f7faddda..e19e046c97a 100644
--- a/forc-plugins/forc-debug/src/server/mod.rs
+++ b/forc-plugins/forc-debug/src/server/mod.rs
@@ -20,9 +20,8 @@ use forc_pkg::{
use forc_test::{
execute::{DebugResult, TestExe... | [
"forc-plugins/forc-debug/src/server/mod.rs",
"forc-test/src/lib.rs",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/.gitignore",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/RESULTS.md... | [
{
"comment": "### Unnecessary `unwrap()` and repeated deserialization in closure\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\n`GasCostsSource::BuiltIn.provide_gas_costs().unwrap()` is called inside a `filter_map` closure, introducing a panic point where every other call site uses `?` for graceful error... | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/.gitignore b/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/.gitignore
new file mode 100644
index 00000000000..13bad1647e4
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/.gitignore... | true | |
FuelLabs/sway | 7,593 | comment_to_fix | Fix default gas costs and add perf diff scripts to `storage_benchmarks` | ### Unnecessary `unwrap()` and repeated deserialization in closure
**Medium Severity**
<!-- DESCRIPTION START -->
`GasCostsSource::BuiltIn.provide_gas_costs().unwrap()` is called inside a `filter_map` closure, introducing a panic point where every other call site uses `?` for graceful error propagation. Since the enc... | 4382e71f35d8b7f7deed31fdace001dcb797118e | 4264490fe63b8098254a223b489cd8fe6a5be9ea | diff --git a/forc-plugins/forc-debug/src/server/mod.rs b/forc-plugins/forc-debug/src/server/mod.rs
index 5b4f7faddda..e19e046c97a 100644
--- a/forc-plugins/forc-debug/src/server/mod.rs
+++ b/forc-plugins/forc-debug/src/server/mod.rs
@@ -20,9 +20,8 @@ use forc_pkg::{
use forc_test::{
execute::{DebugResult, TestExe... | [
"forc-plugins/forc-debug/src/server/mod.rs"
] | [
{
"comment": "### Unnecessary `unwrap()` and repeated deserialization in closure\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\n`GasCostsSource::BuiltIn.provide_gas_costs().unwrap()` is called inside a `filter_map` closure, introducing a panic point where every other call site uses `?` for graceful error... | true | ||
FuelLabs/sway | 7,592 | issue_to_patch | Const Generics
This PR is the tracking-issue for the `const_generics` feature.
For more details go to: https://github.com/FuelLabs/sway-rfcs/pull/42
- [x] Feature toggle (https://github.com/FuelLabs/sway/pull/6926)
- [x] Parsing (https://github.com/FuelLabs/sway/pull/6926)
- [x] `impl` trait for arrays (https://gith... | Promote `const_generics` to a standard feature | ## Description
This PR promotes `const_generics` to a standard feature not anymore behind a feature flag.
#7512 made `const_generic` experimental feature enabled by default, but still kept it as experimental, with the decision to remove the feature flag as a part of the next breaking release 0.71.0.
- Closes #... | 0507c2c9a65a147ef2026fda8ac52ba7223aca40 | 14da455eda533c4e7b7c1daeef9164a5b9f04a00 | diff --git a/docs/book/src/reference/experimental_features.md b/docs/book/src/reference/experimental_features.md
index d06f8b3c772..acb56e5ed05 100644
--- a/docs/book/src/reference/experimental_features.md
+++ b/docs/book/src/reference/experimental_features.md
@@ -12,7 +12,7 @@ The list of [currently active](https://gi... | [
"docs/book/src/reference/experimental_features.md",
"docs/slides/const_generics.md",
"sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs",
"sway-features/src/lib.rs",
"sway-lib-std/generate.sh",
"sway-lib-std/src/clone.sw",
"sway-lib-std/src/codec.sw",
"sway-lib-std/src/debug.sw",
"sway-li... | [] | diff --git a/test/README.md b/test/README.md
index 39523895d49..64cfe6b0d60 100644
--- a/test/README.md
+++ b/test/README.md
@@ -120,7 +120,8 @@ To manipulate these blocks one can:
```toml
cmds = [
{ repeat = "for-each-block", cmds = [
- "forc test --path {root} --release --experimental const_generics"
+ ... | true |
FuelLabs/sway | 7,565 | issue_to_patch | Confusing error message when using non-const `tx_field_id` in `__gtf`
E.g:
```
let x = 0xA;
let _ = __gtf::<raw_ptr>(0, x);
^ Could not evaluate initializer to a const declaration.
```
We should provide a clear error message explaining that `tx_field_id` must be a `u64` constant. | Add `dynamic_storage` experimental feature and offset to `srw` opcode | ## Description
This PR is the first step in implementing #7560.
The PR:
- bumps `fuel-vm` dependencies to v0.66.
- bumps `fuel-core` dependencies to v0.48.
- bumps `fuels-rs` dependencies to v0.77.
- adds the `dynamic_storage` experimental feature.
- extends the `srw` opcode with an immediate offset.
- exte... | 076d4388ebb9b596949c7b802ffc83261e69597c | e3c9bf0432891f033f82e35d8fefc5927d06bf9b | diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 12c8140031e..65da388ac2f 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -437,6 +437,14 @@ jobs:
run: cargo run --locked --release -p forc -- build --release --locked --path ./test/src/sdk-harness --experimental str_... | [
".github/workflows/ci.yml",
"Cargo.lock",
"Cargo.toml",
"docs/book/src/reference/compiler_intrinsics.md",
"forc-plugins/forc-debug/src/server/handlers/handle_variables.rs",
"forc-test/gas_costs_values.json",
"sway-ast/src/expr/op_code.rs",
"sway-core/src/asm_generation/finalized_asm.rs",
"sway-core/... | [
{
"comment": "### `StateLoadWord` offset not hashed in function deduplication\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe `offset` field on `FuelVmInstruction::StateLoadWord` is not included in the hash computation for function deduplication. Two functions that are identical except for different `... | diff --git a/sway-ir/tests/serialize/storage_load.ir b/sway-ir/tests/serialize/storage_load.ir
index 0e3b61830c1..a83c9b6f09b 100644
--- a/sway-ir/tests/serialize/storage_load.ir
+++ b/sway-ir/tests/serialize/storage_load.ir
@@ -15,8 +15,8 @@ script {
v1 = const b256 0x7fbd1192666bfac3767b890bd4d048c940879d316... | true |
FuelLabs/sway | 7,565 | comment_to_fix | Add `dynamic_storage` experimental feature and offset to `srw` opcode | ### `StateLoadWord` offset not hashed in function deduplication
**Medium Severity**
<!-- DESCRIPTION START -->
The `offset` field on `FuelVmInstruction::StateLoadWord` is not included in the hash computation for function deduplication. Two functions that are identical except for different `StateLoadWord` offsets (e.g... | 076d4388ebb9b596949c7b802ffc83261e69597c | e3c9bf0432891f033f82e35d8fefc5927d06bf9b | diff --git a/sway-ir/src/optimize/fn_dedup.rs b/sway-ir/src/optimize/fn_dedup.rs
index cc524e29de6..86729268a77 100644
--- a/sway-ir/src/optimize/fn_dedup.rs
+++ b/sway-ir/src/optimize/fn_dedup.rs
@@ -252,9 +252,11 @@ fn hash_fn(
| crate::FuelVmInstruction::Smo { .. }
|... | [
"sway-ir/src/optimize/fn_dedup.rs"
] | [
{
"comment": "### `StateLoadWord` offset not hashed in function deduplication\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe `offset` field on `FuelVmInstruction::StateLoadWord` is not included in the hash computation for function deduplication. Two functions that are identical except for different `... | true | ||
FuelLabs/sway | 7,565 | comment_to_fix | Add `dynamic_storage` experimental feature and offset to `srw` opcode | ### Git branch patches in Cargo.toml must not be merged
**High Severity**
<!-- DESCRIPTION START -->
The `[patch.crates-io]` section pins dependencies to unreleased git branches (`fuel-core` on `dento/dynamic-storage`, `fuels-rs` on `ironcev/clonable-isuseraccountvariables`, `fuel-vm` on main). If merged, the main br... | 076d4388ebb9b596949c7b802ffc83261e69597c | e3c9bf0432891f033f82e35d8fefc5927d06bf9b | diff --git a/Cargo.toml b/Cargo.toml
index 5ac30c6e3da..37efa59081c 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -41,15 +41,14 @@ iter_over_hash_type = "deny"
# Internal dependencies in order to propagate `workspace.version`
#
+# Forc
forc = { path = "forc/", version = "0.70.3" }
forc-pkg = { path = "forc-pkg/", v... | [
"Cargo.toml"
] | [
{
"comment": "### Git branch patches in Cargo.toml must not be merged\n\n**High Severity**\n\n<!-- DESCRIPTION START -->\nThe `[patch.crates-io]` section pins dependencies to unreleased git branches (`fuel-core` on `dento/dynamic-storage`, `fuels-rs` on `ironcev/clonable-isuseraccountvariables`, `fuel-vm` on ma... | true | ||
FuelLabs/sway | 7,565 | comment_to_fix | Add `dynamic_storage` experimental feature and offset to `srw` opcode | ### Unused `poke` function in new test file
**Low Severity**
<!-- DESCRIPTION START -->
The `poke` function is defined with `#[inline(never)]` but never called anywhere in the file. It appears to be leftover scaffolding, possibly copied from another test that needed to prevent dead-code elimination.
<!-- DESCRIPTION ... | 076d4388ebb9b596949c7b802ffc83261e69597c | e3c9bf0432891f033f82e35d8fefc5927d06bf9b | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/asm/storage_instructions/src/main.sw b/test/src/e2e_vm_tests/test_programs/should_pass/language/asm/storage_instructions/src/main.sw
new file mode 100644
index 00000000000..24980b78e93
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_programs/should_pa... | [
"test/src/e2e_vm_tests/test_programs/should_pass/language/asm/storage_instructions/src/main.sw"
] | [
{
"comment": "### Unused `poke` function in new test file\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\nThe `poke` function is defined with `#[inline(never)]` but never called anywhere in the file. It appears to be leftover scaffolding, possibly copied from another test that needed to prevent dead-code eli... | true | ||
FuelLabs/sway | 7,588 | issue_to_patch | Add comprehensive benchmarks for `StorageVec` | ## Description
This PR is a continuation of #7583. It adds additional benchmarks for benchmarking all `StorageVec` API methods for different element sizes and different number of elements stored.
The `README.md` explains the benchmarks and how to use the benchmarking infrastructure.
The `RESULTS.md` contains t... | 551e37f20aa44e49f2520e333e2934b3d209f820 | c26d6fc22d061f92aef1e6435c589918e3ac2c37 | [
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/RESULTS.md",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/bench_storage_vec.sh",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_b... | [] | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md b/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md
index f03ee0b1165..453bbf2516b 100644
--- a/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md
+++ b/test/src/e2e_vm_tests/te... | true | ||
FuelLabs/sway | 7,587 | issue_to_patch | Pin tracing-subscriber to 0.3.19 | ## Summary
Pin `tracing-subscriber` to `0.3.19`.
## Why
`forc` output regressed because newer `tracing-subscriber` releases escape ANSI sequences in normal terminal output. This was not a snapshot-test-only issue; it changed compiler and CLI output behavior in general. Pinning to `0.3.19` restores the previous behav... | 31d4ea8e68762d7a6fdeb572bccd439b2e5213f9 | a73428e7bf6d4cbd47bce903a89a36f156e78f1d | diff --git a/.github/workflows/scripts/check-dep-versions/src/main.rs b/.github/workflows/scripts/check-dep-versions/src/main.rs
index 0015e6a8311..066d15232c6 100644
--- a/.github/workflows/scripts/check-dep-versions/src/main.rs
+++ b/.github/workflows/scripts/check-dep-versions/src/main.rs
@@ -7,9 +7,16 @@ use toml::... | [
".github/workflows/scripts/check-dep-versions/src/main.rs",
"Cargo.lock",
"Cargo.toml"
] | [] | true | ||
FuelLabs/sway | 7,585 | issue_to_patch | Remove forc-mcp from sway repo | ## Summary
This temporarily removes `forc-mcp` from the Sway repo so we can unblock the upcoming Sway release work and break the current release-order circular dependency.
The immediate issue is that `forc-mcp` still lives in this repo while depending on `forc-client` from the `forc` repo, which makes the Sway and Fo... | cd2aa3562318186e6316edc89721084c69099f56 | da43263b2d39149139144f0ff2badec8efcaea12 | diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 0e379449fce..12c8140031e 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -235,6 +235,8 @@ jobs:
run: cargo install --locked --path ./forc
- name: Install Forc plugins
run: |
+ cargo uninstall... | [
".github/workflows/ci.yml",
".github/workflows/gh-pages.yml",
"Cargo.lock",
"Cargo.toml",
"docs/book/src/SUMMARY.md",
"docs/book/src/forc/plugins/forc_mcp/forc_call_tool/common_commands.md",
"docs/book/src/forc/plugins/forc_mcp/forc_call_tool/contract_samples.md",
"docs/book/src/forc/plugins/forc_mcp/... | [] | diff --git a/forc-plugins/forc-mcp/test/data/contract_with_types/Forc.toml b/forc-plugins/forc-mcp/test/data/contract_with_types/Forc.toml
deleted file mode 100644
index 90dae6aa4f1..00000000000
--- a/forc-plugins/forc-mcp/test/data/contract_with_types/Forc.toml
+++ /dev/null
@@ -1,5 +0,0 @@
-[project]
-authors = ["Fue... | true | |
FuelLabs/sway | 7,299 | issue_to_patch | Optimize initialization of array repeat when the initial value is zero | ## Description
Continuation of https://github.com/FuelLabs/sway/issues/6860.
This PR improves performance of arrays initialized with zero like `[0u16; 5]`. Before, the compiler was initializing the array with `SW` or using a loop, depending on the array size. Now it is being initialized with just one `MCLI`.
E... | f9fcb0edc308edba34d9cbf43ade15882614677d | fb2758255a53ebad95a74d269d688cf435846d45 | diff --git a/sway-core/src/abi_generation/abi_str.rs b/sway-core/src/abi_generation/abi_str.rs
index decaaf27b38..263122461a0 100644
--- a/sway-core/src/abi_generation/abi_str.rs
+++ b/sway-core/src/abi_generation/abi_str.rs
@@ -57,8 +57,11 @@ impl TypeId {
}
(TypeInfo::Array(_, length... | [
"sway-core/src/abi_generation/abi_str.rs",
"sway-core/src/asm_generation/evm/evm_asm_builder.rs",
"sway-core/src/asm_generation/fuel/fuel_asm_builder.rs",
"sway-core/src/asm_lang/allocated_ops.rs",
"sway-core/src/asm_lang/virtual_immediate.rs",
"sway-core/src/ir_generation/function.rs",
"sway-core/src/s... | [
{
"comment": "Is that intended to be implemented in a later PR or what?",
"path": "sway-core/src/asm_generation/evm/evm_asm_builder.rs",
"hunk": "@@ -353,6 +353,9 @@ impl<'ir, 'eng> EvmAsmBuilder<'ir, 'eng> {\n dst_val_ptr,\n src_val_ptr,\n } => se... | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/language/const_generics/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_fail/language/const_generics/stdout.snap
index c8b0e93b214..6a84614ef2b 100644
--- a/test/src/e2e_vm_tests/test_programs/should_fail/language/const_generics/stdout.snap
+++ b/tes... | true | |
FuelLabs/sway | 7,299 | comment_to_fix | Optimize initialization of array repeat when the initial value is zero | Is that intended to be implemented in a later PR or what? | f9fcb0edc308edba34d9cbf43ade15882614677d | fb2758255a53ebad95a74d269d688cf435846d45 | diff --git a/sway-core/src/asm_generation/evm/evm_asm_builder.rs b/sway-core/src/asm_generation/evm/evm_asm_builder.rs
index 16fd7fd2758..989258ea575 100644
--- a/sway-core/src/asm_generation/evm/evm_asm_builder.rs
+++ b/sway-core/src/asm_generation/evm/evm_asm_builder.rs
@@ -353,6 +353,9 @@ impl<'ir, 'eng> EvmAsmBuild... | [
"sway-core/src/asm_generation/evm/evm_asm_builder.rs"
] | [
{
"comment": "Is that intended to be implemented in a later PR or what?",
"path": "sway-core/src/asm_generation/evm/evm_asm_builder.rs",
"hunk": "@@ -353,6 +353,9 @@ impl<'ir, 'eng> EvmAsmBuilder<'ir, 'eng> {\n dst_val_ptr,\n src_val_ptr,\n } => se... | true | ||
FuelLabs/sway | 7,299 | comment_to_fix | Optimize initialization of array repeat when the initial value is zero | `VirtualImmediate18::new_unchecked` must never be used without a check if the value actually fits into 18 bits.
My general issue with `new_unchecked` is that it gives us a false sense of security. It will panic, but only if the provided value is larger then the underlying type, which is `u32` for `VirtualImmediate18`.... | f9fcb0edc308edba34d9cbf43ade15882614677d | fb2758255a53ebad95a74d269d688cf435846d45 | diff --git a/sway-core/src/asm_generation/fuel/fuel_asm_builder.rs b/sway-core/src/asm_generation/fuel/fuel_asm_builder.rs
index 08b86dcd2e2..112c912c750 100644
--- a/sway-core/src/asm_generation/fuel/fuel_asm_builder.rs
+++ b/sway-core/src/asm_generation/fuel/fuel_asm_builder.rs
@@ -24,7 +24,6 @@ use crate::{
Bui... | [
"sway-core/src/asm_generation/fuel/fuel_asm_builder.rs"
] | [
{
"comment": "`VirtualImmediate18::new_unchecked` must never be used without a check if the value actually fits into 18 bits.\n\nMy general issue with `new_unchecked` is that it gives us a false sense of security. It will panic, but only if the provided value is larger then the underlying type, which is `u32` f... | true | ||
FuelLabs/sway | 7,410 | issue_to_patch | Bump to v0.69.4 | 7d45f82d11a7df26ac1b868ad9a87ccb1c553ad7 | e907a527f40108ae144a797b50fec08d34b18781 | diff --git a/Cargo.lock b/Cargo.lock
index 4e45b7420dc..d2973e9fdc0 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -3712,7 +3712,7 @@ checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
[[package]]
name = "forc"
-version = "0.69.3"
+version = "0.69.4"
dependencies = [
"annotate-snippets",
... | [
"Cargo.lock",
"Cargo.toml",
"sway-lib-std/Forc.toml"
] | [] | true | |||
FuelLabs/sway | 7,239 | issue_to_patch | Fix forc-test dependency to include the tx feature | b9ac2a9bdb2069b1c70637be4e2d4ae93361c73f | 4103313d4ff0fa69cee7493bd95c8453b929d9ff | diff --git a/forc-test/Cargo.toml b/forc-test/Cargo.toml
index 5b14752cd2f..cc65b23aeb2 100644
--- a/forc-test/Cargo.toml
+++ b/forc-test/Cargo.toml
@@ -11,7 +11,7 @@ repository.workspace = true
[dependencies]
anyhow.workspace = true
forc-pkg.workspace = true
-forc-util.workspace = true
+forc-util = { workspace = tr... | [
"forc-test/Cargo.toml"
] | [] | true | |||
FuelLabs/sway | 7,583 | issue_to_patch | Add comprehensive benchmarks for storage access | ## Description
This PR adds comprehensive benchmarks for storage fields access. We want to have the benchmark and historical values collected, in order to be able to compare them with the storage access costs after #7560 is implemented.
The `README.md` explains the benchmarks and how to use the benchmarking infra... | 8e643df9de76cb6dbf7972382fed15f820230cff | 97f3a232bbf7ffc26f16a0f9492c4b7983a4d2e8 | [
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/RESULTS.md",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/bench.sh",
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/st... | [
{
"comment": "### Wrong package name in stored_types Forc.lock\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\nThe `stored_types/Forc.lock` is a verbatim copy of the `storage_slot_key_calculation/Forc.lock` from a different project. It declares `name = \"storage_slot_key_calculation\"` instead of `\"stored_t... | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md b/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md
new file mode 100644
index 00000000000..f03ee0b1165
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/README.md
@@... | true | ||
FuelLabs/sway | 7,583 | comment_to_fix | Add comprehensive benchmarks for storage access | ### Wrong package name in stored_types Forc.lock
**Low Severity**
<!-- DESCRIPTION START -->
The `stored_types/Forc.lock` is a verbatim copy of the `storage_slot_key_calculation/Forc.lock` from a different project. It declares `name = "storage_slot_key_calculation"` instead of `"stored_types"`, and lists `std` as a d... | 8e643df9de76cb6dbf7972382fed15f820230cff | 97f3a232bbf7ffc26f16a0f9492c4b7983a4d2e8 | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/stored_types/Forc.lock b/test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/stored_types/Forc.lock
new file mode 100644
index 00000000000..2105ecffce8
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_programs/should_pass/stora... | [
"test/src/e2e_vm_tests/test_programs/should_pass/storage_benchmarks/stored_types/Forc.lock"
] | [
{
"comment": "### Wrong package name in stored_types Forc.lock\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\nThe `stored_types/Forc.lock` is a verbatim copy of the `storage_slot_key_calculation/Forc.lock` from a different project. It declares `name = \"storage_slot_key_calculation\"` instead of `\"stored_t... | true | ||
FuelLabs/sway | 7,247 | issue_to_patch | bump to 0.68.9 | ## Description
~~waiting on #7246 which fixes a critical bug in `forc pkg`~~
## Checklist
- [x] I have linked to any relevant issues.
- [ ] I have commented my code, particularly in hard-to-understand areas.
- [ ] I have updated the documentation where relevant (API docs, the reference, and the Sway book).
... | b21e87e4aa0ea6a7ebf1ff24b5f0474ff71e42b7 | ba4b97c051240b8678ff82d9b604dd2703b46e45 | diff --git a/Cargo.lock b/Cargo.lock
index c70a843a305..e149dbb7027 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2880,7 +2880,7 @@ checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
[[package]]
name = "forc"
-version = "0.68.8"
+version = "0.68.9"
dependencies = [
"annotate-snippets",
... | [
"Cargo.lock",
"Cargo.toml",
"sway-lib-std/Forc.toml",
"sway-lsp/tests/lib.rs"
] | [] | diff --git a/sway-lsp/tests/lib.rs b/sway-lsp/tests/lib.rs
index 284ffc7ab66..ce752d2caf0 100644
--- a/sway-lsp/tests/lib.rs
+++ b/sway-lsp/tests/lib.rs
@@ -294,7 +294,8 @@ fn sync_with_updates_to_manifest_in_workspace() {
});
}
-#[test]
+#[allow(dead_code)]
+// #[test]
fn did_cache_test() {
run_async!({
... | true | |
FuelLabs/sway | 7,580 | issue_to_patch | `cfg` attribute not working in `impl Contract`
E.g., this compiles as expected:
```sway
contract;
abi MyContract {
fn some_contract_method();
}
impl MyContract for Contract {
#[cfg(experimental_new_encoding = true)]
fn some_contract_method() { }
#[cfg(experimental_new_encoding = false)]
fn some... | Support attributes and constants in self `impl Contract`s | ## Description
This PR effectively re-implements self `impl Contract` implementation in order to:
- properly handle attributes:
- fix #7574 by `cfg_eval`ing items before adding them to the contract's interface surface and items.
- add missing error-handling of invalid attributes.
- take over applicable at... | cf207d23df1ded1b21b0fb00a5cfb56175e0f354 | a62000fc6206dad3d5136cf66f548a795663a625 | diff --git a/sway-core/src/language/parsed/declaration/impl_trait.rs b/sway-core/src/language/parsed/declaration/impl_trait.rs
index b5dc4632a07..420d623008c 100644
--- a/sway-core/src/language/parsed/declaration/impl_trait.rs
+++ b/sway-core/src/language/parsed/declaration/impl_trait.rs
@@ -61,8 +61,11 @@ impl DebugWi... | [
"sway-core/src/language/parsed/declaration/impl_trait.rs",
"sway-core/src/transform/attribute.rs",
"sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs",
"test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_self_impl/Forc.lock",
"test/src/e2e_vm_tests/test_programs/sh... | [
{
"comment": "### Wrong filter allows excluded attributes on ABI interface\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe code comment at lines 976–978 explicitly states that `#[inline]` is \"not on the ABI interface method itself,\" yet the filter calls `can_annotate_abi_or_trait_item_fn` which retu... | diff --git a/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_self_impl/Forc.lock b/test/src/e2e_vm_tests/test_programs/should_fail/attributes_invalid_target_contract_self_impl/Forc.lock
new file mode 100644
index 00000000000..0e3fb051ae8
--- /dev/null
+++ b/test/src/e2e_vm_tests/test_... | true |
FuelLabs/sway | 7,580 | comment_to_fix | Support attributes and constants in self `impl Contract`s | ### Wrong filter allows excluded attributes on ABI interface
**Medium Severity**
<!-- DESCRIPTION START -->
The code comment at lines 976–978 explicitly states that `#[inline]` is "not on the ABI interface method itself," yet the filter calls `can_annotate_abi_or_trait_item_fn` which returns `true` for `Inline`, `Tra... | cf207d23df1ded1b21b0fb00a5cfb56175e0f354 | a62000fc6206dad3d5136cf66f548a795663a625 | diff --git a/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs b/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
index c75ecae6cd3..e27d5275d32 100644
--- a/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
+++ b/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
@@ -5,7 +5,... | [
"sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs"
] | [
{
"comment": "### Wrong filter allows excluded attributes on ABI interface\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe code comment at lines 976–978 explicitly states that `#[inline]` is \"not on the ABI interface method itself,\" yet the filter calls `can_annotate_abi_or_trait_item_fn` which retu... | true | ||
FuelLabs/sway | 7,580 | comment_to_fix | Support attributes and constants in self `impl Contract`s | ### Shared constant declaration ID between ABI and impl
**Medium Severity**
<!-- DESCRIPTION START -->
The `Const` case reuses the same `ParsedDeclId` for both `TraitItem::Constant` (ABI interface surface) and `ImplItem::Constant` (impl items). Unlike the `Fn` case — which creates separate declarations with different... | cf207d23df1ded1b21b0fb00a5cfb56175e0f354 | a62000fc6206dad3d5136cf66f548a795663a625 | diff --git a/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs b/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
index c75ecae6cd3..e27d5275d32 100644
--- a/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
+++ b/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
@@ -5,7 +5,... | [
"sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs"
] | [
{
"comment": "### Shared constant declaration ID between ABI and impl\n\n**Medium Severity**\n\n<!-- DESCRIPTION START -->\nThe `Const` case reuses the same `ParsedDeclId` for both `TraitItem::Constant` (ABI interface surface) and `ImplItem::Constant` (impl items). Unlike the `Fn` case — which creates separate ... | true | ||
FuelLabs/sway | 7,580 | comment_to_fix | Support attributes and constants in self `impl Contract`s | Documentation only shows this attribute on types, but it seems strange that we cannot change abi names of fns on abis.... | cf207d23df1ded1b21b0fb00a5cfb56175e0f354 | a62000fc6206dad3d5136cf66f548a795663a625 | diff --git a/sway-core/src/transform/attribute.rs b/sway-core/src/transform/attribute.rs
index 9dda56c00f8..fd144d75441 100644
--- a/sway-core/src/transform/attribute.rs
+++ b/sway-core/src/transform/attribute.rs
@@ -582,6 +582,29 @@ impl Attribute {
}
}
+ pub(crate) fn can_annotate_abi(&self) -> boo... | [
"sway-core/src/transform/attribute.rs"
] | [
{
"comment": "Documentation only shows this attribute on types, but it seems strange that we cannot change abi names of fns on abis....",
"path": "sway-core/src/transform/attribute.rs",
"hunk": "@@ -699,6 +732,85 @@ impl Attribute {\n }\n }\n \n+ /// True if `self` can annotate an *interf... | true | ||
FuelLabs/sway | 7,580 | comment_to_fix | Support attributes and constants in self `impl Contract`s | Same. | cf207d23df1ded1b21b0fb00a5cfb56175e0f354 | a62000fc6206dad3d5136cf66f548a795663a625 | diff --git a/sway-core/src/transform/attribute.rs b/sway-core/src/transform/attribute.rs
index 9dda56c00f8..fd144d75441 100644
--- a/sway-core/src/transform/attribute.rs
+++ b/sway-core/src/transform/attribute.rs
@@ -582,6 +582,29 @@ impl Attribute {
}
}
+ pub(crate) fn can_annotate_abi(&self) -> boo... | [
"sway-core/src/transform/attribute.rs"
] | [
{
"comment": "Same.",
"path": "sway-core/src/transform/attribute.rs",
"hunk": "@@ -699,6 +732,85 @@ impl Attribute {\n }\n }\n \n+ /// True if `self` can annotate an *interface* function of a trait or ABI.\n+ /// E.g.:\n+ /// ```ignore\n+ /// trait Trait {\n+ /// #[some_attr... | true | ||
FuelLabs/sway | 7,580 | comment_to_fix | Support attributes and constants in self `impl Contract`s | Probably better to whitelist what we support, right? Just to be sure. | cf207d23df1ded1b21b0fb00a5cfb56175e0f354 | a62000fc6206dad3d5136cf66f548a795663a625 | diff --git a/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs b/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
index c75ecae6cd3..e27d5275d32 100644
--- a/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
+++ b/sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs
@@ -5,7 +5,... | [
"sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs"
] | [
{
"comment": "Probably better to whitelist what we support, right? Just to be sure.",
"path": "sway-core/src/transform/to_parsed_lang/convert_parse_tree.rs",
"hunk": "@@ -892,140 +909,177 @@ pub fn item_impl_to_declaration(\n }\n }\n \n+/// Compiler generated declarations for an `impl Contract` bloc... | true | ||
FuelLabs/sway | 7,566 | issue_to_patch | Slides for trivial encoding, const generics and dbg | ## Description
Slides and better documentation for trivial encoding, const generics and `__dbg`.
## Checklist
- [ ] I have linked to any relevant issues.
- [ ] I have commented my code, particularly in hard-to-understand areas.
- [x] I have updated the documentation where relevant (API docs, the reference, a... | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/const_generics.md b/docs/slides/const_generics.md
new file mode 100644
index 00000000000..8e0455d307a
--- /dev/null
+++ b/docs/slides/const_generics.md
@@ -0,0 +1,76 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Const Generics
+
+`const generics` let you parameteri... | [
"docs/slides/const_generics.md",
"docs/slides/dbg.md",
"docs/slides/trivial_encoding.md"
] | [
{
"comment": "```suggestion\nThis allowed us to implement all the `std` traits for arrays, string arrays etc.\n```",
"path": "docs/slides/const_generics.md",
"hunk": "@@ -0,0 +1,76 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Const Generics\n+\n+`const generics` let... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
This allowed us to implement all the `std` traits for arrays, string arrays etc.
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/const_generics.md b/docs/slides/const_generics.md
new file mode 100644
index 00000000000..8e0455d307a
--- /dev/null
+++ b/docs/slides/const_generics.md
@@ -0,0 +1,76 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Const Generics
+
+`const generics` let you parameteri... | [
"docs/slides/const_generics.md"
] | [
{
"comment": "```suggestion\nThis allowed us to implement all the `std` traits for arrays, string arrays etc.\n```",
"path": "docs/slides/const_generics.md",
"hunk": "@@ -0,0 +1,76 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Const Generics\n+\n+`const generics` let... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
- etc.
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/const_generics.md b/docs/slides/const_generics.md
new file mode 100644
index 00000000000..8e0455d307a
--- /dev/null
+++ b/docs/slides/const_generics.md
@@ -0,0 +1,76 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Const Generics
+
+`const generics` let you parameteri... | [
"docs/slides/const_generics.md"
] | [
{
"comment": "```suggestion\n- etc.\n```",
"path": "docs/slides/const_generics.md",
"hunk": "@@ -0,0 +1,76 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Const Generics\n+\n+`const generics` let you parameterize types and functions with compile‑time constant values, e... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
"const generics" can be used on structs, enums, functions, impls etc.
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/const_generics.md b/docs/slides/const_generics.md
new file mode 100644
index 00000000000..8e0455d307a
--- /dev/null
+++ b/docs/slides/const_generics.md
@@ -0,0 +1,76 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Const Generics
+
+`const generics` let you parameteri... | [
"docs/slides/const_generics.md"
] | [
{
"comment": "```suggestion\n\"const generics\" can be used on structs, enums, functions, impls etc.\n```",
"path": "docs/slides/const_generics.md",
"hunk": "@@ -0,0 +1,76 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Const Generics\n+\n+`const generics` let you para... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
- What it does
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/dbg.md b/docs/slides/dbg.md
new file mode 100644
index 00000000000..b7a72f6c201
--- /dev/null
+++ b/docs/slides/dbg.md
@@ -0,0 +1,215 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Sway `__dbg`
+
+- What it does
+- How it works (High Level)
+- How it works (Low Leve... | [
"docs/slides/dbg.md"
] | [
{
"comment": "```suggestion\n- What it does\n```",
"path": "docs/slides/dbg.md",
"hunk": "@@ -0,0 +1,214 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Sway `__dbg`\n+\n+- What it does?",
"resolving_sha": "c9e6eae53020e7a85177b2a89abecb9f52895881",
"resolving_... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
All other primitive `impls` live in `sway-lib-std/src/debug.sw`.
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/dbg.md b/docs/slides/dbg.md
new file mode 100644
index 00000000000..b7a72f6c201
--- /dev/null
+++ b/docs/slides/dbg.md
@@ -0,0 +1,215 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Sway `__dbg`
+
+- What it does
+- How it works (High Level)
+- How it works (Low Leve... | [
"docs/slides/dbg.md"
] | [
{
"comment": "```suggestion\nAll other primitive `impls` live in `sway-lib-std/src/debug.sw`.\n```",
"path": "docs/slides/dbg.md",
"hunk": "@@ -0,0 +1,214 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Sway `__dbg`\n+\n+- What it does?\n+- How it works (High Level)\n+... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
We reserved [0, 1000), for the VM, [1000, 2000) for the compiler and [2000, 3000) for the tooling purposes. This way, we can avoid a program having different behavior depending on the interpreter configuration.
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/dbg.md b/docs/slides/dbg.md
new file mode 100644
index 00000000000..b7a72f6c201
--- /dev/null
+++ b/docs/slides/dbg.md
@@ -0,0 +1,215 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Sway `__dbg`
+
+- What it does
+- How it works (High Level)
+- How it works (Low Leve... | [
"docs/slides/dbg.md"
] | [
{
"comment": "```suggestion\nWe reserved [0, 1000), for the VM, [1000, 2000) for the compiler and [2000, 3000) for the tooling purposes. This way, we can avoid a program having different behavior depending on the interpreter configuration.\n```",
"path": "docs/slides/dbg.md",
"hunk": "@@ -0,0 +1,214 @@\... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
Real implementation in `forc-test/src/ecal.rs`
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/dbg.md b/docs/slides/dbg.md
new file mode 100644
index 00000000000..b7a72f6c201
--- /dev/null
+++ b/docs/slides/dbg.md
@@ -0,0 +1,215 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Sway `__dbg`
+
+- What it does
+- How it works (High Level)
+- How it works (Low Leve... | [
"docs/slides/dbg.md"
] | [
{
"comment": "```suggestion\nReal implementation in `forc-test/src/ecal.rs`\n```",
"path": "docs/slides/dbg.md",
"hunk": "@@ -0,0 +1,214 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Sway `__dbg`\n+\n+- What it does?\n+- How it works (High Level)\n+- How it works (Lo... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
Different from `AbiEncode`, `Debug` auto implementation works for any primitive data type, including `raw_ptr`, `raw_slice`, references, etc. So the compiler will generate auto implementation for any type, unless a custom implementation is found.
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/dbg.md b/docs/slides/dbg.md
new file mode 100644
index 00000000000..b7a72f6c201
--- /dev/null
+++ b/docs/slides/dbg.md
@@ -0,0 +1,215 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Sway `__dbg`
+
+- What it does
+- How it works (High Level)
+- How it works (Low Leve... | [
"docs/slides/dbg.md"
] | [
{
"comment": "```suggestion\nDifferent from `AbiEncode`, `Debug` auto implementation works for any primitive data type, including `raw_ptr`, `raw_slice`, references, etc. So the compiler will generate auto implementation for any type, unless a custom implementation is found.\n```",
"path": "docs/slides/dbg.... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
So deploying binaries with it would be wasteful.
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/dbg.md b/docs/slides/dbg.md
new file mode 100644
index 00000000000..b7a72f6c201
--- /dev/null
+++ b/docs/slides/dbg.md
@@ -0,0 +1,215 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Sway `__dbg`
+
+- What it does
+- How it works (High Level)
+- How it works (Low Leve... | [
"docs/slides/dbg.md"
] | [
{
"comment": "```suggestion\nSo deploying binaries with it would be wasteful.\n```",
"path": "docs/slides/dbg.md",
"hunk": "@@ -0,0 +1,214 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Sway `__dbg`\n+\n+- What it does?\n+- How it works (High Level)\n+- How it works (... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
But, if there is a troubleshooting needed in release build, one can force the compiler to emit `__dbg` by using:
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/dbg.md b/docs/slides/dbg.md
new file mode 100644
index 00000000000..b7a72f6c201
--- /dev/null
+++ b/docs/slides/dbg.md
@@ -0,0 +1,215 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Sway `__dbg`
+
+- What it does
+- How it works (High Level)
+- How it works (Low Leve... | [
"docs/slides/dbg.md"
] | [
{
"comment": "```suggestion\nBut, if there is a troubleshooting needed in release build, one can force the compiler to emit `__dbg` by using:\n```",
"path": "docs/slides/dbg.md",
"hunk": "@@ -0,0 +1,214 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownlint-disable -->\n+# Sway `__dbg`\n+\n+... | true | ||
FuelLabs/sway | 7,566 | comment_to_fix | Slides for trivial encoding, const generics and dbg | ```suggestion
If developers are OK with the risks and wants to deal with invalid representation manually, they can force triviality of a type by doing:
``` | 0d16c93b2470d61f669dc7907d53eb20aeb444f4 | c9e6eae53020e7a85177b2a89abecb9f52895881 | diff --git a/docs/slides/trivial_encoding.md b/docs/slides/trivial_encoding.md
new file mode 100644
index 00000000000..925df7ac951
--- /dev/null
+++ b/docs/slides/trivial_encoding.md
@@ -0,0 +1,176 @@
+---
+layout: cover
+marp: true
+---
+
+<!-- markdownlint-disable -->
+# Trivially Encodable/Decodable Types
+
+- Encod... | [
"docs/slides/trivial_encoding.md"
] | [
{
"comment": "```suggestion\nIf developers are OK with the risks and wants to deal with invalid representation manually, they can force triviality of a type by doing:\n```",
"path": "docs/slides/trivial_encoding.md",
"hunk": "@@ -0,0 +1,176 @@\n+---\n+layout: cover\n+marp: true\n+---\n+\n+<!-- markdownl... | true | ||
FuelLabs/sway | 7,561 | issue_to_patch | Optimise `pshl` | ## Description
Change the order of register allocation... instead of starting from "lower" registers... it starts from higher registers... that means that for functions with very few registers, there is no need to save them with `pshl`. Example:
```sway
#[inline(never)]
fn leaf_fn_6(a: u64, b: u64, c: u64, d: u... | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs b/sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs
index abdfde3511e..726d4ee65e8 100644
--- a/sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs
+++ b/sway-core/src/asm_generation/fuel/alloc... | [
"forc-plugins/forc-debug/tests/server_integration.rs",
"forc/tests/cli_integration.rs",
"sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs",
"sway-core/src/asm_generation/fuel/compiler_constants.rs",
"sway-core/src/asm_generation/fuel/programs/abstract.rs",
"sway-core/src/asm_lang/al... | [
{
"comment": "### Off-by-one excludes valid register 16 from allocation\n\n**High Severity**\n\n<!-- DESCRIPTION START -->\nThe boundary check `if id <= 16` incorrectly excludes register 16, which is a valid allocatable register. `NUM_ALLOCATABLE_REGISTERS` is 37, so the register allocator creates `Allocated(0)... | diff --git a/forc-plugins/forc-debug/tests/server_integration.rs b/forc-plugins/forc-debug/tests/server_integration.rs
index 30d71f0f10a..3e7d8ee9eb5 100644
--- a/forc-plugins/forc-debug/tests/server_integration.rs
+++ b/forc-plugins/forc-debug/tests/server_integration.rs
@@ -315,10 +315,10 @@ fn test_sourcemap_build()... | true | |
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | ### Off-by-one excludes valid register 16 from allocation
**High Severity**
<!-- DESCRIPTION START -->
The boundary check `if id <= 16` incorrectly excludes register 16, which is a valid allocatable register. `NUM_ALLOCATABLE_REGISTERS` is 37, so the register allocator creates `Allocated(0)` through `Allocated(36)`. ... | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/sway-core/src/asm_lang/allocated_ops.rs b/sway-core/src/asm_lang/allocated_ops.rs
index 435fad05fa6..9c61b8f1ca8 100644
--- a/sway-core/src/asm_lang/allocated_ops.rs
+++ b/sway-core/src/asm_lang/allocated_ops.rs
@@ -12,7 +12,9 @@
use super::*;
use crate::{
asm_generation::fuel::{
- compiler_c... | [
"sway-core/src/asm_lang/allocated_ops.rs"
] | [
{
"comment": "### Off-by-one excludes valid register 16 from allocation\n\n**High Severity**\n\n<!-- DESCRIPTION START -->\nThe boundary check `if id <= 16` incorrectly excludes register 16, which is a valid allocatable register. `NUM_ALLOCATABLE_REGISTERS` is 37, so the register allocator creates `Allocated(0)... | true | ||
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | ### Commented-out debug eprintln left in code
**Low Severity**
<!-- DESCRIPTION START -->
A commented-out `eprintln!` debug statement was left in the code. This looks like a development/debugging artifact that wasn't cleaned up before committing.
<!-- DESCRIPTION END -->
<!-- BUGBOT_BUG_ID: d61cff86-9b19-4db3-a0df-5... | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs b/sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs
index abdfde3511e..726d4ee65e8 100644
--- a/sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs
+++ b/sway-core/src/asm_generation/fuel/alloc... | [
"sway-core/src/asm_generation/fuel/allocated_abstract_instruction_set.rs"
] | [
{
"comment": "### Commented-out debug eprintln left in code\n\n**Low Severity**\n\n<!-- DESCRIPTION START -->\nA commented-out `eprintln!` debug statement was left in the code. This looks like a development/debugging artifact that wasn't cleaned up before committing.\n<!-- DESCRIPTION END -->\n\n<!-- BUGBOT_BUG... | true | ||
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | ### Unresolved git merge conflict markers in snapshot files
**High Severity**
<!-- DESCRIPTION START -->
Multiple snapshot files (`.snap`) contain unresolved git merge conflict markers (`<<<<<<<`, `=======`, `>>>>>>>`). These appear in at least a dozen test snapshot files including `array_repeat`, `const_generics`, `... | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap b/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap
index 6199f3cdf73..a4d299310c5 100644
--- a/test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.sn... | [
"test/src/e2e_vm_tests/test_programs/should_pass/language/array/array_repeat/stdout.snap"
] | [
{
"comment": "### Unresolved git merge conflict markers in snapshot files\n\n**High Severity**\n\n<!-- DESCRIPTION START -->\nMultiple snapshot files (`.snap`) contain unresolved git merge conflict markers (`<<<<<<<`, `=======`, `>>>>>>>`). These appear in at least a dozen test snapshot files including `array_r... | true | ||
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | ```suggestion
(3, 1, "main function parameters"), // Should have 1 instruction
``` | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/forc-plugins/forc-debug/tests/server_integration.rs b/forc-plugins/forc-debug/tests/server_integration.rs
index 30d71f0f10a..3e7d8ee9eb5 100644
--- a/forc-plugins/forc-debug/tests/server_integration.rs
+++ b/forc-plugins/forc-debug/tests/server_integration.rs
@@ -315,10 +315,10 @@ fn test_sourcemap_build()... | [
"forc-plugins/forc-debug/tests/server_integration.rs"
] | [
{
"comment": "```suggestion\n (3, 1, \"main function parameters\"), // Should have 1 instruction\n```",
"path": "forc-plugins/forc-debug/tests/server_integration.rs",
"hunk": "@@ -315,10 +315,10 @@ fn test_sourcemap_build() {\n // Verify essential source locations are mapped correctly\n l... | true | ||
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | ```suggestion
(11, 1, "helper function parameters"), // Should have 1 instruction
``` | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/forc-plugins/forc-debug/tests/server_integration.rs b/forc-plugins/forc-debug/tests/server_integration.rs
index 30d71f0f10a..3e7d8ee9eb5 100644
--- a/forc-plugins/forc-debug/tests/server_integration.rs
+++ b/forc-plugins/forc-debug/tests/server_integration.rs
@@ -315,10 +315,10 @@ fn test_sourcemap_build()... | [
"forc-plugins/forc-debug/tests/server_integration.rs"
] | [
{
"comment": "```suggestion\n (11, 1, \"helper function parameters\"), // Should have 1 instruction\n```",
"path": "forc-plugins/forc-debug/tests/server_integration.rs",
"hunk": "@@ -315,10 +315,10 @@ fn test_sourcemap_build() {\n // Verify essential source locations are mapped correctly\n ... | true | ||
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | The `NUM_FREE_REGISTERS` is removed. The original comment was describing that const as well, which actually should have been a regular and not a doc-comment than. The suggestion is to simply remove the comment.
```suggestion
``` | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/sway-core/src/asm_generation/fuel/compiler_constants.rs b/sway-core/src/asm_generation/fuel/compiler_constants.rs
index a8526958a8c..ba86a21b620 100644
--- a/sway-core/src/asm_generation/fuel/compiler_constants.rs
+++ b/sway-core/src/asm_generation/fuel/compiler_constants.rs
@@ -1,7 +1,6 @@
-/// The total ... | [
"sway-core/src/asm_generation/fuel/compiler_constants.rs"
] | [
{
"comment": "The `NUM_FREE_REGISTERS` is removed. The original comment was describing that const as well, which actually should have been a regular and not a doc-comment than. The suggestion is to simply remove the comment.\n```suggestion\n```",
"path": "sway-core/src/asm_generation/fuel/compiler_constants... | true | ||
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | The comment is quite confusing because it says "register*s*" and "as others", although it just defines the value of the flags register, which is exactly what the const name `FLAGS_REGISTER` says. IMO, we should just remove the comment. The const name is more than self descriptive.
```suggestion
``` | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/sway-core/src/asm_generation/fuel/compiler_constants.rs b/sway-core/src/asm_generation/fuel/compiler_constants.rs
index a8526958a8c..ba86a21b620 100644
--- a/sway-core/src/asm_generation/fuel/compiler_constants.rs
+++ b/sway-core/src/asm_generation/fuel/compiler_constants.rs
@@ -1,7 +1,6 @@
-/// The total ... | [
"sway-core/src/asm_generation/fuel/compiler_constants.rs"
] | [
{
"comment": "The comment is quite confusing because it says \"register*s*\" and \"as others\", although it just defines the value of the flags register, which is exactly what the const name `FLAGS_REGISTER` says. IMO, we should just remove the comment. The const name is more than self descriptive.\n```suggesti... | true | ||
FuelLabs/sway | 7,561 | comment_to_fix | Optimise `pshl` | Suggestion is to remove the actual numbers because they can change in the future. Instead, have the const names in brackets makes it possible to see the value if needed, by just hovering over in IDE.
```suggestion
/// First allocated register starts at [UPPER_ALLOCATABLE_REGISTER] and goes
/// down until [LOWER... | d71243f17aba2ac1a6af8d0659a573cab7517e38 | 91cad8715014c01bf53f49a3ec87e4812840578a | diff --git a/sway-core/src/asm_lang/allocated_ops.rs b/sway-core/src/asm_lang/allocated_ops.rs
index 435fad05fa6..9c61b8f1ca8 100644
--- a/sway-core/src/asm_lang/allocated_ops.rs
+++ b/sway-core/src/asm_lang/allocated_ops.rs
@@ -12,7 +12,9 @@
use super::*;
use crate::{
asm_generation::fuel::{
- compiler_c... | [
"sway-core/src/asm_lang/allocated_ops.rs"
] | [
{
"comment": "Suggestion is to remove the actual numbers because they can change in the future. Instead, have the const names in brackets makes it possible to see the value if needed, by just hovering over in IDE.\n```suggestion\n /// First allocated register starts at [UPPER_ALLOCATABLE_REGISTER] and goes\n... | true | ||
FuelLabs/sway | 7,573 | issue_to_patch | Bump quinn-proto from 0.11.12 to 0.11.14 in /test/src/sdk-harness | Bumps [quinn-proto](https://github.com/quinn-rs/quinn) from 0.11.12 to 0.11.14.
<details>
<summary>Release notes</summary>
<p><em>Sourced from <a href="https://github.com/quinn-rs/quinn/releases">quinn-proto's releases</a>.</em></p>
<blockquote>
<h2>quinn-proto 0.11.14</h2>
<p><a href="https://github.com/jxs"><code>@j... | 645d81122780050a1f3cbf050756c1c7950d2335 | 9e8e9e3eb624e0a4f685c2b2fd3dbfd558b3c6fe | [
"test/src/sdk-harness/Cargo.lock"
] | [] | diff --git a/test/src/sdk-harness/Cargo.lock b/test/src/sdk-harness/Cargo.lock
index d284ba23027..9769590845a 100644
--- a/test/src/sdk-harness/Cargo.lock
+++ b/test/src/sdk-harness/Cargo.lock
@@ -6078,9 +6078,9 @@ dependencies = [
[[package]]
name = "quinn-proto"
-version = "0.11.12"
+version = "0.11.14"
source =... | true | ||
FuelLabs/sway | 7,550 | issue_to_patch | `$err` register propagated from `move` to `eq` although `move` clears it
Consider the following example:
```sway
#[storage(read)]
fn srdd_empty_slot() {
let dest = [42u64; 2];
let is_err = asm(slot: B256_ZERO, res: __addr_of(dest), index: 0, len: dest.len()) {
srdd res slot index len;
err
... | Improve `asm` const propagation | ## Description
This PR optimises `ASM` const propagation. That means that it tries to use as few registers as possible, hoping that their initialisation can be removed later with DCE and others...
This is particularly useful on function calls, and indexing:
1 - On function calls we normally have something like... | 5cd44e7788de590177213e1b4040493b2db8b989 | 2765f4af57abc203a826d5890c77e4593c6095ff | diff --git a/Cargo.lock b/Cargo.lock
index 2c6a09423f9..4c8b001d46e 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -9163,6 +9163,7 @@ dependencies = [
"clap",
"dirs 5.0.1",
"either",
+ "expect-test",
"fuel-abi-types",
"fuel-ethabi",
"fuel-etk-asm",
diff --git a/sway-core/Cargo.toml b/sway-core/Cargo.toml
index... | [
"Cargo.lock",
"forc/tests/cli_integration.rs",
"sway-core/Cargo.toml",
"sway-core/src/asm_generation/fuel/abstract_instruction_set.rs",
"sway-core/src/asm_generation/fuel/optimizations/constant_propagate.rs",
"sway-core/src/asm_generation/fuel/optimizations/mod.rs",
"sway-core/src/asm_lang/mod.rs",
"s... | [
{
"comment": "### EXP optimization incorrectly folds `0^x` to zero\n\n**High Severity**\n\n<!-- DESCRIPTION START -->\nThe rule `if left is 0 assigns 0` for `EXP` assumes `0^x = 0` for all `x`, but `0^0 = 1`. When the left operand is known to be 0 and the right operand is unknown at compile time, the optimizer ... | diff --git a/forc/tests/cli_integration.rs b/forc/tests/cli_integration.rs
index de22c0bf9d6..e383db3c042 100644
--- a/forc/tests/cli_integration.rs
+++ b/forc/tests/cli_integration.rs
@@ -51,10 +51,10 @@ fn test_forc_test_raw_logs() -> Result<(), rexpect::error::Error> {
// Assert that the output is correct
... | true |
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